1/*
2 * QEMU float support
3 *
4 * The code in this source file is derived from release 2a of the SoftFloat
5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
6 * some later contributions) are provided under that license, as detailed below.
7 * It has subsequently been modified by contributors to the QEMU Project,
8 * so some portions are provided under:
9 *  the SoftFloat-2a license
10 *  the BSD license
11 *  GPL-v2-or-later
12 *
13 * Any future contributions to this file after December 1st 2014 will be
14 * taken to be licensed under the Softfloat-2a license unless specifically
15 * indicated otherwise.
16 */
17
18/*
19===============================================================================
20This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
21Arithmetic Package, Release 2a.
22
23Written by John R. Hauser.  This work was made possible in part by the
24International Computer Science Institute, located at Suite 600, 1947 Center
25Street, Berkeley, California 94704.  Funding was partially provided by the
26National Science Foundation under grant MIP-9311980.  The original version
27of this code was written as part of a project to build a fixed-point vector
28processor in collaboration with the University of California at Berkeley,
29overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
30is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
31arithmetic/SoftFloat.html'.
32
33THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
34has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
35TIMES RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO
36PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
37AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
38
39Derivative works are acceptable, even for commercial purposes, so long as
40(1) they include prominent notice that the work is derivative, and (2) they
41include prominent notice akin to these four paragraphs for those parts of
42this code that are retained.
43
44===============================================================================
45*/
46
47/* BSD licensing:
48 * Copyright (c) 2006, Fabrice Bellard
49 * All rights reserved.
50 *
51 * Redistribution and use in source and binary forms, with or without
52 * modification, are permitted provided that the following conditions are met:
53 *
54 * 1. Redistributions of source code must retain the above copyright notice,
55 * this list of conditions and the following disclaimer.
56 *
57 * 2. Redistributions in binary form must reproduce the above copyright notice,
58 * this list of conditions and the following disclaimer in the documentation
59 * and/or other materials provided with the distribution.
60 *
61 * 3. Neither the name of the copyright holder nor the names of its contributors
62 * may be used to endorse or promote products derived from this software without
63 * specific prior written permission.
64 *
65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
75 * THE POSSIBILITY OF SUCH DAMAGE.
76 */
77
78/* Portions of this work are licensed under the terms of the GNU GPL,
79 * version 2 or later. See the COPYING file in the top-level directory.
80 */
81
82/*
83 * Define whether architecture deviates from IEEE in not supporting
84 * signaling NaNs (so all NaNs are treated as quiet).
85 */
86static inline bool no_signaling_nans(float_status *status)
87{
88#if defined(TARGET_XTENSA)
89    return status->no_signaling_nans;
90#else
91    return false;
92#endif
93}
94
95/* Define how the architecture discriminates signaling NaNs.
96 * This done with the most significant bit of the fraction.
97 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
98 * the msb must be zero.  MIPS is (so far) unique in supporting both the
99 * 2008 revision and backward compatibility with their original choice.
100 * Thus for MIPS we must make the choice at runtime.
101 */
102static inline bool snan_bit_is_one(float_status *status)
103{
104#if defined(TARGET_MIPS)
105    return status->snan_bit_is_one;
106#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4)
107    return 1;
108#else
109    return 0;
110#endif
111}
112
113/*----------------------------------------------------------------------------
114| For the deconstructed floating-point with fraction FRAC, return true
115| if the fraction represents a signalling NaN; otherwise false.
116*----------------------------------------------------------------------------*/
117
118static bool parts_is_snan_frac(uint64_t frac, float_status *status)
119{
120    if (no_signaling_nans(status)) {
121        return false;
122    } else {
123        bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
124        return msb == snan_bit_is_one(status);
125    }
126}
127
128/*----------------------------------------------------------------------------
129| The pattern for a default generated deconstructed floating-point NaN.
130*----------------------------------------------------------------------------*/
131
132static FloatParts parts_default_nan(float_status *status)
133{
134    bool sign = 0;
135    uint64_t frac;
136
137#if defined(TARGET_SPARC) || defined(TARGET_M68K)
138    /* !snan_bit_is_one, set all bits */
139    frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
140#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
141    || defined(TARGET_MICROBLAZE)
142    /* !snan_bit_is_one, set sign and msb */
143    frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
144    sign = 1;
145#elif defined(TARGET_HPPA)
146    /* snan_bit_is_one, set msb-1.  */
147    frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
148#else
149    /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
150     * S390, SH4, TriCore, and Xtensa.  I cannot find documentation
151     * for Unicore32; the choice from the original commit is unchanged.
152     * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile,
153     * do not have floating-point.
154     */
155    if (snan_bit_is_one(status)) {
156        /* set all bits other than msb */
157        frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
158    } else {
159        /* set msb */
160        frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
161    }
162#endif
163
164    return (FloatParts) {
165        .cls = float_class_qnan,
166        .sign = sign,
167        .exp = INT_MAX,
168        .frac = frac
169    };
170}
171
172/*----------------------------------------------------------------------------
173| Returns a quiet NaN from a signalling NaN for the deconstructed
174| floating-point parts.
175*----------------------------------------------------------------------------*/
176
177static FloatParts parts_silence_nan(FloatParts a, float_status *status)
178{
179    g_assert(!no_signaling_nans(status));
180#if defined(TARGET_HPPA)
181    a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
182    a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
183#else
184    if (snan_bit_is_one(status)) {
185        return parts_default_nan(status);
186    } else {
187        a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
188    }
189#endif
190    a.cls = float_class_qnan;
191    return a;
192}
193
194/*----------------------------------------------------------------------------
195| The pattern for a default generated extended double-precision NaN.
196*----------------------------------------------------------------------------*/
197floatx80 floatx80_default_nan(float_status *status)
198{
199    floatx80 r;
200
201    /* None of the targets that have snan_bit_is_one use floatx80.  */
202    assert(!snan_bit_is_one(status));
203#if defined(TARGET_M68K)
204    r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
205    r.high = 0x7FFF;
206#else
207    /* X86 */
208    r.low = UINT64_C(0xC000000000000000);
209    r.high = 0xFFFF;
210#endif
211    return r;
212}
213
214/*----------------------------------------------------------------------------
215| The pattern for a default generated extended double-precision inf.
216*----------------------------------------------------------------------------*/
217
218#define floatx80_infinity_high 0x7FFF
219#if defined(TARGET_M68K)
220#define floatx80_infinity_low  UINT64_C(0x0000000000000000)
221#else
222#define floatx80_infinity_low  UINT64_C(0x8000000000000000)
223#endif
224
225const floatx80 floatx80_infinity
226    = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
227
228/*----------------------------------------------------------------------------
229| Raises the exceptions specified by `flags'.  Floating-point traps can be
230| defined here if desired.  It is currently not possible for such a trap
231| to substitute a result value.  If traps are not implemented, this routine
232| should be simply `float_exception_flags |= flags;'.
233*----------------------------------------------------------------------------*/
234
235void float_raise(uint8_t flags, float_status *status)
236{
237    status->float_exception_flags |= flags;
238}
239
240/*----------------------------------------------------------------------------
241| Internal canonical NaN format.
242*----------------------------------------------------------------------------*/
243typedef struct {
244    bool sign;
245    uint64_t high, low;
246} commonNaNT;
247
248/*----------------------------------------------------------------------------
249| Returns 1 if the half-precision floating-point value `a' is a quiet
250| NaN; otherwise returns 0.
251*----------------------------------------------------------------------------*/
252
253bool float16_is_quiet_nan(float16 a_, float_status *status)
254{
255    if (no_signaling_nans(status)) {
256        return float16_is_any_nan(a_);
257    } else {
258        uint16_t a = float16_val(a_);
259        if (snan_bit_is_one(status)) {
260            return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
261        } else {
262
263            return ((a >> 9) & 0x3F) == 0x3F;
264        }
265    }
266}
267
268/*----------------------------------------------------------------------------
269| Returns 1 if the bfloat16 value `a' is a quiet
270| NaN; otherwise returns 0.
271*----------------------------------------------------------------------------*/
272
273bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status)
274{
275    if (no_signaling_nans(status)) {
276        return bfloat16_is_any_nan(a_);
277    } else {
278        uint16_t a = a_;
279        if (snan_bit_is_one(status)) {
280            return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
281        } else {
282            return ((a >> 6) & 0x1FF) == 0x1FF;
283        }
284    }
285}
286
287/*----------------------------------------------------------------------------
288| Returns 1 if the half-precision floating-point value `a' is a signaling
289| NaN; otherwise returns 0.
290*----------------------------------------------------------------------------*/
291
292bool float16_is_signaling_nan(float16 a_, float_status *status)
293{
294    if (no_signaling_nans(status)) {
295        return 0;
296    } else {
297        uint16_t a = float16_val(a_);
298        if (snan_bit_is_one(status)) {
299            return ((a >> 9) & 0x3F) == 0x3F;
300        } else {
301            return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
302        }
303    }
304}
305
306/*----------------------------------------------------------------------------
307| Returns 1 if the bfloat16 value `a' is a signaling
308| NaN; otherwise returns 0.
309*----------------------------------------------------------------------------*/
310
311bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)
312{
313    if (no_signaling_nans(status)) {
314        return 0;
315    } else {
316        uint16_t a = a_;
317        if (snan_bit_is_one(status)) {
318            return ((a >> 6) & 0x1FF) == 0x1FF;
319        } else {
320            return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
321        }
322    }
323}
324
325/*----------------------------------------------------------------------------
326| Returns 1 if the single-precision floating-point value `a' is a quiet
327| NaN; otherwise returns 0.
328*----------------------------------------------------------------------------*/
329
330bool float32_is_quiet_nan(float32 a_, float_status *status)
331{
332    if (no_signaling_nans(status)) {
333        return float32_is_any_nan(a_);
334    } else {
335        uint32_t a = float32_val(a_);
336        if (snan_bit_is_one(status)) {
337            return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
338        } else {
339            return ((uint32_t)(a << 1) >= 0xFF800000);
340        }
341    }
342}
343
344/*----------------------------------------------------------------------------
345| Returns 1 if the single-precision floating-point value `a' is a signaling
346| NaN; otherwise returns 0.
347*----------------------------------------------------------------------------*/
348
349bool float32_is_signaling_nan(float32 a_, float_status *status)
350{
351    if (no_signaling_nans(status)) {
352        return 0;
353    } else {
354        uint32_t a = float32_val(a_);
355        if (snan_bit_is_one(status)) {
356            return ((uint32_t)(a << 1) >= 0xFF800000);
357        } else {
358            return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
359        }
360    }
361}
362
363/*----------------------------------------------------------------------------
364| Returns the result of converting the single-precision floating-point NaN
365| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
366| exception is raised.
367*----------------------------------------------------------------------------*/
368
369static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
370{
371    commonNaNT z;
372
373    if (float32_is_signaling_nan(a, status)) {
374        float_raise(float_flag_invalid, status);
375    }
376    z.sign = float32_val(a) >> 31;
377    z.low = 0;
378    z.high = ((uint64_t)float32_val(a)) << 41;
379    return z;
380}
381
382/*----------------------------------------------------------------------------
383| Returns the result of converting the canonical NaN `a' to the single-
384| precision floating-point format.
385*----------------------------------------------------------------------------*/
386
387static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
388{
389    uint32_t mantissa = a.high >> 41;
390
391    if (status->default_nan_mode) {
392        return float32_default_nan(status);
393    }
394
395    if (mantissa) {
396        return make_float32(
397            (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41));
398    } else {
399        return float32_default_nan(status);
400    }
401}
402
403/*----------------------------------------------------------------------------
404| Select which NaN to propagate for a two-input operation.
405| IEEE754 doesn't specify all the details of this, so the
406| algorithm is target-specific.
407| The routine is passed various bits of information about the
408| two NaNs and should return 0 to select NaN a and 1 for NaN b.
409| Note that signalling NaNs are always squashed to quiet NaNs
410| by the caller, by calling floatXX_silence_nan() before
411| returning them.
412|
413| aIsLargerSignificand is only valid if both a and b are NaNs
414| of some kind, and is true if a has the larger significand,
415| or if both a and b have the same significand but a is
416| positive but b is negative. It is only needed for the x87
417| tie-break rule.
418*----------------------------------------------------------------------------*/
419
420static int pickNaN(FloatClass a_cls, FloatClass b_cls,
421                   bool aIsLargerSignificand, float_status *status)
422{
423#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA)
424    /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
425     * the first of:
426     *  1. A if it is signaling
427     *  2. B if it is signaling
428     *  3. A (quiet)
429     *  4. B (quiet)
430     * A signaling NaN is always quietened before returning it.
431     */
432    /* According to MIPS specifications, if one of the two operands is
433     * a sNaN, a new qNaN has to be generated. This is done in
434     * floatXX_silence_nan(). For qNaN inputs the specifications
435     * says: "When possible, this QNaN result is one of the operand QNaN
436     * values." In practice it seems that most implementations choose
437     * the first operand if both operands are qNaN. In short this gives
438     * the following rules:
439     *  1. A if it is signaling
440     *  2. B if it is signaling
441     *  3. A (quiet)
442     *  4. B (quiet)
443     * A signaling NaN is always silenced before returning it.
444     */
445    if (is_snan(a_cls)) {
446        return 0;
447    } else if (is_snan(b_cls)) {
448        return 1;
449    } else if (is_qnan(a_cls)) {
450        return 0;
451    } else {
452        return 1;
453    }
454#elif defined(TARGET_PPC) || defined(TARGET_M68K)
455    /* PowerPC propagation rules:
456     *  1. A if it sNaN or qNaN
457     *  2. B if it sNaN or qNaN
458     * A signaling NaN is always silenced before returning it.
459     */
460    /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
461     * 3.4 FLOATING-POINT INSTRUCTION DETAILS
462     * If either operand, but not both operands, of an operation is a
463     * nonsignaling NaN, then that NaN is returned as the result. If both
464     * operands are nonsignaling NaNs, then the destination operand
465     * nonsignaling NaN is returned as the result.
466     * If either operand to an operation is a signaling NaN (SNaN), then the
467     * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
468     * is set in the FPCR ENABLE byte, then the exception is taken and the
469     * destination is not modified. If the SNaN exception enable bit is not
470     * set, setting the SNaN bit in the operand to a one converts the SNaN to
471     * a nonsignaling NaN. The operation then continues as described in the
472     * preceding paragraph for nonsignaling NaNs.
473     */
474    if (is_nan(a_cls)) {
475        return 0;
476    } else {
477        return 1;
478    }
479#elif defined(TARGET_XTENSA)
480    /*
481     * Xtensa has two NaN propagation modes.
482     * Which one is active is controlled by float_status::use_first_nan.
483     */
484    if (status->use_first_nan) {
485        if (is_nan(a_cls)) {
486            return 0;
487        } else {
488            return 1;
489        }
490    } else {
491        if (is_nan(b_cls)) {
492            return 1;
493        } else {
494            return 0;
495        }
496    }
497#else
498    /* This implements x87 NaN propagation rules:
499     * SNaN + QNaN => return the QNaN
500     * two SNaNs => return the one with the larger significand, silenced
501     * two QNaNs => return the one with the larger significand
502     * SNaN and a non-NaN => return the SNaN, silenced
503     * QNaN and a non-NaN => return the QNaN
504     *
505     * If we get down to comparing significands and they are the same,
506     * return the NaN with the positive sign bit (if any).
507     */
508    if (is_snan(a_cls)) {
509        if (is_snan(b_cls)) {
510            return aIsLargerSignificand ? 0 : 1;
511        }
512        return is_qnan(b_cls) ? 1 : 0;
513    } else if (is_qnan(a_cls)) {
514        if (is_snan(b_cls) || !is_qnan(b_cls)) {
515            return 0;
516        } else {
517            return aIsLargerSignificand ? 0 : 1;
518        }
519    } else {
520        return 1;
521    }
522#endif
523}
524
525/*----------------------------------------------------------------------------
526| Select which NaN to propagate for a three-input operation.
527| For the moment we assume that no CPU needs the 'larger significand'
528| information.
529| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
530*----------------------------------------------------------------------------*/
531static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
532                         bool infzero, float_status *status)
533{
534#if defined(TARGET_ARM)
535    /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
536     * the default NaN
537     */
538    if (infzero && is_qnan(c_cls)) {
539        float_raise(float_flag_invalid, status);
540        return 3;
541    }
542
543    /* This looks different from the ARM ARM pseudocode, because the ARM ARM
544     * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
545     */
546    if (is_snan(c_cls)) {
547        return 2;
548    } else if (is_snan(a_cls)) {
549        return 0;
550    } else if (is_snan(b_cls)) {
551        return 1;
552    } else if (is_qnan(c_cls)) {
553        return 2;
554    } else if (is_qnan(a_cls)) {
555        return 0;
556    } else {
557        return 1;
558    }
559#elif defined(TARGET_MIPS)
560    if (snan_bit_is_one(status)) {
561        /*
562         * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
563         * case sets InvalidOp and returns the default NaN
564         */
565        if (infzero) {
566            float_raise(float_flag_invalid, status);
567            return 3;
568        }
569        /* Prefer sNaN over qNaN, in the a, b, c order. */
570        if (is_snan(a_cls)) {
571            return 0;
572        } else if (is_snan(b_cls)) {
573            return 1;
574        } else if (is_snan(c_cls)) {
575            return 2;
576        } else if (is_qnan(a_cls)) {
577            return 0;
578        } else if (is_qnan(b_cls)) {
579            return 1;
580        } else {
581            return 2;
582        }
583    } else {
584        /*
585         * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
586         * case sets InvalidOp and returns the input value 'c'
587         */
588        if (infzero) {
589            float_raise(float_flag_invalid, status);
590            return 2;
591        }
592        /* Prefer sNaN over qNaN, in the c, a, b order. */
593        if (is_snan(c_cls)) {
594            return 2;
595        } else if (is_snan(a_cls)) {
596            return 0;
597        } else if (is_snan(b_cls)) {
598            return 1;
599        } else if (is_qnan(c_cls)) {
600            return 2;
601        } else if (is_qnan(a_cls)) {
602            return 0;
603        } else {
604            return 1;
605        }
606    }
607#elif defined(TARGET_PPC)
608    /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
609     * to return an input NaN if we have one (ie c) rather than generating
610     * a default NaN
611     */
612    if (infzero) {
613        float_raise(float_flag_invalid, status);
614        return 2;
615    }
616
617    /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
618     * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
619     */
620    if (is_nan(a_cls)) {
621        return 0;
622    } else if (is_nan(c_cls)) {
623        return 2;
624    } else {
625        return 1;
626    }
627#elif defined(TARGET_XTENSA)
628    /*
629     * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
630     * an input NaN if we have one (ie c).
631     */
632    if (infzero) {
633        float_raise(float_flag_invalid, status);
634        return 2;
635    }
636    if (status->use_first_nan) {
637        if (is_nan(a_cls)) {
638            return 0;
639        } else if (is_nan(b_cls)) {
640            return 1;
641        } else {
642            return 2;
643        }
644    } else {
645        if (is_nan(c_cls)) {
646            return 2;
647        } else if (is_nan(b_cls)) {
648            return 1;
649        } else {
650            return 0;
651        }
652    }
653#else
654    /* A default implementation: prefer a to b to c.
655     * This is unlikely to actually match any real implementation.
656     */
657    if (is_nan(a_cls)) {
658        return 0;
659    } else if (is_nan(b_cls)) {
660        return 1;
661    } else {
662        return 2;
663    }
664#endif
665}
666
667/*----------------------------------------------------------------------------
668| Takes two single-precision floating-point values `a' and `b', one of which
669| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
670| signaling NaN, the invalid exception is raised.
671*----------------------------------------------------------------------------*/
672
673static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
674{
675    bool aIsLargerSignificand;
676    uint32_t av, bv;
677    FloatClass a_cls, b_cls;
678
679    /* This is not complete, but is good enough for pickNaN.  */
680    a_cls = (!float32_is_any_nan(a)
681             ? float_class_normal
682             : float32_is_signaling_nan(a, status)
683             ? float_class_snan
684             : float_class_qnan);
685    b_cls = (!float32_is_any_nan(b)
686             ? float_class_normal
687             : float32_is_signaling_nan(b, status)
688             ? float_class_snan
689             : float_class_qnan);
690
691    av = float32_val(a);
692    bv = float32_val(b);
693
694    if (is_snan(a_cls) || is_snan(b_cls)) {
695        float_raise(float_flag_invalid, status);
696    }
697
698    if (status->default_nan_mode) {
699        return float32_default_nan(status);
700    }
701
702    if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
703        aIsLargerSignificand = 0;
704    } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
705        aIsLargerSignificand = 1;
706    } else {
707        aIsLargerSignificand = (av < bv) ? 1 : 0;
708    }
709
710    if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
711        if (is_snan(b_cls)) {
712            return float32_silence_nan(b, status);
713        }
714        return b;
715    } else {
716        if (is_snan(a_cls)) {
717            return float32_silence_nan(a, status);
718        }
719        return a;
720    }
721}
722
723/*----------------------------------------------------------------------------
724| Returns 1 if the double-precision floating-point value `a' is a quiet
725| NaN; otherwise returns 0.
726*----------------------------------------------------------------------------*/
727
728bool float64_is_quiet_nan(float64 a_, float_status *status)
729{
730    if (no_signaling_nans(status)) {
731        return float64_is_any_nan(a_);
732    } else {
733        uint64_t a = float64_val(a_);
734        if (snan_bit_is_one(status)) {
735            return (((a >> 51) & 0xFFF) == 0xFFE)
736                && (a & 0x0007FFFFFFFFFFFFULL);
737        } else {
738            return ((a << 1) >= 0xFFF0000000000000ULL);
739        }
740    }
741}
742
743/*----------------------------------------------------------------------------
744| Returns 1 if the double-precision floating-point value `a' is a signaling
745| NaN; otherwise returns 0.
746*----------------------------------------------------------------------------*/
747
748bool float64_is_signaling_nan(float64 a_, float_status *status)
749{
750    if (no_signaling_nans(status)) {
751        return 0;
752    } else {
753        uint64_t a = float64_val(a_);
754        if (snan_bit_is_one(status)) {
755            return ((a << 1) >= 0xFFF0000000000000ULL);
756        } else {
757            return (((a >> 51) & 0xFFF) == 0xFFE)
758                && (a & UINT64_C(0x0007FFFFFFFFFFFF));
759        }
760    }
761}
762
763/*----------------------------------------------------------------------------
764| Returns the result of converting the double-precision floating-point NaN
765| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
766| exception is raised.
767*----------------------------------------------------------------------------*/
768
769static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
770{
771    commonNaNT z;
772
773    if (float64_is_signaling_nan(a, status)) {
774        float_raise(float_flag_invalid, status);
775    }
776    z.sign = float64_val(a) >> 63;
777    z.low = 0;
778    z.high = float64_val(a) << 12;
779    return z;
780}
781
782/*----------------------------------------------------------------------------
783| Returns the result of converting the canonical NaN `a' to the double-
784| precision floating-point format.
785*----------------------------------------------------------------------------*/
786
787static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
788{
789    uint64_t mantissa = a.high >> 12;
790
791    if (status->default_nan_mode) {
792        return float64_default_nan(status);
793    }
794
795    if (mantissa) {
796        return make_float64(
797              (((uint64_t) a.sign) << 63)
798            | UINT64_C(0x7FF0000000000000)
799            | (a.high >> 12));
800    } else {
801        return float64_default_nan(status);
802    }
803}
804
805/*----------------------------------------------------------------------------
806| Takes two double-precision floating-point values `a' and `b', one of which
807| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
808| signaling NaN, the invalid exception is raised.
809*----------------------------------------------------------------------------*/
810
811static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
812{
813    bool aIsLargerSignificand;
814    uint64_t av, bv;
815    FloatClass a_cls, b_cls;
816
817    /* This is not complete, but is good enough for pickNaN.  */
818    a_cls = (!float64_is_any_nan(a)
819             ? float_class_normal
820             : float64_is_signaling_nan(a, status)
821             ? float_class_snan
822             : float_class_qnan);
823    b_cls = (!float64_is_any_nan(b)
824             ? float_class_normal
825             : float64_is_signaling_nan(b, status)
826             ? float_class_snan
827             : float_class_qnan);
828
829    av = float64_val(a);
830    bv = float64_val(b);
831
832    if (is_snan(a_cls) || is_snan(b_cls)) {
833        float_raise(float_flag_invalid, status);
834    }
835
836    if (status->default_nan_mode) {
837        return float64_default_nan(status);
838    }
839
840    if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
841        aIsLargerSignificand = 0;
842    } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) {
843        aIsLargerSignificand = 1;
844    } else {
845        aIsLargerSignificand = (av < bv) ? 1 : 0;
846    }
847
848    if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
849        if (is_snan(b_cls)) {
850            return float64_silence_nan(b, status);
851        }
852        return b;
853    } else {
854        if (is_snan(a_cls)) {
855            return float64_silence_nan(a, status);
856        }
857        return a;
858    }
859}
860
861/*----------------------------------------------------------------------------
862| Returns 1 if the extended double-precision floating-point value `a' is a
863| quiet NaN; otherwise returns 0. This slightly differs from the same
864| function for other types as floatx80 has an explicit bit.
865*----------------------------------------------------------------------------*/
866
867int floatx80_is_quiet_nan(floatx80 a, float_status *status)
868{
869    if (no_signaling_nans(status)) {
870        return floatx80_is_any_nan(a);
871    } else {
872        if (snan_bit_is_one(status)) {
873            uint64_t aLow;
874
875            aLow = a.low & ~0x4000000000000000ULL;
876            return ((a.high & 0x7FFF) == 0x7FFF)
877                && (aLow << 1)
878                && (a.low == aLow);
879        } else {
880            return ((a.high & 0x7FFF) == 0x7FFF)
881                && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
882        }
883    }
884}
885
886/*----------------------------------------------------------------------------
887| Returns 1 if the extended double-precision floating-point value `a' is a
888| signaling NaN; otherwise returns 0. This slightly differs from the same
889| function for other types as floatx80 has an explicit bit.
890*----------------------------------------------------------------------------*/
891
892int floatx80_is_signaling_nan(floatx80 a, float_status *status)
893{
894    if (no_signaling_nans(status)) {
895        return 0;
896    } else {
897        if (snan_bit_is_one(status)) {
898            return ((a.high & 0x7FFF) == 0x7FFF)
899                && ((a.low << 1) >= 0x8000000000000000ULL);
900        } else {
901            uint64_t aLow;
902
903            aLow = a.low & ~UINT64_C(0x4000000000000000);
904            return ((a.high & 0x7FFF) == 0x7FFF)
905                && (uint64_t)(aLow << 1)
906                && (a.low == aLow);
907        }
908    }
909}
910
911/*----------------------------------------------------------------------------
912| Returns a quiet NaN from a signalling NaN for the extended double-precision
913| floating point value `a'.
914*----------------------------------------------------------------------------*/
915
916floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
917{
918    /* None of the targets that have snan_bit_is_one use floatx80.  */
919    assert(!snan_bit_is_one(status));
920    a.low |= UINT64_C(0xC000000000000000);
921    return a;
922}
923
924/*----------------------------------------------------------------------------
925| Returns the result of converting the extended double-precision floating-
926| point NaN `a' to the canonical NaN format.  If `a' is a signaling NaN, the
927| invalid exception is raised.
928*----------------------------------------------------------------------------*/
929
930static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
931{
932    floatx80 dflt;
933    commonNaNT z;
934
935    if (floatx80_is_signaling_nan(a, status)) {
936        float_raise(float_flag_invalid, status);
937    }
938    if (a.low >> 63) {
939        z.sign = a.high >> 15;
940        z.low = 0;
941        z.high = a.low << 1;
942    } else {
943        dflt = floatx80_default_nan(status);
944        z.sign = dflt.high >> 15;
945        z.low = 0;
946        z.high = dflt.low << 1;
947    }
948    return z;
949}
950
951/*----------------------------------------------------------------------------
952| Returns the result of converting the canonical NaN `a' to the extended
953| double-precision floating-point format.
954*----------------------------------------------------------------------------*/
955
956static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
957{
958    floatx80 z;
959
960    if (status->default_nan_mode) {
961        return floatx80_default_nan(status);
962    }
963
964    if (a.high >> 1) {
965        z.low = UINT64_C(0x8000000000000000) | a.high >> 1;
966        z.high = (((uint16_t)a.sign) << 15) | 0x7FFF;
967    } else {
968        z = floatx80_default_nan(status);
969    }
970    return z;
971}
972
973/*----------------------------------------------------------------------------
974| Takes two extended double-precision floating-point values `a' and `b', one
975| of which is a NaN, and returns the appropriate NaN result.  If either `a' or
976| `b' is a signaling NaN, the invalid exception is raised.
977*----------------------------------------------------------------------------*/
978
979floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
980{
981    bool aIsLargerSignificand;
982    FloatClass a_cls, b_cls;
983
984    /* This is not complete, but is good enough for pickNaN.  */
985    a_cls = (!floatx80_is_any_nan(a)
986             ? float_class_normal
987             : floatx80_is_signaling_nan(a, status)
988             ? float_class_snan
989             : float_class_qnan);
990    b_cls = (!floatx80_is_any_nan(b)
991             ? float_class_normal
992             : floatx80_is_signaling_nan(b, status)
993             ? float_class_snan
994             : float_class_qnan);
995
996    if (is_snan(a_cls) || is_snan(b_cls)) {
997        float_raise(float_flag_invalid, status);
998    }
999
1000    if (status->default_nan_mode) {
1001        return floatx80_default_nan(status);
1002    }
1003
1004    if (a.low < b.low) {
1005        aIsLargerSignificand = 0;
1006    } else if (b.low < a.low) {
1007        aIsLargerSignificand = 1;
1008    } else {
1009        aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1010    }
1011
1012    if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
1013        if (is_snan(b_cls)) {
1014            return floatx80_silence_nan(b, status);
1015        }
1016        return b;
1017    } else {
1018        if (is_snan(a_cls)) {
1019            return floatx80_silence_nan(a, status);
1020        }
1021        return a;
1022    }
1023}
1024
1025/*----------------------------------------------------------------------------
1026| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
1027| NaN; otherwise returns 0.
1028*----------------------------------------------------------------------------*/
1029
1030bool float128_is_quiet_nan(float128 a, float_status *status)
1031{
1032    if (no_signaling_nans(status)) {
1033        return float128_is_any_nan(a);
1034    } else {
1035        if (snan_bit_is_one(status)) {
1036            return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1037                && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
1038        } else {
1039            return ((a.high << 1) >= 0xFFFF000000000000ULL)
1040                && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1041        }
1042    }
1043}
1044
1045/*----------------------------------------------------------------------------
1046| Returns 1 if the quadruple-precision floating-point value `a' is a
1047| signaling NaN; otherwise returns 0.
1048*----------------------------------------------------------------------------*/
1049
1050bool float128_is_signaling_nan(float128 a, float_status *status)
1051{
1052    if (no_signaling_nans(status)) {
1053        return 0;
1054    } else {
1055        if (snan_bit_is_one(status)) {
1056            return ((a.high << 1) >= 0xFFFF000000000000ULL)
1057                && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1058        } else {
1059            return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1060                && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
1061        }
1062    }
1063}
1064
1065/*----------------------------------------------------------------------------
1066| Returns a quiet NaN from a signalling NaN for the quadruple-precision
1067| floating point value `a'.
1068*----------------------------------------------------------------------------*/
1069
1070float128 float128_silence_nan(float128 a, float_status *status)
1071{
1072    if (no_signaling_nans(status)) {
1073        g_assert_not_reached();
1074    } else {
1075        if (snan_bit_is_one(status)) {
1076            return float128_default_nan(status);
1077        } else {
1078            a.high |= UINT64_C(0x0000800000000000);
1079            return a;
1080        }
1081    }
1082}
1083
1084/*----------------------------------------------------------------------------
1085| Returns the result of converting the quadruple-precision floating-point NaN
1086| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
1087| exception is raised.
1088*----------------------------------------------------------------------------*/
1089
1090static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
1091{
1092    commonNaNT z;
1093
1094    if (float128_is_signaling_nan(a, status)) {
1095        float_raise(float_flag_invalid, status);
1096    }
1097    z.sign = a.high >> 63;
1098    shortShift128Left(a.high, a.low, 16, &z.high, &z.low);
1099    return z;
1100}
1101
1102/*----------------------------------------------------------------------------
1103| Returns the result of converting the canonical NaN `a' to the quadruple-
1104| precision floating-point format.
1105*----------------------------------------------------------------------------*/
1106
1107static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
1108{
1109    float128 z;
1110
1111    if (status->default_nan_mode) {
1112        return float128_default_nan(status);
1113    }
1114
1115    shift128Right(a.high, a.low, 16, &z.high, &z.low);
1116    z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000);
1117    return z;
1118}
1119
1120/*----------------------------------------------------------------------------
1121| Takes two quadruple-precision floating-point values `a' and `b', one of
1122| which is a NaN, and returns the appropriate NaN result.  If either `a' or
1123| `b' is a signaling NaN, the invalid exception is raised.
1124*----------------------------------------------------------------------------*/
1125
1126static float128 propagateFloat128NaN(float128 a, float128 b,
1127                                     float_status *status)
1128{
1129    bool aIsLargerSignificand;
1130    FloatClass a_cls, b_cls;
1131
1132    /* This is not complete, but is good enough for pickNaN.  */
1133    a_cls = (!float128_is_any_nan(a)
1134             ? float_class_normal
1135             : float128_is_signaling_nan(a, status)
1136             ? float_class_snan
1137             : float_class_qnan);
1138    b_cls = (!float128_is_any_nan(b)
1139             ? float_class_normal
1140             : float128_is_signaling_nan(b, status)
1141             ? float_class_snan
1142             : float_class_qnan);
1143
1144    if (is_snan(a_cls) || is_snan(b_cls)) {
1145        float_raise(float_flag_invalid, status);
1146    }
1147
1148    if (status->default_nan_mode) {
1149        return float128_default_nan(status);
1150    }
1151
1152    if (lt128(a.high << 1, a.low, b.high << 1, b.low)) {
1153        aIsLargerSignificand = 0;
1154    } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) {
1155        aIsLargerSignificand = 1;
1156    } else {
1157        aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1158    }
1159
1160    if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
1161        if (is_snan(b_cls)) {
1162            return float128_silence_nan(b, status);
1163        }
1164        return b;
1165    } else {
1166        if (is_snan(a_cls)) {
1167            return float128_silence_nan(a, status);
1168        }
1169        return a;
1170    }
1171}
1172