1/* 2 * QEMU float support 3 * 4 * The code in this source file is derived from release 2a of the SoftFloat 5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and 6 * some later contributions) are provided under that license, as detailed below. 7 * It has subsequently been modified by contributors to the QEMU Project, 8 * so some portions are provided under: 9 * the SoftFloat-2a license 10 * the BSD license 11 * GPL-v2-or-later 12 * 13 * Any future contributions to this file after December 1st 2014 will be 14 * taken to be licensed under the Softfloat-2a license unless specifically 15 * indicated otherwise. 16 */ 17 18/* 19=============================================================================== 20This C source fragment is part of the SoftFloat IEC/IEEE Floating-point 21Arithmetic Package, Release 2a. 22 23Written by John R. Hauser. This work was made possible in part by the 24International Computer Science Institute, located at Suite 600, 1947 Center 25Street, Berkeley, California 94704. Funding was partially provided by the 26National Science Foundation under grant MIP-9311980. The original version 27of this code was written as part of a project to build a fixed-point vector 28processor in collaboration with the University of California at Berkeley, 29overseen by Profs. Nelson Morgan and John Wawrzynek. More information 30is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ 31arithmetic/SoftFloat.html'. 32 33THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 34has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 35TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 36PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 37AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 38 39Derivative works are acceptable, even for commercial purposes, so long as 40(1) they include prominent notice that the work is derivative, and (2) they 41include prominent notice akin to these four paragraphs for those parts of 42this code that are retained. 43 44=============================================================================== 45*/ 46 47/* BSD licensing: 48 * Copyright (c) 2006, Fabrice Bellard 49 * All rights reserved. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions are met: 53 * 54 * 1. Redistributions of source code must retain the above copyright notice, 55 * this list of conditions and the following disclaimer. 56 * 57 * 2. Redistributions in binary form must reproduce the above copyright notice, 58 * this list of conditions and the following disclaimer in the documentation 59 * and/or other materials provided with the distribution. 60 * 61 * 3. Neither the name of the copyright holder nor the names of its contributors 62 * may be used to endorse or promote products derived from this software without 63 * specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 75 * THE POSSIBILITY OF SUCH DAMAGE. 76 */ 77 78/* Portions of this work are licensed under the terms of the GNU GPL, 79 * version 2 or later. See the COPYING file in the top-level directory. 80 */ 81 82/* 83 * Define whether architecture deviates from IEEE in not supporting 84 * signaling NaNs (so all NaNs are treated as quiet). 85 */ 86static inline bool no_signaling_nans(float_status *status) 87{ 88#if defined(TARGET_XTENSA) 89 return status->no_signaling_nans; 90#else 91 return false; 92#endif 93} 94 95/* Define how the architecture discriminates signaling NaNs. 96 * This done with the most significant bit of the fraction. 97 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 98 * the msb must be zero. MIPS is (so far) unique in supporting both the 99 * 2008 revision and backward compatibility with their original choice. 100 * Thus for MIPS we must make the choice at runtime. 101 */ 102static inline bool snan_bit_is_one(float_status *status) 103{ 104#if defined(TARGET_MIPS) 105 return status->snan_bit_is_one; 106#elif defined(TARGET_HPPA) || defined(TARGET_SH4) 107 return 1; 108#else 109 return 0; 110#endif 111} 112 113/*---------------------------------------------------------------------------- 114| For the deconstructed floating-point with fraction FRAC, return true 115| if the fraction represents a signalling NaN; otherwise false. 116*----------------------------------------------------------------------------*/ 117 118static bool parts_is_snan_frac(uint64_t frac, float_status *status) 119{ 120 if (no_signaling_nans(status)) { 121 return false; 122 } else { 123 bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); 124 return msb == snan_bit_is_one(status); 125 } 126} 127 128/*---------------------------------------------------------------------------- 129| The pattern for a default generated deconstructed floating-point NaN. 130*----------------------------------------------------------------------------*/ 131 132static void parts64_default_nan(FloatParts64 *p, float_status *status) 133{ 134 bool sign = 0; 135 uint64_t frac; 136 137#if defined(TARGET_SPARC) || defined(TARGET_M68K) 138 /* !snan_bit_is_one, set all bits */ 139 frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; 140#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ 141 || defined(TARGET_MICROBLAZE) 142 /* !snan_bit_is_one, set sign and msb */ 143 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); 144 sign = 1; 145#elif defined(TARGET_HPPA) 146 /* snan_bit_is_one, set msb-1. */ 147 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); 148#elif defined(TARGET_HEXAGON) 149 sign = 1; 150 frac = ~0ULL; 151#else 152 /* 153 * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, 154 * S390, SH4, TriCore, and Xtensa. Our other supported targets, 155 * CRIS, Nios2, and Tile, do not have floating-point. 156 */ 157 if (snan_bit_is_one(status)) { 158 /* set all bits other than msb */ 159 frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; 160 } else { 161 /* set msb */ 162 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); 163 } 164#endif 165 166 *p = (FloatParts64) { 167 .cls = float_class_qnan, 168 .sign = sign, 169 .exp = INT_MAX, 170 .frac = frac 171 }; 172} 173 174static void parts128_default_nan(FloatParts128 *p, float_status *status) 175{ 176 /* 177 * Extrapolate from the choices made by parts64_default_nan to fill 178 * in the quad-floating format. If the low bit is set, assume we 179 * want to set all non-snan bits. 180 */ 181 FloatParts64 p64; 182 parts64_default_nan(&p64, status); 183 184 *p = (FloatParts128) { 185 .cls = float_class_qnan, 186 .sign = p64.sign, 187 .exp = INT_MAX, 188 .frac_hi = p64.frac, 189 .frac_lo = -(p64.frac & 1) 190 }; 191} 192 193/*---------------------------------------------------------------------------- 194| Returns a quiet NaN from a signalling NaN for the deconstructed 195| floating-point parts. 196*----------------------------------------------------------------------------*/ 197 198static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status) 199{ 200 g_assert(!no_signaling_nans(status)); 201 g_assert(!status->default_nan_mode); 202 203 /* The only snan_bit_is_one target without default_nan_mode is HPPA. */ 204 if (snan_bit_is_one(status)) { 205 frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); 206 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); 207 } else { 208 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); 209 } 210 return frac; 211} 212 213static void parts64_silence_nan(FloatParts64 *p, float_status *status) 214{ 215 p->frac = parts_silence_nan_frac(p->frac, status); 216 p->cls = float_class_qnan; 217} 218 219static void parts128_silence_nan(FloatParts128 *p, float_status *status) 220{ 221 p->frac_hi = parts_silence_nan_frac(p->frac_hi, status); 222 p->cls = float_class_qnan; 223} 224 225/*---------------------------------------------------------------------------- 226| The pattern for a default generated extended double-precision NaN. 227*----------------------------------------------------------------------------*/ 228floatx80 floatx80_default_nan(float_status *status) 229{ 230 floatx80 r; 231 232 /* None of the targets that have snan_bit_is_one use floatx80. */ 233 assert(!snan_bit_is_one(status)); 234#if defined(TARGET_M68K) 235 r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); 236 r.high = 0x7FFF; 237#else 238 /* X86 */ 239 r.low = UINT64_C(0xC000000000000000); 240 r.high = 0xFFFF; 241#endif 242 return r; 243} 244 245/*---------------------------------------------------------------------------- 246| The pattern for a default generated extended double-precision inf. 247*----------------------------------------------------------------------------*/ 248 249#define floatx80_infinity_high 0x7FFF 250#if defined(TARGET_M68K) 251#define floatx80_infinity_low UINT64_C(0x0000000000000000) 252#else 253#define floatx80_infinity_low UINT64_C(0x8000000000000000) 254#endif 255 256const floatx80 floatx80_infinity 257 = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); 258 259/*---------------------------------------------------------------------------- 260| Returns 1 if the half-precision floating-point value `a' is a quiet 261| NaN; otherwise returns 0. 262*----------------------------------------------------------------------------*/ 263 264bool float16_is_quiet_nan(float16 a_, float_status *status) 265{ 266 if (no_signaling_nans(status)) { 267 return float16_is_any_nan(a_); 268 } else { 269 uint16_t a = float16_val(a_); 270 if (snan_bit_is_one(status)) { 271 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 272 } else { 273 274 return ((a >> 9) & 0x3F) == 0x3F; 275 } 276 } 277} 278 279/*---------------------------------------------------------------------------- 280| Returns 1 if the bfloat16 value `a' is a quiet 281| NaN; otherwise returns 0. 282*----------------------------------------------------------------------------*/ 283 284bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status) 285{ 286 if (no_signaling_nans(status)) { 287 return bfloat16_is_any_nan(a_); 288 } else { 289 uint16_t a = a_; 290 if (snan_bit_is_one(status)) { 291 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); 292 } else { 293 return ((a >> 6) & 0x1FF) == 0x1FF; 294 } 295 } 296} 297 298/*---------------------------------------------------------------------------- 299| Returns 1 if the half-precision floating-point value `a' is a signaling 300| NaN; otherwise returns 0. 301*----------------------------------------------------------------------------*/ 302 303bool float16_is_signaling_nan(float16 a_, float_status *status) 304{ 305 if (no_signaling_nans(status)) { 306 return 0; 307 } else { 308 uint16_t a = float16_val(a_); 309 if (snan_bit_is_one(status)) { 310 return ((a >> 9) & 0x3F) == 0x3F; 311 } else { 312 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 313 } 314 } 315} 316 317/*---------------------------------------------------------------------------- 318| Returns 1 if the bfloat16 value `a' is a signaling 319| NaN; otherwise returns 0. 320*----------------------------------------------------------------------------*/ 321 322bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status) 323{ 324 if (no_signaling_nans(status)) { 325 return 0; 326 } else { 327 uint16_t a = a_; 328 if (snan_bit_is_one(status)) { 329 return ((a >> 6) & 0x1FF) == 0x1FF; 330 } else { 331 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); 332 } 333 } 334} 335 336/*---------------------------------------------------------------------------- 337| Returns 1 if the single-precision floating-point value `a' is a quiet 338| NaN; otherwise returns 0. 339*----------------------------------------------------------------------------*/ 340 341bool float32_is_quiet_nan(float32 a_, float_status *status) 342{ 343 if (no_signaling_nans(status)) { 344 return float32_is_any_nan(a_); 345 } else { 346 uint32_t a = float32_val(a_); 347 if (snan_bit_is_one(status)) { 348 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 349 } else { 350 return ((uint32_t)(a << 1) >= 0xFF800000); 351 } 352 } 353} 354 355/*---------------------------------------------------------------------------- 356| Returns 1 if the single-precision floating-point value `a' is a signaling 357| NaN; otherwise returns 0. 358*----------------------------------------------------------------------------*/ 359 360bool float32_is_signaling_nan(float32 a_, float_status *status) 361{ 362 if (no_signaling_nans(status)) { 363 return 0; 364 } else { 365 uint32_t a = float32_val(a_); 366 if (snan_bit_is_one(status)) { 367 return ((uint32_t)(a << 1) >= 0xFF800000); 368 } else { 369 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 370 } 371 } 372} 373 374/*---------------------------------------------------------------------------- 375| Select which NaN to propagate for a two-input operation. 376| IEEE754 doesn't specify all the details of this, so the 377| algorithm is target-specific. 378| The routine is passed various bits of information about the 379| two NaNs and should return 0 to select NaN a and 1 for NaN b. 380| Note that signalling NaNs are always squashed to quiet NaNs 381| by the caller, by calling floatXX_silence_nan() before 382| returning them. 383| 384| aIsLargerSignificand is only valid if both a and b are NaNs 385| of some kind, and is true if a has the larger significand, 386| or if both a and b have the same significand but a is 387| positive but b is negative. It is only needed for the x87 388| tie-break rule. 389*----------------------------------------------------------------------------*/ 390 391static int pickNaN(FloatClass a_cls, FloatClass b_cls, 392 bool aIsLargerSignificand, float_status *status) 393{ 394#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) 395 /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take 396 * the first of: 397 * 1. A if it is signaling 398 * 2. B if it is signaling 399 * 3. A (quiet) 400 * 4. B (quiet) 401 * A signaling NaN is always quietened before returning it. 402 */ 403 /* According to MIPS specifications, if one of the two operands is 404 * a sNaN, a new qNaN has to be generated. This is done in 405 * floatXX_silence_nan(). For qNaN inputs the specifications 406 * says: "When possible, this QNaN result is one of the operand QNaN 407 * values." In practice it seems that most implementations choose 408 * the first operand if both operands are qNaN. In short this gives 409 * the following rules: 410 * 1. A if it is signaling 411 * 2. B if it is signaling 412 * 3. A (quiet) 413 * 4. B (quiet) 414 * A signaling NaN is always silenced before returning it. 415 */ 416 if (is_snan(a_cls)) { 417 return 0; 418 } else if (is_snan(b_cls)) { 419 return 1; 420 } else if (is_qnan(a_cls)) { 421 return 0; 422 } else { 423 return 1; 424 } 425#elif defined(TARGET_PPC) || defined(TARGET_M68K) 426 /* PowerPC propagation rules: 427 * 1. A if it sNaN or qNaN 428 * 2. B if it sNaN or qNaN 429 * A signaling NaN is always silenced before returning it. 430 */ 431 /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL 432 * 3.4 FLOATING-POINT INSTRUCTION DETAILS 433 * If either operand, but not both operands, of an operation is a 434 * nonsignaling NaN, then that NaN is returned as the result. If both 435 * operands are nonsignaling NaNs, then the destination operand 436 * nonsignaling NaN is returned as the result. 437 * If either operand to an operation is a signaling NaN (SNaN), then the 438 * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit 439 * is set in the FPCR ENABLE byte, then the exception is taken and the 440 * destination is not modified. If the SNaN exception enable bit is not 441 * set, setting the SNaN bit in the operand to a one converts the SNaN to 442 * a nonsignaling NaN. The operation then continues as described in the 443 * preceding paragraph for nonsignaling NaNs. 444 */ 445 if (is_nan(a_cls)) { 446 return 0; 447 } else { 448 return 1; 449 } 450#elif defined(TARGET_XTENSA) 451 /* 452 * Xtensa has two NaN propagation modes. 453 * Which one is active is controlled by float_status::use_first_nan. 454 */ 455 if (status->use_first_nan) { 456 if (is_nan(a_cls)) { 457 return 0; 458 } else { 459 return 1; 460 } 461 } else { 462 if (is_nan(b_cls)) { 463 return 1; 464 } else { 465 return 0; 466 } 467 } 468#else 469 /* This implements x87 NaN propagation rules: 470 * SNaN + QNaN => return the QNaN 471 * two SNaNs => return the one with the larger significand, silenced 472 * two QNaNs => return the one with the larger significand 473 * SNaN and a non-NaN => return the SNaN, silenced 474 * QNaN and a non-NaN => return the QNaN 475 * 476 * If we get down to comparing significands and they are the same, 477 * return the NaN with the positive sign bit (if any). 478 */ 479 if (is_snan(a_cls)) { 480 if (is_snan(b_cls)) { 481 return aIsLargerSignificand ? 0 : 1; 482 } 483 return is_qnan(b_cls) ? 1 : 0; 484 } else if (is_qnan(a_cls)) { 485 if (is_snan(b_cls) || !is_qnan(b_cls)) { 486 return 0; 487 } else { 488 return aIsLargerSignificand ? 0 : 1; 489 } 490 } else { 491 return 1; 492 } 493#endif 494} 495 496/*---------------------------------------------------------------------------- 497| Select which NaN to propagate for a three-input operation. 498| For the moment we assume that no CPU needs the 'larger significand' 499| information. 500| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN 501*----------------------------------------------------------------------------*/ 502static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, 503 bool infzero, float_status *status) 504{ 505#if defined(TARGET_ARM) 506 /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns 507 * the default NaN 508 */ 509 if (infzero && is_qnan(c_cls)) { 510 float_raise(float_flag_invalid, status); 511 return 3; 512 } 513 514 /* This looks different from the ARM ARM pseudocode, because the ARM ARM 515 * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. 516 */ 517 if (is_snan(c_cls)) { 518 return 2; 519 } else if (is_snan(a_cls)) { 520 return 0; 521 } else if (is_snan(b_cls)) { 522 return 1; 523 } else if (is_qnan(c_cls)) { 524 return 2; 525 } else if (is_qnan(a_cls)) { 526 return 0; 527 } else { 528 return 1; 529 } 530#elif defined(TARGET_MIPS) 531 if (snan_bit_is_one(status)) { 532 /* 533 * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) 534 * case sets InvalidOp and returns the default NaN 535 */ 536 if (infzero) { 537 float_raise(float_flag_invalid, status); 538 return 3; 539 } 540 /* Prefer sNaN over qNaN, in the a, b, c order. */ 541 if (is_snan(a_cls)) { 542 return 0; 543 } else if (is_snan(b_cls)) { 544 return 1; 545 } else if (is_snan(c_cls)) { 546 return 2; 547 } else if (is_qnan(a_cls)) { 548 return 0; 549 } else if (is_qnan(b_cls)) { 550 return 1; 551 } else { 552 return 2; 553 } 554 } else { 555 /* 556 * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) 557 * case sets InvalidOp and returns the input value 'c' 558 */ 559 if (infzero) { 560 float_raise(float_flag_invalid, status); 561 return 2; 562 } 563 /* Prefer sNaN over qNaN, in the c, a, b order. */ 564 if (is_snan(c_cls)) { 565 return 2; 566 } else if (is_snan(a_cls)) { 567 return 0; 568 } else if (is_snan(b_cls)) { 569 return 1; 570 } else if (is_qnan(c_cls)) { 571 return 2; 572 } else if (is_qnan(a_cls)) { 573 return 0; 574 } else { 575 return 1; 576 } 577 } 578#elif defined(TARGET_PPC) 579 /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer 580 * to return an input NaN if we have one (ie c) rather than generating 581 * a default NaN 582 */ 583 if (infzero) { 584 float_raise(float_flag_invalid, status); 585 return 2; 586 } 587 588 /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; 589 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB 590 */ 591 if (is_nan(a_cls)) { 592 return 0; 593 } else if (is_nan(c_cls)) { 594 return 2; 595 } else { 596 return 1; 597 } 598#elif defined(TARGET_RISCV) 599 /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ 600 if (infzero) { 601 float_raise(float_flag_invalid, status); 602 } 603 return 3; /* default NaN */ 604#elif defined(TARGET_XTENSA) 605 /* 606 * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns 607 * an input NaN if we have one (ie c). 608 */ 609 if (infzero) { 610 float_raise(float_flag_invalid, status); 611 return 2; 612 } 613 if (status->use_first_nan) { 614 if (is_nan(a_cls)) { 615 return 0; 616 } else if (is_nan(b_cls)) { 617 return 1; 618 } else { 619 return 2; 620 } 621 } else { 622 if (is_nan(c_cls)) { 623 return 2; 624 } else if (is_nan(b_cls)) { 625 return 1; 626 } else { 627 return 0; 628 } 629 } 630#else 631 /* A default implementation: prefer a to b to c. 632 * This is unlikely to actually match any real implementation. 633 */ 634 if (is_nan(a_cls)) { 635 return 0; 636 } else if (is_nan(b_cls)) { 637 return 1; 638 } else { 639 return 2; 640 } 641#endif 642} 643 644/*---------------------------------------------------------------------------- 645| Returns 1 if the double-precision floating-point value `a' is a quiet 646| NaN; otherwise returns 0. 647*----------------------------------------------------------------------------*/ 648 649bool float64_is_quiet_nan(float64 a_, float_status *status) 650{ 651 if (no_signaling_nans(status)) { 652 return float64_is_any_nan(a_); 653 } else { 654 uint64_t a = float64_val(a_); 655 if (snan_bit_is_one(status)) { 656 return (((a >> 51) & 0xFFF) == 0xFFE) 657 && (a & 0x0007FFFFFFFFFFFFULL); 658 } else { 659 return ((a << 1) >= 0xFFF0000000000000ULL); 660 } 661 } 662} 663 664/*---------------------------------------------------------------------------- 665| Returns 1 if the double-precision floating-point value `a' is a signaling 666| NaN; otherwise returns 0. 667*----------------------------------------------------------------------------*/ 668 669bool float64_is_signaling_nan(float64 a_, float_status *status) 670{ 671 if (no_signaling_nans(status)) { 672 return 0; 673 } else { 674 uint64_t a = float64_val(a_); 675 if (snan_bit_is_one(status)) { 676 return ((a << 1) >= 0xFFF0000000000000ULL); 677 } else { 678 return (((a >> 51) & 0xFFF) == 0xFFE) 679 && (a & UINT64_C(0x0007FFFFFFFFFFFF)); 680 } 681 } 682} 683 684/*---------------------------------------------------------------------------- 685| Returns 1 if the extended double-precision floating-point value `a' is a 686| quiet NaN; otherwise returns 0. This slightly differs from the same 687| function for other types as floatx80 has an explicit bit. 688*----------------------------------------------------------------------------*/ 689 690int floatx80_is_quiet_nan(floatx80 a, float_status *status) 691{ 692 if (no_signaling_nans(status)) { 693 return floatx80_is_any_nan(a); 694 } else { 695 if (snan_bit_is_one(status)) { 696 uint64_t aLow; 697 698 aLow = a.low & ~0x4000000000000000ULL; 699 return ((a.high & 0x7FFF) == 0x7FFF) 700 && (aLow << 1) 701 && (a.low == aLow); 702 } else { 703 return ((a.high & 0x7FFF) == 0x7FFF) 704 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); 705 } 706 } 707} 708 709/*---------------------------------------------------------------------------- 710| Returns 1 if the extended double-precision floating-point value `a' is a 711| signaling NaN; otherwise returns 0. This slightly differs from the same 712| function for other types as floatx80 has an explicit bit. 713*----------------------------------------------------------------------------*/ 714 715int floatx80_is_signaling_nan(floatx80 a, float_status *status) 716{ 717 if (no_signaling_nans(status)) { 718 return 0; 719 } else { 720 if (snan_bit_is_one(status)) { 721 return ((a.high & 0x7FFF) == 0x7FFF) 722 && ((a.low << 1) >= 0x8000000000000000ULL); 723 } else { 724 uint64_t aLow; 725 726 aLow = a.low & ~UINT64_C(0x4000000000000000); 727 return ((a.high & 0x7FFF) == 0x7FFF) 728 && (uint64_t)(aLow << 1) 729 && (a.low == aLow); 730 } 731 } 732} 733 734/*---------------------------------------------------------------------------- 735| Returns a quiet NaN from a signalling NaN for the extended double-precision 736| floating point value `a'. 737*----------------------------------------------------------------------------*/ 738 739floatx80 floatx80_silence_nan(floatx80 a, float_status *status) 740{ 741 /* None of the targets that have snan_bit_is_one use floatx80. */ 742 assert(!snan_bit_is_one(status)); 743 a.low |= UINT64_C(0xC000000000000000); 744 return a; 745} 746 747/*---------------------------------------------------------------------------- 748| Takes two extended double-precision floating-point values `a' and `b', one 749| of which is a NaN, and returns the appropriate NaN result. If either `a' or 750| `b' is a signaling NaN, the invalid exception is raised. 751*----------------------------------------------------------------------------*/ 752 753floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) 754{ 755 bool aIsLargerSignificand; 756 FloatClass a_cls, b_cls; 757 758 /* This is not complete, but is good enough for pickNaN. */ 759 a_cls = (!floatx80_is_any_nan(a) 760 ? float_class_normal 761 : floatx80_is_signaling_nan(a, status) 762 ? float_class_snan 763 : float_class_qnan); 764 b_cls = (!floatx80_is_any_nan(b) 765 ? float_class_normal 766 : floatx80_is_signaling_nan(b, status) 767 ? float_class_snan 768 : float_class_qnan); 769 770 if (is_snan(a_cls) || is_snan(b_cls)) { 771 float_raise(float_flag_invalid, status); 772 } 773 774 if (status->default_nan_mode) { 775 return floatx80_default_nan(status); 776 } 777 778 if (a.low < b.low) { 779 aIsLargerSignificand = 0; 780 } else if (b.low < a.low) { 781 aIsLargerSignificand = 1; 782 } else { 783 aIsLargerSignificand = (a.high < b.high) ? 1 : 0; 784 } 785 786 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 787 if (is_snan(b_cls)) { 788 return floatx80_silence_nan(b, status); 789 } 790 return b; 791 } else { 792 if (is_snan(a_cls)) { 793 return floatx80_silence_nan(a, status); 794 } 795 return a; 796 } 797} 798 799/*---------------------------------------------------------------------------- 800| Returns 1 if the quadruple-precision floating-point value `a' is a quiet 801| NaN; otherwise returns 0. 802*----------------------------------------------------------------------------*/ 803 804bool float128_is_quiet_nan(float128 a, float_status *status) 805{ 806 if (no_signaling_nans(status)) { 807 return float128_is_any_nan(a); 808 } else { 809 if (snan_bit_is_one(status)) { 810 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 811 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); 812 } else { 813 return ((a.high << 1) >= 0xFFFF000000000000ULL) 814 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 815 } 816 } 817} 818 819/*---------------------------------------------------------------------------- 820| Returns 1 if the quadruple-precision floating-point value `a' is a 821| signaling NaN; otherwise returns 0. 822*----------------------------------------------------------------------------*/ 823 824bool float128_is_signaling_nan(float128 a, float_status *status) 825{ 826 if (no_signaling_nans(status)) { 827 return 0; 828 } else { 829 if (snan_bit_is_one(status)) { 830 return ((a.high << 1) >= 0xFFFF000000000000ULL) 831 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 832 } else { 833 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 834 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); 835 } 836 } 837} 838