1/* 2 * QEMU float support 3 * 4 * The code in this source file is derived from release 2a of the SoftFloat 5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and 6 * some later contributions) are provided under that license, as detailed below. 7 * It has subsequently been modified by contributors to the QEMU Project, 8 * so some portions are provided under: 9 * the SoftFloat-2a license 10 * the BSD license 11 * GPL-v2-or-later 12 * 13 * Any future contributions to this file after December 1st 2014 will be 14 * taken to be licensed under the Softfloat-2a license unless specifically 15 * indicated otherwise. 16 */ 17 18/* 19=============================================================================== 20This C source fragment is part of the SoftFloat IEC/IEEE Floating-point 21Arithmetic Package, Release 2a. 22 23Written by John R. Hauser. This work was made possible in part by the 24International Computer Science Institute, located at Suite 600, 1947 Center 25Street, Berkeley, California 94704. Funding was partially provided by the 26National Science Foundation under grant MIP-9311980. The original version 27of this code was written as part of a project to build a fixed-point vector 28processor in collaboration with the University of California at Berkeley, 29overseen by Profs. Nelson Morgan and John Wawrzynek. More information 30is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ 31arithmetic/SoftFloat.html'. 32 33THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 34has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 35TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 36PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 37AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 38 39Derivative works are acceptable, even for commercial purposes, so long as 40(1) they include prominent notice that the work is derivative, and (2) they 41include prominent notice akin to these four paragraphs for those parts of 42this code that are retained. 43 44=============================================================================== 45*/ 46 47/* BSD licensing: 48 * Copyright (c) 2006, Fabrice Bellard 49 * All rights reserved. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions are met: 53 * 54 * 1. Redistributions of source code must retain the above copyright notice, 55 * this list of conditions and the following disclaimer. 56 * 57 * 2. Redistributions in binary form must reproduce the above copyright notice, 58 * this list of conditions and the following disclaimer in the documentation 59 * and/or other materials provided with the distribution. 60 * 61 * 3. Neither the name of the copyright holder nor the names of its contributors 62 * may be used to endorse or promote products derived from this software without 63 * specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 75 * THE POSSIBILITY OF SUCH DAMAGE. 76 */ 77 78/* Portions of this work are licensed under the terms of the GNU GPL, 79 * version 2 or later. See the COPYING file in the top-level directory. 80 */ 81 82/* 83 * Define whether architecture deviates from IEEE in not supporting 84 * signaling NaNs (so all NaNs are treated as quiet). 85 */ 86static inline bool no_signaling_nans(float_status *status) 87{ 88#if defined(TARGET_XTENSA) 89 return status->no_signaling_nans; 90#else 91 return false; 92#endif 93} 94 95/* Define how the architecture discriminates signaling NaNs. 96 * This done with the most significant bit of the fraction. 97 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 98 * the msb must be zero. MIPS is (so far) unique in supporting both the 99 * 2008 revision and backward compatibility with their original choice. 100 * Thus for MIPS we must make the choice at runtime. 101 */ 102static inline bool snan_bit_is_one(float_status *status) 103{ 104#if defined(TARGET_MIPS) 105 return status->snan_bit_is_one; 106#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4) 107 return 1; 108#else 109 return 0; 110#endif 111} 112 113/*---------------------------------------------------------------------------- 114| For the deconstructed floating-point with fraction FRAC, return true 115| if the fraction represents a signalling NaN; otherwise false. 116*----------------------------------------------------------------------------*/ 117 118static bool parts_is_snan_frac(uint64_t frac, float_status *status) 119{ 120 if (no_signaling_nans(status)) { 121 return false; 122 } else { 123 bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); 124 return msb == snan_bit_is_one(status); 125 } 126} 127 128/*---------------------------------------------------------------------------- 129| The pattern for a default generated deconstructed floating-point NaN. 130*----------------------------------------------------------------------------*/ 131 132static FloatParts parts_default_nan(float_status *status) 133{ 134 bool sign = 0; 135 uint64_t frac; 136 137#if defined(TARGET_SPARC) || defined(TARGET_M68K) 138 /* !snan_bit_is_one, set all bits */ 139 frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; 140#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ 141 || defined(TARGET_MICROBLAZE) 142 /* !snan_bit_is_one, set sign and msb */ 143 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); 144 sign = 1; 145#elif defined(TARGET_HPPA) 146 /* snan_bit_is_one, set msb-1. */ 147 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); 148#else 149 /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, 150 * S390, SH4, TriCore, and Xtensa. I cannot find documentation 151 * for Unicore32; the choice from the original commit is unchanged. 152 * Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile, 153 * do not have floating-point. 154 */ 155 if (snan_bit_is_one(status)) { 156 /* set all bits other than msb */ 157 frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; 158 } else { 159 /* set msb */ 160 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); 161 } 162#endif 163 164 return (FloatParts) { 165 .cls = float_class_qnan, 166 .sign = sign, 167 .exp = INT_MAX, 168 .frac = frac 169 }; 170} 171 172/*---------------------------------------------------------------------------- 173| Returns a quiet NaN from a signalling NaN for the deconstructed 174| floating-point parts. 175*----------------------------------------------------------------------------*/ 176 177static FloatParts parts_silence_nan(FloatParts a, float_status *status) 178{ 179 g_assert(!no_signaling_nans(status)); 180#if defined(TARGET_HPPA) 181 a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); 182 a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); 183#else 184 if (snan_bit_is_one(status)) { 185 return parts_default_nan(status); 186 } else { 187 a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); 188 } 189#endif 190 a.cls = float_class_qnan; 191 return a; 192} 193 194/*---------------------------------------------------------------------------- 195| The pattern for a default generated extended double-precision NaN. 196*----------------------------------------------------------------------------*/ 197floatx80 floatx80_default_nan(float_status *status) 198{ 199 floatx80 r; 200 201 /* None of the targets that have snan_bit_is_one use floatx80. */ 202 assert(!snan_bit_is_one(status)); 203#if defined(TARGET_M68K) 204 r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); 205 r.high = 0x7FFF; 206#else 207 /* X86 */ 208 r.low = UINT64_C(0xC000000000000000); 209 r.high = 0xFFFF; 210#endif 211 return r; 212} 213 214/*---------------------------------------------------------------------------- 215| The pattern for a default generated extended double-precision inf. 216*----------------------------------------------------------------------------*/ 217 218#define floatx80_infinity_high 0x7FFF 219#if defined(TARGET_M68K) 220#define floatx80_infinity_low UINT64_C(0x0000000000000000) 221#else 222#define floatx80_infinity_low UINT64_C(0x8000000000000000) 223#endif 224 225const floatx80 floatx80_infinity 226 = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); 227 228/*---------------------------------------------------------------------------- 229| Raises the exceptions specified by `flags'. Floating-point traps can be 230| defined here if desired. It is currently not possible for such a trap 231| to substitute a result value. If traps are not implemented, this routine 232| should be simply `float_exception_flags |= flags;'. 233*----------------------------------------------------------------------------*/ 234 235void float_raise(uint8_t flags, float_status *status) 236{ 237 status->float_exception_flags |= flags; 238} 239 240/*---------------------------------------------------------------------------- 241| Internal canonical NaN format. 242*----------------------------------------------------------------------------*/ 243typedef struct { 244 bool sign; 245 uint64_t high, low; 246} commonNaNT; 247 248/*---------------------------------------------------------------------------- 249| Returns 1 if the half-precision floating-point value `a' is a quiet 250| NaN; otherwise returns 0. 251*----------------------------------------------------------------------------*/ 252 253bool float16_is_quiet_nan(float16 a_, float_status *status) 254{ 255 if (no_signaling_nans(status)) { 256 return float16_is_any_nan(a_); 257 } else { 258 uint16_t a = float16_val(a_); 259 if (snan_bit_is_one(status)) { 260 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 261 } else { 262 263 return ((a >> 9) & 0x3F) == 0x3F; 264 } 265 } 266} 267 268/*---------------------------------------------------------------------------- 269| Returns 1 if the half-precision floating-point value `a' is a signaling 270| NaN; otherwise returns 0. 271*----------------------------------------------------------------------------*/ 272 273bool float16_is_signaling_nan(float16 a_, float_status *status) 274{ 275 if (no_signaling_nans(status)) { 276 return 0; 277 } else { 278 uint16_t a = float16_val(a_); 279 if (snan_bit_is_one(status)) { 280 return ((a >> 9) & 0x3F) == 0x3F; 281 } else { 282 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 283 } 284 } 285} 286 287/*---------------------------------------------------------------------------- 288| Returns 1 if the single-precision floating-point value `a' is a quiet 289| NaN; otherwise returns 0. 290*----------------------------------------------------------------------------*/ 291 292bool float32_is_quiet_nan(float32 a_, float_status *status) 293{ 294 if (no_signaling_nans(status)) { 295 return float32_is_any_nan(a_); 296 } else { 297 uint32_t a = float32_val(a_); 298 if (snan_bit_is_one(status)) { 299 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 300 } else { 301 return ((uint32_t)(a << 1) >= 0xFF800000); 302 } 303 } 304} 305 306/*---------------------------------------------------------------------------- 307| Returns 1 if the single-precision floating-point value `a' is a signaling 308| NaN; otherwise returns 0. 309*----------------------------------------------------------------------------*/ 310 311bool float32_is_signaling_nan(float32 a_, float_status *status) 312{ 313 if (no_signaling_nans(status)) { 314 return 0; 315 } else { 316 uint32_t a = float32_val(a_); 317 if (snan_bit_is_one(status)) { 318 return ((uint32_t)(a << 1) >= 0xFF800000); 319 } else { 320 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 321 } 322 } 323} 324 325/*---------------------------------------------------------------------------- 326| Returns the result of converting the single-precision floating-point NaN 327| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid 328| exception is raised. 329*----------------------------------------------------------------------------*/ 330 331static commonNaNT float32ToCommonNaN(float32 a, float_status *status) 332{ 333 commonNaNT z; 334 335 if (float32_is_signaling_nan(a, status)) { 336 float_raise(float_flag_invalid, status); 337 } 338 z.sign = float32_val(a) >> 31; 339 z.low = 0; 340 z.high = ((uint64_t)float32_val(a)) << 41; 341 return z; 342} 343 344/*---------------------------------------------------------------------------- 345| Returns the result of converting the canonical NaN `a' to the single- 346| precision floating-point format. 347*----------------------------------------------------------------------------*/ 348 349static float32 commonNaNToFloat32(commonNaNT a, float_status *status) 350{ 351 uint32_t mantissa = a.high >> 41; 352 353 if (status->default_nan_mode) { 354 return float32_default_nan(status); 355 } 356 357 if (mantissa) { 358 return make_float32( 359 (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41)); 360 } else { 361 return float32_default_nan(status); 362 } 363} 364 365/*---------------------------------------------------------------------------- 366| Select which NaN to propagate for a two-input operation. 367| IEEE754 doesn't specify all the details of this, so the 368| algorithm is target-specific. 369| The routine is passed various bits of information about the 370| two NaNs and should return 0 to select NaN a and 1 for NaN b. 371| Note that signalling NaNs are always squashed to quiet NaNs 372| by the caller, by calling floatXX_silence_nan() before 373| returning them. 374| 375| aIsLargerSignificand is only valid if both a and b are NaNs 376| of some kind, and is true if a has the larger significand, 377| or if both a and b have the same significand but a is 378| positive but b is negative. It is only needed for the x87 379| tie-break rule. 380*----------------------------------------------------------------------------*/ 381 382static int pickNaN(FloatClass a_cls, FloatClass b_cls, 383 bool aIsLargerSignificand, float_status *status) 384{ 385#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) 386 /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take 387 * the first of: 388 * 1. A if it is signaling 389 * 2. B if it is signaling 390 * 3. A (quiet) 391 * 4. B (quiet) 392 * A signaling NaN is always quietened before returning it. 393 */ 394 /* According to MIPS specifications, if one of the two operands is 395 * a sNaN, a new qNaN has to be generated. This is done in 396 * floatXX_silence_nan(). For qNaN inputs the specifications 397 * says: "When possible, this QNaN result is one of the operand QNaN 398 * values." In practice it seems that most implementations choose 399 * the first operand if both operands are qNaN. In short this gives 400 * the following rules: 401 * 1. A if it is signaling 402 * 2. B if it is signaling 403 * 3. A (quiet) 404 * 4. B (quiet) 405 * A signaling NaN is always silenced before returning it. 406 */ 407 if (is_snan(a_cls)) { 408 return 0; 409 } else if (is_snan(b_cls)) { 410 return 1; 411 } else if (is_qnan(a_cls)) { 412 return 0; 413 } else { 414 return 1; 415 } 416#elif defined(TARGET_PPC) || defined(TARGET_M68K) 417 /* PowerPC propagation rules: 418 * 1. A if it sNaN or qNaN 419 * 2. B if it sNaN or qNaN 420 * A signaling NaN is always silenced before returning it. 421 */ 422 /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL 423 * 3.4 FLOATING-POINT INSTRUCTION DETAILS 424 * If either operand, but not both operands, of an operation is a 425 * nonsignaling NaN, then that NaN is returned as the result. If both 426 * operands are nonsignaling NaNs, then the destination operand 427 * nonsignaling NaN is returned as the result. 428 * If either operand to an operation is a signaling NaN (SNaN), then the 429 * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit 430 * is set in the FPCR ENABLE byte, then the exception is taken and the 431 * destination is not modified. If the SNaN exception enable bit is not 432 * set, setting the SNaN bit in the operand to a one converts the SNaN to 433 * a nonsignaling NaN. The operation then continues as described in the 434 * preceding paragraph for nonsignaling NaNs. 435 */ 436 if (is_nan(a_cls)) { 437 return 0; 438 } else { 439 return 1; 440 } 441#elif defined(TARGET_XTENSA) 442 /* 443 * Xtensa has two NaN propagation modes. 444 * Which one is active is controlled by float_status::use_first_nan. 445 */ 446 if (status->use_first_nan) { 447 if (is_nan(a_cls)) { 448 return 0; 449 } else { 450 return 1; 451 } 452 } else { 453 if (is_nan(b_cls)) { 454 return 1; 455 } else { 456 return 0; 457 } 458 } 459#else 460 /* This implements x87 NaN propagation rules: 461 * SNaN + QNaN => return the QNaN 462 * two SNaNs => return the one with the larger significand, silenced 463 * two QNaNs => return the one with the larger significand 464 * SNaN and a non-NaN => return the SNaN, silenced 465 * QNaN and a non-NaN => return the QNaN 466 * 467 * If we get down to comparing significands and they are the same, 468 * return the NaN with the positive sign bit (if any). 469 */ 470 if (is_snan(a_cls)) { 471 if (is_snan(b_cls)) { 472 return aIsLargerSignificand ? 0 : 1; 473 } 474 return is_qnan(b_cls) ? 1 : 0; 475 } else if (is_qnan(a_cls)) { 476 if (is_snan(b_cls) || !is_qnan(b_cls)) { 477 return 0; 478 } else { 479 return aIsLargerSignificand ? 0 : 1; 480 } 481 } else { 482 return 1; 483 } 484#endif 485} 486 487/*---------------------------------------------------------------------------- 488| Select which NaN to propagate for a three-input operation. 489| For the moment we assume that no CPU needs the 'larger significand' 490| information. 491| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN 492*----------------------------------------------------------------------------*/ 493static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, 494 bool infzero, float_status *status) 495{ 496#if defined(TARGET_ARM) 497 /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns 498 * the default NaN 499 */ 500 if (infzero && is_qnan(c_cls)) { 501 float_raise(float_flag_invalid, status); 502 return 3; 503 } 504 505 /* This looks different from the ARM ARM pseudocode, because the ARM ARM 506 * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. 507 */ 508 if (is_snan(c_cls)) { 509 return 2; 510 } else if (is_snan(a_cls)) { 511 return 0; 512 } else if (is_snan(b_cls)) { 513 return 1; 514 } else if (is_qnan(c_cls)) { 515 return 2; 516 } else if (is_qnan(a_cls)) { 517 return 0; 518 } else { 519 return 1; 520 } 521#elif defined(TARGET_MIPS) 522 if (snan_bit_is_one(status)) { 523 /* 524 * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) 525 * case sets InvalidOp and returns the default NaN 526 */ 527 if (infzero) { 528 float_raise(float_flag_invalid, status); 529 return 3; 530 } 531 /* Prefer sNaN over qNaN, in the a, b, c order. */ 532 if (is_snan(a_cls)) { 533 return 0; 534 } else if (is_snan(b_cls)) { 535 return 1; 536 } else if (is_snan(c_cls)) { 537 return 2; 538 } else if (is_qnan(a_cls)) { 539 return 0; 540 } else if (is_qnan(b_cls)) { 541 return 1; 542 } else { 543 return 2; 544 } 545 } else { 546 /* 547 * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) 548 * case sets InvalidOp and returns the input value 'c' 549 */ 550 if (infzero) { 551 float_raise(float_flag_invalid, status); 552 return 2; 553 } 554 /* Prefer sNaN over qNaN, in the c, a, b order. */ 555 if (is_snan(c_cls)) { 556 return 2; 557 } else if (is_snan(a_cls)) { 558 return 0; 559 } else if (is_snan(b_cls)) { 560 return 1; 561 } else if (is_qnan(c_cls)) { 562 return 2; 563 } else if (is_qnan(a_cls)) { 564 return 0; 565 } else { 566 return 1; 567 } 568 } 569#elif defined(TARGET_PPC) 570 /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer 571 * to return an input NaN if we have one (ie c) rather than generating 572 * a default NaN 573 */ 574 if (infzero) { 575 float_raise(float_flag_invalid, status); 576 return 2; 577 } 578 579 /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; 580 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB 581 */ 582 if (is_nan(a_cls)) { 583 return 0; 584 } else if (is_nan(c_cls)) { 585 return 2; 586 } else { 587 return 1; 588 } 589#elif defined(TARGET_XTENSA) 590 /* 591 * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns 592 * an input NaN if we have one (ie c). 593 */ 594 if (infzero) { 595 float_raise(float_flag_invalid, status); 596 return 2; 597 } 598 if (status->use_first_nan) { 599 if (is_nan(a_cls)) { 600 return 0; 601 } else if (is_nan(b_cls)) { 602 return 1; 603 } else { 604 return 2; 605 } 606 } else { 607 if (is_nan(c_cls)) { 608 return 2; 609 } else if (is_nan(b_cls)) { 610 return 1; 611 } else { 612 return 0; 613 } 614 } 615#else 616 /* A default implementation: prefer a to b to c. 617 * This is unlikely to actually match any real implementation. 618 */ 619 if (is_nan(a_cls)) { 620 return 0; 621 } else if (is_nan(b_cls)) { 622 return 1; 623 } else { 624 return 2; 625 } 626#endif 627} 628 629/*---------------------------------------------------------------------------- 630| Takes two single-precision floating-point values `a' and `b', one of which 631| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a 632| signaling NaN, the invalid exception is raised. 633*----------------------------------------------------------------------------*/ 634 635static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) 636{ 637 bool aIsLargerSignificand; 638 uint32_t av, bv; 639 FloatClass a_cls, b_cls; 640 641 /* This is not complete, but is good enough for pickNaN. */ 642 a_cls = (!float32_is_any_nan(a) 643 ? float_class_normal 644 : float32_is_signaling_nan(a, status) 645 ? float_class_snan 646 : float_class_qnan); 647 b_cls = (!float32_is_any_nan(b) 648 ? float_class_normal 649 : float32_is_signaling_nan(b, status) 650 ? float_class_snan 651 : float_class_qnan); 652 653 av = float32_val(a); 654 bv = float32_val(b); 655 656 if (is_snan(a_cls) || is_snan(b_cls)) { 657 float_raise(float_flag_invalid, status); 658 } 659 660 if (status->default_nan_mode) { 661 return float32_default_nan(status); 662 } 663 664 if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) { 665 aIsLargerSignificand = 0; 666 } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) { 667 aIsLargerSignificand = 1; 668 } else { 669 aIsLargerSignificand = (av < bv) ? 1 : 0; 670 } 671 672 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 673 if (is_snan(b_cls)) { 674 return float32_silence_nan(b, status); 675 } 676 return b; 677 } else { 678 if (is_snan(a_cls)) { 679 return float32_silence_nan(a, status); 680 } 681 return a; 682 } 683} 684 685/*---------------------------------------------------------------------------- 686| Returns 1 if the double-precision floating-point value `a' is a quiet 687| NaN; otherwise returns 0. 688*----------------------------------------------------------------------------*/ 689 690bool float64_is_quiet_nan(float64 a_, float_status *status) 691{ 692 if (no_signaling_nans(status)) { 693 return float64_is_any_nan(a_); 694 } else { 695 uint64_t a = float64_val(a_); 696 if (snan_bit_is_one(status)) { 697 return (((a >> 51) & 0xFFF) == 0xFFE) 698 && (a & 0x0007FFFFFFFFFFFFULL); 699 } else { 700 return ((a << 1) >= 0xFFF0000000000000ULL); 701 } 702 } 703} 704 705/*---------------------------------------------------------------------------- 706| Returns 1 if the double-precision floating-point value `a' is a signaling 707| NaN; otherwise returns 0. 708*----------------------------------------------------------------------------*/ 709 710bool float64_is_signaling_nan(float64 a_, float_status *status) 711{ 712 if (no_signaling_nans(status)) { 713 return 0; 714 } else { 715 uint64_t a = float64_val(a_); 716 if (snan_bit_is_one(status)) { 717 return ((a << 1) >= 0xFFF0000000000000ULL); 718 } else { 719 return (((a >> 51) & 0xFFF) == 0xFFE) 720 && (a & UINT64_C(0x0007FFFFFFFFFFFF)); 721 } 722 } 723} 724 725/*---------------------------------------------------------------------------- 726| Returns the result of converting the double-precision floating-point NaN 727| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid 728| exception is raised. 729*----------------------------------------------------------------------------*/ 730 731static commonNaNT float64ToCommonNaN(float64 a, float_status *status) 732{ 733 commonNaNT z; 734 735 if (float64_is_signaling_nan(a, status)) { 736 float_raise(float_flag_invalid, status); 737 } 738 z.sign = float64_val(a) >> 63; 739 z.low = 0; 740 z.high = float64_val(a) << 12; 741 return z; 742} 743 744/*---------------------------------------------------------------------------- 745| Returns the result of converting the canonical NaN `a' to the double- 746| precision floating-point format. 747*----------------------------------------------------------------------------*/ 748 749static float64 commonNaNToFloat64(commonNaNT a, float_status *status) 750{ 751 uint64_t mantissa = a.high >> 12; 752 753 if (status->default_nan_mode) { 754 return float64_default_nan(status); 755 } 756 757 if (mantissa) { 758 return make_float64( 759 (((uint64_t) a.sign) << 63) 760 | UINT64_C(0x7FF0000000000000) 761 | (a.high >> 12)); 762 } else { 763 return float64_default_nan(status); 764 } 765} 766 767/*---------------------------------------------------------------------------- 768| Takes two double-precision floating-point values `a' and `b', one of which 769| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a 770| signaling NaN, the invalid exception is raised. 771*----------------------------------------------------------------------------*/ 772 773static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) 774{ 775 bool aIsLargerSignificand; 776 uint64_t av, bv; 777 FloatClass a_cls, b_cls; 778 779 /* This is not complete, but is good enough for pickNaN. */ 780 a_cls = (!float64_is_any_nan(a) 781 ? float_class_normal 782 : float64_is_signaling_nan(a, status) 783 ? float_class_snan 784 : float_class_qnan); 785 b_cls = (!float64_is_any_nan(b) 786 ? float_class_normal 787 : float64_is_signaling_nan(b, status) 788 ? float_class_snan 789 : float_class_qnan); 790 791 av = float64_val(a); 792 bv = float64_val(b); 793 794 if (is_snan(a_cls) || is_snan(b_cls)) { 795 float_raise(float_flag_invalid, status); 796 } 797 798 if (status->default_nan_mode) { 799 return float64_default_nan(status); 800 } 801 802 if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) { 803 aIsLargerSignificand = 0; 804 } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) { 805 aIsLargerSignificand = 1; 806 } else { 807 aIsLargerSignificand = (av < bv) ? 1 : 0; 808 } 809 810 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 811 if (is_snan(b_cls)) { 812 return float64_silence_nan(b, status); 813 } 814 return b; 815 } else { 816 if (is_snan(a_cls)) { 817 return float64_silence_nan(a, status); 818 } 819 return a; 820 } 821} 822 823/*---------------------------------------------------------------------------- 824| Returns 1 if the extended double-precision floating-point value `a' is a 825| quiet NaN; otherwise returns 0. This slightly differs from the same 826| function for other types as floatx80 has an explicit bit. 827*----------------------------------------------------------------------------*/ 828 829int floatx80_is_quiet_nan(floatx80 a, float_status *status) 830{ 831 if (no_signaling_nans(status)) { 832 return floatx80_is_any_nan(a); 833 } else { 834 if (snan_bit_is_one(status)) { 835 uint64_t aLow; 836 837 aLow = a.low & ~0x4000000000000000ULL; 838 return ((a.high & 0x7FFF) == 0x7FFF) 839 && (aLow << 1) 840 && (a.low == aLow); 841 } else { 842 return ((a.high & 0x7FFF) == 0x7FFF) 843 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); 844 } 845 } 846} 847 848/*---------------------------------------------------------------------------- 849| Returns 1 if the extended double-precision floating-point value `a' is a 850| signaling NaN; otherwise returns 0. This slightly differs from the same 851| function for other types as floatx80 has an explicit bit. 852*----------------------------------------------------------------------------*/ 853 854int floatx80_is_signaling_nan(floatx80 a, float_status *status) 855{ 856 if (no_signaling_nans(status)) { 857 return 0; 858 } else { 859 if (snan_bit_is_one(status)) { 860 return ((a.high & 0x7FFF) == 0x7FFF) 861 && ((a.low << 1) >= 0x8000000000000000ULL); 862 } else { 863 uint64_t aLow; 864 865 aLow = a.low & ~UINT64_C(0x4000000000000000); 866 return ((a.high & 0x7FFF) == 0x7FFF) 867 && (uint64_t)(aLow << 1) 868 && (a.low == aLow); 869 } 870 } 871} 872 873/*---------------------------------------------------------------------------- 874| Returns a quiet NaN from a signalling NaN for the extended double-precision 875| floating point value `a'. 876*----------------------------------------------------------------------------*/ 877 878floatx80 floatx80_silence_nan(floatx80 a, float_status *status) 879{ 880 /* None of the targets that have snan_bit_is_one use floatx80. */ 881 assert(!snan_bit_is_one(status)); 882 a.low |= UINT64_C(0xC000000000000000); 883 return a; 884} 885 886/*---------------------------------------------------------------------------- 887| Returns the result of converting the extended double-precision floating- 888| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the 889| invalid exception is raised. 890*----------------------------------------------------------------------------*/ 891 892static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status) 893{ 894 floatx80 dflt; 895 commonNaNT z; 896 897 if (floatx80_is_signaling_nan(a, status)) { 898 float_raise(float_flag_invalid, status); 899 } 900 if (a.low >> 63) { 901 z.sign = a.high >> 15; 902 z.low = 0; 903 z.high = a.low << 1; 904 } else { 905 dflt = floatx80_default_nan(status); 906 z.sign = dflt.high >> 15; 907 z.low = 0; 908 z.high = dflt.low << 1; 909 } 910 return z; 911} 912 913/*---------------------------------------------------------------------------- 914| Returns the result of converting the canonical NaN `a' to the extended 915| double-precision floating-point format. 916*----------------------------------------------------------------------------*/ 917 918static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status) 919{ 920 floatx80 z; 921 922 if (status->default_nan_mode) { 923 return floatx80_default_nan(status); 924 } 925 926 if (a.high >> 1) { 927 z.low = UINT64_C(0x8000000000000000) | a.high >> 1; 928 z.high = (((uint16_t)a.sign) << 15) | 0x7FFF; 929 } else { 930 z = floatx80_default_nan(status); 931 } 932 return z; 933} 934 935/*---------------------------------------------------------------------------- 936| Takes two extended double-precision floating-point values `a' and `b', one 937| of which is a NaN, and returns the appropriate NaN result. If either `a' or 938| `b' is a signaling NaN, the invalid exception is raised. 939*----------------------------------------------------------------------------*/ 940 941floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) 942{ 943 bool aIsLargerSignificand; 944 FloatClass a_cls, b_cls; 945 946 /* This is not complete, but is good enough for pickNaN. */ 947 a_cls = (!floatx80_is_any_nan(a) 948 ? float_class_normal 949 : floatx80_is_signaling_nan(a, status) 950 ? float_class_snan 951 : float_class_qnan); 952 b_cls = (!floatx80_is_any_nan(b) 953 ? float_class_normal 954 : floatx80_is_signaling_nan(b, status) 955 ? float_class_snan 956 : float_class_qnan); 957 958 if (is_snan(a_cls) || is_snan(b_cls)) { 959 float_raise(float_flag_invalid, status); 960 } 961 962 if (status->default_nan_mode) { 963 return floatx80_default_nan(status); 964 } 965 966 if (a.low < b.low) { 967 aIsLargerSignificand = 0; 968 } else if (b.low < a.low) { 969 aIsLargerSignificand = 1; 970 } else { 971 aIsLargerSignificand = (a.high < b.high) ? 1 : 0; 972 } 973 974 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 975 if (is_snan(b_cls)) { 976 return floatx80_silence_nan(b, status); 977 } 978 return b; 979 } else { 980 if (is_snan(a_cls)) { 981 return floatx80_silence_nan(a, status); 982 } 983 return a; 984 } 985} 986 987/*---------------------------------------------------------------------------- 988| Returns 1 if the quadruple-precision floating-point value `a' is a quiet 989| NaN; otherwise returns 0. 990*----------------------------------------------------------------------------*/ 991 992bool float128_is_quiet_nan(float128 a, float_status *status) 993{ 994 if (no_signaling_nans(status)) { 995 return float128_is_any_nan(a); 996 } else { 997 if (snan_bit_is_one(status)) { 998 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 999 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); 1000 } else { 1001 return ((a.high << 1) >= 0xFFFF000000000000ULL) 1002 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 1003 } 1004 } 1005} 1006 1007/*---------------------------------------------------------------------------- 1008| Returns 1 if the quadruple-precision floating-point value `a' is a 1009| signaling NaN; otherwise returns 0. 1010*----------------------------------------------------------------------------*/ 1011 1012bool float128_is_signaling_nan(float128 a, float_status *status) 1013{ 1014 if (no_signaling_nans(status)) { 1015 return 0; 1016 } else { 1017 if (snan_bit_is_one(status)) { 1018 return ((a.high << 1) >= 0xFFFF000000000000ULL) 1019 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 1020 } else { 1021 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 1022 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); 1023 } 1024 } 1025} 1026 1027/*---------------------------------------------------------------------------- 1028| Returns a quiet NaN from a signalling NaN for the quadruple-precision 1029| floating point value `a'. 1030*----------------------------------------------------------------------------*/ 1031 1032float128 float128_silence_nan(float128 a, float_status *status) 1033{ 1034 if (no_signaling_nans(status)) { 1035 g_assert_not_reached(); 1036 } else { 1037 if (snan_bit_is_one(status)) { 1038 return float128_default_nan(status); 1039 } else { 1040 a.high |= UINT64_C(0x0000800000000000); 1041 return a; 1042 } 1043 } 1044} 1045 1046/*---------------------------------------------------------------------------- 1047| Returns the result of converting the quadruple-precision floating-point NaN 1048| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid 1049| exception is raised. 1050*----------------------------------------------------------------------------*/ 1051 1052static commonNaNT float128ToCommonNaN(float128 a, float_status *status) 1053{ 1054 commonNaNT z; 1055 1056 if (float128_is_signaling_nan(a, status)) { 1057 float_raise(float_flag_invalid, status); 1058 } 1059 z.sign = a.high >> 63; 1060 shortShift128Left(a.high, a.low, 16, &z.high, &z.low); 1061 return z; 1062} 1063 1064/*---------------------------------------------------------------------------- 1065| Returns the result of converting the canonical NaN `a' to the quadruple- 1066| precision floating-point format. 1067*----------------------------------------------------------------------------*/ 1068 1069static float128 commonNaNToFloat128(commonNaNT a, float_status *status) 1070{ 1071 float128 z; 1072 1073 if (status->default_nan_mode) { 1074 return float128_default_nan(status); 1075 } 1076 1077 shift128Right(a.high, a.low, 16, &z.high, &z.low); 1078 z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000); 1079 return z; 1080} 1081 1082/*---------------------------------------------------------------------------- 1083| Takes two quadruple-precision floating-point values `a' and `b', one of 1084| which is a NaN, and returns the appropriate NaN result. If either `a' or 1085| `b' is a signaling NaN, the invalid exception is raised. 1086*----------------------------------------------------------------------------*/ 1087 1088static float128 propagateFloat128NaN(float128 a, float128 b, 1089 float_status *status) 1090{ 1091 bool aIsLargerSignificand; 1092 FloatClass a_cls, b_cls; 1093 1094 /* This is not complete, but is good enough for pickNaN. */ 1095 a_cls = (!float128_is_any_nan(a) 1096 ? float_class_normal 1097 : float128_is_signaling_nan(a, status) 1098 ? float_class_snan 1099 : float_class_qnan); 1100 b_cls = (!float128_is_any_nan(b) 1101 ? float_class_normal 1102 : float128_is_signaling_nan(b, status) 1103 ? float_class_snan 1104 : float_class_qnan); 1105 1106 if (is_snan(a_cls) || is_snan(b_cls)) { 1107 float_raise(float_flag_invalid, status); 1108 } 1109 1110 if (status->default_nan_mode) { 1111 return float128_default_nan(status); 1112 } 1113 1114 if (lt128(a.high << 1, a.low, b.high << 1, b.low)) { 1115 aIsLargerSignificand = 0; 1116 } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) { 1117 aIsLargerSignificand = 1; 1118 } else { 1119 aIsLargerSignificand = (a.high < b.high) ? 1 : 0; 1120 } 1121 1122 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 1123 if (is_snan(b_cls)) { 1124 return float128_silence_nan(b, status); 1125 } 1126 return b; 1127 } else { 1128 if (is_snan(a_cls)) { 1129 return float128_silence_nan(a, status); 1130 } 1131 return a; 1132 } 1133} 1134