1/* 2 * QEMU float support 3 * 4 * The code in this source file is derived from release 2a of the SoftFloat 5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and 6 * some later contributions) are provided under that license, as detailed below. 7 * It has subsequently been modified by contributors to the QEMU Project, 8 * so some portions are provided under: 9 * the SoftFloat-2a license 10 * the BSD license 11 * GPL-v2-or-later 12 * 13 * Any future contributions to this file after December 1st 2014 will be 14 * taken to be licensed under the Softfloat-2a license unless specifically 15 * indicated otherwise. 16 */ 17 18/* 19=============================================================================== 20This C source fragment is part of the SoftFloat IEC/IEEE Floating-point 21Arithmetic Package, Release 2a. 22 23Written by John R. Hauser. This work was made possible in part by the 24International Computer Science Institute, located at Suite 600, 1947 Center 25Street, Berkeley, California 94704. Funding was partially provided by the 26National Science Foundation under grant MIP-9311980. The original version 27of this code was written as part of a project to build a fixed-point vector 28processor in collaboration with the University of California at Berkeley, 29overseen by Profs. Nelson Morgan and John Wawrzynek. More information 30is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ 31arithmetic/SoftFloat.html'. 32 33THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 34has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 35TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 36PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 37AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 38 39Derivative works are acceptable, even for commercial purposes, so long as 40(1) they include prominent notice that the work is derivative, and (2) they 41include prominent notice akin to these four paragraphs for those parts of 42this code that are retained. 43 44=============================================================================== 45*/ 46 47/* BSD licensing: 48 * Copyright (c) 2006, Fabrice Bellard 49 * All rights reserved. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions are met: 53 * 54 * 1. Redistributions of source code must retain the above copyright notice, 55 * this list of conditions and the following disclaimer. 56 * 57 * 2. Redistributions in binary form must reproduce the above copyright notice, 58 * this list of conditions and the following disclaimer in the documentation 59 * and/or other materials provided with the distribution. 60 * 61 * 3. Neither the name of the copyright holder nor the names of its contributors 62 * may be used to endorse or promote products derived from this software without 63 * specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 75 * THE POSSIBILITY OF SUCH DAMAGE. 76 */ 77 78/* Portions of this work are licensed under the terms of the GNU GPL, 79 * version 2 or later. See the COPYING file in the top-level directory. 80 */ 81 82/* 83 * Define whether architecture deviates from IEEE in not supporting 84 * signaling NaNs (so all NaNs are treated as quiet). 85 */ 86static inline bool no_signaling_nans(float_status *status) 87{ 88#if defined(TARGET_XTENSA) 89 return status->no_signaling_nans; 90#else 91 return false; 92#endif 93} 94 95/* Define how the architecture discriminates signaling NaNs. 96 * This done with the most significant bit of the fraction. 97 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 98 * the msb must be zero. MIPS is (so far) unique in supporting both the 99 * 2008 revision and backward compatibility with their original choice. 100 * Thus for MIPS we must make the choice at runtime. 101 */ 102static inline bool snan_bit_is_one(float_status *status) 103{ 104#if defined(TARGET_MIPS) 105 return status->snan_bit_is_one; 106#elif defined(TARGET_HPPA) || defined(TARGET_SH4) 107 return 1; 108#else 109 return 0; 110#endif 111} 112 113/*---------------------------------------------------------------------------- 114| For the deconstructed floating-point with fraction FRAC, return true 115| if the fraction represents a signalling NaN; otherwise false. 116*----------------------------------------------------------------------------*/ 117 118static bool parts_is_snan_frac(uint64_t frac, float_status *status) 119{ 120 if (no_signaling_nans(status)) { 121 return false; 122 } else { 123 bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); 124 return msb == snan_bit_is_one(status); 125 } 126} 127 128/*---------------------------------------------------------------------------- 129| The pattern for a default generated deconstructed floating-point NaN. 130*----------------------------------------------------------------------------*/ 131 132static FloatParts parts_default_nan(float_status *status) 133{ 134 bool sign = 0; 135 uint64_t frac; 136 137#if defined(TARGET_SPARC) || defined(TARGET_M68K) 138 /* !snan_bit_is_one, set all bits */ 139 frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; 140#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ 141 || defined(TARGET_MICROBLAZE) 142 /* !snan_bit_is_one, set sign and msb */ 143 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); 144 sign = 1; 145#elif defined(TARGET_HPPA) 146 /* snan_bit_is_one, set msb-1. */ 147 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); 148#elif defined(TARGET_HEXAGON) 149 sign = 1; 150 frac = ~0ULL; 151#else 152 /* 153 * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, 154 * S390, SH4, TriCore, and Xtensa. Our other supported targets, 155 * CRIS, Nios2, and Tile, do not have floating-point. 156 */ 157 if (snan_bit_is_one(status)) { 158 /* set all bits other than msb */ 159 frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; 160 } else { 161 /* set msb */ 162 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); 163 } 164#endif 165 166 return (FloatParts) { 167 .cls = float_class_qnan, 168 .sign = sign, 169 .exp = INT_MAX, 170 .frac = frac 171 }; 172} 173 174/*---------------------------------------------------------------------------- 175| Returns a quiet NaN from a signalling NaN for the deconstructed 176| floating-point parts. 177*----------------------------------------------------------------------------*/ 178 179static FloatParts parts_silence_nan(FloatParts a, float_status *status) 180{ 181 g_assert(!no_signaling_nans(status)); 182#if defined(TARGET_HPPA) 183 a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); 184 a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); 185#else 186 if (snan_bit_is_one(status)) { 187 return parts_default_nan(status); 188 } else { 189 a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); 190 } 191#endif 192 a.cls = float_class_qnan; 193 return a; 194} 195 196/*---------------------------------------------------------------------------- 197| The pattern for a default generated extended double-precision NaN. 198*----------------------------------------------------------------------------*/ 199floatx80 floatx80_default_nan(float_status *status) 200{ 201 floatx80 r; 202 203 /* None of the targets that have snan_bit_is_one use floatx80. */ 204 assert(!snan_bit_is_one(status)); 205#if defined(TARGET_M68K) 206 r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); 207 r.high = 0x7FFF; 208#else 209 /* X86 */ 210 r.low = UINT64_C(0xC000000000000000); 211 r.high = 0xFFFF; 212#endif 213 return r; 214} 215 216/*---------------------------------------------------------------------------- 217| The pattern for a default generated extended double-precision inf. 218*----------------------------------------------------------------------------*/ 219 220#define floatx80_infinity_high 0x7FFF 221#if defined(TARGET_M68K) 222#define floatx80_infinity_low UINT64_C(0x0000000000000000) 223#else 224#define floatx80_infinity_low UINT64_C(0x8000000000000000) 225#endif 226 227const floatx80 floatx80_infinity 228 = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); 229 230/*---------------------------------------------------------------------------- 231| Raises the exceptions specified by `flags'. Floating-point traps can be 232| defined here if desired. It is currently not possible for such a trap 233| to substitute a result value. If traps are not implemented, this routine 234| should be simply `float_exception_flags |= flags;'. 235*----------------------------------------------------------------------------*/ 236 237void float_raise(uint8_t flags, float_status *status) 238{ 239 status->float_exception_flags |= flags; 240} 241 242/*---------------------------------------------------------------------------- 243| Internal canonical NaN format. 244*----------------------------------------------------------------------------*/ 245typedef struct { 246 bool sign; 247 uint64_t high, low; 248} commonNaNT; 249 250/*---------------------------------------------------------------------------- 251| Returns 1 if the half-precision floating-point value `a' is a quiet 252| NaN; otherwise returns 0. 253*----------------------------------------------------------------------------*/ 254 255bool float16_is_quiet_nan(float16 a_, float_status *status) 256{ 257 if (no_signaling_nans(status)) { 258 return float16_is_any_nan(a_); 259 } else { 260 uint16_t a = float16_val(a_); 261 if (snan_bit_is_one(status)) { 262 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 263 } else { 264 265 return ((a >> 9) & 0x3F) == 0x3F; 266 } 267 } 268} 269 270/*---------------------------------------------------------------------------- 271| Returns 1 if the bfloat16 value `a' is a quiet 272| NaN; otherwise returns 0. 273*----------------------------------------------------------------------------*/ 274 275bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status) 276{ 277 if (no_signaling_nans(status)) { 278 return bfloat16_is_any_nan(a_); 279 } else { 280 uint16_t a = a_; 281 if (snan_bit_is_one(status)) { 282 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); 283 } else { 284 return ((a >> 6) & 0x1FF) == 0x1FF; 285 } 286 } 287} 288 289/*---------------------------------------------------------------------------- 290| Returns 1 if the half-precision floating-point value `a' is a signaling 291| NaN; otherwise returns 0. 292*----------------------------------------------------------------------------*/ 293 294bool float16_is_signaling_nan(float16 a_, float_status *status) 295{ 296 if (no_signaling_nans(status)) { 297 return 0; 298 } else { 299 uint16_t a = float16_val(a_); 300 if (snan_bit_is_one(status)) { 301 return ((a >> 9) & 0x3F) == 0x3F; 302 } else { 303 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 304 } 305 } 306} 307 308/*---------------------------------------------------------------------------- 309| Returns 1 if the bfloat16 value `a' is a signaling 310| NaN; otherwise returns 0. 311*----------------------------------------------------------------------------*/ 312 313bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status) 314{ 315 if (no_signaling_nans(status)) { 316 return 0; 317 } else { 318 uint16_t a = a_; 319 if (snan_bit_is_one(status)) { 320 return ((a >> 6) & 0x1FF) == 0x1FF; 321 } else { 322 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); 323 } 324 } 325} 326 327/*---------------------------------------------------------------------------- 328| Returns 1 if the single-precision floating-point value `a' is a quiet 329| NaN; otherwise returns 0. 330*----------------------------------------------------------------------------*/ 331 332bool float32_is_quiet_nan(float32 a_, float_status *status) 333{ 334 if (no_signaling_nans(status)) { 335 return float32_is_any_nan(a_); 336 } else { 337 uint32_t a = float32_val(a_); 338 if (snan_bit_is_one(status)) { 339 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 340 } else { 341 return ((uint32_t)(a << 1) >= 0xFF800000); 342 } 343 } 344} 345 346/*---------------------------------------------------------------------------- 347| Returns 1 if the single-precision floating-point value `a' is a signaling 348| NaN; otherwise returns 0. 349*----------------------------------------------------------------------------*/ 350 351bool float32_is_signaling_nan(float32 a_, float_status *status) 352{ 353 if (no_signaling_nans(status)) { 354 return 0; 355 } else { 356 uint32_t a = float32_val(a_); 357 if (snan_bit_is_one(status)) { 358 return ((uint32_t)(a << 1) >= 0xFF800000); 359 } else { 360 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 361 } 362 } 363} 364 365/*---------------------------------------------------------------------------- 366| Returns the result of converting the single-precision floating-point NaN 367| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid 368| exception is raised. 369*----------------------------------------------------------------------------*/ 370 371static commonNaNT float32ToCommonNaN(float32 a, float_status *status) 372{ 373 commonNaNT z; 374 375 if (float32_is_signaling_nan(a, status)) { 376 float_raise(float_flag_invalid, status); 377 } 378 z.sign = float32_val(a) >> 31; 379 z.low = 0; 380 z.high = ((uint64_t)float32_val(a)) << 41; 381 return z; 382} 383 384/*---------------------------------------------------------------------------- 385| Returns the result of converting the canonical NaN `a' to the single- 386| precision floating-point format. 387*----------------------------------------------------------------------------*/ 388 389static float32 commonNaNToFloat32(commonNaNT a, float_status *status) 390{ 391 uint32_t mantissa = a.high >> 41; 392 393 if (status->default_nan_mode) { 394 return float32_default_nan(status); 395 } 396 397 if (mantissa) { 398 return make_float32( 399 (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41)); 400 } else { 401 return float32_default_nan(status); 402 } 403} 404 405/*---------------------------------------------------------------------------- 406| Select which NaN to propagate for a two-input operation. 407| IEEE754 doesn't specify all the details of this, so the 408| algorithm is target-specific. 409| The routine is passed various bits of information about the 410| two NaNs and should return 0 to select NaN a and 1 for NaN b. 411| Note that signalling NaNs are always squashed to quiet NaNs 412| by the caller, by calling floatXX_silence_nan() before 413| returning them. 414| 415| aIsLargerSignificand is only valid if both a and b are NaNs 416| of some kind, and is true if a has the larger significand, 417| or if both a and b have the same significand but a is 418| positive but b is negative. It is only needed for the x87 419| tie-break rule. 420*----------------------------------------------------------------------------*/ 421 422static int pickNaN(FloatClass a_cls, FloatClass b_cls, 423 bool aIsLargerSignificand, float_status *status) 424{ 425#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) 426 /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take 427 * the first of: 428 * 1. A if it is signaling 429 * 2. B if it is signaling 430 * 3. A (quiet) 431 * 4. B (quiet) 432 * A signaling NaN is always quietened before returning it. 433 */ 434 /* According to MIPS specifications, if one of the two operands is 435 * a sNaN, a new qNaN has to be generated. This is done in 436 * floatXX_silence_nan(). For qNaN inputs the specifications 437 * says: "When possible, this QNaN result is one of the operand QNaN 438 * values." In practice it seems that most implementations choose 439 * the first operand if both operands are qNaN. In short this gives 440 * the following rules: 441 * 1. A if it is signaling 442 * 2. B if it is signaling 443 * 3. A (quiet) 444 * 4. B (quiet) 445 * A signaling NaN is always silenced before returning it. 446 */ 447 if (is_snan(a_cls)) { 448 return 0; 449 } else if (is_snan(b_cls)) { 450 return 1; 451 } else if (is_qnan(a_cls)) { 452 return 0; 453 } else { 454 return 1; 455 } 456#elif defined(TARGET_PPC) || defined(TARGET_M68K) 457 /* PowerPC propagation rules: 458 * 1. A if it sNaN or qNaN 459 * 2. B if it sNaN or qNaN 460 * A signaling NaN is always silenced before returning it. 461 */ 462 /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL 463 * 3.4 FLOATING-POINT INSTRUCTION DETAILS 464 * If either operand, but not both operands, of an operation is a 465 * nonsignaling NaN, then that NaN is returned as the result. If both 466 * operands are nonsignaling NaNs, then the destination operand 467 * nonsignaling NaN is returned as the result. 468 * If either operand to an operation is a signaling NaN (SNaN), then the 469 * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit 470 * is set in the FPCR ENABLE byte, then the exception is taken and the 471 * destination is not modified. If the SNaN exception enable bit is not 472 * set, setting the SNaN bit in the operand to a one converts the SNaN to 473 * a nonsignaling NaN. The operation then continues as described in the 474 * preceding paragraph for nonsignaling NaNs. 475 */ 476 if (is_nan(a_cls)) { 477 return 0; 478 } else { 479 return 1; 480 } 481#elif defined(TARGET_XTENSA) 482 /* 483 * Xtensa has two NaN propagation modes. 484 * Which one is active is controlled by float_status::use_first_nan. 485 */ 486 if (status->use_first_nan) { 487 if (is_nan(a_cls)) { 488 return 0; 489 } else { 490 return 1; 491 } 492 } else { 493 if (is_nan(b_cls)) { 494 return 1; 495 } else { 496 return 0; 497 } 498 } 499#else 500 /* This implements x87 NaN propagation rules: 501 * SNaN + QNaN => return the QNaN 502 * two SNaNs => return the one with the larger significand, silenced 503 * two QNaNs => return the one with the larger significand 504 * SNaN and a non-NaN => return the SNaN, silenced 505 * QNaN and a non-NaN => return the QNaN 506 * 507 * If we get down to comparing significands and they are the same, 508 * return the NaN with the positive sign bit (if any). 509 */ 510 if (is_snan(a_cls)) { 511 if (is_snan(b_cls)) { 512 return aIsLargerSignificand ? 0 : 1; 513 } 514 return is_qnan(b_cls) ? 1 : 0; 515 } else if (is_qnan(a_cls)) { 516 if (is_snan(b_cls) || !is_qnan(b_cls)) { 517 return 0; 518 } else { 519 return aIsLargerSignificand ? 0 : 1; 520 } 521 } else { 522 return 1; 523 } 524#endif 525} 526 527/*---------------------------------------------------------------------------- 528| Select which NaN to propagate for a three-input operation. 529| For the moment we assume that no CPU needs the 'larger significand' 530| information. 531| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN 532*----------------------------------------------------------------------------*/ 533static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, 534 bool infzero, float_status *status) 535{ 536#if defined(TARGET_ARM) 537 /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns 538 * the default NaN 539 */ 540 if (infzero && is_qnan(c_cls)) { 541 float_raise(float_flag_invalid, status); 542 return 3; 543 } 544 545 /* This looks different from the ARM ARM pseudocode, because the ARM ARM 546 * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. 547 */ 548 if (is_snan(c_cls)) { 549 return 2; 550 } else if (is_snan(a_cls)) { 551 return 0; 552 } else if (is_snan(b_cls)) { 553 return 1; 554 } else if (is_qnan(c_cls)) { 555 return 2; 556 } else if (is_qnan(a_cls)) { 557 return 0; 558 } else { 559 return 1; 560 } 561#elif defined(TARGET_MIPS) 562 if (snan_bit_is_one(status)) { 563 /* 564 * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) 565 * case sets InvalidOp and returns the default NaN 566 */ 567 if (infzero) { 568 float_raise(float_flag_invalid, status); 569 return 3; 570 } 571 /* Prefer sNaN over qNaN, in the a, b, c order. */ 572 if (is_snan(a_cls)) { 573 return 0; 574 } else if (is_snan(b_cls)) { 575 return 1; 576 } else if (is_snan(c_cls)) { 577 return 2; 578 } else if (is_qnan(a_cls)) { 579 return 0; 580 } else if (is_qnan(b_cls)) { 581 return 1; 582 } else { 583 return 2; 584 } 585 } else { 586 /* 587 * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) 588 * case sets InvalidOp and returns the input value 'c' 589 */ 590 if (infzero) { 591 float_raise(float_flag_invalid, status); 592 return 2; 593 } 594 /* Prefer sNaN over qNaN, in the c, a, b order. */ 595 if (is_snan(c_cls)) { 596 return 2; 597 } else if (is_snan(a_cls)) { 598 return 0; 599 } else if (is_snan(b_cls)) { 600 return 1; 601 } else if (is_qnan(c_cls)) { 602 return 2; 603 } else if (is_qnan(a_cls)) { 604 return 0; 605 } else { 606 return 1; 607 } 608 } 609#elif defined(TARGET_PPC) 610 /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer 611 * to return an input NaN if we have one (ie c) rather than generating 612 * a default NaN 613 */ 614 if (infzero) { 615 float_raise(float_flag_invalid, status); 616 return 2; 617 } 618 619 /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; 620 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB 621 */ 622 if (is_nan(a_cls)) { 623 return 0; 624 } else if (is_nan(c_cls)) { 625 return 2; 626 } else { 627 return 1; 628 } 629#elif defined(TARGET_RISCV) 630 /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ 631 if (infzero) { 632 float_raise(float_flag_invalid, status); 633 } 634 return 3; /* default NaN */ 635#elif defined(TARGET_XTENSA) 636 /* 637 * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns 638 * an input NaN if we have one (ie c). 639 */ 640 if (infzero) { 641 float_raise(float_flag_invalid, status); 642 return 2; 643 } 644 if (status->use_first_nan) { 645 if (is_nan(a_cls)) { 646 return 0; 647 } else if (is_nan(b_cls)) { 648 return 1; 649 } else { 650 return 2; 651 } 652 } else { 653 if (is_nan(c_cls)) { 654 return 2; 655 } else if (is_nan(b_cls)) { 656 return 1; 657 } else { 658 return 0; 659 } 660 } 661#else 662 /* A default implementation: prefer a to b to c. 663 * This is unlikely to actually match any real implementation. 664 */ 665 if (is_nan(a_cls)) { 666 return 0; 667 } else if (is_nan(b_cls)) { 668 return 1; 669 } else { 670 return 2; 671 } 672#endif 673} 674 675/*---------------------------------------------------------------------------- 676| Takes two single-precision floating-point values `a' and `b', one of which 677| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a 678| signaling NaN, the invalid exception is raised. 679*----------------------------------------------------------------------------*/ 680 681static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) 682{ 683 bool aIsLargerSignificand; 684 uint32_t av, bv; 685 FloatClass a_cls, b_cls; 686 687 /* This is not complete, but is good enough for pickNaN. */ 688 a_cls = (!float32_is_any_nan(a) 689 ? float_class_normal 690 : float32_is_signaling_nan(a, status) 691 ? float_class_snan 692 : float_class_qnan); 693 b_cls = (!float32_is_any_nan(b) 694 ? float_class_normal 695 : float32_is_signaling_nan(b, status) 696 ? float_class_snan 697 : float_class_qnan); 698 699 av = float32_val(a); 700 bv = float32_val(b); 701 702 if (is_snan(a_cls) || is_snan(b_cls)) { 703 float_raise(float_flag_invalid, status); 704 } 705 706 if (status->default_nan_mode) { 707 return float32_default_nan(status); 708 } 709 710 if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) { 711 aIsLargerSignificand = 0; 712 } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) { 713 aIsLargerSignificand = 1; 714 } else { 715 aIsLargerSignificand = (av < bv) ? 1 : 0; 716 } 717 718 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 719 if (is_snan(b_cls)) { 720 return float32_silence_nan(b, status); 721 } 722 return b; 723 } else { 724 if (is_snan(a_cls)) { 725 return float32_silence_nan(a, status); 726 } 727 return a; 728 } 729} 730 731/*---------------------------------------------------------------------------- 732| Returns 1 if the double-precision floating-point value `a' is a quiet 733| NaN; otherwise returns 0. 734*----------------------------------------------------------------------------*/ 735 736bool float64_is_quiet_nan(float64 a_, float_status *status) 737{ 738 if (no_signaling_nans(status)) { 739 return float64_is_any_nan(a_); 740 } else { 741 uint64_t a = float64_val(a_); 742 if (snan_bit_is_one(status)) { 743 return (((a >> 51) & 0xFFF) == 0xFFE) 744 && (a & 0x0007FFFFFFFFFFFFULL); 745 } else { 746 return ((a << 1) >= 0xFFF0000000000000ULL); 747 } 748 } 749} 750 751/*---------------------------------------------------------------------------- 752| Returns 1 if the double-precision floating-point value `a' is a signaling 753| NaN; otherwise returns 0. 754*----------------------------------------------------------------------------*/ 755 756bool float64_is_signaling_nan(float64 a_, float_status *status) 757{ 758 if (no_signaling_nans(status)) { 759 return 0; 760 } else { 761 uint64_t a = float64_val(a_); 762 if (snan_bit_is_one(status)) { 763 return ((a << 1) >= 0xFFF0000000000000ULL); 764 } else { 765 return (((a >> 51) & 0xFFF) == 0xFFE) 766 && (a & UINT64_C(0x0007FFFFFFFFFFFF)); 767 } 768 } 769} 770 771/*---------------------------------------------------------------------------- 772| Returns the result of converting the double-precision floating-point NaN 773| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid 774| exception is raised. 775*----------------------------------------------------------------------------*/ 776 777static commonNaNT float64ToCommonNaN(float64 a, float_status *status) 778{ 779 commonNaNT z; 780 781 if (float64_is_signaling_nan(a, status)) { 782 float_raise(float_flag_invalid, status); 783 } 784 z.sign = float64_val(a) >> 63; 785 z.low = 0; 786 z.high = float64_val(a) << 12; 787 return z; 788} 789 790/*---------------------------------------------------------------------------- 791| Returns the result of converting the canonical NaN `a' to the double- 792| precision floating-point format. 793*----------------------------------------------------------------------------*/ 794 795static float64 commonNaNToFloat64(commonNaNT a, float_status *status) 796{ 797 uint64_t mantissa = a.high >> 12; 798 799 if (status->default_nan_mode) { 800 return float64_default_nan(status); 801 } 802 803 if (mantissa) { 804 return make_float64( 805 (((uint64_t) a.sign) << 63) 806 | UINT64_C(0x7FF0000000000000) 807 | (a.high >> 12)); 808 } else { 809 return float64_default_nan(status); 810 } 811} 812 813/*---------------------------------------------------------------------------- 814| Takes two double-precision floating-point values `a' and `b', one of which 815| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a 816| signaling NaN, the invalid exception is raised. 817*----------------------------------------------------------------------------*/ 818 819static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) 820{ 821 bool aIsLargerSignificand; 822 uint64_t av, bv; 823 FloatClass a_cls, b_cls; 824 825 /* This is not complete, but is good enough for pickNaN. */ 826 a_cls = (!float64_is_any_nan(a) 827 ? float_class_normal 828 : float64_is_signaling_nan(a, status) 829 ? float_class_snan 830 : float_class_qnan); 831 b_cls = (!float64_is_any_nan(b) 832 ? float_class_normal 833 : float64_is_signaling_nan(b, status) 834 ? float_class_snan 835 : float_class_qnan); 836 837 av = float64_val(a); 838 bv = float64_val(b); 839 840 if (is_snan(a_cls) || is_snan(b_cls)) { 841 float_raise(float_flag_invalid, status); 842 } 843 844 if (status->default_nan_mode) { 845 return float64_default_nan(status); 846 } 847 848 if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) { 849 aIsLargerSignificand = 0; 850 } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) { 851 aIsLargerSignificand = 1; 852 } else { 853 aIsLargerSignificand = (av < bv) ? 1 : 0; 854 } 855 856 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 857 if (is_snan(b_cls)) { 858 return float64_silence_nan(b, status); 859 } 860 return b; 861 } else { 862 if (is_snan(a_cls)) { 863 return float64_silence_nan(a, status); 864 } 865 return a; 866 } 867} 868 869/*---------------------------------------------------------------------------- 870| Returns 1 if the extended double-precision floating-point value `a' is a 871| quiet NaN; otherwise returns 0. This slightly differs from the same 872| function for other types as floatx80 has an explicit bit. 873*----------------------------------------------------------------------------*/ 874 875int floatx80_is_quiet_nan(floatx80 a, float_status *status) 876{ 877 if (no_signaling_nans(status)) { 878 return floatx80_is_any_nan(a); 879 } else { 880 if (snan_bit_is_one(status)) { 881 uint64_t aLow; 882 883 aLow = a.low & ~0x4000000000000000ULL; 884 return ((a.high & 0x7FFF) == 0x7FFF) 885 && (aLow << 1) 886 && (a.low == aLow); 887 } else { 888 return ((a.high & 0x7FFF) == 0x7FFF) 889 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); 890 } 891 } 892} 893 894/*---------------------------------------------------------------------------- 895| Returns 1 if the extended double-precision floating-point value `a' is a 896| signaling NaN; otherwise returns 0. This slightly differs from the same 897| function for other types as floatx80 has an explicit bit. 898*----------------------------------------------------------------------------*/ 899 900int floatx80_is_signaling_nan(floatx80 a, float_status *status) 901{ 902 if (no_signaling_nans(status)) { 903 return 0; 904 } else { 905 if (snan_bit_is_one(status)) { 906 return ((a.high & 0x7FFF) == 0x7FFF) 907 && ((a.low << 1) >= 0x8000000000000000ULL); 908 } else { 909 uint64_t aLow; 910 911 aLow = a.low & ~UINT64_C(0x4000000000000000); 912 return ((a.high & 0x7FFF) == 0x7FFF) 913 && (uint64_t)(aLow << 1) 914 && (a.low == aLow); 915 } 916 } 917} 918 919/*---------------------------------------------------------------------------- 920| Returns a quiet NaN from a signalling NaN for the extended double-precision 921| floating point value `a'. 922*----------------------------------------------------------------------------*/ 923 924floatx80 floatx80_silence_nan(floatx80 a, float_status *status) 925{ 926 /* None of the targets that have snan_bit_is_one use floatx80. */ 927 assert(!snan_bit_is_one(status)); 928 a.low |= UINT64_C(0xC000000000000000); 929 return a; 930} 931 932/*---------------------------------------------------------------------------- 933| Returns the result of converting the extended double-precision floating- 934| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the 935| invalid exception is raised. 936*----------------------------------------------------------------------------*/ 937 938static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status) 939{ 940 floatx80 dflt; 941 commonNaNT z; 942 943 if (floatx80_is_signaling_nan(a, status)) { 944 float_raise(float_flag_invalid, status); 945 } 946 if (a.low >> 63) { 947 z.sign = a.high >> 15; 948 z.low = 0; 949 z.high = a.low << 1; 950 } else { 951 dflt = floatx80_default_nan(status); 952 z.sign = dflt.high >> 15; 953 z.low = 0; 954 z.high = dflt.low << 1; 955 } 956 return z; 957} 958 959/*---------------------------------------------------------------------------- 960| Returns the result of converting the canonical NaN `a' to the extended 961| double-precision floating-point format. 962*----------------------------------------------------------------------------*/ 963 964static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status) 965{ 966 floatx80 z; 967 968 if (status->default_nan_mode) { 969 return floatx80_default_nan(status); 970 } 971 972 if (a.high >> 1) { 973 z.low = UINT64_C(0x8000000000000000) | a.high >> 1; 974 z.high = (((uint16_t)a.sign) << 15) | 0x7FFF; 975 } else { 976 z = floatx80_default_nan(status); 977 } 978 return z; 979} 980 981/*---------------------------------------------------------------------------- 982| Takes two extended double-precision floating-point values `a' and `b', one 983| of which is a NaN, and returns the appropriate NaN result. If either `a' or 984| `b' is a signaling NaN, the invalid exception is raised. 985*----------------------------------------------------------------------------*/ 986 987floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) 988{ 989 bool aIsLargerSignificand; 990 FloatClass a_cls, b_cls; 991 992 /* This is not complete, but is good enough for pickNaN. */ 993 a_cls = (!floatx80_is_any_nan(a) 994 ? float_class_normal 995 : floatx80_is_signaling_nan(a, status) 996 ? float_class_snan 997 : float_class_qnan); 998 b_cls = (!floatx80_is_any_nan(b) 999 ? float_class_normal 1000 : floatx80_is_signaling_nan(b, status) 1001 ? float_class_snan 1002 : float_class_qnan); 1003 1004 if (is_snan(a_cls) || is_snan(b_cls)) { 1005 float_raise(float_flag_invalid, status); 1006 } 1007 1008 if (status->default_nan_mode) { 1009 return floatx80_default_nan(status); 1010 } 1011 1012 if (a.low < b.low) { 1013 aIsLargerSignificand = 0; 1014 } else if (b.low < a.low) { 1015 aIsLargerSignificand = 1; 1016 } else { 1017 aIsLargerSignificand = (a.high < b.high) ? 1 : 0; 1018 } 1019 1020 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 1021 if (is_snan(b_cls)) { 1022 return floatx80_silence_nan(b, status); 1023 } 1024 return b; 1025 } else { 1026 if (is_snan(a_cls)) { 1027 return floatx80_silence_nan(a, status); 1028 } 1029 return a; 1030 } 1031} 1032 1033/*---------------------------------------------------------------------------- 1034| Returns 1 if the quadruple-precision floating-point value `a' is a quiet 1035| NaN; otherwise returns 0. 1036*----------------------------------------------------------------------------*/ 1037 1038bool float128_is_quiet_nan(float128 a, float_status *status) 1039{ 1040 if (no_signaling_nans(status)) { 1041 return float128_is_any_nan(a); 1042 } else { 1043 if (snan_bit_is_one(status)) { 1044 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 1045 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); 1046 } else { 1047 return ((a.high << 1) >= 0xFFFF000000000000ULL) 1048 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 1049 } 1050 } 1051} 1052 1053/*---------------------------------------------------------------------------- 1054| Returns 1 if the quadruple-precision floating-point value `a' is a 1055| signaling NaN; otherwise returns 0. 1056*----------------------------------------------------------------------------*/ 1057 1058bool float128_is_signaling_nan(float128 a, float_status *status) 1059{ 1060 if (no_signaling_nans(status)) { 1061 return 0; 1062 } else { 1063 if (snan_bit_is_one(status)) { 1064 return ((a.high << 1) >= 0xFFFF000000000000ULL) 1065 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 1066 } else { 1067 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 1068 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); 1069 } 1070 } 1071} 1072 1073/*---------------------------------------------------------------------------- 1074| Returns a quiet NaN from a signalling NaN for the quadruple-precision 1075| floating point value `a'. 1076*----------------------------------------------------------------------------*/ 1077 1078float128 float128_silence_nan(float128 a, float_status *status) 1079{ 1080 if (no_signaling_nans(status)) { 1081 g_assert_not_reached(); 1082 } else { 1083 if (snan_bit_is_one(status)) { 1084 return float128_default_nan(status); 1085 } else { 1086 a.high |= UINT64_C(0x0000800000000000); 1087 return a; 1088 } 1089 } 1090} 1091 1092/*---------------------------------------------------------------------------- 1093| Returns the result of converting the quadruple-precision floating-point NaN 1094| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid 1095| exception is raised. 1096*----------------------------------------------------------------------------*/ 1097 1098static commonNaNT float128ToCommonNaN(float128 a, float_status *status) 1099{ 1100 commonNaNT z; 1101 1102 if (float128_is_signaling_nan(a, status)) { 1103 float_raise(float_flag_invalid, status); 1104 } 1105 z.sign = a.high >> 63; 1106 shortShift128Left(a.high, a.low, 16, &z.high, &z.low); 1107 return z; 1108} 1109 1110/*---------------------------------------------------------------------------- 1111| Returns the result of converting the canonical NaN `a' to the quadruple- 1112| precision floating-point format. 1113*----------------------------------------------------------------------------*/ 1114 1115static float128 commonNaNToFloat128(commonNaNT a, float_status *status) 1116{ 1117 float128 z; 1118 1119 if (status->default_nan_mode) { 1120 return float128_default_nan(status); 1121 } 1122 1123 shift128Right(a.high, a.low, 16, &z.high, &z.low); 1124 z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000); 1125 return z; 1126} 1127 1128/*---------------------------------------------------------------------------- 1129| Takes two quadruple-precision floating-point values `a' and `b', one of 1130| which is a NaN, and returns the appropriate NaN result. If either `a' or 1131| `b' is a signaling NaN, the invalid exception is raised. 1132*----------------------------------------------------------------------------*/ 1133 1134static float128 propagateFloat128NaN(float128 a, float128 b, 1135 float_status *status) 1136{ 1137 bool aIsLargerSignificand; 1138 FloatClass a_cls, b_cls; 1139 1140 /* This is not complete, but is good enough for pickNaN. */ 1141 a_cls = (!float128_is_any_nan(a) 1142 ? float_class_normal 1143 : float128_is_signaling_nan(a, status) 1144 ? float_class_snan 1145 : float_class_qnan); 1146 b_cls = (!float128_is_any_nan(b) 1147 ? float_class_normal 1148 : float128_is_signaling_nan(b, status) 1149 ? float_class_snan 1150 : float_class_qnan); 1151 1152 if (is_snan(a_cls) || is_snan(b_cls)) { 1153 float_raise(float_flag_invalid, status); 1154 } 1155 1156 if (status->default_nan_mode) { 1157 return float128_default_nan(status); 1158 } 1159 1160 if (lt128(a.high << 1, a.low, b.high << 1, b.low)) { 1161 aIsLargerSignificand = 0; 1162 } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) { 1163 aIsLargerSignificand = 1; 1164 } else { 1165 aIsLargerSignificand = (a.high < b.high) ? 1 : 0; 1166 } 1167 1168 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 1169 if (is_snan(b_cls)) { 1170 return float128_silence_nan(b, status); 1171 } 1172 return b; 1173 } else { 1174 if (is_snan(a_cls)) { 1175 return float128_silence_nan(a, status); 1176 } 1177 return a; 1178 } 1179} 1180