1/* 2 * QEMU float support 3 * 4 * The code in this source file is derived from release 2a of the SoftFloat 5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and 6 * some later contributions) are provided under that license, as detailed below. 7 * It has subsequently been modified by contributors to the QEMU Project, 8 * so some portions are provided under: 9 * the SoftFloat-2a license 10 * the BSD license 11 * GPL-v2-or-later 12 * 13 * Any future contributions to this file after December 1st 2014 will be 14 * taken to be licensed under the Softfloat-2a license unless specifically 15 * indicated otherwise. 16 */ 17 18/* 19=============================================================================== 20This C source fragment is part of the SoftFloat IEC/IEEE Floating-point 21Arithmetic Package, Release 2a. 22 23Written by John R. Hauser. This work was made possible in part by the 24International Computer Science Institute, located at Suite 600, 1947 Center 25Street, Berkeley, California 94704. Funding was partially provided by the 26National Science Foundation under grant MIP-9311980. The original version 27of this code was written as part of a project to build a fixed-point vector 28processor in collaboration with the University of California at Berkeley, 29overseen by Profs. Nelson Morgan and John Wawrzynek. More information 30is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ 31arithmetic/SoftFloat.html'. 32 33THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 34has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 35TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 36PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 37AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 38 39Derivative works are acceptable, even for commercial purposes, so long as 40(1) they include prominent notice that the work is derivative, and (2) they 41include prominent notice akin to these four paragraphs for those parts of 42this code that are retained. 43 44=============================================================================== 45*/ 46 47/* BSD licensing: 48 * Copyright (c) 2006, Fabrice Bellard 49 * All rights reserved. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions are met: 53 * 54 * 1. Redistributions of source code must retain the above copyright notice, 55 * this list of conditions and the following disclaimer. 56 * 57 * 2. Redistributions in binary form must reproduce the above copyright notice, 58 * this list of conditions and the following disclaimer in the documentation 59 * and/or other materials provided with the distribution. 60 * 61 * 3. Neither the name of the copyright holder nor the names of its contributors 62 * may be used to endorse or promote products derived from this software without 63 * specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 75 * THE POSSIBILITY OF SUCH DAMAGE. 76 */ 77 78/* Portions of this work are licensed under the terms of the GNU GPL, 79 * version 2 or later. See the COPYING file in the top-level directory. 80 */ 81 82/* 83 * Define whether architecture deviates from IEEE in not supporting 84 * signaling NaNs (so all NaNs are treated as quiet). 85 */ 86static inline bool no_signaling_nans(float_status *status) 87{ 88#if defined(TARGET_XTENSA) 89 return status->no_signaling_nans; 90#else 91 return false; 92#endif 93} 94 95/* Define how the architecture discriminates signaling NaNs. 96 * This done with the most significant bit of the fraction. 97 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 98 * the msb must be zero. MIPS is (so far) unique in supporting both the 99 * 2008 revision and backward compatibility with their original choice. 100 * Thus for MIPS we must make the choice at runtime. 101 */ 102static inline bool snan_bit_is_one(float_status *status) 103{ 104#if defined(TARGET_MIPS) 105 return status->snan_bit_is_one; 106#elif defined(TARGET_HPPA) || defined(TARGET_SH4) 107 return 1; 108#else 109 return 0; 110#endif 111} 112 113/*---------------------------------------------------------------------------- 114| For the deconstructed floating-point with fraction FRAC, return true 115| if the fraction represents a signalling NaN; otherwise false. 116*----------------------------------------------------------------------------*/ 117 118static bool parts_is_snan_frac(uint64_t frac, float_status *status) 119{ 120 if (no_signaling_nans(status)) { 121 return false; 122 } else { 123 bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); 124 return msb == snan_bit_is_one(status); 125 } 126} 127 128/*---------------------------------------------------------------------------- 129| The pattern for a default generated deconstructed floating-point NaN. 130*----------------------------------------------------------------------------*/ 131 132static FloatParts parts_default_nan(float_status *status) 133{ 134 bool sign = 0; 135 uint64_t frac; 136 137#if defined(TARGET_SPARC) || defined(TARGET_M68K) 138 /* !snan_bit_is_one, set all bits */ 139 frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; 140#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ 141 || defined(TARGET_MICROBLAZE) 142 /* !snan_bit_is_one, set sign and msb */ 143 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); 144 sign = 1; 145#elif defined(TARGET_HPPA) 146 /* snan_bit_is_one, set msb-1. */ 147 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); 148#elif defined(TARGET_HEXAGON) 149 sign = 1; 150 frac = ~0ULL; 151#else 152 /* 153 * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, 154 * S390, SH4, TriCore, and Xtensa. Our other supported targets, 155 * CRIS, Nios2, and Tile, do not have floating-point. 156 */ 157 if (snan_bit_is_one(status)) { 158 /* set all bits other than msb */ 159 frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; 160 } else { 161 /* set msb */ 162 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); 163 } 164#endif 165 166 return (FloatParts) { 167 .cls = float_class_qnan, 168 .sign = sign, 169 .exp = INT_MAX, 170 .frac = frac 171 }; 172} 173 174/*---------------------------------------------------------------------------- 175| Returns a quiet NaN from a signalling NaN for the deconstructed 176| floating-point parts. 177*----------------------------------------------------------------------------*/ 178 179static FloatParts parts_silence_nan(FloatParts a, float_status *status) 180{ 181 g_assert(!no_signaling_nans(status)); 182#if defined(TARGET_HPPA) 183 a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); 184 a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); 185#else 186 if (snan_bit_is_one(status)) { 187 return parts_default_nan(status); 188 } else { 189 a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); 190 } 191#endif 192 a.cls = float_class_qnan; 193 return a; 194} 195 196/*---------------------------------------------------------------------------- 197| The pattern for a default generated extended double-precision NaN. 198*----------------------------------------------------------------------------*/ 199floatx80 floatx80_default_nan(float_status *status) 200{ 201 floatx80 r; 202 203 /* None of the targets that have snan_bit_is_one use floatx80. */ 204 assert(!snan_bit_is_one(status)); 205#if defined(TARGET_M68K) 206 r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); 207 r.high = 0x7FFF; 208#else 209 /* X86 */ 210 r.low = UINT64_C(0xC000000000000000); 211 r.high = 0xFFFF; 212#endif 213 return r; 214} 215 216/*---------------------------------------------------------------------------- 217| The pattern for a default generated extended double-precision inf. 218*----------------------------------------------------------------------------*/ 219 220#define floatx80_infinity_high 0x7FFF 221#if defined(TARGET_M68K) 222#define floatx80_infinity_low UINT64_C(0x0000000000000000) 223#else 224#define floatx80_infinity_low UINT64_C(0x8000000000000000) 225#endif 226 227const floatx80 floatx80_infinity 228 = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); 229 230/*---------------------------------------------------------------------------- 231| Raises the exceptions specified by `flags'. Floating-point traps can be 232| defined here if desired. It is currently not possible for such a trap 233| to substitute a result value. If traps are not implemented, this routine 234| should be simply `float_exception_flags |= flags;'. 235*----------------------------------------------------------------------------*/ 236 237void float_raise(uint8_t flags, float_status *status) 238{ 239 status->float_exception_flags |= flags; 240} 241 242/*---------------------------------------------------------------------------- 243| Internal canonical NaN format. 244*----------------------------------------------------------------------------*/ 245typedef struct { 246 bool sign; 247 uint64_t high, low; 248} commonNaNT; 249 250/*---------------------------------------------------------------------------- 251| Returns 1 if the half-precision floating-point value `a' is a quiet 252| NaN; otherwise returns 0. 253*----------------------------------------------------------------------------*/ 254 255bool float16_is_quiet_nan(float16 a_, float_status *status) 256{ 257 if (no_signaling_nans(status)) { 258 return float16_is_any_nan(a_); 259 } else { 260 uint16_t a = float16_val(a_); 261 if (snan_bit_is_one(status)) { 262 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 263 } else { 264 265 return ((a >> 9) & 0x3F) == 0x3F; 266 } 267 } 268} 269 270/*---------------------------------------------------------------------------- 271| Returns 1 if the bfloat16 value `a' is a quiet 272| NaN; otherwise returns 0. 273*----------------------------------------------------------------------------*/ 274 275bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status) 276{ 277 if (no_signaling_nans(status)) { 278 return bfloat16_is_any_nan(a_); 279 } else { 280 uint16_t a = a_; 281 if (snan_bit_is_one(status)) { 282 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); 283 } else { 284 return ((a >> 6) & 0x1FF) == 0x1FF; 285 } 286 } 287} 288 289/*---------------------------------------------------------------------------- 290| Returns 1 if the half-precision floating-point value `a' is a signaling 291| NaN; otherwise returns 0. 292*----------------------------------------------------------------------------*/ 293 294bool float16_is_signaling_nan(float16 a_, float_status *status) 295{ 296 if (no_signaling_nans(status)) { 297 return 0; 298 } else { 299 uint16_t a = float16_val(a_); 300 if (snan_bit_is_one(status)) { 301 return ((a >> 9) & 0x3F) == 0x3F; 302 } else { 303 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 304 } 305 } 306} 307 308/*---------------------------------------------------------------------------- 309| Returns 1 if the bfloat16 value `a' is a signaling 310| NaN; otherwise returns 0. 311*----------------------------------------------------------------------------*/ 312 313bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status) 314{ 315 if (no_signaling_nans(status)) { 316 return 0; 317 } else { 318 uint16_t a = a_; 319 if (snan_bit_is_one(status)) { 320 return ((a >> 6) & 0x1FF) == 0x1FF; 321 } else { 322 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); 323 } 324 } 325} 326 327/*---------------------------------------------------------------------------- 328| Returns 1 if the single-precision floating-point value `a' is a quiet 329| NaN; otherwise returns 0. 330*----------------------------------------------------------------------------*/ 331 332bool float32_is_quiet_nan(float32 a_, float_status *status) 333{ 334 if (no_signaling_nans(status)) { 335 return float32_is_any_nan(a_); 336 } else { 337 uint32_t a = float32_val(a_); 338 if (snan_bit_is_one(status)) { 339 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 340 } else { 341 return ((uint32_t)(a << 1) >= 0xFF800000); 342 } 343 } 344} 345 346/*---------------------------------------------------------------------------- 347| Returns 1 if the single-precision floating-point value `a' is a signaling 348| NaN; otherwise returns 0. 349*----------------------------------------------------------------------------*/ 350 351bool float32_is_signaling_nan(float32 a_, float_status *status) 352{ 353 if (no_signaling_nans(status)) { 354 return 0; 355 } else { 356 uint32_t a = float32_val(a_); 357 if (snan_bit_is_one(status)) { 358 return ((uint32_t)(a << 1) >= 0xFF800000); 359 } else { 360 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 361 } 362 } 363} 364 365/*---------------------------------------------------------------------------- 366| Returns the result of converting the single-precision floating-point NaN 367| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid 368| exception is raised. 369*----------------------------------------------------------------------------*/ 370 371static commonNaNT float32ToCommonNaN(float32 a, float_status *status) 372{ 373 commonNaNT z; 374 375 if (float32_is_signaling_nan(a, status)) { 376 float_raise(float_flag_invalid, status); 377 } 378 z.sign = float32_val(a) >> 31; 379 z.low = 0; 380 z.high = ((uint64_t)float32_val(a)) << 41; 381 return z; 382} 383 384/*---------------------------------------------------------------------------- 385| Returns the result of converting the canonical NaN `a' to the single- 386| precision floating-point format. 387*----------------------------------------------------------------------------*/ 388 389static float32 commonNaNToFloat32(commonNaNT a, float_status *status) 390{ 391 uint32_t mantissa = a.high >> 41; 392 393 if (status->default_nan_mode) { 394 return float32_default_nan(status); 395 } 396 397 if (mantissa) { 398 return make_float32( 399 (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41)); 400 } else { 401 return float32_default_nan(status); 402 } 403} 404 405/*---------------------------------------------------------------------------- 406| Select which NaN to propagate for a two-input operation. 407| IEEE754 doesn't specify all the details of this, so the 408| algorithm is target-specific. 409| The routine is passed various bits of information about the 410| two NaNs and should return 0 to select NaN a and 1 for NaN b. 411| Note that signalling NaNs are always squashed to quiet NaNs 412| by the caller, by calling floatXX_silence_nan() before 413| returning them. 414| 415| aIsLargerSignificand is only valid if both a and b are NaNs 416| of some kind, and is true if a has the larger significand, 417| or if both a and b have the same significand but a is 418| positive but b is negative. It is only needed for the x87 419| tie-break rule. 420*----------------------------------------------------------------------------*/ 421 422static int pickNaN(FloatClass a_cls, FloatClass b_cls, 423 bool aIsLargerSignificand, float_status *status) 424{ 425#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) 426 /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take 427 * the first of: 428 * 1. A if it is signaling 429 * 2. B if it is signaling 430 * 3. A (quiet) 431 * 4. B (quiet) 432 * A signaling NaN is always quietened before returning it. 433 */ 434 /* According to MIPS specifications, if one of the two operands is 435 * a sNaN, a new qNaN has to be generated. This is done in 436 * floatXX_silence_nan(). For qNaN inputs the specifications 437 * says: "When possible, this QNaN result is one of the operand QNaN 438 * values." In practice it seems that most implementations choose 439 * the first operand if both operands are qNaN. In short this gives 440 * the following rules: 441 * 1. A if it is signaling 442 * 2. B if it is signaling 443 * 3. A (quiet) 444 * 4. B (quiet) 445 * A signaling NaN is always silenced before returning it. 446 */ 447 if (is_snan(a_cls)) { 448 return 0; 449 } else if (is_snan(b_cls)) { 450 return 1; 451 } else if (is_qnan(a_cls)) { 452 return 0; 453 } else { 454 return 1; 455 } 456#elif defined(TARGET_PPC) || defined(TARGET_M68K) 457 /* PowerPC propagation rules: 458 * 1. A if it sNaN or qNaN 459 * 2. B if it sNaN or qNaN 460 * A signaling NaN is always silenced before returning it. 461 */ 462 /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL 463 * 3.4 FLOATING-POINT INSTRUCTION DETAILS 464 * If either operand, but not both operands, of an operation is a 465 * nonsignaling NaN, then that NaN is returned as the result. If both 466 * operands are nonsignaling NaNs, then the destination operand 467 * nonsignaling NaN is returned as the result. 468 * If either operand to an operation is a signaling NaN (SNaN), then the 469 * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit 470 * is set in the FPCR ENABLE byte, then the exception is taken and the 471 * destination is not modified. If the SNaN exception enable bit is not 472 * set, setting the SNaN bit in the operand to a one converts the SNaN to 473 * a nonsignaling NaN. The operation then continues as described in the 474 * preceding paragraph for nonsignaling NaNs. 475 */ 476 if (is_nan(a_cls)) { 477 return 0; 478 } else { 479 return 1; 480 } 481#elif defined(TARGET_XTENSA) 482 /* 483 * Xtensa has two NaN propagation modes. 484 * Which one is active is controlled by float_status::use_first_nan. 485 */ 486 if (status->use_first_nan) { 487 if (is_nan(a_cls)) { 488 return 0; 489 } else { 490 return 1; 491 } 492 } else { 493 if (is_nan(b_cls)) { 494 return 1; 495 } else { 496 return 0; 497 } 498 } 499#else 500 /* This implements x87 NaN propagation rules: 501 * SNaN + QNaN => return the QNaN 502 * two SNaNs => return the one with the larger significand, silenced 503 * two QNaNs => return the one with the larger significand 504 * SNaN and a non-NaN => return the SNaN, silenced 505 * QNaN and a non-NaN => return the QNaN 506 * 507 * If we get down to comparing significands and they are the same, 508 * return the NaN with the positive sign bit (if any). 509 */ 510 if (is_snan(a_cls)) { 511 if (is_snan(b_cls)) { 512 return aIsLargerSignificand ? 0 : 1; 513 } 514 return is_qnan(b_cls) ? 1 : 0; 515 } else if (is_qnan(a_cls)) { 516 if (is_snan(b_cls) || !is_qnan(b_cls)) { 517 return 0; 518 } else { 519 return aIsLargerSignificand ? 0 : 1; 520 } 521 } else { 522 return 1; 523 } 524#endif 525} 526 527/*---------------------------------------------------------------------------- 528| Select which NaN to propagate for a three-input operation. 529| For the moment we assume that no CPU needs the 'larger significand' 530| information. 531| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN 532*----------------------------------------------------------------------------*/ 533static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, 534 bool infzero, float_status *status) 535{ 536#if defined(TARGET_ARM) 537 /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns 538 * the default NaN 539 */ 540 if (infzero && is_qnan(c_cls)) { 541 float_raise(float_flag_invalid, status); 542 return 3; 543 } 544 545 /* This looks different from the ARM ARM pseudocode, because the ARM ARM 546 * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. 547 */ 548 if (is_snan(c_cls)) { 549 return 2; 550 } else if (is_snan(a_cls)) { 551 return 0; 552 } else if (is_snan(b_cls)) { 553 return 1; 554 } else if (is_qnan(c_cls)) { 555 return 2; 556 } else if (is_qnan(a_cls)) { 557 return 0; 558 } else { 559 return 1; 560 } 561#elif defined(TARGET_MIPS) 562 if (snan_bit_is_one(status)) { 563 /* 564 * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) 565 * case sets InvalidOp and returns the default NaN 566 */ 567 if (infzero) { 568 float_raise(float_flag_invalid, status); 569 return 3; 570 } 571 /* Prefer sNaN over qNaN, in the a, b, c order. */ 572 if (is_snan(a_cls)) { 573 return 0; 574 } else if (is_snan(b_cls)) { 575 return 1; 576 } else if (is_snan(c_cls)) { 577 return 2; 578 } else if (is_qnan(a_cls)) { 579 return 0; 580 } else if (is_qnan(b_cls)) { 581 return 1; 582 } else { 583 return 2; 584 } 585 } else { 586 /* 587 * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) 588 * case sets InvalidOp and returns the input value 'c' 589 */ 590 if (infzero) { 591 float_raise(float_flag_invalid, status); 592 return 2; 593 } 594 /* Prefer sNaN over qNaN, in the c, a, b order. */ 595 if (is_snan(c_cls)) { 596 return 2; 597 } else if (is_snan(a_cls)) { 598 return 0; 599 } else if (is_snan(b_cls)) { 600 return 1; 601 } else if (is_qnan(c_cls)) { 602 return 2; 603 } else if (is_qnan(a_cls)) { 604 return 0; 605 } else { 606 return 1; 607 } 608 } 609#elif defined(TARGET_PPC) 610 /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer 611 * to return an input NaN if we have one (ie c) rather than generating 612 * a default NaN 613 */ 614 if (infzero) { 615 float_raise(float_flag_invalid, status); 616 return 2; 617 } 618 619 /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; 620 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB 621 */ 622 if (is_nan(a_cls)) { 623 return 0; 624 } else if (is_nan(c_cls)) { 625 return 2; 626 } else { 627 return 1; 628 } 629#elif defined(TARGET_XTENSA) 630 /* 631 * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns 632 * an input NaN if we have one (ie c). 633 */ 634 if (infzero) { 635 float_raise(float_flag_invalid, status); 636 return 2; 637 } 638 if (status->use_first_nan) { 639 if (is_nan(a_cls)) { 640 return 0; 641 } else if (is_nan(b_cls)) { 642 return 1; 643 } else { 644 return 2; 645 } 646 } else { 647 if (is_nan(c_cls)) { 648 return 2; 649 } else if (is_nan(b_cls)) { 650 return 1; 651 } else { 652 return 0; 653 } 654 } 655#else 656 /* A default implementation: prefer a to b to c. 657 * This is unlikely to actually match any real implementation. 658 */ 659 if (is_nan(a_cls)) { 660 return 0; 661 } else if (is_nan(b_cls)) { 662 return 1; 663 } else { 664 return 2; 665 } 666#endif 667} 668 669/*---------------------------------------------------------------------------- 670| Takes two single-precision floating-point values `a' and `b', one of which 671| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a 672| signaling NaN, the invalid exception is raised. 673*----------------------------------------------------------------------------*/ 674 675static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) 676{ 677 bool aIsLargerSignificand; 678 uint32_t av, bv; 679 FloatClass a_cls, b_cls; 680 681 /* This is not complete, but is good enough for pickNaN. */ 682 a_cls = (!float32_is_any_nan(a) 683 ? float_class_normal 684 : float32_is_signaling_nan(a, status) 685 ? float_class_snan 686 : float_class_qnan); 687 b_cls = (!float32_is_any_nan(b) 688 ? float_class_normal 689 : float32_is_signaling_nan(b, status) 690 ? float_class_snan 691 : float_class_qnan); 692 693 av = float32_val(a); 694 bv = float32_val(b); 695 696 if (is_snan(a_cls) || is_snan(b_cls)) { 697 float_raise(float_flag_invalid, status); 698 } 699 700 if (status->default_nan_mode) { 701 return float32_default_nan(status); 702 } 703 704 if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) { 705 aIsLargerSignificand = 0; 706 } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) { 707 aIsLargerSignificand = 1; 708 } else { 709 aIsLargerSignificand = (av < bv) ? 1 : 0; 710 } 711 712 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 713 if (is_snan(b_cls)) { 714 return float32_silence_nan(b, status); 715 } 716 return b; 717 } else { 718 if (is_snan(a_cls)) { 719 return float32_silence_nan(a, status); 720 } 721 return a; 722 } 723} 724 725/*---------------------------------------------------------------------------- 726| Returns 1 if the double-precision floating-point value `a' is a quiet 727| NaN; otherwise returns 0. 728*----------------------------------------------------------------------------*/ 729 730bool float64_is_quiet_nan(float64 a_, float_status *status) 731{ 732 if (no_signaling_nans(status)) { 733 return float64_is_any_nan(a_); 734 } else { 735 uint64_t a = float64_val(a_); 736 if (snan_bit_is_one(status)) { 737 return (((a >> 51) & 0xFFF) == 0xFFE) 738 && (a & 0x0007FFFFFFFFFFFFULL); 739 } else { 740 return ((a << 1) >= 0xFFF0000000000000ULL); 741 } 742 } 743} 744 745/*---------------------------------------------------------------------------- 746| Returns 1 if the double-precision floating-point value `a' is a signaling 747| NaN; otherwise returns 0. 748*----------------------------------------------------------------------------*/ 749 750bool float64_is_signaling_nan(float64 a_, float_status *status) 751{ 752 if (no_signaling_nans(status)) { 753 return 0; 754 } else { 755 uint64_t a = float64_val(a_); 756 if (snan_bit_is_one(status)) { 757 return ((a << 1) >= 0xFFF0000000000000ULL); 758 } else { 759 return (((a >> 51) & 0xFFF) == 0xFFE) 760 && (a & UINT64_C(0x0007FFFFFFFFFFFF)); 761 } 762 } 763} 764 765/*---------------------------------------------------------------------------- 766| Returns the result of converting the double-precision floating-point NaN 767| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid 768| exception is raised. 769*----------------------------------------------------------------------------*/ 770 771static commonNaNT float64ToCommonNaN(float64 a, float_status *status) 772{ 773 commonNaNT z; 774 775 if (float64_is_signaling_nan(a, status)) { 776 float_raise(float_flag_invalid, status); 777 } 778 z.sign = float64_val(a) >> 63; 779 z.low = 0; 780 z.high = float64_val(a) << 12; 781 return z; 782} 783 784/*---------------------------------------------------------------------------- 785| Returns the result of converting the canonical NaN `a' to the double- 786| precision floating-point format. 787*----------------------------------------------------------------------------*/ 788 789static float64 commonNaNToFloat64(commonNaNT a, float_status *status) 790{ 791 uint64_t mantissa = a.high >> 12; 792 793 if (status->default_nan_mode) { 794 return float64_default_nan(status); 795 } 796 797 if (mantissa) { 798 return make_float64( 799 (((uint64_t) a.sign) << 63) 800 | UINT64_C(0x7FF0000000000000) 801 | (a.high >> 12)); 802 } else { 803 return float64_default_nan(status); 804 } 805} 806 807/*---------------------------------------------------------------------------- 808| Takes two double-precision floating-point values `a' and `b', one of which 809| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a 810| signaling NaN, the invalid exception is raised. 811*----------------------------------------------------------------------------*/ 812 813static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) 814{ 815 bool aIsLargerSignificand; 816 uint64_t av, bv; 817 FloatClass a_cls, b_cls; 818 819 /* This is not complete, but is good enough for pickNaN. */ 820 a_cls = (!float64_is_any_nan(a) 821 ? float_class_normal 822 : float64_is_signaling_nan(a, status) 823 ? float_class_snan 824 : float_class_qnan); 825 b_cls = (!float64_is_any_nan(b) 826 ? float_class_normal 827 : float64_is_signaling_nan(b, status) 828 ? float_class_snan 829 : float_class_qnan); 830 831 av = float64_val(a); 832 bv = float64_val(b); 833 834 if (is_snan(a_cls) || is_snan(b_cls)) { 835 float_raise(float_flag_invalid, status); 836 } 837 838 if (status->default_nan_mode) { 839 return float64_default_nan(status); 840 } 841 842 if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) { 843 aIsLargerSignificand = 0; 844 } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) { 845 aIsLargerSignificand = 1; 846 } else { 847 aIsLargerSignificand = (av < bv) ? 1 : 0; 848 } 849 850 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 851 if (is_snan(b_cls)) { 852 return float64_silence_nan(b, status); 853 } 854 return b; 855 } else { 856 if (is_snan(a_cls)) { 857 return float64_silence_nan(a, status); 858 } 859 return a; 860 } 861} 862 863/*---------------------------------------------------------------------------- 864| Returns 1 if the extended double-precision floating-point value `a' is a 865| quiet NaN; otherwise returns 0. This slightly differs from the same 866| function for other types as floatx80 has an explicit bit. 867*----------------------------------------------------------------------------*/ 868 869int floatx80_is_quiet_nan(floatx80 a, float_status *status) 870{ 871 if (no_signaling_nans(status)) { 872 return floatx80_is_any_nan(a); 873 } else { 874 if (snan_bit_is_one(status)) { 875 uint64_t aLow; 876 877 aLow = a.low & ~0x4000000000000000ULL; 878 return ((a.high & 0x7FFF) == 0x7FFF) 879 && (aLow << 1) 880 && (a.low == aLow); 881 } else { 882 return ((a.high & 0x7FFF) == 0x7FFF) 883 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); 884 } 885 } 886} 887 888/*---------------------------------------------------------------------------- 889| Returns 1 if the extended double-precision floating-point value `a' is a 890| signaling NaN; otherwise returns 0. This slightly differs from the same 891| function for other types as floatx80 has an explicit bit. 892*----------------------------------------------------------------------------*/ 893 894int floatx80_is_signaling_nan(floatx80 a, float_status *status) 895{ 896 if (no_signaling_nans(status)) { 897 return 0; 898 } else { 899 if (snan_bit_is_one(status)) { 900 return ((a.high & 0x7FFF) == 0x7FFF) 901 && ((a.low << 1) >= 0x8000000000000000ULL); 902 } else { 903 uint64_t aLow; 904 905 aLow = a.low & ~UINT64_C(0x4000000000000000); 906 return ((a.high & 0x7FFF) == 0x7FFF) 907 && (uint64_t)(aLow << 1) 908 && (a.low == aLow); 909 } 910 } 911} 912 913/*---------------------------------------------------------------------------- 914| Returns a quiet NaN from a signalling NaN for the extended double-precision 915| floating point value `a'. 916*----------------------------------------------------------------------------*/ 917 918floatx80 floatx80_silence_nan(floatx80 a, float_status *status) 919{ 920 /* None of the targets that have snan_bit_is_one use floatx80. */ 921 assert(!snan_bit_is_one(status)); 922 a.low |= UINT64_C(0xC000000000000000); 923 return a; 924} 925 926/*---------------------------------------------------------------------------- 927| Returns the result of converting the extended double-precision floating- 928| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the 929| invalid exception is raised. 930*----------------------------------------------------------------------------*/ 931 932static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status) 933{ 934 floatx80 dflt; 935 commonNaNT z; 936 937 if (floatx80_is_signaling_nan(a, status)) { 938 float_raise(float_flag_invalid, status); 939 } 940 if (a.low >> 63) { 941 z.sign = a.high >> 15; 942 z.low = 0; 943 z.high = a.low << 1; 944 } else { 945 dflt = floatx80_default_nan(status); 946 z.sign = dflt.high >> 15; 947 z.low = 0; 948 z.high = dflt.low << 1; 949 } 950 return z; 951} 952 953/*---------------------------------------------------------------------------- 954| Returns the result of converting the canonical NaN `a' to the extended 955| double-precision floating-point format. 956*----------------------------------------------------------------------------*/ 957 958static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status) 959{ 960 floatx80 z; 961 962 if (status->default_nan_mode) { 963 return floatx80_default_nan(status); 964 } 965 966 if (a.high >> 1) { 967 z.low = UINT64_C(0x8000000000000000) | a.high >> 1; 968 z.high = (((uint16_t)a.sign) << 15) | 0x7FFF; 969 } else { 970 z = floatx80_default_nan(status); 971 } 972 return z; 973} 974 975/*---------------------------------------------------------------------------- 976| Takes two extended double-precision floating-point values `a' and `b', one 977| of which is a NaN, and returns the appropriate NaN result. If either `a' or 978| `b' is a signaling NaN, the invalid exception is raised. 979*----------------------------------------------------------------------------*/ 980 981floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) 982{ 983 bool aIsLargerSignificand; 984 FloatClass a_cls, b_cls; 985 986 /* This is not complete, but is good enough for pickNaN. */ 987 a_cls = (!floatx80_is_any_nan(a) 988 ? float_class_normal 989 : floatx80_is_signaling_nan(a, status) 990 ? float_class_snan 991 : float_class_qnan); 992 b_cls = (!floatx80_is_any_nan(b) 993 ? float_class_normal 994 : floatx80_is_signaling_nan(b, status) 995 ? float_class_snan 996 : float_class_qnan); 997 998 if (is_snan(a_cls) || is_snan(b_cls)) { 999 float_raise(float_flag_invalid, status); 1000 } 1001 1002 if (status->default_nan_mode) { 1003 return floatx80_default_nan(status); 1004 } 1005 1006 if (a.low < b.low) { 1007 aIsLargerSignificand = 0; 1008 } else if (b.low < a.low) { 1009 aIsLargerSignificand = 1; 1010 } else { 1011 aIsLargerSignificand = (a.high < b.high) ? 1 : 0; 1012 } 1013 1014 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 1015 if (is_snan(b_cls)) { 1016 return floatx80_silence_nan(b, status); 1017 } 1018 return b; 1019 } else { 1020 if (is_snan(a_cls)) { 1021 return floatx80_silence_nan(a, status); 1022 } 1023 return a; 1024 } 1025} 1026 1027/*---------------------------------------------------------------------------- 1028| Returns 1 if the quadruple-precision floating-point value `a' is a quiet 1029| NaN; otherwise returns 0. 1030*----------------------------------------------------------------------------*/ 1031 1032bool float128_is_quiet_nan(float128 a, float_status *status) 1033{ 1034 if (no_signaling_nans(status)) { 1035 return float128_is_any_nan(a); 1036 } else { 1037 if (snan_bit_is_one(status)) { 1038 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 1039 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); 1040 } else { 1041 return ((a.high << 1) >= 0xFFFF000000000000ULL) 1042 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 1043 } 1044 } 1045} 1046 1047/*---------------------------------------------------------------------------- 1048| Returns 1 if the quadruple-precision floating-point value `a' is a 1049| signaling NaN; otherwise returns 0. 1050*----------------------------------------------------------------------------*/ 1051 1052bool float128_is_signaling_nan(float128 a, float_status *status) 1053{ 1054 if (no_signaling_nans(status)) { 1055 return 0; 1056 } else { 1057 if (snan_bit_is_one(status)) { 1058 return ((a.high << 1) >= 0xFFFF000000000000ULL) 1059 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 1060 } else { 1061 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 1062 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); 1063 } 1064 } 1065} 1066 1067/*---------------------------------------------------------------------------- 1068| Returns a quiet NaN from a signalling NaN for the quadruple-precision 1069| floating point value `a'. 1070*----------------------------------------------------------------------------*/ 1071 1072float128 float128_silence_nan(float128 a, float_status *status) 1073{ 1074 if (no_signaling_nans(status)) { 1075 g_assert_not_reached(); 1076 } else { 1077 if (snan_bit_is_one(status)) { 1078 return float128_default_nan(status); 1079 } else { 1080 a.high |= UINT64_C(0x0000800000000000); 1081 return a; 1082 } 1083 } 1084} 1085 1086/*---------------------------------------------------------------------------- 1087| Returns the result of converting the quadruple-precision floating-point NaN 1088| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid 1089| exception is raised. 1090*----------------------------------------------------------------------------*/ 1091 1092static commonNaNT float128ToCommonNaN(float128 a, float_status *status) 1093{ 1094 commonNaNT z; 1095 1096 if (float128_is_signaling_nan(a, status)) { 1097 float_raise(float_flag_invalid, status); 1098 } 1099 z.sign = a.high >> 63; 1100 shortShift128Left(a.high, a.low, 16, &z.high, &z.low); 1101 return z; 1102} 1103 1104/*---------------------------------------------------------------------------- 1105| Returns the result of converting the canonical NaN `a' to the quadruple- 1106| precision floating-point format. 1107*----------------------------------------------------------------------------*/ 1108 1109static float128 commonNaNToFloat128(commonNaNT a, float_status *status) 1110{ 1111 float128 z; 1112 1113 if (status->default_nan_mode) { 1114 return float128_default_nan(status); 1115 } 1116 1117 shift128Right(a.high, a.low, 16, &z.high, &z.low); 1118 z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000); 1119 return z; 1120} 1121 1122/*---------------------------------------------------------------------------- 1123| Takes two quadruple-precision floating-point values `a' and `b', one of 1124| which is a NaN, and returns the appropriate NaN result. If either `a' or 1125| `b' is a signaling NaN, the invalid exception is raised. 1126*----------------------------------------------------------------------------*/ 1127 1128static float128 propagateFloat128NaN(float128 a, float128 b, 1129 float_status *status) 1130{ 1131 bool aIsLargerSignificand; 1132 FloatClass a_cls, b_cls; 1133 1134 /* This is not complete, but is good enough for pickNaN. */ 1135 a_cls = (!float128_is_any_nan(a) 1136 ? float_class_normal 1137 : float128_is_signaling_nan(a, status) 1138 ? float_class_snan 1139 : float_class_qnan); 1140 b_cls = (!float128_is_any_nan(b) 1141 ? float_class_normal 1142 : float128_is_signaling_nan(b, status) 1143 ? float_class_snan 1144 : float_class_qnan); 1145 1146 if (is_snan(a_cls) || is_snan(b_cls)) { 1147 float_raise(float_flag_invalid, status); 1148 } 1149 1150 if (status->default_nan_mode) { 1151 return float128_default_nan(status); 1152 } 1153 1154 if (lt128(a.high << 1, a.low, b.high << 1, b.low)) { 1155 aIsLargerSignificand = 0; 1156 } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) { 1157 aIsLargerSignificand = 1; 1158 } else { 1159 aIsLargerSignificand = (a.high < b.high) ? 1 : 0; 1160 } 1161 1162 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 1163 if (is_snan(b_cls)) { 1164 return float128_silence_nan(b, status); 1165 } 1166 return b; 1167 } else { 1168 if (is_snan(a_cls)) { 1169 return float128_silence_nan(a, status); 1170 } 1171 return a; 1172 } 1173} 1174