1.. _Arm Emulation: 2 3A-profile CPU architecture support 4================================== 5 6QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and 7Armv8 versions of the A-profile architecture. It also has support for 8the following architecture extensions: 9 10- FEAT_AA32BF16 (AArch32 BFloat16 instructions) 11- FEAT_AA32EL0 (Support for AArch32 at EL0) 12- FEAT_AA32EL1 (Support for AArch32 at EL1) 13- FEAT_AA32EL2 (Support for AArch32 at EL2) 14- FEAT_AA32EL3 (Support for AArch32 at EL3) 15- FEAT_AA32HPD (AArch32 hierarchical permission disables) 16- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions) 17- FEAT_AA64EL0 (Support for AArch64 at EL0) 18- FEAT_AA64EL1 (Support for AArch64 at EL1) 19- FEAT_AA64EL2 (Support for AArch64 at EL2) 20- FEAT_AA64EL3 (Support for AArch64 at EL3) 21- FEAT_AdvSIMD (Advanced SIMD Extension) 22- FEAT_AES (AESD and AESE instructions) 23- FEAT_Armv9_Crypto (Armv9 Cryptographic Extension) 24- FEAT_ASID16 (16 bit ASID) 25- FEAT_BBM at level 2 (Translation table break-before-make levels) 26- FEAT_BF16 (AArch64 BFloat16 instructions) 27- FEAT_BTI (Branch Target Identification) 28- FEAT_CCIDX (Extended cache index) 29- FEAT_CMOW (Control for cache maintenance permission) 30- FEAT_CRC32 (CRC32 instructions) 31- FEAT_Crypto (Cryptographic Extension) 32- FEAT_CSV2 (Cache speculation variant 2) 33- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) 34- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) 35- FEAT_CSV2_2 (Cache speculation variant 2, version 2) 36- FEAT_CSV2_3 (Cache speculation variant 2, version 3) 37- FEAT_CSV3 (Cache speculation variant 3) 38- FEAT_DGH (Data gathering hint) 39- FEAT_DIT (Data Independent Timing instructions) 40- FEAT_DPB (DC CVAP instruction) 41- FEAT_DPB2 (DC CVADP instruction) 42- FEAT_Debugv8p1 (Debug with VHE) 43- FEAT_Debugv8p2 (Debug changes for v8.2) 44- FEAT_Debugv8p4 (Debug changes for v8.4) 45- FEAT_Debugv8p8 (Debug changes for v8.8) 46- FEAT_DotProd (Advanced SIMD dot product instructions) 47- FEAT_DoubleFault (Double Fault Extension) 48- FEAT_E0PD (Preventing EL0 access to halves of address maps) 49- FEAT_EBF16 (AArch64 Extended BFloat16 instructions) 50- FEAT_ECV (Enhanced Counter Virtualization) 51- FEAT_EL0 (Support for execution at EL0) 52- FEAT_EL1 (Support for execution at EL1) 53- FEAT_EL2 (Support for execution at EL2) 54- FEAT_EL3 (Support for execution at EL3) 55- FEAT_EPAC (Enhanced pointer authentication) 56- FEAT_ETS2 (Enhanced Translation Synchronization) 57- FEAT_EVT (Enhanced Virtualization Traps) 58- FEAT_F32MM (Single-precision Matrix Multiplication) 59- FEAT_F64MM (Double-precision Matrix Multiplication) 60- FEAT_FCMA (Floating-point complex number instructions) 61- FEAT_FGT (Fine-Grained Traps) 62- FEAT_FHM (Floating-point half-precision multiplication instructions) 63- FEAT_FP (Floating Point extensions) 64- FEAT_FP16 (Half-precision floating-point data processing) 65- FEAT_FPAC (Faulting on AUT* instructions) 66- FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions) 67- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions) 68- FEAT_FRINTTS (Floating-point to integer instructions) 69- FEAT_FlagM (Flag manipulation instructions v2) 70- FEAT_FlagM2 (Enhancements to flag manipulation instructions) 71- FEAT_GTG (Guest translation granule size) 72- FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) 73- FEAT_HBC (Hinted conditional branches) 74- FEAT_HCX (Support for the HCRX_EL2 register) 75- FEAT_HPDS (Hierarchical permission disables) 76- FEAT_HPDS2 (Translation table page-based hardware attributes) 77- FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero) 78- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) 79- FEAT_IDST (ID space trap handling) 80- FEAT_IESB (Implicit error synchronization event) 81- FEAT_JSCVT (JavaScript conversion instructions) 82- FEAT_LOR (Limited ordering regions) 83- FEAT_LPA (Large Physical Address space) 84- FEAT_LPA2 (Large Physical and virtual Address space v2) 85- FEAT_LRCPC (Load-acquire RCpc instructions) 86- FEAT_LRCPC2 (Load-acquire RCpc instructions v2) 87- FEAT_LSE (Large System Extensions) 88- FEAT_LSE2 (Large System Extensions v2) 89- FEAT_LVA (Large Virtual Address space) 90- FEAT_MixedEnd (Mixed-endian support) 91- FEAT_MixdEndEL0 (Mixed-endian support at EL0) 92- FEAT_MOPS (Standardization of memory operations) 93- FEAT_MTE (Memory Tagging Extension) 94- FEAT_MTE2 (Memory Tagging Extension) 95- FEAT_MTE3 (MTE Asymmetric Fault Handling) 96- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults) 97- FEAT_NMI (Non-maskable Interrupt) 98- FEAT_NV (Nested Virtualization) 99- FEAT_NV2 (Enhanced nested virtualization support) 100- FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm) 101- FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm) 102- FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm) 103- FEAT_PAN (Privileged access never) 104- FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN) 105- FEAT_PAN3 (Support for SCTLR_ELx.EPAN) 106- FEAT_PAuth (Pointer authentication) 107- FEAT_PAuth2 (Enhancements to pointer authentication) 108- FEAT_PMULL (PMULL, PMULL2 instructions) 109- FEAT_PMUv3 (PMU extension version 3) 110- FEAT_PMUv3p1 (PMU Extensions v3.1) 111- FEAT_PMUv3p4 (PMU Extensions v3.4) 112- FEAT_PMUv3p5 (PMU Extensions v3.5) 113- FEAT_RAS (Reliability, availability, and serviceability) 114- FEAT_RASv1p1 (RAS Extension v1.1) 115- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) 116- FEAT_RME (Realm Management Extension) (NB: support status in QEMU is experimental) 117- FEAT_RNG (Random number generator) 118- FEAT_S2FWB (Stage 2 forced Write-Back) 119- FEAT_SB (Speculation Barrier) 120- FEAT_SEL2 (Secure EL2) 121- FEAT_SHA1 (SHA1 instructions) 122- FEAT_SHA256 (SHA256 instructions) 123- FEAT_SHA3 (Advanced SIMD SHA3 instructions) 124- FEAT_SHA512 (Advanced SIMD SHA512 instructions) 125- FEAT_SM3 (Advanced SIMD SM3 instructions) 126- FEAT_SM4 (Advanced SIMD SM4 instructions) 127- FEAT_SME (Scalable Matrix Extension) 128- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) 129- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions) 130- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions) 131- FEAT_SVE (Scalable Vector Extension) 132- FEAT_SVE_AES (Scalable Vector AES instructions) 133- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions) 134- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions) 135- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions) 136- FEAT_SVE_SM4 (Scalable Vector SM4 instructions) 137- FEAT_SVE2 (Scalable Vector Extension version 2) 138- FEAT_SPECRES (Speculation restriction instructions) 139- FEAT_SSBS (Speculative Store Bypass Safe) 140- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1) 141- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) 142- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1) 143- FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality) 144- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) 145- FEAT_TLBIRANGE (TLB invalidate range instructions) 146- FEAT_TTCNP (Translation table Common not private translations) 147- FEAT_TTL (Translation Table Level) 148- FEAT_TTST (Small translation tables) 149- FEAT_UAO (Unprivileged Access Override control) 150- FEAT_VHE (Virtualization Host Extensions) 151- FEAT_VMID16 (16-bit VMID) 152- FEAT_WFxT (WFE and WFI instructions with timeout) 153- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) 154 155For information on the specifics of these extensions, please refer 156to the `Armv8-A Arm Architecture Reference Manual 157<https://developer.arm.com/documentation/ddi0487/latest>`_. 158 159When a specific named CPU is being emulated, only those features which 160are present in hardware for that CPU are emulated. (If a feature is 161not in the list above then it is not supported, even if the real 162hardware should have it.) The ``max`` CPU enables all features. 163 164R-profile CPU architecture support 165================================== 166 167QEMU's TCG emulation support for R-profile CPUs is currently limited. 168We emulate only the Cortex-R5 and Cortex-R5F CPUs. 169 170M-profile CPU architecture support 171================================== 172 173QEMU's TCG emulation includes support for Armv6-M, Armv7-M, Armv8-M, and 174Armv8.1-M versions of the M-profile architucture. It also has support 175for the following architecture extensions: 176 177- FP (Floating-point Extension) 178- FPCXT (FPCXT access instructions) 179- HP (Half-precision floating-point instructions) 180- LOB (Low Overhead loops and Branch future) 181- M (Main Extension) 182- MPU (Memory Protection Unit Extension) 183- PXN (Privileged Execute Never) 184- RAS (Reliability, Serviceability and Availability): "minimum RAS Extension" only 185- S (Security Extension) 186- ST (System Timer Extension) 187 188For information on the specifics of these extensions, please refer 189to the `Armv8-M Arm Architecture Reference Manual 190<https://developer.arm.com/documentation/ddi0553/latest>`_. 191 192When a specific named CPU is being emulated, only those features which 193are present in hardware for that CPU are emulated. (If a feature is 194not in the list above then it is not supported, even if the real 195hardware should have it.) There is no equivalent of the ``max`` CPU for 196M-profile. 197