xref: /openbmc/qemu/docs/system/arm/emulation.rst (revision 27047bd2)
1.. _Arm Emulation:
2
3A-profile CPU architecture support
4==================================
5
6QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and
7Armv8 versions of the A-profile architecture. It also has support for
8the following architecture extensions:
9
10- FEAT_AA32BF16 (AArch32 BFloat16 instructions)
11- FEAT_AA32HPD (AArch32 hierarchical permission disables)
12- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
13- FEAT_AES (AESD and AESE instructions)
14- FEAT_BBM at level 2 (Translation table break-before-make levels)
15- FEAT_BF16 (AArch64 BFloat16 instructions)
16- FEAT_BTI (Branch Target Identification)
17- FEAT_CSV2 (Cache speculation variant 2)
18- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
19- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
20- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
21- FEAT_CSV3 (Cache speculation variant 3)
22- FEAT_DGH (Data gathering hint)
23- FEAT_DIT (Data Independent Timing instructions)
24- FEAT_DPB (DC CVAP instruction)
25- FEAT_Debugv8p2 (Debug changes for v8.2)
26- FEAT_Debugv8p4 (Debug changes for v8.4)
27- FEAT_DotProd (Advanced SIMD dot product instructions)
28- FEAT_DoubleFault (Double Fault Extension)
29- FEAT_E0PD (Preventing EL0 access to halves of address maps)
30- FEAT_ETS (Enhanced Translation Synchronization)
31- FEAT_EVT (Enhanced Virtualization Traps)
32- FEAT_FCMA (Floating-point complex number instructions)
33- FEAT_FGT (Fine-Grained Traps)
34- FEAT_FHM (Floating-point half-precision multiplication instructions)
35- FEAT_FP16 (Half-precision floating-point data processing)
36- FEAT_FRINTTS (Floating-point to integer instructions)
37- FEAT_FlagM (Flag manipulation instructions v2)
38- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
39- FEAT_GTG (Guest translation granule size)
40- FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
41- FEAT_HCX (Support for the HCRX_EL2 register)
42- FEAT_HPDS (Hierarchical permission disables)
43- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
44- FEAT_IDST (ID space trap handling)
45- FEAT_IESB (Implicit error synchronization event)
46- FEAT_JSCVT (JavaScript conversion instructions)
47- FEAT_LOR (Limited ordering regions)
48- FEAT_LPA (Large Physical Address space)
49- FEAT_LPA2 (Large Physical and virtual Address space v2)
50- FEAT_LRCPC (Load-acquire RCpc instructions)
51- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
52- FEAT_LSE (Large System Extensions)
53- FEAT_LSE2 (Large System Extensions v2)
54- FEAT_LVA (Large Virtual Address space)
55- FEAT_MTE (Memory Tagging Extension)
56- FEAT_MTE2 (Memory Tagging Extension)
57- FEAT_MTE3 (MTE Asymmetric Fault Handling)
58- FEAT_PAN (Privileged access never)
59- FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
60- FEAT_PAN3 (Support for SCTLR_ELx.EPAN)
61- FEAT_PAuth (Pointer authentication)
62- FEAT_PMULL (PMULL, PMULL2 instructions)
63- FEAT_PMUv3p1 (PMU Extensions v3.1)
64- FEAT_PMUv3p4 (PMU Extensions v3.4)
65- FEAT_PMUv3p5 (PMU Extensions v3.5)
66- FEAT_RAS (Reliability, availability, and serviceability)
67- FEAT_RASv1p1 (RAS Extension v1.1)
68- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
69- FEAT_RNG (Random number generator)
70- FEAT_S2FWB (Stage 2 forced Write-Back)
71- FEAT_SB (Speculation Barrier)
72- FEAT_SEL2 (Secure EL2)
73- FEAT_SHA1 (SHA1 instructions)
74- FEAT_SHA256 (SHA256 instructions)
75- FEAT_SHA3 (Advanced SIMD SHA3 instructions)
76- FEAT_SHA512 (Advanced SIMD SHA512 instructions)
77- FEAT_SM3 (Advanced SIMD SM3 instructions)
78- FEAT_SM4 (Advanced SIMD SM4 instructions)
79- FEAT_SME (Scalable Matrix Extension)
80- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
81- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
82- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
83- FEAT_SPECRES (Speculation restriction instructions)
84- FEAT_SSBS (Speculative Store Bypass Safe)
85- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
86- FEAT_TLBIRANGE (TLB invalidate range instructions)
87- FEAT_TTCNP (Translation table Common not private translations)
88- FEAT_TTL (Translation Table Level)
89- FEAT_TTST (Small translation tables)
90- FEAT_UAO (Unprivileged Access Override control)
91- FEAT_VHE (Virtualization Host Extensions)
92- FEAT_VMID16 (16-bit VMID)
93- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
94- SVE (The Scalable Vector Extension)
95- SVE2 (The Scalable Vector Extension v2)
96
97For information on the specifics of these extensions, please refer
98to the `Armv8-A Arm Architecture Reference Manual
99<https://developer.arm.com/documentation/ddi0487/latest>`_.
100
101When a specific named CPU is being emulated, only those features which
102are present in hardware for that CPU are emulated. (If a feature is
103not in the list above then it is not supported, even if the real
104hardware should have it.) The ``max`` CPU enables all features.
105
106R-profile CPU architecture support
107==================================
108
109QEMU's TCG emulation support for R-profile CPUs is currently limited.
110We emulate only the Cortex-R5 and Cortex-R5F CPUs.
111
112M-profile CPU architecture support
113==================================
114
115QEMU's TCG emulation includes support for Armv6-M, Armv7-M, Armv8-M, and
116Armv8.1-M versions of the M-profile architucture.  It also has support
117for the following architecture extensions:
118
119- FP (Floating-point Extension)
120- FPCXT (FPCXT access instructions)
121- HP (Half-precision floating-point instructions)
122- LOB (Low Overhead loops and Branch future)
123- M (Main Extension)
124- MPU (Memory Protection Unit Extension)
125- PXN (Privileged Execute Never)
126- RAS (Reliability, Serviceability and Availability): "minimum RAS Extension" only
127- S (Security Extension)
128- ST (System Timer Extension)
129
130For information on the specifics of these extensions, please refer
131to the `Armv8-M Arm Architecture Reference Manual
132<https://developer.arm.com/documentation/ddi0553/latest>`_.
133
134When a specific named CPU is being emulated, only those features which
135are present in hardware for that CPU are emulated. (If a feature is
136not in the list above then it is not supported, even if the real
137hardware should have it.) There is no equivalent of the ``max`` CPU for
138M-profile.
139