1.. _tcg-ops-ref: 2 3******************************* 4TCG Intermediate Representation 5******************************* 6 7Introduction 8============ 9 10TCG (Tiny Code Generator) began as a generic backend for a C compiler. 11It was simplified to be used in QEMU. It also has its roots in the 12QOP code generator written by Paul Brook. 13 14Definitions 15=========== 16 17The TCG *target* is the architecture for which we generate the code. 18It is of course not the same as the "target" of QEMU which is the 19emulated architecture. As TCG started as a generic C backend used 20for cross compiling, the assumption was that TCG target might be 21different from the host, although this is never the case for QEMU. 22 23In this document, we use *guest* to specify what architecture we are 24emulating; *target* always means the TCG target, the machine on which 25we are running QEMU. 26 27An operation with *undefined behavior* may result in a crash. 28 29An operation with *unspecified behavior* shall not crash. However, 30the result may be one of several possibilities so may be considered 31an *undefined result*. 32 33Basic Blocks 34============ 35 36A TCG *basic block* is a single entry, multiple exit region which 37corresponds to a list of instructions terminated by a label, or 38any branch instruction. 39 40A TCG *extended basic block* is a single entry, multiple exit region 41which corresponds to a list of instructions terminated by a label or 42an unconditional branch. Specifically, an extended basic block is 43a sequence of basic blocks connected by the fall-through paths of 44zero or more conditional branch instructions. 45 46Operations 47========== 48 49TCG instructions or *ops* operate on TCG *variables*, both of which 50are strongly typed. Each instruction has a fixed number of output 51variable operands, input variable operands and constant operands. 52Vector instructions have a field specifying the element size within 53the vector. The notable exception is the call instruction which has 54a variable number of outputs and inputs. 55 56In the textual form, output operands usually come first, followed by 57input operands, followed by constant operands. The output type is 58included in the instruction name. Constants are prefixed with a '$'. 59 60.. code-block:: none 61 62 add_i32 t0, t1, t2 /* (t0 <- t1 + t2) */ 63 64Variables 65========= 66 67* ``TEMP_FIXED`` 68 69 There is one TCG *fixed global* variable, ``cpu_env``, which is 70 live in all translation blocks, and holds a pointer to ``CPUArchState``. 71 This variable is held in a host cpu register at all times in all 72 translation blocks. 73 74* ``TEMP_GLOBAL`` 75 76 A TCG *global* is a variable which is live in all translation blocks, 77 and corresponds to memory location that is within ``CPUArchState``. 78 These may be specified as an offset from ``cpu_env``, in which case 79 they are called *direct globals*, or may be specified as an offset 80 from a direct global, in which case they are called *indirect globals*. 81 Even indirect globals should still reference memory within 82 ``CPUArchState``. All TCG globals are defined during 83 ``TCGCPUOps.initialize``, before any translation blocks are generated. 84 85* ``TEMP_CONST`` 86 87 A TCG *constant* is a variable which is live throughout the entire 88 translation block, and contains a constant value. These variables 89 are allocated on demand during translation and are hashed so that 90 there is exactly one variable holding a given value. 91 92* ``TEMP_TB`` 93 94 A TCG *translation block temporary* is a variable which is live 95 throughout the entire translation block, but dies on any exit. 96 These temporaries are allocated explicitly during translation. 97 98* ``TEMP_EBB`` 99 100 A TCG *extended basic block temporary* is a variable which is live 101 throughout an extended basic block, but dies on any exit. 102 These temporaries are allocated explicitly during translation. 103 104Types 105===== 106 107* ``TCG_TYPE_I32`` 108 109 A 32-bit integer. 110 111* ``TCG_TYPE_I64`` 112 113 A 64-bit integer. For 32-bit hosts, such variables are split into a pair 114 of variables with ``type=TCG_TYPE_I32`` and ``base_type=TCG_TYPE_I64``. 115 The ``temp_subindex`` for each indicates where it falls within the 116 host-endian representation. 117 118* ``TCG_TYPE_PTR`` 119 120 An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size 121 of a pointer for the host. 122 123* ``TCG_TYPE_REG`` 124 125 An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size 126 of the integer registers for the host. This may be larger 127 than ``TCG_TYPE_PTR`` depending on the host ABI. 128 129* ``TCG_TYPE_I128`` 130 131 A 128-bit integer. For all hosts, such variables are split into a number 132 of variables with ``type=TCG_TYPE_REG`` and ``base_type=TCG_TYPE_I128``. 133 The ``temp_subindex`` for each indicates where it falls within the 134 host-endian representation. 135 136* ``TCG_TYPE_V64`` 137 138 A 64-bit vector. This type is valid only if the TCG target 139 sets ``TCG_TARGET_HAS_v64``. 140 141* ``TCG_TYPE_V128`` 142 143 A 128-bit vector. This type is valid only if the TCG target 144 sets ``TCG_TARGET_HAS_v128``. 145 146* ``TCG_TYPE_V256`` 147 148 A 256-bit vector. This type is valid only if the TCG target 149 sets ``TCG_TARGET_HAS_v256``. 150 151Helpers 152======= 153 154Helpers are registered in a guest-specific ``helper.h``, 155which is processed to generate ``tcg_gen_helper_*`` functions. 156With these functions it is possible to call a function taking 157i32, i64, i128 or pointer types. 158 159By default, before calling a helper, all globals are stored at their 160canonical location. By default, the helper is allowed to modify the 161CPU state (including the state represented by tcg globals) 162or may raise an exception. This default can be overridden using the 163following function modifiers: 164 165* ``TCG_CALL_NO_WRITE_GLOBALS`` 166 167 The helper does not modify any globals, but may read them. 168 Globals will be saved to their canonical location before calling helpers, 169 but need not be reloaded afterwards. 170 171* ``TCG_CALL_NO_READ_GLOBALS`` 172 173 The helper does not read globals, either directly or via an exception. 174 They will not be saved to their canonical locations before calling 175 the helper. This implies ``TCG_CALL_NO_WRITE_GLOBALS``. 176 177* ``TCG_CALL_NO_SIDE_EFFECTS`` 178 179 The call to the helper function may be removed if the return value is 180 not used. This means that it may not modify any CPU state nor may it 181 raise an exception. 182 183Code Optimizations 184================== 185 186When generating instructions, you can count on at least the following 187optimizations: 188 189- Single instructions are simplified, e.g. 190 191 .. code-block:: none 192 193 and_i32 t0, t0, $0xffffffff 194 195 is suppressed. 196 197- A liveness analysis is done at the basic block level. The 198 information is used to suppress moves from a dead variable to 199 another one. It is also used to remove instructions which compute 200 dead results. The later is especially useful for condition code 201 optimization in QEMU. 202 203 In the following example: 204 205 .. code-block:: none 206 207 add_i32 t0, t1, t2 208 add_i32 t0, t0, $1 209 mov_i32 t0, $1 210 211 only the last instruction is kept. 212 213 214Instruction Reference 215===================== 216 217Function call 218------------- 219 220.. list-table:: 221 222 * - call *<ret>* *<params>* ptr 223 224 - | call function 'ptr' (pointer type) 225 | 226 | *<ret>* optional 32 bit or 64 bit return value 227 | *<params>* optional 32 bit or 64 bit parameters 228 229Jumps/Labels 230------------ 231 232.. list-table:: 233 234 * - set_label $label 235 236 - | Define label 'label' at the current program point. 237 238 * - br $label 239 240 - | Jump to label. 241 242 * - brcond_i32/i64 *t0*, *t1*, *cond*, *label* 243 244 - | Conditional jump if *t0* *cond* *t1* is true. *cond* can be: 245 | 246 | ``TCG_COND_EQ`` 247 | ``TCG_COND_NE`` 248 | ``TCG_COND_LT /* signed */`` 249 | ``TCG_COND_GE /* signed */`` 250 | ``TCG_COND_LE /* signed */`` 251 | ``TCG_COND_GT /* signed */`` 252 | ``TCG_COND_LTU /* unsigned */`` 253 | ``TCG_COND_GEU /* unsigned */`` 254 | ``TCG_COND_LEU /* unsigned */`` 255 | ``TCG_COND_GTU /* unsigned */`` 256 | ``TCG_COND_TSTEQ /* t1 & t2 == 0 */`` 257 | ``TCG_COND_TSTNE /* t1 & t2 != 0 */`` 258 259Arithmetic 260---------- 261 262.. list-table:: 263 264 * - add *t0*, *t1*, *t2* 265 266 - | *t0* = *t1* + *t2* 267 268 * - sub *t0*, *t1*, *t2* 269 270 - | *t0* = *t1* - *t2* 271 272 * - neg *t0*, *t1* 273 274 - | *t0* = -*t1* (two's complement) 275 276 * - mul *t0*, *t1*, *t2* 277 278 - | *t0* = *t1* * *t2* 279 280 * - div_i32/i64 *t0*, *t1*, *t2* 281 282 - | *t0* = *t1* / *t2* (signed) 283 | Undefined behavior if division by zero or overflow. 284 285 * - divu_i32/i64 *t0*, *t1*, *t2* 286 287 - | *t0* = *t1* / *t2* (unsigned) 288 | Undefined behavior if division by zero. 289 290 * - rem_i32/i64 *t0*, *t1*, *t2* 291 292 - | *t0* = *t1* % *t2* (signed) 293 | Undefined behavior if division by zero or overflow. 294 295 * - remu_i32/i64 *t0*, *t1*, *t2* 296 297 - | *t0* = *t1* % *t2* (unsigned) 298 | Undefined behavior if division by zero. 299 300 301Logical 302------- 303 304.. list-table:: 305 306 * - and *t0*, *t1*, *t2* 307 308 - | *t0* = *t1* & *t2* 309 310 * - or *t0*, *t1*, *t2* 311 312 - | *t0* = *t1* | *t2* 313 314 * - xor *t0*, *t1*, *t2* 315 316 - | *t0* = *t1* ^ *t2* 317 318 * - not *t0*, *t1* 319 320 - | *t0* = ~\ *t1* 321 322 * - andc *t0*, *t1*, *t2* 323 324 - | *t0* = *t1* & ~\ *t2* 325 326 * - eqv *t0*, *t1*, *t2* 327 328 - | *t0* = ~(*t1* ^ *t2*), or equivalently, *t0* = *t1* ^ ~\ *t2* 329 330 * - nand *t0*, *t1*, *t2* 331 332 - | *t0* = ~(*t1* & *t2*) 333 334 * - nor *t0*, *t1*, *t2* 335 336 - | *t0* = ~(*t1* | *t2*) 337 338 * - orc *t0*, *t1*, *t2* 339 340 - | *t0* = *t1* | ~\ *t2* 341 342 * - clz_i32/i64 *t0*, *t1*, *t2* 343 344 - | *t0* = *t1* ? clz(*t1*) : *t2* 345 346 * - ctz_i32/i64 *t0*, *t1*, *t2* 347 348 - | *t0* = *t1* ? ctz(*t1*) : *t2* 349 350 * - ctpop_i32/i64 *t0*, *t1* 351 352 - | *t0* = number of bits set in *t1* 353 | 354 | With *ctpop* short for "count population", matching 355 | the function name used in ``include/qemu/host-utils.h``. 356 357 358Shifts/Rotates 359-------------- 360 361.. list-table:: 362 363 * - shl_i32/i64 *t0*, *t1*, *t2* 364 365 - | *t0* = *t1* << *t2* 366 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64) 367 368 * - shr_i32/i64 *t0*, *t1*, *t2* 369 370 - | *t0* = *t1* >> *t2* (unsigned) 371 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64) 372 373 * - sar_i32/i64 *t0*, *t1*, *t2* 374 375 - | *t0* = *t1* >> *t2* (signed) 376 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64) 377 378 * - rotl_i32/i64 *t0*, *t1*, *t2* 379 380 - | Rotation of *t2* bits to the left 381 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64) 382 383 * - rotr_i32/i64 *t0*, *t1*, *t2* 384 385 - | Rotation of *t2* bits to the right. 386 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64) 387 388 389Misc 390---- 391 392.. list-table:: 393 394 * - mov *t0*, *t1* 395 396 - | *t0* = *t1* 397 | Move *t1* to *t0*. 398 399 * - bswap16_i32/i64 *t0*, *t1*, *flags* 400 401 - | 16 bit byte swap on the low bits of a 32/64 bit input. 402 | 403 | If *flags* & ``TCG_BSWAP_IZ``, then *t1* is known to be zero-extended from bit 15. 404 | If *flags* & ``TCG_BSWAP_OZ``, then *t0* will be zero-extended from bit 15. 405 | If *flags* & ``TCG_BSWAP_OS``, then *t0* will be sign-extended from bit 15. 406 | 407 | If neither ``TCG_BSWAP_OZ`` nor ``TCG_BSWAP_OS`` are set, then the bits of *t0* above bit 15 may contain any value. 408 409 * - bswap32_i64 *t0*, *t1*, *flags* 410 411 - | 32 bit byte swap on a 64-bit value. The flags are the same as for bswap16, 412 except they apply from bit 31 instead of bit 15. 413 414 * - bswap32_i32 *t0*, *t1*, *flags* 415 416 bswap64_i64 *t0*, *t1*, *flags* 417 418 - | 32/64 bit byte swap. The flags are ignored, but still present 419 for consistency with the other bswap opcodes. 420 421 * - discard_i32/i64 *t0* 422 423 - | Indicate that the value of *t0* won't be used later. It is useful to 424 force dead code elimination. 425 426 * - deposit_i32/i64 *dest*, *t1*, *t2*, *pos*, *len* 427 428 - | Deposit *t2* as a bitfield into *t1*, placing the result in *dest*. 429 | 430 | The bitfield is described by *pos*/*len*, which are immediate values: 431 | 432 | *len* - the length of the bitfield 433 | *pos* - the position of the first bit, counting from the LSB 434 | 435 | For example, "deposit_i32 dest, t1, t2, 8, 4" indicates a 4-bit field 436 at bit 8. This operation would be equivalent to 437 | 438 | *dest* = (*t1* & ~0x0f00) | ((*t2* << 8) & 0x0f00) 439 440 * - extract_i32/i64 *dest*, *t1*, *pos*, *len* 441 442 sextract_i32/i64 *dest*, *t1*, *pos*, *len* 443 444 - | Extract a bitfield from *t1*, placing the result in *dest*. 445 | 446 | The bitfield is described by *pos*/*len*, which are immediate values, 447 as above for deposit. For extract_*, the result will be extended 448 to the left with zeros; for sextract_*, the result will be extended 449 to the left with copies of the bitfield sign bit at *pos* + *len* - 1. 450 | 451 | For example, "sextract_i32 dest, t1, 8, 4" indicates a 4-bit field 452 at bit 8. This operation would be equivalent to 453 | 454 | *dest* = (*t1* << 20) >> 28 455 | 456 | (using an arithmetic right shift). 457 458 * - extract2_i32/i64 *dest*, *t1*, *t2*, *pos* 459 460 - | For N = {32,64}, extract an N-bit quantity from the concatenation 461 of *t2*:*t1*, beginning at *pos*. The tcg_gen_extract2_{i32,i64} expander 462 accepts 0 <= *pos* <= N as inputs. The backend code generator will 463 not see either 0 or N as inputs for these opcodes. 464 465 * - extrl_i64_i32 *t0*, *t1* 466 467 - | For 64-bit hosts only, extract the low 32-bits of input *t1* and place it 468 into 32-bit output *t0*. Depending on the host, this may be a simple move, 469 or may require additional canonicalization. 470 471 * - extrh_i64_i32 *t0*, *t1* 472 473 - | For 64-bit hosts only, extract the high 32-bits of input *t1* and place it 474 into 32-bit output *t0*. Depending on the host, this may be a simple shift, 475 or may require additional canonicalization. 476 477 478Conditional moves 479----------------- 480 481.. list-table:: 482 483 * - setcond_i32/i64 *dest*, *t1*, *t2*, *cond* 484 485 - | *dest* = (*t1* *cond* *t2*) 486 | 487 | Set *dest* to 1 if (*t1* *cond* *t2*) is true, otherwise set to 0. 488 489 * - negsetcond_i32/i64 *dest*, *t1*, *t2*, *cond* 490 491 - | *dest* = -(*t1* *cond* *t2*) 492 | 493 | Set *dest* to -1 if (*t1* *cond* *t2*) is true, otherwise set to 0. 494 495 * - movcond_i32/i64 *dest*, *c1*, *c2*, *v1*, *v2*, *cond* 496 497 - | *dest* = (*c1* *cond* *c2* ? *v1* : *v2*) 498 | 499 | Set *dest* to *v1* if (*c1* *cond* *c2*) is true, otherwise set to *v2*. 500 501 502Type conversions 503---------------- 504 505.. list-table:: 506 507 * - ext_i32_i64 *t0*, *t1* 508 509 - | Convert *t1* (32 bit) to *t0* (64 bit) and does sign extension 510 511 * - extu_i32_i64 *t0*, *t1* 512 513 - | Convert *t1* (32 bit) to *t0* (64 bit) and does zero extension 514 515 * - trunc_i64_i32 *t0*, *t1* 516 517 - | Truncate *t1* (64 bit) to *t0* (32 bit) 518 519 * - concat_i32_i64 *t0*, *t1*, *t2* 520 521 - | Construct *t0* (64-bit) taking the low half from *t1* (32 bit) and the high half 522 from *t2* (32 bit). 523 524 * - concat32_i64 *t0*, *t1*, *t2* 525 526 - | Construct *t0* (64-bit) taking the low half from *t1* (64 bit) and the high half 527 from *t2* (64 bit). 528 529 530Load/Store 531---------- 532 533.. list-table:: 534 535 * - ld_i32/i64 *t0*, *t1*, *offset* 536 537 ld8s_i32/i64 *t0*, *t1*, *offset* 538 539 ld8u_i32/i64 *t0*, *t1*, *offset* 540 541 ld16s_i32/i64 *t0*, *t1*, *offset* 542 543 ld16u_i32/i64 *t0*, *t1*, *offset* 544 545 ld32s_i64 t0, *t1*, *offset* 546 547 ld32u_i64 t0, *t1*, *offset* 548 549 - | *t0* = read(*t1* + *offset*) 550 | 551 | Load 8, 16, 32 or 64 bits with or without sign extension from host memory. 552 *offset* must be a constant. 553 554 * - st_i32/i64 *t0*, *t1*, *offset* 555 556 st8_i32/i64 *t0*, *t1*, *offset* 557 558 st16_i32/i64 *t0*, *t1*, *offset* 559 560 st32_i64 *t0*, *t1*, *offset* 561 562 - | write(*t0*, *t1* + *offset*) 563 | 564 | Write 8, 16, 32 or 64 bits to host memory. 565 566All this opcodes assume that the pointed host memory doesn't correspond 567to a global. In the latter case the behaviour is unpredictable. 568 569 570Multiword arithmetic support 571---------------------------- 572 573.. list-table:: 574 575 * - add2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high* 576 577 sub2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high* 578 579 - | Similar to add/sub, except that the double-word inputs *t1* and *t2* are 580 formed from two single-word arguments, and the double-word output *t0* 581 is returned in two single-word outputs. 582 583 * - mulu2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2* 584 585 - | Similar to mul, except two unsigned inputs *t1* and *t2* yielding the full 586 double-word product *t0*. The latter is returned in two single-word outputs. 587 588 * - muls2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2* 589 590 - | Similar to mulu2, except the two inputs *t1* and *t2* are signed. 591 592 * - mulsh *t0*, *t1*, *t2* 593 594 muluh *t0*, *t1*, *t2* 595 596 - | Provide the high part of a signed or unsigned multiply, respectively. 597 | 598 | If mulu2/muls2 are not provided by the backend, the tcg-op generator 599 can obtain the same results by emitting a pair of opcodes, mul + muluh/mulsh. 600 601 602Memory Barrier support 603---------------------- 604 605.. list-table:: 606 607 * - mb *<$arg>* 608 609 - | Generate a target memory barrier instruction to ensure memory ordering 610 as being enforced by a corresponding guest memory barrier instruction. 611 | 612 | The ordering enforced by the backend may be stricter than the ordering 613 required by the guest. It cannot be weaker. This opcode takes a constant 614 argument which is required to generate the appropriate barrier 615 instruction. The backend should take care to emit the target barrier 616 instruction only when necessary i.e., for SMP guests and when MTTCG is 617 enabled. 618 | 619 | The guest translators should generate this opcode for all guest instructions 620 which have ordering side effects. 621 | 622 | Please see :ref:`atomics-ref` for more information on memory barriers. 623 624 62564-bit guest on 32-bit host support 626----------------------------------- 627 628The following opcodes are internal to TCG. Thus they are to be implemented by 62932-bit host code generators, but are not to be emitted by guest translators. 630They are emitted as needed by inline functions within ``tcg-op.h``. 631 632.. list-table:: 633 634 * - brcond2_i32 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *cond*, *label* 635 636 - | Similar to brcond, except that the 64-bit values *t0* and *t1* 637 are formed from two 32-bit arguments. 638 639 * - setcond2_i32 *dest*, *t1_low*, *t1_high*, *t2_low*, *t2_high*, *cond* 640 641 - | Similar to setcond, except that the 64-bit values *t1* and *t2* are 642 formed from two 32-bit arguments. The result is a 32-bit value. 643 644 645QEMU specific operations 646------------------------ 647 648.. list-table:: 649 650 * - exit_tb *t0* 651 652 - | Exit the current TB and return the value *t0* (word type). 653 654 * - goto_tb *index* 655 656 - | Exit the current TB and jump to the TB index *index* (constant) if the 657 current TB was linked to this TB. Otherwise execute the next 658 instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued 659 at most once with each slot index per TB. 660 661 * - lookup_and_goto_ptr *tb_addr* 662 663 - | Look up a TB address *tb_addr* and jump to it if valid. If not valid, 664 jump to the TCG epilogue to go back to the exec loop. 665 | 666 | This operation is optional. If the TCG backend does not implement the 667 goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0). 668 669 * - qemu_ld_i32/i64/i128 *t0*, *t1*, *flags*, *memidx* 670 671 qemu_st_i32/i64/i128 *t0*, *t1*, *flags*, *memidx* 672 673 qemu_st8_i32 *t0*, *t1*, *flags*, *memidx* 674 675 - | Load data at the guest address *t1* into *t0*, or store data in *t0* at guest 676 address *t1*. The _i32/_i64/_i128 size applies to the size of the input/output 677 register *t0* only. The address *t1* is always sized according to the guest, 678 and the width of the memory operation is controlled by *flags*. 679 | 680 | Both *t0* and *t1* may be split into little-endian ordered pairs of registers 681 if dealing with 64-bit quantities on a 32-bit host, or 128-bit quantities on 682 a 64-bit host. 683 | 684 | The *memidx* selects the qemu tlb index to use (e.g. user or kernel access). 685 The flags are the MemOp bits, selecting the sign, width, and endianness 686 of the memory access. 687 | 688 | For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a 689 64-bit memory access specified in *flags*. 690 | 691 | For qemu_ld/st_i128, these are only supported for a 64-bit host. 692 | 693 | For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of 694 the memory operation is known to be 8-bit. This allows the backend to 695 provide a different set of register constraints. 696 697 698Host vector operations 699---------------------- 700 701All of the vector ops have two parameters, ``TCGOP_TYPE`` & ``TCGOP_VECE``. 702The former specifies the length of the vector as a TCGType; the latter 703specifies the length of the element (if applicable) in log2 8-bit units. 704 705.. list-table:: 706 707 * - mov_vec *v0*, *v1* 708 709 ld_vec *v0*, *t1* 710 711 st_vec *v0*, *t1* 712 713 - | Move, load and store. 714 715 * - dup_vec *v0*, *r1* 716 717 - | Duplicate the low N bits of *r1* into TYPE/VECE copies across *v0*. 718 719 * - dupi_vec *v0*, *c* 720 721 - | Similarly, for a constant. 722 | Smaller values will be replicated to host register size by the expanders. 723 724 * - dup2_vec *v0*, *r1*, *r2* 725 726 - | Duplicate *r2*:*r1* into TYPE/64 copies across *v0*. This opcode is 727 only present for 32-bit hosts. 728 729 * - add_vec *v0*, *v1*, *v2* 730 731 - | *v0* = *v1* + *v2*, in elements across the vector. 732 733 * - sub_vec *v0*, *v1*, *v2* 734 735 - | Similarly, *v0* = *v1* - *v2*. 736 737 * - mul_vec *v0*, *v1*, *v2* 738 739 - | Similarly, *v0* = *v1* * *v2*. 740 741 * - neg_vec *v0*, *v1* 742 743 - | Similarly, *v0* = -*v1*. 744 745 * - abs_vec *v0*, *v1* 746 747 - | Similarly, *v0* = *v1* < 0 ? -*v1* : *v1*, in elements across the vector. 748 749 * - smin_vec *v0*, *v1*, *v2* 750 751 umin_vec *v0*, *v1*, *v2* 752 753 - | Similarly, *v0* = MIN(*v1*, *v2*), for signed and unsigned element types. 754 755 * - smax_vec *v0*, *v1*, *v2* 756 757 umax_vec *v0*, *v1*, *v2* 758 759 - | Similarly, *v0* = MAX(*v1*, *v2*), for signed and unsigned element types. 760 761 * - ssadd_vec *v0*, *v1*, *v2* 762 763 sssub_vec *v0*, *v1*, *v2* 764 765 usadd_vec *v0*, *v1*, *v2* 766 767 ussub_vec *v0*, *v1*, *v2* 768 769 - | Signed and unsigned saturating addition and subtraction. 770 | 771 | If the true result is not representable within the element type, the 772 element is set to the minimum or maximum value for the type. 773 774 * - and_vec *v0*, *v1*, *v2* 775 776 or_vec *v0*, *v1*, *v2* 777 778 xor_vec *v0*, *v1*, *v2* 779 780 andc_vec *v0*, *v1*, *v2* 781 782 orc_vec *v0*, *v1*, *v2* 783 784 not_vec *v0*, *v1* 785 786 - | Similarly, logical operations with and without complement. 787 | 788 | Note that VECE is unused. 789 790 * - shli_vec *v0*, *v1*, *i2* 791 792 shls_vec *v0*, *v1*, *s2* 793 794 - | Shift all elements from v1 by a scalar *i2*/*s2*. I.e. 795 796 .. code-block:: c 797 798 for (i = 0; i < TYPE/VECE; ++i) { 799 v0[i] = v1[i] << s2; 800 } 801 802 * - shri_vec *v0*, *v1*, *i2* 803 804 sari_vec *v0*, *v1*, *i2* 805 806 rotli_vec *v0*, *v1*, *i2* 807 808 shrs_vec *v0*, *v1*, *s2* 809 810 sars_vec *v0*, *v1*, *s2* 811 812 - | Similarly for logical and arithmetic right shift, and left rotate. 813 814 * - shlv_vec *v0*, *v1*, *v2* 815 816 - | Shift elements from *v1* by elements from *v2*. I.e. 817 818 .. code-block:: c 819 820 for (i = 0; i < TYPE/VECE; ++i) { 821 v0[i] = v1[i] << v2[i]; 822 } 823 824 * - shrv_vec *v0*, *v1*, *v2* 825 826 sarv_vec *v0*, *v1*, *v2* 827 828 rotlv_vec *v0*, *v1*, *v2* 829 830 rotrv_vec *v0*, *v1*, *v2* 831 832 - | Similarly for logical and arithmetic right shift, and rotates. 833 834 * - cmp_vec *v0*, *v1*, *v2*, *cond* 835 836 - | Compare vectors by element, storing -1 for true and 0 for false. 837 838 * - bitsel_vec *v0*, *v1*, *v2*, *v3* 839 840 - | Bitwise select, *v0* = (*v2* & *v1*) | (*v3* & ~\ *v1*), across the entire vector. 841 842 * - cmpsel_vec *v0*, *c1*, *c2*, *v3*, *v4*, *cond* 843 844 - | Select elements based on comparison results: 845 846 .. code-block:: c 847 848 for (i = 0; i < n; ++i) { 849 v0[i] = (c1[i] cond c2[i]) ? v3[i] : v4[i]. 850 } 851 852**Note 1**: Some shortcuts are defined when the last operand is known to be 853a constant (e.g. addi for add, movi for mov). 854 855**Note 2**: When using TCG, the opcodes must never be generated directly 856as some of them may not be available as "real" opcodes. Always use the 857function tcg_gen_xxx(args). 858 859 860Backend 861======= 862 863``tcg-target.h`` contains the target specific definitions. ``tcg-target.c.inc`` 864contains the target specific code; it is #included by ``tcg/tcg.c``, rather 865than being a standalone C file. 866 867Assumptions 868----------- 869 870The target word size (``TCG_TARGET_REG_BITS``) is expected to be 32 bit or 87164 bit. It is expected that the pointer has the same size as the word. 872 873On a 32 bit target, all 64 bit operations are converted to 32 bits. A 874few specific operations must be implemented to allow it (see add2_i32, 875sub2_i32, brcond2_i32). 876 877On a 64 bit target, the values are transferred between 32 and 64-bit 878registers using the following ops: 879 880- extrl_i64_i32 881- extrh_i64_i32 882- ext_i32_i64 883- extu_i32_i64 884 885They ensure that the values are correctly truncated or extended when 886moved from a 32-bit to a 64-bit register or vice-versa. Note that the 887extrl_i64_i32 and extrh_i64_i32 are optional ops. It is not necessary 888to implement them if all the following conditions are met: 889 890- 64-bit registers can hold 32-bit values 891- 32-bit values in a 64-bit register do not need to stay zero or 892 sign extended 893- all 32-bit TCG ops ignore the high part of 64-bit registers 894 895Floating point operations are not supported in this version. A 896previous incarnation of the code generator had full support of them, 897but it is better to concentrate on integer operations first. 898 899Constraints 900---------------- 901 902GCC like constraints are used to define the constraints of every 903instruction. Memory constraints are not supported in this 904version. Aliases are specified in the input operands as for GCC. 905 906The same register may be used for both an input and an output, even when 907they are not explicitly aliased. If an op expands to multiple target 908instructions then care must be taken to avoid clobbering input values. 909GCC style "early clobber" outputs are supported, with '``&``'. 910 911A target can define specific register or constant constraints. If an 912operation uses a constant input constraint which does not allow all 913constants, it must also accept registers in order to have a fallback. 914The constraint '``i``' is defined generically to accept any constant. 915The constraint '``r``' is not defined generically, but is consistently 916used by each backend to indicate all registers. If ``TCG_REG_ZERO`` 917is defined by the backend, the constraint '``z``' is defined generically 918to map constant 0 to the hardware zero register. 919 920The movi_i32 and movi_i64 operations must accept any constants. 921 922The mov_i32 and mov_i64 operations must accept any registers of the 923same type. 924 925The ld/st/sti instructions must accept signed 32 bit constant offsets. 926This can be implemented by reserving a specific register in which to 927compute the address if the offset is too big. 928 929The ld/st instructions must accept any destination (ld) or source (st) 930register. 931 932The sti instruction may fail if it cannot store the given constant. 933 934Function call assumptions 935------------------------- 936 937- The only supported types for parameters and return value are: 32 and 938 64 bit integers and pointer. 939- The stack grows downwards. 940- The first N parameters are passed in registers. 941- The next parameters are passed on the stack by storing them as words. 942- Some registers are clobbered during the call. 943- The function can return 0 or 1 value in registers. On a 32 bit 944 target, functions must be able to return 2 values in registers for 945 64 bit return type. 946 947 948Recommended coding rules for best performance 949============================================= 950 951- Use globals to represent the parts of the QEMU CPU state which are 952 often modified, e.g. the integer registers and the condition 953 codes. TCG will be able to use host registers to store them. 954 955- Don't hesitate to use helpers for complicated or seldom used guest 956 instructions. There is little performance advantage in using TCG to 957 implement guest instructions taking more than about twenty TCG 958 instructions. Note that this rule of thumb is more applicable to 959 helpers doing complex logic or arithmetic, where the C compiler has 960 scope to do a good job of optimisation; it is less relevant where 961 the instruction is mostly doing loads and stores, and in those cases 962 inline TCG may still be faster for longer sequences. 963 964- Use the 'discard' instruction if you know that TCG won't be able to 965 prove that a given global is "dead" at a given program point. The 966 x86 guest uses it to improve the condition codes optimisation. 967