xref: /openbmc/qemu/docs/devel/tcg-ops.rst (revision 7d87775f)
1.. _tcg-ops-ref:
2
3*******************************
4TCG Intermediate Representation
5*******************************
6
7Introduction
8============
9
10TCG (Tiny Code Generator) began as a generic backend for a C compiler.
11It was simplified to be used in QEMU.  It also has its roots in the
12QOP code generator written by Paul Brook.
13
14Definitions
15===========
16
17The TCG *target* is the architecture for which we generate the code.
18It is of course not the same as the "target" of QEMU which is the
19emulated architecture.  As TCG started as a generic C backend used
20for cross compiling, the assumption was that TCG target might be
21different from the host, although this is never the case for QEMU.
22
23In this document, we use *guest* to specify what architecture we are
24emulating; *target* always means the TCG target, the machine on which
25we are running QEMU.
26
27An operation with *undefined behavior* may result in a crash.
28
29An operation with *unspecified behavior* shall not crash.  However,
30the result may be one of several possibilities so may be considered
31an *undefined result*.
32
33Basic Blocks
34============
35
36A TCG *basic block* is a single entry, multiple exit region which
37corresponds to a list of instructions terminated by a label, or
38any branch instruction.
39
40A TCG *extended basic block* is a single entry, multiple exit region
41which corresponds to a list of instructions terminated by a label or
42an unconditional branch.  Specifically, an extended basic block is
43a sequence of basic blocks connected by the fall-through paths of
44zero or more conditional branch instructions.
45
46Operations
47==========
48
49TCG instructions or *ops* operate on TCG *variables*, both of which
50are strongly typed.  Each instruction has a fixed number of output
51variable operands, input variable operands and constant operands.
52Vector instructions have a field specifying the element size within
53the vector.  The notable exception is the call instruction which has
54a variable number of outputs and inputs.
55
56In the textual form, output operands usually come first, followed by
57input operands, followed by constant operands. The output type is
58included in the instruction name. Constants are prefixed with a '$'.
59
60.. code-block:: none
61
62   add_i32 t0, t1, t2    /* (t0 <- t1 + t2) */
63
64Variables
65=========
66
67* ``TEMP_FIXED``
68
69  There is one TCG *fixed global* variable, ``cpu_env``, which is
70  live in all translation blocks, and holds a pointer to ``CPUArchState``.
71  This variable is held in a host cpu register at all times in all
72  translation blocks.
73
74* ``TEMP_GLOBAL``
75
76  A TCG *global* is a variable which is live in all translation blocks,
77  and corresponds to memory location that is within ``CPUArchState``.
78  These may be specified as an offset from ``cpu_env``, in which case
79  they are called *direct globals*, or may be specified as an offset
80  from a direct global, in which case they are called *indirect globals*.
81  Even indirect globals should still reference memory within
82  ``CPUArchState``.  All TCG globals are defined during
83  ``TCGCPUOps.initialize``, before any translation blocks are generated.
84
85* ``TEMP_CONST``
86
87  A TCG *constant* is a variable which is live throughout the entire
88  translation block, and contains a constant value.  These variables
89  are allocated on demand during translation and are hashed so that
90  there is exactly one variable holding a given value.
91
92* ``TEMP_TB``
93
94  A TCG *translation block temporary* is a variable which is live
95  throughout the entire translation block, but dies on any exit.
96  These temporaries are allocated explicitly during translation.
97
98* ``TEMP_EBB``
99
100  A TCG *extended basic block temporary* is a variable which is live
101  throughout an extended basic block, but dies on any exit.
102  These temporaries are allocated explicitly during translation.
103
104Types
105=====
106
107* ``TCG_TYPE_I32``
108
109  A 32-bit integer.
110
111* ``TCG_TYPE_I64``
112
113  A 64-bit integer.  For 32-bit hosts, such variables are split into a pair
114  of variables with ``type=TCG_TYPE_I32`` and ``base_type=TCG_TYPE_I64``.
115  The ``temp_subindex`` for each indicates where it falls within the
116  host-endian representation.
117
118* ``TCG_TYPE_PTR``
119
120  An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size
121  of a pointer for the host.
122
123* ``TCG_TYPE_REG``
124
125  An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size
126  of the integer registers for the host.  This may be larger
127  than ``TCG_TYPE_PTR`` depending on the host ABI.
128
129* ``TCG_TYPE_I128``
130
131  A 128-bit integer.  For all hosts, such variables are split into a number
132  of variables with ``type=TCG_TYPE_REG`` and ``base_type=TCG_TYPE_I128``.
133  The ``temp_subindex`` for each indicates where it falls within the
134  host-endian representation.
135
136* ``TCG_TYPE_V64``
137
138  A 64-bit vector.  This type is valid only if the TCG target
139  sets ``TCG_TARGET_HAS_v64``.
140
141* ``TCG_TYPE_V128``
142
143  A 128-bit vector.  This type is valid only if the TCG target
144  sets ``TCG_TARGET_HAS_v128``.
145
146* ``TCG_TYPE_V256``
147
148  A 256-bit vector.  This type is valid only if the TCG target
149  sets ``TCG_TARGET_HAS_v256``.
150
151Helpers
152=======
153
154Helpers are registered in a guest-specific ``helper.h``,
155which is processed to generate ``tcg_gen_helper_*`` functions.
156With these functions it is possible to call a function taking
157i32, i64, i128 or pointer types.
158
159By default, before calling a helper, all globals are stored at their
160canonical location.  By default, the helper is allowed to modify the
161CPU state (including the state represented by tcg globals)
162or may raise an exception.  This default can be overridden using the
163following function modifiers:
164
165* ``TCG_CALL_NO_WRITE_GLOBALS``
166
167  The helper does not modify any globals, but may read them.
168  Globals will be saved to their canonical location before calling helpers,
169  but need not be reloaded afterwards.
170
171* ``TCG_CALL_NO_READ_GLOBALS``
172
173  The helper does not read globals, either directly or via an exception.
174  They will not be saved to their canonical locations before calling
175  the helper.  This implies ``TCG_CALL_NO_WRITE_GLOBALS``.
176
177* ``TCG_CALL_NO_SIDE_EFFECTS``
178
179  The call to the helper function may be removed if the return value is
180  not used.  This means that it may not modify any CPU state nor may it
181  raise an exception.
182
183Code Optimizations
184==================
185
186When generating instructions, you can count on at least the following
187optimizations:
188
189- Single instructions are simplified, e.g.
190
191  .. code-block:: none
192
193     and_i32 t0, t0, $0xffffffff
194
195  is suppressed.
196
197- A liveness analysis is done at the basic block level. The
198  information is used to suppress moves from a dead variable to
199  another one. It is also used to remove instructions which compute
200  dead results. The later is especially useful for condition code
201  optimization in QEMU.
202
203  In the following example:
204
205  .. code-block:: none
206
207     add_i32 t0, t1, t2
208     add_i32 t0, t0, $1
209     mov_i32 t0, $1
210
211  only the last instruction is kept.
212
213
214Instruction Reference
215=====================
216
217Function call
218-------------
219
220.. list-table::
221
222   * - call *<ret>* *<params>* ptr
223
224     - |  call function 'ptr' (pointer type)
225       |
226       |  *<ret>* optional 32 bit or 64 bit return value
227       |  *<params>* optional 32 bit or 64 bit parameters
228
229Jumps/Labels
230------------
231
232.. list-table::
233
234   * - set_label $label
235
236     - | Define label 'label' at the current program point.
237
238   * - br $label
239
240     - | Jump to label.
241
242   * - brcond_i32/i64 *t0*, *t1*, *cond*, *label*
243
244     - | Conditional jump if *t0* *cond* *t1* is true. *cond* can be:
245       |
246       |   ``TCG_COND_EQ``
247       |   ``TCG_COND_NE``
248       |   ``TCG_COND_LT /* signed */``
249       |   ``TCG_COND_GE /* signed */``
250       |   ``TCG_COND_LE /* signed */``
251       |   ``TCG_COND_GT /* signed */``
252       |   ``TCG_COND_LTU /* unsigned */``
253       |   ``TCG_COND_GEU /* unsigned */``
254       |   ``TCG_COND_LEU /* unsigned */``
255       |   ``TCG_COND_GTU /* unsigned */``
256       |   ``TCG_COND_TSTEQ /* t1 & t2 == 0 */``
257       |   ``TCG_COND_TSTNE /* t1 & t2 != 0 */``
258
259Arithmetic
260----------
261
262.. list-table::
263
264   * - add_i32/i64 *t0*, *t1*, *t2*
265
266     - | *t0* = *t1* + *t2*
267
268   * - sub_i32/i64 *t0*, *t1*, *t2*
269
270     - | *t0* = *t1* - *t2*
271
272   * - neg_i32/i64 *t0*, *t1*
273
274     - | *t0* = -*t1* (two's complement)
275
276   * - mul_i32/i64 *t0*, *t1*, *t2*
277
278     - | *t0* = *t1* * *t2*
279
280   * - div_i32/i64 *t0*, *t1*, *t2*
281
282     - | *t0* = *t1* / *t2* (signed)
283       | Undefined behavior if division by zero or overflow.
284
285   * - divu_i32/i64 *t0*, *t1*, *t2*
286
287     - | *t0* = *t1* / *t2* (unsigned)
288       | Undefined behavior if division by zero.
289
290   * - rem_i32/i64 *t0*, *t1*, *t2*
291
292     - | *t0* = *t1* % *t2* (signed)
293       | Undefined behavior if division by zero or overflow.
294
295   * - remu_i32/i64 *t0*, *t1*, *t2*
296
297     - | *t0* = *t1* % *t2* (unsigned)
298       | Undefined behavior if division by zero.
299
300
301Logical
302-------
303
304.. list-table::
305
306   * - and_i32/i64 *t0*, *t1*, *t2*
307
308     - | *t0* = *t1* & *t2*
309
310   * - or_i32/i64 *t0*, *t1*, *t2*
311
312     - | *t0* = *t1* | *t2*
313
314   * - xor_i32/i64 *t0*, *t1*, *t2*
315
316     - | *t0* = *t1* ^ *t2*
317
318   * - not_i32/i64 *t0*, *t1*
319
320     - | *t0* = ~\ *t1*
321
322   * - andc_i32/i64 *t0*, *t1*, *t2*
323
324     - | *t0* = *t1* & ~\ *t2*
325
326   * - eqv_i32/i64 *t0*, *t1*, *t2*
327
328     - | *t0* = ~(*t1* ^ *t2*), or equivalently, *t0* = *t1* ^ ~\ *t2*
329
330   * - nand_i32/i64 *t0*, *t1*, *t2*
331
332     - | *t0* = ~(*t1* & *t2*)
333
334   * - nor_i32/i64 *t0*, *t1*, *t2*
335
336     - | *t0* = ~(*t1* | *t2*)
337
338   * - orc_i32/i64 *t0*, *t1*, *t2*
339
340     - | *t0* = *t1* | ~\ *t2*
341
342   * - clz_i32/i64 *t0*, *t1*, *t2*
343
344     - | *t0* = *t1* ? clz(*t1*) : *t2*
345
346   * - ctz_i32/i64 *t0*, *t1*, *t2*
347
348     - | *t0* = *t1* ? ctz(*t1*) : *t2*
349
350   * - ctpop_i32/i64 *t0*, *t1*
351
352     - | *t0* = number of bits set in *t1*
353       |
354       | With *ctpop* short for "count population", matching
355       | the function name used in ``include/qemu/host-utils.h``.
356
357
358Shifts/Rotates
359--------------
360
361.. list-table::
362
363   * - shl_i32/i64 *t0*, *t1*, *t2*
364
365     - | *t0* = *t1* << *t2*
366       | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
367
368   * - shr_i32/i64 *t0*, *t1*, *t2*
369
370     - | *t0* = *t1* >> *t2* (unsigned)
371       | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
372
373   * - sar_i32/i64 *t0*, *t1*, *t2*
374
375     - | *t0* = *t1* >> *t2* (signed)
376       | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
377
378   * - rotl_i32/i64 *t0*, *t1*, *t2*
379
380     - | Rotation of *t2* bits to the left
381       | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
382
383   * - rotr_i32/i64 *t0*, *t1*, *t2*
384
385     - | Rotation of *t2* bits to the right.
386       | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
387
388
389Misc
390----
391
392.. list-table::
393
394   * - mov_i32/i64 *t0*, *t1*
395
396     - | *t0* = *t1*
397       | Move *t1* to *t0* (both operands must have the same type).
398
399   * - ext8s_i32/i64 *t0*, *t1*
400
401       ext8u_i32/i64 *t0*, *t1*
402
403       ext16s_i32/i64 *t0*, *t1*
404
405       ext16u_i32/i64 *t0*, *t1*
406
407       ext32s_i64 *t0*, *t1*
408
409       ext32u_i64 *t0*, *t1*
410
411     - | 8, 16 or 32 bit sign/zero extension (both operands must have the same type)
412
413   * - bswap16_i32/i64 *t0*, *t1*, *flags*
414
415     - | 16 bit byte swap on the low bits of a 32/64 bit input.
416       |
417       | If *flags* & ``TCG_BSWAP_IZ``, then *t1* is known to be zero-extended from bit 15.
418       | If *flags* & ``TCG_BSWAP_OZ``, then *t0* will be zero-extended from bit 15.
419       | If *flags* & ``TCG_BSWAP_OS``, then *t0* will be sign-extended from bit 15.
420       |
421       | If neither ``TCG_BSWAP_OZ`` nor ``TCG_BSWAP_OS`` are set, then the bits of *t0* above bit 15 may contain any value.
422
423   * - bswap32_i64 *t0*, *t1*, *flags*
424
425     - | 32 bit byte swap on a 64-bit value.  The flags are the same as for bswap16,
426         except they apply from bit 31 instead of bit 15.
427
428   * - bswap32_i32 *t0*, *t1*, *flags*
429
430       bswap64_i64 *t0*, *t1*, *flags*
431
432     - | 32/64 bit byte swap. The flags are ignored, but still present
433         for consistency with the other bswap opcodes.
434
435   * - discard_i32/i64 *t0*
436
437     - | Indicate that the value of *t0* won't be used later. It is useful to
438         force dead code elimination.
439
440   * - deposit_i32/i64 *dest*, *t1*, *t2*, *pos*, *len*
441
442     - | Deposit *t2* as a bitfield into *t1*, placing the result in *dest*.
443       |
444       | The bitfield is described by *pos*/*len*, which are immediate values:
445       |
446       |     *len* - the length of the bitfield
447       |     *pos* - the position of the first bit, counting from the LSB
448       |
449       | For example, "deposit_i32 dest, t1, t2, 8, 4" indicates a 4-bit field
450         at bit 8. This operation would be equivalent to
451       |
452       |     *dest* = (*t1* & ~0x0f00) | ((*t2* << 8) & 0x0f00)
453
454   * - extract_i32/i64 *dest*, *t1*, *pos*, *len*
455
456       sextract_i32/i64 *dest*, *t1*, *pos*, *len*
457
458     - | Extract a bitfield from *t1*, placing the result in *dest*.
459       |
460       | The bitfield is described by *pos*/*len*, which are immediate values,
461         as above for deposit.  For extract_*, the result will be extended
462         to the left with zeros; for sextract_*, the result will be extended
463         to the left with copies of the bitfield sign bit at *pos* + *len* - 1.
464       |
465       | For example, "sextract_i32 dest, t1, 8, 4" indicates a 4-bit field
466         at bit 8. This operation would be equivalent to
467       |
468       |    *dest* = (*t1* << 20) >> 28
469       |
470       | (using an arithmetic right shift).
471
472   * - extract2_i32/i64 *dest*, *t1*, *t2*, *pos*
473
474     - | For N = {32,64}, extract an N-bit quantity from the concatenation
475         of *t2*:*t1*, beginning at *pos*. The tcg_gen_extract2_{i32,i64} expander
476         accepts 0 <= *pos* <= N as inputs. The backend code generator will
477         not see either 0 or N as inputs for these opcodes.
478
479   * - extrl_i64_i32 *t0*, *t1*
480
481     - | For 64-bit hosts only, extract the low 32-bits of input *t1* and place it
482         into 32-bit output *t0*.  Depending on the host, this may be a simple move,
483         or may require additional canonicalization.
484
485   * - extrh_i64_i32 *t0*, *t1*
486
487     - | For 64-bit hosts only, extract the high 32-bits of input *t1* and place it
488         into 32-bit output *t0*.  Depending on the host, this may be a simple shift,
489         or may require additional canonicalization.
490
491
492Conditional moves
493-----------------
494
495.. list-table::
496
497   * - setcond_i32/i64 *dest*, *t1*, *t2*, *cond*
498
499     - | *dest* = (*t1* *cond* *t2*)
500       |
501       | Set *dest* to 1 if (*t1* *cond* *t2*) is true, otherwise set to 0.
502
503   * - negsetcond_i32/i64 *dest*, *t1*, *t2*, *cond*
504
505     - | *dest* = -(*t1* *cond* *t2*)
506       |
507       | Set *dest* to -1 if (*t1* *cond* *t2*) is true, otherwise set to 0.
508
509   * - movcond_i32/i64 *dest*, *c1*, *c2*, *v1*, *v2*, *cond*
510
511     - | *dest* = (*c1* *cond* *c2* ? *v1* : *v2*)
512       |
513       | Set *dest* to *v1* if (*c1* *cond* *c2*) is true, otherwise set to *v2*.
514
515
516Type conversions
517----------------
518
519.. list-table::
520
521   * - ext_i32_i64 *t0*, *t1*
522
523     - | Convert *t1* (32 bit) to *t0* (64 bit) and does sign extension
524
525   * - extu_i32_i64 *t0*, *t1*
526
527     - | Convert *t1* (32 bit) to *t0* (64 bit) and does zero extension
528
529   * - trunc_i64_i32 *t0*, *t1*
530
531     - | Truncate *t1* (64 bit) to *t0* (32 bit)
532
533   * - concat_i32_i64 *t0*, *t1*, *t2*
534
535     - | Construct *t0* (64-bit) taking the low half from *t1* (32 bit) and the high half
536         from *t2* (32 bit).
537
538   * - concat32_i64 *t0*, *t1*, *t2*
539
540     - | Construct *t0* (64-bit) taking the low half from *t1* (64 bit) and the high half
541         from *t2* (64 bit).
542
543
544Load/Store
545----------
546
547.. list-table::
548
549   * - ld_i32/i64 *t0*, *t1*, *offset*
550
551       ld8s_i32/i64 *t0*, *t1*, *offset*
552
553       ld8u_i32/i64 *t0*, *t1*, *offset*
554
555       ld16s_i32/i64 *t0*, *t1*, *offset*
556
557       ld16u_i32/i64 *t0*, *t1*, *offset*
558
559       ld32s_i64 t0, *t1*, *offset*
560
561       ld32u_i64 t0, *t1*, *offset*
562
563     - | *t0* = read(*t1* + *offset*)
564       |
565       | Load 8, 16, 32 or 64 bits with or without sign extension from host memory.
566         *offset* must be a constant.
567
568   * - st_i32/i64 *t0*, *t1*, *offset*
569
570       st8_i32/i64 *t0*, *t1*, *offset*
571
572       st16_i32/i64 *t0*, *t1*, *offset*
573
574       st32_i64 *t0*, *t1*, *offset*
575
576     - | write(*t0*, *t1* + *offset*)
577       |
578       | Write 8, 16, 32 or 64 bits to host memory.
579
580All this opcodes assume that the pointed host memory doesn't correspond
581to a global. In the latter case the behaviour is unpredictable.
582
583
584Multiword arithmetic support
585----------------------------
586
587.. list-table::
588
589   * - add2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high*
590
591       sub2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high*
592
593     - | Similar to add/sub, except that the double-word inputs *t1* and *t2* are
594         formed from two single-word arguments, and the double-word output *t0*
595         is returned in two single-word outputs.
596
597   * - mulu2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2*
598
599     - | Similar to mul, except two unsigned inputs *t1* and *t2* yielding the full
600         double-word product *t0*. The latter is returned in two single-word outputs.
601
602   * - muls2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2*
603
604     - | Similar to mulu2, except the two inputs *t1* and *t2* are signed.
605
606   * - mulsh_i32/i64 *t0*, *t1*, *t2*
607
608       muluh_i32/i64 *t0*, *t1*, *t2*
609
610     - | Provide the high part of a signed or unsigned multiply, respectively.
611       |
612       | If mulu2/muls2 are not provided by the backend, the tcg-op generator
613         can obtain the same results by emitting a pair of opcodes, mul + muluh/mulsh.
614
615
616Memory Barrier support
617----------------------
618
619.. list-table::
620
621   * - mb *<$arg>*
622
623     - | Generate a target memory barrier instruction to ensure memory ordering
624         as being  enforced by a corresponding guest memory barrier instruction.
625       |
626       | The ordering enforced by the backend may be stricter than the ordering
627         required by the guest. It cannot be weaker. This opcode takes a constant
628         argument which is required to generate the appropriate barrier
629         instruction. The backend should take care to emit the target barrier
630         instruction only when necessary i.e., for SMP guests and when MTTCG is
631         enabled.
632       |
633       | The guest translators should generate this opcode for all guest instructions
634         which have ordering side effects.
635       |
636       | Please see :ref:`atomics-ref` for more information on memory barriers.
637
638
63964-bit guest on 32-bit host support
640-----------------------------------
641
642The following opcodes are internal to TCG.  Thus they are to be implemented by
64332-bit host code generators, but are not to be emitted by guest translators.
644They are emitted as needed by inline functions within ``tcg-op.h``.
645
646.. list-table::
647
648   * - brcond2_i32 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *cond*, *label*
649
650     - | Similar to brcond, except that the 64-bit values *t0* and *t1*
651         are formed from two 32-bit arguments.
652
653   * - setcond2_i32 *dest*, *t1_low*, *t1_high*, *t2_low*, *t2_high*, *cond*
654
655     - | Similar to setcond, except that the 64-bit values *t1* and *t2* are
656         formed from two 32-bit arguments. The result is a 32-bit value.
657
658
659QEMU specific operations
660------------------------
661
662.. list-table::
663
664   * - exit_tb *t0*
665
666     - | Exit the current TB and return the value *t0* (word type).
667
668   * - goto_tb *index*
669
670     - | Exit the current TB and jump to the TB index *index* (constant) if the
671         current TB was linked to this TB. Otherwise execute the next
672         instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued
673         at most once with each slot index per TB.
674
675   * - lookup_and_goto_ptr *tb_addr*
676
677     - | Look up a TB address *tb_addr* and jump to it if valid. If not valid,
678         jump to the TCG epilogue to go back to the exec loop.
679       |
680       | This operation is optional. If the TCG backend does not implement the
681         goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0).
682
683   * - qemu_ld_i32/i64/i128 *t0*, *t1*, *flags*, *memidx*
684
685       qemu_st_i32/i64/i128 *t0*, *t1*, *flags*, *memidx*
686
687       qemu_st8_i32 *t0*, *t1*, *flags*, *memidx*
688
689     - | Load data at the guest address *t1* into *t0*, or store data in *t0* at guest
690         address *t1*.  The _i32/_i64/_i128 size applies to the size of the input/output
691         register *t0* only.  The address *t1* is always sized according to the guest,
692         and the width of the memory operation is controlled by *flags*.
693       |
694       | Both *t0* and *t1* may be split into little-endian ordered pairs of registers
695         if dealing with 64-bit quantities on a 32-bit host, or 128-bit quantities on
696         a 64-bit host.
697       |
698       | The *memidx* selects the qemu tlb index to use (e.g. user or kernel access).
699         The flags are the MemOp bits, selecting the sign, width, and endianness
700         of the memory access.
701       |
702       | For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a
703         64-bit memory access specified in *flags*.
704       |
705       | For qemu_ld/st_i128, these are only supported for a 64-bit host.
706       |
707       | For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of
708         the memory operation is known to be 8-bit.  This allows the backend to
709         provide a different set of register constraints.
710
711
712Host vector operations
713----------------------
714
715All of the vector ops have two parameters, ``TCGOP_VECL`` & ``TCGOP_VECE``.
716The former specifies the length of the vector in log2 64-bit units; the
717latter specifies the length of the element (if applicable) in log2 8-bit units.
718E.g. VECL = 1 -> 64 << 1 -> v128, and VECE = 2 -> 1 << 2 -> i32.
719
720.. list-table::
721
722   * - mov_vec *v0*, *v1*
723
724       ld_vec *v0*, *t1*
725
726       st_vec *v0*, *t1*
727
728     - | Move, load and store.
729
730   * - dup_vec *v0*, *r1*
731
732     - | Duplicate the low N bits of *r1* into VECL/VECE copies across *v0*.
733
734   * - dupi_vec *v0*, *c*
735
736     - | Similarly, for a constant.
737       | Smaller values will be replicated to host register size by the expanders.
738
739   * - dup2_vec *v0*, *r1*, *r2*
740
741     - | Duplicate *r2*:*r1* into VECL/64 copies across *v0*. This opcode is
742         only present for 32-bit hosts.
743
744   * - add_vec *v0*, *v1*, *v2*
745
746     - | *v0* = *v1* + *v2*, in elements across the vector.
747
748   * - sub_vec *v0*, *v1*, *v2*
749
750     - | Similarly, *v0* = *v1* - *v2*.
751
752   * - mul_vec *v0*, *v1*, *v2*
753
754     - | Similarly, *v0* = *v1* * *v2*.
755
756   * - neg_vec *v0*, *v1*
757
758     - | Similarly, *v0* = -*v1*.
759
760   * - abs_vec *v0*, *v1*
761
762     - | Similarly, *v0* = *v1* < 0 ? -*v1* : *v1*, in elements across the vector.
763
764   * - smin_vec *v0*, *v1*, *v2*
765
766       umin_vec *v0*, *v1*, *v2*
767
768     - | Similarly, *v0* = MIN(*v1*, *v2*), for signed and unsigned element types.
769
770   * - smax_vec *v0*, *v1*, *v2*
771
772       umax_vec *v0*, *v1*, *v2*
773
774     - | Similarly, *v0* = MAX(*v1*, *v2*), for signed and unsigned element types.
775
776   * - ssadd_vec *v0*, *v1*, *v2*
777
778       sssub_vec *v0*, *v1*, *v2*
779
780       usadd_vec *v0*, *v1*, *v2*
781
782       ussub_vec *v0*, *v1*, *v2*
783
784     - | Signed and unsigned saturating addition and subtraction.
785       |
786       | If the true result is not representable within the element type, the
787         element is set to the minimum or maximum value for the type.
788
789   * - and_vec *v0*, *v1*, *v2*
790
791       or_vec *v0*, *v1*, *v2*
792
793       xor_vec *v0*, *v1*, *v2*
794
795       andc_vec *v0*, *v1*, *v2*
796
797       orc_vec *v0*, *v1*, *v2*
798
799       not_vec *v0*, *v1*
800
801     - | Similarly, logical operations with and without complement.
802       |
803       | Note that VECE is unused.
804
805   * - shli_vec *v0*, *v1*, *i2*
806
807       shls_vec *v0*, *v1*, *s2*
808
809     - | Shift all elements from v1 by a scalar *i2*/*s2*. I.e.
810
811       .. code-block:: c
812
813          for (i = 0; i < VECL/VECE; ++i) {
814              v0[i] = v1[i] << s2;
815          }
816
817   * - shri_vec *v0*, *v1*, *i2*
818
819       sari_vec *v0*, *v1*, *i2*
820
821       rotli_vec *v0*, *v1*, *i2*
822
823       shrs_vec *v0*, *v1*, *s2*
824
825       sars_vec *v0*, *v1*, *s2*
826
827     - | Similarly for logical and arithmetic right shift, and left rotate.
828
829   * - shlv_vec *v0*, *v1*, *v2*
830
831     - | Shift elements from *v1* by elements from *v2*. I.e.
832
833       .. code-block:: c
834
835          for (i = 0; i < VECL/VECE; ++i) {
836              v0[i] = v1[i] << v2[i];
837          }
838
839   * - shrv_vec *v0*, *v1*, *v2*
840
841       sarv_vec *v0*, *v1*, *v2*
842
843       rotlv_vec *v0*, *v1*, *v2*
844
845       rotrv_vec *v0*, *v1*, *v2*
846
847     - | Similarly for logical and arithmetic right shift, and rotates.
848
849   * - cmp_vec *v0*, *v1*, *v2*, *cond*
850
851     - | Compare vectors by element, storing -1 for true and 0 for false.
852
853   * - bitsel_vec *v0*, *v1*, *v2*, *v3*
854
855     - | Bitwise select, *v0* = (*v2* & *v1*) | (*v3* & ~\ *v1*), across the entire vector.
856
857   * - cmpsel_vec *v0*, *c1*, *c2*, *v3*, *v4*, *cond*
858
859     - | Select elements based on comparison results:
860
861       .. code-block:: c
862
863          for (i = 0; i < n; ++i) {
864              v0[i] = (c1[i] cond c2[i]) ? v3[i] : v4[i].
865          }
866
867**Note 1**: Some shortcuts are defined when the last operand is known to be
868a constant (e.g. addi for add, movi for mov).
869
870**Note 2**: When using TCG, the opcodes must never be generated directly
871as some of them may not be available as "real" opcodes. Always use the
872function tcg_gen_xxx(args).
873
874
875Backend
876=======
877
878``tcg-target.h`` contains the target specific definitions. ``tcg-target.c.inc``
879contains the target specific code; it is #included by ``tcg/tcg.c``, rather
880than being a standalone C file.
881
882Assumptions
883-----------
884
885The target word size (``TCG_TARGET_REG_BITS``) is expected to be 32 bit or
88664 bit. It is expected that the pointer has the same size as the word.
887
888On a 32 bit target, all 64 bit operations are converted to 32 bits. A
889few specific operations must be implemented to allow it (see add2_i32,
890sub2_i32, brcond2_i32).
891
892On a 64 bit target, the values are transferred between 32 and 64-bit
893registers using the following ops:
894
895- extrl_i64_i32
896- extrh_i64_i32
897- ext_i32_i64
898- extu_i32_i64
899
900They ensure that the values are correctly truncated or extended when
901moved from a 32-bit to a 64-bit register or vice-versa. Note that the
902extrl_i64_i32 and extrh_i64_i32 are optional ops. It is not necessary
903to implement them if all the following conditions are met:
904
905- 64-bit registers can hold 32-bit values
906- 32-bit values in a 64-bit register do not need to stay zero or
907  sign extended
908- all 32-bit TCG ops ignore the high part of 64-bit registers
909
910Floating point operations are not supported in this version. A
911previous incarnation of the code generator had full support of them,
912but it is better to concentrate on integer operations first.
913
914Constraints
915----------------
916
917GCC like constraints are used to define the constraints of every
918instruction. Memory constraints are not supported in this
919version. Aliases are specified in the input operands as for GCC.
920
921The same register may be used for both an input and an output, even when
922they are not explicitly aliased.  If an op expands to multiple target
923instructions then care must be taken to avoid clobbering input values.
924GCC style "early clobber" outputs are supported, with '``&``'.
925
926A target can define specific register or constant constraints. If an
927operation uses a constant input constraint which does not allow all
928constants, it must also accept registers in order to have a fallback.
929The constraint '``i``' is defined generically to accept any constant.
930The constraint '``r``' is not defined generically, but is consistently
931used by each backend to indicate all registers.
932
933The movi_i32 and movi_i64 operations must accept any constants.
934
935The mov_i32 and mov_i64 operations must accept any registers of the
936same type.
937
938The ld/st/sti instructions must accept signed 32 bit constant offsets.
939This can be implemented by reserving a specific register in which to
940compute the address if the offset is too big.
941
942The ld/st instructions must accept any destination (ld) or source (st)
943register.
944
945The sti instruction may fail if it cannot store the given constant.
946
947Function call assumptions
948-------------------------
949
950- The only supported types for parameters and return value are: 32 and
951  64 bit integers and pointer.
952- The stack grows downwards.
953- The first N parameters are passed in registers.
954- The next parameters are passed on the stack by storing them as words.
955- Some registers are clobbered during the call.
956- The function can return 0 or 1 value in registers. On a 32 bit
957  target, functions must be able to return 2 values in registers for
958  64 bit return type.
959
960
961Recommended coding rules for best performance
962=============================================
963
964- Use globals to represent the parts of the QEMU CPU state which are
965  often modified, e.g. the integer registers and the condition
966  codes. TCG will be able to use host registers to store them.
967
968- Don't hesitate to use helpers for complicated or seldom used guest
969  instructions. There is little performance advantage in using TCG to
970  implement guest instructions taking more than about twenty TCG
971  instructions. Note that this rule of thumb is more applicable to
972  helpers doing complex logic or arithmetic, where the C compiler has
973  scope to do a good job of optimisation; it is less relevant where
974  the instruction is mostly doing loads and stores, and in those cases
975  inline TCG may still be faster for longer sequences.
976
977- Use the 'discard' instruction if you know that TCG won't be able to
978  prove that a given global is "dead" at a given program point. The
979  x86 guest uses it to improve the condition codes optimisation.
980