1.. _tcg-ops-ref: 2 3******************************* 4TCG Intermediate Representation 5******************************* 6 7Introduction 8============ 9 10TCG (Tiny Code Generator) began as a generic backend for a C compiler. 11It was simplified to be used in QEMU. It also has its roots in the 12QOP code generator written by Paul Brook. 13 14Definitions 15=========== 16 17The TCG *target* is the architecture for which we generate the code. 18It is of course not the same as the "target" of QEMU which is the 19emulated architecture. As TCG started as a generic C backend used 20for cross compiling, the assumption was that TCG target might be 21different from the host, although this is never the case for QEMU. 22 23In this document, we use *guest* to specify what architecture we are 24emulating; *target* always means the TCG target, the machine on which 25we are running QEMU. 26 27An operation with *undefined behavior* may result in a crash. 28 29An operation with *unspecified behavior* shall not crash. However, 30the result may be one of several possibilities so may be considered 31an *undefined result*. 32 33Basic Blocks 34============ 35 36A TCG *basic block* is a single entry, multiple exit region which 37corresponds to a list of instructions terminated by a label, or 38any branch instruction. 39 40A TCG *extended basic block* is a single entry, multiple exit region 41which corresponds to a list of instructions terminated by a label or 42an unconditional branch. Specifically, an extended basic block is 43a sequence of basic blocks connected by the fall-through paths of 44zero or more conditional branch instructions. 45 46Operations 47========== 48 49TCG instructions or *ops* operate on TCG *variables*, both of which 50are strongly typed. Each instruction has a fixed number of output 51variable operands, input variable operands and constant operands. 52Vector instructions have a field specifying the element size within 53the vector. The notable exception is the call instruction which has 54a variable number of outputs and inputs. 55 56In the textual form, output operands usually come first, followed by 57input operands, followed by constant operands. The output type is 58included in the instruction name. Constants are prefixed with a '$'. 59 60.. code-block:: none 61 62 add_i32 t0, t1, t2 /* (t0 <- t1 + t2) */ 63 64Variables 65========= 66 67* ``TEMP_FIXED`` 68 69 There is one TCG *fixed global* variable, ``cpu_env``, which is 70 live in all translation blocks, and holds a pointer to ``CPUArchState``. 71 This variable is held in a host cpu register at all times in all 72 translation blocks. 73 74* ``TEMP_GLOBAL`` 75 76 A TCG *global* is a variable which is live in all translation blocks, 77 and corresponds to memory location that is within ``CPUArchState``. 78 These may be specified as an offset from ``cpu_env``, in which case 79 they are called *direct globals*, or may be specified as an offset 80 from a direct global, in which case they are called *indirect globals*. 81 Even indirect globals should still reference memory within 82 ``CPUArchState``. All TCG globals are defined during 83 ``TCGCPUOps.initialize``, before any translation blocks are generated. 84 85* ``TEMP_CONST`` 86 87 A TCG *constant* is a variable which is live throughout the entire 88 translation block, and contains a constant value. These variables 89 are allocated on demand during translation and are hashed so that 90 there is exactly one variable holding a given value. 91 92* ``TEMP_TB`` 93 94 A TCG *translation block temporary* is a variable which is live 95 throughout the entire translation block, but dies on any exit. 96 These temporaries are allocated explicitly during translation. 97 98* ``TEMP_EBB`` 99 100 A TCG *extended basic block temporary* is a variable which is live 101 throughout an extended basic block, but dies on any exit. 102 These temporaries are allocated explicitly during translation. 103 104Types 105===== 106 107* ``TCG_TYPE_I32`` 108 109 A 32-bit integer. 110 111* ``TCG_TYPE_I64`` 112 113 A 64-bit integer. For 32-bit hosts, such variables are split into a pair 114 of variables with ``type=TCG_TYPE_I32`` and ``base_type=TCG_TYPE_I64``. 115 The ``temp_subindex`` for each indicates where it falls within the 116 host-endian representation. 117 118* ``TCG_TYPE_PTR`` 119 120 An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size 121 of a pointer for the host. 122 123* ``TCG_TYPE_REG`` 124 125 An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size 126 of the integer registers for the host. This may be larger 127 than ``TCG_TYPE_PTR`` depending on the host ABI. 128 129* ``TCG_TYPE_I128`` 130 131 A 128-bit integer. For all hosts, such variables are split into a number 132 of variables with ``type=TCG_TYPE_REG`` and ``base_type=TCG_TYPE_I128``. 133 The ``temp_subindex`` for each indicates where it falls within the 134 host-endian representation. 135 136* ``TCG_TYPE_V64`` 137 138 A 64-bit vector. This type is valid only if the TCG target 139 sets ``TCG_TARGET_HAS_v64``. 140 141* ``TCG_TYPE_V128`` 142 143 A 128-bit vector. This type is valid only if the TCG target 144 sets ``TCG_TARGET_HAS_v128``. 145 146* ``TCG_TYPE_V256`` 147 148 A 256-bit vector. This type is valid only if the TCG target 149 sets ``TCG_TARGET_HAS_v256``. 150 151Helpers 152======= 153 154Helpers are registered in a guest-specific ``helper.h``, 155which is processed to generate ``tcg_gen_helper_*`` functions. 156With these functions it is possible to call a function taking 157i32, i64, i128 or pointer types. 158 159By default, before calling a helper, all globals are stored at their 160canonical location. By default, the helper is allowed to modify the 161CPU state (including the state represented by tcg globals) 162or may raise an exception. This default can be overridden using the 163following function modifiers: 164 165* ``TCG_CALL_NO_WRITE_GLOBALS`` 166 167 The helper does not modify any globals, but may read them. 168 Globals will be saved to their canonical location before calling helpers, 169 but need not be reloaded afterwards. 170 171* ``TCG_CALL_NO_READ_GLOBALS`` 172 173 The helper does not read globals, either directly or via an exception. 174 They will not be saved to their canonical locations before calling 175 the helper. This implies ``TCG_CALL_NO_WRITE_GLOBALS``. 176 177* ``TCG_CALL_NO_SIDE_EFFECTS`` 178 179 The call to the helper function may be removed if the return value is 180 not used. This means that it may not modify any CPU state nor may it 181 raise an exception. 182 183Code Optimizations 184================== 185 186When generating instructions, you can count on at least the following 187optimizations: 188 189- Single instructions are simplified, e.g. 190 191 .. code-block:: none 192 193 and_i32 t0, t0, $0xffffffff 194 195 is suppressed. 196 197- A liveness analysis is done at the basic block level. The 198 information is used to suppress moves from a dead variable to 199 another one. It is also used to remove instructions which compute 200 dead results. The later is especially useful for condition code 201 optimization in QEMU. 202 203 In the following example: 204 205 .. code-block:: none 206 207 add_i32 t0, t1, t2 208 add_i32 t0, t0, $1 209 mov_i32 t0, $1 210 211 only the last instruction is kept. 212 213 214Instruction Reference 215===================== 216 217Function call 218------------- 219 220.. list-table:: 221 222 * - call *<ret>* *<params>* ptr 223 224 - | call function 'ptr' (pointer type) 225 | 226 | *<ret>* optional 32 bit or 64 bit return value 227 | *<params>* optional 32 bit or 64 bit parameters 228 229Jumps/Labels 230------------ 231 232.. list-table:: 233 234 * - set_label $label 235 236 - | Define label 'label' at the current program point. 237 238 * - br $label 239 240 - | Jump to label. 241 242 * - brcond_i32/i64 *t0*, *t1*, *cond*, *label* 243 244 - | Conditional jump if *t0* *cond* *t1* is true. *cond* can be: 245 | 246 | ``TCG_COND_EQ`` 247 | ``TCG_COND_NE`` 248 | ``TCG_COND_LT /* signed */`` 249 | ``TCG_COND_GE /* signed */`` 250 | ``TCG_COND_LE /* signed */`` 251 | ``TCG_COND_GT /* signed */`` 252 | ``TCG_COND_LTU /* unsigned */`` 253 | ``TCG_COND_GEU /* unsigned */`` 254 | ``TCG_COND_LEU /* unsigned */`` 255 | ``TCG_COND_GTU /* unsigned */`` 256 | ``TCG_COND_TSTEQ /* t1 & t2 == 0 */`` 257 | ``TCG_COND_TSTNE /* t1 & t2 != 0 */`` 258 259Arithmetic 260---------- 261 262.. list-table:: 263 264 * - add *t0*, *t1*, *t2* 265 266 - | *t0* = *t1* + *t2* 267 268 * - sub *t0*, *t1*, *t2* 269 270 - | *t0* = *t1* - *t2* 271 272 * - neg *t0*, *t1* 273 274 - | *t0* = -*t1* (two's complement) 275 276 * - mul *t0*, *t1*, *t2* 277 278 - | *t0* = *t1* * *t2* 279 280 * - divs *t0*, *t1*, *t2* 281 282 - | *t0* = *t1* / *t2* (signed) 283 | Undefined behavior if division by zero or overflow. 284 285 * - divu *t0*, *t1*, *t2* 286 287 - | *t0* = *t1* / *t2* (unsigned) 288 | Undefined behavior if division by zero. 289 290 * - rems *t0*, *t1*, *t2* 291 292 - | *t0* = *t1* % *t2* (signed) 293 | Undefined behavior if division by zero or overflow. 294 295 * - remu *t0*, *t1*, *t2* 296 297 - | *t0* = *t1* % *t2* (unsigned) 298 | Undefined behavior if division by zero. 299 300 * - divs2 *q*, *r*, *nl*, *nh*, *d* 301 302 - | *q* = *nh:nl* / *d* (signed) 303 | *r* = *nh:nl* % *d* 304 | Undefined behaviour if division by zero, or the double-word 305 numerator divided by the single-word divisor does not fit 306 within the single-word quotient. The code generator will 307 pass *nh* as a simple sign-extension of *nl*, so the only 308 overflow should be *INT_MIN* / -1. 309 310 * - divu2 *q*, *r*, *nl*, *nh*, *d* 311 312 - | *q* = *nh:nl* / *d* (unsigned) 313 | *r* = *nh:nl* % *d* 314 | Undefined behaviour if division by zero, or the double-word 315 numerator divided by the single-word divisor does not fit 316 within the single-word quotient. The code generator will 317 pass 0 to *nh* to make a simple zero-extension of *nl*, 318 so overflow should never occur. 319 320Logical 321------- 322 323.. list-table:: 324 325 * - and *t0*, *t1*, *t2* 326 327 - | *t0* = *t1* & *t2* 328 329 * - or *t0*, *t1*, *t2* 330 331 - | *t0* = *t1* | *t2* 332 333 * - xor *t0*, *t1*, *t2* 334 335 - | *t0* = *t1* ^ *t2* 336 337 * - not *t0*, *t1* 338 339 - | *t0* = ~\ *t1* 340 341 * - andc *t0*, *t1*, *t2* 342 343 - | *t0* = *t1* & ~\ *t2* 344 345 * - eqv *t0*, *t1*, *t2* 346 347 - | *t0* = ~(*t1* ^ *t2*), or equivalently, *t0* = *t1* ^ ~\ *t2* 348 349 * - nand *t0*, *t1*, *t2* 350 351 - | *t0* = ~(*t1* & *t2*) 352 353 * - nor *t0*, *t1*, *t2* 354 355 - | *t0* = ~(*t1* | *t2*) 356 357 * - orc *t0*, *t1*, *t2* 358 359 - | *t0* = *t1* | ~\ *t2* 360 361 * - clz *t0*, *t1*, *t2* 362 363 - | *t0* = *t1* ? clz(*t1*) : *t2* 364 365 * - ctz_i32/i64 *t0*, *t1*, *t2* 366 367 - | *t0* = *t1* ? ctz(*t1*) : *t2* 368 369 * - ctpop_i32/i64 *t0*, *t1* 370 371 - | *t0* = number of bits set in *t1* 372 | 373 | With *ctpop* short for "count population", matching 374 | the function name used in ``include/qemu/host-utils.h``. 375 376 377Shifts/Rotates 378-------------- 379 380.. list-table:: 381 382 * - shl *t0*, *t1*, *t2* 383 384 - | *t0* = *t1* << *t2* 385 | Unspecified behavior for negative or out-of-range shifts. 386 387 * - shr *t0*, *t1*, *t2* 388 389 - | *t0* = *t1* >> *t2* (unsigned) 390 | Unspecified behavior for negative or out-of-range shifts. 391 392 * - sar *t0*, *t1*, *t2* 393 394 - | *t0* = *t1* >> *t2* (signed) 395 | Unspecified behavior for negative or out-of-range shifts. 396 397 * - rotl *t0*, *t1*, *t2* 398 399 - | Rotation of *t2* bits to the left 400 | Unspecified behavior for negative or out-of-range shifts. 401 402 * - rotr *t0*, *t1*, *t2* 403 404 - | Rotation of *t2* bits to the right. 405 | Unspecified behavior for negative or out-of-range shifts. 406 407 408Misc 409---- 410 411.. list-table:: 412 413 * - mov *t0*, *t1* 414 415 - | *t0* = *t1* 416 | Move *t1* to *t0*. 417 418 * - bswap16_i32/i64 *t0*, *t1*, *flags* 419 420 - | 16 bit byte swap on the low bits of a 32/64 bit input. 421 | 422 | If *flags* & ``TCG_BSWAP_IZ``, then *t1* is known to be zero-extended from bit 15. 423 | If *flags* & ``TCG_BSWAP_OZ``, then *t0* will be zero-extended from bit 15. 424 | If *flags* & ``TCG_BSWAP_OS``, then *t0* will be sign-extended from bit 15. 425 | 426 | If neither ``TCG_BSWAP_OZ`` nor ``TCG_BSWAP_OS`` are set, then the bits of *t0* above bit 15 may contain any value. 427 428 * - bswap32_i64 *t0*, *t1*, *flags* 429 430 - | 32 bit byte swap on a 64-bit value. The flags are the same as for bswap16, 431 except they apply from bit 31 instead of bit 15. 432 433 * - bswap32_i32 *t0*, *t1*, *flags* 434 435 bswap64_i64 *t0*, *t1*, *flags* 436 437 - | 32/64 bit byte swap. The flags are ignored, but still present 438 for consistency with the other bswap opcodes. 439 440 * - discard_i32/i64 *t0* 441 442 - | Indicate that the value of *t0* won't be used later. It is useful to 443 force dead code elimination. 444 445 * - deposit_i32/i64 *dest*, *t1*, *t2*, *pos*, *len* 446 447 - | Deposit *t2* as a bitfield into *t1*, placing the result in *dest*. 448 | 449 | The bitfield is described by *pos*/*len*, which are immediate values: 450 | 451 | *len* - the length of the bitfield 452 | *pos* - the position of the first bit, counting from the LSB 453 | 454 | For example, "deposit_i32 dest, t1, t2, 8, 4" indicates a 4-bit field 455 at bit 8. This operation would be equivalent to 456 | 457 | *dest* = (*t1* & ~0x0f00) | ((*t2* << 8) & 0x0f00) 458 459 * - extract_i32/i64 *dest*, *t1*, *pos*, *len* 460 461 sextract_i32/i64 *dest*, *t1*, *pos*, *len* 462 463 - | Extract a bitfield from *t1*, placing the result in *dest*. 464 | 465 | The bitfield is described by *pos*/*len*, which are immediate values, 466 as above for deposit. For extract_*, the result will be extended 467 to the left with zeros; for sextract_*, the result will be extended 468 to the left with copies of the bitfield sign bit at *pos* + *len* - 1. 469 | 470 | For example, "sextract_i32 dest, t1, 8, 4" indicates a 4-bit field 471 at bit 8. This operation would be equivalent to 472 | 473 | *dest* = (*t1* << 20) >> 28 474 | 475 | (using an arithmetic right shift). 476 477 * - extract2_i32/i64 *dest*, *t1*, *t2*, *pos* 478 479 - | For N = {32,64}, extract an N-bit quantity from the concatenation 480 of *t2*:*t1*, beginning at *pos*. The tcg_gen_extract2_{i32,i64} expander 481 accepts 0 <= *pos* <= N as inputs. The backend code generator will 482 not see either 0 or N as inputs for these opcodes. 483 484 * - extrl_i64_i32 *t0*, *t1* 485 486 - | For 64-bit hosts only, extract the low 32-bits of input *t1* and place it 487 into 32-bit output *t0*. Depending on the host, this may be a simple move, 488 or may require additional canonicalization. 489 490 * - extrh_i64_i32 *t0*, *t1* 491 492 - | For 64-bit hosts only, extract the high 32-bits of input *t1* and place it 493 into 32-bit output *t0*. Depending on the host, this may be a simple shift, 494 or may require additional canonicalization. 495 496 497Conditional moves 498----------------- 499 500.. list-table:: 501 502 * - setcond_i32/i64 *dest*, *t1*, *t2*, *cond* 503 504 - | *dest* = (*t1* *cond* *t2*) 505 | 506 | Set *dest* to 1 if (*t1* *cond* *t2*) is true, otherwise set to 0. 507 508 * - negsetcond_i32/i64 *dest*, *t1*, *t2*, *cond* 509 510 - | *dest* = -(*t1* *cond* *t2*) 511 | 512 | Set *dest* to -1 if (*t1* *cond* *t2*) is true, otherwise set to 0. 513 514 * - movcond_i32/i64 *dest*, *c1*, *c2*, *v1*, *v2*, *cond* 515 516 - | *dest* = (*c1* *cond* *c2* ? *v1* : *v2*) 517 | 518 | Set *dest* to *v1* if (*c1* *cond* *c2*) is true, otherwise set to *v2*. 519 520 521Type conversions 522---------------- 523 524.. list-table:: 525 526 * - ext_i32_i64 *t0*, *t1* 527 528 - | Convert *t1* (32 bit) to *t0* (64 bit) and does sign extension 529 530 * - extu_i32_i64 *t0*, *t1* 531 532 - | Convert *t1* (32 bit) to *t0* (64 bit) and does zero extension 533 534 * - trunc_i64_i32 *t0*, *t1* 535 536 - | Truncate *t1* (64 bit) to *t0* (32 bit) 537 538 * - concat_i32_i64 *t0*, *t1*, *t2* 539 540 - | Construct *t0* (64-bit) taking the low half from *t1* (32 bit) and the high half 541 from *t2* (32 bit). 542 543 * - concat32_i64 *t0*, *t1*, *t2* 544 545 - | Construct *t0* (64-bit) taking the low half from *t1* (64 bit) and the high half 546 from *t2* (64 bit). 547 548 549Load/Store 550---------- 551 552.. list-table:: 553 554 * - ld_i32/i64 *t0*, *t1*, *offset* 555 556 ld8s_i32/i64 *t0*, *t1*, *offset* 557 558 ld8u_i32/i64 *t0*, *t1*, *offset* 559 560 ld16s_i32/i64 *t0*, *t1*, *offset* 561 562 ld16u_i32/i64 *t0*, *t1*, *offset* 563 564 ld32s_i64 t0, *t1*, *offset* 565 566 ld32u_i64 t0, *t1*, *offset* 567 568 - | *t0* = read(*t1* + *offset*) 569 | 570 | Load 8, 16, 32 or 64 bits with or without sign extension from host memory. 571 *offset* must be a constant. 572 573 * - st_i32/i64 *t0*, *t1*, *offset* 574 575 st8_i32/i64 *t0*, *t1*, *offset* 576 577 st16_i32/i64 *t0*, *t1*, *offset* 578 579 st32_i64 *t0*, *t1*, *offset* 580 581 - | write(*t0*, *t1* + *offset*) 582 | 583 | Write 8, 16, 32 or 64 bits to host memory. 584 585All this opcodes assume that the pointed host memory doesn't correspond 586to a global. In the latter case the behaviour is unpredictable. 587 588 589Multiword arithmetic support 590---------------------------- 591 592.. list-table:: 593 594 * - add2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high* 595 596 sub2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high* 597 598 - | Similar to add/sub, except that the double-word inputs *t1* and *t2* are 599 formed from two single-word arguments, and the double-word output *t0* 600 is returned in two single-word outputs. 601 602 * - mulu2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2* 603 604 - | Similar to mul, except two unsigned inputs *t1* and *t2* yielding the full 605 double-word product *t0*. The latter is returned in two single-word outputs. 606 607 * - muls2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2* 608 609 - | Similar to mulu2, except the two inputs *t1* and *t2* are signed. 610 611 * - mulsh *t0*, *t1*, *t2* 612 613 muluh *t0*, *t1*, *t2* 614 615 - | Provide the high part of a signed or unsigned multiply, respectively. 616 | 617 | If mulu2/muls2 are not provided by the backend, the tcg-op generator 618 can obtain the same results by emitting a pair of opcodes, mul + muluh/mulsh. 619 620 621Memory Barrier support 622---------------------- 623 624.. list-table:: 625 626 * - mb *<$arg>* 627 628 - | Generate a target memory barrier instruction to ensure memory ordering 629 as being enforced by a corresponding guest memory barrier instruction. 630 | 631 | The ordering enforced by the backend may be stricter than the ordering 632 required by the guest. It cannot be weaker. This opcode takes a constant 633 argument which is required to generate the appropriate barrier 634 instruction. The backend should take care to emit the target barrier 635 instruction only when necessary i.e., for SMP guests and when MTTCG is 636 enabled. 637 | 638 | The guest translators should generate this opcode for all guest instructions 639 which have ordering side effects. 640 | 641 | Please see :ref:`atomics-ref` for more information on memory barriers. 642 643 64464-bit guest on 32-bit host support 645----------------------------------- 646 647The following opcodes are internal to TCG. Thus they are to be implemented by 64832-bit host code generators, but are not to be emitted by guest translators. 649They are emitted as needed by inline functions within ``tcg-op.h``. 650 651.. list-table:: 652 653 * - brcond2_i32 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *cond*, *label* 654 655 - | Similar to brcond, except that the 64-bit values *t0* and *t1* 656 are formed from two 32-bit arguments. 657 658 * - setcond2_i32 *dest*, *t1_low*, *t1_high*, *t2_low*, *t2_high*, *cond* 659 660 - | Similar to setcond, except that the 64-bit values *t1* and *t2* are 661 formed from two 32-bit arguments. The result is a 32-bit value. 662 663 664QEMU specific operations 665------------------------ 666 667.. list-table:: 668 669 * - exit_tb *t0* 670 671 - | Exit the current TB and return the value *t0* (word type). 672 673 * - goto_tb *index* 674 675 - | Exit the current TB and jump to the TB index *index* (constant) if the 676 current TB was linked to this TB. Otherwise execute the next 677 instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued 678 at most once with each slot index per TB. 679 680 * - lookup_and_goto_ptr *tb_addr* 681 682 - | Look up a TB address *tb_addr* and jump to it if valid. If not valid, 683 jump to the TCG epilogue to go back to the exec loop. 684 | 685 | This operation is optional. If the TCG backend does not implement the 686 goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0). 687 688 * - qemu_ld_i32/i64/i128 *t0*, *t1*, *flags*, *memidx* 689 690 qemu_st_i32/i64/i128 *t0*, *t1*, *flags*, *memidx* 691 692 qemu_st8_i32 *t0*, *t1*, *flags*, *memidx* 693 694 - | Load data at the guest address *t1* into *t0*, or store data in *t0* at guest 695 address *t1*. The _i32/_i64/_i128 size applies to the size of the input/output 696 register *t0* only. The address *t1* is always sized according to the guest, 697 and the width of the memory operation is controlled by *flags*. 698 | 699 | Both *t0* and *t1* may be split into little-endian ordered pairs of registers 700 if dealing with 64-bit quantities on a 32-bit host, or 128-bit quantities on 701 a 64-bit host. 702 | 703 | The *memidx* selects the qemu tlb index to use (e.g. user or kernel access). 704 The flags are the MemOp bits, selecting the sign, width, and endianness 705 of the memory access. 706 | 707 | For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a 708 64-bit memory access specified in *flags*. 709 | 710 | For qemu_ld/st_i128, these are only supported for a 64-bit host. 711 | 712 | For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of 713 the memory operation is known to be 8-bit. This allows the backend to 714 provide a different set of register constraints. 715 716 717Host vector operations 718---------------------- 719 720All of the vector ops have two parameters, ``TCGOP_TYPE`` & ``TCGOP_VECE``. 721The former specifies the length of the vector as a TCGType; the latter 722specifies the length of the element (if applicable) in log2 8-bit units. 723 724.. list-table:: 725 726 * - mov_vec *v0*, *v1* 727 728 ld_vec *v0*, *t1* 729 730 st_vec *v0*, *t1* 731 732 - | Move, load and store. 733 734 * - dup_vec *v0*, *r1* 735 736 - | Duplicate the low N bits of *r1* into TYPE/VECE copies across *v0*. 737 738 * - dupi_vec *v0*, *c* 739 740 - | Similarly, for a constant. 741 | Smaller values will be replicated to host register size by the expanders. 742 743 * - dup2_vec *v0*, *r1*, *r2* 744 745 - | Duplicate *r2*:*r1* into TYPE/64 copies across *v0*. This opcode is 746 only present for 32-bit hosts. 747 748 * - add_vec *v0*, *v1*, *v2* 749 750 - | *v0* = *v1* + *v2*, in elements across the vector. 751 752 * - sub_vec *v0*, *v1*, *v2* 753 754 - | Similarly, *v0* = *v1* - *v2*. 755 756 * - mul_vec *v0*, *v1*, *v2* 757 758 - | Similarly, *v0* = *v1* * *v2*. 759 760 * - neg_vec *v0*, *v1* 761 762 - | Similarly, *v0* = -*v1*. 763 764 * - abs_vec *v0*, *v1* 765 766 - | Similarly, *v0* = *v1* < 0 ? -*v1* : *v1*, in elements across the vector. 767 768 * - smin_vec *v0*, *v1*, *v2* 769 770 umin_vec *v0*, *v1*, *v2* 771 772 - | Similarly, *v0* = MIN(*v1*, *v2*), for signed and unsigned element types. 773 774 * - smax_vec *v0*, *v1*, *v2* 775 776 umax_vec *v0*, *v1*, *v2* 777 778 - | Similarly, *v0* = MAX(*v1*, *v2*), for signed and unsigned element types. 779 780 * - ssadd_vec *v0*, *v1*, *v2* 781 782 sssub_vec *v0*, *v1*, *v2* 783 784 usadd_vec *v0*, *v1*, *v2* 785 786 ussub_vec *v0*, *v1*, *v2* 787 788 - | Signed and unsigned saturating addition and subtraction. 789 | 790 | If the true result is not representable within the element type, the 791 element is set to the minimum or maximum value for the type. 792 793 * - and_vec *v0*, *v1*, *v2* 794 795 or_vec *v0*, *v1*, *v2* 796 797 xor_vec *v0*, *v1*, *v2* 798 799 andc_vec *v0*, *v1*, *v2* 800 801 orc_vec *v0*, *v1*, *v2* 802 803 not_vec *v0*, *v1* 804 805 - | Similarly, logical operations with and without complement. 806 | 807 | Note that VECE is unused. 808 809 * - shli_vec *v0*, *v1*, *i2* 810 811 shls_vec *v0*, *v1*, *s2* 812 813 - | Shift all elements from v1 by a scalar *i2*/*s2*. I.e. 814 815 .. code-block:: c 816 817 for (i = 0; i < TYPE/VECE; ++i) { 818 v0[i] = v1[i] << s2; 819 } 820 821 * - shri_vec *v0*, *v1*, *i2* 822 823 sari_vec *v0*, *v1*, *i2* 824 825 rotli_vec *v0*, *v1*, *i2* 826 827 shrs_vec *v0*, *v1*, *s2* 828 829 sars_vec *v0*, *v1*, *s2* 830 831 - | Similarly for logical and arithmetic right shift, and left rotate. 832 833 * - shlv_vec *v0*, *v1*, *v2* 834 835 - | Shift elements from *v1* by elements from *v2*. I.e. 836 837 .. code-block:: c 838 839 for (i = 0; i < TYPE/VECE; ++i) { 840 v0[i] = v1[i] << v2[i]; 841 } 842 843 * - shrv_vec *v0*, *v1*, *v2* 844 845 sarv_vec *v0*, *v1*, *v2* 846 847 rotlv_vec *v0*, *v1*, *v2* 848 849 rotrv_vec *v0*, *v1*, *v2* 850 851 - | Similarly for logical and arithmetic right shift, and rotates. 852 853 * - cmp_vec *v0*, *v1*, *v2*, *cond* 854 855 - | Compare vectors by element, storing -1 for true and 0 for false. 856 857 * - bitsel_vec *v0*, *v1*, *v2*, *v3* 858 859 - | Bitwise select, *v0* = (*v2* & *v1*) | (*v3* & ~\ *v1*), across the entire vector. 860 861 * - cmpsel_vec *v0*, *c1*, *c2*, *v3*, *v4*, *cond* 862 863 - | Select elements based on comparison results: 864 865 .. code-block:: c 866 867 for (i = 0; i < n; ++i) { 868 v0[i] = (c1[i] cond c2[i]) ? v3[i] : v4[i]. 869 } 870 871**Note 1**: Some shortcuts are defined when the last operand is known to be 872a constant (e.g. addi for add, movi for mov). 873 874**Note 2**: When using TCG, the opcodes must never be generated directly 875as some of them may not be available as "real" opcodes. Always use the 876function tcg_gen_xxx(args). 877 878 879Backend 880======= 881 882``tcg-target.h`` contains the target specific definitions. ``tcg-target.c.inc`` 883contains the target specific code; it is #included by ``tcg/tcg.c``, rather 884than being a standalone C file. 885 886Assumptions 887----------- 888 889The target word size (``TCG_TARGET_REG_BITS``) is expected to be 32 bit or 89064 bit. It is expected that the pointer has the same size as the word. 891 892On a 32 bit target, all 64 bit operations are converted to 32 bits. A 893few specific operations must be implemented to allow it (see add2_i32, 894sub2_i32, brcond2_i32). 895 896On a 64 bit target, the values are transferred between 32 and 64-bit 897registers using the following ops: 898 899- extrl_i64_i32 900- extrh_i64_i32 901- ext_i32_i64 902- extu_i32_i64 903 904They ensure that the values are correctly truncated or extended when 905moved from a 32-bit to a 64-bit register or vice-versa. Note that the 906extrl_i64_i32 and extrh_i64_i32 are optional ops. It is not necessary 907to implement them if all the following conditions are met: 908 909- 64-bit registers can hold 32-bit values 910- 32-bit values in a 64-bit register do not need to stay zero or 911 sign extended 912- all 32-bit TCG ops ignore the high part of 64-bit registers 913 914Floating point operations are not supported in this version. A 915previous incarnation of the code generator had full support of them, 916but it is better to concentrate on integer operations first. 917 918Constraints 919---------------- 920 921GCC like constraints are used to define the constraints of every 922instruction. Memory constraints are not supported in this 923version. Aliases are specified in the input operands as for GCC. 924 925The same register may be used for both an input and an output, even when 926they are not explicitly aliased. If an op expands to multiple target 927instructions then care must be taken to avoid clobbering input values. 928GCC style "early clobber" outputs are supported, with '``&``'. 929 930A target can define specific register or constant constraints. If an 931operation uses a constant input constraint which does not allow all 932constants, it must also accept registers in order to have a fallback. 933The constraint '``i``' is defined generically to accept any constant. 934The constraint '``r``' is not defined generically, but is consistently 935used by each backend to indicate all registers. If ``TCG_REG_ZERO`` 936is defined by the backend, the constraint '``z``' is defined generically 937to map constant 0 to the hardware zero register. 938 939The movi_i32 and movi_i64 operations must accept any constants. 940 941The mov_i32 and mov_i64 operations must accept any registers of the 942same type. 943 944The ld/st/sti instructions must accept signed 32 bit constant offsets. 945This can be implemented by reserving a specific register in which to 946compute the address if the offset is too big. 947 948The ld/st instructions must accept any destination (ld) or source (st) 949register. 950 951The sti instruction may fail if it cannot store the given constant. 952 953Function call assumptions 954------------------------- 955 956- The only supported types for parameters and return value are: 32 and 957 64 bit integers and pointer. 958- The stack grows downwards. 959- The first N parameters are passed in registers. 960- The next parameters are passed on the stack by storing them as words. 961- Some registers are clobbered during the call. 962- The function can return 0 or 1 value in registers. On a 32 bit 963 target, functions must be able to return 2 values in registers for 964 64 bit return type. 965 966 967Recommended coding rules for best performance 968============================================= 969 970- Use globals to represent the parts of the QEMU CPU state which are 971 often modified, e.g. the integer registers and the condition 972 codes. TCG will be able to use host registers to store them. 973 974- Don't hesitate to use helpers for complicated or seldom used guest 975 instructions. There is little performance advantage in using TCG to 976 implement guest instructions taking more than about twenty TCG 977 instructions. Note that this rule of thumb is more applicable to 978 helpers doing complex logic or arithmetic, where the C compiler has 979 scope to do a good job of optimisation; it is less relevant where 980 the instruction is mostly doing loads and stores, and in those cases 981 inline TCG may still be faster for longer sequences. 982 983- Use the 'discard' instruction if you know that TCG won't be able to 984 prove that a given global is "dead" at a given program point. The 985 x86 guest uses it to improve the condition codes optimisation. 986