1.. _tcg-ops-ref: 2 3******************************* 4TCG Intermediate Representation 5******************************* 6 7Introduction 8============ 9 10TCG (Tiny Code Generator) began as a generic backend for a C compiler. 11It was simplified to be used in QEMU. It also has its roots in the 12QOP code generator written by Paul Brook. 13 14Definitions 15=========== 16 17The TCG *target* is the architecture for which we generate the code. 18It is of course not the same as the "target" of QEMU which is the 19emulated architecture. As TCG started as a generic C backend used 20for cross compiling, the assumption was that TCG target might be 21different from the host, although this is never the case for QEMU. 22 23In this document, we use *guest* to specify what architecture we are 24emulating; *target* always means the TCG target, the machine on which 25we are running QEMU. 26 27An operation with *undefined behavior* may result in a crash. 28 29An operation with *unspecified behavior* shall not crash. However, 30the result may be one of several possibilities so may be considered 31an *undefined result*. 32 33Basic Blocks 34============ 35 36A TCG *basic block* is a single entry, multiple exit region which 37corresponds to a list of instructions terminated by a label, or 38any branch instruction. 39 40A TCG *extended basic block* is a single entry, multiple exit region 41which corresponds to a list of instructions terminated by a label or 42an unconditional branch. Specifically, an extended basic block is 43a sequence of basic blocks connected by the fall-through paths of 44zero or more conditional branch instructions. 45 46Operations 47========== 48 49TCG instructions or *ops* operate on TCG *variables*, both of which 50are strongly typed. Each instruction has a fixed number of output 51variable operands, input variable operands and constant operands. 52Vector instructions have a field specifying the element size within 53the vector. The notable exception is the call instruction which has 54a variable number of outputs and inputs. 55 56In the textual form, output operands usually come first, followed by 57input operands, followed by constant operands. The output type is 58included in the instruction name. Constants are prefixed with a '$'. 59 60.. code-block:: none 61 62 add_i32 t0, t1, t2 /* (t0 <- t1 + t2) */ 63 64Variables 65========= 66 67* ``TEMP_FIXED`` 68 69 There is one TCG *fixed global* variable, ``cpu_env``, which is 70 live in all translation blocks, and holds a pointer to ``CPUArchState``. 71 This variable is held in a host cpu register at all times in all 72 translation blocks. 73 74* ``TEMP_GLOBAL`` 75 76 A TCG *global* is a variable which is live in all translation blocks, 77 and corresponds to memory location that is within ``CPUArchState``. 78 These may be specified as an offset from ``cpu_env``, in which case 79 they are called *direct globals*, or may be specified as an offset 80 from a direct global, in which case they are called *indirect globals*. 81 Even indirect globals should still reference memory within 82 ``CPUArchState``. All TCG globals are defined during 83 ``TCGCPUOps.initialize``, before any translation blocks are generated. 84 85* ``TEMP_CONST`` 86 87 A TCG *constant* is a variable which is live throughout the entire 88 translation block, and contains a constant value. These variables 89 are allocated on demand during translation and are hashed so that 90 there is exactly one variable holding a given value. 91 92* ``TEMP_TB`` 93 94 A TCG *translation block temporary* is a variable which is live 95 throughout the entire translation block, but dies on any exit. 96 These temporaries are allocated explicitly during translation. 97 98* ``TEMP_EBB`` 99 100 A TCG *extended basic block temporary* is a variable which is live 101 throughout an extended basic block, but dies on any exit. 102 These temporaries are allocated explicitly during translation. 103 104Types 105===== 106 107* ``TCG_TYPE_I32`` 108 109 A 32-bit integer. 110 111* ``TCG_TYPE_I64`` 112 113 A 64-bit integer. For 32-bit hosts, such variables are split into a pair 114 of variables with ``type=TCG_TYPE_I32`` and ``base_type=TCG_TYPE_I64``. 115 The ``temp_subindex`` for each indicates where it falls within the 116 host-endian representation. 117 118* ``TCG_TYPE_PTR`` 119 120 An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size 121 of a pointer for the host. 122 123* ``TCG_TYPE_REG`` 124 125 An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size 126 of the integer registers for the host. This may be larger 127 than ``TCG_TYPE_PTR`` depending on the host ABI. 128 129* ``TCG_TYPE_I128`` 130 131 A 128-bit integer. For all hosts, such variables are split into a number 132 of variables with ``type=TCG_TYPE_REG`` and ``base_type=TCG_TYPE_I128``. 133 The ``temp_subindex`` for each indicates where it falls within the 134 host-endian representation. 135 136* ``TCG_TYPE_V64`` 137 138 A 64-bit vector. This type is valid only if the TCG target 139 sets ``TCG_TARGET_HAS_v64``. 140 141* ``TCG_TYPE_V128`` 142 143 A 128-bit vector. This type is valid only if the TCG target 144 sets ``TCG_TARGET_HAS_v128``. 145 146* ``TCG_TYPE_V256`` 147 148 A 256-bit vector. This type is valid only if the TCG target 149 sets ``TCG_TARGET_HAS_v256``. 150 151Helpers 152======= 153 154Helpers are registered in a guest-specific ``helper.h``, 155which is processed to generate ``tcg_gen_helper_*`` functions. 156With these functions it is possible to call a function taking 157i32, i64, i128 or pointer types. 158 159By default, before calling a helper, all globals are stored at their 160canonical location. By default, the helper is allowed to modify the 161CPU state (including the state represented by tcg globals) 162or may raise an exception. This default can be overridden using the 163following function modifiers: 164 165* ``TCG_CALL_NO_WRITE_GLOBALS`` 166 167 The helper does not modify any globals, but may read them. 168 Globals will be saved to their canonical location before calling helpers, 169 but need not be reloaded afterwards. 170 171* ``TCG_CALL_NO_READ_GLOBALS`` 172 173 The helper does not read globals, either directly or via an exception. 174 They will not be saved to their canonical locations before calling 175 the helper. This implies ``TCG_CALL_NO_WRITE_GLOBALS``. 176 177* ``TCG_CALL_NO_SIDE_EFFECTS`` 178 179 The call to the helper function may be removed if the return value is 180 not used. This means that it may not modify any CPU state nor may it 181 raise an exception. 182 183Code Optimizations 184================== 185 186When generating instructions, you can count on at least the following 187optimizations: 188 189- Single instructions are simplified, e.g. 190 191 .. code-block:: none 192 193 and_i32 t0, t0, $0xffffffff 194 195 is suppressed. 196 197- A liveness analysis is done at the basic block level. The 198 information is used to suppress moves from a dead variable to 199 another one. It is also used to remove instructions which compute 200 dead results. The later is especially useful for condition code 201 optimization in QEMU. 202 203 In the following example: 204 205 .. code-block:: none 206 207 add_i32 t0, t1, t2 208 add_i32 t0, t0, $1 209 mov_i32 t0, $1 210 211 only the last instruction is kept. 212 213 214Instruction Reference 215===================== 216 217Function call 218------------- 219 220.. list-table:: 221 222 * - call *<ret>* *<params>* ptr 223 224 - | call function 'ptr' (pointer type) 225 | 226 | *<ret>* optional 32 bit or 64 bit return value 227 | *<params>* optional 32 bit or 64 bit parameters 228 229Jumps/Labels 230------------ 231 232.. list-table:: 233 234 * - set_label $label 235 236 - | Define label 'label' at the current program point. 237 238 * - br $label 239 240 - | Jump to label. 241 242 * - brcond *t0*, *t1*, *cond*, *label* 243 244 - | Conditional jump if *t0* *cond* *t1* is true. *cond* can be: 245 | 246 | ``TCG_COND_EQ`` 247 | ``TCG_COND_NE`` 248 | ``TCG_COND_LT /* signed */`` 249 | ``TCG_COND_GE /* signed */`` 250 | ``TCG_COND_LE /* signed */`` 251 | ``TCG_COND_GT /* signed */`` 252 | ``TCG_COND_LTU /* unsigned */`` 253 | ``TCG_COND_GEU /* unsigned */`` 254 | ``TCG_COND_LEU /* unsigned */`` 255 | ``TCG_COND_GTU /* unsigned */`` 256 | ``TCG_COND_TSTEQ /* t1 & t2 == 0 */`` 257 | ``TCG_COND_TSTNE /* t1 & t2 != 0 */`` 258 259Arithmetic 260---------- 261 262.. list-table:: 263 264 * - add *t0*, *t1*, *t2* 265 266 - | *t0* = *t1* + *t2* 267 268 * - sub *t0*, *t1*, *t2* 269 270 - | *t0* = *t1* - *t2* 271 272 * - neg *t0*, *t1* 273 274 - | *t0* = -*t1* (two's complement) 275 276 * - mul *t0*, *t1*, *t2* 277 278 - | *t0* = *t1* * *t2* 279 280 * - divs *t0*, *t1*, *t2* 281 282 - | *t0* = *t1* / *t2* (signed) 283 | Undefined behavior if division by zero or overflow. 284 285 * - divu *t0*, *t1*, *t2* 286 287 - | *t0* = *t1* / *t2* (unsigned) 288 | Undefined behavior if division by zero. 289 290 * - rems *t0*, *t1*, *t2* 291 292 - | *t0* = *t1* % *t2* (signed) 293 | Undefined behavior if division by zero or overflow. 294 295 * - remu *t0*, *t1*, *t2* 296 297 - | *t0* = *t1* % *t2* (unsigned) 298 | Undefined behavior if division by zero. 299 300 * - divs2 *q*, *r*, *nl*, *nh*, *d* 301 302 - | *q* = *nh:nl* / *d* (signed) 303 | *r* = *nh:nl* % *d* 304 | Undefined behaviour if division by zero, or the double-word 305 numerator divided by the single-word divisor does not fit 306 within the single-word quotient. The code generator will 307 pass *nh* as a simple sign-extension of *nl*, so the only 308 overflow should be *INT_MIN* / -1. 309 310 * - divu2 *q*, *r*, *nl*, *nh*, *d* 311 312 - | *q* = *nh:nl* / *d* (unsigned) 313 | *r* = *nh:nl* % *d* 314 | Undefined behaviour if division by zero, or the double-word 315 numerator divided by the single-word divisor does not fit 316 within the single-word quotient. The code generator will 317 pass 0 to *nh* to make a simple zero-extension of *nl*, 318 so overflow should never occur. 319 320Logical 321------- 322 323.. list-table:: 324 325 * - and *t0*, *t1*, *t2* 326 327 - | *t0* = *t1* & *t2* 328 329 * - or *t0*, *t1*, *t2* 330 331 - | *t0* = *t1* | *t2* 332 333 * - xor *t0*, *t1*, *t2* 334 335 - | *t0* = *t1* ^ *t2* 336 337 * - not *t0*, *t1* 338 339 - | *t0* = ~\ *t1* 340 341 * - andc *t0*, *t1*, *t2* 342 343 - | *t0* = *t1* & ~\ *t2* 344 345 * - eqv *t0*, *t1*, *t2* 346 347 - | *t0* = ~(*t1* ^ *t2*), or equivalently, *t0* = *t1* ^ ~\ *t2* 348 349 * - nand *t0*, *t1*, *t2* 350 351 - | *t0* = ~(*t1* & *t2*) 352 353 * - nor *t0*, *t1*, *t2* 354 355 - | *t0* = ~(*t1* | *t2*) 356 357 * - orc *t0*, *t1*, *t2* 358 359 - | *t0* = *t1* | ~\ *t2* 360 361 * - clz *t0*, *t1*, *t2* 362 363 - | *t0* = *t1* ? clz(*t1*) : *t2* 364 365 * - ctz *t0*, *t1*, *t2* 366 367 - | *t0* = *t1* ? ctz(*t1*) : *t2* 368 369 * - ctpop *t0*, *t1* 370 371 - | *t0* = number of bits set in *t1* 372 | 373 | The name *ctpop* is short for "count population", and matches 374 the function name used in ``include/qemu/host-utils.h``. 375 376 377Shifts/Rotates 378-------------- 379 380.. list-table:: 381 382 * - shl *t0*, *t1*, *t2* 383 384 - | *t0* = *t1* << *t2* 385 | Unspecified behavior for negative or out-of-range shifts. 386 387 * - shr *t0*, *t1*, *t2* 388 389 - | *t0* = *t1* >> *t2* (unsigned) 390 | Unspecified behavior for negative or out-of-range shifts. 391 392 * - sar *t0*, *t1*, *t2* 393 394 - | *t0* = *t1* >> *t2* (signed) 395 | Unspecified behavior for negative or out-of-range shifts. 396 397 * - rotl *t0*, *t1*, *t2* 398 399 - | Rotation of *t2* bits to the left 400 | Unspecified behavior for negative or out-of-range shifts. 401 402 * - rotr *t0*, *t1*, *t2* 403 404 - | Rotation of *t2* bits to the right. 405 | Unspecified behavior for negative or out-of-range shifts. 406 407 408Misc 409---- 410 411.. list-table:: 412 413 * - mov *t0*, *t1* 414 415 - | *t0* = *t1* 416 | Move *t1* to *t0*. 417 418 * - bswap16 *t0*, *t1*, *flags* 419 420 - | 16 bit byte swap on the low bits of a 32/64 bit input. 421 | 422 | If *flags* & ``TCG_BSWAP_IZ``, then *t1* is known to be zero-extended from bit 15. 423 | If *flags* & ``TCG_BSWAP_OZ``, then *t0* will be zero-extended from bit 15. 424 | If *flags* & ``TCG_BSWAP_OS``, then *t0* will be sign-extended from bit 15. 425 | 426 | If neither ``TCG_BSWAP_OZ`` nor ``TCG_BSWAP_OS`` are set, then the bits of *t0* above bit 15 may contain any value. 427 428 * - bswap32 *t0*, *t1*, *flags* 429 430 - | 32 bit byte swap. The flags are the same as for bswap16, except 431 they apply from bit 31 instead of bit 15. On TCG_TYPE_I32, the 432 flags should be zero. 433 434 * - bswap64 *t0*, *t1*, *flags* 435 436 - | 64 bit byte swap. The flags are ignored, but still present 437 for consistency with the other bswap opcodes. For future 438 compatibility, the flags should be zero. 439 440 * - discard_i32/i64 *t0* 441 442 - | Indicate that the value of *t0* won't be used later. It is useful to 443 force dead code elimination. 444 445 * - deposit *dest*, *t1*, *t2*, *pos*, *len* 446 447 - | Deposit *t2* as a bitfield into *t1*, placing the result in *dest*. 448 | 449 | The bitfield is described by *pos*/*len*, which are immediate values: 450 | 451 | *len* - the length of the bitfield 452 | *pos* - the position of the first bit, counting from the LSB 453 | 454 | For example, "deposit dest, t1, t2, 8, 4" indicates a 4-bit field 455 at bit 8. This operation would be equivalent to 456 | 457 | *dest* = (*t1* & ~0x0f00) | ((*t2* << 8) & 0x0f00) 458 | 459 | on TCG_TYPE_I32. 460 461 * - extract *dest*, *t1*, *pos*, *len* 462 463 sextract *dest*, *t1*, *pos*, *len* 464 465 - | Extract a bitfield from *t1*, placing the result in *dest*. 466 | 467 | The bitfield is described by *pos*/*len*, which are immediate values, 468 as above for deposit. For extract_*, the result will be extended 469 to the left with zeros; for sextract_*, the result will be extended 470 to the left with copies of the bitfield sign bit at *pos* + *len* - 1. 471 | 472 | For example, "sextract dest, t1, 8, 4" indicates a 4-bit field 473 at bit 8. This operation would be equivalent to 474 | 475 | *dest* = (*t1* << 20) >> 28 476 | 477 | (using an arithmetic right shift) on TCG_TYPE_I32. 478 479 * - extract2_i32/i64 *dest*, *t1*, *t2*, *pos* 480 481 - | For N = {32,64}, extract an N-bit quantity from the concatenation 482 of *t2*:*t1*, beginning at *pos*. The tcg_gen_extract2_{i32,i64} expander 483 accepts 0 <= *pos* <= N as inputs. The backend code generator will 484 not see either 0 or N as inputs for these opcodes. 485 486 * - extrl_i64_i32 *t0*, *t1* 487 488 - | For 64-bit hosts only, extract the low 32-bits of input *t1* and place it 489 into 32-bit output *t0*. Depending on the host, this may be a simple move, 490 or may require additional canonicalization. 491 492 * - extrh_i64_i32 *t0*, *t1* 493 494 - | For 64-bit hosts only, extract the high 32-bits of input *t1* and place it 495 into 32-bit output *t0*. Depending on the host, this may be a simple shift, 496 or may require additional canonicalization. 497 498 499Conditional moves 500----------------- 501 502.. list-table:: 503 504 * - setcond *dest*, *t1*, *t2*, *cond* 505 506 - | *dest* = (*t1* *cond* *t2*) 507 | 508 | Set *dest* to 1 if (*t1* *cond* *t2*) is true, otherwise set to 0. 509 510 * - negsetcond *dest*, *t1*, *t2*, *cond* 511 512 - | *dest* = -(*t1* *cond* *t2*) 513 | 514 | Set *dest* to -1 if (*t1* *cond* *t2*) is true, otherwise set to 0. 515 516 * - movcond *dest*, *c1*, *c2*, *v1*, *v2*, *cond* 517 518 - | *dest* = (*c1* *cond* *c2* ? *v1* : *v2*) 519 | 520 | Set *dest* to *v1* if (*c1* *cond* *c2*) is true, otherwise set to *v2*. 521 522 523Type conversions 524---------------- 525 526.. list-table:: 527 528 * - ext_i32_i64 *t0*, *t1* 529 530 - | Convert *t1* (32 bit) to *t0* (64 bit) and does sign extension 531 532 * - extu_i32_i64 *t0*, *t1* 533 534 - | Convert *t1* (32 bit) to *t0* (64 bit) and does zero extension 535 536 * - trunc_i64_i32 *t0*, *t1* 537 538 - | Truncate *t1* (64 bit) to *t0* (32 bit) 539 540 * - concat_i32_i64 *t0*, *t1*, *t2* 541 542 - | Construct *t0* (64-bit) taking the low half from *t1* (32 bit) and the high half 543 from *t2* (32 bit). 544 545 * - concat32_i64 *t0*, *t1*, *t2* 546 547 - | Construct *t0* (64-bit) taking the low half from *t1* (64 bit) and the high half 548 from *t2* (64 bit). 549 550 551Load/Store 552---------- 553 554.. list-table:: 555 556 * - ld_i32/i64 *t0*, *t1*, *offset* 557 558 ld8s_i32/i64 *t0*, *t1*, *offset* 559 560 ld8u_i32/i64 *t0*, *t1*, *offset* 561 562 ld16s_i32/i64 *t0*, *t1*, *offset* 563 564 ld16u_i32/i64 *t0*, *t1*, *offset* 565 566 ld32s_i64 t0, *t1*, *offset* 567 568 ld32u_i64 t0, *t1*, *offset* 569 570 - | *t0* = read(*t1* + *offset*) 571 | 572 | Load 8, 16, 32 or 64 bits with or without sign extension from host memory. 573 *offset* must be a constant. 574 575 * - st_i32/i64 *t0*, *t1*, *offset* 576 577 st8_i32/i64 *t0*, *t1*, *offset* 578 579 st16_i32/i64 *t0*, *t1*, *offset* 580 581 st32_i64 *t0*, *t1*, *offset* 582 583 - | write(*t0*, *t1* + *offset*) 584 | 585 | Write 8, 16, 32 or 64 bits to host memory. 586 587All this opcodes assume that the pointed host memory doesn't correspond 588to a global. In the latter case the behaviour is unpredictable. 589 590 591Multiword arithmetic support 592---------------------------- 593 594.. list-table:: 595 596 * - add2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high* 597 598 sub2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high* 599 600 - | Similar to add/sub, except that the double-word inputs *t1* and *t2* are 601 formed from two single-word arguments, and the double-word output *t0* 602 is returned in two single-word outputs. 603 604 * - mulu2 *t0_low*, *t0_high*, *t1*, *t2* 605 606 - | Similar to mul, except two unsigned inputs *t1* and *t2* yielding the full 607 double-word product *t0*. The latter is returned in two single-word outputs. 608 609 * - muls2 *t0_low*, *t0_high*, *t1*, *t2* 610 611 - | Similar to mulu2, except the two inputs *t1* and *t2* are signed. 612 613 * - mulsh *t0*, *t1*, *t2* 614 615 muluh *t0*, *t1*, *t2* 616 617 - | Provide the high part of a signed or unsigned multiply, respectively. 618 | 619 | If mulu2/muls2 are not provided by the backend, the tcg-op generator 620 can obtain the same results by emitting a pair of opcodes, mul + muluh/mulsh. 621 622 623Memory Barrier support 624---------------------- 625 626.. list-table:: 627 628 * - mb *<$arg>* 629 630 - | Generate a target memory barrier instruction to ensure memory ordering 631 as being enforced by a corresponding guest memory barrier instruction. 632 | 633 | The ordering enforced by the backend may be stricter than the ordering 634 required by the guest. It cannot be weaker. This opcode takes a constant 635 argument which is required to generate the appropriate barrier 636 instruction. The backend should take care to emit the target barrier 637 instruction only when necessary i.e., for SMP guests and when MTTCG is 638 enabled. 639 | 640 | The guest translators should generate this opcode for all guest instructions 641 which have ordering side effects. 642 | 643 | Please see :ref:`atomics-ref` for more information on memory barriers. 644 645 64664-bit guest on 32-bit host support 647----------------------------------- 648 649The following opcodes are internal to TCG. Thus they are to be implemented by 65032-bit host code generators, but are not to be emitted by guest translators. 651They are emitted as needed by inline functions within ``tcg-op.h``. 652 653.. list-table:: 654 655 * - brcond2_i32 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *cond*, *label* 656 657 - | Similar to brcond, except that the 64-bit values *t0* and *t1* 658 are formed from two 32-bit arguments. 659 660 * - setcond2_i32 *dest*, *t1_low*, *t1_high*, *t2_low*, *t2_high*, *cond* 661 662 - | Similar to setcond, except that the 64-bit values *t1* and *t2* are 663 formed from two 32-bit arguments. The result is a 32-bit value. 664 665 666QEMU specific operations 667------------------------ 668 669.. list-table:: 670 671 * - exit_tb *t0* 672 673 - | Exit the current TB and return the value *t0* (word type). 674 675 * - goto_tb *index* 676 677 - | Exit the current TB and jump to the TB index *index* (constant) if the 678 current TB was linked to this TB. Otherwise execute the next 679 instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued 680 at most once with each slot index per TB. 681 682 * - lookup_and_goto_ptr *tb_addr* 683 684 - | Look up a TB address *tb_addr* and jump to it if valid. If not valid, 685 jump to the TCG epilogue to go back to the exec loop. 686 | 687 | This operation is optional. If the TCG backend does not implement the 688 goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0). 689 690 * - qemu_ld_i32/i64/i128 *t0*, *t1*, *flags*, *memidx* 691 692 qemu_st_i32/i64/i128 *t0*, *t1*, *flags*, *memidx* 693 694 qemu_st8_i32 *t0*, *t1*, *flags*, *memidx* 695 696 - | Load data at the guest address *t1* into *t0*, or store data in *t0* at guest 697 address *t1*. The _i32/_i64/_i128 size applies to the size of the input/output 698 register *t0* only. The address *t1* is always sized according to the guest, 699 and the width of the memory operation is controlled by *flags*. 700 | 701 | Both *t0* and *t1* may be split into little-endian ordered pairs of registers 702 if dealing with 64-bit quantities on a 32-bit host, or 128-bit quantities on 703 a 64-bit host. 704 | 705 | The *memidx* selects the qemu tlb index to use (e.g. user or kernel access). 706 The flags are the MemOp bits, selecting the sign, width, and endianness 707 of the memory access. 708 | 709 | For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a 710 64-bit memory access specified in *flags*. 711 | 712 | For qemu_ld/st_i128, these are only supported for a 64-bit host. 713 | 714 | For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of 715 the memory operation is known to be 8-bit. This allows the backend to 716 provide a different set of register constraints. 717 718 719Host vector operations 720---------------------- 721 722All of the vector ops have two parameters, ``TCGOP_TYPE`` & ``TCGOP_VECE``. 723The former specifies the length of the vector as a TCGType; the latter 724specifies the length of the element (if applicable) in log2 8-bit units. 725 726.. list-table:: 727 728 * - mov_vec *v0*, *v1* 729 730 ld_vec *v0*, *t1* 731 732 st_vec *v0*, *t1* 733 734 - | Move, load and store. 735 736 * - dup_vec *v0*, *r1* 737 738 - | Duplicate the low N bits of *r1* into TYPE/VECE copies across *v0*. 739 740 * - dupi_vec *v0*, *c* 741 742 - | Similarly, for a constant. 743 | Smaller values will be replicated to host register size by the expanders. 744 745 * - dup2_vec *v0*, *r1*, *r2* 746 747 - | Duplicate *r2*:*r1* into TYPE/64 copies across *v0*. This opcode is 748 only present for 32-bit hosts. 749 750 * - add_vec *v0*, *v1*, *v2* 751 752 - | *v0* = *v1* + *v2*, in elements across the vector. 753 754 * - sub_vec *v0*, *v1*, *v2* 755 756 - | Similarly, *v0* = *v1* - *v2*. 757 758 * - mul_vec *v0*, *v1*, *v2* 759 760 - | Similarly, *v0* = *v1* * *v2*. 761 762 * - neg_vec *v0*, *v1* 763 764 - | Similarly, *v0* = -*v1*. 765 766 * - abs_vec *v0*, *v1* 767 768 - | Similarly, *v0* = *v1* < 0 ? -*v1* : *v1*, in elements across the vector. 769 770 * - smin_vec *v0*, *v1*, *v2* 771 772 umin_vec *v0*, *v1*, *v2* 773 774 - | Similarly, *v0* = MIN(*v1*, *v2*), for signed and unsigned element types. 775 776 * - smax_vec *v0*, *v1*, *v2* 777 778 umax_vec *v0*, *v1*, *v2* 779 780 - | Similarly, *v0* = MAX(*v1*, *v2*), for signed and unsigned element types. 781 782 * - ssadd_vec *v0*, *v1*, *v2* 783 784 sssub_vec *v0*, *v1*, *v2* 785 786 usadd_vec *v0*, *v1*, *v2* 787 788 ussub_vec *v0*, *v1*, *v2* 789 790 - | Signed and unsigned saturating addition and subtraction. 791 | 792 | If the true result is not representable within the element type, the 793 element is set to the minimum or maximum value for the type. 794 795 * - and_vec *v0*, *v1*, *v2* 796 797 or_vec *v0*, *v1*, *v2* 798 799 xor_vec *v0*, *v1*, *v2* 800 801 andc_vec *v0*, *v1*, *v2* 802 803 orc_vec *v0*, *v1*, *v2* 804 805 not_vec *v0*, *v1* 806 807 - | Similarly, logical operations with and without complement. 808 | 809 | Note that VECE is unused. 810 811 * - shli_vec *v0*, *v1*, *i2* 812 813 shls_vec *v0*, *v1*, *s2* 814 815 - | Shift all elements from v1 by a scalar *i2*/*s2*. I.e. 816 817 .. code-block:: c 818 819 for (i = 0; i < TYPE/VECE; ++i) { 820 v0[i] = v1[i] << s2; 821 } 822 823 * - shri_vec *v0*, *v1*, *i2* 824 825 sari_vec *v0*, *v1*, *i2* 826 827 rotli_vec *v0*, *v1*, *i2* 828 829 shrs_vec *v0*, *v1*, *s2* 830 831 sars_vec *v0*, *v1*, *s2* 832 833 - | Similarly for logical and arithmetic right shift, and left rotate. 834 835 * - shlv_vec *v0*, *v1*, *v2* 836 837 - | Shift elements from *v1* by elements from *v2*. I.e. 838 839 .. code-block:: c 840 841 for (i = 0; i < TYPE/VECE; ++i) { 842 v0[i] = v1[i] << v2[i]; 843 } 844 845 * - shrv_vec *v0*, *v1*, *v2* 846 847 sarv_vec *v0*, *v1*, *v2* 848 849 rotlv_vec *v0*, *v1*, *v2* 850 851 rotrv_vec *v0*, *v1*, *v2* 852 853 - | Similarly for logical and arithmetic right shift, and rotates. 854 855 * - cmp_vec *v0*, *v1*, *v2*, *cond* 856 857 - | Compare vectors by element, storing -1 for true and 0 for false. 858 859 * - bitsel_vec *v0*, *v1*, *v2*, *v3* 860 861 - | Bitwise select, *v0* = (*v2* & *v1*) | (*v3* & ~\ *v1*), across the entire vector. 862 863 * - cmpsel_vec *v0*, *c1*, *c2*, *v3*, *v4*, *cond* 864 865 - | Select elements based on comparison results: 866 867 .. code-block:: c 868 869 for (i = 0; i < n; ++i) { 870 v0[i] = (c1[i] cond c2[i]) ? v3[i] : v4[i]. 871 } 872 873**Note 1**: Some shortcuts are defined when the last operand is known to be 874a constant (e.g. addi for add, movi for mov). 875 876**Note 2**: When using TCG, the opcodes must never be generated directly 877as some of them may not be available as "real" opcodes. Always use the 878function tcg_gen_xxx(args). 879 880 881Backend 882======= 883 884``tcg-target.h`` contains the target specific definitions. ``tcg-target.c.inc`` 885contains the target specific code; it is #included by ``tcg/tcg.c``, rather 886than being a standalone C file. 887 888Assumptions 889----------- 890 891The target word size (``TCG_TARGET_REG_BITS``) is expected to be 32 bit or 89264 bit. It is expected that the pointer has the same size as the word. 893 894On a 32 bit target, all 64 bit operations are converted to 32 bits. A 895few specific operations must be implemented to allow it (see add2_i32, 896sub2_i32, brcond2_i32). 897 898On a 64 bit target, the values are transferred between 32 and 64-bit 899registers using the following ops: 900 901- extrl_i64_i32 902- extrh_i64_i32 903- ext_i32_i64 904- extu_i32_i64 905 906They ensure that the values are correctly truncated or extended when 907moved from a 32-bit to a 64-bit register or vice-versa. Note that the 908extrl_i64_i32 and extrh_i64_i32 are optional ops. It is not necessary 909to implement them if all the following conditions are met: 910 911- 64-bit registers can hold 32-bit values 912- 32-bit values in a 64-bit register do not need to stay zero or 913 sign extended 914- all 32-bit TCG ops ignore the high part of 64-bit registers 915 916Floating point operations are not supported in this version. A 917previous incarnation of the code generator had full support of them, 918but it is better to concentrate on integer operations first. 919 920Constraints 921---------------- 922 923GCC like constraints are used to define the constraints of every 924instruction. Memory constraints are not supported in this 925version. Aliases are specified in the input operands as for GCC. 926 927The same register may be used for both an input and an output, even when 928they are not explicitly aliased. If an op expands to multiple target 929instructions then care must be taken to avoid clobbering input values. 930GCC style "early clobber" outputs are supported, with '``&``'. 931 932A target can define specific register or constant constraints. If an 933operation uses a constant input constraint which does not allow all 934constants, it must also accept registers in order to have a fallback. 935The constraint '``i``' is defined generically to accept any constant. 936The constraint '``r``' is not defined generically, but is consistently 937used by each backend to indicate all registers. If ``TCG_REG_ZERO`` 938is defined by the backend, the constraint '``z``' is defined generically 939to map constant 0 to the hardware zero register. 940 941The movi_i32 and movi_i64 operations must accept any constants. 942 943The mov_i32 and mov_i64 operations must accept any registers of the 944same type. 945 946The ld/st/sti instructions must accept signed 32 bit constant offsets. 947This can be implemented by reserving a specific register in which to 948compute the address if the offset is too big. 949 950The ld/st instructions must accept any destination (ld) or source (st) 951register. 952 953The sti instruction may fail if it cannot store the given constant. 954 955Function call assumptions 956------------------------- 957 958- The only supported types for parameters and return value are: 32 and 959 64 bit integers and pointer. 960- The stack grows downwards. 961- The first N parameters are passed in registers. 962- The next parameters are passed on the stack by storing them as words. 963- Some registers are clobbered during the call. 964- The function can return 0 or 1 value in registers. On a 32 bit 965 target, functions must be able to return 2 values in registers for 966 64 bit return type. 967 968 969Recommended coding rules for best performance 970============================================= 971 972- Use globals to represent the parts of the QEMU CPU state which are 973 often modified, e.g. the integer registers and the condition 974 codes. TCG will be able to use host registers to store them. 975 976- Don't hesitate to use helpers for complicated or seldom used guest 977 instructions. There is little performance advantage in using TCG to 978 implement guest instructions taking more than about twenty TCG 979 instructions. Note that this rule of thumb is more applicable to 980 helpers doing complex logic or arithmetic, where the C compiler has 981 scope to do a good job of optimisation; it is less relevant where 982 the instruction is mostly doing loads and stores, and in those cases 983 inline TCG may still be faster for longer sequences. 984 985- Use the 'discard' instruction if you know that TCG won't be able to 986 prove that a given global is "dead" at a given program point. The 987 x86 guest uses it to improve the condition codes optimisation. 988