xref: /openbmc/qemu/docs/about/emulation.rst (revision a0a6754bb549b255a269b9ab63674e06a1d14ddb) 
1Emulation
2=========
3
4QEMU's Tiny Code Generator (TCG) provides the ability to emulate a
5number of CPU architectures on any supported host platform. Both
6:ref:`System Emulation` and :ref:`User Mode Emulation` are supported
7depending on the guest architecture.
8
9.. list-table:: Supported Guest Architectures for Emulation
10  :widths: 30 10 10 50
11  :header-rows: 1
12
13  * - Architecture (qemu name)
14    - System
15    - User
16    - Notes
17  * - Alpha
18    - Yes
19    - Yes
20    - Legacy 64 bit RISC ISA developed by DEC
21  * - Arm (arm, aarch64)
22    - :ref:`Yes<ARM-System-emulator>`
23    - Yes
24    - Wide range of features, see :ref:`Arm Emulation` for details
25  * - AVR
26    - :ref:`Yes<AVR-System-emulator>`
27    - No
28    - 8 bit micro controller, often used in maker projects
29  * - Cris
30    - Yes
31    - Yes
32    - Embedded RISC chip developed by AXIS
33  * - Hexagon
34    - No
35    - Yes
36    - Family of DSPs by Qualcomm
37  * - PA-RISC (hppa)
38    - Yes
39    - Yes
40    - A legacy RISC system used in HP's old minicomputers
41  * - x86 (i386, x86_64)
42    - :ref:`Yes<QEMU-PC-System-emulator>`
43    - Yes
44    - The ubiquitous desktop PC CPU architecture, 32 and 64 bit.
45  * - Loongarch
46    - Yes
47    - Yes
48    - A MIPS-like 64bit RISC architecture developed in China
49  * - m68k
50    - :ref:`Yes<ColdFire-System-emulator>`
51    - Yes
52    - Motorola 68000 variants and ColdFire
53  * - Microblaze
54    - Yes
55    - Yes
56    - RISC based soft-core by Xilinx
57  * - MIPS (mips*)
58    - :ref:`Yes<MIPS-System-emulator>`
59    - Yes
60    - Venerable RISC architecture originally out of Stanford University
61  * - Nios2
62    - Yes
63    - Yes
64    - 32 bit embedded soft-core by Altera
65  * - OpenRISC
66    - :ref:`Yes<OpenRISC-System-emulator>`
67    - Yes
68    - Open source RISC architecture developed by the OpenRISC community
69  * - Power (ppc, ppc64)
70    - :ref:`Yes<PowerPC-System-emulator>`
71    - Yes
72    - A general purpose RISC architecture now managed by IBM
73  * - RISC-V
74    - :ref:`Yes<RISC-V-System-emulator>`
75    - Yes
76    - An open standard RISC ISA maintained by RISC-V International
77  * - RX
78    - :ref:`Yes<RX-System-emulator>`
79    - No
80    - A 32 bit micro controller developed by Renesas
81  * - s390x
82    - :ref:`Yes<s390x-System-emulator>`
83    - Yes
84    - A 64 bit CPU found in IBM's System Z mainframes
85  * - sh4
86    - Yes
87    - Yes
88    - A 32 bit RISC embedded CPU developed by Hitachi
89  * - SPARC (sparc, sparc64)
90    - :ref:`Yes<Sparc32-System-emulator>`
91    - Yes
92    - A RISC ISA originally developed by Sun Microsystems
93  * - Tricore
94    - Yes
95    - No
96    - A 32 bit RISC/uController/DSP developed by Infineon
97  * - Xtensa
98    - :ref:`Yes<Xtensa-System-emulator>`
99    - Yes
100    - A configurable 32 bit soft core now owned by Cadence
101
102A number of features are are only available when running under
103emulation including :ref:`Record/Replay<replay>` and :ref:`TCG Plugins`.
104