1 /* 2 * QEMU RISC-V Disassembler 3 * 4 * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com> 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/bitops.h" 22 #include "disas/dis-asm.h" 23 #include "target/riscv/cpu_cfg.h" 24 #include "disas/riscv.h" 25 26 /* Vendor extensions */ 27 #include "disas/riscv-xthead.h" 28 #include "disas/riscv-xventana.h" 29 30 typedef enum { 31 /* 0 is reserved for rv_op_illegal. */ 32 rv_op_lui = 1, 33 rv_op_auipc = 2, 34 rv_op_jal = 3, 35 rv_op_jalr = 4, 36 rv_op_beq = 5, 37 rv_op_bne = 6, 38 rv_op_blt = 7, 39 rv_op_bge = 8, 40 rv_op_bltu = 9, 41 rv_op_bgeu = 10, 42 rv_op_lb = 11, 43 rv_op_lh = 12, 44 rv_op_lw = 13, 45 rv_op_lbu = 14, 46 rv_op_lhu = 15, 47 rv_op_sb = 16, 48 rv_op_sh = 17, 49 rv_op_sw = 18, 50 rv_op_addi = 19, 51 rv_op_slti = 20, 52 rv_op_sltiu = 21, 53 rv_op_xori = 22, 54 rv_op_ori = 23, 55 rv_op_andi = 24, 56 rv_op_slli = 25, 57 rv_op_srli = 26, 58 rv_op_srai = 27, 59 rv_op_add = 28, 60 rv_op_sub = 29, 61 rv_op_sll = 30, 62 rv_op_slt = 31, 63 rv_op_sltu = 32, 64 rv_op_xor = 33, 65 rv_op_srl = 34, 66 rv_op_sra = 35, 67 rv_op_or = 36, 68 rv_op_and = 37, 69 rv_op_fence = 38, 70 rv_op_fence_i = 39, 71 rv_op_lwu = 40, 72 rv_op_ld = 41, 73 rv_op_sd = 42, 74 rv_op_addiw = 43, 75 rv_op_slliw = 44, 76 rv_op_srliw = 45, 77 rv_op_sraiw = 46, 78 rv_op_addw = 47, 79 rv_op_subw = 48, 80 rv_op_sllw = 49, 81 rv_op_srlw = 50, 82 rv_op_sraw = 51, 83 rv_op_ldu = 52, 84 rv_op_lq = 53, 85 rv_op_sq = 54, 86 rv_op_addid = 55, 87 rv_op_sllid = 56, 88 rv_op_srlid = 57, 89 rv_op_sraid = 58, 90 rv_op_addd = 59, 91 rv_op_subd = 60, 92 rv_op_slld = 61, 93 rv_op_srld = 62, 94 rv_op_srad = 63, 95 rv_op_mul = 64, 96 rv_op_mulh = 65, 97 rv_op_mulhsu = 66, 98 rv_op_mulhu = 67, 99 rv_op_div = 68, 100 rv_op_divu = 69, 101 rv_op_rem = 70, 102 rv_op_remu = 71, 103 rv_op_mulw = 72, 104 rv_op_divw = 73, 105 rv_op_divuw = 74, 106 rv_op_remw = 75, 107 rv_op_remuw = 76, 108 rv_op_muld = 77, 109 rv_op_divd = 78, 110 rv_op_divud = 79, 111 rv_op_remd = 80, 112 rv_op_remud = 81, 113 rv_op_lr_w = 82, 114 rv_op_sc_w = 83, 115 rv_op_amoswap_w = 84, 116 rv_op_amoadd_w = 85, 117 rv_op_amoxor_w = 86, 118 rv_op_amoor_w = 87, 119 rv_op_amoand_w = 88, 120 rv_op_amomin_w = 89, 121 rv_op_amomax_w = 90, 122 rv_op_amominu_w = 91, 123 rv_op_amomaxu_w = 92, 124 rv_op_lr_d = 93, 125 rv_op_sc_d = 94, 126 rv_op_amoswap_d = 95, 127 rv_op_amoadd_d = 96, 128 rv_op_amoxor_d = 97, 129 rv_op_amoor_d = 98, 130 rv_op_amoand_d = 99, 131 rv_op_amomin_d = 100, 132 rv_op_amomax_d = 101, 133 rv_op_amominu_d = 102, 134 rv_op_amomaxu_d = 103, 135 rv_op_lr_q = 104, 136 rv_op_sc_q = 105, 137 rv_op_amoswap_q = 106, 138 rv_op_amoadd_q = 107, 139 rv_op_amoxor_q = 108, 140 rv_op_amoor_q = 109, 141 rv_op_amoand_q = 110, 142 rv_op_amomin_q = 111, 143 rv_op_amomax_q = 112, 144 rv_op_amominu_q = 113, 145 rv_op_amomaxu_q = 114, 146 rv_op_ecall = 115, 147 rv_op_ebreak = 116, 148 rv_op_uret = 117, 149 rv_op_sret = 118, 150 rv_op_hret = 119, 151 rv_op_mret = 120, 152 rv_op_dret = 121, 153 rv_op_sfence_vm = 122, 154 rv_op_sfence_vma = 123, 155 rv_op_wfi = 124, 156 rv_op_csrrw = 125, 157 rv_op_csrrs = 126, 158 rv_op_csrrc = 127, 159 rv_op_csrrwi = 128, 160 rv_op_csrrsi = 129, 161 rv_op_csrrci = 130, 162 rv_op_flw = 131, 163 rv_op_fsw = 132, 164 rv_op_fmadd_s = 133, 165 rv_op_fmsub_s = 134, 166 rv_op_fnmsub_s = 135, 167 rv_op_fnmadd_s = 136, 168 rv_op_fadd_s = 137, 169 rv_op_fsub_s = 138, 170 rv_op_fmul_s = 139, 171 rv_op_fdiv_s = 140, 172 rv_op_fsgnj_s = 141, 173 rv_op_fsgnjn_s = 142, 174 rv_op_fsgnjx_s = 143, 175 rv_op_fmin_s = 144, 176 rv_op_fmax_s = 145, 177 rv_op_fsqrt_s = 146, 178 rv_op_fle_s = 147, 179 rv_op_flt_s = 148, 180 rv_op_feq_s = 149, 181 rv_op_fcvt_w_s = 150, 182 rv_op_fcvt_wu_s = 151, 183 rv_op_fcvt_s_w = 152, 184 rv_op_fcvt_s_wu = 153, 185 rv_op_fmv_x_s = 154, 186 rv_op_fclass_s = 155, 187 rv_op_fmv_s_x = 156, 188 rv_op_fcvt_l_s = 157, 189 rv_op_fcvt_lu_s = 158, 190 rv_op_fcvt_s_l = 159, 191 rv_op_fcvt_s_lu = 160, 192 rv_op_fld = 161, 193 rv_op_fsd = 162, 194 rv_op_fmadd_d = 163, 195 rv_op_fmsub_d = 164, 196 rv_op_fnmsub_d = 165, 197 rv_op_fnmadd_d = 166, 198 rv_op_fadd_d = 167, 199 rv_op_fsub_d = 168, 200 rv_op_fmul_d = 169, 201 rv_op_fdiv_d = 170, 202 rv_op_fsgnj_d = 171, 203 rv_op_fsgnjn_d = 172, 204 rv_op_fsgnjx_d = 173, 205 rv_op_fmin_d = 174, 206 rv_op_fmax_d = 175, 207 rv_op_fcvt_s_d = 176, 208 rv_op_fcvt_d_s = 177, 209 rv_op_fsqrt_d = 178, 210 rv_op_fle_d = 179, 211 rv_op_flt_d = 180, 212 rv_op_feq_d = 181, 213 rv_op_fcvt_w_d = 182, 214 rv_op_fcvt_wu_d = 183, 215 rv_op_fcvt_d_w = 184, 216 rv_op_fcvt_d_wu = 185, 217 rv_op_fclass_d = 186, 218 rv_op_fcvt_l_d = 187, 219 rv_op_fcvt_lu_d = 188, 220 rv_op_fmv_x_d = 189, 221 rv_op_fcvt_d_l = 190, 222 rv_op_fcvt_d_lu = 191, 223 rv_op_fmv_d_x = 192, 224 rv_op_flq = 193, 225 rv_op_fsq = 194, 226 rv_op_fmadd_q = 195, 227 rv_op_fmsub_q = 196, 228 rv_op_fnmsub_q = 197, 229 rv_op_fnmadd_q = 198, 230 rv_op_fadd_q = 199, 231 rv_op_fsub_q = 200, 232 rv_op_fmul_q = 201, 233 rv_op_fdiv_q = 202, 234 rv_op_fsgnj_q = 203, 235 rv_op_fsgnjn_q = 204, 236 rv_op_fsgnjx_q = 205, 237 rv_op_fmin_q = 206, 238 rv_op_fmax_q = 207, 239 rv_op_fcvt_s_q = 208, 240 rv_op_fcvt_q_s = 209, 241 rv_op_fcvt_d_q = 210, 242 rv_op_fcvt_q_d = 211, 243 rv_op_fsqrt_q = 212, 244 rv_op_fle_q = 213, 245 rv_op_flt_q = 214, 246 rv_op_feq_q = 215, 247 rv_op_fcvt_w_q = 216, 248 rv_op_fcvt_wu_q = 217, 249 rv_op_fcvt_q_w = 218, 250 rv_op_fcvt_q_wu = 219, 251 rv_op_fclass_q = 220, 252 rv_op_fcvt_l_q = 221, 253 rv_op_fcvt_lu_q = 222, 254 rv_op_fcvt_q_l = 223, 255 rv_op_fcvt_q_lu = 224, 256 rv_op_fmv_x_q = 225, 257 rv_op_fmv_q_x = 226, 258 rv_op_c_addi4spn = 227, 259 rv_op_c_fld = 228, 260 rv_op_c_lw = 229, 261 rv_op_c_flw = 230, 262 rv_op_c_fsd = 231, 263 rv_op_c_sw = 232, 264 rv_op_c_fsw = 233, 265 rv_op_c_nop = 234, 266 rv_op_c_addi = 235, 267 rv_op_c_jal = 236, 268 rv_op_c_li = 237, 269 rv_op_c_addi16sp = 238, 270 rv_op_c_lui = 239, 271 rv_op_c_srli = 240, 272 rv_op_c_srai = 241, 273 rv_op_c_andi = 242, 274 rv_op_c_sub = 243, 275 rv_op_c_xor = 244, 276 rv_op_c_or = 245, 277 rv_op_c_and = 246, 278 rv_op_c_subw = 247, 279 rv_op_c_addw = 248, 280 rv_op_c_j = 249, 281 rv_op_c_beqz = 250, 282 rv_op_c_bnez = 251, 283 rv_op_c_slli = 252, 284 rv_op_c_fldsp = 253, 285 rv_op_c_lwsp = 254, 286 rv_op_c_flwsp = 255, 287 rv_op_c_jr = 256, 288 rv_op_c_mv = 257, 289 rv_op_c_ebreak = 258, 290 rv_op_c_jalr = 259, 291 rv_op_c_add = 260, 292 rv_op_c_fsdsp = 261, 293 rv_op_c_swsp = 262, 294 rv_op_c_fswsp = 263, 295 rv_op_c_ld = 264, 296 rv_op_c_sd = 265, 297 rv_op_c_addiw = 266, 298 rv_op_c_ldsp = 267, 299 rv_op_c_sdsp = 268, 300 rv_op_c_lq = 269, 301 rv_op_c_sq = 270, 302 rv_op_c_lqsp = 271, 303 rv_op_c_sqsp = 272, 304 rv_op_nop = 273, 305 rv_op_mv = 274, 306 rv_op_not = 275, 307 rv_op_neg = 276, 308 rv_op_negw = 277, 309 rv_op_sext_w = 278, 310 rv_op_seqz = 279, 311 rv_op_snez = 280, 312 rv_op_sltz = 281, 313 rv_op_sgtz = 282, 314 rv_op_fmv_s = 283, 315 rv_op_fabs_s = 284, 316 rv_op_fneg_s = 285, 317 rv_op_fmv_d = 286, 318 rv_op_fabs_d = 287, 319 rv_op_fneg_d = 288, 320 rv_op_fmv_q = 289, 321 rv_op_fabs_q = 290, 322 rv_op_fneg_q = 291, 323 rv_op_beqz = 292, 324 rv_op_bnez = 293, 325 rv_op_blez = 294, 326 rv_op_bgez = 295, 327 rv_op_bltz = 296, 328 rv_op_bgtz = 297, 329 rv_op_ble = 298, 330 rv_op_bleu = 299, 331 rv_op_bgt = 300, 332 rv_op_bgtu = 301, 333 rv_op_j = 302, 334 rv_op_ret = 303, 335 rv_op_jr = 304, 336 rv_op_rdcycle = 305, 337 rv_op_rdtime = 306, 338 rv_op_rdinstret = 307, 339 rv_op_rdcycleh = 308, 340 rv_op_rdtimeh = 309, 341 rv_op_rdinstreth = 310, 342 rv_op_frcsr = 311, 343 rv_op_frrm = 312, 344 rv_op_frflags = 313, 345 rv_op_fscsr = 314, 346 rv_op_fsrm = 315, 347 rv_op_fsflags = 316, 348 rv_op_fsrmi = 317, 349 rv_op_fsflagsi = 318, 350 rv_op_bseti = 319, 351 rv_op_bclri = 320, 352 rv_op_binvi = 321, 353 rv_op_bexti = 322, 354 rv_op_rori = 323, 355 rv_op_clz = 324, 356 rv_op_ctz = 325, 357 rv_op_cpop = 326, 358 rv_op_sext_h = 327, 359 rv_op_sext_b = 328, 360 rv_op_xnor = 329, 361 rv_op_orn = 330, 362 rv_op_andn = 331, 363 rv_op_rol = 332, 364 rv_op_ror = 333, 365 rv_op_sh1add = 334, 366 rv_op_sh2add = 335, 367 rv_op_sh3add = 336, 368 rv_op_sh1add_uw = 337, 369 rv_op_sh2add_uw = 338, 370 rv_op_sh3add_uw = 339, 371 rv_op_clmul = 340, 372 rv_op_clmulr = 341, 373 rv_op_clmulh = 342, 374 rv_op_min = 343, 375 rv_op_minu = 344, 376 rv_op_max = 345, 377 rv_op_maxu = 346, 378 rv_op_clzw = 347, 379 rv_op_ctzw = 348, 380 rv_op_cpopw = 349, 381 rv_op_slli_uw = 350, 382 rv_op_add_uw = 351, 383 rv_op_rolw = 352, 384 rv_op_rorw = 353, 385 rv_op_rev8 = 354, 386 rv_op_zext_h = 355, 387 rv_op_roriw = 356, 388 rv_op_orc_b = 357, 389 rv_op_bset = 358, 390 rv_op_bclr = 359, 391 rv_op_binv = 360, 392 rv_op_bext = 361, 393 rv_op_aes32esmi = 362, 394 rv_op_aes32esi = 363, 395 rv_op_aes32dsmi = 364, 396 rv_op_aes32dsi = 365, 397 rv_op_aes64ks1i = 366, 398 rv_op_aes64ks2 = 367, 399 rv_op_aes64im = 368, 400 rv_op_aes64esm = 369, 401 rv_op_aes64es = 370, 402 rv_op_aes64dsm = 371, 403 rv_op_aes64ds = 372, 404 rv_op_sha256sig0 = 373, 405 rv_op_sha256sig1 = 374, 406 rv_op_sha256sum0 = 375, 407 rv_op_sha256sum1 = 376, 408 rv_op_sha512sig0 = 377, 409 rv_op_sha512sig1 = 378, 410 rv_op_sha512sum0 = 379, 411 rv_op_sha512sum1 = 380, 412 rv_op_sha512sum0r = 381, 413 rv_op_sha512sum1r = 382, 414 rv_op_sha512sig0l = 383, 415 rv_op_sha512sig0h = 384, 416 rv_op_sha512sig1l = 385, 417 rv_op_sha512sig1h = 386, 418 rv_op_sm3p0 = 387, 419 rv_op_sm3p1 = 388, 420 rv_op_sm4ed = 389, 421 rv_op_sm4ks = 390, 422 rv_op_brev8 = 391, 423 rv_op_pack = 392, 424 rv_op_packh = 393, 425 rv_op_packw = 394, 426 rv_op_unzip = 395, 427 rv_op_zip = 396, 428 rv_op_xperm4 = 397, 429 rv_op_xperm8 = 398, 430 rv_op_vle8_v = 399, 431 rv_op_vle16_v = 400, 432 rv_op_vle32_v = 401, 433 rv_op_vle64_v = 402, 434 rv_op_vse8_v = 403, 435 rv_op_vse16_v = 404, 436 rv_op_vse32_v = 405, 437 rv_op_vse64_v = 406, 438 rv_op_vlm_v = 407, 439 rv_op_vsm_v = 408, 440 rv_op_vlse8_v = 409, 441 rv_op_vlse16_v = 410, 442 rv_op_vlse32_v = 411, 443 rv_op_vlse64_v = 412, 444 rv_op_vsse8_v = 413, 445 rv_op_vsse16_v = 414, 446 rv_op_vsse32_v = 415, 447 rv_op_vsse64_v = 416, 448 rv_op_vluxei8_v = 417, 449 rv_op_vluxei16_v = 418, 450 rv_op_vluxei32_v = 419, 451 rv_op_vluxei64_v = 420, 452 rv_op_vloxei8_v = 421, 453 rv_op_vloxei16_v = 422, 454 rv_op_vloxei32_v = 423, 455 rv_op_vloxei64_v = 424, 456 rv_op_vsuxei8_v = 425, 457 rv_op_vsuxei16_v = 426, 458 rv_op_vsuxei32_v = 427, 459 rv_op_vsuxei64_v = 428, 460 rv_op_vsoxei8_v = 429, 461 rv_op_vsoxei16_v = 430, 462 rv_op_vsoxei32_v = 431, 463 rv_op_vsoxei64_v = 432, 464 rv_op_vle8ff_v = 433, 465 rv_op_vle16ff_v = 434, 466 rv_op_vle32ff_v = 435, 467 rv_op_vle64ff_v = 436, 468 rv_op_vl1re8_v = 437, 469 rv_op_vl1re16_v = 438, 470 rv_op_vl1re32_v = 439, 471 rv_op_vl1re64_v = 440, 472 rv_op_vl2re8_v = 441, 473 rv_op_vl2re16_v = 442, 474 rv_op_vl2re32_v = 443, 475 rv_op_vl2re64_v = 444, 476 rv_op_vl4re8_v = 445, 477 rv_op_vl4re16_v = 446, 478 rv_op_vl4re32_v = 447, 479 rv_op_vl4re64_v = 448, 480 rv_op_vl8re8_v = 449, 481 rv_op_vl8re16_v = 450, 482 rv_op_vl8re32_v = 451, 483 rv_op_vl8re64_v = 452, 484 rv_op_vs1r_v = 453, 485 rv_op_vs2r_v = 454, 486 rv_op_vs4r_v = 455, 487 rv_op_vs8r_v = 456, 488 rv_op_vadd_vv = 457, 489 rv_op_vadd_vx = 458, 490 rv_op_vadd_vi = 459, 491 rv_op_vsub_vv = 460, 492 rv_op_vsub_vx = 461, 493 rv_op_vrsub_vx = 462, 494 rv_op_vrsub_vi = 463, 495 rv_op_vwaddu_vv = 464, 496 rv_op_vwaddu_vx = 465, 497 rv_op_vwadd_vv = 466, 498 rv_op_vwadd_vx = 467, 499 rv_op_vwsubu_vv = 468, 500 rv_op_vwsubu_vx = 469, 501 rv_op_vwsub_vv = 470, 502 rv_op_vwsub_vx = 471, 503 rv_op_vwaddu_wv = 472, 504 rv_op_vwaddu_wx = 473, 505 rv_op_vwadd_wv = 474, 506 rv_op_vwadd_wx = 475, 507 rv_op_vwsubu_wv = 476, 508 rv_op_vwsubu_wx = 477, 509 rv_op_vwsub_wv = 478, 510 rv_op_vwsub_wx = 479, 511 rv_op_vadc_vvm = 480, 512 rv_op_vadc_vxm = 481, 513 rv_op_vadc_vim = 482, 514 rv_op_vmadc_vvm = 483, 515 rv_op_vmadc_vxm = 484, 516 rv_op_vmadc_vim = 485, 517 rv_op_vsbc_vvm = 486, 518 rv_op_vsbc_vxm = 487, 519 rv_op_vmsbc_vvm = 488, 520 rv_op_vmsbc_vxm = 489, 521 rv_op_vand_vv = 490, 522 rv_op_vand_vx = 491, 523 rv_op_vand_vi = 492, 524 rv_op_vor_vv = 493, 525 rv_op_vor_vx = 494, 526 rv_op_vor_vi = 495, 527 rv_op_vxor_vv = 496, 528 rv_op_vxor_vx = 497, 529 rv_op_vxor_vi = 498, 530 rv_op_vsll_vv = 499, 531 rv_op_vsll_vx = 500, 532 rv_op_vsll_vi = 501, 533 rv_op_vsrl_vv = 502, 534 rv_op_vsrl_vx = 503, 535 rv_op_vsrl_vi = 504, 536 rv_op_vsra_vv = 505, 537 rv_op_vsra_vx = 506, 538 rv_op_vsra_vi = 507, 539 rv_op_vnsrl_wv = 508, 540 rv_op_vnsrl_wx = 509, 541 rv_op_vnsrl_wi = 510, 542 rv_op_vnsra_wv = 511, 543 rv_op_vnsra_wx = 512, 544 rv_op_vnsra_wi = 513, 545 rv_op_vmseq_vv = 514, 546 rv_op_vmseq_vx = 515, 547 rv_op_vmseq_vi = 516, 548 rv_op_vmsne_vv = 517, 549 rv_op_vmsne_vx = 518, 550 rv_op_vmsne_vi = 519, 551 rv_op_vmsltu_vv = 520, 552 rv_op_vmsltu_vx = 521, 553 rv_op_vmslt_vv = 522, 554 rv_op_vmslt_vx = 523, 555 rv_op_vmsleu_vv = 524, 556 rv_op_vmsleu_vx = 525, 557 rv_op_vmsleu_vi = 526, 558 rv_op_vmsle_vv = 527, 559 rv_op_vmsle_vx = 528, 560 rv_op_vmsle_vi = 529, 561 rv_op_vmsgtu_vx = 530, 562 rv_op_vmsgtu_vi = 531, 563 rv_op_vmsgt_vx = 532, 564 rv_op_vmsgt_vi = 533, 565 rv_op_vminu_vv = 534, 566 rv_op_vminu_vx = 535, 567 rv_op_vmin_vv = 536, 568 rv_op_vmin_vx = 537, 569 rv_op_vmaxu_vv = 538, 570 rv_op_vmaxu_vx = 539, 571 rv_op_vmax_vv = 540, 572 rv_op_vmax_vx = 541, 573 rv_op_vmul_vv = 542, 574 rv_op_vmul_vx = 543, 575 rv_op_vmulh_vv = 544, 576 rv_op_vmulh_vx = 545, 577 rv_op_vmulhu_vv = 546, 578 rv_op_vmulhu_vx = 547, 579 rv_op_vmulhsu_vv = 548, 580 rv_op_vmulhsu_vx = 549, 581 rv_op_vdivu_vv = 550, 582 rv_op_vdivu_vx = 551, 583 rv_op_vdiv_vv = 552, 584 rv_op_vdiv_vx = 553, 585 rv_op_vremu_vv = 554, 586 rv_op_vremu_vx = 555, 587 rv_op_vrem_vv = 556, 588 rv_op_vrem_vx = 557, 589 rv_op_vwmulu_vv = 558, 590 rv_op_vwmulu_vx = 559, 591 rv_op_vwmulsu_vv = 560, 592 rv_op_vwmulsu_vx = 561, 593 rv_op_vwmul_vv = 562, 594 rv_op_vwmul_vx = 563, 595 rv_op_vmacc_vv = 564, 596 rv_op_vmacc_vx = 565, 597 rv_op_vnmsac_vv = 566, 598 rv_op_vnmsac_vx = 567, 599 rv_op_vmadd_vv = 568, 600 rv_op_vmadd_vx = 569, 601 rv_op_vnmsub_vv = 570, 602 rv_op_vnmsub_vx = 571, 603 rv_op_vwmaccu_vv = 572, 604 rv_op_vwmaccu_vx = 573, 605 rv_op_vwmacc_vv = 574, 606 rv_op_vwmacc_vx = 575, 607 rv_op_vwmaccsu_vv = 576, 608 rv_op_vwmaccsu_vx = 577, 609 rv_op_vwmaccus_vx = 578, 610 rv_op_vmv_v_v = 579, 611 rv_op_vmv_v_x = 580, 612 rv_op_vmv_v_i = 581, 613 rv_op_vmerge_vvm = 582, 614 rv_op_vmerge_vxm = 583, 615 rv_op_vmerge_vim = 584, 616 rv_op_vsaddu_vv = 585, 617 rv_op_vsaddu_vx = 586, 618 rv_op_vsaddu_vi = 587, 619 rv_op_vsadd_vv = 588, 620 rv_op_vsadd_vx = 589, 621 rv_op_vsadd_vi = 590, 622 rv_op_vssubu_vv = 591, 623 rv_op_vssubu_vx = 592, 624 rv_op_vssub_vv = 593, 625 rv_op_vssub_vx = 594, 626 rv_op_vaadd_vv = 595, 627 rv_op_vaadd_vx = 596, 628 rv_op_vaaddu_vv = 597, 629 rv_op_vaaddu_vx = 598, 630 rv_op_vasub_vv = 599, 631 rv_op_vasub_vx = 600, 632 rv_op_vasubu_vv = 601, 633 rv_op_vasubu_vx = 602, 634 rv_op_vsmul_vv = 603, 635 rv_op_vsmul_vx = 604, 636 rv_op_vssrl_vv = 605, 637 rv_op_vssrl_vx = 606, 638 rv_op_vssrl_vi = 607, 639 rv_op_vssra_vv = 608, 640 rv_op_vssra_vx = 609, 641 rv_op_vssra_vi = 610, 642 rv_op_vnclipu_wv = 611, 643 rv_op_vnclipu_wx = 612, 644 rv_op_vnclipu_wi = 613, 645 rv_op_vnclip_wv = 614, 646 rv_op_vnclip_wx = 615, 647 rv_op_vnclip_wi = 616, 648 rv_op_vfadd_vv = 617, 649 rv_op_vfadd_vf = 618, 650 rv_op_vfsub_vv = 619, 651 rv_op_vfsub_vf = 620, 652 rv_op_vfrsub_vf = 621, 653 rv_op_vfwadd_vv = 622, 654 rv_op_vfwadd_vf = 623, 655 rv_op_vfwadd_wv = 624, 656 rv_op_vfwadd_wf = 625, 657 rv_op_vfwsub_vv = 626, 658 rv_op_vfwsub_vf = 627, 659 rv_op_vfwsub_wv = 628, 660 rv_op_vfwsub_wf = 629, 661 rv_op_vfmul_vv = 630, 662 rv_op_vfmul_vf = 631, 663 rv_op_vfdiv_vv = 632, 664 rv_op_vfdiv_vf = 633, 665 rv_op_vfrdiv_vf = 634, 666 rv_op_vfwmul_vv = 635, 667 rv_op_vfwmul_vf = 636, 668 rv_op_vfmacc_vv = 637, 669 rv_op_vfmacc_vf = 638, 670 rv_op_vfnmacc_vv = 639, 671 rv_op_vfnmacc_vf = 640, 672 rv_op_vfmsac_vv = 641, 673 rv_op_vfmsac_vf = 642, 674 rv_op_vfnmsac_vv = 643, 675 rv_op_vfnmsac_vf = 644, 676 rv_op_vfmadd_vv = 645, 677 rv_op_vfmadd_vf = 646, 678 rv_op_vfnmadd_vv = 647, 679 rv_op_vfnmadd_vf = 648, 680 rv_op_vfmsub_vv = 649, 681 rv_op_vfmsub_vf = 650, 682 rv_op_vfnmsub_vv = 651, 683 rv_op_vfnmsub_vf = 652, 684 rv_op_vfwmacc_vv = 653, 685 rv_op_vfwmacc_vf = 654, 686 rv_op_vfwnmacc_vv = 655, 687 rv_op_vfwnmacc_vf = 656, 688 rv_op_vfwmsac_vv = 657, 689 rv_op_vfwmsac_vf = 658, 690 rv_op_vfwnmsac_vv = 659, 691 rv_op_vfwnmsac_vf = 660, 692 rv_op_vfsqrt_v = 661, 693 rv_op_vfrsqrt7_v = 662, 694 rv_op_vfrec7_v = 663, 695 rv_op_vfmin_vv = 664, 696 rv_op_vfmin_vf = 665, 697 rv_op_vfmax_vv = 666, 698 rv_op_vfmax_vf = 667, 699 rv_op_vfsgnj_vv = 668, 700 rv_op_vfsgnj_vf = 669, 701 rv_op_vfsgnjn_vv = 670, 702 rv_op_vfsgnjn_vf = 671, 703 rv_op_vfsgnjx_vv = 672, 704 rv_op_vfsgnjx_vf = 673, 705 rv_op_vfslide1up_vf = 674, 706 rv_op_vfslide1down_vf = 675, 707 rv_op_vmfeq_vv = 676, 708 rv_op_vmfeq_vf = 677, 709 rv_op_vmfne_vv = 678, 710 rv_op_vmfne_vf = 679, 711 rv_op_vmflt_vv = 680, 712 rv_op_vmflt_vf = 681, 713 rv_op_vmfle_vv = 682, 714 rv_op_vmfle_vf = 683, 715 rv_op_vmfgt_vf = 684, 716 rv_op_vmfge_vf = 685, 717 rv_op_vfclass_v = 686, 718 rv_op_vfmerge_vfm = 687, 719 rv_op_vfmv_v_f = 688, 720 rv_op_vfcvt_xu_f_v = 689, 721 rv_op_vfcvt_x_f_v = 690, 722 rv_op_vfcvt_f_xu_v = 691, 723 rv_op_vfcvt_f_x_v = 692, 724 rv_op_vfcvt_rtz_xu_f_v = 693, 725 rv_op_vfcvt_rtz_x_f_v = 694, 726 rv_op_vfwcvt_xu_f_v = 695, 727 rv_op_vfwcvt_x_f_v = 696, 728 rv_op_vfwcvt_f_xu_v = 697, 729 rv_op_vfwcvt_f_x_v = 698, 730 rv_op_vfwcvt_f_f_v = 699, 731 rv_op_vfwcvt_rtz_xu_f_v = 700, 732 rv_op_vfwcvt_rtz_x_f_v = 701, 733 rv_op_vfncvt_xu_f_w = 702, 734 rv_op_vfncvt_x_f_w = 703, 735 rv_op_vfncvt_f_xu_w = 704, 736 rv_op_vfncvt_f_x_w = 705, 737 rv_op_vfncvt_f_f_w = 706, 738 rv_op_vfncvt_rod_f_f_w = 707, 739 rv_op_vfncvt_rtz_xu_f_w = 708, 740 rv_op_vfncvt_rtz_x_f_w = 709, 741 rv_op_vredsum_vs = 710, 742 rv_op_vredand_vs = 711, 743 rv_op_vredor_vs = 712, 744 rv_op_vredxor_vs = 713, 745 rv_op_vredminu_vs = 714, 746 rv_op_vredmin_vs = 715, 747 rv_op_vredmaxu_vs = 716, 748 rv_op_vredmax_vs = 717, 749 rv_op_vwredsumu_vs = 718, 750 rv_op_vwredsum_vs = 719, 751 rv_op_vfredusum_vs = 720, 752 rv_op_vfredosum_vs = 721, 753 rv_op_vfredmin_vs = 722, 754 rv_op_vfredmax_vs = 723, 755 rv_op_vfwredusum_vs = 724, 756 rv_op_vfwredosum_vs = 725, 757 rv_op_vmand_mm = 726, 758 rv_op_vmnand_mm = 727, 759 rv_op_vmandn_mm = 728, 760 rv_op_vmxor_mm = 729, 761 rv_op_vmor_mm = 730, 762 rv_op_vmnor_mm = 731, 763 rv_op_vmorn_mm = 732, 764 rv_op_vmxnor_mm = 733, 765 rv_op_vcpop_m = 734, 766 rv_op_vfirst_m = 735, 767 rv_op_vmsbf_m = 736, 768 rv_op_vmsif_m = 737, 769 rv_op_vmsof_m = 738, 770 rv_op_viota_m = 739, 771 rv_op_vid_v = 740, 772 rv_op_vmv_x_s = 741, 773 rv_op_vmv_s_x = 742, 774 rv_op_vfmv_f_s = 743, 775 rv_op_vfmv_s_f = 744, 776 rv_op_vslideup_vx = 745, 777 rv_op_vslideup_vi = 746, 778 rv_op_vslide1up_vx = 747, 779 rv_op_vslidedown_vx = 748, 780 rv_op_vslidedown_vi = 749, 781 rv_op_vslide1down_vx = 750, 782 rv_op_vrgather_vv = 751, 783 rv_op_vrgatherei16_vv = 752, 784 rv_op_vrgather_vx = 753, 785 rv_op_vrgather_vi = 754, 786 rv_op_vcompress_vm = 755, 787 rv_op_vmv1r_v = 756, 788 rv_op_vmv2r_v = 757, 789 rv_op_vmv4r_v = 758, 790 rv_op_vmv8r_v = 759, 791 rv_op_vzext_vf2 = 760, 792 rv_op_vzext_vf4 = 761, 793 rv_op_vzext_vf8 = 762, 794 rv_op_vsext_vf2 = 763, 795 rv_op_vsext_vf4 = 764, 796 rv_op_vsext_vf8 = 765, 797 rv_op_vsetvli = 766, 798 rv_op_vsetivli = 767, 799 rv_op_vsetvl = 768, 800 rv_op_c_zext_b = 769, 801 rv_op_c_sext_b = 770, 802 rv_op_c_zext_h = 771, 803 rv_op_c_sext_h = 772, 804 rv_op_c_zext_w = 773, 805 rv_op_c_not = 774, 806 rv_op_c_mul = 775, 807 rv_op_c_lbu = 776, 808 rv_op_c_lhu = 777, 809 rv_op_c_lh = 778, 810 rv_op_c_sb = 779, 811 rv_op_c_sh = 780, 812 rv_op_cm_push = 781, 813 rv_op_cm_pop = 782, 814 rv_op_cm_popret = 783, 815 rv_op_cm_popretz = 784, 816 rv_op_cm_mva01s = 785, 817 rv_op_cm_mvsa01 = 786, 818 rv_op_cm_jt = 787, 819 rv_op_cm_jalt = 788, 820 rv_op_czero_eqz = 789, 821 rv_op_czero_nez = 790, 822 rv_op_fcvt_bf16_s = 791, 823 rv_op_fcvt_s_bf16 = 792, 824 rv_op_vfncvtbf16_f_f_w = 793, 825 rv_op_vfwcvtbf16_f_f_v = 794, 826 rv_op_vfwmaccbf16_vv = 795, 827 rv_op_vfwmaccbf16_vf = 796, 828 rv_op_flh = 797, 829 rv_op_fsh = 798, 830 rv_op_fmv_h_x = 799, 831 rv_op_fmv_x_h = 800, 832 rv_op_fli_s = 801, 833 rv_op_fli_d = 802, 834 rv_op_fli_q = 803, 835 rv_op_fli_h = 804, 836 rv_op_fminm_s = 805, 837 rv_op_fmaxm_s = 806, 838 rv_op_fminm_d = 807, 839 rv_op_fmaxm_d = 808, 840 rv_op_fminm_q = 809, 841 rv_op_fmaxm_q = 810, 842 rv_op_fminm_h = 811, 843 rv_op_fmaxm_h = 812, 844 rv_op_fround_s = 813, 845 rv_op_froundnx_s = 814, 846 rv_op_fround_d = 815, 847 rv_op_froundnx_d = 816, 848 rv_op_fround_q = 817, 849 rv_op_froundnx_q = 818, 850 rv_op_fround_h = 819, 851 rv_op_froundnx_h = 820, 852 rv_op_fcvtmod_w_d = 821, 853 rv_op_fmvh_x_d = 822, 854 rv_op_fmvp_d_x = 823, 855 rv_op_fmvh_x_q = 824, 856 rv_op_fmvp_q_x = 825, 857 rv_op_fleq_s = 826, 858 rv_op_fltq_s = 827, 859 rv_op_fleq_d = 828, 860 rv_op_fltq_d = 829, 861 rv_op_fleq_q = 830, 862 rv_op_fltq_q = 831, 863 rv_op_fleq_h = 832, 864 rv_op_fltq_h = 833, 865 rv_op_vaesdf_vv = 834, 866 rv_op_vaesdf_vs = 835, 867 rv_op_vaesdm_vv = 836, 868 rv_op_vaesdm_vs = 837, 869 rv_op_vaesef_vv = 838, 870 rv_op_vaesef_vs = 839, 871 rv_op_vaesem_vv = 840, 872 rv_op_vaesem_vs = 841, 873 rv_op_vaeskf1_vi = 842, 874 rv_op_vaeskf2_vi = 843, 875 rv_op_vaesz_vs = 844, 876 rv_op_vandn_vv = 845, 877 rv_op_vandn_vx = 846, 878 rv_op_vbrev_v = 847, 879 rv_op_vbrev8_v = 848, 880 rv_op_vclmul_vv = 849, 881 rv_op_vclmul_vx = 850, 882 rv_op_vclmulh_vv = 851, 883 rv_op_vclmulh_vx = 852, 884 rv_op_vclz_v = 853, 885 rv_op_vcpop_v = 854, 886 rv_op_vctz_v = 855, 887 rv_op_vghsh_vv = 856, 888 rv_op_vgmul_vv = 857, 889 rv_op_vrev8_v = 858, 890 rv_op_vrol_vv = 859, 891 rv_op_vrol_vx = 860, 892 rv_op_vror_vv = 861, 893 rv_op_vror_vx = 862, 894 rv_op_vror_vi = 863, 895 rv_op_vsha2ch_vv = 864, 896 rv_op_vsha2cl_vv = 865, 897 rv_op_vsha2ms_vv = 866, 898 rv_op_vsm3c_vi = 867, 899 rv_op_vsm3me_vv = 868, 900 rv_op_vsm4k_vi = 869, 901 rv_op_vsm4r_vv = 870, 902 rv_op_vsm4r_vs = 871, 903 rv_op_vwsll_vv = 872, 904 rv_op_vwsll_vx = 873, 905 rv_op_vwsll_vi = 874, 906 rv_op_amocas_w = 875, 907 rv_op_amocas_d = 876, 908 rv_op_amocas_q = 877, 909 rv_mop_r_0 = 878, 910 rv_mop_r_1 = 879, 911 rv_mop_r_2 = 880, 912 rv_mop_r_3 = 881, 913 rv_mop_r_4 = 882, 914 rv_mop_r_5 = 883, 915 rv_mop_r_6 = 884, 916 rv_mop_r_7 = 885, 917 rv_mop_r_8 = 886, 918 rv_mop_r_9 = 887, 919 rv_mop_r_10 = 888, 920 rv_mop_r_11 = 889, 921 rv_mop_r_12 = 890, 922 rv_mop_r_13 = 891, 923 rv_mop_r_14 = 892, 924 rv_mop_r_15 = 893, 925 rv_mop_r_16 = 894, 926 rv_mop_r_17 = 895, 927 rv_mop_r_18 = 896, 928 rv_mop_r_19 = 897, 929 rv_mop_r_20 = 898, 930 rv_mop_r_21 = 899, 931 rv_mop_r_22 = 900, 932 rv_mop_r_23 = 901, 933 rv_mop_r_24 = 902, 934 rv_mop_r_25 = 903, 935 rv_mop_r_26 = 904, 936 rv_mop_r_27 = 905, 937 rv_mop_r_28 = 906, 938 rv_mop_r_29 = 907, 939 rv_mop_r_30 = 908, 940 rv_mop_r_31 = 909, 941 rv_mop_rr_0 = 910, 942 rv_mop_rr_1 = 911, 943 rv_mop_rr_2 = 912, 944 rv_mop_rr_3 = 913, 945 rv_mop_rr_4 = 914, 946 rv_mop_rr_5 = 915, 947 rv_mop_rr_6 = 916, 948 rv_mop_rr_7 = 917, 949 } rv_op; 950 951 /* register names */ 952 953 static const char rv_ireg_name_sym[32][5] = { 954 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 955 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 956 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 957 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", 958 }; 959 960 static const char rv_freg_name_sym[32][5] = { 961 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", 962 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", 963 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", 964 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11", 965 }; 966 967 static const char rv_vreg_name_sym[32][4] = { 968 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 969 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 970 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 971 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 972 }; 973 974 /* The FLI.[HSDQ] numeric constants (0.0 for symbolic constants). 975 * The constants use the hex floating-point literal representation 976 * that is printed when using the printf %a format specifier, 977 * which matches the output that is generated by the disassembler. 978 */ 979 static const char rv_fli_name_const[32][9] = 980 { 981 "0x1p+0", "min", "0x1p-16", "0x1p-15", 982 "0x1p-8", "0x1p-7", "0x1p-4", "0x1p-3", 983 "0x1p-2", "0x1.4p-2", "0x1.8p-2", "0x1.cp-2", 984 "0x1p-1", "0x1.4p-1", "0x1.8p-1", "0x1.cp-1", 985 "0x1p+0", "0x1.4p+0", "0x1.8p+0", "0x1.cp+0", 986 "0x1p+1", "0x1.4p+1", "0x1.8p+1", "0x1p+2", 987 "0x1p+3", "0x1p+4", "0x1p+7", "0x1p+8", 988 "0x1p+15", "0x1p+16", "inf", "nan" 989 }; 990 991 /* pseudo-instruction constraints */ 992 993 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end }; 994 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, 995 rvc_end }; 996 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, 997 rvc_imm_eq_zero, rvc_end }; 998 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; 999 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end }; 1000 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end }; 1001 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end }; 1002 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end }; 1003 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end }; 1004 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end }; 1005 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end }; 1006 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end }; 1007 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1008 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1009 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1010 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1011 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1012 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1013 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1014 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1015 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1016 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end }; 1017 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end }; 1018 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end }; 1019 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end }; 1020 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end }; 1021 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end }; 1022 static const rvc_constraint rvcc_ble[] = { rvc_end }; 1023 static const rvc_constraint rvcc_bleu[] = { rvc_end }; 1024 static const rvc_constraint rvcc_bgt[] = { rvc_end }; 1025 static const rvc_constraint rvcc_bgtu[] = { rvc_end }; 1026 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end }; 1027 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, 1028 rvc_end }; 1029 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, 1030 rvc_end }; 1031 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, 1032 rvc_end }; 1033 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, 1034 rvc_end }; 1035 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, 1036 rvc_csr_eq_0xc02, rvc_end }; 1037 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, 1038 rvc_csr_eq_0xc80, rvc_end }; 1039 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, 1040 rvc_end }; 1041 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, 1042 rvc_csr_eq_0xc82, rvc_end }; 1043 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, 1044 rvc_end }; 1045 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, 1046 rvc_end }; 1047 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, 1048 rvc_end }; 1049 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end }; 1050 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end }; 1051 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end }; 1052 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end }; 1053 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end }; 1054 1055 /* pseudo-instruction metadata */ 1056 1057 static const rv_comp_data rvcp_jal[] = { 1058 { rv_op_j, rvcc_j }, 1059 { rv_op_jal, rvcc_jal }, 1060 { rv_op_illegal, NULL } 1061 }; 1062 1063 static const rv_comp_data rvcp_jalr[] = { 1064 { rv_op_ret, rvcc_ret }, 1065 { rv_op_jr, rvcc_jr }, 1066 { rv_op_jalr, rvcc_jalr }, 1067 { rv_op_illegal, NULL } 1068 }; 1069 1070 static const rv_comp_data rvcp_beq[] = { 1071 { rv_op_beqz, rvcc_beqz }, 1072 { rv_op_illegal, NULL } 1073 }; 1074 1075 static const rv_comp_data rvcp_bne[] = { 1076 { rv_op_bnez, rvcc_bnez }, 1077 { rv_op_illegal, NULL } 1078 }; 1079 1080 static const rv_comp_data rvcp_blt[] = { 1081 { rv_op_bltz, rvcc_bltz }, 1082 { rv_op_bgtz, rvcc_bgtz }, 1083 { rv_op_bgt, rvcc_bgt }, 1084 { rv_op_illegal, NULL } 1085 }; 1086 1087 static const rv_comp_data rvcp_bge[] = { 1088 { rv_op_blez, rvcc_blez }, 1089 { rv_op_bgez, rvcc_bgez }, 1090 { rv_op_ble, rvcc_ble }, 1091 { rv_op_illegal, NULL } 1092 }; 1093 1094 static const rv_comp_data rvcp_bltu[] = { 1095 { rv_op_bgtu, rvcc_bgtu }, 1096 { rv_op_illegal, NULL } 1097 }; 1098 1099 static const rv_comp_data rvcp_bgeu[] = { 1100 { rv_op_bleu, rvcc_bleu }, 1101 { rv_op_illegal, NULL } 1102 }; 1103 1104 static const rv_comp_data rvcp_addi[] = { 1105 { rv_op_nop, rvcc_nop }, 1106 { rv_op_mv, rvcc_mv }, 1107 { rv_op_illegal, NULL } 1108 }; 1109 1110 static const rv_comp_data rvcp_sltiu[] = { 1111 { rv_op_seqz, rvcc_seqz }, 1112 { rv_op_illegal, NULL } 1113 }; 1114 1115 static const rv_comp_data rvcp_xori[] = { 1116 { rv_op_not, rvcc_not }, 1117 { rv_op_illegal, NULL } 1118 }; 1119 1120 static const rv_comp_data rvcp_sub[] = { 1121 { rv_op_neg, rvcc_neg }, 1122 { rv_op_illegal, NULL } 1123 }; 1124 1125 static const rv_comp_data rvcp_slt[] = { 1126 { rv_op_sltz, rvcc_sltz }, 1127 { rv_op_sgtz, rvcc_sgtz }, 1128 { rv_op_illegal, NULL } 1129 }; 1130 1131 static const rv_comp_data rvcp_sltu[] = { 1132 { rv_op_snez, rvcc_snez }, 1133 { rv_op_illegal, NULL } 1134 }; 1135 1136 static const rv_comp_data rvcp_addiw[] = { 1137 { rv_op_sext_w, rvcc_sext_w }, 1138 { rv_op_illegal, NULL } 1139 }; 1140 1141 static const rv_comp_data rvcp_subw[] = { 1142 { rv_op_negw, rvcc_negw }, 1143 { rv_op_illegal, NULL } 1144 }; 1145 1146 static const rv_comp_data rvcp_csrrw[] = { 1147 { rv_op_fscsr, rvcc_fscsr }, 1148 { rv_op_fsrm, rvcc_fsrm }, 1149 { rv_op_fsflags, rvcc_fsflags }, 1150 { rv_op_illegal, NULL } 1151 }; 1152 1153 1154 static const rv_comp_data rvcp_csrrs[] = { 1155 { rv_op_rdcycle, rvcc_rdcycle }, 1156 { rv_op_rdtime, rvcc_rdtime }, 1157 { rv_op_rdinstret, rvcc_rdinstret }, 1158 { rv_op_rdcycleh, rvcc_rdcycleh }, 1159 { rv_op_rdtimeh, rvcc_rdtimeh }, 1160 { rv_op_rdinstreth, rvcc_rdinstreth }, 1161 { rv_op_frcsr, rvcc_frcsr }, 1162 { rv_op_frrm, rvcc_frrm }, 1163 { rv_op_frflags, rvcc_frflags }, 1164 { rv_op_illegal, NULL } 1165 }; 1166 1167 static const rv_comp_data rvcp_csrrwi[] = { 1168 { rv_op_fsrmi, rvcc_fsrmi }, 1169 { rv_op_fsflagsi, rvcc_fsflagsi }, 1170 { rv_op_illegal, NULL } 1171 }; 1172 1173 static const rv_comp_data rvcp_fsgnj_s[] = { 1174 { rv_op_fmv_s, rvcc_fmv_s }, 1175 { rv_op_illegal, NULL } 1176 }; 1177 1178 static const rv_comp_data rvcp_fsgnjn_s[] = { 1179 { rv_op_fneg_s, rvcc_fneg_s }, 1180 { rv_op_illegal, NULL } 1181 }; 1182 1183 static const rv_comp_data rvcp_fsgnjx_s[] = { 1184 { rv_op_fabs_s, rvcc_fabs_s }, 1185 { rv_op_illegal, NULL } 1186 }; 1187 1188 static const rv_comp_data rvcp_fsgnj_d[] = { 1189 { rv_op_fmv_d, rvcc_fmv_d }, 1190 { rv_op_illegal, NULL } 1191 }; 1192 1193 static const rv_comp_data rvcp_fsgnjn_d[] = { 1194 { rv_op_fneg_d, rvcc_fneg_d }, 1195 { rv_op_illegal, NULL } 1196 }; 1197 1198 static const rv_comp_data rvcp_fsgnjx_d[] = { 1199 { rv_op_fabs_d, rvcc_fabs_d }, 1200 { rv_op_illegal, NULL } 1201 }; 1202 1203 static const rv_comp_data rvcp_fsgnj_q[] = { 1204 { rv_op_fmv_q, rvcc_fmv_q }, 1205 { rv_op_illegal, NULL } 1206 }; 1207 1208 static const rv_comp_data rvcp_fsgnjn_q[] = { 1209 { rv_op_fneg_q, rvcc_fneg_q }, 1210 { rv_op_illegal, NULL } 1211 }; 1212 1213 static const rv_comp_data rvcp_fsgnjx_q[] = { 1214 { rv_op_fabs_q, rvcc_fabs_q }, 1215 { rv_op_illegal, NULL } 1216 }; 1217 1218 /* instruction metadata */ 1219 1220 const rv_opcode_data rvi_opcode_data[] = { 1221 { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, 1222 { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 }, 1223 { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 }, 1224 { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 }, 1225 { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 }, 1226 { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 }, 1227 { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 }, 1228 { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 }, 1229 { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 }, 1230 { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 }, 1231 { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 }, 1232 { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1233 { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1234 { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1235 { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1236 { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1237 { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1238 { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1239 { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1240 { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 }, 1241 { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1242 { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 }, 1243 { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 }, 1244 { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1245 { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1246 { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1247 { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1248 { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1249 { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1250 { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 }, 1251 { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1252 { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 }, 1253 { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 }, 1254 { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1255 { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1256 { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1257 { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1258 { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1259 { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 }, 1260 { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1261 { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1262 { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1263 { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1264 { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 }, 1265 { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1266 { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1267 { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1268 { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1269 { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 }, 1270 { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1271 { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1272 { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1273 { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1274 { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1275 { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1276 { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1277 { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1278 { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1279 { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1280 { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1281 { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1282 { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1283 { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1284 { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1285 { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1286 { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1287 { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1288 { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1289 { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1290 { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1291 { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1292 { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1293 { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1294 { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1295 { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1296 { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1297 { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1298 { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1299 { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1300 { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1301 { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1302 { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1303 { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1304 { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1305 { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1306 { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1307 { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1308 { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1309 { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1310 { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1311 { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1312 { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1313 { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1314 { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1315 { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1316 { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1317 { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1318 { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1319 { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1320 { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1321 { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1322 { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1323 { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1324 { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1325 { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1326 { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1327 { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1328 { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1329 { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1330 { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1331 { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1332 { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1333 { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1334 { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1335 { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1336 { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1337 { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1338 { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1339 { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1340 { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1341 { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1342 { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1343 { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, 1344 { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 }, 1345 { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1346 { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 }, 1347 { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 }, 1348 { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 }, 1349 { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 }, 1350 { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1351 { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1352 { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1353 { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1354 { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1355 { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1356 { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1357 { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1358 { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1359 { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1360 { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1361 { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1362 { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 }, 1363 { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 }, 1364 { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 }, 1365 { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1366 { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1367 { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1368 { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1369 { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1370 { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1371 { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1372 { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1373 { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1374 { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1375 { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1376 { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1377 { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1378 { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1379 { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1380 { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1381 { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1382 { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1383 { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1384 { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1385 { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1386 { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1387 { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1388 { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1389 { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1390 { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1391 { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1392 { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 }, 1393 { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 }, 1394 { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 }, 1395 { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1396 { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1397 { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1398 { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1399 { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1400 { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1401 { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1402 { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1403 { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1404 { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1405 { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1406 { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1407 { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1408 { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1409 { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1410 { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1411 { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1412 { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1413 { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1414 { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1415 { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1416 { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1417 { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1418 { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1419 { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1420 { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1421 { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1422 { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1423 { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1424 { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 }, 1425 { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 }, 1426 { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 }, 1427 { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1428 { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1429 { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1430 { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1431 { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1432 { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1433 { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1434 { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1435 { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1436 { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1437 { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1438 { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1439 { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1440 { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1441 { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1442 { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1443 { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1444 { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1445 { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1446 { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1447 { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1448 { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1449 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1450 { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1451 rv_op_fld, 0 }, 1452 { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, 1453 rv_op_lw }, 1454 { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, 1455 { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1456 rv_op_fsd, 0 }, 1457 { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, 1458 rv_op_sw }, 1459 { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, 1460 { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, 1461 rv_op_addi }, 1462 { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1463 rv_op_addi, rvcd_imm_nz }, 1464 { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 }, 1465 { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1466 rv_op_addi }, 1467 { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1468 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1469 { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui, 1470 rv_op_lui, rvcd_imm_nz }, 1471 { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, 1472 rv_op_srli, rv_op_srli, rvcd_imm_nz }, 1473 { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, 1474 rv_op_srai, rv_op_srai, rvcd_imm_nz }, 1475 { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, 1476 rv_op_andi, rv_op_andi }, 1477 { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, 1478 rv_op_sub }, 1479 { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, 1480 rv_op_xor }, 1481 { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, 1482 rv_op_or }, 1483 { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, 1484 rv_op_and }, 1485 { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, 1486 rv_op_subw }, 1487 { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, 1488 rv_op_addw }, 1489 { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, 1490 rv_op_jal }, 1491 { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, 1492 rv_op_beq }, 1493 { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, 1494 rv_op_bne }, 1495 { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, 1496 rv_op_slli, rv_op_slli, rvcd_imm_nz }, 1497 { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1498 rv_op_fld, rv_op_fld }, 1499 { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, 1500 rv_op_lw, rv_op_lw }, 1501 { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 1502 0 }, 1503 { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1504 rv_op_jalr, rv_op_jalr }, 1505 { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, 1506 rv_op_addi }, 1507 { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, 1508 rv_op_ebreak, rv_op_ebreak }, 1509 { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1510 rv_op_jalr, rv_op_jalr }, 1511 { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, 1512 rv_op_add }, 1513 { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1514 rv_op_fsd, rv_op_fsd }, 1515 { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, 1516 rv_op_sw, rv_op_sw }, 1517 { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 1518 0 }, 1519 { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1520 rv_op_ld }, 1521 { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1522 rv_op_sd }, 1523 { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, 1524 rv_op_addiw }, 1525 { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1526 rv_op_ld }, 1527 { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1528 rv_op_sd }, 1529 { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1530 { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, 1531 { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1532 { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 1533 rv_op_sq }, 1534 { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1535 { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1536 { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1537 { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1538 { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1539 { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1540 { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1541 { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1542 { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1543 { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1544 { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1545 { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1546 { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1547 { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1548 { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1549 { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1550 { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1551 { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1552 { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1553 { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1554 { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1555 { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1556 { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1557 { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1558 { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1559 { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1560 { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1561 { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1562 { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1563 { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 }, 1564 { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1565 { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 }, 1566 { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1567 { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1568 { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1569 { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1570 { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1571 { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1572 { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1573 { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1574 { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1575 { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1576 { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1577 { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1578 { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1579 { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1580 { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1581 { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1582 { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1583 { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1584 { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1585 { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1586 { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1587 { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1588 { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1589 { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1590 { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1591 { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1592 { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1593 { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1594 { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1595 { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1596 { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1597 { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1598 { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1599 { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1600 { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1601 { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1602 { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1603 { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1604 { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1605 { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1606 { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1607 { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1608 { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1609 { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1610 { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1611 { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1612 { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1613 { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1614 { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1615 { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1616 { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1617 { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1618 { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1619 { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1620 { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1621 { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1622 { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1623 { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1624 { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1625 { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1626 { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1627 { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 }, 1628 { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1629 { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1630 { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1631 { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1632 { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1633 { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1634 { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1635 { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1636 { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1637 { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1638 { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1639 { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1640 { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1641 { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1642 { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1643 { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1644 { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1645 { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1646 { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1647 { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1648 { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1649 { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1650 { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1651 { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1652 { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1653 { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1654 { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1655 { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1656 { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1657 { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1658 { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1659 { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1660 { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1661 { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1662 { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1663 { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1664 { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1665 { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1666 { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1667 { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1668 { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1669 { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1670 { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1671 { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1672 { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1673 { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1674 { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1675 { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1676 { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1677 { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1678 { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1679 { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1680 { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1681 { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1682 { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1683 { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1684 { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1685 { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1686 { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1687 { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1688 { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1689 { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1690 { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1691 { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1692 { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1693 { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1694 { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1695 { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1696 { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1697 { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1698 { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1699 { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1700 { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1701 { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1702 { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1703 { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1704 { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1705 { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1706 { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1707 { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1708 { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1709 { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1710 { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1711 { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1712 { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1713 { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1714 { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1715 { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1716 { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1717 { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1718 { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1719 { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1720 { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1721 { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1722 { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1723 { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1724 { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1725 { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1726 { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1727 { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1728 { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1729 { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1730 { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1731 { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1732 { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1733 { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1734 { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1735 { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1736 { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1737 { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1738 { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1739 { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1740 { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1741 { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1742 { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1743 { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1744 { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1745 { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1746 { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1747 { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1748 { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1749 { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1750 { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1751 { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1752 { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1753 { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1754 { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1755 { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1756 { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1757 { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1758 { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1759 { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1760 { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1761 { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1762 { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1763 { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1764 { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1765 { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1766 { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1767 { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1768 { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1769 { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1770 { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1771 { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1772 { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1773 { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1774 { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1775 { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1776 { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1777 { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1778 { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1779 { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1780 { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1781 { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1782 { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1783 { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1784 { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1785 { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1786 { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1787 { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1788 { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1789 { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1790 { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1791 { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1792 { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1793 { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1794 { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1795 { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1796 { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1797 { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1798 { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1799 { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1800 { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1801 { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1802 { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1803 { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1804 { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1805 { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1806 { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1807 { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1808 { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1809 { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1810 { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1811 { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1812 { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1813 { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1814 { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1815 { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1816 { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1817 { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1818 { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1819 { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1820 { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1821 { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1822 { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1823 { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1824 { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1825 { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1826 { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1827 { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1828 { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1829 { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1830 { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1831 { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1832 { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1833 { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1834 { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1835 { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1836 { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1837 { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1838 { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1839 { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1840 { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 }, 1841 { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 1842 { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 }, 1843 { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1844 { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1845 { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1846 { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1847 { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1848 { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1849 { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1850 { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1851 { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1852 { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1853 { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1854 { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1855 { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1856 { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1857 { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1858 { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1859 { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1860 { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1861 { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1862 { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1863 { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1864 { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1865 { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1866 { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1867 { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1868 { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1869 { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1870 { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1871 { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1872 { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1873 { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1874 { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1875 { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1876 { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1877 { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1878 { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1879 { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1880 { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1881 { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1882 { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1883 { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1884 { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1885 { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1886 { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1887 { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1888 { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1889 { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1890 { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1891 { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1892 { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1893 { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1894 { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1895 { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1896 { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1897 { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1898 { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1899 { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1900 { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1901 { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1902 { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1903 { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1904 { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1905 { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1906 { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1907 { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1908 { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1909 { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1910 { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1911 { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1912 { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1913 { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1914 { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1915 { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1916 { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1917 { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1918 { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1919 { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1920 { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1921 { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1922 { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1923 { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1924 { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1925 { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1926 { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1927 { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1928 { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1929 { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1930 { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1931 { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1932 { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1933 { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1934 { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1935 { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1936 { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1937 { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1938 { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1939 { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1940 { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1941 { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1942 { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1943 { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1944 { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1945 { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1946 { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1947 { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1948 { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 }, 1949 { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 1950 { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1951 { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1952 { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1953 { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1954 { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1955 { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1956 { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1957 { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1958 { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1959 { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1960 { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1961 { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1962 { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1963 { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1964 { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1965 { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1966 { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1967 { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1968 { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1969 { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1970 { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1971 { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1972 { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1973 { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1974 { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1975 { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1976 { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1977 { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1978 { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1979 { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1980 { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1981 { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1982 { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1983 { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1984 { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1985 { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1986 { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1987 { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1988 { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1989 { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1990 { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1991 { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1992 { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1993 { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1994 { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1995 { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 1996 { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 1997 { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1998 { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1999 { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2000 { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2001 { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 }, 2002 { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 }, 2003 { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 2004 { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 }, 2005 { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 2006 { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2007 { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2008 { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2009 { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2010 { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2011 { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2012 { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2013 { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2014 { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2015 { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2016 { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2017 { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2018 { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2019 { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2020 { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2021 { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2022 { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2023 { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2024 { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2025 { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2026 { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2027 { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 }, 2028 { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 }, 2029 { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2030 { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2031 { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2032 { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2033 { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2034 { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2035 { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2036 { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 }, 2037 { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2038 { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2039 { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2040 { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2041 { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2042 { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 }, 2043 { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2044 { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 }, 2045 { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2046 { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2047 { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2048 { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2049 { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2050 { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2051 { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2052 { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2053 { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2054 { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2055 { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2056 { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 2057 { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 2058 { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 2059 { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 2060 { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 2061 { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2062 { "fli.s", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2063 { "fli.d", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2064 { "fli.q", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2065 { "fli.h", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2066 { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2067 { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2068 { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2069 { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2070 { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2071 { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2072 { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2073 { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2074 { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2075 { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2076 { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2077 { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2078 { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2079 { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2080 { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2081 { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2082 { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 2083 { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2084 { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2085 { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2086 { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2087 { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2088 { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2089 { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2090 { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2091 { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2092 { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2093 { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2094 { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2095 { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2096 { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2097 { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2098 { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2099 { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2100 { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2101 { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2102 { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2103 { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2104 { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2105 { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2106 { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2107 { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2108 { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2109 { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2110 { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2111 { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2112 { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2113 { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2114 { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2115 { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2116 { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2117 { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2118 { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2119 { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2120 { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2121 { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2122 { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2123 { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2124 { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2125 { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2126 { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2127 { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2128 { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2129 { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2130 { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2131 { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2132 { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2133 { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2134 { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2135 { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2136 { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2137 { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2138 { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2139 { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2140 { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2141 { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2142 { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2143 { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2144 { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2145 { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2146 { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2147 { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2148 { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2149 { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2150 { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2151 { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2152 { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2153 { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2154 { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2155 { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2156 { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2157 { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2158 { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2159 { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2160 { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2161 { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2162 { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2163 { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2164 { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2165 { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2166 { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2167 { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2168 { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2169 { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2170 { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2171 { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2172 { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2173 { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2174 { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2175 { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2176 { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2177 { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2178 { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2179 }; 2180 2181 /* CSR names */ 2182 2183 static const char *csr_name(int csrno) 2184 { 2185 switch (csrno) { 2186 case 0x0000: return "ustatus"; 2187 case 0x0001: return "fflags"; 2188 case 0x0002: return "frm"; 2189 case 0x0003: return "fcsr"; 2190 case 0x0004: return "uie"; 2191 case 0x0005: return "utvec"; 2192 case 0x0008: return "vstart"; 2193 case 0x0009: return "vxsat"; 2194 case 0x000a: return "vxrm"; 2195 case 0x000f: return "vcsr"; 2196 case 0x0015: return "seed"; 2197 case 0x0017: return "jvt"; 2198 case 0x0040: return "uscratch"; 2199 case 0x0041: return "uepc"; 2200 case 0x0042: return "ucause"; 2201 case 0x0043: return "utval"; 2202 case 0x0044: return "uip"; 2203 case 0x0100: return "sstatus"; 2204 case 0x0104: return "sie"; 2205 case 0x0105: return "stvec"; 2206 case 0x0106: return "scounteren"; 2207 case 0x0140: return "sscratch"; 2208 case 0x0141: return "sepc"; 2209 case 0x0142: return "scause"; 2210 case 0x0143: return "stval"; 2211 case 0x0144: return "sip"; 2212 case 0x0180: return "satp"; 2213 case 0x0200: return "hstatus"; 2214 case 0x0202: return "hedeleg"; 2215 case 0x0203: return "hideleg"; 2216 case 0x0204: return "hie"; 2217 case 0x0205: return "htvec"; 2218 case 0x0240: return "hscratch"; 2219 case 0x0241: return "hepc"; 2220 case 0x0242: return "hcause"; 2221 case 0x0243: return "hbadaddr"; 2222 case 0x0244: return "hip"; 2223 case 0x0300: return "mstatus"; 2224 case 0x0301: return "misa"; 2225 case 0x0302: return "medeleg"; 2226 case 0x0303: return "mideleg"; 2227 case 0x0304: return "mie"; 2228 case 0x0305: return "mtvec"; 2229 case 0x0306: return "mcounteren"; 2230 case 0x0320: return "mucounteren"; 2231 case 0x0321: return "mscounteren"; 2232 case 0x0322: return "mhcounteren"; 2233 case 0x0323: return "mhpmevent3"; 2234 case 0x0324: return "mhpmevent4"; 2235 case 0x0325: return "mhpmevent5"; 2236 case 0x0326: return "mhpmevent6"; 2237 case 0x0327: return "mhpmevent7"; 2238 case 0x0328: return "mhpmevent8"; 2239 case 0x0329: return "mhpmevent9"; 2240 case 0x032a: return "mhpmevent10"; 2241 case 0x032b: return "mhpmevent11"; 2242 case 0x032c: return "mhpmevent12"; 2243 case 0x032d: return "mhpmevent13"; 2244 case 0x032e: return "mhpmevent14"; 2245 case 0x032f: return "mhpmevent15"; 2246 case 0x0330: return "mhpmevent16"; 2247 case 0x0331: return "mhpmevent17"; 2248 case 0x0332: return "mhpmevent18"; 2249 case 0x0333: return "mhpmevent19"; 2250 case 0x0334: return "mhpmevent20"; 2251 case 0x0335: return "mhpmevent21"; 2252 case 0x0336: return "mhpmevent22"; 2253 case 0x0337: return "mhpmevent23"; 2254 case 0x0338: return "mhpmevent24"; 2255 case 0x0339: return "mhpmevent25"; 2256 case 0x033a: return "mhpmevent26"; 2257 case 0x033b: return "mhpmevent27"; 2258 case 0x033c: return "mhpmevent28"; 2259 case 0x033d: return "mhpmevent29"; 2260 case 0x033e: return "mhpmevent30"; 2261 case 0x033f: return "mhpmevent31"; 2262 case 0x0340: return "mscratch"; 2263 case 0x0341: return "mepc"; 2264 case 0x0342: return "mcause"; 2265 case 0x0343: return "mtval"; 2266 case 0x0344: return "mip"; 2267 case 0x0380: return "mbase"; 2268 case 0x0381: return "mbound"; 2269 case 0x0382: return "mibase"; 2270 case 0x0383: return "mibound"; 2271 case 0x0384: return "mdbase"; 2272 case 0x0385: return "mdbound"; 2273 case 0x03a0: return "pmpcfg0"; 2274 case 0x03a1: return "pmpcfg1"; 2275 case 0x03a2: return "pmpcfg2"; 2276 case 0x03a3: return "pmpcfg3"; 2277 case 0x03a4: return "pmpcfg4"; 2278 case 0x03a5: return "pmpcfg5"; 2279 case 0x03a6: return "pmpcfg6"; 2280 case 0x03a7: return "pmpcfg7"; 2281 case 0x03a8: return "pmpcfg8"; 2282 case 0x03a9: return "pmpcfg9"; 2283 case 0x03aa: return "pmpcfg10"; 2284 case 0x03ab: return "pmpcfg11"; 2285 case 0x03ac: return "pmpcfg12"; 2286 case 0x03ad: return "pmpcfg13"; 2287 case 0x03ae: return "pmpcfg14"; 2288 case 0x03af: return "pmpcfg15"; 2289 case 0x03b0: return "pmpaddr0"; 2290 case 0x03b1: return "pmpaddr1"; 2291 case 0x03b2: return "pmpaddr2"; 2292 case 0x03b3: return "pmpaddr3"; 2293 case 0x03b4: return "pmpaddr4"; 2294 case 0x03b5: return "pmpaddr5"; 2295 case 0x03b6: return "pmpaddr6"; 2296 case 0x03b7: return "pmpaddr7"; 2297 case 0x03b8: return "pmpaddr8"; 2298 case 0x03b9: return "pmpaddr9"; 2299 case 0x03ba: return "pmpaddr10"; 2300 case 0x03bb: return "pmpaddr11"; 2301 case 0x03bc: return "pmpaddr12"; 2302 case 0x03bd: return "pmpaddr13"; 2303 case 0x03be: return "pmpaddr14"; 2304 case 0x03bf: return "pmpaddr15"; 2305 case 0x03c0: return "pmpaddr16"; 2306 case 0x03c1: return "pmpaddr17"; 2307 case 0x03c2: return "pmpaddr18"; 2308 case 0x03c3: return "pmpaddr19"; 2309 case 0x03c4: return "pmpaddr20"; 2310 case 0x03c5: return "pmpaddr21"; 2311 case 0x03c6: return "pmpaddr22"; 2312 case 0x03c7: return "pmpaddr23"; 2313 case 0x03c8: return "pmpaddr24"; 2314 case 0x03c9: return "pmpaddr25"; 2315 case 0x03ca: return "pmpaddr26"; 2316 case 0x03cb: return "pmpaddr27"; 2317 case 0x03cc: return "pmpaddr28"; 2318 case 0x03cd: return "pmpaddr29"; 2319 case 0x03ce: return "pmpaddr30"; 2320 case 0x03cf: return "pmpaddr31"; 2321 case 0x03d0: return "pmpaddr32"; 2322 case 0x03d1: return "pmpaddr33"; 2323 case 0x03d2: return "pmpaddr34"; 2324 case 0x03d3: return "pmpaddr35"; 2325 case 0x03d4: return "pmpaddr36"; 2326 case 0x03d5: return "pmpaddr37"; 2327 case 0x03d6: return "pmpaddr38"; 2328 case 0x03d7: return "pmpaddr39"; 2329 case 0x03d8: return "pmpaddr40"; 2330 case 0x03d9: return "pmpaddr41"; 2331 case 0x03da: return "pmpaddr42"; 2332 case 0x03db: return "pmpaddr43"; 2333 case 0x03dc: return "pmpaddr44"; 2334 case 0x03dd: return "pmpaddr45"; 2335 case 0x03de: return "pmpaddr46"; 2336 case 0x03df: return "pmpaddr47"; 2337 case 0x03e0: return "pmpaddr48"; 2338 case 0x03e1: return "pmpaddr49"; 2339 case 0x03e2: return "pmpaddr50"; 2340 case 0x03e3: return "pmpaddr51"; 2341 case 0x03e4: return "pmpaddr52"; 2342 case 0x03e5: return "pmpaddr53"; 2343 case 0x03e6: return "pmpaddr54"; 2344 case 0x03e7: return "pmpaddr55"; 2345 case 0x03e8: return "pmpaddr56"; 2346 case 0x03e9: return "pmpaddr57"; 2347 case 0x03ea: return "pmpaddr58"; 2348 case 0x03eb: return "pmpaddr59"; 2349 case 0x03ec: return "pmpaddr60"; 2350 case 0x03ed: return "pmpaddr61"; 2351 case 0x03ee: return "pmpaddr62"; 2352 case 0x03ef: return "pmpaddr63"; 2353 case 0x0780: return "mtohost"; 2354 case 0x0781: return "mfromhost"; 2355 case 0x0782: return "mreset"; 2356 case 0x0783: return "mipi"; 2357 case 0x0784: return "miobase"; 2358 case 0x07a0: return "tselect"; 2359 case 0x07a1: return "tdata1"; 2360 case 0x07a2: return "tdata2"; 2361 case 0x07a3: return "tdata3"; 2362 case 0x07b0: return "dcsr"; 2363 case 0x07b1: return "dpc"; 2364 case 0x07b2: return "dscratch"; 2365 case 0x0b00: return "mcycle"; 2366 case 0x0b01: return "mtime"; 2367 case 0x0b02: return "minstret"; 2368 case 0x0b03: return "mhpmcounter3"; 2369 case 0x0b04: return "mhpmcounter4"; 2370 case 0x0b05: return "mhpmcounter5"; 2371 case 0x0b06: return "mhpmcounter6"; 2372 case 0x0b07: return "mhpmcounter7"; 2373 case 0x0b08: return "mhpmcounter8"; 2374 case 0x0b09: return "mhpmcounter9"; 2375 case 0x0b0a: return "mhpmcounter10"; 2376 case 0x0b0b: return "mhpmcounter11"; 2377 case 0x0b0c: return "mhpmcounter12"; 2378 case 0x0b0d: return "mhpmcounter13"; 2379 case 0x0b0e: return "mhpmcounter14"; 2380 case 0x0b0f: return "mhpmcounter15"; 2381 case 0x0b10: return "mhpmcounter16"; 2382 case 0x0b11: return "mhpmcounter17"; 2383 case 0x0b12: return "mhpmcounter18"; 2384 case 0x0b13: return "mhpmcounter19"; 2385 case 0x0b14: return "mhpmcounter20"; 2386 case 0x0b15: return "mhpmcounter21"; 2387 case 0x0b16: return "mhpmcounter22"; 2388 case 0x0b17: return "mhpmcounter23"; 2389 case 0x0b18: return "mhpmcounter24"; 2390 case 0x0b19: return "mhpmcounter25"; 2391 case 0x0b1a: return "mhpmcounter26"; 2392 case 0x0b1b: return "mhpmcounter27"; 2393 case 0x0b1c: return "mhpmcounter28"; 2394 case 0x0b1d: return "mhpmcounter29"; 2395 case 0x0b1e: return "mhpmcounter30"; 2396 case 0x0b1f: return "mhpmcounter31"; 2397 case 0x0b80: return "mcycleh"; 2398 case 0x0b81: return "mtimeh"; 2399 case 0x0b82: return "minstreth"; 2400 case 0x0b83: return "mhpmcounter3h"; 2401 case 0x0b84: return "mhpmcounter4h"; 2402 case 0x0b85: return "mhpmcounter5h"; 2403 case 0x0b86: return "mhpmcounter6h"; 2404 case 0x0b87: return "mhpmcounter7h"; 2405 case 0x0b88: return "mhpmcounter8h"; 2406 case 0x0b89: return "mhpmcounter9h"; 2407 case 0x0b8a: return "mhpmcounter10h"; 2408 case 0x0b8b: return "mhpmcounter11h"; 2409 case 0x0b8c: return "mhpmcounter12h"; 2410 case 0x0b8d: return "mhpmcounter13h"; 2411 case 0x0b8e: return "mhpmcounter14h"; 2412 case 0x0b8f: return "mhpmcounter15h"; 2413 case 0x0b90: return "mhpmcounter16h"; 2414 case 0x0b91: return "mhpmcounter17h"; 2415 case 0x0b92: return "mhpmcounter18h"; 2416 case 0x0b93: return "mhpmcounter19h"; 2417 case 0x0b94: return "mhpmcounter20h"; 2418 case 0x0b95: return "mhpmcounter21h"; 2419 case 0x0b96: return "mhpmcounter22h"; 2420 case 0x0b97: return "mhpmcounter23h"; 2421 case 0x0b98: return "mhpmcounter24h"; 2422 case 0x0b99: return "mhpmcounter25h"; 2423 case 0x0b9a: return "mhpmcounter26h"; 2424 case 0x0b9b: return "mhpmcounter27h"; 2425 case 0x0b9c: return "mhpmcounter28h"; 2426 case 0x0b9d: return "mhpmcounter29h"; 2427 case 0x0b9e: return "mhpmcounter30h"; 2428 case 0x0b9f: return "mhpmcounter31h"; 2429 case 0x0c00: return "cycle"; 2430 case 0x0c01: return "time"; 2431 case 0x0c02: return "instret"; 2432 case 0x0c20: return "vl"; 2433 case 0x0c21: return "vtype"; 2434 case 0x0c22: return "vlenb"; 2435 case 0x0c80: return "cycleh"; 2436 case 0x0c81: return "timeh"; 2437 case 0x0c82: return "instreth"; 2438 case 0x0d00: return "scycle"; 2439 case 0x0d01: return "stime"; 2440 case 0x0d02: return "sinstret"; 2441 case 0x0d80: return "scycleh"; 2442 case 0x0d81: return "stimeh"; 2443 case 0x0d82: return "sinstreth"; 2444 case 0x0e00: return "hcycle"; 2445 case 0x0e01: return "htime"; 2446 case 0x0e02: return "hinstret"; 2447 case 0x0e80: return "hcycleh"; 2448 case 0x0e81: return "htimeh"; 2449 case 0x0e82: return "hinstreth"; 2450 case 0x0f11: return "mvendorid"; 2451 case 0x0f12: return "marchid"; 2452 case 0x0f13: return "mimpid"; 2453 case 0x0f14: return "mhartid"; 2454 default: return NULL; 2455 } 2456 } 2457 2458 /* decode opcode */ 2459 2460 static void decode_inst_opcode(rv_decode *dec, rv_isa isa) 2461 { 2462 rv_inst inst = dec->inst; 2463 rv_opcode op = rv_op_illegal; 2464 switch ((inst >> 0) & 0b11) { 2465 case 0: 2466 switch ((inst >> 13) & 0b111) { 2467 case 0: op = rv_op_c_addi4spn; break; 2468 case 1: 2469 if (isa == rv128) { 2470 op = rv_op_c_lq; 2471 } else { 2472 op = rv_op_c_fld; 2473 } 2474 break; 2475 case 2: op = rv_op_c_lw; break; 2476 case 3: 2477 if (isa == rv32) { 2478 op = rv_op_c_flw; 2479 } else { 2480 op = rv_op_c_ld; 2481 } 2482 break; 2483 case 4: 2484 switch ((inst >> 10) & 0b111) { 2485 case 0: op = rv_op_c_lbu; break; 2486 case 1: 2487 if (((inst >> 6) & 1) == 0) { 2488 op = rv_op_c_lhu; 2489 } else { 2490 op = rv_op_c_lh; 2491 } 2492 break; 2493 case 2: op = rv_op_c_sb; break; 2494 case 3: 2495 if (((inst >> 6) & 1) == 0) { 2496 op = rv_op_c_sh; 2497 } 2498 break; 2499 } 2500 break; 2501 case 5: 2502 if (isa == rv128) { 2503 op = rv_op_c_sq; 2504 } else { 2505 op = rv_op_c_fsd; 2506 } 2507 break; 2508 case 6: op = rv_op_c_sw; break; 2509 case 7: 2510 if (isa == rv32) { 2511 op = rv_op_c_fsw; 2512 } else { 2513 op = rv_op_c_sd; 2514 } 2515 break; 2516 } 2517 break; 2518 case 1: 2519 switch ((inst >> 13) & 0b111) { 2520 case 0: 2521 switch ((inst >> 2) & 0b11111111111) { 2522 case 0: op = rv_op_c_nop; break; 2523 default: op = rv_op_c_addi; break; 2524 } 2525 break; 2526 case 1: 2527 if (isa == rv32) { 2528 op = rv_op_c_jal; 2529 } else { 2530 op = rv_op_c_addiw; 2531 } 2532 break; 2533 case 2: op = rv_op_c_li; break; 2534 case 3: 2535 switch ((inst >> 7) & 0b11111) { 2536 case 2: op = rv_op_c_addi16sp; break; 2537 default: op = rv_op_c_lui; break; 2538 } 2539 break; 2540 case 4: 2541 switch ((inst >> 10) & 0b11) { 2542 case 0: 2543 op = rv_op_c_srli; 2544 break; 2545 case 1: 2546 op = rv_op_c_srai; 2547 break; 2548 case 2: op = rv_op_c_andi; break; 2549 case 3: 2550 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) { 2551 case 0: op = rv_op_c_sub; break; 2552 case 1: op = rv_op_c_xor; break; 2553 case 2: op = rv_op_c_or; break; 2554 case 3: op = rv_op_c_and; break; 2555 case 4: op = rv_op_c_subw; break; 2556 case 5: op = rv_op_c_addw; break; 2557 case 6: op = rv_op_c_mul; break; 2558 case 7: 2559 switch ((inst >> 2) & 0b111) { 2560 case 0: op = rv_op_c_zext_b; break; 2561 case 1: op = rv_op_c_sext_b; break; 2562 case 2: op = rv_op_c_zext_h; break; 2563 case 3: op = rv_op_c_sext_h; break; 2564 case 4: op = rv_op_c_zext_w; break; 2565 case 5: op = rv_op_c_not; break; 2566 } 2567 break; 2568 } 2569 break; 2570 } 2571 break; 2572 case 5: op = rv_op_c_j; break; 2573 case 6: op = rv_op_c_beqz; break; 2574 case 7: op = rv_op_c_bnez; break; 2575 } 2576 break; 2577 case 2: 2578 switch ((inst >> 13) & 0b111) { 2579 case 0: 2580 op = rv_op_c_slli; 2581 break; 2582 case 1: 2583 if (isa == rv128) { 2584 op = rv_op_c_lqsp; 2585 } else { 2586 op = rv_op_c_fldsp; 2587 } 2588 break; 2589 case 2: op = rv_op_c_lwsp; break; 2590 case 3: 2591 if (isa == rv32) { 2592 op = rv_op_c_flwsp; 2593 } else { 2594 op = rv_op_c_ldsp; 2595 } 2596 break; 2597 case 4: 2598 switch ((inst >> 12) & 0b1) { 2599 case 0: 2600 switch ((inst >> 2) & 0b11111) { 2601 case 0: op = rv_op_c_jr; break; 2602 default: op = rv_op_c_mv; break; 2603 } 2604 break; 2605 case 1: 2606 switch ((inst >> 2) & 0b11111) { 2607 case 0: 2608 switch ((inst >> 7) & 0b11111) { 2609 case 0: op = rv_op_c_ebreak; break; 2610 default: op = rv_op_c_jalr; break; 2611 } 2612 break; 2613 default: op = rv_op_c_add; break; 2614 } 2615 break; 2616 } 2617 break; 2618 case 5: 2619 if (isa == rv128) { 2620 op = rv_op_c_sqsp; 2621 } else { 2622 op = rv_op_c_fsdsp; 2623 if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { 2624 switch ((inst >> 8) & 0b01111) { 2625 case 8: 2626 if (((inst >> 4) & 0b01111) >= 4) { 2627 op = rv_op_cm_push; 2628 } 2629 break; 2630 case 10: 2631 if (((inst >> 4) & 0b01111) >= 4) { 2632 op = rv_op_cm_pop; 2633 } 2634 break; 2635 case 12: 2636 if (((inst >> 4) & 0b01111) >= 4) { 2637 op = rv_op_cm_popretz; 2638 } 2639 break; 2640 case 14: 2641 if (((inst >> 4) & 0b01111) >= 4) { 2642 op = rv_op_cm_popret; 2643 } 2644 break; 2645 } 2646 } else { 2647 switch ((inst >> 10) & 0b011) { 2648 case 0: 2649 if (!dec->cfg->ext_zcmt) { 2650 break; 2651 } 2652 if (((inst >> 2) & 0xFF) >= 32) { 2653 op = rv_op_cm_jalt; 2654 } else { 2655 op = rv_op_cm_jt; 2656 } 2657 break; 2658 case 3: 2659 if (!dec->cfg->ext_zcmp) { 2660 break; 2661 } 2662 switch ((inst >> 5) & 0b011) { 2663 case 1: op = rv_op_cm_mvsa01; break; 2664 case 3: op = rv_op_cm_mva01s; break; 2665 } 2666 break; 2667 } 2668 } 2669 } 2670 break; 2671 case 6: op = rv_op_c_swsp; break; 2672 case 7: 2673 if (isa == rv32) { 2674 op = rv_op_c_fswsp; 2675 } else { 2676 op = rv_op_c_sdsp; 2677 } 2678 break; 2679 } 2680 break; 2681 case 3: 2682 switch ((inst >> 2) & 0b11111) { 2683 case 0: 2684 switch ((inst >> 12) & 0b111) { 2685 case 0: op = rv_op_lb; break; 2686 case 1: op = rv_op_lh; break; 2687 case 2: op = rv_op_lw; break; 2688 case 3: op = rv_op_ld; break; 2689 case 4: op = rv_op_lbu; break; 2690 case 5: op = rv_op_lhu; break; 2691 case 6: op = rv_op_lwu; break; 2692 case 7: op = rv_op_ldu; break; 2693 } 2694 break; 2695 case 1: 2696 switch ((inst >> 12) & 0b111) { 2697 case 0: 2698 switch ((inst >> 20) & 0b111111111111) { 2699 case 40: op = rv_op_vl1re8_v; break; 2700 case 552: op = rv_op_vl2re8_v; break; 2701 case 1576: op = rv_op_vl4re8_v; break; 2702 case 3624: op = rv_op_vl8re8_v; break; 2703 } 2704 switch ((inst >> 26) & 0b111) { 2705 case 0: 2706 switch ((inst >> 20) & 0b11111) { 2707 case 0: op = rv_op_vle8_v; break; 2708 case 11: op = rv_op_vlm_v; break; 2709 case 16: op = rv_op_vle8ff_v; break; 2710 } 2711 break; 2712 case 1: op = rv_op_vluxei8_v; break; 2713 case 2: op = rv_op_vlse8_v; break; 2714 case 3: op = rv_op_vloxei8_v; break; 2715 } 2716 break; 2717 case 1: op = rv_op_flh; break; 2718 case 2: op = rv_op_flw; break; 2719 case 3: op = rv_op_fld; break; 2720 case 4: op = rv_op_flq; break; 2721 case 5: 2722 switch ((inst >> 20) & 0b111111111111) { 2723 case 40: op = rv_op_vl1re16_v; break; 2724 case 552: op = rv_op_vl2re16_v; break; 2725 case 1576: op = rv_op_vl4re16_v; break; 2726 case 3624: op = rv_op_vl8re16_v; break; 2727 } 2728 switch ((inst >> 26) & 0b111) { 2729 case 0: 2730 switch ((inst >> 20) & 0b11111) { 2731 case 0: op = rv_op_vle16_v; break; 2732 case 16: op = rv_op_vle16ff_v; break; 2733 } 2734 break; 2735 case 1: op = rv_op_vluxei16_v; break; 2736 case 2: op = rv_op_vlse16_v; break; 2737 case 3: op = rv_op_vloxei16_v; break; 2738 } 2739 break; 2740 case 6: 2741 switch ((inst >> 20) & 0b111111111111) { 2742 case 40: op = rv_op_vl1re32_v; break; 2743 case 552: op = rv_op_vl2re32_v; break; 2744 case 1576: op = rv_op_vl4re32_v; break; 2745 case 3624: op = rv_op_vl8re32_v; break; 2746 } 2747 switch ((inst >> 26) & 0b111) { 2748 case 0: 2749 switch ((inst >> 20) & 0b11111) { 2750 case 0: op = rv_op_vle32_v; break; 2751 case 16: op = rv_op_vle32ff_v; break; 2752 } 2753 break; 2754 case 1: op = rv_op_vluxei32_v; break; 2755 case 2: op = rv_op_vlse32_v; break; 2756 case 3: op = rv_op_vloxei32_v; break; 2757 } 2758 break; 2759 case 7: 2760 switch ((inst >> 20) & 0b111111111111) { 2761 case 40: op = rv_op_vl1re64_v; break; 2762 case 552: op = rv_op_vl2re64_v; break; 2763 case 1576: op = rv_op_vl4re64_v; break; 2764 case 3624: op = rv_op_vl8re64_v; break; 2765 } 2766 switch ((inst >> 26) & 0b111) { 2767 case 0: 2768 switch ((inst >> 20) & 0b11111) { 2769 case 0: op = rv_op_vle64_v; break; 2770 case 16: op = rv_op_vle64ff_v; break; 2771 } 2772 break; 2773 case 1: op = rv_op_vluxei64_v; break; 2774 case 2: op = rv_op_vlse64_v; break; 2775 case 3: op = rv_op_vloxei64_v; break; 2776 } 2777 break; 2778 } 2779 break; 2780 case 3: 2781 switch ((inst >> 12) & 0b111) { 2782 case 0: op = rv_op_fence; break; 2783 case 1: op = rv_op_fence_i; break; 2784 case 2: op = rv_op_lq; break; 2785 } 2786 break; 2787 case 4: 2788 switch ((inst >> 12) & 0b111) { 2789 case 0: op = rv_op_addi; break; 2790 case 1: 2791 switch ((inst >> 27) & 0b11111) { 2792 case 0b00000: op = rv_op_slli; break; 2793 case 0b00001: 2794 switch ((inst >> 20) & 0b1111111) { 2795 case 0b0001111: op = rv_op_zip; break; 2796 } 2797 break; 2798 case 0b00010: 2799 switch ((inst >> 20) & 0b1111111) { 2800 case 0b0000000: op = rv_op_sha256sum0; break; 2801 case 0b0000001: op = rv_op_sha256sum1; break; 2802 case 0b0000010: op = rv_op_sha256sig0; break; 2803 case 0b0000011: op = rv_op_sha256sig1; break; 2804 case 0b0000100: op = rv_op_sha512sum0; break; 2805 case 0b0000101: op = rv_op_sha512sum1; break; 2806 case 0b0000110: op = rv_op_sha512sig0; break; 2807 case 0b0000111: op = rv_op_sha512sig1; break; 2808 case 0b0001000: op = rv_op_sm3p0; break; 2809 case 0b0001001: op = rv_op_sm3p1; break; 2810 } 2811 break; 2812 case 0b00101: op = rv_op_bseti; break; 2813 case 0b00110: 2814 switch ((inst >> 20) & 0b1111111) { 2815 case 0b0000000: op = rv_op_aes64im; break; 2816 default: 2817 if (((inst >> 24) & 0b0111) == 0b001) { 2818 op = rv_op_aes64ks1i; 2819 } 2820 break; 2821 } 2822 break; 2823 case 0b01001: op = rv_op_bclri; break; 2824 case 0b01101: op = rv_op_binvi; break; 2825 case 0b01100: 2826 switch ((inst >> 20) & 0b1111111) { 2827 case 0b0000000: op = rv_op_clz; break; 2828 case 0b0000001: op = rv_op_ctz; break; 2829 case 0b0000010: op = rv_op_cpop; break; 2830 /* 0b0000011 */ 2831 case 0b0000100: op = rv_op_sext_b; break; 2832 case 0b0000101: op = rv_op_sext_h; break; 2833 } 2834 break; 2835 } 2836 break; 2837 case 2: op = rv_op_slti; break; 2838 case 3: op = rv_op_sltiu; break; 2839 case 4: op = rv_op_xori; break; 2840 case 5: 2841 switch ((inst >> 27) & 0b11111) { 2842 case 0b00000: op = rv_op_srli; break; 2843 case 0b00001: 2844 switch ((inst >> 20) & 0b1111111) { 2845 case 0b0001111: op = rv_op_unzip; break; 2846 } 2847 break; 2848 case 0b00101: op = rv_op_orc_b; break; 2849 case 0b01000: op = rv_op_srai; break; 2850 case 0b01001: op = rv_op_bexti; break; 2851 case 0b01100: op = rv_op_rori; break; 2852 case 0b01101: 2853 switch ((inst >> 20) & 0b1111111) { 2854 case 0b0011000: op = rv_op_rev8; break; 2855 case 0b0111000: op = rv_op_rev8; break; 2856 case 0b0000111: op = rv_op_brev8; break; 2857 } 2858 break; 2859 } 2860 break; 2861 case 6: op = rv_op_ori; break; 2862 case 7: op = rv_op_andi; break; 2863 } 2864 break; 2865 case 5: op = rv_op_auipc; break; 2866 case 6: 2867 switch ((inst >> 12) & 0b111) { 2868 case 0: op = rv_op_addiw; break; 2869 case 1: 2870 switch ((inst >> 26) & 0b111111) { 2871 case 0: op = rv_op_slliw; break; 2872 case 2: op = rv_op_slli_uw; break; 2873 case 24: 2874 switch ((inst >> 20) & 0b11111) { 2875 case 0b00000: op = rv_op_clzw; break; 2876 case 0b00001: op = rv_op_ctzw; break; 2877 case 0b00010: op = rv_op_cpopw; break; 2878 } 2879 break; 2880 } 2881 break; 2882 case 5: 2883 switch ((inst >> 25) & 0b1111111) { 2884 case 0: op = rv_op_srliw; break; 2885 case 32: op = rv_op_sraiw; break; 2886 case 48: op = rv_op_roriw; break; 2887 } 2888 break; 2889 } 2890 break; 2891 case 8: 2892 switch ((inst >> 12) & 0b111) { 2893 case 0: op = rv_op_sb; break; 2894 case 1: op = rv_op_sh; break; 2895 case 2: op = rv_op_sw; break; 2896 case 3: op = rv_op_sd; break; 2897 case 4: op = rv_op_sq; break; 2898 } 2899 break; 2900 case 9: 2901 switch ((inst >> 12) & 0b111) { 2902 case 0: 2903 switch ((inst >> 20) & 0b111111111111) { 2904 case 40: op = rv_op_vs1r_v; break; 2905 case 552: op = rv_op_vs2r_v; break; 2906 case 1576: op = rv_op_vs4r_v; break; 2907 case 3624: op = rv_op_vs8r_v; break; 2908 } 2909 switch ((inst >> 26) & 0b111) { 2910 case 0: 2911 switch ((inst >> 20) & 0b11111) { 2912 case 0: op = rv_op_vse8_v; break; 2913 case 11: op = rv_op_vsm_v; break; 2914 } 2915 break; 2916 case 1: op = rv_op_vsuxei8_v; break; 2917 case 2: op = rv_op_vsse8_v; break; 2918 case 3: op = rv_op_vsoxei8_v; break; 2919 } 2920 break; 2921 case 1: op = rv_op_fsh; break; 2922 case 2: op = rv_op_fsw; break; 2923 case 3: op = rv_op_fsd; break; 2924 case 4: op = rv_op_fsq; break; 2925 case 5: 2926 switch ((inst >> 26) & 0b111) { 2927 case 0: 2928 switch ((inst >> 20) & 0b11111) { 2929 case 0: op = rv_op_vse16_v; break; 2930 } 2931 break; 2932 case 1: op = rv_op_vsuxei16_v; break; 2933 case 2: op = rv_op_vsse16_v; break; 2934 case 3: op = rv_op_vsoxei16_v; break; 2935 } 2936 break; 2937 case 6: 2938 switch ((inst >> 26) & 0b111) { 2939 case 0: 2940 switch ((inst >> 20) & 0b11111) { 2941 case 0: op = rv_op_vse32_v; break; 2942 } 2943 break; 2944 case 1: op = rv_op_vsuxei32_v; break; 2945 case 2: op = rv_op_vsse32_v; break; 2946 case 3: op = rv_op_vsoxei32_v; break; 2947 } 2948 break; 2949 case 7: 2950 switch ((inst >> 26) & 0b111) { 2951 case 0: 2952 switch ((inst >> 20) & 0b11111) { 2953 case 0: op = rv_op_vse64_v; break; 2954 } 2955 break; 2956 case 1: op = rv_op_vsuxei64_v; break; 2957 case 2: op = rv_op_vsse64_v; break; 2958 case 3: op = rv_op_vsoxei64_v; break; 2959 } 2960 break; 2961 } 2962 break; 2963 case 11: 2964 switch (((inst >> 24) & 0b11111000) | 2965 ((inst >> 12) & 0b00000111)) { 2966 case 2: op = rv_op_amoadd_w; break; 2967 case 3: op = rv_op_amoadd_d; break; 2968 case 4: op = rv_op_amoadd_q; break; 2969 case 10: op = rv_op_amoswap_w; break; 2970 case 11: op = rv_op_amoswap_d; break; 2971 case 12: op = rv_op_amoswap_q; break; 2972 case 18: 2973 switch ((inst >> 20) & 0b11111) { 2974 case 0: op = rv_op_lr_w; break; 2975 } 2976 break; 2977 case 19: 2978 switch ((inst >> 20) & 0b11111) { 2979 case 0: op = rv_op_lr_d; break; 2980 } 2981 break; 2982 case 20: 2983 switch ((inst >> 20) & 0b11111) { 2984 case 0: op = rv_op_lr_q; break; 2985 } 2986 break; 2987 case 26: op = rv_op_sc_w; break; 2988 case 27: op = rv_op_sc_d; break; 2989 case 28: op = rv_op_sc_q; break; 2990 case 34: op = rv_op_amoxor_w; break; 2991 case 35: op = rv_op_amoxor_d; break; 2992 case 36: op = rv_op_amoxor_q; break; 2993 case 42: op = rv_op_amocas_w; break; 2994 case 43: op = rv_op_amocas_d; break; 2995 case 44: op = rv_op_amocas_q; break; 2996 case 66: op = rv_op_amoor_w; break; 2997 case 67: op = rv_op_amoor_d; break; 2998 case 68: op = rv_op_amoor_q; break; 2999 case 98: op = rv_op_amoand_w; break; 3000 case 99: op = rv_op_amoand_d; break; 3001 case 100: op = rv_op_amoand_q; break; 3002 case 130: op = rv_op_amomin_w; break; 3003 case 131: op = rv_op_amomin_d; break; 3004 case 132: op = rv_op_amomin_q; break; 3005 case 162: op = rv_op_amomax_w; break; 3006 case 163: op = rv_op_amomax_d; break; 3007 case 164: op = rv_op_amomax_q; break; 3008 case 194: op = rv_op_amominu_w; break; 3009 case 195: op = rv_op_amominu_d; break; 3010 case 196: op = rv_op_amominu_q; break; 3011 case 226: op = rv_op_amomaxu_w; break; 3012 case 227: op = rv_op_amomaxu_d; break; 3013 case 228: op = rv_op_amomaxu_q; break; 3014 } 3015 break; 3016 case 12: 3017 switch (((inst >> 22) & 0b1111111000) | 3018 ((inst >> 12) & 0b0000000111)) { 3019 case 0: op = rv_op_add; break; 3020 case 1: op = rv_op_sll; break; 3021 case 2: op = rv_op_slt; break; 3022 case 3: op = rv_op_sltu; break; 3023 case 4: op = rv_op_xor; break; 3024 case 5: op = rv_op_srl; break; 3025 case 6: op = rv_op_or; break; 3026 case 7: op = rv_op_and; break; 3027 case 8: op = rv_op_mul; break; 3028 case 9: op = rv_op_mulh; break; 3029 case 10: op = rv_op_mulhsu; break; 3030 case 11: op = rv_op_mulhu; break; 3031 case 12: op = rv_op_div; break; 3032 case 13: op = rv_op_divu; break; 3033 case 14: op = rv_op_rem; break; 3034 case 15: op = rv_op_remu; break; 3035 case 36: 3036 switch ((inst >> 20) & 0b11111) { 3037 case 0: op = rv_op_zext_h; break; 3038 default: op = rv_op_pack; break; 3039 } 3040 break; 3041 case 39: op = rv_op_packh; break; 3042 3043 case 41: op = rv_op_clmul; break; 3044 case 42: op = rv_op_clmulr; break; 3045 case 43: op = rv_op_clmulh; break; 3046 case 44: op = rv_op_min; break; 3047 case 45: op = rv_op_minu; break; 3048 case 46: op = rv_op_max; break; 3049 case 47: op = rv_op_maxu; break; 3050 case 075: op = rv_op_czero_eqz; break; 3051 case 077: op = rv_op_czero_nez; break; 3052 case 130: op = rv_op_sh1add; break; 3053 case 132: op = rv_op_sh2add; break; 3054 case 134: op = rv_op_sh3add; break; 3055 case 161: op = rv_op_bset; break; 3056 case 162: op = rv_op_xperm4; break; 3057 case 164: op = rv_op_xperm8; break; 3058 case 200: op = rv_op_aes64es; break; 3059 case 216: op = rv_op_aes64esm; break; 3060 case 232: op = rv_op_aes64ds; break; 3061 case 248: op = rv_op_aes64dsm; break; 3062 case 256: op = rv_op_sub; break; 3063 case 260: op = rv_op_xnor; break; 3064 case 261: op = rv_op_sra; break; 3065 case 262: op = rv_op_orn; break; 3066 case 263: op = rv_op_andn; break; 3067 case 289: op = rv_op_bclr; break; 3068 case 293: op = rv_op_bext; break; 3069 case 320: op = rv_op_sha512sum0r; break; 3070 case 328: op = rv_op_sha512sum1r; break; 3071 case 336: op = rv_op_sha512sig0l; break; 3072 case 344: op = rv_op_sha512sig1l; break; 3073 case 368: op = rv_op_sha512sig0h; break; 3074 case 376: op = rv_op_sha512sig1h; break; 3075 case 385: op = rv_op_rol; break; 3076 case 389: op = rv_op_ror; break; 3077 case 417: op = rv_op_binv; break; 3078 case 504: op = rv_op_aes64ks2; break; 3079 } 3080 switch ((inst >> 25) & 0b0011111) { 3081 case 17: op = rv_op_aes32esi; break; 3082 case 19: op = rv_op_aes32esmi; break; 3083 case 21: op = rv_op_aes32dsi; break; 3084 case 23: op = rv_op_aes32dsmi; break; 3085 case 24: op = rv_op_sm4ed; break; 3086 case 26: op = rv_op_sm4ks; break; 3087 } 3088 break; 3089 case 13: op = rv_op_lui; break; 3090 case 14: 3091 switch (((inst >> 22) & 0b1111111000) | 3092 ((inst >> 12) & 0b0000000111)) { 3093 case 0: op = rv_op_addw; break; 3094 case 1: op = rv_op_sllw; break; 3095 case 5: op = rv_op_srlw; break; 3096 case 8: op = rv_op_mulw; break; 3097 case 12: op = rv_op_divw; break; 3098 case 13: op = rv_op_divuw; break; 3099 case 14: op = rv_op_remw; break; 3100 case 15: op = rv_op_remuw; break; 3101 case 32: op = rv_op_add_uw; break; 3102 case 36: 3103 switch ((inst >> 20) & 0b11111) { 3104 case 0: op = rv_op_zext_h; break; 3105 default: op = rv_op_packw; break; 3106 } 3107 break; 3108 case 130: op = rv_op_sh1add_uw; break; 3109 case 132: op = rv_op_sh2add_uw; break; 3110 case 134: op = rv_op_sh3add_uw; break; 3111 case 256: op = rv_op_subw; break; 3112 case 261: op = rv_op_sraw; break; 3113 case 385: op = rv_op_rolw; break; 3114 case 389: op = rv_op_rorw; break; 3115 } 3116 break; 3117 case 16: 3118 switch ((inst >> 25) & 0b11) { 3119 case 0: op = rv_op_fmadd_s; break; 3120 case 1: op = rv_op_fmadd_d; break; 3121 case 3: op = rv_op_fmadd_q; break; 3122 } 3123 break; 3124 case 17: 3125 switch ((inst >> 25) & 0b11) { 3126 case 0: op = rv_op_fmsub_s; break; 3127 case 1: op = rv_op_fmsub_d; break; 3128 case 3: op = rv_op_fmsub_q; break; 3129 } 3130 break; 3131 case 18: 3132 switch ((inst >> 25) & 0b11) { 3133 case 0: op = rv_op_fnmsub_s; break; 3134 case 1: op = rv_op_fnmsub_d; break; 3135 case 3: op = rv_op_fnmsub_q; break; 3136 } 3137 break; 3138 case 19: 3139 switch ((inst >> 25) & 0b11) { 3140 case 0: op = rv_op_fnmadd_s; break; 3141 case 1: op = rv_op_fnmadd_d; break; 3142 case 3: op = rv_op_fnmadd_q; break; 3143 } 3144 break; 3145 case 20: 3146 switch ((inst >> 25) & 0b1111111) { 3147 case 0: op = rv_op_fadd_s; break; 3148 case 1: op = rv_op_fadd_d; break; 3149 case 3: op = rv_op_fadd_q; break; 3150 case 4: op = rv_op_fsub_s; break; 3151 case 5: op = rv_op_fsub_d; break; 3152 case 7: op = rv_op_fsub_q; break; 3153 case 8: op = rv_op_fmul_s; break; 3154 case 9: op = rv_op_fmul_d; break; 3155 case 11: op = rv_op_fmul_q; break; 3156 case 12: op = rv_op_fdiv_s; break; 3157 case 13: op = rv_op_fdiv_d; break; 3158 case 15: op = rv_op_fdiv_q; break; 3159 case 16: 3160 switch ((inst >> 12) & 0b111) { 3161 case 0: op = rv_op_fsgnj_s; break; 3162 case 1: op = rv_op_fsgnjn_s; break; 3163 case 2: op = rv_op_fsgnjx_s; break; 3164 } 3165 break; 3166 case 17: 3167 switch ((inst >> 12) & 0b111) { 3168 case 0: op = rv_op_fsgnj_d; break; 3169 case 1: op = rv_op_fsgnjn_d; break; 3170 case 2: op = rv_op_fsgnjx_d; break; 3171 } 3172 break; 3173 case 19: 3174 switch ((inst >> 12) & 0b111) { 3175 case 0: op = rv_op_fsgnj_q; break; 3176 case 1: op = rv_op_fsgnjn_q; break; 3177 case 2: op = rv_op_fsgnjx_q; break; 3178 } 3179 break; 3180 case 20: 3181 switch ((inst >> 12) & 0b111) { 3182 case 0: op = rv_op_fmin_s; break; 3183 case 1: op = rv_op_fmax_s; break; 3184 case 2: op = rv_op_fminm_s; break; 3185 case 3: op = rv_op_fmaxm_s; break; 3186 } 3187 break; 3188 case 21: 3189 switch ((inst >> 12) & 0b111) { 3190 case 0: op = rv_op_fmin_d; break; 3191 case 1: op = rv_op_fmax_d; break; 3192 case 2: op = rv_op_fminm_d; break; 3193 case 3: op = rv_op_fmaxm_d; break; 3194 } 3195 break; 3196 case 22: 3197 switch (((inst >> 12) & 0b111)) { 3198 case 2: op = rv_op_fminm_h; break; 3199 case 3: op = rv_op_fmaxm_h; break; 3200 } 3201 break; 3202 case 23: 3203 switch ((inst >> 12) & 0b111) { 3204 case 0: op = rv_op_fmin_q; break; 3205 case 1: op = rv_op_fmax_q; break; 3206 case 2: op = rv_op_fminm_q; break; 3207 case 3: op = rv_op_fmaxm_q; break; 3208 } 3209 break; 3210 case 32: 3211 switch ((inst >> 20) & 0b11111) { 3212 case 1: op = rv_op_fcvt_s_d; break; 3213 case 3: op = rv_op_fcvt_s_q; break; 3214 case 4: op = rv_op_fround_s; break; 3215 case 5: op = rv_op_froundnx_s; break; 3216 case 6: op = rv_op_fcvt_s_bf16; break; 3217 } 3218 break; 3219 case 33: 3220 switch ((inst >> 20) & 0b11111) { 3221 case 0: op = rv_op_fcvt_d_s; break; 3222 case 3: op = rv_op_fcvt_d_q; break; 3223 case 4: op = rv_op_fround_d; break; 3224 case 5: op = rv_op_froundnx_d; break; 3225 } 3226 break; 3227 case 34: 3228 switch (((inst >> 20) & 0b11111)) { 3229 case 4: op = rv_op_fround_h; break; 3230 case 5: op = rv_op_froundnx_h; break; 3231 case 8: op = rv_op_fcvt_bf16_s; break; 3232 } 3233 break; 3234 case 35: 3235 switch ((inst >> 20) & 0b11111) { 3236 case 0: op = rv_op_fcvt_q_s; break; 3237 case 1: op = rv_op_fcvt_q_d; break; 3238 case 4: op = rv_op_fround_q; break; 3239 case 5: op = rv_op_froundnx_q; break; 3240 } 3241 break; 3242 case 44: 3243 switch ((inst >> 20) & 0b11111) { 3244 case 0: op = rv_op_fsqrt_s; break; 3245 } 3246 break; 3247 case 45: 3248 switch ((inst >> 20) & 0b11111) { 3249 case 0: op = rv_op_fsqrt_d; break; 3250 } 3251 break; 3252 case 47: 3253 switch ((inst >> 20) & 0b11111) { 3254 case 0: op = rv_op_fsqrt_q; break; 3255 } 3256 break; 3257 case 80: 3258 switch ((inst >> 12) & 0b111) { 3259 case 0: op = rv_op_fle_s; break; 3260 case 1: op = rv_op_flt_s; break; 3261 case 2: op = rv_op_feq_s; break; 3262 case 4: op = rv_op_fleq_s; break; 3263 case 5: op = rv_op_fltq_s; break; 3264 } 3265 break; 3266 case 81: 3267 switch ((inst >> 12) & 0b111) { 3268 case 0: op = rv_op_fle_d; break; 3269 case 1: op = rv_op_flt_d; break; 3270 case 2: op = rv_op_feq_d; break; 3271 case 4: op = rv_op_fleq_d; break; 3272 case 5: op = rv_op_fltq_d; break; 3273 } 3274 break; 3275 case 82: 3276 switch (((inst >> 12) & 0b111)) { 3277 case 4: op = rv_op_fleq_h; break; 3278 case 5: op = rv_op_fltq_h; break; 3279 } 3280 break; 3281 case 83: 3282 switch ((inst >> 12) & 0b111) { 3283 case 0: op = rv_op_fle_q; break; 3284 case 1: op = rv_op_flt_q; break; 3285 case 2: op = rv_op_feq_q; break; 3286 case 4: op = rv_op_fleq_q; break; 3287 case 5: op = rv_op_fltq_q; break; 3288 } 3289 break; 3290 case 89: 3291 switch (((inst >> 12) & 0b111)) { 3292 case 0: op = rv_op_fmvp_d_x; break; 3293 } 3294 break; 3295 case 91: 3296 switch (((inst >> 12) & 0b111)) { 3297 case 0: op = rv_op_fmvp_q_x; break; 3298 } 3299 break; 3300 case 96: 3301 switch ((inst >> 20) & 0b11111) { 3302 case 0: op = rv_op_fcvt_w_s; break; 3303 case 1: op = rv_op_fcvt_wu_s; break; 3304 case 2: op = rv_op_fcvt_l_s; break; 3305 case 3: op = rv_op_fcvt_lu_s; break; 3306 } 3307 break; 3308 case 97: 3309 switch ((inst >> 20) & 0b11111) { 3310 case 0: op = rv_op_fcvt_w_d; break; 3311 case 1: op = rv_op_fcvt_wu_d; break; 3312 case 2: op = rv_op_fcvt_l_d; break; 3313 case 3: op = rv_op_fcvt_lu_d; break; 3314 case 8: op = rv_op_fcvtmod_w_d; break; 3315 } 3316 break; 3317 case 99: 3318 switch ((inst >> 20) & 0b11111) { 3319 case 0: op = rv_op_fcvt_w_q; break; 3320 case 1: op = rv_op_fcvt_wu_q; break; 3321 case 2: op = rv_op_fcvt_l_q; break; 3322 case 3: op = rv_op_fcvt_lu_q; break; 3323 } 3324 break; 3325 case 104: 3326 switch ((inst >> 20) & 0b11111) { 3327 case 0: op = rv_op_fcvt_s_w; break; 3328 case 1: op = rv_op_fcvt_s_wu; break; 3329 case 2: op = rv_op_fcvt_s_l; break; 3330 case 3: op = rv_op_fcvt_s_lu; break; 3331 } 3332 break; 3333 case 105: 3334 switch ((inst >> 20) & 0b11111) { 3335 case 0: op = rv_op_fcvt_d_w; break; 3336 case 1: op = rv_op_fcvt_d_wu; break; 3337 case 2: op = rv_op_fcvt_d_l; break; 3338 case 3: op = rv_op_fcvt_d_lu; break; 3339 } 3340 break; 3341 case 107: 3342 switch ((inst >> 20) & 0b11111) { 3343 case 0: op = rv_op_fcvt_q_w; break; 3344 case 1: op = rv_op_fcvt_q_wu; break; 3345 case 2: op = rv_op_fcvt_q_l; break; 3346 case 3: op = rv_op_fcvt_q_lu; break; 3347 } 3348 break; 3349 case 112: 3350 switch (((inst >> 17) & 0b11111000) | 3351 ((inst >> 12) & 0b00000111)) { 3352 case 0: op = rv_op_fmv_x_s; break; 3353 case 1: op = rv_op_fclass_s; break; 3354 } 3355 break; 3356 case 113: 3357 switch (((inst >> 17) & 0b11111000) | 3358 ((inst >> 12) & 0b00000111)) { 3359 case 0: op = rv_op_fmv_x_d; break; 3360 case 1: op = rv_op_fclass_d; break; 3361 case 8: op = rv_op_fmvh_x_d; break; 3362 } 3363 break; 3364 case 114: 3365 switch (((inst >> 17) & 0b11111000) | 3366 ((inst >> 12) & 0b00000111)) { 3367 case 0: op = rv_op_fmv_x_h; break; 3368 } 3369 break; 3370 case 115: 3371 switch (((inst >> 17) & 0b11111000) | 3372 ((inst >> 12) & 0b00000111)) { 3373 case 0: op = rv_op_fmv_x_q; break; 3374 case 1: op = rv_op_fclass_q; break; 3375 case 8: op = rv_op_fmvh_x_q; break; 3376 } 3377 break; 3378 case 120: 3379 switch (((inst >> 17) & 0b11111000) | 3380 ((inst >> 12) & 0b00000111)) { 3381 case 0: op = rv_op_fmv_s_x; break; 3382 case 8: op = rv_op_fli_s; break; 3383 } 3384 break; 3385 case 121: 3386 switch (((inst >> 17) & 0b11111000) | 3387 ((inst >> 12) & 0b00000111)) { 3388 case 0: op = rv_op_fmv_d_x; break; 3389 case 8: op = rv_op_fli_d; break; 3390 } 3391 break; 3392 case 122: 3393 switch (((inst >> 17) & 0b11111000) | 3394 ((inst >> 12) & 0b00000111)) { 3395 case 0: op = rv_op_fmv_h_x; break; 3396 case 8: op = rv_op_fli_h; break; 3397 } 3398 break; 3399 case 123: 3400 switch (((inst >> 17) & 0b11111000) | 3401 ((inst >> 12) & 0b00000111)) { 3402 case 0: op = rv_op_fmv_q_x; break; 3403 case 8: op = rv_op_fli_q; break; 3404 } 3405 break; 3406 } 3407 break; 3408 case 21: 3409 switch ((inst >> 12) & 0b111) { 3410 case 0: 3411 switch ((inst >> 26) & 0b111111) { 3412 case 0: op = rv_op_vadd_vv; break; 3413 case 1: op = rv_op_vandn_vv; break; 3414 case 2: op = rv_op_vsub_vv; break; 3415 case 4: op = rv_op_vminu_vv; break; 3416 case 5: op = rv_op_vmin_vv; break; 3417 case 6: op = rv_op_vmaxu_vv; break; 3418 case 7: op = rv_op_vmax_vv; break; 3419 case 9: op = rv_op_vand_vv; break; 3420 case 10: op = rv_op_vor_vv; break; 3421 case 11: op = rv_op_vxor_vv; break; 3422 case 12: op = rv_op_vrgather_vv; break; 3423 case 14: op = rv_op_vrgatherei16_vv; break; 3424 case 16: 3425 if (((inst >> 25) & 1) == 0) { 3426 op = rv_op_vadc_vvm; 3427 } 3428 break; 3429 case 17: op = rv_op_vmadc_vvm; break; 3430 case 18: 3431 if (((inst >> 25) & 1) == 0) { 3432 op = rv_op_vsbc_vvm; 3433 } 3434 break; 3435 case 19: op = rv_op_vmsbc_vvm; break; 3436 case 20: op = rv_op_vror_vv; break; 3437 case 21: op = rv_op_vrol_vv; break; 3438 case 23: 3439 if (((inst >> 20) & 0b111111) == 32) 3440 op = rv_op_vmv_v_v; 3441 else if (((inst >> 25) & 1) == 0) 3442 op = rv_op_vmerge_vvm; 3443 break; 3444 case 24: op = rv_op_vmseq_vv; break; 3445 case 25: op = rv_op_vmsne_vv; break; 3446 case 26: op = rv_op_vmsltu_vv; break; 3447 case 27: op = rv_op_vmslt_vv; break; 3448 case 28: op = rv_op_vmsleu_vv; break; 3449 case 29: op = rv_op_vmsle_vv; break; 3450 case 32: op = rv_op_vsaddu_vv; break; 3451 case 33: op = rv_op_vsadd_vv; break; 3452 case 34: op = rv_op_vssubu_vv; break; 3453 case 35: op = rv_op_vssub_vv; break; 3454 case 37: op = rv_op_vsll_vv; break; 3455 case 39: op = rv_op_vsmul_vv; break; 3456 case 40: op = rv_op_vsrl_vv; break; 3457 case 41: op = rv_op_vsra_vv; break; 3458 case 42: op = rv_op_vssrl_vv; break; 3459 case 43: op = rv_op_vssra_vv; break; 3460 case 44: op = rv_op_vnsrl_wv; break; 3461 case 45: op = rv_op_vnsra_wv; break; 3462 case 46: op = rv_op_vnclipu_wv; break; 3463 case 47: op = rv_op_vnclip_wv; break; 3464 case 48: op = rv_op_vwredsumu_vs; break; 3465 case 49: op = rv_op_vwredsum_vs; break; 3466 case 53: op = rv_op_vwsll_vv; break; 3467 } 3468 break; 3469 case 1: 3470 switch ((inst >> 26) & 0b111111) { 3471 case 0: op = rv_op_vfadd_vv; break; 3472 case 1: op = rv_op_vfredusum_vs; break; 3473 case 2: op = rv_op_vfsub_vv; break; 3474 case 3: op = rv_op_vfredosum_vs; break; 3475 case 4: op = rv_op_vfmin_vv; break; 3476 case 5: op = rv_op_vfredmin_vs; break; 3477 case 6: op = rv_op_vfmax_vv; break; 3478 case 7: op = rv_op_vfredmax_vs; break; 3479 case 8: op = rv_op_vfsgnj_vv; break; 3480 case 9: op = rv_op_vfsgnjn_vv; break; 3481 case 10: op = rv_op_vfsgnjx_vv; break; 3482 case 16: 3483 switch ((inst >> 15) & 0b11111) { 3484 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break; 3485 } 3486 break; 3487 case 18: 3488 switch ((inst >> 15) & 0b11111) { 3489 case 0: op = rv_op_vfcvt_xu_f_v; break; 3490 case 1: op = rv_op_vfcvt_x_f_v; break; 3491 case 2: op = rv_op_vfcvt_f_xu_v; break; 3492 case 3: op = rv_op_vfcvt_f_x_v; break; 3493 case 6: op = rv_op_vfcvt_rtz_xu_f_v; break; 3494 case 7: op = rv_op_vfcvt_rtz_x_f_v; break; 3495 case 8: op = rv_op_vfwcvt_xu_f_v; break; 3496 case 9: op = rv_op_vfwcvt_x_f_v; break; 3497 case 10: op = rv_op_vfwcvt_f_xu_v; break; 3498 case 11: op = rv_op_vfwcvt_f_x_v; break; 3499 case 12: op = rv_op_vfwcvt_f_f_v; break; 3500 case 13: op = rv_op_vfwcvtbf16_f_f_v; break; 3501 case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break; 3502 case 15: op = rv_op_vfwcvt_rtz_x_f_v; break; 3503 case 16: op = rv_op_vfncvt_xu_f_w; break; 3504 case 17: op = rv_op_vfncvt_x_f_w; break; 3505 case 18: op = rv_op_vfncvt_f_xu_w; break; 3506 case 19: op = rv_op_vfncvt_f_x_w; break; 3507 case 20: op = rv_op_vfncvt_f_f_w; break; 3508 case 21: op = rv_op_vfncvt_rod_f_f_w; break; 3509 case 22: op = rv_op_vfncvt_rtz_xu_f_w; break; 3510 case 23: op = rv_op_vfncvt_rtz_x_f_w; break; 3511 case 29: op = rv_op_vfncvtbf16_f_f_w; break; 3512 } 3513 break; 3514 case 19: 3515 switch ((inst >> 15) & 0b11111) { 3516 case 0: op = rv_op_vfsqrt_v; break; 3517 case 4: op = rv_op_vfrsqrt7_v; break; 3518 case 5: op = rv_op_vfrec7_v; break; 3519 case 16: op = rv_op_vfclass_v; break; 3520 } 3521 break; 3522 case 24: op = rv_op_vmfeq_vv; break; 3523 case 25: op = rv_op_vmfle_vv; break; 3524 case 27: op = rv_op_vmflt_vv; break; 3525 case 28: op = rv_op_vmfne_vv; break; 3526 case 32: op = rv_op_vfdiv_vv; break; 3527 case 36: op = rv_op_vfmul_vv; break; 3528 case 40: op = rv_op_vfmadd_vv; break; 3529 case 41: op = rv_op_vfnmadd_vv; break; 3530 case 42: op = rv_op_vfmsub_vv; break; 3531 case 43: op = rv_op_vfnmsub_vv; break; 3532 case 44: op = rv_op_vfmacc_vv; break; 3533 case 45: op = rv_op_vfnmacc_vv; break; 3534 case 46: op = rv_op_vfmsac_vv; break; 3535 case 47: op = rv_op_vfnmsac_vv; break; 3536 case 48: op = rv_op_vfwadd_vv; break; 3537 case 49: op = rv_op_vfwredusum_vs; break; 3538 case 50: op = rv_op_vfwsub_vv; break; 3539 case 51: op = rv_op_vfwredosum_vs; break; 3540 case 52: op = rv_op_vfwadd_wv; break; 3541 case 54: op = rv_op_vfwsub_wv; break; 3542 case 56: op = rv_op_vfwmul_vv; break; 3543 case 59: op = rv_op_vfwmaccbf16_vv; break; 3544 case 60: op = rv_op_vfwmacc_vv; break; 3545 case 61: op = rv_op_vfwnmacc_vv; break; 3546 case 62: op = rv_op_vfwmsac_vv; break; 3547 case 63: op = rv_op_vfwnmsac_vv; break; 3548 } 3549 break; 3550 case 2: 3551 switch ((inst >> 26) & 0b111111) { 3552 case 0: op = rv_op_vredsum_vs; break; 3553 case 1: op = rv_op_vredand_vs; break; 3554 case 2: op = rv_op_vredor_vs; break; 3555 case 3: op = rv_op_vredxor_vs; break; 3556 case 4: op = rv_op_vredminu_vs; break; 3557 case 5: op = rv_op_vredmin_vs; break; 3558 case 6: op = rv_op_vredmaxu_vs; break; 3559 case 7: op = rv_op_vredmax_vs; break; 3560 case 8: op = rv_op_vaaddu_vv; break; 3561 case 9: op = rv_op_vaadd_vv; break; 3562 case 10: op = rv_op_vasubu_vv; break; 3563 case 11: op = rv_op_vasub_vv; break; 3564 case 12: op = rv_op_vclmul_vv; break; 3565 case 13: op = rv_op_vclmulh_vv; break; 3566 case 16: 3567 switch ((inst >> 15) & 0b11111) { 3568 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break; 3569 case 16: op = rv_op_vcpop_m; break; 3570 case 17: op = rv_op_vfirst_m; break; 3571 } 3572 break; 3573 case 18: 3574 switch ((inst >> 15) & 0b11111) { 3575 case 2: op = rv_op_vzext_vf8; break; 3576 case 3: op = rv_op_vsext_vf8; break; 3577 case 4: op = rv_op_vzext_vf4; break; 3578 case 5: op = rv_op_vsext_vf4; break; 3579 case 6: op = rv_op_vzext_vf2; break; 3580 case 7: op = rv_op_vsext_vf2; break; 3581 case 8: op = rv_op_vbrev8_v; break; 3582 case 9: op = rv_op_vrev8_v; break; 3583 case 10: op = rv_op_vbrev_v; break; 3584 case 12: op = rv_op_vclz_v; break; 3585 case 13: op = rv_op_vctz_v; break; 3586 case 14: op = rv_op_vcpop_v; break; 3587 } 3588 break; 3589 case 20: 3590 switch ((inst >> 15) & 0b11111) { 3591 case 1: op = rv_op_vmsbf_m; break; 3592 case 2: op = rv_op_vmsof_m; break; 3593 case 3: op = rv_op_vmsif_m; break; 3594 case 16: op = rv_op_viota_m; break; 3595 case 17: 3596 if (((inst >> 20) & 0b11111) == 0) { 3597 op = rv_op_vid_v; 3598 } 3599 break; 3600 } 3601 break; 3602 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break; 3603 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break; 3604 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break; 3605 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break; 3606 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break; 3607 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break; 3608 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break; 3609 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break; 3610 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break; 3611 case 32: op = rv_op_vdivu_vv; break; 3612 case 33: op = rv_op_vdiv_vv; break; 3613 case 34: op = rv_op_vremu_vv; break; 3614 case 35: op = rv_op_vrem_vv; break; 3615 case 36: op = rv_op_vmulhu_vv; break; 3616 case 37: op = rv_op_vmul_vv; break; 3617 case 38: op = rv_op_vmulhsu_vv; break; 3618 case 39: op = rv_op_vmulh_vv; break; 3619 case 41: op = rv_op_vmadd_vv; break; 3620 case 43: op = rv_op_vnmsub_vv; break; 3621 case 45: op = rv_op_vmacc_vv; break; 3622 case 47: op = rv_op_vnmsac_vv; break; 3623 case 48: op = rv_op_vwaddu_vv; break; 3624 case 49: op = rv_op_vwadd_vv; break; 3625 case 50: op = rv_op_vwsubu_vv; break; 3626 case 51: op = rv_op_vwsub_vv; break; 3627 case 52: op = rv_op_vwaddu_wv; break; 3628 case 53: op = rv_op_vwadd_wv; break; 3629 case 54: op = rv_op_vwsubu_wv; break; 3630 case 55: op = rv_op_vwsub_wv; break; 3631 case 56: op = rv_op_vwmulu_vv; break; 3632 case 58: op = rv_op_vwmulsu_vv; break; 3633 case 59: op = rv_op_vwmul_vv; break; 3634 case 60: op = rv_op_vwmaccu_vv; break; 3635 case 61: op = rv_op_vwmacc_vv; break; 3636 case 63: op = rv_op_vwmaccsu_vv; break; 3637 } 3638 break; 3639 case 3: 3640 switch ((inst >> 26) & 0b111111) { 3641 case 0: op = rv_op_vadd_vi; break; 3642 case 3: op = rv_op_vrsub_vi; break; 3643 case 9: op = rv_op_vand_vi; break; 3644 case 10: op = rv_op_vor_vi; break; 3645 case 11: op = rv_op_vxor_vi; break; 3646 case 12: op = rv_op_vrgather_vi; break; 3647 case 14: op = rv_op_vslideup_vi; break; 3648 case 15: op = rv_op_vslidedown_vi; break; 3649 case 16: 3650 if (((inst >> 25) & 1) == 0) { 3651 op = rv_op_vadc_vim; 3652 } 3653 break; 3654 case 17: op = rv_op_vmadc_vim; break; 3655 case 20: case 21: op = rv_op_vror_vi; break; 3656 case 23: 3657 if (((inst >> 20) & 0b111111) == 32) 3658 op = rv_op_vmv_v_i; 3659 else if (((inst >> 25) & 1) == 0) 3660 op = rv_op_vmerge_vim; 3661 break; 3662 case 24: op = rv_op_vmseq_vi; break; 3663 case 25: op = rv_op_vmsne_vi; break; 3664 case 28: op = rv_op_vmsleu_vi; break; 3665 case 29: op = rv_op_vmsle_vi; break; 3666 case 30: op = rv_op_vmsgtu_vi; break; 3667 case 31: op = rv_op_vmsgt_vi; break; 3668 case 32: op = rv_op_vsaddu_vi; break; 3669 case 33: op = rv_op_vsadd_vi; break; 3670 case 37: op = rv_op_vsll_vi; break; 3671 case 39: 3672 switch ((inst >> 15) & 0b11111) { 3673 case 0: op = rv_op_vmv1r_v; break; 3674 case 1: op = rv_op_vmv2r_v; break; 3675 case 3: op = rv_op_vmv4r_v; break; 3676 case 7: op = rv_op_vmv8r_v; break; 3677 } 3678 break; 3679 case 40: op = rv_op_vsrl_vi; break; 3680 case 41: op = rv_op_vsra_vi; break; 3681 case 42: op = rv_op_vssrl_vi; break; 3682 case 43: op = rv_op_vssra_vi; break; 3683 case 44: op = rv_op_vnsrl_wi; break; 3684 case 45: op = rv_op_vnsra_wi; break; 3685 case 46: op = rv_op_vnclipu_wi; break; 3686 case 47: op = rv_op_vnclip_wi; break; 3687 case 53: op = rv_op_vwsll_vi; break; 3688 } 3689 break; 3690 case 4: 3691 switch ((inst >> 26) & 0b111111) { 3692 case 0: op = rv_op_vadd_vx; break; 3693 case 1: op = rv_op_vandn_vx; break; 3694 case 2: op = rv_op_vsub_vx; break; 3695 case 3: op = rv_op_vrsub_vx; break; 3696 case 4: op = rv_op_vminu_vx; break; 3697 case 5: op = rv_op_vmin_vx; break; 3698 case 6: op = rv_op_vmaxu_vx; break; 3699 case 7: op = rv_op_vmax_vx; break; 3700 case 9: op = rv_op_vand_vx; break; 3701 case 10: op = rv_op_vor_vx; break; 3702 case 11: op = rv_op_vxor_vx; break; 3703 case 12: op = rv_op_vrgather_vx; break; 3704 case 14: op = rv_op_vslideup_vx; break; 3705 case 15: op = rv_op_vslidedown_vx; break; 3706 case 16: 3707 if (((inst >> 25) & 1) == 0) { 3708 op = rv_op_vadc_vxm; 3709 } 3710 break; 3711 case 17: op = rv_op_vmadc_vxm; break; 3712 case 18: 3713 if (((inst >> 25) & 1) == 0) { 3714 op = rv_op_vsbc_vxm; 3715 } 3716 break; 3717 case 19: op = rv_op_vmsbc_vxm; break; 3718 case 20: op = rv_op_vror_vx; break; 3719 case 21: op = rv_op_vrol_vx; break; 3720 case 23: 3721 if (((inst >> 20) & 0b111111) == 32) 3722 op = rv_op_vmv_v_x; 3723 else if (((inst >> 25) & 1) == 0) 3724 op = rv_op_vmerge_vxm; 3725 break; 3726 case 24: op = rv_op_vmseq_vx; break; 3727 case 25: op = rv_op_vmsne_vx; break; 3728 case 26: op = rv_op_vmsltu_vx; break; 3729 case 27: op = rv_op_vmslt_vx; break; 3730 case 28: op = rv_op_vmsleu_vx; break; 3731 case 29: op = rv_op_vmsle_vx; break; 3732 case 30: op = rv_op_vmsgtu_vx; break; 3733 case 31: op = rv_op_vmsgt_vx; break; 3734 case 32: op = rv_op_vsaddu_vx; break; 3735 case 33: op = rv_op_vsadd_vx; break; 3736 case 34: op = rv_op_vssubu_vx; break; 3737 case 35: op = rv_op_vssub_vx; break; 3738 case 37: op = rv_op_vsll_vx; break; 3739 case 39: op = rv_op_vsmul_vx; break; 3740 case 40: op = rv_op_vsrl_vx; break; 3741 case 41: op = rv_op_vsra_vx; break; 3742 case 42: op = rv_op_vssrl_vx; break; 3743 case 43: op = rv_op_vssra_vx; break; 3744 case 44: op = rv_op_vnsrl_wx; break; 3745 case 45: op = rv_op_vnsra_wx; break; 3746 case 46: op = rv_op_vnclipu_wx; break; 3747 case 47: op = rv_op_vnclip_wx; break; 3748 case 53: op = rv_op_vwsll_vx; break; 3749 } 3750 break; 3751 case 5: 3752 switch ((inst >> 26) & 0b111111) { 3753 case 0: op = rv_op_vfadd_vf; break; 3754 case 2: op = rv_op_vfsub_vf; break; 3755 case 4: op = rv_op_vfmin_vf; break; 3756 case 6: op = rv_op_vfmax_vf; break; 3757 case 8: op = rv_op_vfsgnj_vf; break; 3758 case 9: op = rv_op_vfsgnjn_vf; break; 3759 case 10: op = rv_op_vfsgnjx_vf; break; 3760 case 14: op = rv_op_vfslide1up_vf; break; 3761 case 15: op = rv_op_vfslide1down_vf; break; 3762 case 16: 3763 switch ((inst >> 20) & 0b11111) { 3764 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break; 3765 } 3766 break; 3767 case 23: 3768 if (((inst >> 25) & 1) == 0) 3769 op = rv_op_vfmerge_vfm; 3770 else if (((inst >> 20) & 0b111111) == 32) 3771 op = rv_op_vfmv_v_f; 3772 break; 3773 case 24: op = rv_op_vmfeq_vf; break; 3774 case 25: op = rv_op_vmfle_vf; break; 3775 case 27: op = rv_op_vmflt_vf; break; 3776 case 28: op = rv_op_vmfne_vf; break; 3777 case 29: op = rv_op_vmfgt_vf; break; 3778 case 31: op = rv_op_vmfge_vf; break; 3779 case 32: op = rv_op_vfdiv_vf; break; 3780 case 33: op = rv_op_vfrdiv_vf; break; 3781 case 36: op = rv_op_vfmul_vf; break; 3782 case 39: op = rv_op_vfrsub_vf; break; 3783 case 40: op = rv_op_vfmadd_vf; break; 3784 case 41: op = rv_op_vfnmadd_vf; break; 3785 case 42: op = rv_op_vfmsub_vf; break; 3786 case 43: op = rv_op_vfnmsub_vf; break; 3787 case 44: op = rv_op_vfmacc_vf; break; 3788 case 45: op = rv_op_vfnmacc_vf; break; 3789 case 46: op = rv_op_vfmsac_vf; break; 3790 case 47: op = rv_op_vfnmsac_vf; break; 3791 case 48: op = rv_op_vfwadd_vf; break; 3792 case 50: op = rv_op_vfwsub_vf; break; 3793 case 52: op = rv_op_vfwadd_wf; break; 3794 case 54: op = rv_op_vfwsub_wf; break; 3795 case 56: op = rv_op_vfwmul_vf; break; 3796 case 59: op = rv_op_vfwmaccbf16_vf; break; 3797 case 60: op = rv_op_vfwmacc_vf; break; 3798 case 61: op = rv_op_vfwnmacc_vf; break; 3799 case 62: op = rv_op_vfwmsac_vf; break; 3800 case 63: op = rv_op_vfwnmsac_vf; break; 3801 } 3802 break; 3803 case 6: 3804 switch ((inst >> 26) & 0b111111) { 3805 case 8: op = rv_op_vaaddu_vx; break; 3806 case 9: op = rv_op_vaadd_vx; break; 3807 case 10: op = rv_op_vasubu_vx; break; 3808 case 11: op = rv_op_vasub_vx; break; 3809 case 12: op = rv_op_vclmul_vx; break; 3810 case 13: op = rv_op_vclmulh_vx; break; 3811 case 14: op = rv_op_vslide1up_vx; break; 3812 case 15: op = rv_op_vslide1down_vx; break; 3813 case 16: 3814 switch ((inst >> 20) & 0b11111) { 3815 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break; 3816 } 3817 break; 3818 case 32: op = rv_op_vdivu_vx; break; 3819 case 33: op = rv_op_vdiv_vx; break; 3820 case 34: op = rv_op_vremu_vx; break; 3821 case 35: op = rv_op_vrem_vx; break; 3822 case 36: op = rv_op_vmulhu_vx; break; 3823 case 37: op = rv_op_vmul_vx; break; 3824 case 38: op = rv_op_vmulhsu_vx; break; 3825 case 39: op = rv_op_vmulh_vx; break; 3826 case 41: op = rv_op_vmadd_vx; break; 3827 case 43: op = rv_op_vnmsub_vx; break; 3828 case 45: op = rv_op_vmacc_vx; break; 3829 case 47: op = rv_op_vnmsac_vx; break; 3830 case 48: op = rv_op_vwaddu_vx; break; 3831 case 49: op = rv_op_vwadd_vx; break; 3832 case 50: op = rv_op_vwsubu_vx; break; 3833 case 51: op = rv_op_vwsub_vx; break; 3834 case 52: op = rv_op_vwaddu_wx; break; 3835 case 53: op = rv_op_vwadd_wx; break; 3836 case 54: op = rv_op_vwsubu_wx; break; 3837 case 55: op = rv_op_vwsub_wx; break; 3838 case 56: op = rv_op_vwmulu_vx; break; 3839 case 58: op = rv_op_vwmulsu_vx; break; 3840 case 59: op = rv_op_vwmul_vx; break; 3841 case 60: op = rv_op_vwmaccu_vx; break; 3842 case 61: op = rv_op_vwmacc_vx; break; 3843 case 62: op = rv_op_vwmaccus_vx; break; 3844 case 63: op = rv_op_vwmaccsu_vx; break; 3845 } 3846 break; 3847 case 7: 3848 if (((inst >> 31) & 1) == 0) { 3849 op = rv_op_vsetvli; 3850 } else if ((inst >> 30) & 1) { 3851 op = rv_op_vsetivli; 3852 } else if (((inst >> 25) & 0b11111) == 0) { 3853 op = rv_op_vsetvl; 3854 } 3855 break; 3856 } 3857 break; 3858 case 22: 3859 switch ((inst >> 12) & 0b111) { 3860 case 0: op = rv_op_addid; break; 3861 case 1: 3862 switch ((inst >> 26) & 0b111111) { 3863 case 0: op = rv_op_sllid; break; 3864 } 3865 break; 3866 case 5: 3867 switch ((inst >> 26) & 0b111111) { 3868 case 0: op = rv_op_srlid; break; 3869 case 16: op = rv_op_sraid; break; 3870 } 3871 break; 3872 } 3873 break; 3874 case 24: 3875 switch ((inst >> 12) & 0b111) { 3876 case 0: op = rv_op_beq; break; 3877 case 1: op = rv_op_bne; break; 3878 case 4: op = rv_op_blt; break; 3879 case 5: op = rv_op_bge; break; 3880 case 6: op = rv_op_bltu; break; 3881 case 7: op = rv_op_bgeu; break; 3882 } 3883 break; 3884 case 25: 3885 switch ((inst >> 12) & 0b111) { 3886 case 0: op = rv_op_jalr; break; 3887 } 3888 break; 3889 case 27: op = rv_op_jal; break; 3890 case 28: 3891 switch ((inst >> 12) & 0b111) { 3892 case 0: 3893 switch (((inst >> 20) & 0b111111100000) | 3894 ((inst >> 7) & 0b000000011111)) { 3895 case 0: 3896 switch ((inst >> 15) & 0b1111111111) { 3897 case 0: op = rv_op_ecall; break; 3898 case 32: op = rv_op_ebreak; break; 3899 case 64: op = rv_op_uret; break; 3900 } 3901 break; 3902 case 256: 3903 switch ((inst >> 20) & 0b11111) { 3904 case 2: 3905 switch ((inst >> 15) & 0b11111) { 3906 case 0: op = rv_op_sret; break; 3907 } 3908 break; 3909 case 4: op = rv_op_sfence_vm; break; 3910 case 5: 3911 switch ((inst >> 15) & 0b11111) { 3912 case 0: op = rv_op_wfi; break; 3913 } 3914 break; 3915 } 3916 break; 3917 case 288: op = rv_op_sfence_vma; break; 3918 case 512: 3919 switch ((inst >> 15) & 0b1111111111) { 3920 case 64: op = rv_op_hret; break; 3921 } 3922 break; 3923 case 768: 3924 switch ((inst >> 15) & 0b1111111111) { 3925 case 64: op = rv_op_mret; break; 3926 } 3927 break; 3928 case 1952: 3929 switch ((inst >> 15) & 0b1111111111) { 3930 case 576: op = rv_op_dret; break; 3931 } 3932 break; 3933 } 3934 break; 3935 case 1: op = rv_op_csrrw; break; 3936 case 2: op = rv_op_csrrs; break; 3937 case 3: op = rv_op_csrrc; break; 3938 case 4: 3939 if (dec->cfg->ext_zimop) { 3940 int imm_mop5, imm_mop3; 3941 if ((extract32(inst, 22, 10) & 0b1011001111) 3942 == 0b1000000111) { 3943 imm_mop5 = deposit32(deposit32(extract32(inst, 20, 2), 3944 2, 2, 3945 extract32(inst, 26, 2)), 3946 4, 1, extract32(inst, 30, 1)); 3947 op = rv_mop_r_0 + imm_mop5; 3948 } else if ((extract32(inst, 25, 7) & 0b1011001) 3949 == 0b1000001) { 3950 imm_mop3 = deposit32(extract32(inst, 26, 2), 3951 2, 1, extract32(inst, 30, 1)); 3952 op = rv_mop_rr_0 + imm_mop3; 3953 } 3954 } 3955 break; 3956 case 5: op = rv_op_csrrwi; break; 3957 case 6: op = rv_op_csrrsi; break; 3958 case 7: op = rv_op_csrrci; break; 3959 } 3960 break; 3961 case 29: 3962 if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) { 3963 switch ((inst >> 26) & 0b111111) { 3964 case 32: op = rv_op_vsm3me_vv; break; 3965 case 33: op = rv_op_vsm4k_vi; break; 3966 case 34: op = rv_op_vaeskf1_vi; break; 3967 case 40: 3968 switch ((inst >> 15) & 0b11111) { 3969 case 0: op = rv_op_vaesdm_vv; break; 3970 case 1: op = rv_op_vaesdf_vv; break; 3971 case 2: op = rv_op_vaesem_vv; break; 3972 case 3: op = rv_op_vaesef_vv; break; 3973 case 16: op = rv_op_vsm4r_vv; break; 3974 case 17: op = rv_op_vgmul_vv; break; 3975 } 3976 break; 3977 case 41: 3978 switch ((inst >> 15) & 0b11111) { 3979 case 0: op = rv_op_vaesdm_vs; break; 3980 case 1: op = rv_op_vaesdf_vs; break; 3981 case 2: op = rv_op_vaesem_vs; break; 3982 case 3: op = rv_op_vaesef_vs; break; 3983 case 7: op = rv_op_vaesz_vs; break; 3984 case 16: op = rv_op_vsm4r_vs; break; 3985 } 3986 break; 3987 case 42: op = rv_op_vaeskf2_vi; break; 3988 case 43: op = rv_op_vsm3c_vi; break; 3989 case 44: op = rv_op_vghsh_vv; break; 3990 case 45: op = rv_op_vsha2ms_vv; break; 3991 case 46: op = rv_op_vsha2ch_vv; break; 3992 case 47: op = rv_op_vsha2cl_vv; break; 3993 } 3994 } 3995 break; 3996 case 30: 3997 switch (((inst >> 22) & 0b1111111000) | 3998 ((inst >> 12) & 0b0000000111)) { 3999 case 0: op = rv_op_addd; break; 4000 case 1: op = rv_op_slld; break; 4001 case 5: op = rv_op_srld; break; 4002 case 8: op = rv_op_muld; break; 4003 case 12: op = rv_op_divd; break; 4004 case 13: op = rv_op_divud; break; 4005 case 14: op = rv_op_remd; break; 4006 case 15: op = rv_op_remud; break; 4007 case 256: op = rv_op_subd; break; 4008 case 261: op = rv_op_srad; break; 4009 } 4010 break; 4011 } 4012 break; 4013 } 4014 dec->op = op; 4015 } 4016 4017 /* operand extractors */ 4018 4019 static uint32_t operand_rd(rv_inst inst) 4020 { 4021 return (inst << 52) >> 59; 4022 } 4023 4024 static uint32_t operand_rs1(rv_inst inst) 4025 { 4026 return (inst << 44) >> 59; 4027 } 4028 4029 static uint32_t operand_rs2(rv_inst inst) 4030 { 4031 return (inst << 39) >> 59; 4032 } 4033 4034 static uint32_t operand_rs3(rv_inst inst) 4035 { 4036 return (inst << 32) >> 59; 4037 } 4038 4039 static uint32_t operand_aq(rv_inst inst) 4040 { 4041 return (inst << 37) >> 63; 4042 } 4043 4044 static uint32_t operand_rl(rv_inst inst) 4045 { 4046 return (inst << 38) >> 63; 4047 } 4048 4049 static uint32_t operand_pred(rv_inst inst) 4050 { 4051 return (inst << 36) >> 60; 4052 } 4053 4054 static uint32_t operand_succ(rv_inst inst) 4055 { 4056 return (inst << 40) >> 60; 4057 } 4058 4059 static uint32_t operand_rm(rv_inst inst) 4060 { 4061 return (inst << 49) >> 61; 4062 } 4063 4064 static uint32_t operand_shamt5(rv_inst inst) 4065 { 4066 return (inst << 39) >> 59; 4067 } 4068 4069 static uint32_t operand_shamt6(rv_inst inst) 4070 { 4071 return (inst << 38) >> 58; 4072 } 4073 4074 static uint32_t operand_shamt7(rv_inst inst) 4075 { 4076 return (inst << 37) >> 57; 4077 } 4078 4079 static uint32_t operand_crdq(rv_inst inst) 4080 { 4081 return (inst << 59) >> 61; 4082 } 4083 4084 static uint32_t operand_crs1q(rv_inst inst) 4085 { 4086 return (inst << 54) >> 61; 4087 } 4088 4089 static uint32_t operand_crs1rdq(rv_inst inst) 4090 { 4091 return (inst << 54) >> 61; 4092 } 4093 4094 static uint32_t operand_crs2q(rv_inst inst) 4095 { 4096 return (inst << 59) >> 61; 4097 } 4098 4099 static uint32_t calculate_xreg(uint32_t sreg) 4100 { 4101 return sreg < 2 ? sreg + 8 : sreg + 16; 4102 } 4103 4104 static uint32_t operand_sreg1(rv_inst inst) 4105 { 4106 return calculate_xreg((inst << 54) >> 61); 4107 } 4108 4109 static uint32_t operand_sreg2(rv_inst inst) 4110 { 4111 return calculate_xreg((inst << 59) >> 61); 4112 } 4113 4114 static uint32_t operand_crd(rv_inst inst) 4115 { 4116 return (inst << 52) >> 59; 4117 } 4118 4119 static uint32_t operand_crs1(rv_inst inst) 4120 { 4121 return (inst << 52) >> 59; 4122 } 4123 4124 static uint32_t operand_crs1rd(rv_inst inst) 4125 { 4126 return (inst << 52) >> 59; 4127 } 4128 4129 static uint32_t operand_crs2(rv_inst inst) 4130 { 4131 return (inst << 57) >> 59; 4132 } 4133 4134 static uint32_t operand_cimmsh5(rv_inst inst) 4135 { 4136 return (inst << 57) >> 59; 4137 } 4138 4139 static uint32_t operand_csr12(rv_inst inst) 4140 { 4141 return (inst << 32) >> 52; 4142 } 4143 4144 static int32_t operand_imm12(rv_inst inst) 4145 { 4146 return ((int64_t)inst << 32) >> 52; 4147 } 4148 4149 static int32_t operand_imm20(rv_inst inst) 4150 { 4151 return (((int64_t)inst << 32) >> 44) << 12; 4152 } 4153 4154 static int32_t operand_jimm20(rv_inst inst) 4155 { 4156 return (((int64_t)inst << 32) >> 63) << 20 | 4157 ((inst << 33) >> 54) << 1 | 4158 ((inst << 43) >> 63) << 11 | 4159 ((inst << 44) >> 56) << 12; 4160 } 4161 4162 static int32_t operand_simm12(rv_inst inst) 4163 { 4164 return (((int64_t)inst << 32) >> 57) << 5 | 4165 (inst << 52) >> 59; 4166 } 4167 4168 static int32_t operand_sbimm12(rv_inst inst) 4169 { 4170 return (((int64_t)inst << 32) >> 63) << 12 | 4171 ((inst << 33) >> 58) << 5 | 4172 ((inst << 52) >> 60) << 1 | 4173 ((inst << 56) >> 63) << 11; 4174 } 4175 4176 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) 4177 { 4178 int imm = ((inst << 51) >> 63) << 5 | 4179 (inst << 57) >> 59; 4180 if (isa == rv128) { 4181 imm = imm ? imm : 64; 4182 } 4183 return imm; 4184 } 4185 4186 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) 4187 { 4188 int imm = ((inst << 51) >> 63) << 5 | 4189 (inst << 57) >> 59; 4190 if (isa == rv128) { 4191 imm = imm | (imm & 32) << 1; 4192 imm = imm ? imm : 64; 4193 } 4194 return imm; 4195 } 4196 4197 static int32_t operand_cimmi(rv_inst inst) 4198 { 4199 return (((int64_t)inst << 51) >> 63) << 5 | 4200 (inst << 57) >> 59; 4201 } 4202 4203 static int32_t operand_cimmui(rv_inst inst) 4204 { 4205 return (((int64_t)inst << 51) >> 63) << 17 | 4206 ((inst << 57) >> 59) << 12; 4207 } 4208 4209 static uint32_t operand_cimmlwsp(rv_inst inst) 4210 { 4211 return ((inst << 51) >> 63) << 5 | 4212 ((inst << 57) >> 61) << 2 | 4213 ((inst << 60) >> 62) << 6; 4214 } 4215 4216 static uint32_t operand_cimmldsp(rv_inst inst) 4217 { 4218 return ((inst << 51) >> 63) << 5 | 4219 ((inst << 57) >> 62) << 3 | 4220 ((inst << 59) >> 61) << 6; 4221 } 4222 4223 static uint32_t operand_cimmlqsp(rv_inst inst) 4224 { 4225 return ((inst << 51) >> 63) << 5 | 4226 ((inst << 57) >> 63) << 4 | 4227 ((inst << 58) >> 60) << 6; 4228 } 4229 4230 static int32_t operand_cimm16sp(rv_inst inst) 4231 { 4232 return (((int64_t)inst << 51) >> 63) << 9 | 4233 ((inst << 57) >> 63) << 4 | 4234 ((inst << 58) >> 63) << 6 | 4235 ((inst << 59) >> 62) << 7 | 4236 ((inst << 61) >> 63) << 5; 4237 } 4238 4239 static int32_t operand_cimmj(rv_inst inst) 4240 { 4241 return (((int64_t)inst << 51) >> 63) << 11 | 4242 ((inst << 52) >> 63) << 4 | 4243 ((inst << 53) >> 62) << 8 | 4244 ((inst << 55) >> 63) << 10 | 4245 ((inst << 56) >> 63) << 6 | 4246 ((inst << 57) >> 63) << 7 | 4247 ((inst << 58) >> 61) << 1 | 4248 ((inst << 61) >> 63) << 5; 4249 } 4250 4251 static int32_t operand_cimmb(rv_inst inst) 4252 { 4253 return (((int64_t)inst << 51) >> 63) << 8 | 4254 ((inst << 52) >> 62) << 3 | 4255 ((inst << 57) >> 62) << 6 | 4256 ((inst << 59) >> 62) << 1 | 4257 ((inst << 61) >> 63) << 5; 4258 } 4259 4260 static uint32_t operand_cimmswsp(rv_inst inst) 4261 { 4262 return ((inst << 51) >> 60) << 2 | 4263 ((inst << 55) >> 62) << 6; 4264 } 4265 4266 static uint32_t operand_cimmsdsp(rv_inst inst) 4267 { 4268 return ((inst << 51) >> 61) << 3 | 4269 ((inst << 54) >> 61) << 6; 4270 } 4271 4272 static uint32_t operand_cimmsqsp(rv_inst inst) 4273 { 4274 return ((inst << 51) >> 62) << 4 | 4275 ((inst << 53) >> 60) << 6; 4276 } 4277 4278 static uint32_t operand_cimm4spn(rv_inst inst) 4279 { 4280 return ((inst << 51) >> 62) << 4 | 4281 ((inst << 53) >> 60) << 6 | 4282 ((inst << 57) >> 63) << 2 | 4283 ((inst << 58) >> 63) << 3; 4284 } 4285 4286 static uint32_t operand_cimmw(rv_inst inst) 4287 { 4288 return ((inst << 51) >> 61) << 3 | 4289 ((inst << 57) >> 63) << 2 | 4290 ((inst << 58) >> 63) << 6; 4291 } 4292 4293 static uint32_t operand_cimmd(rv_inst inst) 4294 { 4295 return ((inst << 51) >> 61) << 3 | 4296 ((inst << 57) >> 62) << 6; 4297 } 4298 4299 static uint32_t operand_cimmq(rv_inst inst) 4300 { 4301 return ((inst << 51) >> 62) << 4 | 4302 ((inst << 53) >> 63) << 8 | 4303 ((inst << 57) >> 62) << 6; 4304 } 4305 4306 static uint32_t operand_vimm(rv_inst inst) 4307 { 4308 return (int64_t)(inst << 44) >> 59; 4309 } 4310 4311 static uint32_t operand_vzimm11(rv_inst inst) 4312 { 4313 return (inst << 33) >> 53; 4314 } 4315 4316 static uint32_t operand_vzimm10(rv_inst inst) 4317 { 4318 return (inst << 34) >> 54; 4319 } 4320 4321 static uint32_t operand_vzimm6(rv_inst inst) 4322 { 4323 return ((inst << 37) >> 63) << 5 | 4324 ((inst << 44) >> 59); 4325 } 4326 4327 static uint32_t operand_bs(rv_inst inst) 4328 { 4329 return (inst << 32) >> 62; 4330 } 4331 4332 static uint32_t operand_rnum(rv_inst inst) 4333 { 4334 return (inst << 40) >> 60; 4335 } 4336 4337 static uint32_t operand_vm(rv_inst inst) 4338 { 4339 return (inst << 38) >> 63; 4340 } 4341 4342 static uint32_t operand_uimm_c_lb(rv_inst inst) 4343 { 4344 return (((inst << 58) >> 63) << 1) | 4345 ((inst << 57) >> 63); 4346 } 4347 4348 static uint32_t operand_uimm_c_lh(rv_inst inst) 4349 { 4350 return (((inst << 58) >> 63) << 1); 4351 } 4352 4353 static uint32_t operand_zcmp_spimm(rv_inst inst) 4354 { 4355 return ((inst << 60) >> 62) << 4; 4356 } 4357 4358 static uint32_t operand_zcmp_rlist(rv_inst inst) 4359 { 4360 return ((inst << 56) >> 60); 4361 } 4362 4363 static uint32_t operand_imm6(rv_inst inst) 4364 { 4365 return (inst << 38) >> 60; 4366 } 4367 4368 static uint32_t operand_imm2(rv_inst inst) 4369 { 4370 return (inst << 37) >> 62; 4371 } 4372 4373 static uint32_t operand_immh(rv_inst inst) 4374 { 4375 return (inst << 32) >> 58; 4376 } 4377 4378 static uint32_t operand_imml(rv_inst inst) 4379 { 4380 return (inst << 38) >> 58; 4381 } 4382 4383 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm) 4384 { 4385 int xlen_bytes_log2 = isa == rv64 ? 3 : 2; 4386 int regs = rlist == 15 ? 13 : rlist - 3; 4387 uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16); 4388 return stack_adj_base + spimm; 4389 } 4390 4391 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa) 4392 { 4393 return calculate_stack_adj(isa, operand_zcmp_rlist(inst), 4394 operand_zcmp_spimm(inst)); 4395 } 4396 4397 static uint32_t operand_tbl_index(rv_inst inst) 4398 { 4399 return ((inst << 54) >> 56); 4400 } 4401 4402 /* decode operands */ 4403 4404 static void decode_inst_operands(rv_decode *dec, rv_isa isa) 4405 { 4406 const rv_opcode_data *opcode_data = dec->opcode_data; 4407 rv_inst inst = dec->inst; 4408 dec->codec = opcode_data[dec->op].codec; 4409 switch (dec->codec) { 4410 case rv_codec_none: 4411 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4412 dec->imm = 0; 4413 break; 4414 case rv_codec_u: 4415 dec->rd = operand_rd(inst); 4416 dec->rs1 = dec->rs2 = rv_ireg_zero; 4417 dec->imm = operand_imm20(inst); 4418 break; 4419 case rv_codec_uj: 4420 dec->rd = operand_rd(inst); 4421 dec->rs1 = dec->rs2 = rv_ireg_zero; 4422 dec->imm = operand_jimm20(inst); 4423 break; 4424 case rv_codec_i: 4425 dec->rd = operand_rd(inst); 4426 dec->rs1 = operand_rs1(inst); 4427 dec->rs2 = rv_ireg_zero; 4428 dec->imm = operand_imm12(inst); 4429 break; 4430 case rv_codec_i_sh5: 4431 dec->rd = operand_rd(inst); 4432 dec->rs1 = operand_rs1(inst); 4433 dec->rs2 = rv_ireg_zero; 4434 dec->imm = operand_shamt5(inst); 4435 break; 4436 case rv_codec_i_sh6: 4437 dec->rd = operand_rd(inst); 4438 dec->rs1 = operand_rs1(inst); 4439 dec->rs2 = rv_ireg_zero; 4440 dec->imm = operand_shamt6(inst); 4441 break; 4442 case rv_codec_i_sh7: 4443 dec->rd = operand_rd(inst); 4444 dec->rs1 = operand_rs1(inst); 4445 dec->rs2 = rv_ireg_zero; 4446 dec->imm = operand_shamt7(inst); 4447 break; 4448 case rv_codec_i_csr: 4449 dec->rd = operand_rd(inst); 4450 dec->rs1 = operand_rs1(inst); 4451 dec->rs2 = rv_ireg_zero; 4452 dec->imm = operand_csr12(inst); 4453 break; 4454 case rv_codec_s: 4455 dec->rd = rv_ireg_zero; 4456 dec->rs1 = operand_rs1(inst); 4457 dec->rs2 = operand_rs2(inst); 4458 dec->imm = operand_simm12(inst); 4459 break; 4460 case rv_codec_sb: 4461 dec->rd = rv_ireg_zero; 4462 dec->rs1 = operand_rs1(inst); 4463 dec->rs2 = operand_rs2(inst); 4464 dec->imm = operand_sbimm12(inst); 4465 break; 4466 case rv_codec_r: 4467 dec->rd = operand_rd(inst); 4468 dec->rs1 = operand_rs1(inst); 4469 dec->rs2 = operand_rs2(inst); 4470 dec->imm = 0; 4471 break; 4472 case rv_codec_r_m: 4473 dec->rd = operand_rd(inst); 4474 dec->rs1 = operand_rs1(inst); 4475 dec->rs2 = operand_rs2(inst); 4476 dec->imm = 0; 4477 dec->rm = operand_rm(inst); 4478 break; 4479 case rv_codec_r4_m: 4480 dec->rd = operand_rd(inst); 4481 dec->rs1 = operand_rs1(inst); 4482 dec->rs2 = operand_rs2(inst); 4483 dec->rs3 = operand_rs3(inst); 4484 dec->imm = 0; 4485 dec->rm = operand_rm(inst); 4486 break; 4487 case rv_codec_r_a: 4488 dec->rd = operand_rd(inst); 4489 dec->rs1 = operand_rs1(inst); 4490 dec->rs2 = operand_rs2(inst); 4491 dec->imm = 0; 4492 dec->aq = operand_aq(inst); 4493 dec->rl = operand_rl(inst); 4494 break; 4495 case rv_codec_r_l: 4496 dec->rd = operand_rd(inst); 4497 dec->rs1 = operand_rs1(inst); 4498 dec->rs2 = rv_ireg_zero; 4499 dec->imm = 0; 4500 dec->aq = operand_aq(inst); 4501 dec->rl = operand_rl(inst); 4502 break; 4503 case rv_codec_r_f: 4504 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4505 dec->pred = operand_pred(inst); 4506 dec->succ = operand_succ(inst); 4507 dec->imm = 0; 4508 break; 4509 case rv_codec_cb: 4510 dec->rd = rv_ireg_zero; 4511 dec->rs1 = operand_crs1q(inst) + 8; 4512 dec->rs2 = rv_ireg_zero; 4513 dec->imm = operand_cimmb(inst); 4514 break; 4515 case rv_codec_cb_imm: 4516 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4517 dec->rs2 = rv_ireg_zero; 4518 dec->imm = operand_cimmi(inst); 4519 break; 4520 case rv_codec_cb_sh5: 4521 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4522 dec->rs2 = rv_ireg_zero; 4523 dec->imm = operand_cimmsh5(inst); 4524 break; 4525 case rv_codec_cb_sh6: 4526 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4527 dec->rs2 = rv_ireg_zero; 4528 dec->imm = operand_cimmshr6(inst, isa); 4529 break; 4530 case rv_codec_ci: 4531 dec->rd = dec->rs1 = operand_crs1rd(inst); 4532 dec->rs2 = rv_ireg_zero; 4533 dec->imm = operand_cimmi(inst); 4534 break; 4535 case rv_codec_ci_sh5: 4536 dec->rd = dec->rs1 = operand_crs1rd(inst); 4537 dec->rs2 = rv_ireg_zero; 4538 dec->imm = operand_cimmsh5(inst); 4539 break; 4540 case rv_codec_ci_sh6: 4541 dec->rd = dec->rs1 = operand_crs1rd(inst); 4542 dec->rs2 = rv_ireg_zero; 4543 dec->imm = operand_cimmshl6(inst, isa); 4544 break; 4545 case rv_codec_ci_16sp: 4546 dec->rd = rv_ireg_sp; 4547 dec->rs1 = rv_ireg_sp; 4548 dec->rs2 = rv_ireg_zero; 4549 dec->imm = operand_cimm16sp(inst); 4550 break; 4551 case rv_codec_ci_lwsp: 4552 dec->rd = operand_crd(inst); 4553 dec->rs1 = rv_ireg_sp; 4554 dec->rs2 = rv_ireg_zero; 4555 dec->imm = operand_cimmlwsp(inst); 4556 break; 4557 case rv_codec_ci_ldsp: 4558 dec->rd = operand_crd(inst); 4559 dec->rs1 = rv_ireg_sp; 4560 dec->rs2 = rv_ireg_zero; 4561 dec->imm = operand_cimmldsp(inst); 4562 break; 4563 case rv_codec_ci_lqsp: 4564 dec->rd = operand_crd(inst); 4565 dec->rs1 = rv_ireg_sp; 4566 dec->rs2 = rv_ireg_zero; 4567 dec->imm = operand_cimmlqsp(inst); 4568 break; 4569 case rv_codec_ci_li: 4570 dec->rd = operand_crd(inst); 4571 dec->rs1 = rv_ireg_zero; 4572 dec->rs2 = rv_ireg_zero; 4573 dec->imm = operand_cimmi(inst); 4574 break; 4575 case rv_codec_ci_lui: 4576 dec->rd = operand_crd(inst); 4577 dec->rs1 = rv_ireg_zero; 4578 dec->rs2 = rv_ireg_zero; 4579 dec->imm = operand_cimmui(inst); 4580 break; 4581 case rv_codec_ci_none: 4582 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4583 dec->imm = 0; 4584 break; 4585 case rv_codec_ciw_4spn: 4586 dec->rd = operand_crdq(inst) + 8; 4587 dec->rs1 = rv_ireg_sp; 4588 dec->rs2 = rv_ireg_zero; 4589 dec->imm = operand_cimm4spn(inst); 4590 break; 4591 case rv_codec_cj: 4592 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4593 dec->imm = operand_cimmj(inst); 4594 break; 4595 case rv_codec_cj_jal: 4596 dec->rd = rv_ireg_ra; 4597 dec->rs1 = dec->rs2 = rv_ireg_zero; 4598 dec->imm = operand_cimmj(inst); 4599 break; 4600 case rv_codec_cl_lw: 4601 dec->rd = operand_crdq(inst) + 8; 4602 dec->rs1 = operand_crs1q(inst) + 8; 4603 dec->rs2 = rv_ireg_zero; 4604 dec->imm = operand_cimmw(inst); 4605 break; 4606 case rv_codec_cl_ld: 4607 dec->rd = operand_crdq(inst) + 8; 4608 dec->rs1 = operand_crs1q(inst) + 8; 4609 dec->rs2 = rv_ireg_zero; 4610 dec->imm = operand_cimmd(inst); 4611 break; 4612 case rv_codec_cl_lq: 4613 dec->rd = operand_crdq(inst) + 8; 4614 dec->rs1 = operand_crs1q(inst) + 8; 4615 dec->rs2 = rv_ireg_zero; 4616 dec->imm = operand_cimmq(inst); 4617 break; 4618 case rv_codec_cr: 4619 dec->rd = dec->rs1 = operand_crs1rd(inst); 4620 dec->rs2 = operand_crs2(inst); 4621 dec->imm = 0; 4622 break; 4623 case rv_codec_cr_mv: 4624 dec->rd = operand_crd(inst); 4625 dec->rs1 = operand_crs2(inst); 4626 dec->rs2 = rv_ireg_zero; 4627 dec->imm = 0; 4628 break; 4629 case rv_codec_cr_jalr: 4630 dec->rd = rv_ireg_ra; 4631 dec->rs1 = operand_crs1(inst); 4632 dec->rs2 = rv_ireg_zero; 4633 dec->imm = 0; 4634 break; 4635 case rv_codec_cr_jr: 4636 dec->rd = rv_ireg_zero; 4637 dec->rs1 = operand_crs1(inst); 4638 dec->rs2 = rv_ireg_zero; 4639 dec->imm = 0; 4640 break; 4641 case rv_codec_cs: 4642 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4643 dec->rs2 = operand_crs2q(inst) + 8; 4644 dec->imm = 0; 4645 break; 4646 case rv_codec_cs_sw: 4647 dec->rd = rv_ireg_zero; 4648 dec->rs1 = operand_crs1q(inst) + 8; 4649 dec->rs2 = operand_crs2q(inst) + 8; 4650 dec->imm = operand_cimmw(inst); 4651 break; 4652 case rv_codec_cs_sd: 4653 dec->rd = rv_ireg_zero; 4654 dec->rs1 = operand_crs1q(inst) + 8; 4655 dec->rs2 = operand_crs2q(inst) + 8; 4656 dec->imm = operand_cimmd(inst); 4657 break; 4658 case rv_codec_cs_sq: 4659 dec->rd = rv_ireg_zero; 4660 dec->rs1 = operand_crs1q(inst) + 8; 4661 dec->rs2 = operand_crs2q(inst) + 8; 4662 dec->imm = operand_cimmq(inst); 4663 break; 4664 case rv_codec_css_swsp: 4665 dec->rd = rv_ireg_zero; 4666 dec->rs1 = rv_ireg_sp; 4667 dec->rs2 = operand_crs2(inst); 4668 dec->imm = operand_cimmswsp(inst); 4669 break; 4670 case rv_codec_css_sdsp: 4671 dec->rd = rv_ireg_zero; 4672 dec->rs1 = rv_ireg_sp; 4673 dec->rs2 = operand_crs2(inst); 4674 dec->imm = operand_cimmsdsp(inst); 4675 break; 4676 case rv_codec_css_sqsp: 4677 dec->rd = rv_ireg_zero; 4678 dec->rs1 = rv_ireg_sp; 4679 dec->rs2 = operand_crs2(inst); 4680 dec->imm = operand_cimmsqsp(inst); 4681 break; 4682 case rv_codec_k_bs: 4683 dec->rs1 = operand_rs1(inst); 4684 dec->rs2 = operand_rs2(inst); 4685 dec->bs = operand_bs(inst); 4686 break; 4687 case rv_codec_k_rnum: 4688 dec->rd = operand_rd(inst); 4689 dec->rs1 = operand_rs1(inst); 4690 dec->rnum = operand_rnum(inst); 4691 break; 4692 case rv_codec_v_r: 4693 dec->rd = operand_rd(inst); 4694 dec->rs1 = operand_rs1(inst); 4695 dec->rs2 = operand_rs2(inst); 4696 dec->vm = operand_vm(inst); 4697 break; 4698 case rv_codec_v_ldst: 4699 dec->rd = operand_rd(inst); 4700 dec->rs1 = operand_rs1(inst); 4701 dec->vm = operand_vm(inst); 4702 break; 4703 case rv_codec_v_i: 4704 dec->rd = operand_rd(inst); 4705 dec->rs2 = operand_rs2(inst); 4706 dec->imm = operand_vimm(inst); 4707 dec->vm = operand_vm(inst); 4708 break; 4709 case rv_codec_vror_vi: 4710 dec->rd = operand_rd(inst); 4711 dec->rs2 = operand_rs2(inst); 4712 dec->imm = operand_vzimm6(inst); 4713 dec->vm = operand_vm(inst); 4714 break; 4715 case rv_codec_vsetvli: 4716 dec->rd = operand_rd(inst); 4717 dec->rs1 = operand_rs1(inst); 4718 dec->vzimm = operand_vzimm11(inst); 4719 break; 4720 case rv_codec_vsetivli: 4721 dec->rd = operand_rd(inst); 4722 dec->imm = operand_vimm(inst); 4723 dec->vzimm = operand_vzimm10(inst); 4724 break; 4725 case rv_codec_zcb_lb: 4726 dec->rs1 = operand_crs1q(inst) + 8; 4727 dec->rs2 = operand_crs2q(inst) + 8; 4728 dec->imm = operand_uimm_c_lb(inst); 4729 break; 4730 case rv_codec_zcb_lh: 4731 dec->rs1 = operand_crs1q(inst) + 8; 4732 dec->rs2 = operand_crs2q(inst) + 8; 4733 dec->imm = operand_uimm_c_lh(inst); 4734 break; 4735 case rv_codec_zcb_ext: 4736 dec->rd = operand_crs1q(inst) + 8; 4737 break; 4738 case rv_codec_zcb_mul: 4739 dec->rd = operand_crs1rdq(inst) + 8; 4740 dec->rs2 = operand_crs2q(inst) + 8; 4741 break; 4742 case rv_codec_zcmp_cm_pushpop: 4743 dec->imm = operand_zcmp_stack_adj(inst, isa); 4744 dec->rlist = operand_zcmp_rlist(inst); 4745 break; 4746 case rv_codec_zcmp_cm_mv: 4747 dec->rd = operand_sreg1(inst); 4748 dec->rs2 = operand_sreg2(inst); 4749 break; 4750 case rv_codec_zcmt_jt: 4751 dec->imm = operand_tbl_index(inst); 4752 break; 4753 case rv_codec_fli: 4754 dec->rd = operand_rd(inst); 4755 dec->imm = operand_rs1(inst); 4756 break; 4757 case rv_codec_r2_imm5: 4758 dec->rd = operand_rd(inst); 4759 dec->rs1 = operand_rs1(inst); 4760 dec->imm = operand_rs2(inst); 4761 break; 4762 case rv_codec_r2: 4763 dec->rd = operand_rd(inst); 4764 dec->rs1 = operand_rs1(inst); 4765 break; 4766 case rv_codec_r2_imm6: 4767 dec->rd = operand_rd(inst); 4768 dec->rs1 = operand_rs1(inst); 4769 dec->imm = operand_imm6(inst); 4770 break; 4771 case rv_codec_r_imm2: 4772 dec->rd = operand_rd(inst); 4773 dec->rs1 = operand_rs1(inst); 4774 dec->rs2 = operand_rs2(inst); 4775 dec->imm = operand_imm2(inst); 4776 break; 4777 case rv_codec_r2_immhl: 4778 dec->rd = operand_rd(inst); 4779 dec->rs1 = operand_rs1(inst); 4780 dec->imm = operand_immh(inst); 4781 dec->imm1 = operand_imml(inst); 4782 break; 4783 case rv_codec_r2_imm2_imm5: 4784 dec->rd = operand_rd(inst); 4785 dec->rs1 = operand_rs1(inst); 4786 dec->imm = sextract32(operand_rs2(inst), 0, 5); 4787 dec->imm1 = operand_imm2(inst); 4788 break; 4789 }; 4790 } 4791 4792 /* check constraint */ 4793 4794 static bool check_constraints(rv_decode *dec, const rvc_constraint *c) 4795 { 4796 int32_t imm = dec->imm; 4797 uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2; 4798 while (*c != rvc_end) { 4799 switch (*c) { 4800 case rvc_rd_eq_ra: 4801 if (!(rd == 1)) { 4802 return false; 4803 } 4804 break; 4805 case rvc_rd_eq_x0: 4806 if (!(rd == 0)) { 4807 return false; 4808 } 4809 break; 4810 case rvc_rs1_eq_x0: 4811 if (!(rs1 == 0)) { 4812 return false; 4813 } 4814 break; 4815 case rvc_rs2_eq_x0: 4816 if (!(rs2 == 0)) { 4817 return false; 4818 } 4819 break; 4820 case rvc_rs2_eq_rs1: 4821 if (!(rs2 == rs1)) { 4822 return false; 4823 } 4824 break; 4825 case rvc_rs1_eq_ra: 4826 if (!(rs1 == 1)) { 4827 return false; 4828 } 4829 break; 4830 case rvc_imm_eq_zero: 4831 if (!(imm == 0)) { 4832 return false; 4833 } 4834 break; 4835 case rvc_imm_eq_n1: 4836 if (!(imm == -1)) { 4837 return false; 4838 } 4839 break; 4840 case rvc_imm_eq_p1: 4841 if (!(imm == 1)) { 4842 return false; 4843 } 4844 break; 4845 case rvc_csr_eq_0x001: 4846 if (!(imm == 0x001)) { 4847 return false; 4848 } 4849 break; 4850 case rvc_csr_eq_0x002: 4851 if (!(imm == 0x002)) { 4852 return false; 4853 } 4854 break; 4855 case rvc_csr_eq_0x003: 4856 if (!(imm == 0x003)) { 4857 return false; 4858 } 4859 break; 4860 case rvc_csr_eq_0xc00: 4861 if (!(imm == 0xc00)) { 4862 return false; 4863 } 4864 break; 4865 case rvc_csr_eq_0xc01: 4866 if (!(imm == 0xc01)) { 4867 return false; 4868 } 4869 break; 4870 case rvc_csr_eq_0xc02: 4871 if (!(imm == 0xc02)) { 4872 return false; 4873 } 4874 break; 4875 case rvc_csr_eq_0xc80: 4876 if (!(imm == 0xc80)) { 4877 return false; 4878 } 4879 break; 4880 case rvc_csr_eq_0xc81: 4881 if (!(imm == 0xc81)) { 4882 return false; 4883 } 4884 break; 4885 case rvc_csr_eq_0xc82: 4886 if (!(imm == 0xc82)) { 4887 return false; 4888 } 4889 break; 4890 default: break; 4891 } 4892 c++; 4893 } 4894 return true; 4895 } 4896 4897 /* instruction length */ 4898 4899 static size_t inst_length(rv_inst inst) 4900 { 4901 /* NOTE: supports maximum instruction size of 64-bits */ 4902 4903 /* 4904 * instruction length coding 4905 * 4906 * aa - 16 bit aa != 11 4907 * bbb11 - 32 bit bbb != 111 4908 * 011111 - 48 bit 4909 * 0111111 - 64 bit 4910 */ 4911 4912 return (inst & 0b11) != 0b11 ? 2 4913 : (inst & 0b11100) != 0b11100 ? 4 4914 : (inst & 0b111111) == 0b011111 ? 6 4915 : (inst & 0b1111111) == 0b0111111 ? 8 4916 : 0; 4917 } 4918 4919 /* format instruction */ 4920 4921 static GString *format_inst(size_t tab, rv_decode *dec) 4922 { 4923 const rv_opcode_data *opcode_data = dec->opcode_data; 4924 GString *buf = g_string_sized_new(64); 4925 const char *fmt; 4926 4927 fmt = opcode_data[dec->op].format; 4928 while (*fmt) { 4929 switch (*fmt) { 4930 case 'O': 4931 g_string_append(buf, opcode_data[dec->op].name); 4932 break; 4933 case '(': 4934 case ',': 4935 case ')': 4936 case '-': 4937 g_string_append_c(buf, *fmt); 4938 break; 4939 case 'b': 4940 g_string_append_printf(buf, "%d", dec->bs); 4941 break; 4942 case 'n': 4943 g_string_append_printf(buf, "%d", dec->rnum); 4944 break; 4945 case '0': 4946 g_string_append(buf, rv_ireg_name_sym[dec->rd]); 4947 break; 4948 case '1': 4949 g_string_append(buf, rv_ireg_name_sym[dec->rs1]); 4950 break; 4951 case '2': 4952 g_string_append(buf, rv_ireg_name_sym[dec->rs2]); 4953 break; 4954 case '3': 4955 if (dec->cfg->ext_zfinx) { 4956 g_string_append(buf, rv_ireg_name_sym[dec->rd]); 4957 } else { 4958 g_string_append(buf, rv_freg_name_sym[dec->rd]); 4959 } 4960 break; 4961 case '4': 4962 if (dec->cfg->ext_zfinx) { 4963 g_string_append(buf, rv_ireg_name_sym[dec->rs1]); 4964 } else { 4965 g_string_append(buf, rv_freg_name_sym[dec->rs1]); 4966 } 4967 break; 4968 case '5': 4969 if (dec->cfg->ext_zfinx) { 4970 g_string_append(buf, rv_ireg_name_sym[dec->rs2]); 4971 } else { 4972 g_string_append(buf, rv_freg_name_sym[dec->rs2]); 4973 } 4974 break; 4975 case '6': 4976 if (dec->cfg->ext_zfinx) { 4977 g_string_append(buf, rv_ireg_name_sym[dec->rs3]); 4978 } else { 4979 g_string_append(buf, rv_freg_name_sym[dec->rs3]); 4980 } 4981 break; 4982 case '7': 4983 g_string_append_printf(buf, "%d", dec->rs1); 4984 break; 4985 case 'i': 4986 g_string_append_printf(buf, "%d", dec->imm); 4987 break; 4988 case 'u': 4989 g_string_append_printf(buf, "%u", ((uint32_t)dec->imm & 0b111111)); 4990 break; 4991 case 'j': 4992 g_string_append_printf(buf, "%d", dec->imm1); 4993 break; 4994 case 'o': 4995 g_string_append_printf(buf, "%d", dec->imm); 4996 while (buf->len < tab * 2) { 4997 g_string_append_c(buf, ' '); 4998 } 4999 g_string_append_printf(buf, "# 0x%" PRIx64, dec->pc + dec->imm); 5000 break; 5001 case 'U': 5002 fmt++; 5003 g_string_append_printf(buf, "%d", dec->imm >> 12); 5004 if (*fmt == 'o') { 5005 while (buf->len < tab * 2) { 5006 g_string_append_c(buf, ' '); 5007 } 5008 g_string_append_printf(buf, "# 0x%" PRIx64, dec->pc + dec->imm); 5009 } 5010 break; 5011 case 'c': { 5012 const char *name = csr_name(dec->imm & 0xfff); 5013 if (name) { 5014 g_string_append(buf, name); 5015 } else { 5016 g_string_append_printf(buf, "0x%03x", dec->imm & 0xfff); 5017 } 5018 break; 5019 } 5020 case 'r': 5021 switch (dec->rm) { 5022 case rv_rm_rne: 5023 g_string_append(buf, "rne"); 5024 break; 5025 case rv_rm_rtz: 5026 g_string_append(buf, "rtz"); 5027 break; 5028 case rv_rm_rdn: 5029 g_string_append(buf, "rdn"); 5030 break; 5031 case rv_rm_rup: 5032 g_string_append(buf, "rup"); 5033 break; 5034 case rv_rm_rmm: 5035 g_string_append(buf, "rmm"); 5036 break; 5037 case rv_rm_dyn: 5038 g_string_append(buf, "dyn"); 5039 break; 5040 default: 5041 g_string_append(buf, "inv"); 5042 break; 5043 } 5044 break; 5045 case 'p': 5046 if (dec->pred & rv_fence_i) { 5047 g_string_append_c(buf, 'i'); 5048 } 5049 if (dec->pred & rv_fence_o) { 5050 g_string_append_c(buf, 'o'); 5051 } 5052 if (dec->pred & rv_fence_r) { 5053 g_string_append_c(buf, 'r'); 5054 } 5055 if (dec->pred & rv_fence_w) { 5056 g_string_append_c(buf, 'w'); 5057 } 5058 break; 5059 case 's': 5060 if (dec->succ & rv_fence_i) { 5061 g_string_append_c(buf, 'i'); 5062 } 5063 if (dec->succ & rv_fence_o) { 5064 g_string_append_c(buf, 'o'); 5065 } 5066 if (dec->succ & rv_fence_r) { 5067 g_string_append_c(buf, 'r'); 5068 } 5069 if (dec->succ & rv_fence_w) { 5070 g_string_append_c(buf, 'w'); 5071 } 5072 break; 5073 case '\t': 5074 while (buf->len < tab) { 5075 g_string_append_c(buf, ' '); 5076 } 5077 break; 5078 case 'A': 5079 if (dec->aq) { 5080 g_string_append(buf, ".aq"); 5081 } 5082 break; 5083 case 'R': 5084 if (dec->rl) { 5085 g_string_append(buf, ".rl"); 5086 } 5087 break; 5088 case 'l': 5089 g_string_append(buf, ",v0"); 5090 break; 5091 case 'm': 5092 if (dec->vm == 0) { 5093 g_string_append(buf, ",v0.t"); 5094 } 5095 break; 5096 case 'D': 5097 g_string_append(buf, rv_vreg_name_sym[dec->rd]); 5098 break; 5099 case 'E': 5100 g_string_append(buf, rv_vreg_name_sym[dec->rs1]); 5101 break; 5102 case 'F': 5103 g_string_append(buf, rv_vreg_name_sym[dec->rs2]); 5104 break; 5105 case 'G': 5106 g_string_append(buf, rv_vreg_name_sym[dec->rs3]); 5107 break; 5108 case 'v': { 5109 const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3); 5110 const int lmul = dec->vzimm & 0b11; 5111 const int flmul = (dec->vzimm >> 2) & 1; 5112 const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu"; 5113 const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu"; 5114 5115 g_string_append_printf(buf, "e%d,m", sew); 5116 if (flmul) { 5117 switch (lmul) { 5118 case 3: 5119 g_string_append(buf, "f2"); 5120 break; 5121 case 2: 5122 g_string_append(buf, "f4"); 5123 break; 5124 case 1: 5125 g_string_append(buf, "f8"); 5126 break; 5127 } 5128 } else { 5129 g_string_append_printf(buf, "%d", 1 << lmul); 5130 } 5131 g_string_append_c(buf, ','); 5132 g_string_append(buf, vta); 5133 g_string_append_c(buf, ','); 5134 g_string_append(buf, vma); 5135 break; 5136 } 5137 case 'x': { 5138 switch (dec->rlist) { 5139 case 4: 5140 g_string_append(buf, "{ra}"); 5141 break; 5142 case 5: 5143 g_string_append(buf, "{ra, s0}"); 5144 break; 5145 case 15: 5146 g_string_append(buf, "{ra, s0-s11}"); 5147 break; 5148 default: 5149 g_string_append_printf(buf, "{ra, s0-s%d}", dec->rlist - 5); 5150 break; 5151 } 5152 break; 5153 } 5154 case 'h': 5155 g_string_append(buf, rv_fli_name_const[dec->imm]); 5156 break; 5157 default: 5158 break; 5159 } 5160 fmt++; 5161 } 5162 5163 return buf; 5164 } 5165 5166 /* lift instruction to pseudo-instruction */ 5167 5168 static void decode_inst_lift_pseudo(rv_decode *dec) 5169 { 5170 const rv_opcode_data *opcode_data = dec->opcode_data; 5171 const rv_comp_data *comp_data = opcode_data[dec->op].pseudo; 5172 if (!comp_data) { 5173 return; 5174 } 5175 while (comp_data->constraints) { 5176 if (check_constraints(dec, comp_data->constraints)) { 5177 dec->op = comp_data->op; 5178 dec->codec = opcode_data[dec->op].codec; 5179 return; 5180 } 5181 comp_data++; 5182 } 5183 } 5184 5185 /* decompress instruction */ 5186 5187 static void decode_inst_decompress_rv32(rv_decode *dec) 5188 { 5189 const rv_opcode_data *opcode_data = dec->opcode_data; 5190 int decomp_op = opcode_data[dec->op].decomp_rv32; 5191 if (decomp_op != rv_op_illegal) { 5192 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5193 && dec->imm == 0) { 5194 dec->op = rv_op_illegal; 5195 } else { 5196 dec->op = decomp_op; 5197 dec->codec = opcode_data[decomp_op].codec; 5198 } 5199 } 5200 } 5201 5202 static void decode_inst_decompress_rv64(rv_decode *dec) 5203 { 5204 const rv_opcode_data *opcode_data = dec->opcode_data; 5205 int decomp_op = opcode_data[dec->op].decomp_rv64; 5206 if (decomp_op != rv_op_illegal) { 5207 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5208 && dec->imm == 0) { 5209 dec->op = rv_op_illegal; 5210 } else { 5211 dec->op = decomp_op; 5212 dec->codec = opcode_data[decomp_op].codec; 5213 } 5214 } 5215 } 5216 5217 static void decode_inst_decompress_rv128(rv_decode *dec) 5218 { 5219 const rv_opcode_data *opcode_data = dec->opcode_data; 5220 int decomp_op = opcode_data[dec->op].decomp_rv128; 5221 if (decomp_op != rv_op_illegal) { 5222 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5223 && dec->imm == 0) { 5224 dec->op = rv_op_illegal; 5225 } else { 5226 dec->op = decomp_op; 5227 dec->codec = opcode_data[decomp_op].codec; 5228 } 5229 } 5230 } 5231 5232 static void decode_inst_decompress(rv_decode *dec, rv_isa isa) 5233 { 5234 switch (isa) { 5235 case rv32: 5236 decode_inst_decompress_rv32(dec); 5237 break; 5238 case rv64: 5239 decode_inst_decompress_rv64(dec); 5240 break; 5241 case rv128: 5242 decode_inst_decompress_rv128(dec); 5243 break; 5244 } 5245 } 5246 5247 /* disassemble instruction */ 5248 5249 static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst, 5250 RISCVCPUConfig *cfg) 5251 { 5252 rv_decode dec = { 0 }; 5253 dec.pc = pc; 5254 dec.inst = inst; 5255 dec.cfg = cfg; 5256 5257 static const struct { 5258 bool (*guard_func)(const RISCVCPUConfig *); 5259 const rv_opcode_data *opcode_data; 5260 void (*decode_func)(rv_decode *, rv_isa); 5261 } decoders[] = { 5262 { always_true_p, rvi_opcode_data, decode_inst_opcode }, 5263 { has_xtheadba_p, xthead_opcode_data, decode_xtheadba }, 5264 { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb }, 5265 { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs }, 5266 { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo }, 5267 { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov }, 5268 { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx }, 5269 { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv }, 5270 { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac }, 5271 { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx }, 5272 { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair }, 5273 { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync }, 5274 { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops }, 5275 }; 5276 5277 for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { 5278 bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func; 5279 const rv_opcode_data *opcode_data = decoders[i].opcode_data; 5280 void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func; 5281 5282 if (guard_func(cfg)) { 5283 dec.opcode_data = opcode_data; 5284 decode_func(&dec, isa); 5285 if (dec.op != rv_op_illegal) 5286 break; 5287 } 5288 } 5289 5290 if (dec.op == rv_op_illegal) { 5291 dec.opcode_data = rvi_opcode_data; 5292 } 5293 5294 decode_inst_operands(&dec, isa); 5295 decode_inst_decompress(&dec, isa); 5296 decode_inst_lift_pseudo(&dec); 5297 return format_inst(24, &dec); 5298 } 5299 5300 #define INST_FMT_2 "%04" PRIx64 " " 5301 #define INST_FMT_4 "%08" PRIx64 " " 5302 #define INST_FMT_6 "%012" PRIx64 " " 5303 #define INST_FMT_8 "%016" PRIx64 " " 5304 5305 static int 5306 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) 5307 { 5308 bfd_byte packet[2]; 5309 rv_inst inst = 0; 5310 size_t len = 2; 5311 bfd_vma n; 5312 int status; 5313 5314 /* Instructions are made of 2-byte packets in little-endian order */ 5315 for (n = 0; n < len; n += 2) { 5316 status = (*info->read_memory_func)(memaddr + n, packet, 2, info); 5317 if (status != 0) { 5318 /* Don't fail just because we fell off the end. */ 5319 if (n > 0) { 5320 break; 5321 } 5322 (*info->memory_error_func)(status, memaddr, info); 5323 return status; 5324 } 5325 inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n); 5326 if (n == 0) { 5327 len = inst_length(inst); 5328 } 5329 } 5330 5331 if (info->show_opcodes) { 5332 switch (len) { 5333 case 2: 5334 (*info->fprintf_func)(info->stream, INST_FMT_2, inst); 5335 break; 5336 case 4: 5337 (*info->fprintf_func)(info->stream, INST_FMT_4, inst); 5338 break; 5339 case 6: 5340 (*info->fprintf_func)(info->stream, INST_FMT_6, inst); 5341 break; 5342 default: 5343 (*info->fprintf_func)(info->stream, INST_FMT_8, inst); 5344 break; 5345 } 5346 } 5347 5348 g_autoptr(GString) str = 5349 disasm_inst(isa, memaddr, inst, (RISCVCPUConfig *)info->target_info); 5350 (*info->fprintf_func)(info->stream, "%s", str->str); 5351 5352 return len; 5353 } 5354 5355 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info) 5356 { 5357 return print_insn_riscv(memaddr, info, rv32); 5358 } 5359 5360 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info) 5361 { 5362 return print_insn_riscv(memaddr, info, rv64); 5363 } 5364 5365 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info) 5366 { 5367 return print_insn_riscv(memaddr, info, rv128); 5368 } 5369