1 /* 2 * QEMU RISC-V Disassembler 3 * 4 * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com> 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/bitops.h" 22 #include "disas/dis-asm.h" 23 #include "target/riscv/cpu_cfg.h" 24 #include "disas/riscv.h" 25 26 /* Vendor extensions */ 27 #include "disas/riscv-xthead.h" 28 #include "disas/riscv-xventana.h" 29 30 typedef enum { 31 /* 0 is reserved for rv_op_illegal. */ 32 rv_op_lui = 1, 33 rv_op_auipc = 2, 34 rv_op_jal = 3, 35 rv_op_jalr = 4, 36 rv_op_beq = 5, 37 rv_op_bne = 6, 38 rv_op_blt = 7, 39 rv_op_bge = 8, 40 rv_op_bltu = 9, 41 rv_op_bgeu = 10, 42 rv_op_lb = 11, 43 rv_op_lh = 12, 44 rv_op_lw = 13, 45 rv_op_lbu = 14, 46 rv_op_lhu = 15, 47 rv_op_sb = 16, 48 rv_op_sh = 17, 49 rv_op_sw = 18, 50 rv_op_addi = 19, 51 rv_op_slti = 20, 52 rv_op_sltiu = 21, 53 rv_op_xori = 22, 54 rv_op_ori = 23, 55 rv_op_andi = 24, 56 rv_op_slli = 25, 57 rv_op_srli = 26, 58 rv_op_srai = 27, 59 rv_op_add = 28, 60 rv_op_sub = 29, 61 rv_op_sll = 30, 62 rv_op_slt = 31, 63 rv_op_sltu = 32, 64 rv_op_xor = 33, 65 rv_op_srl = 34, 66 rv_op_sra = 35, 67 rv_op_or = 36, 68 rv_op_and = 37, 69 rv_op_fence = 38, 70 rv_op_fence_i = 39, 71 rv_op_lwu = 40, 72 rv_op_ld = 41, 73 rv_op_sd = 42, 74 rv_op_addiw = 43, 75 rv_op_slliw = 44, 76 rv_op_srliw = 45, 77 rv_op_sraiw = 46, 78 rv_op_addw = 47, 79 rv_op_subw = 48, 80 rv_op_sllw = 49, 81 rv_op_srlw = 50, 82 rv_op_sraw = 51, 83 rv_op_ldu = 52, 84 rv_op_lq = 53, 85 rv_op_sq = 54, 86 rv_op_addid = 55, 87 rv_op_sllid = 56, 88 rv_op_srlid = 57, 89 rv_op_sraid = 58, 90 rv_op_addd = 59, 91 rv_op_subd = 60, 92 rv_op_slld = 61, 93 rv_op_srld = 62, 94 rv_op_srad = 63, 95 rv_op_mul = 64, 96 rv_op_mulh = 65, 97 rv_op_mulhsu = 66, 98 rv_op_mulhu = 67, 99 rv_op_div = 68, 100 rv_op_divu = 69, 101 rv_op_rem = 70, 102 rv_op_remu = 71, 103 rv_op_mulw = 72, 104 rv_op_divw = 73, 105 rv_op_divuw = 74, 106 rv_op_remw = 75, 107 rv_op_remuw = 76, 108 rv_op_muld = 77, 109 rv_op_divd = 78, 110 rv_op_divud = 79, 111 rv_op_remd = 80, 112 rv_op_remud = 81, 113 rv_op_lr_w = 82, 114 rv_op_sc_w = 83, 115 rv_op_amoswap_w = 84, 116 rv_op_amoadd_w = 85, 117 rv_op_amoxor_w = 86, 118 rv_op_amoor_w = 87, 119 rv_op_amoand_w = 88, 120 rv_op_amomin_w = 89, 121 rv_op_amomax_w = 90, 122 rv_op_amominu_w = 91, 123 rv_op_amomaxu_w = 92, 124 rv_op_lr_d = 93, 125 rv_op_sc_d = 94, 126 rv_op_amoswap_d = 95, 127 rv_op_amoadd_d = 96, 128 rv_op_amoxor_d = 97, 129 rv_op_amoor_d = 98, 130 rv_op_amoand_d = 99, 131 rv_op_amomin_d = 100, 132 rv_op_amomax_d = 101, 133 rv_op_amominu_d = 102, 134 rv_op_amomaxu_d = 103, 135 rv_op_lr_q = 104, 136 rv_op_sc_q = 105, 137 rv_op_amoswap_q = 106, 138 rv_op_amoadd_q = 107, 139 rv_op_amoxor_q = 108, 140 rv_op_amoor_q = 109, 141 rv_op_amoand_q = 110, 142 rv_op_amomin_q = 111, 143 rv_op_amomax_q = 112, 144 rv_op_amominu_q = 113, 145 rv_op_amomaxu_q = 114, 146 rv_op_ecall = 115, 147 rv_op_ebreak = 116, 148 rv_op_uret = 117, 149 rv_op_sret = 118, 150 rv_op_hret = 119, 151 rv_op_mret = 120, 152 rv_op_dret = 121, 153 rv_op_sfence_vm = 122, 154 rv_op_sfence_vma = 123, 155 rv_op_wfi = 124, 156 rv_op_csrrw = 125, 157 rv_op_csrrs = 126, 158 rv_op_csrrc = 127, 159 rv_op_csrrwi = 128, 160 rv_op_csrrsi = 129, 161 rv_op_csrrci = 130, 162 rv_op_flw = 131, 163 rv_op_fsw = 132, 164 rv_op_fmadd_s = 133, 165 rv_op_fmsub_s = 134, 166 rv_op_fnmsub_s = 135, 167 rv_op_fnmadd_s = 136, 168 rv_op_fadd_s = 137, 169 rv_op_fsub_s = 138, 170 rv_op_fmul_s = 139, 171 rv_op_fdiv_s = 140, 172 rv_op_fsgnj_s = 141, 173 rv_op_fsgnjn_s = 142, 174 rv_op_fsgnjx_s = 143, 175 rv_op_fmin_s = 144, 176 rv_op_fmax_s = 145, 177 rv_op_fsqrt_s = 146, 178 rv_op_fle_s = 147, 179 rv_op_flt_s = 148, 180 rv_op_feq_s = 149, 181 rv_op_fcvt_w_s = 150, 182 rv_op_fcvt_wu_s = 151, 183 rv_op_fcvt_s_w = 152, 184 rv_op_fcvt_s_wu = 153, 185 rv_op_fmv_x_s = 154, 186 rv_op_fclass_s = 155, 187 rv_op_fmv_s_x = 156, 188 rv_op_fcvt_l_s = 157, 189 rv_op_fcvt_lu_s = 158, 190 rv_op_fcvt_s_l = 159, 191 rv_op_fcvt_s_lu = 160, 192 rv_op_fld = 161, 193 rv_op_fsd = 162, 194 rv_op_fmadd_d = 163, 195 rv_op_fmsub_d = 164, 196 rv_op_fnmsub_d = 165, 197 rv_op_fnmadd_d = 166, 198 rv_op_fadd_d = 167, 199 rv_op_fsub_d = 168, 200 rv_op_fmul_d = 169, 201 rv_op_fdiv_d = 170, 202 rv_op_fsgnj_d = 171, 203 rv_op_fsgnjn_d = 172, 204 rv_op_fsgnjx_d = 173, 205 rv_op_fmin_d = 174, 206 rv_op_fmax_d = 175, 207 rv_op_fcvt_s_d = 176, 208 rv_op_fcvt_d_s = 177, 209 rv_op_fsqrt_d = 178, 210 rv_op_fle_d = 179, 211 rv_op_flt_d = 180, 212 rv_op_feq_d = 181, 213 rv_op_fcvt_w_d = 182, 214 rv_op_fcvt_wu_d = 183, 215 rv_op_fcvt_d_w = 184, 216 rv_op_fcvt_d_wu = 185, 217 rv_op_fclass_d = 186, 218 rv_op_fcvt_l_d = 187, 219 rv_op_fcvt_lu_d = 188, 220 rv_op_fmv_x_d = 189, 221 rv_op_fcvt_d_l = 190, 222 rv_op_fcvt_d_lu = 191, 223 rv_op_fmv_d_x = 192, 224 rv_op_flq = 193, 225 rv_op_fsq = 194, 226 rv_op_fmadd_q = 195, 227 rv_op_fmsub_q = 196, 228 rv_op_fnmsub_q = 197, 229 rv_op_fnmadd_q = 198, 230 rv_op_fadd_q = 199, 231 rv_op_fsub_q = 200, 232 rv_op_fmul_q = 201, 233 rv_op_fdiv_q = 202, 234 rv_op_fsgnj_q = 203, 235 rv_op_fsgnjn_q = 204, 236 rv_op_fsgnjx_q = 205, 237 rv_op_fmin_q = 206, 238 rv_op_fmax_q = 207, 239 rv_op_fcvt_s_q = 208, 240 rv_op_fcvt_q_s = 209, 241 rv_op_fcvt_d_q = 210, 242 rv_op_fcvt_q_d = 211, 243 rv_op_fsqrt_q = 212, 244 rv_op_fle_q = 213, 245 rv_op_flt_q = 214, 246 rv_op_feq_q = 215, 247 rv_op_fcvt_w_q = 216, 248 rv_op_fcvt_wu_q = 217, 249 rv_op_fcvt_q_w = 218, 250 rv_op_fcvt_q_wu = 219, 251 rv_op_fclass_q = 220, 252 rv_op_fcvt_l_q = 221, 253 rv_op_fcvt_lu_q = 222, 254 rv_op_fcvt_q_l = 223, 255 rv_op_fcvt_q_lu = 224, 256 rv_op_fmv_x_q = 225, 257 rv_op_fmv_q_x = 226, 258 rv_op_c_addi4spn = 227, 259 rv_op_c_fld = 228, 260 rv_op_c_lw = 229, 261 rv_op_c_flw = 230, 262 rv_op_c_fsd = 231, 263 rv_op_c_sw = 232, 264 rv_op_c_fsw = 233, 265 rv_op_c_nop = 234, 266 rv_op_c_addi = 235, 267 rv_op_c_jal = 236, 268 rv_op_c_li = 237, 269 rv_op_c_addi16sp = 238, 270 rv_op_c_lui = 239, 271 rv_op_c_srli = 240, 272 rv_op_c_srai = 241, 273 rv_op_c_andi = 242, 274 rv_op_c_sub = 243, 275 rv_op_c_xor = 244, 276 rv_op_c_or = 245, 277 rv_op_c_and = 246, 278 rv_op_c_subw = 247, 279 rv_op_c_addw = 248, 280 rv_op_c_j = 249, 281 rv_op_c_beqz = 250, 282 rv_op_c_bnez = 251, 283 rv_op_c_slli = 252, 284 rv_op_c_fldsp = 253, 285 rv_op_c_lwsp = 254, 286 rv_op_c_flwsp = 255, 287 rv_op_c_jr = 256, 288 rv_op_c_mv = 257, 289 rv_op_c_ebreak = 258, 290 rv_op_c_jalr = 259, 291 rv_op_c_add = 260, 292 rv_op_c_fsdsp = 261, 293 rv_op_c_swsp = 262, 294 rv_op_c_fswsp = 263, 295 rv_op_c_ld = 264, 296 rv_op_c_sd = 265, 297 rv_op_c_addiw = 266, 298 rv_op_c_ldsp = 267, 299 rv_op_c_sdsp = 268, 300 rv_op_c_lq = 269, 301 rv_op_c_sq = 270, 302 rv_op_c_lqsp = 271, 303 rv_op_c_sqsp = 272, 304 rv_op_nop = 273, 305 rv_op_mv = 274, 306 rv_op_not = 275, 307 rv_op_neg = 276, 308 rv_op_negw = 277, 309 rv_op_sext_w = 278, 310 rv_op_seqz = 279, 311 rv_op_snez = 280, 312 rv_op_sltz = 281, 313 rv_op_sgtz = 282, 314 rv_op_fmv_s = 283, 315 rv_op_fabs_s = 284, 316 rv_op_fneg_s = 285, 317 rv_op_fmv_d = 286, 318 rv_op_fabs_d = 287, 319 rv_op_fneg_d = 288, 320 rv_op_fmv_q = 289, 321 rv_op_fabs_q = 290, 322 rv_op_fneg_q = 291, 323 rv_op_beqz = 292, 324 rv_op_bnez = 293, 325 rv_op_blez = 294, 326 rv_op_bgez = 295, 327 rv_op_bltz = 296, 328 rv_op_bgtz = 297, 329 rv_op_ble = 298, 330 rv_op_bleu = 299, 331 rv_op_bgt = 300, 332 rv_op_bgtu = 301, 333 rv_op_j = 302, 334 rv_op_ret = 303, 335 rv_op_jr = 304, 336 rv_op_rdcycle = 305, 337 rv_op_rdtime = 306, 338 rv_op_rdinstret = 307, 339 rv_op_rdcycleh = 308, 340 rv_op_rdtimeh = 309, 341 rv_op_rdinstreth = 310, 342 rv_op_frcsr = 311, 343 rv_op_frrm = 312, 344 rv_op_frflags = 313, 345 rv_op_fscsr = 314, 346 rv_op_fsrm = 315, 347 rv_op_fsflags = 316, 348 rv_op_fsrmi = 317, 349 rv_op_fsflagsi = 318, 350 rv_op_bseti = 319, 351 rv_op_bclri = 320, 352 rv_op_binvi = 321, 353 rv_op_bexti = 322, 354 rv_op_rori = 323, 355 rv_op_clz = 324, 356 rv_op_ctz = 325, 357 rv_op_cpop = 326, 358 rv_op_sext_h = 327, 359 rv_op_sext_b = 328, 360 rv_op_xnor = 329, 361 rv_op_orn = 330, 362 rv_op_andn = 331, 363 rv_op_rol = 332, 364 rv_op_ror = 333, 365 rv_op_sh1add = 334, 366 rv_op_sh2add = 335, 367 rv_op_sh3add = 336, 368 rv_op_sh1add_uw = 337, 369 rv_op_sh2add_uw = 338, 370 rv_op_sh3add_uw = 339, 371 rv_op_clmul = 340, 372 rv_op_clmulr = 341, 373 rv_op_clmulh = 342, 374 rv_op_min = 343, 375 rv_op_minu = 344, 376 rv_op_max = 345, 377 rv_op_maxu = 346, 378 rv_op_clzw = 347, 379 rv_op_ctzw = 348, 380 rv_op_cpopw = 349, 381 rv_op_slli_uw = 350, 382 rv_op_add_uw = 351, 383 rv_op_rolw = 352, 384 rv_op_rorw = 353, 385 rv_op_rev8 = 354, 386 rv_op_zext_h = 355, 387 rv_op_roriw = 356, 388 rv_op_orc_b = 357, 389 rv_op_bset = 358, 390 rv_op_bclr = 359, 391 rv_op_binv = 360, 392 rv_op_bext = 361, 393 rv_op_aes32esmi = 362, 394 rv_op_aes32esi = 363, 395 rv_op_aes32dsmi = 364, 396 rv_op_aes32dsi = 365, 397 rv_op_aes64ks1i = 366, 398 rv_op_aes64ks2 = 367, 399 rv_op_aes64im = 368, 400 rv_op_aes64esm = 369, 401 rv_op_aes64es = 370, 402 rv_op_aes64dsm = 371, 403 rv_op_aes64ds = 372, 404 rv_op_sha256sig0 = 373, 405 rv_op_sha256sig1 = 374, 406 rv_op_sha256sum0 = 375, 407 rv_op_sha256sum1 = 376, 408 rv_op_sha512sig0 = 377, 409 rv_op_sha512sig1 = 378, 410 rv_op_sha512sum0 = 379, 411 rv_op_sha512sum1 = 380, 412 rv_op_sha512sum0r = 381, 413 rv_op_sha512sum1r = 382, 414 rv_op_sha512sig0l = 383, 415 rv_op_sha512sig0h = 384, 416 rv_op_sha512sig1l = 385, 417 rv_op_sha512sig1h = 386, 418 rv_op_sm3p0 = 387, 419 rv_op_sm3p1 = 388, 420 rv_op_sm4ed = 389, 421 rv_op_sm4ks = 390, 422 rv_op_brev8 = 391, 423 rv_op_pack = 392, 424 rv_op_packh = 393, 425 rv_op_packw = 394, 426 rv_op_unzip = 395, 427 rv_op_zip = 396, 428 rv_op_xperm4 = 397, 429 rv_op_xperm8 = 398, 430 rv_op_vle8_v = 399, 431 rv_op_vle16_v = 400, 432 rv_op_vle32_v = 401, 433 rv_op_vle64_v = 402, 434 rv_op_vse8_v = 403, 435 rv_op_vse16_v = 404, 436 rv_op_vse32_v = 405, 437 rv_op_vse64_v = 406, 438 rv_op_vlm_v = 407, 439 rv_op_vsm_v = 408, 440 rv_op_vlse8_v = 409, 441 rv_op_vlse16_v = 410, 442 rv_op_vlse32_v = 411, 443 rv_op_vlse64_v = 412, 444 rv_op_vsse8_v = 413, 445 rv_op_vsse16_v = 414, 446 rv_op_vsse32_v = 415, 447 rv_op_vsse64_v = 416, 448 rv_op_vluxei8_v = 417, 449 rv_op_vluxei16_v = 418, 450 rv_op_vluxei32_v = 419, 451 rv_op_vluxei64_v = 420, 452 rv_op_vloxei8_v = 421, 453 rv_op_vloxei16_v = 422, 454 rv_op_vloxei32_v = 423, 455 rv_op_vloxei64_v = 424, 456 rv_op_vsuxei8_v = 425, 457 rv_op_vsuxei16_v = 426, 458 rv_op_vsuxei32_v = 427, 459 rv_op_vsuxei64_v = 428, 460 rv_op_vsoxei8_v = 429, 461 rv_op_vsoxei16_v = 430, 462 rv_op_vsoxei32_v = 431, 463 rv_op_vsoxei64_v = 432, 464 rv_op_vle8ff_v = 433, 465 rv_op_vle16ff_v = 434, 466 rv_op_vle32ff_v = 435, 467 rv_op_vle64ff_v = 436, 468 rv_op_vl1re8_v = 437, 469 rv_op_vl1re16_v = 438, 470 rv_op_vl1re32_v = 439, 471 rv_op_vl1re64_v = 440, 472 rv_op_vl2re8_v = 441, 473 rv_op_vl2re16_v = 442, 474 rv_op_vl2re32_v = 443, 475 rv_op_vl2re64_v = 444, 476 rv_op_vl4re8_v = 445, 477 rv_op_vl4re16_v = 446, 478 rv_op_vl4re32_v = 447, 479 rv_op_vl4re64_v = 448, 480 rv_op_vl8re8_v = 449, 481 rv_op_vl8re16_v = 450, 482 rv_op_vl8re32_v = 451, 483 rv_op_vl8re64_v = 452, 484 rv_op_vs1r_v = 453, 485 rv_op_vs2r_v = 454, 486 rv_op_vs4r_v = 455, 487 rv_op_vs8r_v = 456, 488 rv_op_vadd_vv = 457, 489 rv_op_vadd_vx = 458, 490 rv_op_vadd_vi = 459, 491 rv_op_vsub_vv = 460, 492 rv_op_vsub_vx = 461, 493 rv_op_vrsub_vx = 462, 494 rv_op_vrsub_vi = 463, 495 rv_op_vwaddu_vv = 464, 496 rv_op_vwaddu_vx = 465, 497 rv_op_vwadd_vv = 466, 498 rv_op_vwadd_vx = 467, 499 rv_op_vwsubu_vv = 468, 500 rv_op_vwsubu_vx = 469, 501 rv_op_vwsub_vv = 470, 502 rv_op_vwsub_vx = 471, 503 rv_op_vwaddu_wv = 472, 504 rv_op_vwaddu_wx = 473, 505 rv_op_vwadd_wv = 474, 506 rv_op_vwadd_wx = 475, 507 rv_op_vwsubu_wv = 476, 508 rv_op_vwsubu_wx = 477, 509 rv_op_vwsub_wv = 478, 510 rv_op_vwsub_wx = 479, 511 rv_op_vadc_vvm = 480, 512 rv_op_vadc_vxm = 481, 513 rv_op_vadc_vim = 482, 514 rv_op_vmadc_vvm = 483, 515 rv_op_vmadc_vxm = 484, 516 rv_op_vmadc_vim = 485, 517 rv_op_vsbc_vvm = 486, 518 rv_op_vsbc_vxm = 487, 519 rv_op_vmsbc_vvm = 488, 520 rv_op_vmsbc_vxm = 489, 521 rv_op_vand_vv = 490, 522 rv_op_vand_vx = 491, 523 rv_op_vand_vi = 492, 524 rv_op_vor_vv = 493, 525 rv_op_vor_vx = 494, 526 rv_op_vor_vi = 495, 527 rv_op_vxor_vv = 496, 528 rv_op_vxor_vx = 497, 529 rv_op_vxor_vi = 498, 530 rv_op_vsll_vv = 499, 531 rv_op_vsll_vx = 500, 532 rv_op_vsll_vi = 501, 533 rv_op_vsrl_vv = 502, 534 rv_op_vsrl_vx = 503, 535 rv_op_vsrl_vi = 504, 536 rv_op_vsra_vv = 505, 537 rv_op_vsra_vx = 506, 538 rv_op_vsra_vi = 507, 539 rv_op_vnsrl_wv = 508, 540 rv_op_vnsrl_wx = 509, 541 rv_op_vnsrl_wi = 510, 542 rv_op_vnsra_wv = 511, 543 rv_op_vnsra_wx = 512, 544 rv_op_vnsra_wi = 513, 545 rv_op_vmseq_vv = 514, 546 rv_op_vmseq_vx = 515, 547 rv_op_vmseq_vi = 516, 548 rv_op_vmsne_vv = 517, 549 rv_op_vmsne_vx = 518, 550 rv_op_vmsne_vi = 519, 551 rv_op_vmsltu_vv = 520, 552 rv_op_vmsltu_vx = 521, 553 rv_op_vmslt_vv = 522, 554 rv_op_vmslt_vx = 523, 555 rv_op_vmsleu_vv = 524, 556 rv_op_vmsleu_vx = 525, 557 rv_op_vmsleu_vi = 526, 558 rv_op_vmsle_vv = 527, 559 rv_op_vmsle_vx = 528, 560 rv_op_vmsle_vi = 529, 561 rv_op_vmsgtu_vx = 530, 562 rv_op_vmsgtu_vi = 531, 563 rv_op_vmsgt_vx = 532, 564 rv_op_vmsgt_vi = 533, 565 rv_op_vminu_vv = 534, 566 rv_op_vminu_vx = 535, 567 rv_op_vmin_vv = 536, 568 rv_op_vmin_vx = 537, 569 rv_op_vmaxu_vv = 538, 570 rv_op_vmaxu_vx = 539, 571 rv_op_vmax_vv = 540, 572 rv_op_vmax_vx = 541, 573 rv_op_vmul_vv = 542, 574 rv_op_vmul_vx = 543, 575 rv_op_vmulh_vv = 544, 576 rv_op_vmulh_vx = 545, 577 rv_op_vmulhu_vv = 546, 578 rv_op_vmulhu_vx = 547, 579 rv_op_vmulhsu_vv = 548, 580 rv_op_vmulhsu_vx = 549, 581 rv_op_vdivu_vv = 550, 582 rv_op_vdivu_vx = 551, 583 rv_op_vdiv_vv = 552, 584 rv_op_vdiv_vx = 553, 585 rv_op_vremu_vv = 554, 586 rv_op_vremu_vx = 555, 587 rv_op_vrem_vv = 556, 588 rv_op_vrem_vx = 557, 589 rv_op_vwmulu_vv = 558, 590 rv_op_vwmulu_vx = 559, 591 rv_op_vwmulsu_vv = 560, 592 rv_op_vwmulsu_vx = 561, 593 rv_op_vwmul_vv = 562, 594 rv_op_vwmul_vx = 563, 595 rv_op_vmacc_vv = 564, 596 rv_op_vmacc_vx = 565, 597 rv_op_vnmsac_vv = 566, 598 rv_op_vnmsac_vx = 567, 599 rv_op_vmadd_vv = 568, 600 rv_op_vmadd_vx = 569, 601 rv_op_vnmsub_vv = 570, 602 rv_op_vnmsub_vx = 571, 603 rv_op_vwmaccu_vv = 572, 604 rv_op_vwmaccu_vx = 573, 605 rv_op_vwmacc_vv = 574, 606 rv_op_vwmacc_vx = 575, 607 rv_op_vwmaccsu_vv = 576, 608 rv_op_vwmaccsu_vx = 577, 609 rv_op_vwmaccus_vx = 578, 610 rv_op_vmv_v_v = 579, 611 rv_op_vmv_v_x = 580, 612 rv_op_vmv_v_i = 581, 613 rv_op_vmerge_vvm = 582, 614 rv_op_vmerge_vxm = 583, 615 rv_op_vmerge_vim = 584, 616 rv_op_vsaddu_vv = 585, 617 rv_op_vsaddu_vx = 586, 618 rv_op_vsaddu_vi = 587, 619 rv_op_vsadd_vv = 588, 620 rv_op_vsadd_vx = 589, 621 rv_op_vsadd_vi = 590, 622 rv_op_vssubu_vv = 591, 623 rv_op_vssubu_vx = 592, 624 rv_op_vssub_vv = 593, 625 rv_op_vssub_vx = 594, 626 rv_op_vaadd_vv = 595, 627 rv_op_vaadd_vx = 596, 628 rv_op_vaaddu_vv = 597, 629 rv_op_vaaddu_vx = 598, 630 rv_op_vasub_vv = 599, 631 rv_op_vasub_vx = 600, 632 rv_op_vasubu_vv = 601, 633 rv_op_vasubu_vx = 602, 634 rv_op_vsmul_vv = 603, 635 rv_op_vsmul_vx = 604, 636 rv_op_vssrl_vv = 605, 637 rv_op_vssrl_vx = 606, 638 rv_op_vssrl_vi = 607, 639 rv_op_vssra_vv = 608, 640 rv_op_vssra_vx = 609, 641 rv_op_vssra_vi = 610, 642 rv_op_vnclipu_wv = 611, 643 rv_op_vnclipu_wx = 612, 644 rv_op_vnclipu_wi = 613, 645 rv_op_vnclip_wv = 614, 646 rv_op_vnclip_wx = 615, 647 rv_op_vnclip_wi = 616, 648 rv_op_vfadd_vv = 617, 649 rv_op_vfadd_vf = 618, 650 rv_op_vfsub_vv = 619, 651 rv_op_vfsub_vf = 620, 652 rv_op_vfrsub_vf = 621, 653 rv_op_vfwadd_vv = 622, 654 rv_op_vfwadd_vf = 623, 655 rv_op_vfwadd_wv = 624, 656 rv_op_vfwadd_wf = 625, 657 rv_op_vfwsub_vv = 626, 658 rv_op_vfwsub_vf = 627, 659 rv_op_vfwsub_wv = 628, 660 rv_op_vfwsub_wf = 629, 661 rv_op_vfmul_vv = 630, 662 rv_op_vfmul_vf = 631, 663 rv_op_vfdiv_vv = 632, 664 rv_op_vfdiv_vf = 633, 665 rv_op_vfrdiv_vf = 634, 666 rv_op_vfwmul_vv = 635, 667 rv_op_vfwmul_vf = 636, 668 rv_op_vfmacc_vv = 637, 669 rv_op_vfmacc_vf = 638, 670 rv_op_vfnmacc_vv = 639, 671 rv_op_vfnmacc_vf = 640, 672 rv_op_vfmsac_vv = 641, 673 rv_op_vfmsac_vf = 642, 674 rv_op_vfnmsac_vv = 643, 675 rv_op_vfnmsac_vf = 644, 676 rv_op_vfmadd_vv = 645, 677 rv_op_vfmadd_vf = 646, 678 rv_op_vfnmadd_vv = 647, 679 rv_op_vfnmadd_vf = 648, 680 rv_op_vfmsub_vv = 649, 681 rv_op_vfmsub_vf = 650, 682 rv_op_vfnmsub_vv = 651, 683 rv_op_vfnmsub_vf = 652, 684 rv_op_vfwmacc_vv = 653, 685 rv_op_vfwmacc_vf = 654, 686 rv_op_vfwnmacc_vv = 655, 687 rv_op_vfwnmacc_vf = 656, 688 rv_op_vfwmsac_vv = 657, 689 rv_op_vfwmsac_vf = 658, 690 rv_op_vfwnmsac_vv = 659, 691 rv_op_vfwnmsac_vf = 660, 692 rv_op_vfsqrt_v = 661, 693 rv_op_vfrsqrt7_v = 662, 694 rv_op_vfrec7_v = 663, 695 rv_op_vfmin_vv = 664, 696 rv_op_vfmin_vf = 665, 697 rv_op_vfmax_vv = 666, 698 rv_op_vfmax_vf = 667, 699 rv_op_vfsgnj_vv = 668, 700 rv_op_vfsgnj_vf = 669, 701 rv_op_vfsgnjn_vv = 670, 702 rv_op_vfsgnjn_vf = 671, 703 rv_op_vfsgnjx_vv = 672, 704 rv_op_vfsgnjx_vf = 673, 705 rv_op_vfslide1up_vf = 674, 706 rv_op_vfslide1down_vf = 675, 707 rv_op_vmfeq_vv = 676, 708 rv_op_vmfeq_vf = 677, 709 rv_op_vmfne_vv = 678, 710 rv_op_vmfne_vf = 679, 711 rv_op_vmflt_vv = 680, 712 rv_op_vmflt_vf = 681, 713 rv_op_vmfle_vv = 682, 714 rv_op_vmfle_vf = 683, 715 rv_op_vmfgt_vf = 684, 716 rv_op_vmfge_vf = 685, 717 rv_op_vfclass_v = 686, 718 rv_op_vfmerge_vfm = 687, 719 rv_op_vfmv_v_f = 688, 720 rv_op_vfcvt_xu_f_v = 689, 721 rv_op_vfcvt_x_f_v = 690, 722 rv_op_vfcvt_f_xu_v = 691, 723 rv_op_vfcvt_f_x_v = 692, 724 rv_op_vfcvt_rtz_xu_f_v = 693, 725 rv_op_vfcvt_rtz_x_f_v = 694, 726 rv_op_vfwcvt_xu_f_v = 695, 727 rv_op_vfwcvt_x_f_v = 696, 728 rv_op_vfwcvt_f_xu_v = 697, 729 rv_op_vfwcvt_f_x_v = 698, 730 rv_op_vfwcvt_f_f_v = 699, 731 rv_op_vfwcvt_rtz_xu_f_v = 700, 732 rv_op_vfwcvt_rtz_x_f_v = 701, 733 rv_op_vfncvt_xu_f_w = 702, 734 rv_op_vfncvt_x_f_w = 703, 735 rv_op_vfncvt_f_xu_w = 704, 736 rv_op_vfncvt_f_x_w = 705, 737 rv_op_vfncvt_f_f_w = 706, 738 rv_op_vfncvt_rod_f_f_w = 707, 739 rv_op_vfncvt_rtz_xu_f_w = 708, 740 rv_op_vfncvt_rtz_x_f_w = 709, 741 rv_op_vredsum_vs = 710, 742 rv_op_vredand_vs = 711, 743 rv_op_vredor_vs = 712, 744 rv_op_vredxor_vs = 713, 745 rv_op_vredminu_vs = 714, 746 rv_op_vredmin_vs = 715, 747 rv_op_vredmaxu_vs = 716, 748 rv_op_vredmax_vs = 717, 749 rv_op_vwredsumu_vs = 718, 750 rv_op_vwredsum_vs = 719, 751 rv_op_vfredusum_vs = 720, 752 rv_op_vfredosum_vs = 721, 753 rv_op_vfredmin_vs = 722, 754 rv_op_vfredmax_vs = 723, 755 rv_op_vfwredusum_vs = 724, 756 rv_op_vfwredosum_vs = 725, 757 rv_op_vmand_mm = 726, 758 rv_op_vmnand_mm = 727, 759 rv_op_vmandn_mm = 728, 760 rv_op_vmxor_mm = 729, 761 rv_op_vmor_mm = 730, 762 rv_op_vmnor_mm = 731, 763 rv_op_vmorn_mm = 732, 764 rv_op_vmxnor_mm = 733, 765 rv_op_vcpop_m = 734, 766 rv_op_vfirst_m = 735, 767 rv_op_vmsbf_m = 736, 768 rv_op_vmsif_m = 737, 769 rv_op_vmsof_m = 738, 770 rv_op_viota_m = 739, 771 rv_op_vid_v = 740, 772 rv_op_vmv_x_s = 741, 773 rv_op_vmv_s_x = 742, 774 rv_op_vfmv_f_s = 743, 775 rv_op_vfmv_s_f = 744, 776 rv_op_vslideup_vx = 745, 777 rv_op_vslideup_vi = 746, 778 rv_op_vslide1up_vx = 747, 779 rv_op_vslidedown_vx = 748, 780 rv_op_vslidedown_vi = 749, 781 rv_op_vslide1down_vx = 750, 782 rv_op_vrgather_vv = 751, 783 rv_op_vrgatherei16_vv = 752, 784 rv_op_vrgather_vx = 753, 785 rv_op_vrgather_vi = 754, 786 rv_op_vcompress_vm = 755, 787 rv_op_vmv1r_v = 756, 788 rv_op_vmv2r_v = 757, 789 rv_op_vmv4r_v = 758, 790 rv_op_vmv8r_v = 759, 791 rv_op_vzext_vf2 = 760, 792 rv_op_vzext_vf4 = 761, 793 rv_op_vzext_vf8 = 762, 794 rv_op_vsext_vf2 = 763, 795 rv_op_vsext_vf4 = 764, 796 rv_op_vsext_vf8 = 765, 797 rv_op_vsetvli = 766, 798 rv_op_vsetivli = 767, 799 rv_op_vsetvl = 768, 800 rv_op_c_zext_b = 769, 801 rv_op_c_sext_b = 770, 802 rv_op_c_zext_h = 771, 803 rv_op_c_sext_h = 772, 804 rv_op_c_zext_w = 773, 805 rv_op_c_not = 774, 806 rv_op_c_mul = 775, 807 rv_op_c_lbu = 776, 808 rv_op_c_lhu = 777, 809 rv_op_c_lh = 778, 810 rv_op_c_sb = 779, 811 rv_op_c_sh = 780, 812 rv_op_cm_push = 781, 813 rv_op_cm_pop = 782, 814 rv_op_cm_popret = 783, 815 rv_op_cm_popretz = 784, 816 rv_op_cm_mva01s = 785, 817 rv_op_cm_mvsa01 = 786, 818 rv_op_cm_jt = 787, 819 rv_op_cm_jalt = 788, 820 rv_op_czero_eqz = 789, 821 rv_op_czero_nez = 790, 822 rv_op_fcvt_bf16_s = 791, 823 rv_op_fcvt_s_bf16 = 792, 824 rv_op_vfncvtbf16_f_f_w = 793, 825 rv_op_vfwcvtbf16_f_f_v = 794, 826 rv_op_vfwmaccbf16_vv = 795, 827 rv_op_vfwmaccbf16_vf = 796, 828 rv_op_flh = 797, 829 rv_op_fsh = 798, 830 rv_op_fmv_h_x = 799, 831 rv_op_fmv_x_h = 800, 832 rv_op_fli_s = 801, 833 rv_op_fli_d = 802, 834 rv_op_fli_q = 803, 835 rv_op_fli_h = 804, 836 rv_op_fminm_s = 805, 837 rv_op_fmaxm_s = 806, 838 rv_op_fminm_d = 807, 839 rv_op_fmaxm_d = 808, 840 rv_op_fminm_q = 809, 841 rv_op_fmaxm_q = 810, 842 rv_op_fminm_h = 811, 843 rv_op_fmaxm_h = 812, 844 rv_op_fround_s = 813, 845 rv_op_froundnx_s = 814, 846 rv_op_fround_d = 815, 847 rv_op_froundnx_d = 816, 848 rv_op_fround_q = 817, 849 rv_op_froundnx_q = 818, 850 rv_op_fround_h = 819, 851 rv_op_froundnx_h = 820, 852 rv_op_fcvtmod_w_d = 821, 853 rv_op_fmvh_x_d = 822, 854 rv_op_fmvp_d_x = 823, 855 rv_op_fmvh_x_q = 824, 856 rv_op_fmvp_q_x = 825, 857 rv_op_fleq_s = 826, 858 rv_op_fltq_s = 827, 859 rv_op_fleq_d = 828, 860 rv_op_fltq_d = 829, 861 rv_op_fleq_q = 830, 862 rv_op_fltq_q = 831, 863 rv_op_fleq_h = 832, 864 rv_op_fltq_h = 833, 865 rv_op_vaesdf_vv = 834, 866 rv_op_vaesdf_vs = 835, 867 rv_op_vaesdm_vv = 836, 868 rv_op_vaesdm_vs = 837, 869 rv_op_vaesef_vv = 838, 870 rv_op_vaesef_vs = 839, 871 rv_op_vaesem_vv = 840, 872 rv_op_vaesem_vs = 841, 873 rv_op_vaeskf1_vi = 842, 874 rv_op_vaeskf2_vi = 843, 875 rv_op_vaesz_vs = 844, 876 rv_op_vandn_vv = 845, 877 rv_op_vandn_vx = 846, 878 rv_op_vbrev_v = 847, 879 rv_op_vbrev8_v = 848, 880 rv_op_vclmul_vv = 849, 881 rv_op_vclmul_vx = 850, 882 rv_op_vclmulh_vv = 851, 883 rv_op_vclmulh_vx = 852, 884 rv_op_vclz_v = 853, 885 rv_op_vcpop_v = 854, 886 rv_op_vctz_v = 855, 887 rv_op_vghsh_vv = 856, 888 rv_op_vgmul_vv = 857, 889 rv_op_vrev8_v = 858, 890 rv_op_vrol_vv = 859, 891 rv_op_vrol_vx = 860, 892 rv_op_vror_vv = 861, 893 rv_op_vror_vx = 862, 894 rv_op_vror_vi = 863, 895 rv_op_vsha2ch_vv = 864, 896 rv_op_vsha2cl_vv = 865, 897 rv_op_vsha2ms_vv = 866, 898 rv_op_vsm3c_vi = 867, 899 rv_op_vsm3me_vv = 868, 900 rv_op_vsm4k_vi = 869, 901 rv_op_vsm4r_vv = 870, 902 rv_op_vsm4r_vs = 871, 903 rv_op_vwsll_vv = 872, 904 rv_op_vwsll_vx = 873, 905 rv_op_vwsll_vi = 874, 906 rv_op_amocas_w = 875, 907 rv_op_amocas_d = 876, 908 rv_op_amocas_q = 877, 909 rv_mop_r_0 = 878, 910 rv_mop_r_1 = 879, 911 rv_mop_r_2 = 880, 912 rv_mop_r_3 = 881, 913 rv_mop_r_4 = 882, 914 rv_mop_r_5 = 883, 915 rv_mop_r_6 = 884, 916 rv_mop_r_7 = 885, 917 rv_mop_r_8 = 886, 918 rv_mop_r_9 = 887, 919 rv_mop_r_10 = 888, 920 rv_mop_r_11 = 889, 921 rv_mop_r_12 = 890, 922 rv_mop_r_13 = 891, 923 rv_mop_r_14 = 892, 924 rv_mop_r_15 = 893, 925 rv_mop_r_16 = 894, 926 rv_mop_r_17 = 895, 927 rv_mop_r_18 = 896, 928 rv_mop_r_19 = 897, 929 rv_mop_r_20 = 898, 930 rv_mop_r_21 = 899, 931 rv_mop_r_22 = 900, 932 rv_mop_r_23 = 901, 933 rv_mop_r_24 = 902, 934 rv_mop_r_25 = 903, 935 rv_mop_r_26 = 904, 936 rv_mop_r_27 = 905, 937 rv_mop_r_28 = 906, 938 rv_mop_r_29 = 907, 939 rv_mop_r_30 = 908, 940 rv_mop_r_31 = 909, 941 rv_mop_rr_0 = 910, 942 rv_mop_rr_1 = 911, 943 rv_mop_rr_2 = 912, 944 rv_mop_rr_3 = 913, 945 rv_mop_rr_4 = 914, 946 rv_mop_rr_5 = 915, 947 rv_mop_rr_6 = 916, 948 rv_mop_rr_7 = 917, 949 rv_c_mop_1 = 918, 950 rv_c_mop_3 = 919, 951 rv_c_mop_5 = 920, 952 rv_c_mop_7 = 921, 953 rv_c_mop_9 = 922, 954 rv_c_mop_11 = 923, 955 rv_c_mop_13 = 924, 956 rv_c_mop_15 = 925, 957 rv_op_amoswap_b = 926, 958 rv_op_amoadd_b = 927, 959 rv_op_amoxor_b = 928, 960 rv_op_amoor_b = 929, 961 rv_op_amoand_b = 930, 962 rv_op_amomin_b = 931, 963 rv_op_amomax_b = 932, 964 rv_op_amominu_b = 933, 965 rv_op_amomaxu_b = 934, 966 rv_op_amoswap_h = 935, 967 rv_op_amoadd_h = 936, 968 rv_op_amoxor_h = 937, 969 rv_op_amoor_h = 938, 970 rv_op_amoand_h = 939, 971 rv_op_amomin_h = 940, 972 rv_op_amomax_h = 941, 973 rv_op_amominu_h = 942, 974 rv_op_amomaxu_h = 943, 975 rv_op_amocas_b = 944, 976 rv_op_amocas_h = 945, 977 } rv_op; 978 979 /* register names */ 980 981 static const char rv_ireg_name_sym[32][5] = { 982 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 983 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 984 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 985 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", 986 }; 987 988 static const char rv_freg_name_sym[32][5] = { 989 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", 990 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", 991 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", 992 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11", 993 }; 994 995 static const char rv_vreg_name_sym[32][4] = { 996 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 997 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 998 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 999 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 1000 }; 1001 1002 /* The FLI.[HSDQ] numeric constants (0.0 for symbolic constants). 1003 * The constants use the hex floating-point literal representation 1004 * that is printed when using the printf %a format specifier, 1005 * which matches the output that is generated by the disassembler. 1006 */ 1007 static const char rv_fli_name_const[32][9] = 1008 { 1009 "0x1p+0", "min", "0x1p-16", "0x1p-15", 1010 "0x1p-8", "0x1p-7", "0x1p-4", "0x1p-3", 1011 "0x1p-2", "0x1.4p-2", "0x1.8p-2", "0x1.cp-2", 1012 "0x1p-1", "0x1.4p-1", "0x1.8p-1", "0x1.cp-1", 1013 "0x1p+0", "0x1.4p+0", "0x1.8p+0", "0x1.cp+0", 1014 "0x1p+1", "0x1.4p+1", "0x1.8p+1", "0x1p+2", 1015 "0x1p+3", "0x1p+4", "0x1p+7", "0x1p+8", 1016 "0x1p+15", "0x1p+16", "inf", "nan" 1017 }; 1018 1019 /* pseudo-instruction constraints */ 1020 1021 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end }; 1022 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, 1023 rvc_end }; 1024 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, 1025 rvc_imm_eq_zero, rvc_end }; 1026 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; 1027 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end }; 1028 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end }; 1029 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end }; 1030 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end }; 1031 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end }; 1032 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end }; 1033 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end }; 1034 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end }; 1035 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1036 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1037 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1038 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1039 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1040 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1041 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1042 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1043 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1044 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end }; 1045 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end }; 1046 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end }; 1047 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end }; 1048 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end }; 1049 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end }; 1050 static const rvc_constraint rvcc_ble[] = { rvc_end }; 1051 static const rvc_constraint rvcc_bleu[] = { rvc_end }; 1052 static const rvc_constraint rvcc_bgt[] = { rvc_end }; 1053 static const rvc_constraint rvcc_bgtu[] = { rvc_end }; 1054 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end }; 1055 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, 1056 rvc_end }; 1057 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, 1058 rvc_end }; 1059 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, 1060 rvc_end }; 1061 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, 1062 rvc_end }; 1063 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, 1064 rvc_csr_eq_0xc02, rvc_end }; 1065 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, 1066 rvc_csr_eq_0xc80, rvc_end }; 1067 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, 1068 rvc_end }; 1069 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, 1070 rvc_csr_eq_0xc82, rvc_end }; 1071 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, 1072 rvc_end }; 1073 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, 1074 rvc_end }; 1075 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, 1076 rvc_end }; 1077 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end }; 1078 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end }; 1079 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end }; 1080 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end }; 1081 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end }; 1082 1083 /* pseudo-instruction metadata */ 1084 1085 static const rv_comp_data rvcp_jal[] = { 1086 { rv_op_j, rvcc_j }, 1087 { rv_op_jal, rvcc_jal }, 1088 { rv_op_illegal, NULL } 1089 }; 1090 1091 static const rv_comp_data rvcp_jalr[] = { 1092 { rv_op_ret, rvcc_ret }, 1093 { rv_op_jr, rvcc_jr }, 1094 { rv_op_jalr, rvcc_jalr }, 1095 { rv_op_illegal, NULL } 1096 }; 1097 1098 static const rv_comp_data rvcp_beq[] = { 1099 { rv_op_beqz, rvcc_beqz }, 1100 { rv_op_illegal, NULL } 1101 }; 1102 1103 static const rv_comp_data rvcp_bne[] = { 1104 { rv_op_bnez, rvcc_bnez }, 1105 { rv_op_illegal, NULL } 1106 }; 1107 1108 static const rv_comp_data rvcp_blt[] = { 1109 { rv_op_bltz, rvcc_bltz }, 1110 { rv_op_bgtz, rvcc_bgtz }, 1111 { rv_op_bgt, rvcc_bgt }, 1112 { rv_op_illegal, NULL } 1113 }; 1114 1115 static const rv_comp_data rvcp_bge[] = { 1116 { rv_op_blez, rvcc_blez }, 1117 { rv_op_bgez, rvcc_bgez }, 1118 { rv_op_ble, rvcc_ble }, 1119 { rv_op_illegal, NULL } 1120 }; 1121 1122 static const rv_comp_data rvcp_bltu[] = { 1123 { rv_op_bgtu, rvcc_bgtu }, 1124 { rv_op_illegal, NULL } 1125 }; 1126 1127 static const rv_comp_data rvcp_bgeu[] = { 1128 { rv_op_bleu, rvcc_bleu }, 1129 { rv_op_illegal, NULL } 1130 }; 1131 1132 static const rv_comp_data rvcp_addi[] = { 1133 { rv_op_nop, rvcc_nop }, 1134 { rv_op_mv, rvcc_mv }, 1135 { rv_op_illegal, NULL } 1136 }; 1137 1138 static const rv_comp_data rvcp_sltiu[] = { 1139 { rv_op_seqz, rvcc_seqz }, 1140 { rv_op_illegal, NULL } 1141 }; 1142 1143 static const rv_comp_data rvcp_xori[] = { 1144 { rv_op_not, rvcc_not }, 1145 { rv_op_illegal, NULL } 1146 }; 1147 1148 static const rv_comp_data rvcp_sub[] = { 1149 { rv_op_neg, rvcc_neg }, 1150 { rv_op_illegal, NULL } 1151 }; 1152 1153 static const rv_comp_data rvcp_slt[] = { 1154 { rv_op_sltz, rvcc_sltz }, 1155 { rv_op_sgtz, rvcc_sgtz }, 1156 { rv_op_illegal, NULL } 1157 }; 1158 1159 static const rv_comp_data rvcp_sltu[] = { 1160 { rv_op_snez, rvcc_snez }, 1161 { rv_op_illegal, NULL } 1162 }; 1163 1164 static const rv_comp_data rvcp_addiw[] = { 1165 { rv_op_sext_w, rvcc_sext_w }, 1166 { rv_op_illegal, NULL } 1167 }; 1168 1169 static const rv_comp_data rvcp_subw[] = { 1170 { rv_op_negw, rvcc_negw }, 1171 { rv_op_illegal, NULL } 1172 }; 1173 1174 static const rv_comp_data rvcp_csrrw[] = { 1175 { rv_op_fscsr, rvcc_fscsr }, 1176 { rv_op_fsrm, rvcc_fsrm }, 1177 { rv_op_fsflags, rvcc_fsflags }, 1178 { rv_op_illegal, NULL } 1179 }; 1180 1181 1182 static const rv_comp_data rvcp_csrrs[] = { 1183 { rv_op_rdcycle, rvcc_rdcycle }, 1184 { rv_op_rdtime, rvcc_rdtime }, 1185 { rv_op_rdinstret, rvcc_rdinstret }, 1186 { rv_op_rdcycleh, rvcc_rdcycleh }, 1187 { rv_op_rdtimeh, rvcc_rdtimeh }, 1188 { rv_op_rdinstreth, rvcc_rdinstreth }, 1189 { rv_op_frcsr, rvcc_frcsr }, 1190 { rv_op_frrm, rvcc_frrm }, 1191 { rv_op_frflags, rvcc_frflags }, 1192 { rv_op_illegal, NULL } 1193 }; 1194 1195 static const rv_comp_data rvcp_csrrwi[] = { 1196 { rv_op_fsrmi, rvcc_fsrmi }, 1197 { rv_op_fsflagsi, rvcc_fsflagsi }, 1198 { rv_op_illegal, NULL } 1199 }; 1200 1201 static const rv_comp_data rvcp_fsgnj_s[] = { 1202 { rv_op_fmv_s, rvcc_fmv_s }, 1203 { rv_op_illegal, NULL } 1204 }; 1205 1206 static const rv_comp_data rvcp_fsgnjn_s[] = { 1207 { rv_op_fneg_s, rvcc_fneg_s }, 1208 { rv_op_illegal, NULL } 1209 }; 1210 1211 static const rv_comp_data rvcp_fsgnjx_s[] = { 1212 { rv_op_fabs_s, rvcc_fabs_s }, 1213 { rv_op_illegal, NULL } 1214 }; 1215 1216 static const rv_comp_data rvcp_fsgnj_d[] = { 1217 { rv_op_fmv_d, rvcc_fmv_d }, 1218 { rv_op_illegal, NULL } 1219 }; 1220 1221 static const rv_comp_data rvcp_fsgnjn_d[] = { 1222 { rv_op_fneg_d, rvcc_fneg_d }, 1223 { rv_op_illegal, NULL } 1224 }; 1225 1226 static const rv_comp_data rvcp_fsgnjx_d[] = { 1227 { rv_op_fabs_d, rvcc_fabs_d }, 1228 { rv_op_illegal, NULL } 1229 }; 1230 1231 static const rv_comp_data rvcp_fsgnj_q[] = { 1232 { rv_op_fmv_q, rvcc_fmv_q }, 1233 { rv_op_illegal, NULL } 1234 }; 1235 1236 static const rv_comp_data rvcp_fsgnjn_q[] = { 1237 { rv_op_fneg_q, rvcc_fneg_q }, 1238 { rv_op_illegal, NULL } 1239 }; 1240 1241 static const rv_comp_data rvcp_fsgnjx_q[] = { 1242 { rv_op_fabs_q, rvcc_fabs_q }, 1243 { rv_op_illegal, NULL } 1244 }; 1245 1246 /* instruction metadata */ 1247 1248 const rv_opcode_data rvi_opcode_data[] = { 1249 { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, 1250 { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 }, 1251 { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 }, 1252 { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 }, 1253 { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 }, 1254 { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 }, 1255 { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 }, 1256 { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 }, 1257 { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 }, 1258 { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 }, 1259 { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 }, 1260 { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1261 { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1262 { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1263 { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1264 { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1265 { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1266 { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1267 { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1268 { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 }, 1269 { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1270 { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 }, 1271 { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 }, 1272 { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1273 { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1274 { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1275 { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1276 { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1277 { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1278 { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 }, 1279 { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1280 { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 }, 1281 { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 }, 1282 { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1283 { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1284 { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1285 { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1286 { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1287 { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 }, 1288 { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1289 { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1290 { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1291 { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1292 { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 }, 1293 { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1294 { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1295 { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1296 { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1297 { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 }, 1298 { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1299 { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1300 { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1301 { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1302 { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1303 { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1304 { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1305 { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1306 { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1307 { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1308 { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1309 { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1310 { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1311 { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1312 { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1313 { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1314 { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1315 { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1316 { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1317 { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1318 { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1319 { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1320 { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1321 { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1322 { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1323 { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1324 { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1325 { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1326 { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1327 { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1328 { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1329 { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1330 { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1331 { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1332 { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1333 { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1334 { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1335 { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1336 { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1337 { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1338 { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1339 { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1340 { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1341 { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1342 { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1343 { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1344 { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1345 { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1346 { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1347 { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1348 { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1349 { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1350 { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1351 { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1352 { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1353 { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1354 { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1355 { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1356 { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1357 { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1358 { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1359 { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1360 { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1361 { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1362 { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1363 { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1364 { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1365 { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1366 { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1367 { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1368 { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1369 { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1370 { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1371 { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, 1372 { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 }, 1373 { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1374 { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 }, 1375 { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 }, 1376 { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 }, 1377 { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 }, 1378 { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1379 { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1380 { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1381 { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1382 { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1383 { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1384 { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1385 { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1386 { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1387 { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1388 { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1389 { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1390 { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 }, 1391 { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 }, 1392 { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 }, 1393 { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1394 { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1395 { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1396 { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1397 { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1398 { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1399 { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1400 { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1401 { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1402 { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1403 { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1404 { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1405 { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1406 { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1407 { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1408 { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1409 { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1410 { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1411 { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1412 { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1413 { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1414 { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1415 { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1416 { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1417 { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1418 { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1419 { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1420 { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 }, 1421 { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 }, 1422 { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 }, 1423 { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1424 { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1425 { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1426 { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1427 { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1428 { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1429 { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1430 { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1431 { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1432 { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1433 { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1434 { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1435 { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1436 { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1437 { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1438 { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1439 { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1440 { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1441 { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1442 { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1443 { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1444 { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1445 { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1446 { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1447 { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1448 { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1449 { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1450 { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1451 { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1452 { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 }, 1453 { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 }, 1454 { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 }, 1455 { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1456 { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1457 { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1458 { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1459 { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1460 { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1461 { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1462 { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1463 { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1464 { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1465 { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1466 { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1467 { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1468 { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1469 { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1470 { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1471 { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1472 { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1473 { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1474 { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1475 { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1476 { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1477 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1478 { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1479 rv_op_fld, 0 }, 1480 { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, 1481 rv_op_lw }, 1482 { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, 1483 { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1484 rv_op_fsd, 0 }, 1485 { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, 1486 rv_op_sw }, 1487 { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, 1488 { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, 1489 rv_op_addi }, 1490 { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1491 rv_op_addi, rvcd_imm_nz }, 1492 { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 }, 1493 { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1494 rv_op_addi }, 1495 { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1496 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1497 { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui, 1498 rv_op_lui, rvcd_imm_nz }, 1499 { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, 1500 rv_op_srli, rv_op_srli, rvcd_imm_nz }, 1501 { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, 1502 rv_op_srai, rv_op_srai, rvcd_imm_nz }, 1503 { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, 1504 rv_op_andi, rv_op_andi }, 1505 { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, 1506 rv_op_sub }, 1507 { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, 1508 rv_op_xor }, 1509 { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, 1510 rv_op_or }, 1511 { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, 1512 rv_op_and }, 1513 { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, 1514 rv_op_subw }, 1515 { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, 1516 rv_op_addw }, 1517 { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, 1518 rv_op_jal }, 1519 { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, 1520 rv_op_beq }, 1521 { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, 1522 rv_op_bne }, 1523 { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, 1524 rv_op_slli, rv_op_slli, rvcd_imm_nz }, 1525 { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1526 rv_op_fld, rv_op_fld }, 1527 { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, 1528 rv_op_lw, rv_op_lw }, 1529 { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 1530 0 }, 1531 { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1532 rv_op_jalr, rv_op_jalr }, 1533 { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, 1534 rv_op_addi }, 1535 { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, 1536 rv_op_ebreak, rv_op_ebreak }, 1537 { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1538 rv_op_jalr, rv_op_jalr }, 1539 { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, 1540 rv_op_add }, 1541 { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1542 rv_op_fsd, rv_op_fsd }, 1543 { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, 1544 rv_op_sw, rv_op_sw }, 1545 { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 1546 0 }, 1547 { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1548 rv_op_ld }, 1549 { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1550 rv_op_sd }, 1551 { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, 1552 rv_op_addiw }, 1553 { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1554 rv_op_ld }, 1555 { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1556 rv_op_sd }, 1557 { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1558 { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, 1559 { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1560 { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 1561 rv_op_sq }, 1562 { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1563 { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1564 { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1565 { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1566 { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1567 { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1568 { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1569 { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1570 { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1571 { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1572 { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1573 { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1574 { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1575 { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1576 { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1577 { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1578 { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1579 { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1580 { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1581 { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1582 { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1583 { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1584 { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1585 { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1586 { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1587 { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1588 { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1589 { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1590 { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1591 { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 }, 1592 { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1593 { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 }, 1594 { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1595 { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1596 { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1597 { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1598 { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1599 { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1600 { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1601 { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1602 { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1603 { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1604 { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1605 { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1606 { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1607 { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1608 { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1609 { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1610 { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1611 { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1612 { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1613 { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1614 { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1615 { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1616 { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1617 { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1618 { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1619 { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1620 { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1621 { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1622 { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1623 { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1624 { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1625 { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1626 { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1627 { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1628 { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1629 { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1630 { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1631 { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1632 { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1633 { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1634 { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1635 { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1636 { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1637 { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1638 { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1639 { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1640 { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1641 { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1642 { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1643 { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1644 { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1645 { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1646 { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1647 { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1648 { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1649 { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1650 { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1651 { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1652 { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1653 { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1654 { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1655 { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 }, 1656 { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1657 { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1658 { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1659 { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1660 { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1661 { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1662 { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1663 { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1664 { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1665 { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1666 { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1667 { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1668 { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1669 { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1670 { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1671 { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1672 { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1673 { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1674 { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1675 { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1676 { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1677 { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1678 { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1679 { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1680 { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1681 { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1682 { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1683 { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1684 { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1685 { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1686 { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1687 { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1688 { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1689 { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1690 { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1691 { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1692 { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1693 { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1694 { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1695 { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1696 { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1697 { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1698 { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1699 { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1700 { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1701 { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1702 { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1703 { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1704 { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1705 { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1706 { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1707 { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1708 { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1709 { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1710 { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1711 { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1712 { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1713 { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1714 { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1715 { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1716 { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1717 { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1718 { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1719 { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1720 { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1721 { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1722 { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1723 { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1724 { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1725 { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1726 { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1727 { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1728 { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1729 { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1730 { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1731 { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1732 { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1733 { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1734 { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1735 { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1736 { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1737 { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1738 { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1739 { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1740 { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1741 { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1742 { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1743 { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1744 { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1745 { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1746 { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1747 { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1748 { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1749 { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1750 { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1751 { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1752 { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1753 { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1754 { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1755 { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1756 { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1757 { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1758 { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1759 { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1760 { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1761 { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1762 { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1763 { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1764 { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1765 { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1766 { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1767 { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1768 { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1769 { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1770 { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1771 { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1772 { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1773 { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1774 { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1775 { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1776 { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1777 { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1778 { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1779 { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1780 { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1781 { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1782 { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1783 { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1784 { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1785 { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1786 { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1787 { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1788 { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1789 { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1790 { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1791 { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1792 { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1793 { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1794 { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1795 { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1796 { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1797 { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1798 { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1799 { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1800 { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1801 { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1802 { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1803 { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1804 { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1805 { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1806 { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1807 { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1808 { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1809 { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1810 { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1811 { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1812 { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1813 { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1814 { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1815 { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1816 { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1817 { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1818 { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1819 { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1820 { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1821 { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1822 { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1823 { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1824 { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1825 { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1826 { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1827 { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1828 { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1829 { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1830 { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1831 { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1832 { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1833 { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1834 { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1835 { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1836 { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1837 { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1838 { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1839 { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1840 { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1841 { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1842 { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1843 { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1844 { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1845 { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1846 { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1847 { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1848 { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1849 { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1850 { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1851 { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1852 { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1853 { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1854 { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1855 { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1856 { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1857 { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1858 { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1859 { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1860 { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1861 { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1862 { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1863 { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1864 { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1865 { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1866 { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1867 { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1868 { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 }, 1869 { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 1870 { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 }, 1871 { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1872 { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1873 { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1874 { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1875 { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1876 { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1877 { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1878 { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1879 { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1880 { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1881 { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1882 { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1883 { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1884 { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1885 { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1886 { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1887 { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1888 { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1889 { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1890 { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1891 { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1892 { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1893 { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1894 { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1895 { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1896 { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1897 { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1898 { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1899 { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1900 { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1901 { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1902 { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1903 { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1904 { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1905 { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1906 { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1907 { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1908 { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1909 { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1910 { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1911 { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1912 { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1913 { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1914 { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1915 { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1916 { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1917 { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1918 { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1919 { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1920 { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1921 { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1922 { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1923 { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1924 { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1925 { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1926 { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1927 { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1928 { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1929 { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1930 { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1931 { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1932 { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1933 { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1934 { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1935 { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1936 { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1937 { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1938 { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1939 { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1940 { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1941 { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1942 { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1943 { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1944 { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1945 { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1946 { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1947 { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1948 { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1949 { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1950 { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1951 { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1952 { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1953 { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1954 { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1955 { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1956 { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1957 { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1958 { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1959 { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1960 { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1961 { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1962 { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1963 { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1964 { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1965 { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1966 { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1967 { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1968 { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1969 { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1970 { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1971 { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1972 { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1973 { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1974 { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1975 { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1976 { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 }, 1977 { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 1978 { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1979 { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1980 { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1981 { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1982 { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1983 { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1984 { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1985 { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1986 { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1987 { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1988 { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1989 { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1990 { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1991 { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1992 { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1993 { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1994 { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1995 { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1996 { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1997 { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1998 { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1999 { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2000 { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2001 { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2002 { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2003 { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2004 { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2005 { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2006 { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2007 { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2008 { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2009 { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2010 { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2011 { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2012 { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2013 { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2014 { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2015 { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2016 { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2017 { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2018 { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2019 { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2020 { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2021 { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2022 { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2023 { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 2024 { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 2025 { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2026 { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2027 { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2028 { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2029 { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 }, 2030 { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 }, 2031 { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 2032 { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 }, 2033 { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 2034 { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2035 { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2036 { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2037 { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2038 { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2039 { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2040 { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2041 { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2042 { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2043 { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2044 { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2045 { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2046 { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2047 { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2048 { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2049 { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2050 { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2051 { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2052 { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2053 { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2054 { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2055 { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 }, 2056 { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 }, 2057 { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2058 { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2059 { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2060 { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2061 { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2062 { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2063 { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2064 { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 }, 2065 { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2066 { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2067 { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2068 { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2069 { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2070 { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 }, 2071 { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2072 { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 }, 2073 { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2074 { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2075 { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2076 { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2077 { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2078 { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2079 { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2080 { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2081 { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2082 { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2083 { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2084 { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 2085 { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 2086 { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 2087 { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 2088 { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 2089 { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2090 { "fli.s", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2091 { "fli.d", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2092 { "fli.q", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2093 { "fli.h", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2094 { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2095 { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2096 { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2097 { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2098 { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2099 { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2100 { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2101 { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2102 { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2103 { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2104 { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2105 { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2106 { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2107 { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2108 { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2109 { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2110 { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 2111 { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2112 { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2113 { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2114 { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2115 { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2116 { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2117 { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2118 { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2119 { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2120 { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2121 { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2122 { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2123 { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2124 { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2125 { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2126 { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2127 { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2128 { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2129 { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2130 { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2131 { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2132 { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2133 { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2134 { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2135 { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2136 { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2137 { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2138 { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2139 { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2140 { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2141 { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2142 { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2143 { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2144 { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2145 { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2146 { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2147 { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2148 { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2149 { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2150 { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2151 { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2152 { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2153 { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2154 { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2155 { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2156 { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2157 { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2158 { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2159 { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2160 { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2161 { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2162 { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2163 { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2164 { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2165 { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2166 { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2167 { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2168 { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2169 { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2170 { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2171 { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2172 { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2173 { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2174 { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2175 { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2176 { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2177 { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2178 { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2179 { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2180 { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2181 { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2182 { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2183 { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2184 { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2185 { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2186 { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2187 { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2188 { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2189 { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2190 { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2191 { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2192 { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2193 { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2194 { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2195 { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2196 { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2197 { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2198 { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2199 { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2200 { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2201 { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2202 { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2203 { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2204 { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2205 { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2206 { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2207 { "c.mop.1", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2208 { "c.mop.3", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2209 { "c.mop.5", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2210 { "c.mop.7", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2211 { "c.mop.9", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2212 { "c.mop.11", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2213 { "c.mop.13", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2214 { "c.mop.15", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2215 { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2216 { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2217 { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2218 { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2219 { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2220 { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2221 { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2222 { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2223 { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2224 { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2225 { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2226 { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2227 { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2228 { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2229 { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2230 { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2231 { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2232 { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2233 { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2234 { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2235 }; 2236 2237 /* CSR names */ 2238 2239 static const char *csr_name(int csrno) 2240 { 2241 switch (csrno) { 2242 case 0x0000: return "ustatus"; 2243 case 0x0001: return "fflags"; 2244 case 0x0002: return "frm"; 2245 case 0x0003: return "fcsr"; 2246 case 0x0004: return "uie"; 2247 case 0x0005: return "utvec"; 2248 case 0x0008: return "vstart"; 2249 case 0x0009: return "vxsat"; 2250 case 0x000a: return "vxrm"; 2251 case 0x000f: return "vcsr"; 2252 case 0x0015: return "seed"; 2253 case 0x0017: return "jvt"; 2254 case 0x0040: return "uscratch"; 2255 case 0x0041: return "uepc"; 2256 case 0x0042: return "ucause"; 2257 case 0x0043: return "utval"; 2258 case 0x0044: return "uip"; 2259 case 0x0100: return "sstatus"; 2260 case 0x0104: return "sie"; 2261 case 0x0105: return "stvec"; 2262 case 0x0106: return "scounteren"; 2263 case 0x0140: return "sscratch"; 2264 case 0x0141: return "sepc"; 2265 case 0x0142: return "scause"; 2266 case 0x0143: return "stval"; 2267 case 0x0144: return "sip"; 2268 case 0x0180: return "satp"; 2269 case 0x0200: return "hstatus"; 2270 case 0x0202: return "hedeleg"; 2271 case 0x0203: return "hideleg"; 2272 case 0x0204: return "hie"; 2273 case 0x0205: return "htvec"; 2274 case 0x0240: return "hscratch"; 2275 case 0x0241: return "hepc"; 2276 case 0x0242: return "hcause"; 2277 case 0x0243: return "hbadaddr"; 2278 case 0x0244: return "hip"; 2279 case 0x0300: return "mstatus"; 2280 case 0x0301: return "misa"; 2281 case 0x0302: return "medeleg"; 2282 case 0x0303: return "mideleg"; 2283 case 0x0304: return "mie"; 2284 case 0x0305: return "mtvec"; 2285 case 0x0306: return "mcounteren"; 2286 case 0x0320: return "mucounteren"; 2287 case 0x0321: return "mscounteren"; 2288 case 0x0322: return "mhcounteren"; 2289 case 0x0323: return "mhpmevent3"; 2290 case 0x0324: return "mhpmevent4"; 2291 case 0x0325: return "mhpmevent5"; 2292 case 0x0326: return "mhpmevent6"; 2293 case 0x0327: return "mhpmevent7"; 2294 case 0x0328: return "mhpmevent8"; 2295 case 0x0329: return "mhpmevent9"; 2296 case 0x032a: return "mhpmevent10"; 2297 case 0x032b: return "mhpmevent11"; 2298 case 0x032c: return "mhpmevent12"; 2299 case 0x032d: return "mhpmevent13"; 2300 case 0x032e: return "mhpmevent14"; 2301 case 0x032f: return "mhpmevent15"; 2302 case 0x0330: return "mhpmevent16"; 2303 case 0x0331: return "mhpmevent17"; 2304 case 0x0332: return "mhpmevent18"; 2305 case 0x0333: return "mhpmevent19"; 2306 case 0x0334: return "mhpmevent20"; 2307 case 0x0335: return "mhpmevent21"; 2308 case 0x0336: return "mhpmevent22"; 2309 case 0x0337: return "mhpmevent23"; 2310 case 0x0338: return "mhpmevent24"; 2311 case 0x0339: return "mhpmevent25"; 2312 case 0x033a: return "mhpmevent26"; 2313 case 0x033b: return "mhpmevent27"; 2314 case 0x033c: return "mhpmevent28"; 2315 case 0x033d: return "mhpmevent29"; 2316 case 0x033e: return "mhpmevent30"; 2317 case 0x033f: return "mhpmevent31"; 2318 case 0x0340: return "mscratch"; 2319 case 0x0341: return "mepc"; 2320 case 0x0342: return "mcause"; 2321 case 0x0343: return "mtval"; 2322 case 0x0344: return "mip"; 2323 case 0x0380: return "mbase"; 2324 case 0x0381: return "mbound"; 2325 case 0x0382: return "mibase"; 2326 case 0x0383: return "mibound"; 2327 case 0x0384: return "mdbase"; 2328 case 0x0385: return "mdbound"; 2329 case 0x03a0: return "pmpcfg0"; 2330 case 0x03a1: return "pmpcfg1"; 2331 case 0x03a2: return "pmpcfg2"; 2332 case 0x03a3: return "pmpcfg3"; 2333 case 0x03a4: return "pmpcfg4"; 2334 case 0x03a5: return "pmpcfg5"; 2335 case 0x03a6: return "pmpcfg6"; 2336 case 0x03a7: return "pmpcfg7"; 2337 case 0x03a8: return "pmpcfg8"; 2338 case 0x03a9: return "pmpcfg9"; 2339 case 0x03aa: return "pmpcfg10"; 2340 case 0x03ab: return "pmpcfg11"; 2341 case 0x03ac: return "pmpcfg12"; 2342 case 0x03ad: return "pmpcfg13"; 2343 case 0x03ae: return "pmpcfg14"; 2344 case 0x03af: return "pmpcfg15"; 2345 case 0x03b0: return "pmpaddr0"; 2346 case 0x03b1: return "pmpaddr1"; 2347 case 0x03b2: return "pmpaddr2"; 2348 case 0x03b3: return "pmpaddr3"; 2349 case 0x03b4: return "pmpaddr4"; 2350 case 0x03b5: return "pmpaddr5"; 2351 case 0x03b6: return "pmpaddr6"; 2352 case 0x03b7: return "pmpaddr7"; 2353 case 0x03b8: return "pmpaddr8"; 2354 case 0x03b9: return "pmpaddr9"; 2355 case 0x03ba: return "pmpaddr10"; 2356 case 0x03bb: return "pmpaddr11"; 2357 case 0x03bc: return "pmpaddr12"; 2358 case 0x03bd: return "pmpaddr13"; 2359 case 0x03be: return "pmpaddr14"; 2360 case 0x03bf: return "pmpaddr15"; 2361 case 0x03c0: return "pmpaddr16"; 2362 case 0x03c1: return "pmpaddr17"; 2363 case 0x03c2: return "pmpaddr18"; 2364 case 0x03c3: return "pmpaddr19"; 2365 case 0x03c4: return "pmpaddr20"; 2366 case 0x03c5: return "pmpaddr21"; 2367 case 0x03c6: return "pmpaddr22"; 2368 case 0x03c7: return "pmpaddr23"; 2369 case 0x03c8: return "pmpaddr24"; 2370 case 0x03c9: return "pmpaddr25"; 2371 case 0x03ca: return "pmpaddr26"; 2372 case 0x03cb: return "pmpaddr27"; 2373 case 0x03cc: return "pmpaddr28"; 2374 case 0x03cd: return "pmpaddr29"; 2375 case 0x03ce: return "pmpaddr30"; 2376 case 0x03cf: return "pmpaddr31"; 2377 case 0x03d0: return "pmpaddr32"; 2378 case 0x03d1: return "pmpaddr33"; 2379 case 0x03d2: return "pmpaddr34"; 2380 case 0x03d3: return "pmpaddr35"; 2381 case 0x03d4: return "pmpaddr36"; 2382 case 0x03d5: return "pmpaddr37"; 2383 case 0x03d6: return "pmpaddr38"; 2384 case 0x03d7: return "pmpaddr39"; 2385 case 0x03d8: return "pmpaddr40"; 2386 case 0x03d9: return "pmpaddr41"; 2387 case 0x03da: return "pmpaddr42"; 2388 case 0x03db: return "pmpaddr43"; 2389 case 0x03dc: return "pmpaddr44"; 2390 case 0x03dd: return "pmpaddr45"; 2391 case 0x03de: return "pmpaddr46"; 2392 case 0x03df: return "pmpaddr47"; 2393 case 0x03e0: return "pmpaddr48"; 2394 case 0x03e1: return "pmpaddr49"; 2395 case 0x03e2: return "pmpaddr50"; 2396 case 0x03e3: return "pmpaddr51"; 2397 case 0x03e4: return "pmpaddr52"; 2398 case 0x03e5: return "pmpaddr53"; 2399 case 0x03e6: return "pmpaddr54"; 2400 case 0x03e7: return "pmpaddr55"; 2401 case 0x03e8: return "pmpaddr56"; 2402 case 0x03e9: return "pmpaddr57"; 2403 case 0x03ea: return "pmpaddr58"; 2404 case 0x03eb: return "pmpaddr59"; 2405 case 0x03ec: return "pmpaddr60"; 2406 case 0x03ed: return "pmpaddr61"; 2407 case 0x03ee: return "pmpaddr62"; 2408 case 0x03ef: return "pmpaddr63"; 2409 case 0x0780: return "mtohost"; 2410 case 0x0781: return "mfromhost"; 2411 case 0x0782: return "mreset"; 2412 case 0x0783: return "mipi"; 2413 case 0x0784: return "miobase"; 2414 case 0x07a0: return "tselect"; 2415 case 0x07a1: return "tdata1"; 2416 case 0x07a2: return "tdata2"; 2417 case 0x07a3: return "tdata3"; 2418 case 0x07b0: return "dcsr"; 2419 case 0x07b1: return "dpc"; 2420 case 0x07b2: return "dscratch"; 2421 case 0x0b00: return "mcycle"; 2422 case 0x0b01: return "mtime"; 2423 case 0x0b02: return "minstret"; 2424 case 0x0b03: return "mhpmcounter3"; 2425 case 0x0b04: return "mhpmcounter4"; 2426 case 0x0b05: return "mhpmcounter5"; 2427 case 0x0b06: return "mhpmcounter6"; 2428 case 0x0b07: return "mhpmcounter7"; 2429 case 0x0b08: return "mhpmcounter8"; 2430 case 0x0b09: return "mhpmcounter9"; 2431 case 0x0b0a: return "mhpmcounter10"; 2432 case 0x0b0b: return "mhpmcounter11"; 2433 case 0x0b0c: return "mhpmcounter12"; 2434 case 0x0b0d: return "mhpmcounter13"; 2435 case 0x0b0e: return "mhpmcounter14"; 2436 case 0x0b0f: return "mhpmcounter15"; 2437 case 0x0b10: return "mhpmcounter16"; 2438 case 0x0b11: return "mhpmcounter17"; 2439 case 0x0b12: return "mhpmcounter18"; 2440 case 0x0b13: return "mhpmcounter19"; 2441 case 0x0b14: return "mhpmcounter20"; 2442 case 0x0b15: return "mhpmcounter21"; 2443 case 0x0b16: return "mhpmcounter22"; 2444 case 0x0b17: return "mhpmcounter23"; 2445 case 0x0b18: return "mhpmcounter24"; 2446 case 0x0b19: return "mhpmcounter25"; 2447 case 0x0b1a: return "mhpmcounter26"; 2448 case 0x0b1b: return "mhpmcounter27"; 2449 case 0x0b1c: return "mhpmcounter28"; 2450 case 0x0b1d: return "mhpmcounter29"; 2451 case 0x0b1e: return "mhpmcounter30"; 2452 case 0x0b1f: return "mhpmcounter31"; 2453 case 0x0b80: return "mcycleh"; 2454 case 0x0b81: return "mtimeh"; 2455 case 0x0b82: return "minstreth"; 2456 case 0x0b83: return "mhpmcounter3h"; 2457 case 0x0b84: return "mhpmcounter4h"; 2458 case 0x0b85: return "mhpmcounter5h"; 2459 case 0x0b86: return "mhpmcounter6h"; 2460 case 0x0b87: return "mhpmcounter7h"; 2461 case 0x0b88: return "mhpmcounter8h"; 2462 case 0x0b89: return "mhpmcounter9h"; 2463 case 0x0b8a: return "mhpmcounter10h"; 2464 case 0x0b8b: return "mhpmcounter11h"; 2465 case 0x0b8c: return "mhpmcounter12h"; 2466 case 0x0b8d: return "mhpmcounter13h"; 2467 case 0x0b8e: return "mhpmcounter14h"; 2468 case 0x0b8f: return "mhpmcounter15h"; 2469 case 0x0b90: return "mhpmcounter16h"; 2470 case 0x0b91: return "mhpmcounter17h"; 2471 case 0x0b92: return "mhpmcounter18h"; 2472 case 0x0b93: return "mhpmcounter19h"; 2473 case 0x0b94: return "mhpmcounter20h"; 2474 case 0x0b95: return "mhpmcounter21h"; 2475 case 0x0b96: return "mhpmcounter22h"; 2476 case 0x0b97: return "mhpmcounter23h"; 2477 case 0x0b98: return "mhpmcounter24h"; 2478 case 0x0b99: return "mhpmcounter25h"; 2479 case 0x0b9a: return "mhpmcounter26h"; 2480 case 0x0b9b: return "mhpmcounter27h"; 2481 case 0x0b9c: return "mhpmcounter28h"; 2482 case 0x0b9d: return "mhpmcounter29h"; 2483 case 0x0b9e: return "mhpmcounter30h"; 2484 case 0x0b9f: return "mhpmcounter31h"; 2485 case 0x0c00: return "cycle"; 2486 case 0x0c01: return "time"; 2487 case 0x0c02: return "instret"; 2488 case 0x0c20: return "vl"; 2489 case 0x0c21: return "vtype"; 2490 case 0x0c22: return "vlenb"; 2491 case 0x0c80: return "cycleh"; 2492 case 0x0c81: return "timeh"; 2493 case 0x0c82: return "instreth"; 2494 case 0x0d00: return "scycle"; 2495 case 0x0d01: return "stime"; 2496 case 0x0d02: return "sinstret"; 2497 case 0x0d80: return "scycleh"; 2498 case 0x0d81: return "stimeh"; 2499 case 0x0d82: return "sinstreth"; 2500 case 0x0e00: return "hcycle"; 2501 case 0x0e01: return "htime"; 2502 case 0x0e02: return "hinstret"; 2503 case 0x0e80: return "hcycleh"; 2504 case 0x0e81: return "htimeh"; 2505 case 0x0e82: return "hinstreth"; 2506 case 0x0f11: return "mvendorid"; 2507 case 0x0f12: return "marchid"; 2508 case 0x0f13: return "mimpid"; 2509 case 0x0f14: return "mhartid"; 2510 default: return NULL; 2511 } 2512 } 2513 2514 /* decode opcode */ 2515 2516 static void decode_inst_opcode(rv_decode *dec, rv_isa isa) 2517 { 2518 rv_inst inst = dec->inst; 2519 rv_opcode op = rv_op_illegal; 2520 switch ((inst >> 0) & 0b11) { 2521 case 0: 2522 switch ((inst >> 13) & 0b111) { 2523 case 0: op = rv_op_c_addi4spn; break; 2524 case 1: 2525 if (isa == rv128) { 2526 op = rv_op_c_lq; 2527 } else { 2528 op = rv_op_c_fld; 2529 } 2530 break; 2531 case 2: op = rv_op_c_lw; break; 2532 case 3: 2533 if (isa == rv32) { 2534 op = rv_op_c_flw; 2535 } else { 2536 op = rv_op_c_ld; 2537 } 2538 break; 2539 case 4: 2540 switch ((inst >> 10) & 0b111) { 2541 case 0: op = rv_op_c_lbu; break; 2542 case 1: 2543 if (((inst >> 6) & 1) == 0) { 2544 op = rv_op_c_lhu; 2545 } else { 2546 op = rv_op_c_lh; 2547 } 2548 break; 2549 case 2: op = rv_op_c_sb; break; 2550 case 3: 2551 if (((inst >> 6) & 1) == 0) { 2552 op = rv_op_c_sh; 2553 } 2554 break; 2555 } 2556 break; 2557 case 5: 2558 if (isa == rv128) { 2559 op = rv_op_c_sq; 2560 } else { 2561 op = rv_op_c_fsd; 2562 } 2563 break; 2564 case 6: op = rv_op_c_sw; break; 2565 case 7: 2566 if (isa == rv32) { 2567 op = rv_op_c_fsw; 2568 } else { 2569 op = rv_op_c_sd; 2570 } 2571 break; 2572 } 2573 break; 2574 case 1: 2575 switch ((inst >> 13) & 0b111) { 2576 case 0: 2577 switch ((inst >> 2) & 0b11111111111) { 2578 case 0: op = rv_op_c_nop; break; 2579 default: op = rv_op_c_addi; break; 2580 } 2581 break; 2582 case 1: 2583 if (isa == rv32) { 2584 op = rv_op_c_jal; 2585 } else { 2586 op = rv_op_c_addiw; 2587 } 2588 break; 2589 case 2: op = rv_op_c_li; break; 2590 case 3: 2591 if (dec->cfg->ext_zcmop) { 2592 if ((((inst >> 2) & 0b111111) == 0b100000) && 2593 (((inst >> 11) & 0b11) == 0b0)) { 2594 op = rv_c_mop_1 + ((inst >> 8) & 0b111); 2595 break; 2596 } 2597 } 2598 switch ((inst >> 7) & 0b11111) { 2599 case 2: op = rv_op_c_addi16sp; break; 2600 default: op = rv_op_c_lui; break; 2601 } 2602 break; 2603 case 4: 2604 switch ((inst >> 10) & 0b11) { 2605 case 0: 2606 op = rv_op_c_srli; 2607 break; 2608 case 1: 2609 op = rv_op_c_srai; 2610 break; 2611 case 2: op = rv_op_c_andi; break; 2612 case 3: 2613 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) { 2614 case 0: op = rv_op_c_sub; break; 2615 case 1: op = rv_op_c_xor; break; 2616 case 2: op = rv_op_c_or; break; 2617 case 3: op = rv_op_c_and; break; 2618 case 4: op = rv_op_c_subw; break; 2619 case 5: op = rv_op_c_addw; break; 2620 case 6: op = rv_op_c_mul; break; 2621 case 7: 2622 switch ((inst >> 2) & 0b111) { 2623 case 0: op = rv_op_c_zext_b; break; 2624 case 1: op = rv_op_c_sext_b; break; 2625 case 2: op = rv_op_c_zext_h; break; 2626 case 3: op = rv_op_c_sext_h; break; 2627 case 4: op = rv_op_c_zext_w; break; 2628 case 5: op = rv_op_c_not; break; 2629 } 2630 break; 2631 } 2632 break; 2633 } 2634 break; 2635 case 5: op = rv_op_c_j; break; 2636 case 6: op = rv_op_c_beqz; break; 2637 case 7: op = rv_op_c_bnez; break; 2638 } 2639 break; 2640 case 2: 2641 switch ((inst >> 13) & 0b111) { 2642 case 0: 2643 op = rv_op_c_slli; 2644 break; 2645 case 1: 2646 if (isa == rv128) { 2647 op = rv_op_c_lqsp; 2648 } else { 2649 op = rv_op_c_fldsp; 2650 } 2651 break; 2652 case 2: op = rv_op_c_lwsp; break; 2653 case 3: 2654 if (isa == rv32) { 2655 op = rv_op_c_flwsp; 2656 } else { 2657 op = rv_op_c_ldsp; 2658 } 2659 break; 2660 case 4: 2661 switch ((inst >> 12) & 0b1) { 2662 case 0: 2663 switch ((inst >> 2) & 0b11111) { 2664 case 0: op = rv_op_c_jr; break; 2665 default: op = rv_op_c_mv; break; 2666 } 2667 break; 2668 case 1: 2669 switch ((inst >> 2) & 0b11111) { 2670 case 0: 2671 switch ((inst >> 7) & 0b11111) { 2672 case 0: op = rv_op_c_ebreak; break; 2673 default: op = rv_op_c_jalr; break; 2674 } 2675 break; 2676 default: op = rv_op_c_add; break; 2677 } 2678 break; 2679 } 2680 break; 2681 case 5: 2682 if (isa == rv128) { 2683 op = rv_op_c_sqsp; 2684 } else { 2685 op = rv_op_c_fsdsp; 2686 if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { 2687 switch ((inst >> 8) & 0b01111) { 2688 case 8: 2689 if (((inst >> 4) & 0b01111) >= 4) { 2690 op = rv_op_cm_push; 2691 } 2692 break; 2693 case 10: 2694 if (((inst >> 4) & 0b01111) >= 4) { 2695 op = rv_op_cm_pop; 2696 } 2697 break; 2698 case 12: 2699 if (((inst >> 4) & 0b01111) >= 4) { 2700 op = rv_op_cm_popretz; 2701 } 2702 break; 2703 case 14: 2704 if (((inst >> 4) & 0b01111) >= 4) { 2705 op = rv_op_cm_popret; 2706 } 2707 break; 2708 } 2709 } else { 2710 switch ((inst >> 10) & 0b011) { 2711 case 0: 2712 if (!dec->cfg->ext_zcmt) { 2713 break; 2714 } 2715 if (((inst >> 2) & 0xFF) >= 32) { 2716 op = rv_op_cm_jalt; 2717 } else { 2718 op = rv_op_cm_jt; 2719 } 2720 break; 2721 case 3: 2722 if (!dec->cfg->ext_zcmp) { 2723 break; 2724 } 2725 switch ((inst >> 5) & 0b011) { 2726 case 1: op = rv_op_cm_mvsa01; break; 2727 case 3: op = rv_op_cm_mva01s; break; 2728 } 2729 break; 2730 } 2731 } 2732 } 2733 break; 2734 case 6: op = rv_op_c_swsp; break; 2735 case 7: 2736 if (isa == rv32) { 2737 op = rv_op_c_fswsp; 2738 } else { 2739 op = rv_op_c_sdsp; 2740 } 2741 break; 2742 } 2743 break; 2744 case 3: 2745 switch ((inst >> 2) & 0b11111) { 2746 case 0: 2747 switch ((inst >> 12) & 0b111) { 2748 case 0: op = rv_op_lb; break; 2749 case 1: op = rv_op_lh; break; 2750 case 2: op = rv_op_lw; break; 2751 case 3: op = rv_op_ld; break; 2752 case 4: op = rv_op_lbu; break; 2753 case 5: op = rv_op_lhu; break; 2754 case 6: op = rv_op_lwu; break; 2755 case 7: op = rv_op_ldu; break; 2756 } 2757 break; 2758 case 1: 2759 switch ((inst >> 12) & 0b111) { 2760 case 0: 2761 switch ((inst >> 20) & 0b111111111111) { 2762 case 40: op = rv_op_vl1re8_v; break; 2763 case 552: op = rv_op_vl2re8_v; break; 2764 case 1576: op = rv_op_vl4re8_v; break; 2765 case 3624: op = rv_op_vl8re8_v; break; 2766 } 2767 switch ((inst >> 26) & 0b111) { 2768 case 0: 2769 switch ((inst >> 20) & 0b11111) { 2770 case 0: op = rv_op_vle8_v; break; 2771 case 11: op = rv_op_vlm_v; break; 2772 case 16: op = rv_op_vle8ff_v; break; 2773 } 2774 break; 2775 case 1: op = rv_op_vluxei8_v; break; 2776 case 2: op = rv_op_vlse8_v; break; 2777 case 3: op = rv_op_vloxei8_v; break; 2778 } 2779 break; 2780 case 1: op = rv_op_flh; break; 2781 case 2: op = rv_op_flw; break; 2782 case 3: op = rv_op_fld; break; 2783 case 4: op = rv_op_flq; break; 2784 case 5: 2785 switch ((inst >> 20) & 0b111111111111) { 2786 case 40: op = rv_op_vl1re16_v; break; 2787 case 552: op = rv_op_vl2re16_v; break; 2788 case 1576: op = rv_op_vl4re16_v; break; 2789 case 3624: op = rv_op_vl8re16_v; break; 2790 } 2791 switch ((inst >> 26) & 0b111) { 2792 case 0: 2793 switch ((inst >> 20) & 0b11111) { 2794 case 0: op = rv_op_vle16_v; break; 2795 case 16: op = rv_op_vle16ff_v; break; 2796 } 2797 break; 2798 case 1: op = rv_op_vluxei16_v; break; 2799 case 2: op = rv_op_vlse16_v; break; 2800 case 3: op = rv_op_vloxei16_v; break; 2801 } 2802 break; 2803 case 6: 2804 switch ((inst >> 20) & 0b111111111111) { 2805 case 40: op = rv_op_vl1re32_v; break; 2806 case 552: op = rv_op_vl2re32_v; break; 2807 case 1576: op = rv_op_vl4re32_v; break; 2808 case 3624: op = rv_op_vl8re32_v; break; 2809 } 2810 switch ((inst >> 26) & 0b111) { 2811 case 0: 2812 switch ((inst >> 20) & 0b11111) { 2813 case 0: op = rv_op_vle32_v; break; 2814 case 16: op = rv_op_vle32ff_v; break; 2815 } 2816 break; 2817 case 1: op = rv_op_vluxei32_v; break; 2818 case 2: op = rv_op_vlse32_v; break; 2819 case 3: op = rv_op_vloxei32_v; break; 2820 } 2821 break; 2822 case 7: 2823 switch ((inst >> 20) & 0b111111111111) { 2824 case 40: op = rv_op_vl1re64_v; break; 2825 case 552: op = rv_op_vl2re64_v; break; 2826 case 1576: op = rv_op_vl4re64_v; break; 2827 case 3624: op = rv_op_vl8re64_v; break; 2828 } 2829 switch ((inst >> 26) & 0b111) { 2830 case 0: 2831 switch ((inst >> 20) & 0b11111) { 2832 case 0: op = rv_op_vle64_v; break; 2833 case 16: op = rv_op_vle64ff_v; break; 2834 } 2835 break; 2836 case 1: op = rv_op_vluxei64_v; break; 2837 case 2: op = rv_op_vlse64_v; break; 2838 case 3: op = rv_op_vloxei64_v; break; 2839 } 2840 break; 2841 } 2842 break; 2843 case 3: 2844 switch ((inst >> 12) & 0b111) { 2845 case 0: op = rv_op_fence; break; 2846 case 1: op = rv_op_fence_i; break; 2847 case 2: op = rv_op_lq; break; 2848 } 2849 break; 2850 case 4: 2851 switch ((inst >> 12) & 0b111) { 2852 case 0: op = rv_op_addi; break; 2853 case 1: 2854 switch ((inst >> 27) & 0b11111) { 2855 case 0b00000: op = rv_op_slli; break; 2856 case 0b00001: 2857 switch ((inst >> 20) & 0b1111111) { 2858 case 0b0001111: op = rv_op_zip; break; 2859 } 2860 break; 2861 case 0b00010: 2862 switch ((inst >> 20) & 0b1111111) { 2863 case 0b0000000: op = rv_op_sha256sum0; break; 2864 case 0b0000001: op = rv_op_sha256sum1; break; 2865 case 0b0000010: op = rv_op_sha256sig0; break; 2866 case 0b0000011: op = rv_op_sha256sig1; break; 2867 case 0b0000100: op = rv_op_sha512sum0; break; 2868 case 0b0000101: op = rv_op_sha512sum1; break; 2869 case 0b0000110: op = rv_op_sha512sig0; break; 2870 case 0b0000111: op = rv_op_sha512sig1; break; 2871 case 0b0001000: op = rv_op_sm3p0; break; 2872 case 0b0001001: op = rv_op_sm3p1; break; 2873 } 2874 break; 2875 case 0b00101: op = rv_op_bseti; break; 2876 case 0b00110: 2877 switch ((inst >> 20) & 0b1111111) { 2878 case 0b0000000: op = rv_op_aes64im; break; 2879 default: 2880 if (((inst >> 24) & 0b0111) == 0b001) { 2881 op = rv_op_aes64ks1i; 2882 } 2883 break; 2884 } 2885 break; 2886 case 0b01001: op = rv_op_bclri; break; 2887 case 0b01101: op = rv_op_binvi; break; 2888 case 0b01100: 2889 switch ((inst >> 20) & 0b1111111) { 2890 case 0b0000000: op = rv_op_clz; break; 2891 case 0b0000001: op = rv_op_ctz; break; 2892 case 0b0000010: op = rv_op_cpop; break; 2893 /* 0b0000011 */ 2894 case 0b0000100: op = rv_op_sext_b; break; 2895 case 0b0000101: op = rv_op_sext_h; break; 2896 } 2897 break; 2898 } 2899 break; 2900 case 2: op = rv_op_slti; break; 2901 case 3: op = rv_op_sltiu; break; 2902 case 4: op = rv_op_xori; break; 2903 case 5: 2904 switch ((inst >> 27) & 0b11111) { 2905 case 0b00000: op = rv_op_srli; break; 2906 case 0b00001: 2907 switch ((inst >> 20) & 0b1111111) { 2908 case 0b0001111: op = rv_op_unzip; break; 2909 } 2910 break; 2911 case 0b00101: op = rv_op_orc_b; break; 2912 case 0b01000: op = rv_op_srai; break; 2913 case 0b01001: op = rv_op_bexti; break; 2914 case 0b01100: op = rv_op_rori; break; 2915 case 0b01101: 2916 switch ((inst >> 20) & 0b1111111) { 2917 case 0b0011000: op = rv_op_rev8; break; 2918 case 0b0111000: op = rv_op_rev8; break; 2919 case 0b0000111: op = rv_op_brev8; break; 2920 } 2921 break; 2922 } 2923 break; 2924 case 6: op = rv_op_ori; break; 2925 case 7: op = rv_op_andi; break; 2926 } 2927 break; 2928 case 5: op = rv_op_auipc; break; 2929 case 6: 2930 switch ((inst >> 12) & 0b111) { 2931 case 0: op = rv_op_addiw; break; 2932 case 1: 2933 switch ((inst >> 26) & 0b111111) { 2934 case 0: op = rv_op_slliw; break; 2935 case 2: op = rv_op_slli_uw; break; 2936 case 24: 2937 switch ((inst >> 20) & 0b11111) { 2938 case 0b00000: op = rv_op_clzw; break; 2939 case 0b00001: op = rv_op_ctzw; break; 2940 case 0b00010: op = rv_op_cpopw; break; 2941 } 2942 break; 2943 } 2944 break; 2945 case 5: 2946 switch ((inst >> 25) & 0b1111111) { 2947 case 0: op = rv_op_srliw; break; 2948 case 32: op = rv_op_sraiw; break; 2949 case 48: op = rv_op_roriw; break; 2950 } 2951 break; 2952 } 2953 break; 2954 case 8: 2955 switch ((inst >> 12) & 0b111) { 2956 case 0: op = rv_op_sb; break; 2957 case 1: op = rv_op_sh; break; 2958 case 2: op = rv_op_sw; break; 2959 case 3: op = rv_op_sd; break; 2960 case 4: op = rv_op_sq; break; 2961 } 2962 break; 2963 case 9: 2964 switch ((inst >> 12) & 0b111) { 2965 case 0: 2966 switch ((inst >> 20) & 0b111111111111) { 2967 case 40: op = rv_op_vs1r_v; break; 2968 case 552: op = rv_op_vs2r_v; break; 2969 case 1576: op = rv_op_vs4r_v; break; 2970 case 3624: op = rv_op_vs8r_v; break; 2971 } 2972 switch ((inst >> 26) & 0b111) { 2973 case 0: 2974 switch ((inst >> 20) & 0b11111) { 2975 case 0: op = rv_op_vse8_v; break; 2976 case 11: op = rv_op_vsm_v; break; 2977 } 2978 break; 2979 case 1: op = rv_op_vsuxei8_v; break; 2980 case 2: op = rv_op_vsse8_v; break; 2981 case 3: op = rv_op_vsoxei8_v; break; 2982 } 2983 break; 2984 case 1: op = rv_op_fsh; break; 2985 case 2: op = rv_op_fsw; break; 2986 case 3: op = rv_op_fsd; break; 2987 case 4: op = rv_op_fsq; break; 2988 case 5: 2989 switch ((inst >> 26) & 0b111) { 2990 case 0: 2991 switch ((inst >> 20) & 0b11111) { 2992 case 0: op = rv_op_vse16_v; break; 2993 } 2994 break; 2995 case 1: op = rv_op_vsuxei16_v; break; 2996 case 2: op = rv_op_vsse16_v; break; 2997 case 3: op = rv_op_vsoxei16_v; break; 2998 } 2999 break; 3000 case 6: 3001 switch ((inst >> 26) & 0b111) { 3002 case 0: 3003 switch ((inst >> 20) & 0b11111) { 3004 case 0: op = rv_op_vse32_v; break; 3005 } 3006 break; 3007 case 1: op = rv_op_vsuxei32_v; break; 3008 case 2: op = rv_op_vsse32_v; break; 3009 case 3: op = rv_op_vsoxei32_v; break; 3010 } 3011 break; 3012 case 7: 3013 switch ((inst >> 26) & 0b111) { 3014 case 0: 3015 switch ((inst >> 20) & 0b11111) { 3016 case 0: op = rv_op_vse64_v; break; 3017 } 3018 break; 3019 case 1: op = rv_op_vsuxei64_v; break; 3020 case 2: op = rv_op_vsse64_v; break; 3021 case 3: op = rv_op_vsoxei64_v; break; 3022 } 3023 break; 3024 } 3025 break; 3026 case 11: 3027 switch (((inst >> 24) & 0b11111000) | 3028 ((inst >> 12) & 0b00000111)) { 3029 case 0: op = rv_op_amoadd_b; break; 3030 case 1: op = rv_op_amoadd_h; break; 3031 case 2: op = rv_op_amoadd_w; break; 3032 case 3: op = rv_op_amoadd_d; break; 3033 case 4: op = rv_op_amoadd_q; break; 3034 case 8: op = rv_op_amoswap_b; break; 3035 case 9: op = rv_op_amoswap_h; break; 3036 case 10: op = rv_op_amoswap_w; break; 3037 case 11: op = rv_op_amoswap_d; break; 3038 case 12: op = rv_op_amoswap_q; break; 3039 case 18: 3040 switch ((inst >> 20) & 0b11111) { 3041 case 0: op = rv_op_lr_w; break; 3042 } 3043 break; 3044 case 19: 3045 switch ((inst >> 20) & 0b11111) { 3046 case 0: op = rv_op_lr_d; break; 3047 } 3048 break; 3049 case 20: 3050 switch ((inst >> 20) & 0b11111) { 3051 case 0: op = rv_op_lr_q; break; 3052 } 3053 break; 3054 case 26: op = rv_op_sc_w; break; 3055 case 27: op = rv_op_sc_d; break; 3056 case 28: op = rv_op_sc_q; break; 3057 case 32: op = rv_op_amoxor_b; break; 3058 case 33: op = rv_op_amoxor_h; break; 3059 case 34: op = rv_op_amoxor_w; break; 3060 case 35: op = rv_op_amoxor_d; break; 3061 case 36: op = rv_op_amoxor_q; break; 3062 case 40: op = rv_op_amocas_b; break; 3063 case 41: op = rv_op_amocas_h; break; 3064 case 42: op = rv_op_amocas_w; break; 3065 case 43: op = rv_op_amocas_d; break; 3066 case 44: op = rv_op_amocas_q; break; 3067 case 64: op = rv_op_amoor_b; break; 3068 case 65: op = rv_op_amoor_h; break; 3069 case 66: op = rv_op_amoor_w; break; 3070 case 67: op = rv_op_amoor_d; break; 3071 case 68: op = rv_op_amoor_q; break; 3072 case 96: op = rv_op_amoand_b; break; 3073 case 97: op = rv_op_amoand_h; break; 3074 case 98: op = rv_op_amoand_w; break; 3075 case 99: op = rv_op_amoand_d; break; 3076 case 100: op = rv_op_amoand_q; break; 3077 case 128: op = rv_op_amomin_b; break; 3078 case 129: op = rv_op_amomin_h; break; 3079 case 130: op = rv_op_amomin_w; break; 3080 case 131: op = rv_op_amomin_d; break; 3081 case 132: op = rv_op_amomin_q; break; 3082 case 160: op = rv_op_amomax_b; break; 3083 case 161: op = rv_op_amomax_h; break; 3084 case 162: op = rv_op_amomax_w; break; 3085 case 163: op = rv_op_amomax_d; break; 3086 case 164: op = rv_op_amomax_q; break; 3087 case 192: op = rv_op_amominu_b; break; 3088 case 193: op = rv_op_amominu_h; break; 3089 case 194: op = rv_op_amominu_w; break; 3090 case 195: op = rv_op_amominu_d; break; 3091 case 196: op = rv_op_amominu_q; break; 3092 case 224: op = rv_op_amomaxu_b; break; 3093 case 225: op = rv_op_amomaxu_h; break; 3094 case 226: op = rv_op_amomaxu_w; break; 3095 case 227: op = rv_op_amomaxu_d; break; 3096 case 228: op = rv_op_amomaxu_q; break; 3097 } 3098 break; 3099 case 12: 3100 switch (((inst >> 22) & 0b1111111000) | 3101 ((inst >> 12) & 0b0000000111)) { 3102 case 0: op = rv_op_add; break; 3103 case 1: op = rv_op_sll; break; 3104 case 2: op = rv_op_slt; break; 3105 case 3: op = rv_op_sltu; break; 3106 case 4: op = rv_op_xor; break; 3107 case 5: op = rv_op_srl; break; 3108 case 6: op = rv_op_or; break; 3109 case 7: op = rv_op_and; break; 3110 case 8: op = rv_op_mul; break; 3111 case 9: op = rv_op_mulh; break; 3112 case 10: op = rv_op_mulhsu; break; 3113 case 11: op = rv_op_mulhu; break; 3114 case 12: op = rv_op_div; break; 3115 case 13: op = rv_op_divu; break; 3116 case 14: op = rv_op_rem; break; 3117 case 15: op = rv_op_remu; break; 3118 case 36: 3119 switch ((inst >> 20) & 0b11111) { 3120 case 0: op = rv_op_zext_h; break; 3121 default: op = rv_op_pack; break; 3122 } 3123 break; 3124 case 39: op = rv_op_packh; break; 3125 3126 case 41: op = rv_op_clmul; break; 3127 case 42: op = rv_op_clmulr; break; 3128 case 43: op = rv_op_clmulh; break; 3129 case 44: op = rv_op_min; break; 3130 case 45: op = rv_op_minu; break; 3131 case 46: op = rv_op_max; break; 3132 case 47: op = rv_op_maxu; break; 3133 case 075: op = rv_op_czero_eqz; break; 3134 case 077: op = rv_op_czero_nez; break; 3135 case 130: op = rv_op_sh1add; break; 3136 case 132: op = rv_op_sh2add; break; 3137 case 134: op = rv_op_sh3add; break; 3138 case 161: op = rv_op_bset; break; 3139 case 162: op = rv_op_xperm4; break; 3140 case 164: op = rv_op_xperm8; break; 3141 case 200: op = rv_op_aes64es; break; 3142 case 216: op = rv_op_aes64esm; break; 3143 case 232: op = rv_op_aes64ds; break; 3144 case 248: op = rv_op_aes64dsm; break; 3145 case 256: op = rv_op_sub; break; 3146 case 260: op = rv_op_xnor; break; 3147 case 261: op = rv_op_sra; break; 3148 case 262: op = rv_op_orn; break; 3149 case 263: op = rv_op_andn; break; 3150 case 289: op = rv_op_bclr; break; 3151 case 293: op = rv_op_bext; break; 3152 case 320: op = rv_op_sha512sum0r; break; 3153 case 328: op = rv_op_sha512sum1r; break; 3154 case 336: op = rv_op_sha512sig0l; break; 3155 case 344: op = rv_op_sha512sig1l; break; 3156 case 368: op = rv_op_sha512sig0h; break; 3157 case 376: op = rv_op_sha512sig1h; break; 3158 case 385: op = rv_op_rol; break; 3159 case 389: op = rv_op_ror; break; 3160 case 417: op = rv_op_binv; break; 3161 case 504: op = rv_op_aes64ks2; break; 3162 } 3163 switch ((inst >> 25) & 0b0011111) { 3164 case 17: op = rv_op_aes32esi; break; 3165 case 19: op = rv_op_aes32esmi; break; 3166 case 21: op = rv_op_aes32dsi; break; 3167 case 23: op = rv_op_aes32dsmi; break; 3168 case 24: op = rv_op_sm4ed; break; 3169 case 26: op = rv_op_sm4ks; break; 3170 } 3171 break; 3172 case 13: op = rv_op_lui; break; 3173 case 14: 3174 switch (((inst >> 22) & 0b1111111000) | 3175 ((inst >> 12) & 0b0000000111)) { 3176 case 0: op = rv_op_addw; break; 3177 case 1: op = rv_op_sllw; break; 3178 case 5: op = rv_op_srlw; break; 3179 case 8: op = rv_op_mulw; break; 3180 case 12: op = rv_op_divw; break; 3181 case 13: op = rv_op_divuw; break; 3182 case 14: op = rv_op_remw; break; 3183 case 15: op = rv_op_remuw; break; 3184 case 32: op = rv_op_add_uw; break; 3185 case 36: 3186 switch ((inst >> 20) & 0b11111) { 3187 case 0: op = rv_op_zext_h; break; 3188 default: op = rv_op_packw; break; 3189 } 3190 break; 3191 case 130: op = rv_op_sh1add_uw; break; 3192 case 132: op = rv_op_sh2add_uw; break; 3193 case 134: op = rv_op_sh3add_uw; break; 3194 case 256: op = rv_op_subw; break; 3195 case 261: op = rv_op_sraw; break; 3196 case 385: op = rv_op_rolw; break; 3197 case 389: op = rv_op_rorw; break; 3198 } 3199 break; 3200 case 16: 3201 switch ((inst >> 25) & 0b11) { 3202 case 0: op = rv_op_fmadd_s; break; 3203 case 1: op = rv_op_fmadd_d; break; 3204 case 3: op = rv_op_fmadd_q; break; 3205 } 3206 break; 3207 case 17: 3208 switch ((inst >> 25) & 0b11) { 3209 case 0: op = rv_op_fmsub_s; break; 3210 case 1: op = rv_op_fmsub_d; break; 3211 case 3: op = rv_op_fmsub_q; break; 3212 } 3213 break; 3214 case 18: 3215 switch ((inst >> 25) & 0b11) { 3216 case 0: op = rv_op_fnmsub_s; break; 3217 case 1: op = rv_op_fnmsub_d; break; 3218 case 3: op = rv_op_fnmsub_q; break; 3219 } 3220 break; 3221 case 19: 3222 switch ((inst >> 25) & 0b11) { 3223 case 0: op = rv_op_fnmadd_s; break; 3224 case 1: op = rv_op_fnmadd_d; break; 3225 case 3: op = rv_op_fnmadd_q; break; 3226 } 3227 break; 3228 case 20: 3229 switch ((inst >> 25) & 0b1111111) { 3230 case 0: op = rv_op_fadd_s; break; 3231 case 1: op = rv_op_fadd_d; break; 3232 case 3: op = rv_op_fadd_q; break; 3233 case 4: op = rv_op_fsub_s; break; 3234 case 5: op = rv_op_fsub_d; break; 3235 case 7: op = rv_op_fsub_q; break; 3236 case 8: op = rv_op_fmul_s; break; 3237 case 9: op = rv_op_fmul_d; break; 3238 case 11: op = rv_op_fmul_q; break; 3239 case 12: op = rv_op_fdiv_s; break; 3240 case 13: op = rv_op_fdiv_d; break; 3241 case 15: op = rv_op_fdiv_q; break; 3242 case 16: 3243 switch ((inst >> 12) & 0b111) { 3244 case 0: op = rv_op_fsgnj_s; break; 3245 case 1: op = rv_op_fsgnjn_s; break; 3246 case 2: op = rv_op_fsgnjx_s; break; 3247 } 3248 break; 3249 case 17: 3250 switch ((inst >> 12) & 0b111) { 3251 case 0: op = rv_op_fsgnj_d; break; 3252 case 1: op = rv_op_fsgnjn_d; break; 3253 case 2: op = rv_op_fsgnjx_d; break; 3254 } 3255 break; 3256 case 19: 3257 switch ((inst >> 12) & 0b111) { 3258 case 0: op = rv_op_fsgnj_q; break; 3259 case 1: op = rv_op_fsgnjn_q; break; 3260 case 2: op = rv_op_fsgnjx_q; break; 3261 } 3262 break; 3263 case 20: 3264 switch ((inst >> 12) & 0b111) { 3265 case 0: op = rv_op_fmin_s; break; 3266 case 1: op = rv_op_fmax_s; break; 3267 case 2: op = rv_op_fminm_s; break; 3268 case 3: op = rv_op_fmaxm_s; break; 3269 } 3270 break; 3271 case 21: 3272 switch ((inst >> 12) & 0b111) { 3273 case 0: op = rv_op_fmin_d; break; 3274 case 1: op = rv_op_fmax_d; break; 3275 case 2: op = rv_op_fminm_d; break; 3276 case 3: op = rv_op_fmaxm_d; break; 3277 } 3278 break; 3279 case 22: 3280 switch (((inst >> 12) & 0b111)) { 3281 case 2: op = rv_op_fminm_h; break; 3282 case 3: op = rv_op_fmaxm_h; break; 3283 } 3284 break; 3285 case 23: 3286 switch ((inst >> 12) & 0b111) { 3287 case 0: op = rv_op_fmin_q; break; 3288 case 1: op = rv_op_fmax_q; break; 3289 case 2: op = rv_op_fminm_q; break; 3290 case 3: op = rv_op_fmaxm_q; break; 3291 } 3292 break; 3293 case 32: 3294 switch ((inst >> 20) & 0b11111) { 3295 case 1: op = rv_op_fcvt_s_d; break; 3296 case 3: op = rv_op_fcvt_s_q; break; 3297 case 4: op = rv_op_fround_s; break; 3298 case 5: op = rv_op_froundnx_s; break; 3299 case 6: op = rv_op_fcvt_s_bf16; break; 3300 } 3301 break; 3302 case 33: 3303 switch ((inst >> 20) & 0b11111) { 3304 case 0: op = rv_op_fcvt_d_s; break; 3305 case 3: op = rv_op_fcvt_d_q; break; 3306 case 4: op = rv_op_fround_d; break; 3307 case 5: op = rv_op_froundnx_d; break; 3308 } 3309 break; 3310 case 34: 3311 switch (((inst >> 20) & 0b11111)) { 3312 case 4: op = rv_op_fround_h; break; 3313 case 5: op = rv_op_froundnx_h; break; 3314 case 8: op = rv_op_fcvt_bf16_s; break; 3315 } 3316 break; 3317 case 35: 3318 switch ((inst >> 20) & 0b11111) { 3319 case 0: op = rv_op_fcvt_q_s; break; 3320 case 1: op = rv_op_fcvt_q_d; break; 3321 case 4: op = rv_op_fround_q; break; 3322 case 5: op = rv_op_froundnx_q; break; 3323 } 3324 break; 3325 case 44: 3326 switch ((inst >> 20) & 0b11111) { 3327 case 0: op = rv_op_fsqrt_s; break; 3328 } 3329 break; 3330 case 45: 3331 switch ((inst >> 20) & 0b11111) { 3332 case 0: op = rv_op_fsqrt_d; break; 3333 } 3334 break; 3335 case 47: 3336 switch ((inst >> 20) & 0b11111) { 3337 case 0: op = rv_op_fsqrt_q; break; 3338 } 3339 break; 3340 case 80: 3341 switch ((inst >> 12) & 0b111) { 3342 case 0: op = rv_op_fle_s; break; 3343 case 1: op = rv_op_flt_s; break; 3344 case 2: op = rv_op_feq_s; break; 3345 case 4: op = rv_op_fleq_s; break; 3346 case 5: op = rv_op_fltq_s; break; 3347 } 3348 break; 3349 case 81: 3350 switch ((inst >> 12) & 0b111) { 3351 case 0: op = rv_op_fle_d; break; 3352 case 1: op = rv_op_flt_d; break; 3353 case 2: op = rv_op_feq_d; break; 3354 case 4: op = rv_op_fleq_d; break; 3355 case 5: op = rv_op_fltq_d; break; 3356 } 3357 break; 3358 case 82: 3359 switch (((inst >> 12) & 0b111)) { 3360 case 4: op = rv_op_fleq_h; break; 3361 case 5: op = rv_op_fltq_h; break; 3362 } 3363 break; 3364 case 83: 3365 switch ((inst >> 12) & 0b111) { 3366 case 0: op = rv_op_fle_q; break; 3367 case 1: op = rv_op_flt_q; break; 3368 case 2: op = rv_op_feq_q; break; 3369 case 4: op = rv_op_fleq_q; break; 3370 case 5: op = rv_op_fltq_q; break; 3371 } 3372 break; 3373 case 89: 3374 switch (((inst >> 12) & 0b111)) { 3375 case 0: op = rv_op_fmvp_d_x; break; 3376 } 3377 break; 3378 case 91: 3379 switch (((inst >> 12) & 0b111)) { 3380 case 0: op = rv_op_fmvp_q_x; break; 3381 } 3382 break; 3383 case 96: 3384 switch ((inst >> 20) & 0b11111) { 3385 case 0: op = rv_op_fcvt_w_s; break; 3386 case 1: op = rv_op_fcvt_wu_s; break; 3387 case 2: op = rv_op_fcvt_l_s; break; 3388 case 3: op = rv_op_fcvt_lu_s; break; 3389 } 3390 break; 3391 case 97: 3392 switch ((inst >> 20) & 0b11111) { 3393 case 0: op = rv_op_fcvt_w_d; break; 3394 case 1: op = rv_op_fcvt_wu_d; break; 3395 case 2: op = rv_op_fcvt_l_d; break; 3396 case 3: op = rv_op_fcvt_lu_d; break; 3397 case 8: op = rv_op_fcvtmod_w_d; break; 3398 } 3399 break; 3400 case 99: 3401 switch ((inst >> 20) & 0b11111) { 3402 case 0: op = rv_op_fcvt_w_q; break; 3403 case 1: op = rv_op_fcvt_wu_q; break; 3404 case 2: op = rv_op_fcvt_l_q; break; 3405 case 3: op = rv_op_fcvt_lu_q; break; 3406 } 3407 break; 3408 case 104: 3409 switch ((inst >> 20) & 0b11111) { 3410 case 0: op = rv_op_fcvt_s_w; break; 3411 case 1: op = rv_op_fcvt_s_wu; break; 3412 case 2: op = rv_op_fcvt_s_l; break; 3413 case 3: op = rv_op_fcvt_s_lu; break; 3414 } 3415 break; 3416 case 105: 3417 switch ((inst >> 20) & 0b11111) { 3418 case 0: op = rv_op_fcvt_d_w; break; 3419 case 1: op = rv_op_fcvt_d_wu; break; 3420 case 2: op = rv_op_fcvt_d_l; break; 3421 case 3: op = rv_op_fcvt_d_lu; break; 3422 } 3423 break; 3424 case 107: 3425 switch ((inst >> 20) & 0b11111) { 3426 case 0: op = rv_op_fcvt_q_w; break; 3427 case 1: op = rv_op_fcvt_q_wu; break; 3428 case 2: op = rv_op_fcvt_q_l; break; 3429 case 3: op = rv_op_fcvt_q_lu; break; 3430 } 3431 break; 3432 case 112: 3433 switch (((inst >> 17) & 0b11111000) | 3434 ((inst >> 12) & 0b00000111)) { 3435 case 0: op = rv_op_fmv_x_s; break; 3436 case 1: op = rv_op_fclass_s; break; 3437 } 3438 break; 3439 case 113: 3440 switch (((inst >> 17) & 0b11111000) | 3441 ((inst >> 12) & 0b00000111)) { 3442 case 0: op = rv_op_fmv_x_d; break; 3443 case 1: op = rv_op_fclass_d; break; 3444 case 8: op = rv_op_fmvh_x_d; break; 3445 } 3446 break; 3447 case 114: 3448 switch (((inst >> 17) & 0b11111000) | 3449 ((inst >> 12) & 0b00000111)) { 3450 case 0: op = rv_op_fmv_x_h; break; 3451 } 3452 break; 3453 case 115: 3454 switch (((inst >> 17) & 0b11111000) | 3455 ((inst >> 12) & 0b00000111)) { 3456 case 0: op = rv_op_fmv_x_q; break; 3457 case 1: op = rv_op_fclass_q; break; 3458 case 8: op = rv_op_fmvh_x_q; break; 3459 } 3460 break; 3461 case 120: 3462 switch (((inst >> 17) & 0b11111000) | 3463 ((inst >> 12) & 0b00000111)) { 3464 case 0: op = rv_op_fmv_s_x; break; 3465 case 8: op = rv_op_fli_s; break; 3466 } 3467 break; 3468 case 121: 3469 switch (((inst >> 17) & 0b11111000) | 3470 ((inst >> 12) & 0b00000111)) { 3471 case 0: op = rv_op_fmv_d_x; break; 3472 case 8: op = rv_op_fli_d; break; 3473 } 3474 break; 3475 case 122: 3476 switch (((inst >> 17) & 0b11111000) | 3477 ((inst >> 12) & 0b00000111)) { 3478 case 0: op = rv_op_fmv_h_x; break; 3479 case 8: op = rv_op_fli_h; break; 3480 } 3481 break; 3482 case 123: 3483 switch (((inst >> 17) & 0b11111000) | 3484 ((inst >> 12) & 0b00000111)) { 3485 case 0: op = rv_op_fmv_q_x; break; 3486 case 8: op = rv_op_fli_q; break; 3487 } 3488 break; 3489 } 3490 break; 3491 case 21: 3492 switch ((inst >> 12) & 0b111) { 3493 case 0: 3494 switch ((inst >> 26) & 0b111111) { 3495 case 0: op = rv_op_vadd_vv; break; 3496 case 1: op = rv_op_vandn_vv; break; 3497 case 2: op = rv_op_vsub_vv; break; 3498 case 4: op = rv_op_vminu_vv; break; 3499 case 5: op = rv_op_vmin_vv; break; 3500 case 6: op = rv_op_vmaxu_vv; break; 3501 case 7: op = rv_op_vmax_vv; break; 3502 case 9: op = rv_op_vand_vv; break; 3503 case 10: op = rv_op_vor_vv; break; 3504 case 11: op = rv_op_vxor_vv; break; 3505 case 12: op = rv_op_vrgather_vv; break; 3506 case 14: op = rv_op_vrgatherei16_vv; break; 3507 case 16: 3508 if (((inst >> 25) & 1) == 0) { 3509 op = rv_op_vadc_vvm; 3510 } 3511 break; 3512 case 17: op = rv_op_vmadc_vvm; break; 3513 case 18: 3514 if (((inst >> 25) & 1) == 0) { 3515 op = rv_op_vsbc_vvm; 3516 } 3517 break; 3518 case 19: op = rv_op_vmsbc_vvm; break; 3519 case 20: op = rv_op_vror_vv; break; 3520 case 21: op = rv_op_vrol_vv; break; 3521 case 23: 3522 if (((inst >> 20) & 0b111111) == 32) 3523 op = rv_op_vmv_v_v; 3524 else if (((inst >> 25) & 1) == 0) 3525 op = rv_op_vmerge_vvm; 3526 break; 3527 case 24: op = rv_op_vmseq_vv; break; 3528 case 25: op = rv_op_vmsne_vv; break; 3529 case 26: op = rv_op_vmsltu_vv; break; 3530 case 27: op = rv_op_vmslt_vv; break; 3531 case 28: op = rv_op_vmsleu_vv; break; 3532 case 29: op = rv_op_vmsle_vv; break; 3533 case 32: op = rv_op_vsaddu_vv; break; 3534 case 33: op = rv_op_vsadd_vv; break; 3535 case 34: op = rv_op_vssubu_vv; break; 3536 case 35: op = rv_op_vssub_vv; break; 3537 case 37: op = rv_op_vsll_vv; break; 3538 case 39: op = rv_op_vsmul_vv; break; 3539 case 40: op = rv_op_vsrl_vv; break; 3540 case 41: op = rv_op_vsra_vv; break; 3541 case 42: op = rv_op_vssrl_vv; break; 3542 case 43: op = rv_op_vssra_vv; break; 3543 case 44: op = rv_op_vnsrl_wv; break; 3544 case 45: op = rv_op_vnsra_wv; break; 3545 case 46: op = rv_op_vnclipu_wv; break; 3546 case 47: op = rv_op_vnclip_wv; break; 3547 case 48: op = rv_op_vwredsumu_vs; break; 3548 case 49: op = rv_op_vwredsum_vs; break; 3549 case 53: op = rv_op_vwsll_vv; break; 3550 } 3551 break; 3552 case 1: 3553 switch ((inst >> 26) & 0b111111) { 3554 case 0: op = rv_op_vfadd_vv; break; 3555 case 1: op = rv_op_vfredusum_vs; break; 3556 case 2: op = rv_op_vfsub_vv; break; 3557 case 3: op = rv_op_vfredosum_vs; break; 3558 case 4: op = rv_op_vfmin_vv; break; 3559 case 5: op = rv_op_vfredmin_vs; break; 3560 case 6: op = rv_op_vfmax_vv; break; 3561 case 7: op = rv_op_vfredmax_vs; break; 3562 case 8: op = rv_op_vfsgnj_vv; break; 3563 case 9: op = rv_op_vfsgnjn_vv; break; 3564 case 10: op = rv_op_vfsgnjx_vv; break; 3565 case 16: 3566 switch ((inst >> 15) & 0b11111) { 3567 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break; 3568 } 3569 break; 3570 case 18: 3571 switch ((inst >> 15) & 0b11111) { 3572 case 0: op = rv_op_vfcvt_xu_f_v; break; 3573 case 1: op = rv_op_vfcvt_x_f_v; break; 3574 case 2: op = rv_op_vfcvt_f_xu_v; break; 3575 case 3: op = rv_op_vfcvt_f_x_v; break; 3576 case 6: op = rv_op_vfcvt_rtz_xu_f_v; break; 3577 case 7: op = rv_op_vfcvt_rtz_x_f_v; break; 3578 case 8: op = rv_op_vfwcvt_xu_f_v; break; 3579 case 9: op = rv_op_vfwcvt_x_f_v; break; 3580 case 10: op = rv_op_vfwcvt_f_xu_v; break; 3581 case 11: op = rv_op_vfwcvt_f_x_v; break; 3582 case 12: op = rv_op_vfwcvt_f_f_v; break; 3583 case 13: op = rv_op_vfwcvtbf16_f_f_v; break; 3584 case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break; 3585 case 15: op = rv_op_vfwcvt_rtz_x_f_v; break; 3586 case 16: op = rv_op_vfncvt_xu_f_w; break; 3587 case 17: op = rv_op_vfncvt_x_f_w; break; 3588 case 18: op = rv_op_vfncvt_f_xu_w; break; 3589 case 19: op = rv_op_vfncvt_f_x_w; break; 3590 case 20: op = rv_op_vfncvt_f_f_w; break; 3591 case 21: op = rv_op_vfncvt_rod_f_f_w; break; 3592 case 22: op = rv_op_vfncvt_rtz_xu_f_w; break; 3593 case 23: op = rv_op_vfncvt_rtz_x_f_w; break; 3594 case 29: op = rv_op_vfncvtbf16_f_f_w; break; 3595 } 3596 break; 3597 case 19: 3598 switch ((inst >> 15) & 0b11111) { 3599 case 0: op = rv_op_vfsqrt_v; break; 3600 case 4: op = rv_op_vfrsqrt7_v; break; 3601 case 5: op = rv_op_vfrec7_v; break; 3602 case 16: op = rv_op_vfclass_v; break; 3603 } 3604 break; 3605 case 24: op = rv_op_vmfeq_vv; break; 3606 case 25: op = rv_op_vmfle_vv; break; 3607 case 27: op = rv_op_vmflt_vv; break; 3608 case 28: op = rv_op_vmfne_vv; break; 3609 case 32: op = rv_op_vfdiv_vv; break; 3610 case 36: op = rv_op_vfmul_vv; break; 3611 case 40: op = rv_op_vfmadd_vv; break; 3612 case 41: op = rv_op_vfnmadd_vv; break; 3613 case 42: op = rv_op_vfmsub_vv; break; 3614 case 43: op = rv_op_vfnmsub_vv; break; 3615 case 44: op = rv_op_vfmacc_vv; break; 3616 case 45: op = rv_op_vfnmacc_vv; break; 3617 case 46: op = rv_op_vfmsac_vv; break; 3618 case 47: op = rv_op_vfnmsac_vv; break; 3619 case 48: op = rv_op_vfwadd_vv; break; 3620 case 49: op = rv_op_vfwredusum_vs; break; 3621 case 50: op = rv_op_vfwsub_vv; break; 3622 case 51: op = rv_op_vfwredosum_vs; break; 3623 case 52: op = rv_op_vfwadd_wv; break; 3624 case 54: op = rv_op_vfwsub_wv; break; 3625 case 56: op = rv_op_vfwmul_vv; break; 3626 case 59: op = rv_op_vfwmaccbf16_vv; break; 3627 case 60: op = rv_op_vfwmacc_vv; break; 3628 case 61: op = rv_op_vfwnmacc_vv; break; 3629 case 62: op = rv_op_vfwmsac_vv; break; 3630 case 63: op = rv_op_vfwnmsac_vv; break; 3631 } 3632 break; 3633 case 2: 3634 switch ((inst >> 26) & 0b111111) { 3635 case 0: op = rv_op_vredsum_vs; break; 3636 case 1: op = rv_op_vredand_vs; break; 3637 case 2: op = rv_op_vredor_vs; break; 3638 case 3: op = rv_op_vredxor_vs; break; 3639 case 4: op = rv_op_vredminu_vs; break; 3640 case 5: op = rv_op_vredmin_vs; break; 3641 case 6: op = rv_op_vredmaxu_vs; break; 3642 case 7: op = rv_op_vredmax_vs; break; 3643 case 8: op = rv_op_vaaddu_vv; break; 3644 case 9: op = rv_op_vaadd_vv; break; 3645 case 10: op = rv_op_vasubu_vv; break; 3646 case 11: op = rv_op_vasub_vv; break; 3647 case 12: op = rv_op_vclmul_vv; break; 3648 case 13: op = rv_op_vclmulh_vv; break; 3649 case 16: 3650 switch ((inst >> 15) & 0b11111) { 3651 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break; 3652 case 16: op = rv_op_vcpop_m; break; 3653 case 17: op = rv_op_vfirst_m; break; 3654 } 3655 break; 3656 case 18: 3657 switch ((inst >> 15) & 0b11111) { 3658 case 2: op = rv_op_vzext_vf8; break; 3659 case 3: op = rv_op_vsext_vf8; break; 3660 case 4: op = rv_op_vzext_vf4; break; 3661 case 5: op = rv_op_vsext_vf4; break; 3662 case 6: op = rv_op_vzext_vf2; break; 3663 case 7: op = rv_op_vsext_vf2; break; 3664 case 8: op = rv_op_vbrev8_v; break; 3665 case 9: op = rv_op_vrev8_v; break; 3666 case 10: op = rv_op_vbrev_v; break; 3667 case 12: op = rv_op_vclz_v; break; 3668 case 13: op = rv_op_vctz_v; break; 3669 case 14: op = rv_op_vcpop_v; break; 3670 } 3671 break; 3672 case 20: 3673 switch ((inst >> 15) & 0b11111) { 3674 case 1: op = rv_op_vmsbf_m; break; 3675 case 2: op = rv_op_vmsof_m; break; 3676 case 3: op = rv_op_vmsif_m; break; 3677 case 16: op = rv_op_viota_m; break; 3678 case 17: 3679 if (((inst >> 20) & 0b11111) == 0) { 3680 op = rv_op_vid_v; 3681 } 3682 break; 3683 } 3684 break; 3685 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break; 3686 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break; 3687 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break; 3688 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break; 3689 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break; 3690 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break; 3691 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break; 3692 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break; 3693 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break; 3694 case 32: op = rv_op_vdivu_vv; break; 3695 case 33: op = rv_op_vdiv_vv; break; 3696 case 34: op = rv_op_vremu_vv; break; 3697 case 35: op = rv_op_vrem_vv; break; 3698 case 36: op = rv_op_vmulhu_vv; break; 3699 case 37: op = rv_op_vmul_vv; break; 3700 case 38: op = rv_op_vmulhsu_vv; break; 3701 case 39: op = rv_op_vmulh_vv; break; 3702 case 41: op = rv_op_vmadd_vv; break; 3703 case 43: op = rv_op_vnmsub_vv; break; 3704 case 45: op = rv_op_vmacc_vv; break; 3705 case 47: op = rv_op_vnmsac_vv; break; 3706 case 48: op = rv_op_vwaddu_vv; break; 3707 case 49: op = rv_op_vwadd_vv; break; 3708 case 50: op = rv_op_vwsubu_vv; break; 3709 case 51: op = rv_op_vwsub_vv; break; 3710 case 52: op = rv_op_vwaddu_wv; break; 3711 case 53: op = rv_op_vwadd_wv; break; 3712 case 54: op = rv_op_vwsubu_wv; break; 3713 case 55: op = rv_op_vwsub_wv; break; 3714 case 56: op = rv_op_vwmulu_vv; break; 3715 case 58: op = rv_op_vwmulsu_vv; break; 3716 case 59: op = rv_op_vwmul_vv; break; 3717 case 60: op = rv_op_vwmaccu_vv; break; 3718 case 61: op = rv_op_vwmacc_vv; break; 3719 case 63: op = rv_op_vwmaccsu_vv; break; 3720 } 3721 break; 3722 case 3: 3723 switch ((inst >> 26) & 0b111111) { 3724 case 0: op = rv_op_vadd_vi; break; 3725 case 3: op = rv_op_vrsub_vi; break; 3726 case 9: op = rv_op_vand_vi; break; 3727 case 10: op = rv_op_vor_vi; break; 3728 case 11: op = rv_op_vxor_vi; break; 3729 case 12: op = rv_op_vrgather_vi; break; 3730 case 14: op = rv_op_vslideup_vi; break; 3731 case 15: op = rv_op_vslidedown_vi; break; 3732 case 16: 3733 if (((inst >> 25) & 1) == 0) { 3734 op = rv_op_vadc_vim; 3735 } 3736 break; 3737 case 17: op = rv_op_vmadc_vim; break; 3738 case 20: case 21: op = rv_op_vror_vi; break; 3739 case 23: 3740 if (((inst >> 20) & 0b111111) == 32) 3741 op = rv_op_vmv_v_i; 3742 else if (((inst >> 25) & 1) == 0) 3743 op = rv_op_vmerge_vim; 3744 break; 3745 case 24: op = rv_op_vmseq_vi; break; 3746 case 25: op = rv_op_vmsne_vi; break; 3747 case 28: op = rv_op_vmsleu_vi; break; 3748 case 29: op = rv_op_vmsle_vi; break; 3749 case 30: op = rv_op_vmsgtu_vi; break; 3750 case 31: op = rv_op_vmsgt_vi; break; 3751 case 32: op = rv_op_vsaddu_vi; break; 3752 case 33: op = rv_op_vsadd_vi; break; 3753 case 37: op = rv_op_vsll_vi; break; 3754 case 39: 3755 switch ((inst >> 15) & 0b11111) { 3756 case 0: op = rv_op_vmv1r_v; break; 3757 case 1: op = rv_op_vmv2r_v; break; 3758 case 3: op = rv_op_vmv4r_v; break; 3759 case 7: op = rv_op_vmv8r_v; break; 3760 } 3761 break; 3762 case 40: op = rv_op_vsrl_vi; break; 3763 case 41: op = rv_op_vsra_vi; break; 3764 case 42: op = rv_op_vssrl_vi; break; 3765 case 43: op = rv_op_vssra_vi; break; 3766 case 44: op = rv_op_vnsrl_wi; break; 3767 case 45: op = rv_op_vnsra_wi; break; 3768 case 46: op = rv_op_vnclipu_wi; break; 3769 case 47: op = rv_op_vnclip_wi; break; 3770 case 53: op = rv_op_vwsll_vi; break; 3771 } 3772 break; 3773 case 4: 3774 switch ((inst >> 26) & 0b111111) { 3775 case 0: op = rv_op_vadd_vx; break; 3776 case 1: op = rv_op_vandn_vx; break; 3777 case 2: op = rv_op_vsub_vx; break; 3778 case 3: op = rv_op_vrsub_vx; break; 3779 case 4: op = rv_op_vminu_vx; break; 3780 case 5: op = rv_op_vmin_vx; break; 3781 case 6: op = rv_op_vmaxu_vx; break; 3782 case 7: op = rv_op_vmax_vx; break; 3783 case 9: op = rv_op_vand_vx; break; 3784 case 10: op = rv_op_vor_vx; break; 3785 case 11: op = rv_op_vxor_vx; break; 3786 case 12: op = rv_op_vrgather_vx; break; 3787 case 14: op = rv_op_vslideup_vx; break; 3788 case 15: op = rv_op_vslidedown_vx; break; 3789 case 16: 3790 if (((inst >> 25) & 1) == 0) { 3791 op = rv_op_vadc_vxm; 3792 } 3793 break; 3794 case 17: op = rv_op_vmadc_vxm; break; 3795 case 18: 3796 if (((inst >> 25) & 1) == 0) { 3797 op = rv_op_vsbc_vxm; 3798 } 3799 break; 3800 case 19: op = rv_op_vmsbc_vxm; break; 3801 case 20: op = rv_op_vror_vx; break; 3802 case 21: op = rv_op_vrol_vx; break; 3803 case 23: 3804 if (((inst >> 20) & 0b111111) == 32) 3805 op = rv_op_vmv_v_x; 3806 else if (((inst >> 25) & 1) == 0) 3807 op = rv_op_vmerge_vxm; 3808 break; 3809 case 24: op = rv_op_vmseq_vx; break; 3810 case 25: op = rv_op_vmsne_vx; break; 3811 case 26: op = rv_op_vmsltu_vx; break; 3812 case 27: op = rv_op_vmslt_vx; break; 3813 case 28: op = rv_op_vmsleu_vx; break; 3814 case 29: op = rv_op_vmsle_vx; break; 3815 case 30: op = rv_op_vmsgtu_vx; break; 3816 case 31: op = rv_op_vmsgt_vx; break; 3817 case 32: op = rv_op_vsaddu_vx; break; 3818 case 33: op = rv_op_vsadd_vx; break; 3819 case 34: op = rv_op_vssubu_vx; break; 3820 case 35: op = rv_op_vssub_vx; break; 3821 case 37: op = rv_op_vsll_vx; break; 3822 case 39: op = rv_op_vsmul_vx; break; 3823 case 40: op = rv_op_vsrl_vx; break; 3824 case 41: op = rv_op_vsra_vx; break; 3825 case 42: op = rv_op_vssrl_vx; break; 3826 case 43: op = rv_op_vssra_vx; break; 3827 case 44: op = rv_op_vnsrl_wx; break; 3828 case 45: op = rv_op_vnsra_wx; break; 3829 case 46: op = rv_op_vnclipu_wx; break; 3830 case 47: op = rv_op_vnclip_wx; break; 3831 case 53: op = rv_op_vwsll_vx; break; 3832 } 3833 break; 3834 case 5: 3835 switch ((inst >> 26) & 0b111111) { 3836 case 0: op = rv_op_vfadd_vf; break; 3837 case 2: op = rv_op_vfsub_vf; break; 3838 case 4: op = rv_op_vfmin_vf; break; 3839 case 6: op = rv_op_vfmax_vf; break; 3840 case 8: op = rv_op_vfsgnj_vf; break; 3841 case 9: op = rv_op_vfsgnjn_vf; break; 3842 case 10: op = rv_op_vfsgnjx_vf; break; 3843 case 14: op = rv_op_vfslide1up_vf; break; 3844 case 15: op = rv_op_vfslide1down_vf; break; 3845 case 16: 3846 switch ((inst >> 20) & 0b11111) { 3847 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break; 3848 } 3849 break; 3850 case 23: 3851 if (((inst >> 25) & 1) == 0) 3852 op = rv_op_vfmerge_vfm; 3853 else if (((inst >> 20) & 0b111111) == 32) 3854 op = rv_op_vfmv_v_f; 3855 break; 3856 case 24: op = rv_op_vmfeq_vf; break; 3857 case 25: op = rv_op_vmfle_vf; break; 3858 case 27: op = rv_op_vmflt_vf; break; 3859 case 28: op = rv_op_vmfne_vf; break; 3860 case 29: op = rv_op_vmfgt_vf; break; 3861 case 31: op = rv_op_vmfge_vf; break; 3862 case 32: op = rv_op_vfdiv_vf; break; 3863 case 33: op = rv_op_vfrdiv_vf; break; 3864 case 36: op = rv_op_vfmul_vf; break; 3865 case 39: op = rv_op_vfrsub_vf; break; 3866 case 40: op = rv_op_vfmadd_vf; break; 3867 case 41: op = rv_op_vfnmadd_vf; break; 3868 case 42: op = rv_op_vfmsub_vf; break; 3869 case 43: op = rv_op_vfnmsub_vf; break; 3870 case 44: op = rv_op_vfmacc_vf; break; 3871 case 45: op = rv_op_vfnmacc_vf; break; 3872 case 46: op = rv_op_vfmsac_vf; break; 3873 case 47: op = rv_op_vfnmsac_vf; break; 3874 case 48: op = rv_op_vfwadd_vf; break; 3875 case 50: op = rv_op_vfwsub_vf; break; 3876 case 52: op = rv_op_vfwadd_wf; break; 3877 case 54: op = rv_op_vfwsub_wf; break; 3878 case 56: op = rv_op_vfwmul_vf; break; 3879 case 59: op = rv_op_vfwmaccbf16_vf; break; 3880 case 60: op = rv_op_vfwmacc_vf; break; 3881 case 61: op = rv_op_vfwnmacc_vf; break; 3882 case 62: op = rv_op_vfwmsac_vf; break; 3883 case 63: op = rv_op_vfwnmsac_vf; break; 3884 } 3885 break; 3886 case 6: 3887 switch ((inst >> 26) & 0b111111) { 3888 case 8: op = rv_op_vaaddu_vx; break; 3889 case 9: op = rv_op_vaadd_vx; break; 3890 case 10: op = rv_op_vasubu_vx; break; 3891 case 11: op = rv_op_vasub_vx; break; 3892 case 12: op = rv_op_vclmul_vx; break; 3893 case 13: op = rv_op_vclmulh_vx; break; 3894 case 14: op = rv_op_vslide1up_vx; break; 3895 case 15: op = rv_op_vslide1down_vx; break; 3896 case 16: 3897 switch ((inst >> 20) & 0b11111) { 3898 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break; 3899 } 3900 break; 3901 case 32: op = rv_op_vdivu_vx; break; 3902 case 33: op = rv_op_vdiv_vx; break; 3903 case 34: op = rv_op_vremu_vx; break; 3904 case 35: op = rv_op_vrem_vx; break; 3905 case 36: op = rv_op_vmulhu_vx; break; 3906 case 37: op = rv_op_vmul_vx; break; 3907 case 38: op = rv_op_vmulhsu_vx; break; 3908 case 39: op = rv_op_vmulh_vx; break; 3909 case 41: op = rv_op_vmadd_vx; break; 3910 case 43: op = rv_op_vnmsub_vx; break; 3911 case 45: op = rv_op_vmacc_vx; break; 3912 case 47: op = rv_op_vnmsac_vx; break; 3913 case 48: op = rv_op_vwaddu_vx; break; 3914 case 49: op = rv_op_vwadd_vx; break; 3915 case 50: op = rv_op_vwsubu_vx; break; 3916 case 51: op = rv_op_vwsub_vx; break; 3917 case 52: op = rv_op_vwaddu_wx; break; 3918 case 53: op = rv_op_vwadd_wx; break; 3919 case 54: op = rv_op_vwsubu_wx; break; 3920 case 55: op = rv_op_vwsub_wx; break; 3921 case 56: op = rv_op_vwmulu_vx; break; 3922 case 58: op = rv_op_vwmulsu_vx; break; 3923 case 59: op = rv_op_vwmul_vx; break; 3924 case 60: op = rv_op_vwmaccu_vx; break; 3925 case 61: op = rv_op_vwmacc_vx; break; 3926 case 62: op = rv_op_vwmaccus_vx; break; 3927 case 63: op = rv_op_vwmaccsu_vx; break; 3928 } 3929 break; 3930 case 7: 3931 if (((inst >> 31) & 1) == 0) { 3932 op = rv_op_vsetvli; 3933 } else if ((inst >> 30) & 1) { 3934 op = rv_op_vsetivli; 3935 } else if (((inst >> 25) & 0b11111) == 0) { 3936 op = rv_op_vsetvl; 3937 } 3938 break; 3939 } 3940 break; 3941 case 22: 3942 switch ((inst >> 12) & 0b111) { 3943 case 0: op = rv_op_addid; break; 3944 case 1: 3945 switch ((inst >> 26) & 0b111111) { 3946 case 0: op = rv_op_sllid; break; 3947 } 3948 break; 3949 case 5: 3950 switch ((inst >> 26) & 0b111111) { 3951 case 0: op = rv_op_srlid; break; 3952 case 16: op = rv_op_sraid; break; 3953 } 3954 break; 3955 } 3956 break; 3957 case 24: 3958 switch ((inst >> 12) & 0b111) { 3959 case 0: op = rv_op_beq; break; 3960 case 1: op = rv_op_bne; break; 3961 case 4: op = rv_op_blt; break; 3962 case 5: op = rv_op_bge; break; 3963 case 6: op = rv_op_bltu; break; 3964 case 7: op = rv_op_bgeu; break; 3965 } 3966 break; 3967 case 25: 3968 switch ((inst >> 12) & 0b111) { 3969 case 0: op = rv_op_jalr; break; 3970 } 3971 break; 3972 case 27: op = rv_op_jal; break; 3973 case 28: 3974 switch ((inst >> 12) & 0b111) { 3975 case 0: 3976 switch (((inst >> 20) & 0b111111100000) | 3977 ((inst >> 7) & 0b000000011111)) { 3978 case 0: 3979 switch ((inst >> 15) & 0b1111111111) { 3980 case 0: op = rv_op_ecall; break; 3981 case 32: op = rv_op_ebreak; break; 3982 case 64: op = rv_op_uret; break; 3983 } 3984 break; 3985 case 256: 3986 switch ((inst >> 20) & 0b11111) { 3987 case 2: 3988 switch ((inst >> 15) & 0b11111) { 3989 case 0: op = rv_op_sret; break; 3990 } 3991 break; 3992 case 4: op = rv_op_sfence_vm; break; 3993 case 5: 3994 switch ((inst >> 15) & 0b11111) { 3995 case 0: op = rv_op_wfi; break; 3996 } 3997 break; 3998 } 3999 break; 4000 case 288: op = rv_op_sfence_vma; break; 4001 case 512: 4002 switch ((inst >> 15) & 0b1111111111) { 4003 case 64: op = rv_op_hret; break; 4004 } 4005 break; 4006 case 768: 4007 switch ((inst >> 15) & 0b1111111111) { 4008 case 64: op = rv_op_mret; break; 4009 } 4010 break; 4011 case 1952: 4012 switch ((inst >> 15) & 0b1111111111) { 4013 case 576: op = rv_op_dret; break; 4014 } 4015 break; 4016 } 4017 break; 4018 case 1: op = rv_op_csrrw; break; 4019 case 2: op = rv_op_csrrs; break; 4020 case 3: op = rv_op_csrrc; break; 4021 case 4: 4022 if (dec->cfg->ext_zimop) { 4023 int imm_mop5, imm_mop3; 4024 if ((extract32(inst, 22, 10) & 0b1011001111) 4025 == 0b1000000111) { 4026 imm_mop5 = deposit32(deposit32(extract32(inst, 20, 2), 4027 2, 2, 4028 extract32(inst, 26, 2)), 4029 4, 1, extract32(inst, 30, 1)); 4030 op = rv_mop_r_0 + imm_mop5; 4031 } else if ((extract32(inst, 25, 7) & 0b1011001) 4032 == 0b1000001) { 4033 imm_mop3 = deposit32(extract32(inst, 26, 2), 4034 2, 1, extract32(inst, 30, 1)); 4035 op = rv_mop_rr_0 + imm_mop3; 4036 } 4037 } 4038 break; 4039 case 5: op = rv_op_csrrwi; break; 4040 case 6: op = rv_op_csrrsi; break; 4041 case 7: op = rv_op_csrrci; break; 4042 } 4043 break; 4044 case 29: 4045 if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) { 4046 switch ((inst >> 26) & 0b111111) { 4047 case 32: op = rv_op_vsm3me_vv; break; 4048 case 33: op = rv_op_vsm4k_vi; break; 4049 case 34: op = rv_op_vaeskf1_vi; break; 4050 case 40: 4051 switch ((inst >> 15) & 0b11111) { 4052 case 0: op = rv_op_vaesdm_vv; break; 4053 case 1: op = rv_op_vaesdf_vv; break; 4054 case 2: op = rv_op_vaesem_vv; break; 4055 case 3: op = rv_op_vaesef_vv; break; 4056 case 16: op = rv_op_vsm4r_vv; break; 4057 case 17: op = rv_op_vgmul_vv; break; 4058 } 4059 break; 4060 case 41: 4061 switch ((inst >> 15) & 0b11111) { 4062 case 0: op = rv_op_vaesdm_vs; break; 4063 case 1: op = rv_op_vaesdf_vs; break; 4064 case 2: op = rv_op_vaesem_vs; break; 4065 case 3: op = rv_op_vaesef_vs; break; 4066 case 7: op = rv_op_vaesz_vs; break; 4067 case 16: op = rv_op_vsm4r_vs; break; 4068 } 4069 break; 4070 case 42: op = rv_op_vaeskf2_vi; break; 4071 case 43: op = rv_op_vsm3c_vi; break; 4072 case 44: op = rv_op_vghsh_vv; break; 4073 case 45: op = rv_op_vsha2ms_vv; break; 4074 case 46: op = rv_op_vsha2ch_vv; break; 4075 case 47: op = rv_op_vsha2cl_vv; break; 4076 } 4077 } 4078 break; 4079 case 30: 4080 switch (((inst >> 22) & 0b1111111000) | 4081 ((inst >> 12) & 0b0000000111)) { 4082 case 0: op = rv_op_addd; break; 4083 case 1: op = rv_op_slld; break; 4084 case 5: op = rv_op_srld; break; 4085 case 8: op = rv_op_muld; break; 4086 case 12: op = rv_op_divd; break; 4087 case 13: op = rv_op_divud; break; 4088 case 14: op = rv_op_remd; break; 4089 case 15: op = rv_op_remud; break; 4090 case 256: op = rv_op_subd; break; 4091 case 261: op = rv_op_srad; break; 4092 } 4093 break; 4094 } 4095 break; 4096 } 4097 dec->op = op; 4098 } 4099 4100 /* operand extractors */ 4101 4102 static uint32_t operand_rd(rv_inst inst) 4103 { 4104 return (inst << 52) >> 59; 4105 } 4106 4107 static uint32_t operand_rs1(rv_inst inst) 4108 { 4109 return (inst << 44) >> 59; 4110 } 4111 4112 static uint32_t operand_rs2(rv_inst inst) 4113 { 4114 return (inst << 39) >> 59; 4115 } 4116 4117 static uint32_t operand_rs3(rv_inst inst) 4118 { 4119 return (inst << 32) >> 59; 4120 } 4121 4122 static uint32_t operand_aq(rv_inst inst) 4123 { 4124 return (inst << 37) >> 63; 4125 } 4126 4127 static uint32_t operand_rl(rv_inst inst) 4128 { 4129 return (inst << 38) >> 63; 4130 } 4131 4132 static uint32_t operand_pred(rv_inst inst) 4133 { 4134 return (inst << 36) >> 60; 4135 } 4136 4137 static uint32_t operand_succ(rv_inst inst) 4138 { 4139 return (inst << 40) >> 60; 4140 } 4141 4142 static uint32_t operand_rm(rv_inst inst) 4143 { 4144 return (inst << 49) >> 61; 4145 } 4146 4147 static uint32_t operand_shamt5(rv_inst inst) 4148 { 4149 return (inst << 39) >> 59; 4150 } 4151 4152 static uint32_t operand_shamt6(rv_inst inst) 4153 { 4154 return (inst << 38) >> 58; 4155 } 4156 4157 static uint32_t operand_shamt7(rv_inst inst) 4158 { 4159 return (inst << 37) >> 57; 4160 } 4161 4162 static uint32_t operand_crdq(rv_inst inst) 4163 { 4164 return (inst << 59) >> 61; 4165 } 4166 4167 static uint32_t operand_crs1q(rv_inst inst) 4168 { 4169 return (inst << 54) >> 61; 4170 } 4171 4172 static uint32_t operand_crs1rdq(rv_inst inst) 4173 { 4174 return (inst << 54) >> 61; 4175 } 4176 4177 static uint32_t operand_crs2q(rv_inst inst) 4178 { 4179 return (inst << 59) >> 61; 4180 } 4181 4182 static uint32_t calculate_xreg(uint32_t sreg) 4183 { 4184 return sreg < 2 ? sreg + 8 : sreg + 16; 4185 } 4186 4187 static uint32_t operand_sreg1(rv_inst inst) 4188 { 4189 return calculate_xreg((inst << 54) >> 61); 4190 } 4191 4192 static uint32_t operand_sreg2(rv_inst inst) 4193 { 4194 return calculate_xreg((inst << 59) >> 61); 4195 } 4196 4197 static uint32_t operand_crd(rv_inst inst) 4198 { 4199 return (inst << 52) >> 59; 4200 } 4201 4202 static uint32_t operand_crs1(rv_inst inst) 4203 { 4204 return (inst << 52) >> 59; 4205 } 4206 4207 static uint32_t operand_crs1rd(rv_inst inst) 4208 { 4209 return (inst << 52) >> 59; 4210 } 4211 4212 static uint32_t operand_crs2(rv_inst inst) 4213 { 4214 return (inst << 57) >> 59; 4215 } 4216 4217 static uint32_t operand_cimmsh5(rv_inst inst) 4218 { 4219 return (inst << 57) >> 59; 4220 } 4221 4222 static uint32_t operand_csr12(rv_inst inst) 4223 { 4224 return (inst << 32) >> 52; 4225 } 4226 4227 static int32_t operand_imm12(rv_inst inst) 4228 { 4229 return ((int64_t)inst << 32) >> 52; 4230 } 4231 4232 static int32_t operand_imm20(rv_inst inst) 4233 { 4234 return (((int64_t)inst << 32) >> 44) << 12; 4235 } 4236 4237 static int32_t operand_jimm20(rv_inst inst) 4238 { 4239 return (((int64_t)inst << 32) >> 63) << 20 | 4240 ((inst << 33) >> 54) << 1 | 4241 ((inst << 43) >> 63) << 11 | 4242 ((inst << 44) >> 56) << 12; 4243 } 4244 4245 static int32_t operand_simm12(rv_inst inst) 4246 { 4247 return (((int64_t)inst << 32) >> 57) << 5 | 4248 (inst << 52) >> 59; 4249 } 4250 4251 static int32_t operand_sbimm12(rv_inst inst) 4252 { 4253 return (((int64_t)inst << 32) >> 63) << 12 | 4254 ((inst << 33) >> 58) << 5 | 4255 ((inst << 52) >> 60) << 1 | 4256 ((inst << 56) >> 63) << 11; 4257 } 4258 4259 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) 4260 { 4261 int imm = ((inst << 51) >> 63) << 5 | 4262 (inst << 57) >> 59; 4263 if (isa == rv128) { 4264 imm = imm ? imm : 64; 4265 } 4266 return imm; 4267 } 4268 4269 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) 4270 { 4271 int imm = ((inst << 51) >> 63) << 5 | 4272 (inst << 57) >> 59; 4273 if (isa == rv128) { 4274 imm = imm | (imm & 32) << 1; 4275 imm = imm ? imm : 64; 4276 } 4277 return imm; 4278 } 4279 4280 static int32_t operand_cimmi(rv_inst inst) 4281 { 4282 return (((int64_t)inst << 51) >> 63) << 5 | 4283 (inst << 57) >> 59; 4284 } 4285 4286 static int32_t operand_cimmui(rv_inst inst) 4287 { 4288 return (((int64_t)inst << 51) >> 63) << 17 | 4289 ((inst << 57) >> 59) << 12; 4290 } 4291 4292 static uint32_t operand_cimmlwsp(rv_inst inst) 4293 { 4294 return ((inst << 51) >> 63) << 5 | 4295 ((inst << 57) >> 61) << 2 | 4296 ((inst << 60) >> 62) << 6; 4297 } 4298 4299 static uint32_t operand_cimmldsp(rv_inst inst) 4300 { 4301 return ((inst << 51) >> 63) << 5 | 4302 ((inst << 57) >> 62) << 3 | 4303 ((inst << 59) >> 61) << 6; 4304 } 4305 4306 static uint32_t operand_cimmlqsp(rv_inst inst) 4307 { 4308 return ((inst << 51) >> 63) << 5 | 4309 ((inst << 57) >> 63) << 4 | 4310 ((inst << 58) >> 60) << 6; 4311 } 4312 4313 static int32_t operand_cimm16sp(rv_inst inst) 4314 { 4315 return (((int64_t)inst << 51) >> 63) << 9 | 4316 ((inst << 57) >> 63) << 4 | 4317 ((inst << 58) >> 63) << 6 | 4318 ((inst << 59) >> 62) << 7 | 4319 ((inst << 61) >> 63) << 5; 4320 } 4321 4322 static int32_t operand_cimmj(rv_inst inst) 4323 { 4324 return (((int64_t)inst << 51) >> 63) << 11 | 4325 ((inst << 52) >> 63) << 4 | 4326 ((inst << 53) >> 62) << 8 | 4327 ((inst << 55) >> 63) << 10 | 4328 ((inst << 56) >> 63) << 6 | 4329 ((inst << 57) >> 63) << 7 | 4330 ((inst << 58) >> 61) << 1 | 4331 ((inst << 61) >> 63) << 5; 4332 } 4333 4334 static int32_t operand_cimmb(rv_inst inst) 4335 { 4336 return (((int64_t)inst << 51) >> 63) << 8 | 4337 ((inst << 52) >> 62) << 3 | 4338 ((inst << 57) >> 62) << 6 | 4339 ((inst << 59) >> 62) << 1 | 4340 ((inst << 61) >> 63) << 5; 4341 } 4342 4343 static uint32_t operand_cimmswsp(rv_inst inst) 4344 { 4345 return ((inst << 51) >> 60) << 2 | 4346 ((inst << 55) >> 62) << 6; 4347 } 4348 4349 static uint32_t operand_cimmsdsp(rv_inst inst) 4350 { 4351 return ((inst << 51) >> 61) << 3 | 4352 ((inst << 54) >> 61) << 6; 4353 } 4354 4355 static uint32_t operand_cimmsqsp(rv_inst inst) 4356 { 4357 return ((inst << 51) >> 62) << 4 | 4358 ((inst << 53) >> 60) << 6; 4359 } 4360 4361 static uint32_t operand_cimm4spn(rv_inst inst) 4362 { 4363 return ((inst << 51) >> 62) << 4 | 4364 ((inst << 53) >> 60) << 6 | 4365 ((inst << 57) >> 63) << 2 | 4366 ((inst << 58) >> 63) << 3; 4367 } 4368 4369 static uint32_t operand_cimmw(rv_inst inst) 4370 { 4371 return ((inst << 51) >> 61) << 3 | 4372 ((inst << 57) >> 63) << 2 | 4373 ((inst << 58) >> 63) << 6; 4374 } 4375 4376 static uint32_t operand_cimmd(rv_inst inst) 4377 { 4378 return ((inst << 51) >> 61) << 3 | 4379 ((inst << 57) >> 62) << 6; 4380 } 4381 4382 static uint32_t operand_cimmq(rv_inst inst) 4383 { 4384 return ((inst << 51) >> 62) << 4 | 4385 ((inst << 53) >> 63) << 8 | 4386 ((inst << 57) >> 62) << 6; 4387 } 4388 4389 static uint32_t operand_vimm(rv_inst inst) 4390 { 4391 return (int64_t)(inst << 44) >> 59; 4392 } 4393 4394 static uint32_t operand_vzimm11(rv_inst inst) 4395 { 4396 return (inst << 33) >> 53; 4397 } 4398 4399 static uint32_t operand_vzimm10(rv_inst inst) 4400 { 4401 return (inst << 34) >> 54; 4402 } 4403 4404 static uint32_t operand_vzimm6(rv_inst inst) 4405 { 4406 return ((inst << 37) >> 63) << 5 | 4407 ((inst << 44) >> 59); 4408 } 4409 4410 static uint32_t operand_bs(rv_inst inst) 4411 { 4412 return (inst << 32) >> 62; 4413 } 4414 4415 static uint32_t operand_rnum(rv_inst inst) 4416 { 4417 return (inst << 40) >> 60; 4418 } 4419 4420 static uint32_t operand_vm(rv_inst inst) 4421 { 4422 return (inst << 38) >> 63; 4423 } 4424 4425 static uint32_t operand_uimm_c_lb(rv_inst inst) 4426 { 4427 return (((inst << 58) >> 63) << 1) | 4428 ((inst << 57) >> 63); 4429 } 4430 4431 static uint32_t operand_uimm_c_lh(rv_inst inst) 4432 { 4433 return (((inst << 58) >> 63) << 1); 4434 } 4435 4436 static uint32_t operand_zcmp_spimm(rv_inst inst) 4437 { 4438 return ((inst << 60) >> 62) << 4; 4439 } 4440 4441 static uint32_t operand_zcmp_rlist(rv_inst inst) 4442 { 4443 return ((inst << 56) >> 60); 4444 } 4445 4446 static uint32_t operand_imm6(rv_inst inst) 4447 { 4448 return (inst << 38) >> 60; 4449 } 4450 4451 static uint32_t operand_imm2(rv_inst inst) 4452 { 4453 return (inst << 37) >> 62; 4454 } 4455 4456 static uint32_t operand_immh(rv_inst inst) 4457 { 4458 return (inst << 32) >> 58; 4459 } 4460 4461 static uint32_t operand_imml(rv_inst inst) 4462 { 4463 return (inst << 38) >> 58; 4464 } 4465 4466 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm) 4467 { 4468 int xlen_bytes_log2 = isa == rv64 ? 3 : 2; 4469 int regs = rlist == 15 ? 13 : rlist - 3; 4470 uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16); 4471 return stack_adj_base + spimm; 4472 } 4473 4474 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa) 4475 { 4476 return calculate_stack_adj(isa, operand_zcmp_rlist(inst), 4477 operand_zcmp_spimm(inst)); 4478 } 4479 4480 static uint32_t operand_tbl_index(rv_inst inst) 4481 { 4482 return ((inst << 54) >> 56); 4483 } 4484 4485 /* decode operands */ 4486 4487 static void decode_inst_operands(rv_decode *dec, rv_isa isa) 4488 { 4489 const rv_opcode_data *opcode_data = dec->opcode_data; 4490 rv_inst inst = dec->inst; 4491 dec->codec = opcode_data[dec->op].codec; 4492 switch (dec->codec) { 4493 case rv_codec_none: 4494 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4495 dec->imm = 0; 4496 break; 4497 case rv_codec_u: 4498 dec->rd = operand_rd(inst); 4499 dec->rs1 = dec->rs2 = rv_ireg_zero; 4500 dec->imm = operand_imm20(inst); 4501 break; 4502 case rv_codec_uj: 4503 dec->rd = operand_rd(inst); 4504 dec->rs1 = dec->rs2 = rv_ireg_zero; 4505 dec->imm = operand_jimm20(inst); 4506 break; 4507 case rv_codec_i: 4508 dec->rd = operand_rd(inst); 4509 dec->rs1 = operand_rs1(inst); 4510 dec->rs2 = rv_ireg_zero; 4511 dec->imm = operand_imm12(inst); 4512 break; 4513 case rv_codec_i_sh5: 4514 dec->rd = operand_rd(inst); 4515 dec->rs1 = operand_rs1(inst); 4516 dec->rs2 = rv_ireg_zero; 4517 dec->imm = operand_shamt5(inst); 4518 break; 4519 case rv_codec_i_sh6: 4520 dec->rd = operand_rd(inst); 4521 dec->rs1 = operand_rs1(inst); 4522 dec->rs2 = rv_ireg_zero; 4523 dec->imm = operand_shamt6(inst); 4524 break; 4525 case rv_codec_i_sh7: 4526 dec->rd = operand_rd(inst); 4527 dec->rs1 = operand_rs1(inst); 4528 dec->rs2 = rv_ireg_zero; 4529 dec->imm = operand_shamt7(inst); 4530 break; 4531 case rv_codec_i_csr: 4532 dec->rd = operand_rd(inst); 4533 dec->rs1 = operand_rs1(inst); 4534 dec->rs2 = rv_ireg_zero; 4535 dec->imm = operand_csr12(inst); 4536 break; 4537 case rv_codec_s: 4538 dec->rd = rv_ireg_zero; 4539 dec->rs1 = operand_rs1(inst); 4540 dec->rs2 = operand_rs2(inst); 4541 dec->imm = operand_simm12(inst); 4542 break; 4543 case rv_codec_sb: 4544 dec->rd = rv_ireg_zero; 4545 dec->rs1 = operand_rs1(inst); 4546 dec->rs2 = operand_rs2(inst); 4547 dec->imm = operand_sbimm12(inst); 4548 break; 4549 case rv_codec_r: 4550 dec->rd = operand_rd(inst); 4551 dec->rs1 = operand_rs1(inst); 4552 dec->rs2 = operand_rs2(inst); 4553 dec->imm = 0; 4554 break; 4555 case rv_codec_r_m: 4556 dec->rd = operand_rd(inst); 4557 dec->rs1 = operand_rs1(inst); 4558 dec->rs2 = operand_rs2(inst); 4559 dec->imm = 0; 4560 dec->rm = operand_rm(inst); 4561 break; 4562 case rv_codec_r4_m: 4563 dec->rd = operand_rd(inst); 4564 dec->rs1 = operand_rs1(inst); 4565 dec->rs2 = operand_rs2(inst); 4566 dec->rs3 = operand_rs3(inst); 4567 dec->imm = 0; 4568 dec->rm = operand_rm(inst); 4569 break; 4570 case rv_codec_r_a: 4571 dec->rd = operand_rd(inst); 4572 dec->rs1 = operand_rs1(inst); 4573 dec->rs2 = operand_rs2(inst); 4574 dec->imm = 0; 4575 dec->aq = operand_aq(inst); 4576 dec->rl = operand_rl(inst); 4577 break; 4578 case rv_codec_r_l: 4579 dec->rd = operand_rd(inst); 4580 dec->rs1 = operand_rs1(inst); 4581 dec->rs2 = rv_ireg_zero; 4582 dec->imm = 0; 4583 dec->aq = operand_aq(inst); 4584 dec->rl = operand_rl(inst); 4585 break; 4586 case rv_codec_r_f: 4587 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4588 dec->pred = operand_pred(inst); 4589 dec->succ = operand_succ(inst); 4590 dec->imm = 0; 4591 break; 4592 case rv_codec_cb: 4593 dec->rd = rv_ireg_zero; 4594 dec->rs1 = operand_crs1q(inst) + 8; 4595 dec->rs2 = rv_ireg_zero; 4596 dec->imm = operand_cimmb(inst); 4597 break; 4598 case rv_codec_cb_imm: 4599 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4600 dec->rs2 = rv_ireg_zero; 4601 dec->imm = operand_cimmi(inst); 4602 break; 4603 case rv_codec_cb_sh5: 4604 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4605 dec->rs2 = rv_ireg_zero; 4606 dec->imm = operand_cimmsh5(inst); 4607 break; 4608 case rv_codec_cb_sh6: 4609 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4610 dec->rs2 = rv_ireg_zero; 4611 dec->imm = operand_cimmshr6(inst, isa); 4612 break; 4613 case rv_codec_ci: 4614 dec->rd = dec->rs1 = operand_crs1rd(inst); 4615 dec->rs2 = rv_ireg_zero; 4616 dec->imm = operand_cimmi(inst); 4617 break; 4618 case rv_codec_ci_sh5: 4619 dec->rd = dec->rs1 = operand_crs1rd(inst); 4620 dec->rs2 = rv_ireg_zero; 4621 dec->imm = operand_cimmsh5(inst); 4622 break; 4623 case rv_codec_ci_sh6: 4624 dec->rd = dec->rs1 = operand_crs1rd(inst); 4625 dec->rs2 = rv_ireg_zero; 4626 dec->imm = operand_cimmshl6(inst, isa); 4627 break; 4628 case rv_codec_ci_16sp: 4629 dec->rd = rv_ireg_sp; 4630 dec->rs1 = rv_ireg_sp; 4631 dec->rs2 = rv_ireg_zero; 4632 dec->imm = operand_cimm16sp(inst); 4633 break; 4634 case rv_codec_ci_lwsp: 4635 dec->rd = operand_crd(inst); 4636 dec->rs1 = rv_ireg_sp; 4637 dec->rs2 = rv_ireg_zero; 4638 dec->imm = operand_cimmlwsp(inst); 4639 break; 4640 case rv_codec_ci_ldsp: 4641 dec->rd = operand_crd(inst); 4642 dec->rs1 = rv_ireg_sp; 4643 dec->rs2 = rv_ireg_zero; 4644 dec->imm = operand_cimmldsp(inst); 4645 break; 4646 case rv_codec_ci_lqsp: 4647 dec->rd = operand_crd(inst); 4648 dec->rs1 = rv_ireg_sp; 4649 dec->rs2 = rv_ireg_zero; 4650 dec->imm = operand_cimmlqsp(inst); 4651 break; 4652 case rv_codec_ci_li: 4653 dec->rd = operand_crd(inst); 4654 dec->rs1 = rv_ireg_zero; 4655 dec->rs2 = rv_ireg_zero; 4656 dec->imm = operand_cimmi(inst); 4657 break; 4658 case rv_codec_ci_lui: 4659 dec->rd = operand_crd(inst); 4660 dec->rs1 = rv_ireg_zero; 4661 dec->rs2 = rv_ireg_zero; 4662 dec->imm = operand_cimmui(inst); 4663 break; 4664 case rv_codec_ci_none: 4665 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4666 dec->imm = 0; 4667 break; 4668 case rv_codec_ciw_4spn: 4669 dec->rd = operand_crdq(inst) + 8; 4670 dec->rs1 = rv_ireg_sp; 4671 dec->rs2 = rv_ireg_zero; 4672 dec->imm = operand_cimm4spn(inst); 4673 break; 4674 case rv_codec_cj: 4675 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4676 dec->imm = operand_cimmj(inst); 4677 break; 4678 case rv_codec_cj_jal: 4679 dec->rd = rv_ireg_ra; 4680 dec->rs1 = dec->rs2 = rv_ireg_zero; 4681 dec->imm = operand_cimmj(inst); 4682 break; 4683 case rv_codec_cl_lw: 4684 dec->rd = operand_crdq(inst) + 8; 4685 dec->rs1 = operand_crs1q(inst) + 8; 4686 dec->rs2 = rv_ireg_zero; 4687 dec->imm = operand_cimmw(inst); 4688 break; 4689 case rv_codec_cl_ld: 4690 dec->rd = operand_crdq(inst) + 8; 4691 dec->rs1 = operand_crs1q(inst) + 8; 4692 dec->rs2 = rv_ireg_zero; 4693 dec->imm = operand_cimmd(inst); 4694 break; 4695 case rv_codec_cl_lq: 4696 dec->rd = operand_crdq(inst) + 8; 4697 dec->rs1 = operand_crs1q(inst) + 8; 4698 dec->rs2 = rv_ireg_zero; 4699 dec->imm = operand_cimmq(inst); 4700 break; 4701 case rv_codec_cr: 4702 dec->rd = dec->rs1 = operand_crs1rd(inst); 4703 dec->rs2 = operand_crs2(inst); 4704 dec->imm = 0; 4705 break; 4706 case rv_codec_cr_mv: 4707 dec->rd = operand_crd(inst); 4708 dec->rs1 = operand_crs2(inst); 4709 dec->rs2 = rv_ireg_zero; 4710 dec->imm = 0; 4711 break; 4712 case rv_codec_cr_jalr: 4713 dec->rd = rv_ireg_ra; 4714 dec->rs1 = operand_crs1(inst); 4715 dec->rs2 = rv_ireg_zero; 4716 dec->imm = 0; 4717 break; 4718 case rv_codec_cr_jr: 4719 dec->rd = rv_ireg_zero; 4720 dec->rs1 = operand_crs1(inst); 4721 dec->rs2 = rv_ireg_zero; 4722 dec->imm = 0; 4723 break; 4724 case rv_codec_cs: 4725 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4726 dec->rs2 = operand_crs2q(inst) + 8; 4727 dec->imm = 0; 4728 break; 4729 case rv_codec_cs_sw: 4730 dec->rd = rv_ireg_zero; 4731 dec->rs1 = operand_crs1q(inst) + 8; 4732 dec->rs2 = operand_crs2q(inst) + 8; 4733 dec->imm = operand_cimmw(inst); 4734 break; 4735 case rv_codec_cs_sd: 4736 dec->rd = rv_ireg_zero; 4737 dec->rs1 = operand_crs1q(inst) + 8; 4738 dec->rs2 = operand_crs2q(inst) + 8; 4739 dec->imm = operand_cimmd(inst); 4740 break; 4741 case rv_codec_cs_sq: 4742 dec->rd = rv_ireg_zero; 4743 dec->rs1 = operand_crs1q(inst) + 8; 4744 dec->rs2 = operand_crs2q(inst) + 8; 4745 dec->imm = operand_cimmq(inst); 4746 break; 4747 case rv_codec_css_swsp: 4748 dec->rd = rv_ireg_zero; 4749 dec->rs1 = rv_ireg_sp; 4750 dec->rs2 = operand_crs2(inst); 4751 dec->imm = operand_cimmswsp(inst); 4752 break; 4753 case rv_codec_css_sdsp: 4754 dec->rd = rv_ireg_zero; 4755 dec->rs1 = rv_ireg_sp; 4756 dec->rs2 = operand_crs2(inst); 4757 dec->imm = operand_cimmsdsp(inst); 4758 break; 4759 case rv_codec_css_sqsp: 4760 dec->rd = rv_ireg_zero; 4761 dec->rs1 = rv_ireg_sp; 4762 dec->rs2 = operand_crs2(inst); 4763 dec->imm = operand_cimmsqsp(inst); 4764 break; 4765 case rv_codec_k_bs: 4766 dec->rs1 = operand_rs1(inst); 4767 dec->rs2 = operand_rs2(inst); 4768 dec->bs = operand_bs(inst); 4769 break; 4770 case rv_codec_k_rnum: 4771 dec->rd = operand_rd(inst); 4772 dec->rs1 = operand_rs1(inst); 4773 dec->rnum = operand_rnum(inst); 4774 break; 4775 case rv_codec_v_r: 4776 dec->rd = operand_rd(inst); 4777 dec->rs1 = operand_rs1(inst); 4778 dec->rs2 = operand_rs2(inst); 4779 dec->vm = operand_vm(inst); 4780 break; 4781 case rv_codec_v_ldst: 4782 dec->rd = operand_rd(inst); 4783 dec->rs1 = operand_rs1(inst); 4784 dec->vm = operand_vm(inst); 4785 break; 4786 case rv_codec_v_i: 4787 dec->rd = operand_rd(inst); 4788 dec->rs2 = operand_rs2(inst); 4789 dec->imm = operand_vimm(inst); 4790 dec->vm = operand_vm(inst); 4791 break; 4792 case rv_codec_vror_vi: 4793 dec->rd = operand_rd(inst); 4794 dec->rs2 = operand_rs2(inst); 4795 dec->imm = operand_vzimm6(inst); 4796 dec->vm = operand_vm(inst); 4797 break; 4798 case rv_codec_vsetvli: 4799 dec->rd = operand_rd(inst); 4800 dec->rs1 = operand_rs1(inst); 4801 dec->vzimm = operand_vzimm11(inst); 4802 break; 4803 case rv_codec_vsetivli: 4804 dec->rd = operand_rd(inst); 4805 dec->imm = operand_vimm(inst); 4806 dec->vzimm = operand_vzimm10(inst); 4807 break; 4808 case rv_codec_zcb_lb: 4809 dec->rs1 = operand_crs1q(inst) + 8; 4810 dec->rs2 = operand_crs2q(inst) + 8; 4811 dec->imm = operand_uimm_c_lb(inst); 4812 break; 4813 case rv_codec_zcb_lh: 4814 dec->rs1 = operand_crs1q(inst) + 8; 4815 dec->rs2 = operand_crs2q(inst) + 8; 4816 dec->imm = operand_uimm_c_lh(inst); 4817 break; 4818 case rv_codec_zcb_ext: 4819 dec->rd = operand_crs1q(inst) + 8; 4820 break; 4821 case rv_codec_zcb_mul: 4822 dec->rd = operand_crs1rdq(inst) + 8; 4823 dec->rs2 = operand_crs2q(inst) + 8; 4824 break; 4825 case rv_codec_zcmp_cm_pushpop: 4826 dec->imm = operand_zcmp_stack_adj(inst, isa); 4827 dec->rlist = operand_zcmp_rlist(inst); 4828 break; 4829 case rv_codec_zcmp_cm_mv: 4830 dec->rd = operand_sreg1(inst); 4831 dec->rs2 = operand_sreg2(inst); 4832 break; 4833 case rv_codec_zcmt_jt: 4834 dec->imm = operand_tbl_index(inst); 4835 break; 4836 case rv_codec_fli: 4837 dec->rd = operand_rd(inst); 4838 dec->imm = operand_rs1(inst); 4839 break; 4840 case rv_codec_r2_imm5: 4841 dec->rd = operand_rd(inst); 4842 dec->rs1 = operand_rs1(inst); 4843 dec->imm = operand_rs2(inst); 4844 break; 4845 case rv_codec_r2: 4846 dec->rd = operand_rd(inst); 4847 dec->rs1 = operand_rs1(inst); 4848 break; 4849 case rv_codec_r2_imm6: 4850 dec->rd = operand_rd(inst); 4851 dec->rs1 = operand_rs1(inst); 4852 dec->imm = operand_imm6(inst); 4853 break; 4854 case rv_codec_r_imm2: 4855 dec->rd = operand_rd(inst); 4856 dec->rs1 = operand_rs1(inst); 4857 dec->rs2 = operand_rs2(inst); 4858 dec->imm = operand_imm2(inst); 4859 break; 4860 case rv_codec_r2_immhl: 4861 dec->rd = operand_rd(inst); 4862 dec->rs1 = operand_rs1(inst); 4863 dec->imm = operand_immh(inst); 4864 dec->imm1 = operand_imml(inst); 4865 break; 4866 case rv_codec_r2_imm2_imm5: 4867 dec->rd = operand_rd(inst); 4868 dec->rs1 = operand_rs1(inst); 4869 dec->imm = sextract32(operand_rs2(inst), 0, 5); 4870 dec->imm1 = operand_imm2(inst); 4871 break; 4872 }; 4873 } 4874 4875 /* check constraint */ 4876 4877 static bool check_constraints(rv_decode *dec, const rvc_constraint *c) 4878 { 4879 int32_t imm = dec->imm; 4880 uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2; 4881 while (*c != rvc_end) { 4882 switch (*c) { 4883 case rvc_rd_eq_ra: 4884 if (!(rd == 1)) { 4885 return false; 4886 } 4887 break; 4888 case rvc_rd_eq_x0: 4889 if (!(rd == 0)) { 4890 return false; 4891 } 4892 break; 4893 case rvc_rs1_eq_x0: 4894 if (!(rs1 == 0)) { 4895 return false; 4896 } 4897 break; 4898 case rvc_rs2_eq_x0: 4899 if (!(rs2 == 0)) { 4900 return false; 4901 } 4902 break; 4903 case rvc_rs2_eq_rs1: 4904 if (!(rs2 == rs1)) { 4905 return false; 4906 } 4907 break; 4908 case rvc_rs1_eq_ra: 4909 if (!(rs1 == 1)) { 4910 return false; 4911 } 4912 break; 4913 case rvc_imm_eq_zero: 4914 if (!(imm == 0)) { 4915 return false; 4916 } 4917 break; 4918 case rvc_imm_eq_n1: 4919 if (!(imm == -1)) { 4920 return false; 4921 } 4922 break; 4923 case rvc_imm_eq_p1: 4924 if (!(imm == 1)) { 4925 return false; 4926 } 4927 break; 4928 case rvc_csr_eq_0x001: 4929 if (!(imm == 0x001)) { 4930 return false; 4931 } 4932 break; 4933 case rvc_csr_eq_0x002: 4934 if (!(imm == 0x002)) { 4935 return false; 4936 } 4937 break; 4938 case rvc_csr_eq_0x003: 4939 if (!(imm == 0x003)) { 4940 return false; 4941 } 4942 break; 4943 case rvc_csr_eq_0xc00: 4944 if (!(imm == 0xc00)) { 4945 return false; 4946 } 4947 break; 4948 case rvc_csr_eq_0xc01: 4949 if (!(imm == 0xc01)) { 4950 return false; 4951 } 4952 break; 4953 case rvc_csr_eq_0xc02: 4954 if (!(imm == 0xc02)) { 4955 return false; 4956 } 4957 break; 4958 case rvc_csr_eq_0xc80: 4959 if (!(imm == 0xc80)) { 4960 return false; 4961 } 4962 break; 4963 case rvc_csr_eq_0xc81: 4964 if (!(imm == 0xc81)) { 4965 return false; 4966 } 4967 break; 4968 case rvc_csr_eq_0xc82: 4969 if (!(imm == 0xc82)) { 4970 return false; 4971 } 4972 break; 4973 default: break; 4974 } 4975 c++; 4976 } 4977 return true; 4978 } 4979 4980 /* instruction length */ 4981 4982 static size_t inst_length(rv_inst inst) 4983 { 4984 /* NOTE: supports maximum instruction size of 64-bits */ 4985 4986 /* 4987 * instruction length coding 4988 * 4989 * aa - 16 bit aa != 11 4990 * bbb11 - 32 bit bbb != 111 4991 * 011111 - 48 bit 4992 * 0111111 - 64 bit 4993 */ 4994 4995 return (inst & 0b11) != 0b11 ? 2 4996 : (inst & 0b11100) != 0b11100 ? 4 4997 : (inst & 0b111111) == 0b011111 ? 6 4998 : (inst & 0b1111111) == 0b0111111 ? 8 4999 : 0; 5000 } 5001 5002 /* format instruction */ 5003 5004 static GString *format_inst(size_t tab, rv_decode *dec) 5005 { 5006 const rv_opcode_data *opcode_data = dec->opcode_data; 5007 GString *buf = g_string_sized_new(64); 5008 const char *fmt; 5009 5010 fmt = opcode_data[dec->op].format; 5011 while (*fmt) { 5012 switch (*fmt) { 5013 case 'O': 5014 g_string_append(buf, opcode_data[dec->op].name); 5015 break; 5016 case '(': 5017 case ',': 5018 case ')': 5019 case '-': 5020 g_string_append_c(buf, *fmt); 5021 break; 5022 case 'b': 5023 g_string_append_printf(buf, "%d", dec->bs); 5024 break; 5025 case 'n': 5026 g_string_append_printf(buf, "%d", dec->rnum); 5027 break; 5028 case '0': 5029 g_string_append(buf, rv_ireg_name_sym[dec->rd]); 5030 break; 5031 case '1': 5032 g_string_append(buf, rv_ireg_name_sym[dec->rs1]); 5033 break; 5034 case '2': 5035 g_string_append(buf, rv_ireg_name_sym[dec->rs2]); 5036 break; 5037 case '3': 5038 if (dec->cfg->ext_zfinx) { 5039 g_string_append(buf, rv_ireg_name_sym[dec->rd]); 5040 } else { 5041 g_string_append(buf, rv_freg_name_sym[dec->rd]); 5042 } 5043 break; 5044 case '4': 5045 if (dec->cfg->ext_zfinx) { 5046 g_string_append(buf, rv_ireg_name_sym[dec->rs1]); 5047 } else { 5048 g_string_append(buf, rv_freg_name_sym[dec->rs1]); 5049 } 5050 break; 5051 case '5': 5052 if (dec->cfg->ext_zfinx) { 5053 g_string_append(buf, rv_ireg_name_sym[dec->rs2]); 5054 } else { 5055 g_string_append(buf, rv_freg_name_sym[dec->rs2]); 5056 } 5057 break; 5058 case '6': 5059 if (dec->cfg->ext_zfinx) { 5060 g_string_append(buf, rv_ireg_name_sym[dec->rs3]); 5061 } else { 5062 g_string_append(buf, rv_freg_name_sym[dec->rs3]); 5063 } 5064 break; 5065 case '7': 5066 g_string_append_printf(buf, "%d", dec->rs1); 5067 break; 5068 case 'i': 5069 g_string_append_printf(buf, "%d", dec->imm); 5070 break; 5071 case 'u': 5072 g_string_append_printf(buf, "%u", ((uint32_t)dec->imm & 0b111111)); 5073 break; 5074 case 'j': 5075 g_string_append_printf(buf, "%d", dec->imm1); 5076 break; 5077 case 'o': 5078 g_string_append_printf(buf, "%d", dec->imm); 5079 while (buf->len < tab * 2) { 5080 g_string_append_c(buf, ' '); 5081 } 5082 g_string_append_printf(buf, "# 0x%" PRIx64, dec->pc + dec->imm); 5083 break; 5084 case 'U': 5085 fmt++; 5086 g_string_append_printf(buf, "%d", dec->imm >> 12); 5087 if (*fmt == 'o') { 5088 while (buf->len < tab * 2) { 5089 g_string_append_c(buf, ' '); 5090 } 5091 g_string_append_printf(buf, "# 0x%" PRIx64, dec->pc + dec->imm); 5092 } 5093 break; 5094 case 'c': { 5095 const char *name = csr_name(dec->imm & 0xfff); 5096 if (name) { 5097 g_string_append(buf, name); 5098 } else { 5099 g_string_append_printf(buf, "0x%03x", dec->imm & 0xfff); 5100 } 5101 break; 5102 } 5103 case 'r': 5104 switch (dec->rm) { 5105 case rv_rm_rne: 5106 g_string_append(buf, "rne"); 5107 break; 5108 case rv_rm_rtz: 5109 g_string_append(buf, "rtz"); 5110 break; 5111 case rv_rm_rdn: 5112 g_string_append(buf, "rdn"); 5113 break; 5114 case rv_rm_rup: 5115 g_string_append(buf, "rup"); 5116 break; 5117 case rv_rm_rmm: 5118 g_string_append(buf, "rmm"); 5119 break; 5120 case rv_rm_dyn: 5121 g_string_append(buf, "dyn"); 5122 break; 5123 default: 5124 g_string_append(buf, "inv"); 5125 break; 5126 } 5127 break; 5128 case 'p': 5129 if (dec->pred & rv_fence_i) { 5130 g_string_append_c(buf, 'i'); 5131 } 5132 if (dec->pred & rv_fence_o) { 5133 g_string_append_c(buf, 'o'); 5134 } 5135 if (dec->pred & rv_fence_r) { 5136 g_string_append_c(buf, 'r'); 5137 } 5138 if (dec->pred & rv_fence_w) { 5139 g_string_append_c(buf, 'w'); 5140 } 5141 break; 5142 case 's': 5143 if (dec->succ & rv_fence_i) { 5144 g_string_append_c(buf, 'i'); 5145 } 5146 if (dec->succ & rv_fence_o) { 5147 g_string_append_c(buf, 'o'); 5148 } 5149 if (dec->succ & rv_fence_r) { 5150 g_string_append_c(buf, 'r'); 5151 } 5152 if (dec->succ & rv_fence_w) { 5153 g_string_append_c(buf, 'w'); 5154 } 5155 break; 5156 case '\t': 5157 while (buf->len < tab) { 5158 g_string_append_c(buf, ' '); 5159 } 5160 break; 5161 case 'A': 5162 if (dec->aq) { 5163 g_string_append(buf, ".aq"); 5164 } 5165 break; 5166 case 'R': 5167 if (dec->rl) { 5168 g_string_append(buf, ".rl"); 5169 } 5170 break; 5171 case 'l': 5172 g_string_append(buf, ",v0"); 5173 break; 5174 case 'm': 5175 if (dec->vm == 0) { 5176 g_string_append(buf, ",v0.t"); 5177 } 5178 break; 5179 case 'D': 5180 g_string_append(buf, rv_vreg_name_sym[dec->rd]); 5181 break; 5182 case 'E': 5183 g_string_append(buf, rv_vreg_name_sym[dec->rs1]); 5184 break; 5185 case 'F': 5186 g_string_append(buf, rv_vreg_name_sym[dec->rs2]); 5187 break; 5188 case 'G': 5189 g_string_append(buf, rv_vreg_name_sym[dec->rs3]); 5190 break; 5191 case 'v': { 5192 const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3); 5193 const int lmul = dec->vzimm & 0b11; 5194 const int flmul = (dec->vzimm >> 2) & 1; 5195 const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu"; 5196 const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu"; 5197 5198 g_string_append_printf(buf, "e%d,m", sew); 5199 if (flmul) { 5200 switch (lmul) { 5201 case 3: 5202 g_string_append(buf, "f2"); 5203 break; 5204 case 2: 5205 g_string_append(buf, "f4"); 5206 break; 5207 case 1: 5208 g_string_append(buf, "f8"); 5209 break; 5210 } 5211 } else { 5212 g_string_append_printf(buf, "%d", 1 << lmul); 5213 } 5214 g_string_append_c(buf, ','); 5215 g_string_append(buf, vta); 5216 g_string_append_c(buf, ','); 5217 g_string_append(buf, vma); 5218 break; 5219 } 5220 case 'x': { 5221 switch (dec->rlist) { 5222 case 4: 5223 g_string_append(buf, "{ra}"); 5224 break; 5225 case 5: 5226 g_string_append(buf, "{ra, s0}"); 5227 break; 5228 case 15: 5229 g_string_append(buf, "{ra, s0-s11}"); 5230 break; 5231 default: 5232 g_string_append_printf(buf, "{ra, s0-s%d}", dec->rlist - 5); 5233 break; 5234 } 5235 break; 5236 } 5237 case 'h': 5238 g_string_append(buf, rv_fli_name_const[dec->imm]); 5239 break; 5240 default: 5241 break; 5242 } 5243 fmt++; 5244 } 5245 5246 return buf; 5247 } 5248 5249 /* lift instruction to pseudo-instruction */ 5250 5251 static void decode_inst_lift_pseudo(rv_decode *dec) 5252 { 5253 const rv_opcode_data *opcode_data = dec->opcode_data; 5254 const rv_comp_data *comp_data = opcode_data[dec->op].pseudo; 5255 if (!comp_data) { 5256 return; 5257 } 5258 while (comp_data->constraints) { 5259 if (check_constraints(dec, comp_data->constraints)) { 5260 dec->op = comp_data->op; 5261 dec->codec = opcode_data[dec->op].codec; 5262 return; 5263 } 5264 comp_data++; 5265 } 5266 } 5267 5268 /* decompress instruction */ 5269 5270 static void decode_inst_decompress_rv32(rv_decode *dec) 5271 { 5272 const rv_opcode_data *opcode_data = dec->opcode_data; 5273 int decomp_op = opcode_data[dec->op].decomp_rv32; 5274 if (decomp_op != rv_op_illegal) { 5275 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5276 && dec->imm == 0) { 5277 dec->op = rv_op_illegal; 5278 } else { 5279 dec->op = decomp_op; 5280 dec->codec = opcode_data[decomp_op].codec; 5281 } 5282 } 5283 } 5284 5285 static void decode_inst_decompress_rv64(rv_decode *dec) 5286 { 5287 const rv_opcode_data *opcode_data = dec->opcode_data; 5288 int decomp_op = opcode_data[dec->op].decomp_rv64; 5289 if (decomp_op != rv_op_illegal) { 5290 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5291 && dec->imm == 0) { 5292 dec->op = rv_op_illegal; 5293 } else { 5294 dec->op = decomp_op; 5295 dec->codec = opcode_data[decomp_op].codec; 5296 } 5297 } 5298 } 5299 5300 static void decode_inst_decompress_rv128(rv_decode *dec) 5301 { 5302 const rv_opcode_data *opcode_data = dec->opcode_data; 5303 int decomp_op = opcode_data[dec->op].decomp_rv128; 5304 if (decomp_op != rv_op_illegal) { 5305 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5306 && dec->imm == 0) { 5307 dec->op = rv_op_illegal; 5308 } else { 5309 dec->op = decomp_op; 5310 dec->codec = opcode_data[decomp_op].codec; 5311 } 5312 } 5313 } 5314 5315 static void decode_inst_decompress(rv_decode *dec, rv_isa isa) 5316 { 5317 switch (isa) { 5318 case rv32: 5319 decode_inst_decompress_rv32(dec); 5320 break; 5321 case rv64: 5322 decode_inst_decompress_rv64(dec); 5323 break; 5324 case rv128: 5325 decode_inst_decompress_rv128(dec); 5326 break; 5327 } 5328 } 5329 5330 /* disassemble instruction */ 5331 5332 static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst, 5333 RISCVCPUConfig *cfg) 5334 { 5335 rv_decode dec = { 0 }; 5336 dec.pc = pc; 5337 dec.inst = inst; 5338 dec.cfg = cfg; 5339 5340 static const struct { 5341 bool (*guard_func)(const RISCVCPUConfig *); 5342 const rv_opcode_data *opcode_data; 5343 void (*decode_func)(rv_decode *, rv_isa); 5344 } decoders[] = { 5345 { always_true_p, rvi_opcode_data, decode_inst_opcode }, 5346 { has_xtheadba_p, xthead_opcode_data, decode_xtheadba }, 5347 { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb }, 5348 { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs }, 5349 { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo }, 5350 { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov }, 5351 { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx }, 5352 { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv }, 5353 { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac }, 5354 { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx }, 5355 { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair }, 5356 { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync }, 5357 { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops }, 5358 }; 5359 5360 for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { 5361 bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func; 5362 const rv_opcode_data *opcode_data = decoders[i].opcode_data; 5363 void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func; 5364 5365 if (guard_func(cfg)) { 5366 dec.opcode_data = opcode_data; 5367 decode_func(&dec, isa); 5368 if (dec.op != rv_op_illegal) 5369 break; 5370 } 5371 } 5372 5373 if (dec.op == rv_op_illegal) { 5374 dec.opcode_data = rvi_opcode_data; 5375 } 5376 5377 decode_inst_operands(&dec, isa); 5378 decode_inst_decompress(&dec, isa); 5379 decode_inst_lift_pseudo(&dec); 5380 return format_inst(24, &dec); 5381 } 5382 5383 #define INST_FMT_2 "%04" PRIx64 " " 5384 #define INST_FMT_4 "%08" PRIx64 " " 5385 #define INST_FMT_6 "%012" PRIx64 " " 5386 #define INST_FMT_8 "%016" PRIx64 " " 5387 5388 static int 5389 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) 5390 { 5391 bfd_byte packet[2]; 5392 rv_inst inst = 0; 5393 size_t len = 2; 5394 bfd_vma n; 5395 int status; 5396 5397 /* Instructions are made of 2-byte packets in little-endian order */ 5398 for (n = 0; n < len; n += 2) { 5399 status = (*info->read_memory_func)(memaddr + n, packet, 2, info); 5400 if (status != 0) { 5401 /* Don't fail just because we fell off the end. */ 5402 if (n > 0) { 5403 break; 5404 } 5405 (*info->memory_error_func)(status, memaddr, info); 5406 return status; 5407 } 5408 inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n); 5409 if (n == 0) { 5410 len = inst_length(inst); 5411 } 5412 } 5413 5414 if (info->show_opcodes) { 5415 switch (len) { 5416 case 2: 5417 (*info->fprintf_func)(info->stream, INST_FMT_2, inst); 5418 break; 5419 case 4: 5420 (*info->fprintf_func)(info->stream, INST_FMT_4, inst); 5421 break; 5422 case 6: 5423 (*info->fprintf_func)(info->stream, INST_FMT_6, inst); 5424 break; 5425 default: 5426 (*info->fprintf_func)(info->stream, INST_FMT_8, inst); 5427 break; 5428 } 5429 } 5430 5431 g_autoptr(GString) str = 5432 disasm_inst(isa, memaddr, inst, (RISCVCPUConfig *)info->target_info); 5433 (*info->fprintf_func)(info->stream, "%s", str->str); 5434 5435 return len; 5436 } 5437 5438 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info) 5439 { 5440 return print_insn_riscv(memaddr, info, rv32); 5441 } 5442 5443 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info) 5444 { 5445 return print_insn_riscv(memaddr, info, rv64); 5446 } 5447 5448 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info) 5449 { 5450 return print_insn_riscv(memaddr, info, rv128); 5451 } 5452