1 /* 2 * QEMU RISC-V Disassembler 3 * 4 * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com> 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/bitops.h" 22 #include "disas/dis-asm.h" 23 #include "target/riscv/cpu_cfg.h" 24 #include "disas/riscv.h" 25 26 /* Vendor extensions */ 27 #include "disas/riscv-xthead.h" 28 #include "disas/riscv-xventana.h" 29 30 typedef enum { 31 /* 0 is reserved for rv_op_illegal. */ 32 rv_op_lui = 1, 33 rv_op_auipc = 2, 34 rv_op_jal = 3, 35 rv_op_jalr = 4, 36 rv_op_beq = 5, 37 rv_op_bne = 6, 38 rv_op_blt = 7, 39 rv_op_bge = 8, 40 rv_op_bltu = 9, 41 rv_op_bgeu = 10, 42 rv_op_lb = 11, 43 rv_op_lh = 12, 44 rv_op_lw = 13, 45 rv_op_lbu = 14, 46 rv_op_lhu = 15, 47 rv_op_sb = 16, 48 rv_op_sh = 17, 49 rv_op_sw = 18, 50 rv_op_addi = 19, 51 rv_op_slti = 20, 52 rv_op_sltiu = 21, 53 rv_op_xori = 22, 54 rv_op_ori = 23, 55 rv_op_andi = 24, 56 rv_op_slli = 25, 57 rv_op_srli = 26, 58 rv_op_srai = 27, 59 rv_op_add = 28, 60 rv_op_sub = 29, 61 rv_op_sll = 30, 62 rv_op_slt = 31, 63 rv_op_sltu = 32, 64 rv_op_xor = 33, 65 rv_op_srl = 34, 66 rv_op_sra = 35, 67 rv_op_or = 36, 68 rv_op_and = 37, 69 rv_op_fence = 38, 70 rv_op_fence_i = 39, 71 rv_op_lwu = 40, 72 rv_op_ld = 41, 73 rv_op_sd = 42, 74 rv_op_addiw = 43, 75 rv_op_slliw = 44, 76 rv_op_srliw = 45, 77 rv_op_sraiw = 46, 78 rv_op_addw = 47, 79 rv_op_subw = 48, 80 rv_op_sllw = 49, 81 rv_op_srlw = 50, 82 rv_op_sraw = 51, 83 rv_op_ldu = 52, 84 rv_op_lq = 53, 85 rv_op_sq = 54, 86 rv_op_addid = 55, 87 rv_op_sllid = 56, 88 rv_op_srlid = 57, 89 rv_op_sraid = 58, 90 rv_op_addd = 59, 91 rv_op_subd = 60, 92 rv_op_slld = 61, 93 rv_op_srld = 62, 94 rv_op_srad = 63, 95 rv_op_mul = 64, 96 rv_op_mulh = 65, 97 rv_op_mulhsu = 66, 98 rv_op_mulhu = 67, 99 rv_op_div = 68, 100 rv_op_divu = 69, 101 rv_op_rem = 70, 102 rv_op_remu = 71, 103 rv_op_mulw = 72, 104 rv_op_divw = 73, 105 rv_op_divuw = 74, 106 rv_op_remw = 75, 107 rv_op_remuw = 76, 108 rv_op_muld = 77, 109 rv_op_divd = 78, 110 rv_op_divud = 79, 111 rv_op_remd = 80, 112 rv_op_remud = 81, 113 rv_op_lr_w = 82, 114 rv_op_sc_w = 83, 115 rv_op_amoswap_w = 84, 116 rv_op_amoadd_w = 85, 117 rv_op_amoxor_w = 86, 118 rv_op_amoor_w = 87, 119 rv_op_amoand_w = 88, 120 rv_op_amomin_w = 89, 121 rv_op_amomax_w = 90, 122 rv_op_amominu_w = 91, 123 rv_op_amomaxu_w = 92, 124 rv_op_lr_d = 93, 125 rv_op_sc_d = 94, 126 rv_op_amoswap_d = 95, 127 rv_op_amoadd_d = 96, 128 rv_op_amoxor_d = 97, 129 rv_op_amoor_d = 98, 130 rv_op_amoand_d = 99, 131 rv_op_amomin_d = 100, 132 rv_op_amomax_d = 101, 133 rv_op_amominu_d = 102, 134 rv_op_amomaxu_d = 103, 135 rv_op_lr_q = 104, 136 rv_op_sc_q = 105, 137 rv_op_amoswap_q = 106, 138 rv_op_amoadd_q = 107, 139 rv_op_amoxor_q = 108, 140 rv_op_amoor_q = 109, 141 rv_op_amoand_q = 110, 142 rv_op_amomin_q = 111, 143 rv_op_amomax_q = 112, 144 rv_op_amominu_q = 113, 145 rv_op_amomaxu_q = 114, 146 rv_op_ecall = 115, 147 rv_op_ebreak = 116, 148 rv_op_uret = 117, 149 rv_op_sret = 118, 150 rv_op_hret = 119, 151 rv_op_mret = 120, 152 rv_op_dret = 121, 153 rv_op_sfence_vm = 122, 154 rv_op_sfence_vma = 123, 155 rv_op_wfi = 124, 156 rv_op_csrrw = 125, 157 rv_op_csrrs = 126, 158 rv_op_csrrc = 127, 159 rv_op_csrrwi = 128, 160 rv_op_csrrsi = 129, 161 rv_op_csrrci = 130, 162 rv_op_flw = 131, 163 rv_op_fsw = 132, 164 rv_op_fmadd_s = 133, 165 rv_op_fmsub_s = 134, 166 rv_op_fnmsub_s = 135, 167 rv_op_fnmadd_s = 136, 168 rv_op_fadd_s = 137, 169 rv_op_fsub_s = 138, 170 rv_op_fmul_s = 139, 171 rv_op_fdiv_s = 140, 172 rv_op_fsgnj_s = 141, 173 rv_op_fsgnjn_s = 142, 174 rv_op_fsgnjx_s = 143, 175 rv_op_fmin_s = 144, 176 rv_op_fmax_s = 145, 177 rv_op_fsqrt_s = 146, 178 rv_op_fle_s = 147, 179 rv_op_flt_s = 148, 180 rv_op_feq_s = 149, 181 rv_op_fcvt_w_s = 150, 182 rv_op_fcvt_wu_s = 151, 183 rv_op_fcvt_s_w = 152, 184 rv_op_fcvt_s_wu = 153, 185 rv_op_fmv_x_s = 154, 186 rv_op_fclass_s = 155, 187 rv_op_fmv_s_x = 156, 188 rv_op_fcvt_l_s = 157, 189 rv_op_fcvt_lu_s = 158, 190 rv_op_fcvt_s_l = 159, 191 rv_op_fcvt_s_lu = 160, 192 rv_op_fld = 161, 193 rv_op_fsd = 162, 194 rv_op_fmadd_d = 163, 195 rv_op_fmsub_d = 164, 196 rv_op_fnmsub_d = 165, 197 rv_op_fnmadd_d = 166, 198 rv_op_fadd_d = 167, 199 rv_op_fsub_d = 168, 200 rv_op_fmul_d = 169, 201 rv_op_fdiv_d = 170, 202 rv_op_fsgnj_d = 171, 203 rv_op_fsgnjn_d = 172, 204 rv_op_fsgnjx_d = 173, 205 rv_op_fmin_d = 174, 206 rv_op_fmax_d = 175, 207 rv_op_fcvt_s_d = 176, 208 rv_op_fcvt_d_s = 177, 209 rv_op_fsqrt_d = 178, 210 rv_op_fle_d = 179, 211 rv_op_flt_d = 180, 212 rv_op_feq_d = 181, 213 rv_op_fcvt_w_d = 182, 214 rv_op_fcvt_wu_d = 183, 215 rv_op_fcvt_d_w = 184, 216 rv_op_fcvt_d_wu = 185, 217 rv_op_fclass_d = 186, 218 rv_op_fcvt_l_d = 187, 219 rv_op_fcvt_lu_d = 188, 220 rv_op_fmv_x_d = 189, 221 rv_op_fcvt_d_l = 190, 222 rv_op_fcvt_d_lu = 191, 223 rv_op_fmv_d_x = 192, 224 rv_op_flq = 193, 225 rv_op_fsq = 194, 226 rv_op_fmadd_q = 195, 227 rv_op_fmsub_q = 196, 228 rv_op_fnmsub_q = 197, 229 rv_op_fnmadd_q = 198, 230 rv_op_fadd_q = 199, 231 rv_op_fsub_q = 200, 232 rv_op_fmul_q = 201, 233 rv_op_fdiv_q = 202, 234 rv_op_fsgnj_q = 203, 235 rv_op_fsgnjn_q = 204, 236 rv_op_fsgnjx_q = 205, 237 rv_op_fmin_q = 206, 238 rv_op_fmax_q = 207, 239 rv_op_fcvt_s_q = 208, 240 rv_op_fcvt_q_s = 209, 241 rv_op_fcvt_d_q = 210, 242 rv_op_fcvt_q_d = 211, 243 rv_op_fsqrt_q = 212, 244 rv_op_fle_q = 213, 245 rv_op_flt_q = 214, 246 rv_op_feq_q = 215, 247 rv_op_fcvt_w_q = 216, 248 rv_op_fcvt_wu_q = 217, 249 rv_op_fcvt_q_w = 218, 250 rv_op_fcvt_q_wu = 219, 251 rv_op_fclass_q = 220, 252 rv_op_fcvt_l_q = 221, 253 rv_op_fcvt_lu_q = 222, 254 rv_op_fcvt_q_l = 223, 255 rv_op_fcvt_q_lu = 224, 256 rv_op_fmv_x_q = 225, 257 rv_op_fmv_q_x = 226, 258 rv_op_c_addi4spn = 227, 259 rv_op_c_fld = 228, 260 rv_op_c_lw = 229, 261 rv_op_c_flw = 230, 262 rv_op_c_fsd = 231, 263 rv_op_c_sw = 232, 264 rv_op_c_fsw = 233, 265 rv_op_c_nop = 234, 266 rv_op_c_addi = 235, 267 rv_op_c_jal = 236, 268 rv_op_c_li = 237, 269 rv_op_c_addi16sp = 238, 270 rv_op_c_lui = 239, 271 rv_op_c_srli = 240, 272 rv_op_c_srai = 241, 273 rv_op_c_andi = 242, 274 rv_op_c_sub = 243, 275 rv_op_c_xor = 244, 276 rv_op_c_or = 245, 277 rv_op_c_and = 246, 278 rv_op_c_subw = 247, 279 rv_op_c_addw = 248, 280 rv_op_c_j = 249, 281 rv_op_c_beqz = 250, 282 rv_op_c_bnez = 251, 283 rv_op_c_slli = 252, 284 rv_op_c_fldsp = 253, 285 rv_op_c_lwsp = 254, 286 rv_op_c_flwsp = 255, 287 rv_op_c_jr = 256, 288 rv_op_c_mv = 257, 289 rv_op_c_ebreak = 258, 290 rv_op_c_jalr = 259, 291 rv_op_c_add = 260, 292 rv_op_c_fsdsp = 261, 293 rv_op_c_swsp = 262, 294 rv_op_c_fswsp = 263, 295 rv_op_c_ld = 264, 296 rv_op_c_sd = 265, 297 rv_op_c_addiw = 266, 298 rv_op_c_ldsp = 267, 299 rv_op_c_sdsp = 268, 300 rv_op_c_lq = 269, 301 rv_op_c_sq = 270, 302 rv_op_c_lqsp = 271, 303 rv_op_c_sqsp = 272, 304 rv_op_nop = 273, 305 rv_op_mv = 274, 306 rv_op_not = 275, 307 rv_op_neg = 276, 308 rv_op_negw = 277, 309 rv_op_sext_w = 278, 310 rv_op_seqz = 279, 311 rv_op_snez = 280, 312 rv_op_sltz = 281, 313 rv_op_sgtz = 282, 314 rv_op_fmv_s = 283, 315 rv_op_fabs_s = 284, 316 rv_op_fneg_s = 285, 317 rv_op_fmv_d = 286, 318 rv_op_fabs_d = 287, 319 rv_op_fneg_d = 288, 320 rv_op_fmv_q = 289, 321 rv_op_fabs_q = 290, 322 rv_op_fneg_q = 291, 323 rv_op_beqz = 292, 324 rv_op_bnez = 293, 325 rv_op_blez = 294, 326 rv_op_bgez = 295, 327 rv_op_bltz = 296, 328 rv_op_bgtz = 297, 329 rv_op_ble = 298, 330 rv_op_bleu = 299, 331 rv_op_bgt = 300, 332 rv_op_bgtu = 301, 333 rv_op_j = 302, 334 rv_op_ret = 303, 335 rv_op_jr = 304, 336 rv_op_rdcycle = 305, 337 rv_op_rdtime = 306, 338 rv_op_rdinstret = 307, 339 rv_op_rdcycleh = 308, 340 rv_op_rdtimeh = 309, 341 rv_op_rdinstreth = 310, 342 rv_op_frcsr = 311, 343 rv_op_frrm = 312, 344 rv_op_frflags = 313, 345 rv_op_fscsr = 314, 346 rv_op_fsrm = 315, 347 rv_op_fsflags = 316, 348 rv_op_fsrmi = 317, 349 rv_op_fsflagsi = 318, 350 rv_op_bseti = 319, 351 rv_op_bclri = 320, 352 rv_op_binvi = 321, 353 rv_op_bexti = 322, 354 rv_op_rori = 323, 355 rv_op_clz = 324, 356 rv_op_ctz = 325, 357 rv_op_cpop = 326, 358 rv_op_sext_h = 327, 359 rv_op_sext_b = 328, 360 rv_op_xnor = 329, 361 rv_op_orn = 330, 362 rv_op_andn = 331, 363 rv_op_rol = 332, 364 rv_op_ror = 333, 365 rv_op_sh1add = 334, 366 rv_op_sh2add = 335, 367 rv_op_sh3add = 336, 368 rv_op_sh1add_uw = 337, 369 rv_op_sh2add_uw = 338, 370 rv_op_sh3add_uw = 339, 371 rv_op_clmul = 340, 372 rv_op_clmulr = 341, 373 rv_op_clmulh = 342, 374 rv_op_min = 343, 375 rv_op_minu = 344, 376 rv_op_max = 345, 377 rv_op_maxu = 346, 378 rv_op_clzw = 347, 379 rv_op_ctzw = 348, 380 rv_op_cpopw = 349, 381 rv_op_slli_uw = 350, 382 rv_op_add_uw = 351, 383 rv_op_rolw = 352, 384 rv_op_rorw = 353, 385 rv_op_rev8 = 354, 386 rv_op_zext_h = 355, 387 rv_op_roriw = 356, 388 rv_op_orc_b = 357, 389 rv_op_bset = 358, 390 rv_op_bclr = 359, 391 rv_op_binv = 360, 392 rv_op_bext = 361, 393 rv_op_aes32esmi = 362, 394 rv_op_aes32esi = 363, 395 rv_op_aes32dsmi = 364, 396 rv_op_aes32dsi = 365, 397 rv_op_aes64ks1i = 366, 398 rv_op_aes64ks2 = 367, 399 rv_op_aes64im = 368, 400 rv_op_aes64esm = 369, 401 rv_op_aes64es = 370, 402 rv_op_aes64dsm = 371, 403 rv_op_aes64ds = 372, 404 rv_op_sha256sig0 = 373, 405 rv_op_sha256sig1 = 374, 406 rv_op_sha256sum0 = 375, 407 rv_op_sha256sum1 = 376, 408 rv_op_sha512sig0 = 377, 409 rv_op_sha512sig1 = 378, 410 rv_op_sha512sum0 = 379, 411 rv_op_sha512sum1 = 380, 412 rv_op_sha512sum0r = 381, 413 rv_op_sha512sum1r = 382, 414 rv_op_sha512sig0l = 383, 415 rv_op_sha512sig0h = 384, 416 rv_op_sha512sig1l = 385, 417 rv_op_sha512sig1h = 386, 418 rv_op_sm3p0 = 387, 419 rv_op_sm3p1 = 388, 420 rv_op_sm4ed = 389, 421 rv_op_sm4ks = 390, 422 rv_op_brev8 = 391, 423 rv_op_pack = 392, 424 rv_op_packh = 393, 425 rv_op_packw = 394, 426 rv_op_unzip = 395, 427 rv_op_zip = 396, 428 rv_op_xperm4 = 397, 429 rv_op_xperm8 = 398, 430 rv_op_vle8_v = 399, 431 rv_op_vle16_v = 400, 432 rv_op_vle32_v = 401, 433 rv_op_vle64_v = 402, 434 rv_op_vse8_v = 403, 435 rv_op_vse16_v = 404, 436 rv_op_vse32_v = 405, 437 rv_op_vse64_v = 406, 438 rv_op_vlm_v = 407, 439 rv_op_vsm_v = 408, 440 rv_op_vlse8_v = 409, 441 rv_op_vlse16_v = 410, 442 rv_op_vlse32_v = 411, 443 rv_op_vlse64_v = 412, 444 rv_op_vsse8_v = 413, 445 rv_op_vsse16_v = 414, 446 rv_op_vsse32_v = 415, 447 rv_op_vsse64_v = 416, 448 rv_op_vluxei8_v = 417, 449 rv_op_vluxei16_v = 418, 450 rv_op_vluxei32_v = 419, 451 rv_op_vluxei64_v = 420, 452 rv_op_vloxei8_v = 421, 453 rv_op_vloxei16_v = 422, 454 rv_op_vloxei32_v = 423, 455 rv_op_vloxei64_v = 424, 456 rv_op_vsuxei8_v = 425, 457 rv_op_vsuxei16_v = 426, 458 rv_op_vsuxei32_v = 427, 459 rv_op_vsuxei64_v = 428, 460 rv_op_vsoxei8_v = 429, 461 rv_op_vsoxei16_v = 430, 462 rv_op_vsoxei32_v = 431, 463 rv_op_vsoxei64_v = 432, 464 rv_op_vle8ff_v = 433, 465 rv_op_vle16ff_v = 434, 466 rv_op_vle32ff_v = 435, 467 rv_op_vle64ff_v = 436, 468 rv_op_vl1re8_v = 437, 469 rv_op_vl1re16_v = 438, 470 rv_op_vl1re32_v = 439, 471 rv_op_vl1re64_v = 440, 472 rv_op_vl2re8_v = 441, 473 rv_op_vl2re16_v = 442, 474 rv_op_vl2re32_v = 443, 475 rv_op_vl2re64_v = 444, 476 rv_op_vl4re8_v = 445, 477 rv_op_vl4re16_v = 446, 478 rv_op_vl4re32_v = 447, 479 rv_op_vl4re64_v = 448, 480 rv_op_vl8re8_v = 449, 481 rv_op_vl8re16_v = 450, 482 rv_op_vl8re32_v = 451, 483 rv_op_vl8re64_v = 452, 484 rv_op_vs1r_v = 453, 485 rv_op_vs2r_v = 454, 486 rv_op_vs4r_v = 455, 487 rv_op_vs8r_v = 456, 488 rv_op_vadd_vv = 457, 489 rv_op_vadd_vx = 458, 490 rv_op_vadd_vi = 459, 491 rv_op_vsub_vv = 460, 492 rv_op_vsub_vx = 461, 493 rv_op_vrsub_vx = 462, 494 rv_op_vrsub_vi = 463, 495 rv_op_vwaddu_vv = 464, 496 rv_op_vwaddu_vx = 465, 497 rv_op_vwadd_vv = 466, 498 rv_op_vwadd_vx = 467, 499 rv_op_vwsubu_vv = 468, 500 rv_op_vwsubu_vx = 469, 501 rv_op_vwsub_vv = 470, 502 rv_op_vwsub_vx = 471, 503 rv_op_vwaddu_wv = 472, 504 rv_op_vwaddu_wx = 473, 505 rv_op_vwadd_wv = 474, 506 rv_op_vwadd_wx = 475, 507 rv_op_vwsubu_wv = 476, 508 rv_op_vwsubu_wx = 477, 509 rv_op_vwsub_wv = 478, 510 rv_op_vwsub_wx = 479, 511 rv_op_vadc_vvm = 480, 512 rv_op_vadc_vxm = 481, 513 rv_op_vadc_vim = 482, 514 rv_op_vmadc_vvm = 483, 515 rv_op_vmadc_vxm = 484, 516 rv_op_vmadc_vim = 485, 517 rv_op_vsbc_vvm = 486, 518 rv_op_vsbc_vxm = 487, 519 rv_op_vmsbc_vvm = 488, 520 rv_op_vmsbc_vxm = 489, 521 rv_op_vand_vv = 490, 522 rv_op_vand_vx = 491, 523 rv_op_vand_vi = 492, 524 rv_op_vor_vv = 493, 525 rv_op_vor_vx = 494, 526 rv_op_vor_vi = 495, 527 rv_op_vxor_vv = 496, 528 rv_op_vxor_vx = 497, 529 rv_op_vxor_vi = 498, 530 rv_op_vsll_vv = 499, 531 rv_op_vsll_vx = 500, 532 rv_op_vsll_vi = 501, 533 rv_op_vsrl_vv = 502, 534 rv_op_vsrl_vx = 503, 535 rv_op_vsrl_vi = 504, 536 rv_op_vsra_vv = 505, 537 rv_op_vsra_vx = 506, 538 rv_op_vsra_vi = 507, 539 rv_op_vnsrl_wv = 508, 540 rv_op_vnsrl_wx = 509, 541 rv_op_vnsrl_wi = 510, 542 rv_op_vnsra_wv = 511, 543 rv_op_vnsra_wx = 512, 544 rv_op_vnsra_wi = 513, 545 rv_op_vmseq_vv = 514, 546 rv_op_vmseq_vx = 515, 547 rv_op_vmseq_vi = 516, 548 rv_op_vmsne_vv = 517, 549 rv_op_vmsne_vx = 518, 550 rv_op_vmsne_vi = 519, 551 rv_op_vmsltu_vv = 520, 552 rv_op_vmsltu_vx = 521, 553 rv_op_vmslt_vv = 522, 554 rv_op_vmslt_vx = 523, 555 rv_op_vmsleu_vv = 524, 556 rv_op_vmsleu_vx = 525, 557 rv_op_vmsleu_vi = 526, 558 rv_op_vmsle_vv = 527, 559 rv_op_vmsle_vx = 528, 560 rv_op_vmsle_vi = 529, 561 rv_op_vmsgtu_vx = 530, 562 rv_op_vmsgtu_vi = 531, 563 rv_op_vmsgt_vx = 532, 564 rv_op_vmsgt_vi = 533, 565 rv_op_vminu_vv = 534, 566 rv_op_vminu_vx = 535, 567 rv_op_vmin_vv = 536, 568 rv_op_vmin_vx = 537, 569 rv_op_vmaxu_vv = 538, 570 rv_op_vmaxu_vx = 539, 571 rv_op_vmax_vv = 540, 572 rv_op_vmax_vx = 541, 573 rv_op_vmul_vv = 542, 574 rv_op_vmul_vx = 543, 575 rv_op_vmulh_vv = 544, 576 rv_op_vmulh_vx = 545, 577 rv_op_vmulhu_vv = 546, 578 rv_op_vmulhu_vx = 547, 579 rv_op_vmulhsu_vv = 548, 580 rv_op_vmulhsu_vx = 549, 581 rv_op_vdivu_vv = 550, 582 rv_op_vdivu_vx = 551, 583 rv_op_vdiv_vv = 552, 584 rv_op_vdiv_vx = 553, 585 rv_op_vremu_vv = 554, 586 rv_op_vremu_vx = 555, 587 rv_op_vrem_vv = 556, 588 rv_op_vrem_vx = 557, 589 rv_op_vwmulu_vv = 558, 590 rv_op_vwmulu_vx = 559, 591 rv_op_vwmulsu_vv = 560, 592 rv_op_vwmulsu_vx = 561, 593 rv_op_vwmul_vv = 562, 594 rv_op_vwmul_vx = 563, 595 rv_op_vmacc_vv = 564, 596 rv_op_vmacc_vx = 565, 597 rv_op_vnmsac_vv = 566, 598 rv_op_vnmsac_vx = 567, 599 rv_op_vmadd_vv = 568, 600 rv_op_vmadd_vx = 569, 601 rv_op_vnmsub_vv = 570, 602 rv_op_vnmsub_vx = 571, 603 rv_op_vwmaccu_vv = 572, 604 rv_op_vwmaccu_vx = 573, 605 rv_op_vwmacc_vv = 574, 606 rv_op_vwmacc_vx = 575, 607 rv_op_vwmaccsu_vv = 576, 608 rv_op_vwmaccsu_vx = 577, 609 rv_op_vwmaccus_vx = 578, 610 rv_op_vmv_v_v = 579, 611 rv_op_vmv_v_x = 580, 612 rv_op_vmv_v_i = 581, 613 rv_op_vmerge_vvm = 582, 614 rv_op_vmerge_vxm = 583, 615 rv_op_vmerge_vim = 584, 616 rv_op_vsaddu_vv = 585, 617 rv_op_vsaddu_vx = 586, 618 rv_op_vsaddu_vi = 587, 619 rv_op_vsadd_vv = 588, 620 rv_op_vsadd_vx = 589, 621 rv_op_vsadd_vi = 590, 622 rv_op_vssubu_vv = 591, 623 rv_op_vssubu_vx = 592, 624 rv_op_vssub_vv = 593, 625 rv_op_vssub_vx = 594, 626 rv_op_vaadd_vv = 595, 627 rv_op_vaadd_vx = 596, 628 rv_op_vaaddu_vv = 597, 629 rv_op_vaaddu_vx = 598, 630 rv_op_vasub_vv = 599, 631 rv_op_vasub_vx = 600, 632 rv_op_vasubu_vv = 601, 633 rv_op_vasubu_vx = 602, 634 rv_op_vsmul_vv = 603, 635 rv_op_vsmul_vx = 604, 636 rv_op_vssrl_vv = 605, 637 rv_op_vssrl_vx = 606, 638 rv_op_vssrl_vi = 607, 639 rv_op_vssra_vv = 608, 640 rv_op_vssra_vx = 609, 641 rv_op_vssra_vi = 610, 642 rv_op_vnclipu_wv = 611, 643 rv_op_vnclipu_wx = 612, 644 rv_op_vnclipu_wi = 613, 645 rv_op_vnclip_wv = 614, 646 rv_op_vnclip_wx = 615, 647 rv_op_vnclip_wi = 616, 648 rv_op_vfadd_vv = 617, 649 rv_op_vfadd_vf = 618, 650 rv_op_vfsub_vv = 619, 651 rv_op_vfsub_vf = 620, 652 rv_op_vfrsub_vf = 621, 653 rv_op_vfwadd_vv = 622, 654 rv_op_vfwadd_vf = 623, 655 rv_op_vfwadd_wv = 624, 656 rv_op_vfwadd_wf = 625, 657 rv_op_vfwsub_vv = 626, 658 rv_op_vfwsub_vf = 627, 659 rv_op_vfwsub_wv = 628, 660 rv_op_vfwsub_wf = 629, 661 rv_op_vfmul_vv = 630, 662 rv_op_vfmul_vf = 631, 663 rv_op_vfdiv_vv = 632, 664 rv_op_vfdiv_vf = 633, 665 rv_op_vfrdiv_vf = 634, 666 rv_op_vfwmul_vv = 635, 667 rv_op_vfwmul_vf = 636, 668 rv_op_vfmacc_vv = 637, 669 rv_op_vfmacc_vf = 638, 670 rv_op_vfnmacc_vv = 639, 671 rv_op_vfnmacc_vf = 640, 672 rv_op_vfmsac_vv = 641, 673 rv_op_vfmsac_vf = 642, 674 rv_op_vfnmsac_vv = 643, 675 rv_op_vfnmsac_vf = 644, 676 rv_op_vfmadd_vv = 645, 677 rv_op_vfmadd_vf = 646, 678 rv_op_vfnmadd_vv = 647, 679 rv_op_vfnmadd_vf = 648, 680 rv_op_vfmsub_vv = 649, 681 rv_op_vfmsub_vf = 650, 682 rv_op_vfnmsub_vv = 651, 683 rv_op_vfnmsub_vf = 652, 684 rv_op_vfwmacc_vv = 653, 685 rv_op_vfwmacc_vf = 654, 686 rv_op_vfwnmacc_vv = 655, 687 rv_op_vfwnmacc_vf = 656, 688 rv_op_vfwmsac_vv = 657, 689 rv_op_vfwmsac_vf = 658, 690 rv_op_vfwnmsac_vv = 659, 691 rv_op_vfwnmsac_vf = 660, 692 rv_op_vfsqrt_v = 661, 693 rv_op_vfrsqrt7_v = 662, 694 rv_op_vfrec7_v = 663, 695 rv_op_vfmin_vv = 664, 696 rv_op_vfmin_vf = 665, 697 rv_op_vfmax_vv = 666, 698 rv_op_vfmax_vf = 667, 699 rv_op_vfsgnj_vv = 668, 700 rv_op_vfsgnj_vf = 669, 701 rv_op_vfsgnjn_vv = 670, 702 rv_op_vfsgnjn_vf = 671, 703 rv_op_vfsgnjx_vv = 672, 704 rv_op_vfsgnjx_vf = 673, 705 rv_op_vfslide1up_vf = 674, 706 rv_op_vfslide1down_vf = 675, 707 rv_op_vmfeq_vv = 676, 708 rv_op_vmfeq_vf = 677, 709 rv_op_vmfne_vv = 678, 710 rv_op_vmfne_vf = 679, 711 rv_op_vmflt_vv = 680, 712 rv_op_vmflt_vf = 681, 713 rv_op_vmfle_vv = 682, 714 rv_op_vmfle_vf = 683, 715 rv_op_vmfgt_vf = 684, 716 rv_op_vmfge_vf = 685, 717 rv_op_vfclass_v = 686, 718 rv_op_vfmerge_vfm = 687, 719 rv_op_vfmv_v_f = 688, 720 rv_op_vfcvt_xu_f_v = 689, 721 rv_op_vfcvt_x_f_v = 690, 722 rv_op_vfcvt_f_xu_v = 691, 723 rv_op_vfcvt_f_x_v = 692, 724 rv_op_vfcvt_rtz_xu_f_v = 693, 725 rv_op_vfcvt_rtz_x_f_v = 694, 726 rv_op_vfwcvt_xu_f_v = 695, 727 rv_op_vfwcvt_x_f_v = 696, 728 rv_op_vfwcvt_f_xu_v = 697, 729 rv_op_vfwcvt_f_x_v = 698, 730 rv_op_vfwcvt_f_f_v = 699, 731 rv_op_vfwcvt_rtz_xu_f_v = 700, 732 rv_op_vfwcvt_rtz_x_f_v = 701, 733 rv_op_vfncvt_xu_f_w = 702, 734 rv_op_vfncvt_x_f_w = 703, 735 rv_op_vfncvt_f_xu_w = 704, 736 rv_op_vfncvt_f_x_w = 705, 737 rv_op_vfncvt_f_f_w = 706, 738 rv_op_vfncvt_rod_f_f_w = 707, 739 rv_op_vfncvt_rtz_xu_f_w = 708, 740 rv_op_vfncvt_rtz_x_f_w = 709, 741 rv_op_vredsum_vs = 710, 742 rv_op_vredand_vs = 711, 743 rv_op_vredor_vs = 712, 744 rv_op_vredxor_vs = 713, 745 rv_op_vredminu_vs = 714, 746 rv_op_vredmin_vs = 715, 747 rv_op_vredmaxu_vs = 716, 748 rv_op_vredmax_vs = 717, 749 rv_op_vwredsumu_vs = 718, 750 rv_op_vwredsum_vs = 719, 751 rv_op_vfredusum_vs = 720, 752 rv_op_vfredosum_vs = 721, 753 rv_op_vfredmin_vs = 722, 754 rv_op_vfredmax_vs = 723, 755 rv_op_vfwredusum_vs = 724, 756 rv_op_vfwredosum_vs = 725, 757 rv_op_vmand_mm = 726, 758 rv_op_vmnand_mm = 727, 759 rv_op_vmandn_mm = 728, 760 rv_op_vmxor_mm = 729, 761 rv_op_vmor_mm = 730, 762 rv_op_vmnor_mm = 731, 763 rv_op_vmorn_mm = 732, 764 rv_op_vmxnor_mm = 733, 765 rv_op_vcpop_m = 734, 766 rv_op_vfirst_m = 735, 767 rv_op_vmsbf_m = 736, 768 rv_op_vmsif_m = 737, 769 rv_op_vmsof_m = 738, 770 rv_op_viota_m = 739, 771 rv_op_vid_v = 740, 772 rv_op_vmv_x_s = 741, 773 rv_op_vmv_s_x = 742, 774 rv_op_vfmv_f_s = 743, 775 rv_op_vfmv_s_f = 744, 776 rv_op_vslideup_vx = 745, 777 rv_op_vslideup_vi = 746, 778 rv_op_vslide1up_vx = 747, 779 rv_op_vslidedown_vx = 748, 780 rv_op_vslidedown_vi = 749, 781 rv_op_vslide1down_vx = 750, 782 rv_op_vrgather_vv = 751, 783 rv_op_vrgatherei16_vv = 752, 784 rv_op_vrgather_vx = 753, 785 rv_op_vrgather_vi = 754, 786 rv_op_vcompress_vm = 755, 787 rv_op_vmv1r_v = 756, 788 rv_op_vmv2r_v = 757, 789 rv_op_vmv4r_v = 758, 790 rv_op_vmv8r_v = 759, 791 rv_op_vzext_vf2 = 760, 792 rv_op_vzext_vf4 = 761, 793 rv_op_vzext_vf8 = 762, 794 rv_op_vsext_vf2 = 763, 795 rv_op_vsext_vf4 = 764, 796 rv_op_vsext_vf8 = 765, 797 rv_op_vsetvli = 766, 798 rv_op_vsetivli = 767, 799 rv_op_vsetvl = 768, 800 rv_op_c_zext_b = 769, 801 rv_op_c_sext_b = 770, 802 rv_op_c_zext_h = 771, 803 rv_op_c_sext_h = 772, 804 rv_op_c_zext_w = 773, 805 rv_op_c_not = 774, 806 rv_op_c_mul = 775, 807 rv_op_c_lbu = 776, 808 rv_op_c_lhu = 777, 809 rv_op_c_lh = 778, 810 rv_op_c_sb = 779, 811 rv_op_c_sh = 780, 812 rv_op_cm_push = 781, 813 rv_op_cm_pop = 782, 814 rv_op_cm_popret = 783, 815 rv_op_cm_popretz = 784, 816 rv_op_cm_mva01s = 785, 817 rv_op_cm_mvsa01 = 786, 818 rv_op_cm_jt = 787, 819 rv_op_cm_jalt = 788, 820 rv_op_czero_eqz = 789, 821 rv_op_czero_nez = 790, 822 rv_op_fcvt_bf16_s = 791, 823 rv_op_fcvt_s_bf16 = 792, 824 rv_op_vfncvtbf16_f_f_w = 793, 825 rv_op_vfwcvtbf16_f_f_v = 794, 826 rv_op_vfwmaccbf16_vv = 795, 827 rv_op_vfwmaccbf16_vf = 796, 828 rv_op_flh = 797, 829 rv_op_fsh = 798, 830 rv_op_fmv_h_x = 799, 831 rv_op_fmv_x_h = 800, 832 rv_op_fli_s = 801, 833 rv_op_fli_d = 802, 834 rv_op_fli_q = 803, 835 rv_op_fli_h = 804, 836 rv_op_fminm_s = 805, 837 rv_op_fmaxm_s = 806, 838 rv_op_fminm_d = 807, 839 rv_op_fmaxm_d = 808, 840 rv_op_fminm_q = 809, 841 rv_op_fmaxm_q = 810, 842 rv_op_fminm_h = 811, 843 rv_op_fmaxm_h = 812, 844 rv_op_fround_s = 813, 845 rv_op_froundnx_s = 814, 846 rv_op_fround_d = 815, 847 rv_op_froundnx_d = 816, 848 rv_op_fround_q = 817, 849 rv_op_froundnx_q = 818, 850 rv_op_fround_h = 819, 851 rv_op_froundnx_h = 820, 852 rv_op_fcvtmod_w_d = 821, 853 rv_op_fmvh_x_d = 822, 854 rv_op_fmvp_d_x = 823, 855 rv_op_fmvh_x_q = 824, 856 rv_op_fmvp_q_x = 825, 857 rv_op_fleq_s = 826, 858 rv_op_fltq_s = 827, 859 rv_op_fleq_d = 828, 860 rv_op_fltq_d = 829, 861 rv_op_fleq_q = 830, 862 rv_op_fltq_q = 831, 863 rv_op_fleq_h = 832, 864 rv_op_fltq_h = 833, 865 rv_op_vaesdf_vv = 834, 866 rv_op_vaesdf_vs = 835, 867 rv_op_vaesdm_vv = 836, 868 rv_op_vaesdm_vs = 837, 869 rv_op_vaesef_vv = 838, 870 rv_op_vaesef_vs = 839, 871 rv_op_vaesem_vv = 840, 872 rv_op_vaesem_vs = 841, 873 rv_op_vaeskf1_vi = 842, 874 rv_op_vaeskf2_vi = 843, 875 rv_op_vaesz_vs = 844, 876 rv_op_vandn_vv = 845, 877 rv_op_vandn_vx = 846, 878 rv_op_vbrev_v = 847, 879 rv_op_vbrev8_v = 848, 880 rv_op_vclmul_vv = 849, 881 rv_op_vclmul_vx = 850, 882 rv_op_vclmulh_vv = 851, 883 rv_op_vclmulh_vx = 852, 884 rv_op_vclz_v = 853, 885 rv_op_vcpop_v = 854, 886 rv_op_vctz_v = 855, 887 rv_op_vghsh_vv = 856, 888 rv_op_vgmul_vv = 857, 889 rv_op_vrev8_v = 858, 890 rv_op_vrol_vv = 859, 891 rv_op_vrol_vx = 860, 892 rv_op_vror_vv = 861, 893 rv_op_vror_vx = 862, 894 rv_op_vror_vi = 863, 895 rv_op_vsha2ch_vv = 864, 896 rv_op_vsha2cl_vv = 865, 897 rv_op_vsha2ms_vv = 866, 898 rv_op_vsm3c_vi = 867, 899 rv_op_vsm3me_vv = 868, 900 rv_op_vsm4k_vi = 869, 901 rv_op_vsm4r_vv = 870, 902 rv_op_vsm4r_vs = 871, 903 rv_op_vwsll_vv = 872, 904 rv_op_vwsll_vx = 873, 905 rv_op_vwsll_vi = 874, 906 rv_op_amocas_w = 875, 907 rv_op_amocas_d = 876, 908 rv_op_amocas_q = 877, 909 } rv_op; 910 911 /* register names */ 912 913 static const char rv_ireg_name_sym[32][5] = { 914 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 915 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 916 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 917 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", 918 }; 919 920 static const char rv_freg_name_sym[32][5] = { 921 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", 922 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", 923 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", 924 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11", 925 }; 926 927 static const char rv_vreg_name_sym[32][4] = { 928 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 929 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 930 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 931 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 932 }; 933 934 /* The FLI.[HSDQ] numeric constants (0.0 for symbolic constants). 935 * The constants use the hex floating-point literal representation 936 * that is printed when using the printf %a format specifier, 937 * which matches the output that is generated by the disassembler. 938 */ 939 static const char rv_fli_name_const[32][9] = 940 { 941 "0x1p+0", "min", "0x1p-16", "0x1p-15", 942 "0x1p-8", "0x1p-7", "0x1p-4", "0x1p-3", 943 "0x1p-2", "0x1.4p-2", "0x1.8p-2", "0x1.cp-2", 944 "0x1p-1", "0x1.4p-1", "0x1.8p-1", "0x1.cp-1", 945 "0x1p+0", "0x1.4p+0", "0x1.8p+0", "0x1.cp+0", 946 "0x1p+1", "0x1.4p+1", "0x1.8p+1", "0x1p+2", 947 "0x1p+3", "0x1p+4", "0x1p+7", "0x1p+8", 948 "0x1p+15", "0x1p+16", "inf", "nan" 949 }; 950 951 /* pseudo-instruction constraints */ 952 953 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end }; 954 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, 955 rvc_end }; 956 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, 957 rvc_imm_eq_zero, rvc_end }; 958 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; 959 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end }; 960 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end }; 961 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end }; 962 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end }; 963 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end }; 964 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end }; 965 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end }; 966 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end }; 967 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end }; 968 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end }; 969 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end }; 970 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end }; 971 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end }; 972 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end }; 973 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end }; 974 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end }; 975 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end }; 976 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end }; 977 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end }; 978 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end }; 979 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end }; 980 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end }; 981 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end }; 982 static const rvc_constraint rvcc_ble[] = { rvc_end }; 983 static const rvc_constraint rvcc_bleu[] = { rvc_end }; 984 static const rvc_constraint rvcc_bgt[] = { rvc_end }; 985 static const rvc_constraint rvcc_bgtu[] = { rvc_end }; 986 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end }; 987 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, 988 rvc_end }; 989 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, 990 rvc_end }; 991 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, 992 rvc_end }; 993 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, 994 rvc_end }; 995 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, 996 rvc_csr_eq_0xc02, rvc_end }; 997 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, 998 rvc_csr_eq_0xc80, rvc_end }; 999 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, 1000 rvc_end }; 1001 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, 1002 rvc_csr_eq_0xc82, rvc_end }; 1003 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, 1004 rvc_end }; 1005 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, 1006 rvc_end }; 1007 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, 1008 rvc_end }; 1009 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end }; 1010 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end }; 1011 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end }; 1012 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end }; 1013 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end }; 1014 1015 /* pseudo-instruction metadata */ 1016 1017 static const rv_comp_data rvcp_jal[] = { 1018 { rv_op_j, rvcc_j }, 1019 { rv_op_jal, rvcc_jal }, 1020 { rv_op_illegal, NULL } 1021 }; 1022 1023 static const rv_comp_data rvcp_jalr[] = { 1024 { rv_op_ret, rvcc_ret }, 1025 { rv_op_jr, rvcc_jr }, 1026 { rv_op_jalr, rvcc_jalr }, 1027 { rv_op_illegal, NULL } 1028 }; 1029 1030 static const rv_comp_data rvcp_beq[] = { 1031 { rv_op_beqz, rvcc_beqz }, 1032 { rv_op_illegal, NULL } 1033 }; 1034 1035 static const rv_comp_data rvcp_bne[] = { 1036 { rv_op_bnez, rvcc_bnez }, 1037 { rv_op_illegal, NULL } 1038 }; 1039 1040 static const rv_comp_data rvcp_blt[] = { 1041 { rv_op_bltz, rvcc_bltz }, 1042 { rv_op_bgtz, rvcc_bgtz }, 1043 { rv_op_bgt, rvcc_bgt }, 1044 { rv_op_illegal, NULL } 1045 }; 1046 1047 static const rv_comp_data rvcp_bge[] = { 1048 { rv_op_blez, rvcc_blez }, 1049 { rv_op_bgez, rvcc_bgez }, 1050 { rv_op_ble, rvcc_ble }, 1051 { rv_op_illegal, NULL } 1052 }; 1053 1054 static const rv_comp_data rvcp_bltu[] = { 1055 { rv_op_bgtu, rvcc_bgtu }, 1056 { rv_op_illegal, NULL } 1057 }; 1058 1059 static const rv_comp_data rvcp_bgeu[] = { 1060 { rv_op_bleu, rvcc_bleu }, 1061 { rv_op_illegal, NULL } 1062 }; 1063 1064 static const rv_comp_data rvcp_addi[] = { 1065 { rv_op_nop, rvcc_nop }, 1066 { rv_op_mv, rvcc_mv }, 1067 { rv_op_illegal, NULL } 1068 }; 1069 1070 static const rv_comp_data rvcp_sltiu[] = { 1071 { rv_op_seqz, rvcc_seqz }, 1072 { rv_op_illegal, NULL } 1073 }; 1074 1075 static const rv_comp_data rvcp_xori[] = { 1076 { rv_op_not, rvcc_not }, 1077 { rv_op_illegal, NULL } 1078 }; 1079 1080 static const rv_comp_data rvcp_sub[] = { 1081 { rv_op_neg, rvcc_neg }, 1082 { rv_op_illegal, NULL } 1083 }; 1084 1085 static const rv_comp_data rvcp_slt[] = { 1086 { rv_op_sltz, rvcc_sltz }, 1087 { rv_op_sgtz, rvcc_sgtz }, 1088 { rv_op_illegal, NULL } 1089 }; 1090 1091 static const rv_comp_data rvcp_sltu[] = { 1092 { rv_op_snez, rvcc_snez }, 1093 { rv_op_illegal, NULL } 1094 }; 1095 1096 static const rv_comp_data rvcp_addiw[] = { 1097 { rv_op_sext_w, rvcc_sext_w }, 1098 { rv_op_illegal, NULL } 1099 }; 1100 1101 static const rv_comp_data rvcp_subw[] = { 1102 { rv_op_negw, rvcc_negw }, 1103 { rv_op_illegal, NULL } 1104 }; 1105 1106 static const rv_comp_data rvcp_csrrw[] = { 1107 { rv_op_fscsr, rvcc_fscsr }, 1108 { rv_op_fsrm, rvcc_fsrm }, 1109 { rv_op_fsflags, rvcc_fsflags }, 1110 { rv_op_illegal, NULL } 1111 }; 1112 1113 1114 static const rv_comp_data rvcp_csrrs[] = { 1115 { rv_op_rdcycle, rvcc_rdcycle }, 1116 { rv_op_rdtime, rvcc_rdtime }, 1117 { rv_op_rdinstret, rvcc_rdinstret }, 1118 { rv_op_rdcycleh, rvcc_rdcycleh }, 1119 { rv_op_rdtimeh, rvcc_rdtimeh }, 1120 { rv_op_rdinstreth, rvcc_rdinstreth }, 1121 { rv_op_frcsr, rvcc_frcsr }, 1122 { rv_op_frrm, rvcc_frrm }, 1123 { rv_op_frflags, rvcc_frflags }, 1124 { rv_op_illegal, NULL } 1125 }; 1126 1127 static const rv_comp_data rvcp_csrrwi[] = { 1128 { rv_op_fsrmi, rvcc_fsrmi }, 1129 { rv_op_fsflagsi, rvcc_fsflagsi }, 1130 { rv_op_illegal, NULL } 1131 }; 1132 1133 static const rv_comp_data rvcp_fsgnj_s[] = { 1134 { rv_op_fmv_s, rvcc_fmv_s }, 1135 { rv_op_illegal, NULL } 1136 }; 1137 1138 static const rv_comp_data rvcp_fsgnjn_s[] = { 1139 { rv_op_fneg_s, rvcc_fneg_s }, 1140 { rv_op_illegal, NULL } 1141 }; 1142 1143 static const rv_comp_data rvcp_fsgnjx_s[] = { 1144 { rv_op_fabs_s, rvcc_fabs_s }, 1145 { rv_op_illegal, NULL } 1146 }; 1147 1148 static const rv_comp_data rvcp_fsgnj_d[] = { 1149 { rv_op_fmv_d, rvcc_fmv_d }, 1150 { rv_op_illegal, NULL } 1151 }; 1152 1153 static const rv_comp_data rvcp_fsgnjn_d[] = { 1154 { rv_op_fneg_d, rvcc_fneg_d }, 1155 { rv_op_illegal, NULL } 1156 }; 1157 1158 static const rv_comp_data rvcp_fsgnjx_d[] = { 1159 { rv_op_fabs_d, rvcc_fabs_d }, 1160 { rv_op_illegal, NULL } 1161 }; 1162 1163 static const rv_comp_data rvcp_fsgnj_q[] = { 1164 { rv_op_fmv_q, rvcc_fmv_q }, 1165 { rv_op_illegal, NULL } 1166 }; 1167 1168 static const rv_comp_data rvcp_fsgnjn_q[] = { 1169 { rv_op_fneg_q, rvcc_fneg_q }, 1170 { rv_op_illegal, NULL } 1171 }; 1172 1173 static const rv_comp_data rvcp_fsgnjx_q[] = { 1174 { rv_op_fabs_q, rvcc_fabs_q }, 1175 { rv_op_illegal, NULL } 1176 }; 1177 1178 /* instruction metadata */ 1179 1180 const rv_opcode_data rvi_opcode_data[] = { 1181 { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, 1182 { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 }, 1183 { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 }, 1184 { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 }, 1185 { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 }, 1186 { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 }, 1187 { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 }, 1188 { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 }, 1189 { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 }, 1190 { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 }, 1191 { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 }, 1192 { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1193 { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1194 { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1195 { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1196 { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1197 { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1198 { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1199 { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1200 { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 }, 1201 { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1202 { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 }, 1203 { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 }, 1204 { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1205 { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1206 { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1207 { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1208 { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1209 { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1210 { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 }, 1211 { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1212 { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 }, 1213 { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 }, 1214 { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1215 { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1216 { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1217 { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1218 { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1219 { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 }, 1220 { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1221 { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1222 { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1223 { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1224 { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 }, 1225 { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1226 { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1227 { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1228 { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1229 { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 }, 1230 { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1231 { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1232 { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1233 { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1234 { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1235 { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1236 { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1237 { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1238 { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1239 { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1240 { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1241 { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1242 { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1243 { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1244 { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1245 { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1246 { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1247 { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1248 { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1249 { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1250 { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1251 { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1252 { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1253 { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1254 { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1255 { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1256 { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1257 { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1258 { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1259 { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1260 { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1261 { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1262 { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1263 { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1264 { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1265 { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1266 { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1267 { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1268 { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1269 { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1270 { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1271 { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1272 { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1273 { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1274 { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1275 { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1276 { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1277 { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1278 { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1279 { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1280 { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1281 { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1282 { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1283 { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1284 { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1285 { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1286 { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1287 { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1288 { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1289 { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1290 { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1291 { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1292 { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1293 { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1294 { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1295 { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1296 { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1297 { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1298 { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1299 { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1300 { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1301 { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1302 { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1303 { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, 1304 { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 }, 1305 { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1306 { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 }, 1307 { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 }, 1308 { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 }, 1309 { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 }, 1310 { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1311 { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1312 { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1313 { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1314 { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1315 { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1316 { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1317 { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1318 { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1319 { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1320 { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1321 { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1322 { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 }, 1323 { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 }, 1324 { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 }, 1325 { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1326 { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1327 { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1328 { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1329 { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1330 { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1331 { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1332 { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1333 { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1334 { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1335 { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1336 { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1337 { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1338 { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1339 { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1340 { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1341 { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1342 { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1343 { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1344 { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1345 { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1346 { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1347 { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1348 { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1349 { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1350 { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1351 { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1352 { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 }, 1353 { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 }, 1354 { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 }, 1355 { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1356 { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1357 { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1358 { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1359 { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1360 { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1361 { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1362 { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1363 { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1364 { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1365 { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1366 { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1367 { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1368 { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1369 { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1370 { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1371 { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1372 { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1373 { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1374 { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1375 { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1376 { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1377 { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1378 { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1379 { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1380 { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1381 { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1382 { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1383 { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1384 { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 }, 1385 { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 }, 1386 { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 }, 1387 { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1388 { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1389 { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1390 { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1391 { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1392 { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1393 { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1394 { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1395 { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1396 { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1397 { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1398 { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1399 { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1400 { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1401 { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1402 { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1403 { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1404 { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1405 { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1406 { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1407 { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1408 { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1409 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1410 { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1411 rv_op_fld, 0 }, 1412 { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, 1413 rv_op_lw }, 1414 { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, 1415 { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1416 rv_op_fsd, 0 }, 1417 { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, 1418 rv_op_sw }, 1419 { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, 1420 { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, 1421 rv_op_addi }, 1422 { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1423 rv_op_addi, rvcd_imm_nz }, 1424 { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 }, 1425 { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1426 rv_op_addi }, 1427 { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1428 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1429 { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui, 1430 rv_op_lui, rvcd_imm_nz }, 1431 { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, 1432 rv_op_srli, rv_op_srli, rvcd_imm_nz }, 1433 { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, 1434 rv_op_srai, rv_op_srai, rvcd_imm_nz }, 1435 { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, 1436 rv_op_andi, rv_op_andi }, 1437 { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, 1438 rv_op_sub }, 1439 { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, 1440 rv_op_xor }, 1441 { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, 1442 rv_op_or }, 1443 { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, 1444 rv_op_and }, 1445 { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, 1446 rv_op_subw }, 1447 { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, 1448 rv_op_addw }, 1449 { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, 1450 rv_op_jal }, 1451 { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, 1452 rv_op_beq }, 1453 { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, 1454 rv_op_bne }, 1455 { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, 1456 rv_op_slli, rv_op_slli, rvcd_imm_nz }, 1457 { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1458 rv_op_fld, rv_op_fld }, 1459 { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, 1460 rv_op_lw, rv_op_lw }, 1461 { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 1462 0 }, 1463 { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1464 rv_op_jalr, rv_op_jalr }, 1465 { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, 1466 rv_op_addi }, 1467 { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, 1468 rv_op_ebreak, rv_op_ebreak }, 1469 { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1470 rv_op_jalr, rv_op_jalr }, 1471 { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, 1472 rv_op_add }, 1473 { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1474 rv_op_fsd, rv_op_fsd }, 1475 { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, 1476 rv_op_sw, rv_op_sw }, 1477 { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 1478 0 }, 1479 { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1480 rv_op_ld }, 1481 { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1482 rv_op_sd }, 1483 { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, 1484 rv_op_addiw }, 1485 { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1486 rv_op_ld }, 1487 { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1488 rv_op_sd }, 1489 { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1490 { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, 1491 { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1492 { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 1493 rv_op_sq }, 1494 { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1495 { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1496 { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1497 { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1498 { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1499 { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1500 { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1501 { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1502 { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1503 { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1504 { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1505 { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1506 { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1507 { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1508 { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1509 { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1510 { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1511 { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1512 { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1513 { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1514 { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1515 { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1516 { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1517 { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1518 { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1519 { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1520 { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1521 { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1522 { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1523 { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 }, 1524 { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1525 { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 }, 1526 { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1527 { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1528 { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1529 { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1530 { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1531 { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1532 { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1533 { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1534 { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1535 { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1536 { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1537 { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1538 { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1539 { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1540 { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1541 { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1542 { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1543 { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1544 { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1545 { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1546 { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1547 { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1548 { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1549 { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1550 { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1551 { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1552 { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1553 { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1554 { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1555 { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1556 { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1557 { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1558 { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1559 { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1560 { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1561 { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1562 { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1563 { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1564 { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1565 { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1566 { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1567 { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1568 { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1569 { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1570 { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1571 { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1572 { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1573 { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1574 { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1575 { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1576 { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1577 { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1578 { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1579 { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1580 { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1581 { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1582 { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1583 { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1584 { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1585 { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1586 { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1587 { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 }, 1588 { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1589 { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1590 { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1591 { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1592 { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1593 { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1594 { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1595 { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1596 { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1597 { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1598 { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1599 { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1600 { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1601 { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1602 { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1603 { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1604 { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1605 { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1606 { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1607 { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1608 { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1609 { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1610 { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1611 { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1612 { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1613 { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1614 { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1615 { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1616 { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1617 { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1618 { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1619 { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1620 { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1621 { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1622 { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1623 { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1624 { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1625 { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1626 { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1627 { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1628 { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1629 { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1630 { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1631 { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1632 { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1633 { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1634 { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1635 { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1636 { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1637 { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1638 { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1639 { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1640 { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1641 { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1642 { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1643 { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1644 { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1645 { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1646 { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1647 { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1648 { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1649 { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1650 { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1651 { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1652 { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1653 { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1654 { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1655 { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1656 { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1657 { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1658 { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1659 { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1660 { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1661 { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1662 { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1663 { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1664 { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1665 { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1666 { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1667 { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1668 { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1669 { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1670 { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1671 { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1672 { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1673 { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1674 { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1675 { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1676 { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1677 { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1678 { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1679 { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1680 { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1681 { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1682 { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1683 { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1684 { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1685 { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1686 { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1687 { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1688 { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1689 { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1690 { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1691 { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1692 { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1693 { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1694 { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1695 { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1696 { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1697 { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1698 { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1699 { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1700 { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1701 { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1702 { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1703 { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1704 { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1705 { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1706 { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1707 { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1708 { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1709 { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1710 { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1711 { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1712 { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1713 { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1714 { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1715 { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1716 { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1717 { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1718 { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1719 { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1720 { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1721 { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1722 { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1723 { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1724 { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1725 { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1726 { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1727 { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1728 { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1729 { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1730 { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1731 { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1732 { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1733 { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1734 { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1735 { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1736 { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1737 { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1738 { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1739 { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1740 { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1741 { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1742 { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1743 { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1744 { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1745 { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1746 { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1747 { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1748 { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1749 { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1750 { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1751 { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1752 { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1753 { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1754 { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1755 { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1756 { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1757 { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1758 { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1759 { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1760 { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1761 { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1762 { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1763 { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1764 { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1765 { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1766 { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1767 { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1768 { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1769 { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1770 { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1771 { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1772 { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1773 { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1774 { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1775 { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1776 { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1777 { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1778 { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1779 { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1780 { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1781 { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1782 { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1783 { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1784 { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1785 { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1786 { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1787 { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1788 { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1789 { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1790 { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1791 { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1792 { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1793 { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1794 { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1795 { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1796 { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1797 { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1798 { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1799 { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1800 { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 }, 1801 { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 1802 { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 }, 1803 { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1804 { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1805 { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1806 { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1807 { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1808 { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1809 { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1810 { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1811 { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1812 { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1813 { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1814 { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1815 { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1816 { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1817 { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1818 { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1819 { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1820 { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1821 { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1822 { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1823 { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1824 { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1825 { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1826 { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1827 { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1828 { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1829 { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1830 { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1831 { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1832 { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1833 { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1834 { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1835 { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1836 { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1837 { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1838 { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1839 { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1840 { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1841 { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1842 { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1843 { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1844 { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1845 { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1846 { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1847 { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1848 { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1849 { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1850 { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1851 { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1852 { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1853 { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1854 { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1855 { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1856 { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1857 { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1858 { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1859 { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1860 { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1861 { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1862 { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1863 { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1864 { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1865 { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1866 { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1867 { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1868 { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1869 { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1870 { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1871 { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1872 { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1873 { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1874 { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1875 { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1876 { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1877 { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1878 { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1879 { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1880 { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1881 { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1882 { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1883 { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1884 { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1885 { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1886 { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1887 { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1888 { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1889 { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1890 { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1891 { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1892 { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1893 { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1894 { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1895 { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1896 { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1897 { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1898 { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1899 { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1900 { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1901 { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1902 { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1903 { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1904 { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1905 { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1906 { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1907 { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1908 { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 }, 1909 { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 1910 { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1911 { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1912 { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1913 { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1914 { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1915 { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1916 { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1917 { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1918 { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1919 { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1920 { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1921 { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1922 { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1923 { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1924 { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1925 { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1926 { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1927 { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1928 { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1929 { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1930 { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1931 { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1932 { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1933 { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1934 { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1935 { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1936 { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1937 { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1938 { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1939 { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1940 { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1941 { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1942 { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1943 { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1944 { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1945 { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1946 { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1947 { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1948 { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1949 { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1950 { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1951 { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1952 { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1953 { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1954 { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1955 { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 1956 { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 1957 { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1958 { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1959 { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1960 { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1961 { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 }, 1962 { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 }, 1963 { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 1964 { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 }, 1965 { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 1966 { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1967 { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1968 { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1969 { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1970 { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1971 { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1972 { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1973 { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1974 { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1975 { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1976 { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 1977 { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1978 { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1979 { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1980 { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1981 { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1982 { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1983 { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1984 { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1985 { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1986 { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1987 { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 }, 1988 { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 }, 1989 { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1990 { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1991 { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1992 { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1993 { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1994 { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1995 { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1996 { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 }, 1997 { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1998 { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1999 { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2000 { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2001 { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2002 { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 }, 2003 { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2004 { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 }, 2005 { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2006 { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2007 { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2008 { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2009 { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2010 { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2011 { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2012 { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2013 { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2014 { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2015 { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2016 { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 2017 { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 2018 { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 2019 { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 2020 { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 2021 { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2022 { "fli.s", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2023 { "fli.d", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2024 { "fli.q", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2025 { "fli.h", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2026 { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2027 { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2028 { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2029 { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2030 { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2031 { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2032 { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2033 { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2034 { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2035 { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2036 { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2037 { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2038 { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2039 { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2040 { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2041 { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2042 { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 2043 { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2044 { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2045 { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2046 { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2047 { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2048 { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2049 { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2050 { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2051 { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2052 { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2053 { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2054 { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2055 { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2056 { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2057 { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2058 { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2059 { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2060 { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2061 { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2062 { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2063 { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2064 { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2065 { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2066 { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2067 { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2068 { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2069 { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2070 { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2071 { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2072 { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2073 { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2074 { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2075 { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2076 { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2077 { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2078 { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2079 { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2080 { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2081 { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2082 { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2083 { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2084 { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2085 { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2086 { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2087 { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2088 { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2089 { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2090 { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2091 { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2092 { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2093 { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2094 { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2095 { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2096 { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2097 { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2098 { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2099 }; 2100 2101 /* CSR names */ 2102 2103 static const char *csr_name(int csrno) 2104 { 2105 switch (csrno) { 2106 case 0x0000: return "ustatus"; 2107 case 0x0001: return "fflags"; 2108 case 0x0002: return "frm"; 2109 case 0x0003: return "fcsr"; 2110 case 0x0004: return "uie"; 2111 case 0x0005: return "utvec"; 2112 case 0x0008: return "vstart"; 2113 case 0x0009: return "vxsat"; 2114 case 0x000a: return "vxrm"; 2115 case 0x000f: return "vcsr"; 2116 case 0x0015: return "seed"; 2117 case 0x0017: return "jvt"; 2118 case 0x0040: return "uscratch"; 2119 case 0x0041: return "uepc"; 2120 case 0x0042: return "ucause"; 2121 case 0x0043: return "utval"; 2122 case 0x0044: return "uip"; 2123 case 0x0100: return "sstatus"; 2124 case 0x0104: return "sie"; 2125 case 0x0105: return "stvec"; 2126 case 0x0106: return "scounteren"; 2127 case 0x0140: return "sscratch"; 2128 case 0x0141: return "sepc"; 2129 case 0x0142: return "scause"; 2130 case 0x0143: return "stval"; 2131 case 0x0144: return "sip"; 2132 case 0x0180: return "satp"; 2133 case 0x0200: return "hstatus"; 2134 case 0x0202: return "hedeleg"; 2135 case 0x0203: return "hideleg"; 2136 case 0x0204: return "hie"; 2137 case 0x0205: return "htvec"; 2138 case 0x0240: return "hscratch"; 2139 case 0x0241: return "hepc"; 2140 case 0x0242: return "hcause"; 2141 case 0x0243: return "hbadaddr"; 2142 case 0x0244: return "hip"; 2143 case 0x0300: return "mstatus"; 2144 case 0x0301: return "misa"; 2145 case 0x0302: return "medeleg"; 2146 case 0x0303: return "mideleg"; 2147 case 0x0304: return "mie"; 2148 case 0x0305: return "mtvec"; 2149 case 0x0306: return "mcounteren"; 2150 case 0x0320: return "mucounteren"; 2151 case 0x0321: return "mscounteren"; 2152 case 0x0322: return "mhcounteren"; 2153 case 0x0323: return "mhpmevent3"; 2154 case 0x0324: return "mhpmevent4"; 2155 case 0x0325: return "mhpmevent5"; 2156 case 0x0326: return "mhpmevent6"; 2157 case 0x0327: return "mhpmevent7"; 2158 case 0x0328: return "mhpmevent8"; 2159 case 0x0329: return "mhpmevent9"; 2160 case 0x032a: return "mhpmevent10"; 2161 case 0x032b: return "mhpmevent11"; 2162 case 0x032c: return "mhpmevent12"; 2163 case 0x032d: return "mhpmevent13"; 2164 case 0x032e: return "mhpmevent14"; 2165 case 0x032f: return "mhpmevent15"; 2166 case 0x0330: return "mhpmevent16"; 2167 case 0x0331: return "mhpmevent17"; 2168 case 0x0332: return "mhpmevent18"; 2169 case 0x0333: return "mhpmevent19"; 2170 case 0x0334: return "mhpmevent20"; 2171 case 0x0335: return "mhpmevent21"; 2172 case 0x0336: return "mhpmevent22"; 2173 case 0x0337: return "mhpmevent23"; 2174 case 0x0338: return "mhpmevent24"; 2175 case 0x0339: return "mhpmevent25"; 2176 case 0x033a: return "mhpmevent26"; 2177 case 0x033b: return "mhpmevent27"; 2178 case 0x033c: return "mhpmevent28"; 2179 case 0x033d: return "mhpmevent29"; 2180 case 0x033e: return "mhpmevent30"; 2181 case 0x033f: return "mhpmevent31"; 2182 case 0x0340: return "mscratch"; 2183 case 0x0341: return "mepc"; 2184 case 0x0342: return "mcause"; 2185 case 0x0343: return "mtval"; 2186 case 0x0344: return "mip"; 2187 case 0x0380: return "mbase"; 2188 case 0x0381: return "mbound"; 2189 case 0x0382: return "mibase"; 2190 case 0x0383: return "mibound"; 2191 case 0x0384: return "mdbase"; 2192 case 0x0385: return "mdbound"; 2193 case 0x03a0: return "pmpcfg0"; 2194 case 0x03a1: return "pmpcfg1"; 2195 case 0x03a2: return "pmpcfg2"; 2196 case 0x03a3: return "pmpcfg3"; 2197 case 0x03a4: return "pmpcfg4"; 2198 case 0x03a5: return "pmpcfg5"; 2199 case 0x03a6: return "pmpcfg6"; 2200 case 0x03a7: return "pmpcfg7"; 2201 case 0x03a8: return "pmpcfg8"; 2202 case 0x03a9: return "pmpcfg9"; 2203 case 0x03aa: return "pmpcfg10"; 2204 case 0x03ab: return "pmpcfg11"; 2205 case 0x03ac: return "pmpcfg12"; 2206 case 0x03ad: return "pmpcfg13"; 2207 case 0x03ae: return "pmpcfg14"; 2208 case 0x03af: return "pmpcfg15"; 2209 case 0x03b0: return "pmpaddr0"; 2210 case 0x03b1: return "pmpaddr1"; 2211 case 0x03b2: return "pmpaddr2"; 2212 case 0x03b3: return "pmpaddr3"; 2213 case 0x03b4: return "pmpaddr4"; 2214 case 0x03b5: return "pmpaddr5"; 2215 case 0x03b6: return "pmpaddr6"; 2216 case 0x03b7: return "pmpaddr7"; 2217 case 0x03b8: return "pmpaddr8"; 2218 case 0x03b9: return "pmpaddr9"; 2219 case 0x03ba: return "pmpaddr10"; 2220 case 0x03bb: return "pmpaddr11"; 2221 case 0x03bc: return "pmpaddr12"; 2222 case 0x03bd: return "pmpaddr13"; 2223 case 0x03be: return "pmpaddr14"; 2224 case 0x03bf: return "pmpaddr15"; 2225 case 0x03c0: return "pmpaddr16"; 2226 case 0x03c1: return "pmpaddr17"; 2227 case 0x03c2: return "pmpaddr18"; 2228 case 0x03c3: return "pmpaddr19"; 2229 case 0x03c4: return "pmpaddr20"; 2230 case 0x03c5: return "pmpaddr21"; 2231 case 0x03c6: return "pmpaddr22"; 2232 case 0x03c7: return "pmpaddr23"; 2233 case 0x03c8: return "pmpaddr24"; 2234 case 0x03c9: return "pmpaddr25"; 2235 case 0x03ca: return "pmpaddr26"; 2236 case 0x03cb: return "pmpaddr27"; 2237 case 0x03cc: return "pmpaddr28"; 2238 case 0x03cd: return "pmpaddr29"; 2239 case 0x03ce: return "pmpaddr30"; 2240 case 0x03cf: return "pmpaddr31"; 2241 case 0x03d0: return "pmpaddr32"; 2242 case 0x03d1: return "pmpaddr33"; 2243 case 0x03d2: return "pmpaddr34"; 2244 case 0x03d3: return "pmpaddr35"; 2245 case 0x03d4: return "pmpaddr36"; 2246 case 0x03d5: return "pmpaddr37"; 2247 case 0x03d6: return "pmpaddr38"; 2248 case 0x03d7: return "pmpaddr39"; 2249 case 0x03d8: return "pmpaddr40"; 2250 case 0x03d9: return "pmpaddr41"; 2251 case 0x03da: return "pmpaddr42"; 2252 case 0x03db: return "pmpaddr43"; 2253 case 0x03dc: return "pmpaddr44"; 2254 case 0x03dd: return "pmpaddr45"; 2255 case 0x03de: return "pmpaddr46"; 2256 case 0x03df: return "pmpaddr47"; 2257 case 0x03e0: return "pmpaddr48"; 2258 case 0x03e1: return "pmpaddr49"; 2259 case 0x03e2: return "pmpaddr50"; 2260 case 0x03e3: return "pmpaddr51"; 2261 case 0x03e4: return "pmpaddr52"; 2262 case 0x03e5: return "pmpaddr53"; 2263 case 0x03e6: return "pmpaddr54"; 2264 case 0x03e7: return "pmpaddr55"; 2265 case 0x03e8: return "pmpaddr56"; 2266 case 0x03e9: return "pmpaddr57"; 2267 case 0x03ea: return "pmpaddr58"; 2268 case 0x03eb: return "pmpaddr59"; 2269 case 0x03ec: return "pmpaddr60"; 2270 case 0x03ed: return "pmpaddr61"; 2271 case 0x03ee: return "pmpaddr62"; 2272 case 0x03ef: return "pmpaddr63"; 2273 case 0x0780: return "mtohost"; 2274 case 0x0781: return "mfromhost"; 2275 case 0x0782: return "mreset"; 2276 case 0x0783: return "mipi"; 2277 case 0x0784: return "miobase"; 2278 case 0x07a0: return "tselect"; 2279 case 0x07a1: return "tdata1"; 2280 case 0x07a2: return "tdata2"; 2281 case 0x07a3: return "tdata3"; 2282 case 0x07b0: return "dcsr"; 2283 case 0x07b1: return "dpc"; 2284 case 0x07b2: return "dscratch"; 2285 case 0x0b00: return "mcycle"; 2286 case 0x0b01: return "mtime"; 2287 case 0x0b02: return "minstret"; 2288 case 0x0b03: return "mhpmcounter3"; 2289 case 0x0b04: return "mhpmcounter4"; 2290 case 0x0b05: return "mhpmcounter5"; 2291 case 0x0b06: return "mhpmcounter6"; 2292 case 0x0b07: return "mhpmcounter7"; 2293 case 0x0b08: return "mhpmcounter8"; 2294 case 0x0b09: return "mhpmcounter9"; 2295 case 0x0b0a: return "mhpmcounter10"; 2296 case 0x0b0b: return "mhpmcounter11"; 2297 case 0x0b0c: return "mhpmcounter12"; 2298 case 0x0b0d: return "mhpmcounter13"; 2299 case 0x0b0e: return "mhpmcounter14"; 2300 case 0x0b0f: return "mhpmcounter15"; 2301 case 0x0b10: return "mhpmcounter16"; 2302 case 0x0b11: return "mhpmcounter17"; 2303 case 0x0b12: return "mhpmcounter18"; 2304 case 0x0b13: return "mhpmcounter19"; 2305 case 0x0b14: return "mhpmcounter20"; 2306 case 0x0b15: return "mhpmcounter21"; 2307 case 0x0b16: return "mhpmcounter22"; 2308 case 0x0b17: return "mhpmcounter23"; 2309 case 0x0b18: return "mhpmcounter24"; 2310 case 0x0b19: return "mhpmcounter25"; 2311 case 0x0b1a: return "mhpmcounter26"; 2312 case 0x0b1b: return "mhpmcounter27"; 2313 case 0x0b1c: return "mhpmcounter28"; 2314 case 0x0b1d: return "mhpmcounter29"; 2315 case 0x0b1e: return "mhpmcounter30"; 2316 case 0x0b1f: return "mhpmcounter31"; 2317 case 0x0b80: return "mcycleh"; 2318 case 0x0b81: return "mtimeh"; 2319 case 0x0b82: return "minstreth"; 2320 case 0x0b83: return "mhpmcounter3h"; 2321 case 0x0b84: return "mhpmcounter4h"; 2322 case 0x0b85: return "mhpmcounter5h"; 2323 case 0x0b86: return "mhpmcounter6h"; 2324 case 0x0b87: return "mhpmcounter7h"; 2325 case 0x0b88: return "mhpmcounter8h"; 2326 case 0x0b89: return "mhpmcounter9h"; 2327 case 0x0b8a: return "mhpmcounter10h"; 2328 case 0x0b8b: return "mhpmcounter11h"; 2329 case 0x0b8c: return "mhpmcounter12h"; 2330 case 0x0b8d: return "mhpmcounter13h"; 2331 case 0x0b8e: return "mhpmcounter14h"; 2332 case 0x0b8f: return "mhpmcounter15h"; 2333 case 0x0b90: return "mhpmcounter16h"; 2334 case 0x0b91: return "mhpmcounter17h"; 2335 case 0x0b92: return "mhpmcounter18h"; 2336 case 0x0b93: return "mhpmcounter19h"; 2337 case 0x0b94: return "mhpmcounter20h"; 2338 case 0x0b95: return "mhpmcounter21h"; 2339 case 0x0b96: return "mhpmcounter22h"; 2340 case 0x0b97: return "mhpmcounter23h"; 2341 case 0x0b98: return "mhpmcounter24h"; 2342 case 0x0b99: return "mhpmcounter25h"; 2343 case 0x0b9a: return "mhpmcounter26h"; 2344 case 0x0b9b: return "mhpmcounter27h"; 2345 case 0x0b9c: return "mhpmcounter28h"; 2346 case 0x0b9d: return "mhpmcounter29h"; 2347 case 0x0b9e: return "mhpmcounter30h"; 2348 case 0x0b9f: return "mhpmcounter31h"; 2349 case 0x0c00: return "cycle"; 2350 case 0x0c01: return "time"; 2351 case 0x0c02: return "instret"; 2352 case 0x0c20: return "vl"; 2353 case 0x0c21: return "vtype"; 2354 case 0x0c22: return "vlenb"; 2355 case 0x0c80: return "cycleh"; 2356 case 0x0c81: return "timeh"; 2357 case 0x0c82: return "instreth"; 2358 case 0x0d00: return "scycle"; 2359 case 0x0d01: return "stime"; 2360 case 0x0d02: return "sinstret"; 2361 case 0x0d80: return "scycleh"; 2362 case 0x0d81: return "stimeh"; 2363 case 0x0d82: return "sinstreth"; 2364 case 0x0e00: return "hcycle"; 2365 case 0x0e01: return "htime"; 2366 case 0x0e02: return "hinstret"; 2367 case 0x0e80: return "hcycleh"; 2368 case 0x0e81: return "htimeh"; 2369 case 0x0e82: return "hinstreth"; 2370 case 0x0f11: return "mvendorid"; 2371 case 0x0f12: return "marchid"; 2372 case 0x0f13: return "mimpid"; 2373 case 0x0f14: return "mhartid"; 2374 default: return NULL; 2375 } 2376 } 2377 2378 /* decode opcode */ 2379 2380 static void decode_inst_opcode(rv_decode *dec, rv_isa isa) 2381 { 2382 rv_inst inst = dec->inst; 2383 rv_opcode op = rv_op_illegal; 2384 switch ((inst >> 0) & 0b11) { 2385 case 0: 2386 switch ((inst >> 13) & 0b111) { 2387 case 0: op = rv_op_c_addi4spn; break; 2388 case 1: 2389 if (isa == rv128) { 2390 op = rv_op_c_lq; 2391 } else { 2392 op = rv_op_c_fld; 2393 } 2394 break; 2395 case 2: op = rv_op_c_lw; break; 2396 case 3: 2397 if (isa == rv32) { 2398 op = rv_op_c_flw; 2399 } else { 2400 op = rv_op_c_ld; 2401 } 2402 break; 2403 case 4: 2404 switch ((inst >> 10) & 0b111) { 2405 case 0: op = rv_op_c_lbu; break; 2406 case 1: 2407 if (((inst >> 6) & 1) == 0) { 2408 op = rv_op_c_lhu; 2409 } else { 2410 op = rv_op_c_lh; 2411 } 2412 break; 2413 case 2: op = rv_op_c_sb; break; 2414 case 3: 2415 if (((inst >> 6) & 1) == 0) { 2416 op = rv_op_c_sh; 2417 } 2418 break; 2419 } 2420 break; 2421 case 5: 2422 if (isa == rv128) { 2423 op = rv_op_c_sq; 2424 } else { 2425 op = rv_op_c_fsd; 2426 } 2427 break; 2428 case 6: op = rv_op_c_sw; break; 2429 case 7: 2430 if (isa == rv32) { 2431 op = rv_op_c_fsw; 2432 } else { 2433 op = rv_op_c_sd; 2434 } 2435 break; 2436 } 2437 break; 2438 case 1: 2439 switch ((inst >> 13) & 0b111) { 2440 case 0: 2441 switch ((inst >> 2) & 0b11111111111) { 2442 case 0: op = rv_op_c_nop; break; 2443 default: op = rv_op_c_addi; break; 2444 } 2445 break; 2446 case 1: 2447 if (isa == rv32) { 2448 op = rv_op_c_jal; 2449 } else { 2450 op = rv_op_c_addiw; 2451 } 2452 break; 2453 case 2: op = rv_op_c_li; break; 2454 case 3: 2455 switch ((inst >> 7) & 0b11111) { 2456 case 2: op = rv_op_c_addi16sp; break; 2457 default: op = rv_op_c_lui; break; 2458 } 2459 break; 2460 case 4: 2461 switch ((inst >> 10) & 0b11) { 2462 case 0: 2463 op = rv_op_c_srli; 2464 break; 2465 case 1: 2466 op = rv_op_c_srai; 2467 break; 2468 case 2: op = rv_op_c_andi; break; 2469 case 3: 2470 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) { 2471 case 0: op = rv_op_c_sub; break; 2472 case 1: op = rv_op_c_xor; break; 2473 case 2: op = rv_op_c_or; break; 2474 case 3: op = rv_op_c_and; break; 2475 case 4: op = rv_op_c_subw; break; 2476 case 5: op = rv_op_c_addw; break; 2477 case 6: op = rv_op_c_mul; break; 2478 case 7: 2479 switch ((inst >> 2) & 0b111) { 2480 case 0: op = rv_op_c_zext_b; break; 2481 case 1: op = rv_op_c_sext_b; break; 2482 case 2: op = rv_op_c_zext_h; break; 2483 case 3: op = rv_op_c_sext_h; break; 2484 case 4: op = rv_op_c_zext_w; break; 2485 case 5: op = rv_op_c_not; break; 2486 } 2487 break; 2488 } 2489 break; 2490 } 2491 break; 2492 case 5: op = rv_op_c_j; break; 2493 case 6: op = rv_op_c_beqz; break; 2494 case 7: op = rv_op_c_bnez; break; 2495 } 2496 break; 2497 case 2: 2498 switch ((inst >> 13) & 0b111) { 2499 case 0: 2500 op = rv_op_c_slli; 2501 break; 2502 case 1: 2503 if (isa == rv128) { 2504 op = rv_op_c_lqsp; 2505 } else { 2506 op = rv_op_c_fldsp; 2507 } 2508 break; 2509 case 2: op = rv_op_c_lwsp; break; 2510 case 3: 2511 if (isa == rv32) { 2512 op = rv_op_c_flwsp; 2513 } else { 2514 op = rv_op_c_ldsp; 2515 } 2516 break; 2517 case 4: 2518 switch ((inst >> 12) & 0b1) { 2519 case 0: 2520 switch ((inst >> 2) & 0b11111) { 2521 case 0: op = rv_op_c_jr; break; 2522 default: op = rv_op_c_mv; break; 2523 } 2524 break; 2525 case 1: 2526 switch ((inst >> 2) & 0b11111) { 2527 case 0: 2528 switch ((inst >> 7) & 0b11111) { 2529 case 0: op = rv_op_c_ebreak; break; 2530 default: op = rv_op_c_jalr; break; 2531 } 2532 break; 2533 default: op = rv_op_c_add; break; 2534 } 2535 break; 2536 } 2537 break; 2538 case 5: 2539 if (isa == rv128) { 2540 op = rv_op_c_sqsp; 2541 } else { 2542 op = rv_op_c_fsdsp; 2543 if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { 2544 switch ((inst >> 8) & 0b01111) { 2545 case 8: 2546 if (((inst >> 4) & 0b01111) >= 4) { 2547 op = rv_op_cm_push; 2548 } 2549 break; 2550 case 10: 2551 if (((inst >> 4) & 0b01111) >= 4) { 2552 op = rv_op_cm_pop; 2553 } 2554 break; 2555 case 12: 2556 if (((inst >> 4) & 0b01111) >= 4) { 2557 op = rv_op_cm_popretz; 2558 } 2559 break; 2560 case 14: 2561 if (((inst >> 4) & 0b01111) >= 4) { 2562 op = rv_op_cm_popret; 2563 } 2564 break; 2565 } 2566 } else { 2567 switch ((inst >> 10) & 0b011) { 2568 case 0: 2569 if (!dec->cfg->ext_zcmt) { 2570 break; 2571 } 2572 if (((inst >> 2) & 0xFF) >= 32) { 2573 op = rv_op_cm_jalt; 2574 } else { 2575 op = rv_op_cm_jt; 2576 } 2577 break; 2578 case 3: 2579 if (!dec->cfg->ext_zcmp) { 2580 break; 2581 } 2582 switch ((inst >> 5) & 0b011) { 2583 case 1: op = rv_op_cm_mvsa01; break; 2584 case 3: op = rv_op_cm_mva01s; break; 2585 } 2586 break; 2587 } 2588 } 2589 } 2590 break; 2591 case 6: op = rv_op_c_swsp; break; 2592 case 7: 2593 if (isa == rv32) { 2594 op = rv_op_c_fswsp; 2595 } else { 2596 op = rv_op_c_sdsp; 2597 } 2598 break; 2599 } 2600 break; 2601 case 3: 2602 switch ((inst >> 2) & 0b11111) { 2603 case 0: 2604 switch ((inst >> 12) & 0b111) { 2605 case 0: op = rv_op_lb; break; 2606 case 1: op = rv_op_lh; break; 2607 case 2: op = rv_op_lw; break; 2608 case 3: op = rv_op_ld; break; 2609 case 4: op = rv_op_lbu; break; 2610 case 5: op = rv_op_lhu; break; 2611 case 6: op = rv_op_lwu; break; 2612 case 7: op = rv_op_ldu; break; 2613 } 2614 break; 2615 case 1: 2616 switch ((inst >> 12) & 0b111) { 2617 case 0: 2618 switch ((inst >> 20) & 0b111111111111) { 2619 case 40: op = rv_op_vl1re8_v; break; 2620 case 552: op = rv_op_vl2re8_v; break; 2621 case 1576: op = rv_op_vl4re8_v; break; 2622 case 3624: op = rv_op_vl8re8_v; break; 2623 } 2624 switch ((inst >> 26) & 0b111) { 2625 case 0: 2626 switch ((inst >> 20) & 0b11111) { 2627 case 0: op = rv_op_vle8_v; break; 2628 case 11: op = rv_op_vlm_v; break; 2629 case 16: op = rv_op_vle8ff_v; break; 2630 } 2631 break; 2632 case 1: op = rv_op_vluxei8_v; break; 2633 case 2: op = rv_op_vlse8_v; break; 2634 case 3: op = rv_op_vloxei8_v; break; 2635 } 2636 break; 2637 case 1: op = rv_op_flh; break; 2638 case 2: op = rv_op_flw; break; 2639 case 3: op = rv_op_fld; break; 2640 case 4: op = rv_op_flq; break; 2641 case 5: 2642 switch ((inst >> 20) & 0b111111111111) { 2643 case 40: op = rv_op_vl1re16_v; break; 2644 case 552: op = rv_op_vl2re16_v; break; 2645 case 1576: op = rv_op_vl4re16_v; break; 2646 case 3624: op = rv_op_vl8re16_v; break; 2647 } 2648 switch ((inst >> 26) & 0b111) { 2649 case 0: 2650 switch ((inst >> 20) & 0b11111) { 2651 case 0: op = rv_op_vle16_v; break; 2652 case 16: op = rv_op_vle16ff_v; break; 2653 } 2654 break; 2655 case 1: op = rv_op_vluxei16_v; break; 2656 case 2: op = rv_op_vlse16_v; break; 2657 case 3: op = rv_op_vloxei16_v; break; 2658 } 2659 break; 2660 case 6: 2661 switch ((inst >> 20) & 0b111111111111) { 2662 case 40: op = rv_op_vl1re32_v; break; 2663 case 552: op = rv_op_vl2re32_v; break; 2664 case 1576: op = rv_op_vl4re32_v; break; 2665 case 3624: op = rv_op_vl8re32_v; break; 2666 } 2667 switch ((inst >> 26) & 0b111) { 2668 case 0: 2669 switch ((inst >> 20) & 0b11111) { 2670 case 0: op = rv_op_vle32_v; break; 2671 case 16: op = rv_op_vle32ff_v; break; 2672 } 2673 break; 2674 case 1: op = rv_op_vluxei32_v; break; 2675 case 2: op = rv_op_vlse32_v; break; 2676 case 3: op = rv_op_vloxei32_v; break; 2677 } 2678 break; 2679 case 7: 2680 switch ((inst >> 20) & 0b111111111111) { 2681 case 40: op = rv_op_vl1re64_v; break; 2682 case 552: op = rv_op_vl2re64_v; break; 2683 case 1576: op = rv_op_vl4re64_v; break; 2684 case 3624: op = rv_op_vl8re64_v; break; 2685 } 2686 switch ((inst >> 26) & 0b111) { 2687 case 0: 2688 switch ((inst >> 20) & 0b11111) { 2689 case 0: op = rv_op_vle64_v; break; 2690 case 16: op = rv_op_vle64ff_v; break; 2691 } 2692 break; 2693 case 1: op = rv_op_vluxei64_v; break; 2694 case 2: op = rv_op_vlse64_v; break; 2695 case 3: op = rv_op_vloxei64_v; break; 2696 } 2697 break; 2698 } 2699 break; 2700 case 3: 2701 switch ((inst >> 12) & 0b111) { 2702 case 0: op = rv_op_fence; break; 2703 case 1: op = rv_op_fence_i; break; 2704 case 2: op = rv_op_lq; break; 2705 } 2706 break; 2707 case 4: 2708 switch ((inst >> 12) & 0b111) { 2709 case 0: op = rv_op_addi; break; 2710 case 1: 2711 switch ((inst >> 27) & 0b11111) { 2712 case 0b00000: op = rv_op_slli; break; 2713 case 0b00001: 2714 switch ((inst >> 20) & 0b1111111) { 2715 case 0b0001111: op = rv_op_zip; break; 2716 } 2717 break; 2718 case 0b00010: 2719 switch ((inst >> 20) & 0b1111111) { 2720 case 0b0000000: op = rv_op_sha256sum0; break; 2721 case 0b0000001: op = rv_op_sha256sum1; break; 2722 case 0b0000010: op = rv_op_sha256sig0; break; 2723 case 0b0000011: op = rv_op_sha256sig1; break; 2724 case 0b0000100: op = rv_op_sha512sum0; break; 2725 case 0b0000101: op = rv_op_sha512sum1; break; 2726 case 0b0000110: op = rv_op_sha512sig0; break; 2727 case 0b0000111: op = rv_op_sha512sig1; break; 2728 case 0b0001000: op = rv_op_sm3p0; break; 2729 case 0b0001001: op = rv_op_sm3p1; break; 2730 } 2731 break; 2732 case 0b00101: op = rv_op_bseti; break; 2733 case 0b00110: 2734 switch ((inst >> 20) & 0b1111111) { 2735 case 0b0000000: op = rv_op_aes64im; break; 2736 default: 2737 if (((inst >> 24) & 0b0111) == 0b001) { 2738 op = rv_op_aes64ks1i; 2739 } 2740 break; 2741 } 2742 break; 2743 case 0b01001: op = rv_op_bclri; break; 2744 case 0b01101: op = rv_op_binvi; break; 2745 case 0b01100: 2746 switch ((inst >> 20) & 0b1111111) { 2747 case 0b0000000: op = rv_op_clz; break; 2748 case 0b0000001: op = rv_op_ctz; break; 2749 case 0b0000010: op = rv_op_cpop; break; 2750 /* 0b0000011 */ 2751 case 0b0000100: op = rv_op_sext_b; break; 2752 case 0b0000101: op = rv_op_sext_h; break; 2753 } 2754 break; 2755 } 2756 break; 2757 case 2: op = rv_op_slti; break; 2758 case 3: op = rv_op_sltiu; break; 2759 case 4: op = rv_op_xori; break; 2760 case 5: 2761 switch ((inst >> 27) & 0b11111) { 2762 case 0b00000: op = rv_op_srli; break; 2763 case 0b00001: 2764 switch ((inst >> 20) & 0b1111111) { 2765 case 0b0001111: op = rv_op_unzip; break; 2766 } 2767 break; 2768 case 0b00101: op = rv_op_orc_b; break; 2769 case 0b01000: op = rv_op_srai; break; 2770 case 0b01001: op = rv_op_bexti; break; 2771 case 0b01100: op = rv_op_rori; break; 2772 case 0b01101: 2773 switch ((inst >> 20) & 0b1111111) { 2774 case 0b0011000: op = rv_op_rev8; break; 2775 case 0b0111000: op = rv_op_rev8; break; 2776 case 0b0000111: op = rv_op_brev8; break; 2777 } 2778 break; 2779 } 2780 break; 2781 case 6: op = rv_op_ori; break; 2782 case 7: op = rv_op_andi; break; 2783 } 2784 break; 2785 case 5: op = rv_op_auipc; break; 2786 case 6: 2787 switch ((inst >> 12) & 0b111) { 2788 case 0: op = rv_op_addiw; break; 2789 case 1: 2790 switch ((inst >> 26) & 0b111111) { 2791 case 0: op = rv_op_slliw; break; 2792 case 2: op = rv_op_slli_uw; break; 2793 case 24: 2794 switch ((inst >> 20) & 0b11111) { 2795 case 0b00000: op = rv_op_clzw; break; 2796 case 0b00001: op = rv_op_ctzw; break; 2797 case 0b00010: op = rv_op_cpopw; break; 2798 } 2799 break; 2800 } 2801 break; 2802 case 5: 2803 switch ((inst >> 25) & 0b1111111) { 2804 case 0: op = rv_op_srliw; break; 2805 case 32: op = rv_op_sraiw; break; 2806 case 48: op = rv_op_roriw; break; 2807 } 2808 break; 2809 } 2810 break; 2811 case 8: 2812 switch ((inst >> 12) & 0b111) { 2813 case 0: op = rv_op_sb; break; 2814 case 1: op = rv_op_sh; break; 2815 case 2: op = rv_op_sw; break; 2816 case 3: op = rv_op_sd; break; 2817 case 4: op = rv_op_sq; break; 2818 } 2819 break; 2820 case 9: 2821 switch ((inst >> 12) & 0b111) { 2822 case 0: 2823 switch ((inst >> 20) & 0b111111111111) { 2824 case 40: op = rv_op_vs1r_v; break; 2825 case 552: op = rv_op_vs2r_v; break; 2826 case 1576: op = rv_op_vs4r_v; break; 2827 case 3624: op = rv_op_vs8r_v; break; 2828 } 2829 switch ((inst >> 26) & 0b111) { 2830 case 0: 2831 switch ((inst >> 20) & 0b11111) { 2832 case 0: op = rv_op_vse8_v; break; 2833 case 11: op = rv_op_vsm_v; break; 2834 } 2835 break; 2836 case 1: op = rv_op_vsuxei8_v; break; 2837 case 2: op = rv_op_vsse8_v; break; 2838 case 3: op = rv_op_vsoxei8_v; break; 2839 } 2840 break; 2841 case 1: op = rv_op_fsh; break; 2842 case 2: op = rv_op_fsw; break; 2843 case 3: op = rv_op_fsd; break; 2844 case 4: op = rv_op_fsq; break; 2845 case 5: 2846 switch ((inst >> 26) & 0b111) { 2847 case 0: 2848 switch ((inst >> 20) & 0b11111) { 2849 case 0: op = rv_op_vse16_v; break; 2850 } 2851 break; 2852 case 1: op = rv_op_vsuxei16_v; break; 2853 case 2: op = rv_op_vsse16_v; break; 2854 case 3: op = rv_op_vsoxei16_v; break; 2855 } 2856 break; 2857 case 6: 2858 switch ((inst >> 26) & 0b111) { 2859 case 0: 2860 switch ((inst >> 20) & 0b11111) { 2861 case 0: op = rv_op_vse32_v; break; 2862 } 2863 break; 2864 case 1: op = rv_op_vsuxei32_v; break; 2865 case 2: op = rv_op_vsse32_v; break; 2866 case 3: op = rv_op_vsoxei32_v; break; 2867 } 2868 break; 2869 case 7: 2870 switch ((inst >> 26) & 0b111) { 2871 case 0: 2872 switch ((inst >> 20) & 0b11111) { 2873 case 0: op = rv_op_vse64_v; break; 2874 } 2875 break; 2876 case 1: op = rv_op_vsuxei64_v; break; 2877 case 2: op = rv_op_vsse64_v; break; 2878 case 3: op = rv_op_vsoxei64_v; break; 2879 } 2880 break; 2881 } 2882 break; 2883 case 11: 2884 switch (((inst >> 24) & 0b11111000) | 2885 ((inst >> 12) & 0b00000111)) { 2886 case 2: op = rv_op_amoadd_w; break; 2887 case 3: op = rv_op_amoadd_d; break; 2888 case 4: op = rv_op_amoadd_q; break; 2889 case 10: op = rv_op_amoswap_w; break; 2890 case 11: op = rv_op_amoswap_d; break; 2891 case 12: op = rv_op_amoswap_q; break; 2892 case 18: 2893 switch ((inst >> 20) & 0b11111) { 2894 case 0: op = rv_op_lr_w; break; 2895 } 2896 break; 2897 case 19: 2898 switch ((inst >> 20) & 0b11111) { 2899 case 0: op = rv_op_lr_d; break; 2900 } 2901 break; 2902 case 20: 2903 switch ((inst >> 20) & 0b11111) { 2904 case 0: op = rv_op_lr_q; break; 2905 } 2906 break; 2907 case 26: op = rv_op_sc_w; break; 2908 case 27: op = rv_op_sc_d; break; 2909 case 28: op = rv_op_sc_q; break; 2910 case 34: op = rv_op_amoxor_w; break; 2911 case 35: op = rv_op_amoxor_d; break; 2912 case 36: op = rv_op_amoxor_q; break; 2913 case 42: op = rv_op_amocas_w; break; 2914 case 43: op = rv_op_amocas_d; break; 2915 case 44: op = rv_op_amocas_q; break; 2916 case 66: op = rv_op_amoor_w; break; 2917 case 67: op = rv_op_amoor_d; break; 2918 case 68: op = rv_op_amoor_q; break; 2919 case 98: op = rv_op_amoand_w; break; 2920 case 99: op = rv_op_amoand_d; break; 2921 case 100: op = rv_op_amoand_q; break; 2922 case 130: op = rv_op_amomin_w; break; 2923 case 131: op = rv_op_amomin_d; break; 2924 case 132: op = rv_op_amomin_q; break; 2925 case 162: op = rv_op_amomax_w; break; 2926 case 163: op = rv_op_amomax_d; break; 2927 case 164: op = rv_op_amomax_q; break; 2928 case 194: op = rv_op_amominu_w; break; 2929 case 195: op = rv_op_amominu_d; break; 2930 case 196: op = rv_op_amominu_q; break; 2931 case 226: op = rv_op_amomaxu_w; break; 2932 case 227: op = rv_op_amomaxu_d; break; 2933 case 228: op = rv_op_amomaxu_q; break; 2934 } 2935 break; 2936 case 12: 2937 switch (((inst >> 22) & 0b1111111000) | 2938 ((inst >> 12) & 0b0000000111)) { 2939 case 0: op = rv_op_add; break; 2940 case 1: op = rv_op_sll; break; 2941 case 2: op = rv_op_slt; break; 2942 case 3: op = rv_op_sltu; break; 2943 case 4: op = rv_op_xor; break; 2944 case 5: op = rv_op_srl; break; 2945 case 6: op = rv_op_or; break; 2946 case 7: op = rv_op_and; break; 2947 case 8: op = rv_op_mul; break; 2948 case 9: op = rv_op_mulh; break; 2949 case 10: op = rv_op_mulhsu; break; 2950 case 11: op = rv_op_mulhu; break; 2951 case 12: op = rv_op_div; break; 2952 case 13: op = rv_op_divu; break; 2953 case 14: op = rv_op_rem; break; 2954 case 15: op = rv_op_remu; break; 2955 case 36: 2956 switch ((inst >> 20) & 0b11111) { 2957 case 0: op = rv_op_zext_h; break; 2958 default: op = rv_op_pack; break; 2959 } 2960 break; 2961 case 39: op = rv_op_packh; break; 2962 2963 case 41: op = rv_op_clmul; break; 2964 case 42: op = rv_op_clmulr; break; 2965 case 43: op = rv_op_clmulh; break; 2966 case 44: op = rv_op_min; break; 2967 case 45: op = rv_op_minu; break; 2968 case 46: op = rv_op_max; break; 2969 case 47: op = rv_op_maxu; break; 2970 case 075: op = rv_op_czero_eqz; break; 2971 case 077: op = rv_op_czero_nez; break; 2972 case 130: op = rv_op_sh1add; break; 2973 case 132: op = rv_op_sh2add; break; 2974 case 134: op = rv_op_sh3add; break; 2975 case 161: op = rv_op_bset; break; 2976 case 162: op = rv_op_xperm4; break; 2977 case 164: op = rv_op_xperm8; break; 2978 case 200: op = rv_op_aes64es; break; 2979 case 216: op = rv_op_aes64esm; break; 2980 case 232: op = rv_op_aes64ds; break; 2981 case 248: op = rv_op_aes64dsm; break; 2982 case 256: op = rv_op_sub; break; 2983 case 260: op = rv_op_xnor; break; 2984 case 261: op = rv_op_sra; break; 2985 case 262: op = rv_op_orn; break; 2986 case 263: op = rv_op_andn; break; 2987 case 289: op = rv_op_bclr; break; 2988 case 293: op = rv_op_bext; break; 2989 case 320: op = rv_op_sha512sum0r; break; 2990 case 328: op = rv_op_sha512sum1r; break; 2991 case 336: op = rv_op_sha512sig0l; break; 2992 case 344: op = rv_op_sha512sig1l; break; 2993 case 368: op = rv_op_sha512sig0h; break; 2994 case 376: op = rv_op_sha512sig1h; break; 2995 case 385: op = rv_op_rol; break; 2996 case 389: op = rv_op_ror; break; 2997 case 417: op = rv_op_binv; break; 2998 case 504: op = rv_op_aes64ks2; break; 2999 } 3000 switch ((inst >> 25) & 0b0011111) { 3001 case 17: op = rv_op_aes32esi; break; 3002 case 19: op = rv_op_aes32esmi; break; 3003 case 21: op = rv_op_aes32dsi; break; 3004 case 23: op = rv_op_aes32dsmi; break; 3005 case 24: op = rv_op_sm4ed; break; 3006 case 26: op = rv_op_sm4ks; break; 3007 } 3008 break; 3009 case 13: op = rv_op_lui; break; 3010 case 14: 3011 switch (((inst >> 22) & 0b1111111000) | 3012 ((inst >> 12) & 0b0000000111)) { 3013 case 0: op = rv_op_addw; break; 3014 case 1: op = rv_op_sllw; break; 3015 case 5: op = rv_op_srlw; break; 3016 case 8: op = rv_op_mulw; break; 3017 case 12: op = rv_op_divw; break; 3018 case 13: op = rv_op_divuw; break; 3019 case 14: op = rv_op_remw; break; 3020 case 15: op = rv_op_remuw; break; 3021 case 32: op = rv_op_add_uw; break; 3022 case 36: 3023 switch ((inst >> 20) & 0b11111) { 3024 case 0: op = rv_op_zext_h; break; 3025 default: op = rv_op_packw; break; 3026 } 3027 break; 3028 case 130: op = rv_op_sh1add_uw; break; 3029 case 132: op = rv_op_sh2add_uw; break; 3030 case 134: op = rv_op_sh3add_uw; break; 3031 case 256: op = rv_op_subw; break; 3032 case 261: op = rv_op_sraw; break; 3033 case 385: op = rv_op_rolw; break; 3034 case 389: op = rv_op_rorw; break; 3035 } 3036 break; 3037 case 16: 3038 switch ((inst >> 25) & 0b11) { 3039 case 0: op = rv_op_fmadd_s; break; 3040 case 1: op = rv_op_fmadd_d; break; 3041 case 3: op = rv_op_fmadd_q; break; 3042 } 3043 break; 3044 case 17: 3045 switch ((inst >> 25) & 0b11) { 3046 case 0: op = rv_op_fmsub_s; break; 3047 case 1: op = rv_op_fmsub_d; break; 3048 case 3: op = rv_op_fmsub_q; break; 3049 } 3050 break; 3051 case 18: 3052 switch ((inst >> 25) & 0b11) { 3053 case 0: op = rv_op_fnmsub_s; break; 3054 case 1: op = rv_op_fnmsub_d; break; 3055 case 3: op = rv_op_fnmsub_q; break; 3056 } 3057 break; 3058 case 19: 3059 switch ((inst >> 25) & 0b11) { 3060 case 0: op = rv_op_fnmadd_s; break; 3061 case 1: op = rv_op_fnmadd_d; break; 3062 case 3: op = rv_op_fnmadd_q; break; 3063 } 3064 break; 3065 case 20: 3066 switch ((inst >> 25) & 0b1111111) { 3067 case 0: op = rv_op_fadd_s; break; 3068 case 1: op = rv_op_fadd_d; break; 3069 case 3: op = rv_op_fadd_q; break; 3070 case 4: op = rv_op_fsub_s; break; 3071 case 5: op = rv_op_fsub_d; break; 3072 case 7: op = rv_op_fsub_q; break; 3073 case 8: op = rv_op_fmul_s; break; 3074 case 9: op = rv_op_fmul_d; break; 3075 case 11: op = rv_op_fmul_q; break; 3076 case 12: op = rv_op_fdiv_s; break; 3077 case 13: op = rv_op_fdiv_d; break; 3078 case 15: op = rv_op_fdiv_q; break; 3079 case 16: 3080 switch ((inst >> 12) & 0b111) { 3081 case 0: op = rv_op_fsgnj_s; break; 3082 case 1: op = rv_op_fsgnjn_s; break; 3083 case 2: op = rv_op_fsgnjx_s; break; 3084 } 3085 break; 3086 case 17: 3087 switch ((inst >> 12) & 0b111) { 3088 case 0: op = rv_op_fsgnj_d; break; 3089 case 1: op = rv_op_fsgnjn_d; break; 3090 case 2: op = rv_op_fsgnjx_d; break; 3091 } 3092 break; 3093 case 19: 3094 switch ((inst >> 12) & 0b111) { 3095 case 0: op = rv_op_fsgnj_q; break; 3096 case 1: op = rv_op_fsgnjn_q; break; 3097 case 2: op = rv_op_fsgnjx_q; break; 3098 } 3099 break; 3100 case 20: 3101 switch ((inst >> 12) & 0b111) { 3102 case 0: op = rv_op_fmin_s; break; 3103 case 1: op = rv_op_fmax_s; break; 3104 case 2: op = rv_op_fminm_s; break; 3105 case 3: op = rv_op_fmaxm_s; break; 3106 } 3107 break; 3108 case 21: 3109 switch ((inst >> 12) & 0b111) { 3110 case 0: op = rv_op_fmin_d; break; 3111 case 1: op = rv_op_fmax_d; break; 3112 case 2: op = rv_op_fminm_d; break; 3113 case 3: op = rv_op_fmaxm_d; break; 3114 } 3115 break; 3116 case 22: 3117 switch (((inst >> 12) & 0b111)) { 3118 case 2: op = rv_op_fminm_h; break; 3119 case 3: op = rv_op_fmaxm_h; break; 3120 } 3121 break; 3122 case 23: 3123 switch ((inst >> 12) & 0b111) { 3124 case 0: op = rv_op_fmin_q; break; 3125 case 1: op = rv_op_fmax_q; break; 3126 case 2: op = rv_op_fminm_q; break; 3127 case 3: op = rv_op_fmaxm_q; break; 3128 } 3129 break; 3130 case 32: 3131 switch ((inst >> 20) & 0b11111) { 3132 case 1: op = rv_op_fcvt_s_d; break; 3133 case 3: op = rv_op_fcvt_s_q; break; 3134 case 4: op = rv_op_fround_s; break; 3135 case 5: op = rv_op_froundnx_s; break; 3136 case 6: op = rv_op_fcvt_s_bf16; break; 3137 } 3138 break; 3139 case 33: 3140 switch ((inst >> 20) & 0b11111) { 3141 case 0: op = rv_op_fcvt_d_s; break; 3142 case 3: op = rv_op_fcvt_d_q; break; 3143 case 4: op = rv_op_fround_d; break; 3144 case 5: op = rv_op_froundnx_d; break; 3145 } 3146 break; 3147 case 34: 3148 switch (((inst >> 20) & 0b11111)) { 3149 case 4: op = rv_op_fround_h; break; 3150 case 5: op = rv_op_froundnx_h; break; 3151 case 8: op = rv_op_fcvt_bf16_s; break; 3152 } 3153 break; 3154 case 35: 3155 switch ((inst >> 20) & 0b11111) { 3156 case 0: op = rv_op_fcvt_q_s; break; 3157 case 1: op = rv_op_fcvt_q_d; break; 3158 case 4: op = rv_op_fround_q; break; 3159 case 5: op = rv_op_froundnx_q; break; 3160 } 3161 break; 3162 case 44: 3163 switch ((inst >> 20) & 0b11111) { 3164 case 0: op = rv_op_fsqrt_s; break; 3165 } 3166 break; 3167 case 45: 3168 switch ((inst >> 20) & 0b11111) { 3169 case 0: op = rv_op_fsqrt_d; break; 3170 } 3171 break; 3172 case 47: 3173 switch ((inst >> 20) & 0b11111) { 3174 case 0: op = rv_op_fsqrt_q; break; 3175 } 3176 break; 3177 case 80: 3178 switch ((inst >> 12) & 0b111) { 3179 case 0: op = rv_op_fle_s; break; 3180 case 1: op = rv_op_flt_s; break; 3181 case 2: op = rv_op_feq_s; break; 3182 case 4: op = rv_op_fleq_s; break; 3183 case 5: op = rv_op_fltq_s; break; 3184 } 3185 break; 3186 case 81: 3187 switch ((inst >> 12) & 0b111) { 3188 case 0: op = rv_op_fle_d; break; 3189 case 1: op = rv_op_flt_d; break; 3190 case 2: op = rv_op_feq_d; break; 3191 case 4: op = rv_op_fleq_d; break; 3192 case 5: op = rv_op_fltq_d; break; 3193 } 3194 break; 3195 case 82: 3196 switch (((inst >> 12) & 0b111)) { 3197 case 4: op = rv_op_fleq_h; break; 3198 case 5: op = rv_op_fltq_h; break; 3199 } 3200 break; 3201 case 83: 3202 switch ((inst >> 12) & 0b111) { 3203 case 0: op = rv_op_fle_q; break; 3204 case 1: op = rv_op_flt_q; break; 3205 case 2: op = rv_op_feq_q; break; 3206 case 4: op = rv_op_fleq_q; break; 3207 case 5: op = rv_op_fltq_q; break; 3208 } 3209 break; 3210 case 89: 3211 switch (((inst >> 12) & 0b111)) { 3212 case 0: op = rv_op_fmvp_d_x; break; 3213 } 3214 break; 3215 case 91: 3216 switch (((inst >> 12) & 0b111)) { 3217 case 0: op = rv_op_fmvp_q_x; break; 3218 } 3219 break; 3220 case 96: 3221 switch ((inst >> 20) & 0b11111) { 3222 case 0: op = rv_op_fcvt_w_s; break; 3223 case 1: op = rv_op_fcvt_wu_s; break; 3224 case 2: op = rv_op_fcvt_l_s; break; 3225 case 3: op = rv_op_fcvt_lu_s; break; 3226 } 3227 break; 3228 case 97: 3229 switch ((inst >> 20) & 0b11111) { 3230 case 0: op = rv_op_fcvt_w_d; break; 3231 case 1: op = rv_op_fcvt_wu_d; break; 3232 case 2: op = rv_op_fcvt_l_d; break; 3233 case 3: op = rv_op_fcvt_lu_d; break; 3234 case 8: op = rv_op_fcvtmod_w_d; break; 3235 } 3236 break; 3237 case 99: 3238 switch ((inst >> 20) & 0b11111) { 3239 case 0: op = rv_op_fcvt_w_q; break; 3240 case 1: op = rv_op_fcvt_wu_q; break; 3241 case 2: op = rv_op_fcvt_l_q; break; 3242 case 3: op = rv_op_fcvt_lu_q; break; 3243 } 3244 break; 3245 case 104: 3246 switch ((inst >> 20) & 0b11111) { 3247 case 0: op = rv_op_fcvt_s_w; break; 3248 case 1: op = rv_op_fcvt_s_wu; break; 3249 case 2: op = rv_op_fcvt_s_l; break; 3250 case 3: op = rv_op_fcvt_s_lu; break; 3251 } 3252 break; 3253 case 105: 3254 switch ((inst >> 20) & 0b11111) { 3255 case 0: op = rv_op_fcvt_d_w; break; 3256 case 1: op = rv_op_fcvt_d_wu; break; 3257 case 2: op = rv_op_fcvt_d_l; break; 3258 case 3: op = rv_op_fcvt_d_lu; break; 3259 } 3260 break; 3261 case 107: 3262 switch ((inst >> 20) & 0b11111) { 3263 case 0: op = rv_op_fcvt_q_w; break; 3264 case 1: op = rv_op_fcvt_q_wu; break; 3265 case 2: op = rv_op_fcvt_q_l; break; 3266 case 3: op = rv_op_fcvt_q_lu; break; 3267 } 3268 break; 3269 case 112: 3270 switch (((inst >> 17) & 0b11111000) | 3271 ((inst >> 12) & 0b00000111)) { 3272 case 0: op = rv_op_fmv_x_s; break; 3273 case 1: op = rv_op_fclass_s; break; 3274 } 3275 break; 3276 case 113: 3277 switch (((inst >> 17) & 0b11111000) | 3278 ((inst >> 12) & 0b00000111)) { 3279 case 0: op = rv_op_fmv_x_d; break; 3280 case 1: op = rv_op_fclass_d; break; 3281 case 8: op = rv_op_fmvh_x_d; break; 3282 } 3283 break; 3284 case 114: 3285 switch (((inst >> 17) & 0b11111000) | 3286 ((inst >> 12) & 0b00000111)) { 3287 case 0: op = rv_op_fmv_x_h; break; 3288 } 3289 break; 3290 case 115: 3291 switch (((inst >> 17) & 0b11111000) | 3292 ((inst >> 12) & 0b00000111)) { 3293 case 0: op = rv_op_fmv_x_q; break; 3294 case 1: op = rv_op_fclass_q; break; 3295 case 8: op = rv_op_fmvh_x_q; break; 3296 } 3297 break; 3298 case 120: 3299 switch (((inst >> 17) & 0b11111000) | 3300 ((inst >> 12) & 0b00000111)) { 3301 case 0: op = rv_op_fmv_s_x; break; 3302 case 8: op = rv_op_fli_s; break; 3303 } 3304 break; 3305 case 121: 3306 switch (((inst >> 17) & 0b11111000) | 3307 ((inst >> 12) & 0b00000111)) { 3308 case 0: op = rv_op_fmv_d_x; break; 3309 case 8: op = rv_op_fli_d; break; 3310 } 3311 break; 3312 case 122: 3313 switch (((inst >> 17) & 0b11111000) | 3314 ((inst >> 12) & 0b00000111)) { 3315 case 0: op = rv_op_fmv_h_x; break; 3316 case 8: op = rv_op_fli_h; break; 3317 } 3318 break; 3319 case 123: 3320 switch (((inst >> 17) & 0b11111000) | 3321 ((inst >> 12) & 0b00000111)) { 3322 case 0: op = rv_op_fmv_q_x; break; 3323 case 8: op = rv_op_fli_q; break; 3324 } 3325 break; 3326 } 3327 break; 3328 case 21: 3329 switch ((inst >> 12) & 0b111) { 3330 case 0: 3331 switch ((inst >> 26) & 0b111111) { 3332 case 0: op = rv_op_vadd_vv; break; 3333 case 1: op = rv_op_vandn_vv; break; 3334 case 2: op = rv_op_vsub_vv; break; 3335 case 4: op = rv_op_vminu_vv; break; 3336 case 5: op = rv_op_vmin_vv; break; 3337 case 6: op = rv_op_vmaxu_vv; break; 3338 case 7: op = rv_op_vmax_vv; break; 3339 case 9: op = rv_op_vand_vv; break; 3340 case 10: op = rv_op_vor_vv; break; 3341 case 11: op = rv_op_vxor_vv; break; 3342 case 12: op = rv_op_vrgather_vv; break; 3343 case 14: op = rv_op_vrgatherei16_vv; break; 3344 case 16: 3345 if (((inst >> 25) & 1) == 0) { 3346 op = rv_op_vadc_vvm; 3347 } 3348 break; 3349 case 17: op = rv_op_vmadc_vvm; break; 3350 case 18: 3351 if (((inst >> 25) & 1) == 0) { 3352 op = rv_op_vsbc_vvm; 3353 } 3354 break; 3355 case 19: op = rv_op_vmsbc_vvm; break; 3356 case 20: op = rv_op_vror_vv; break; 3357 case 21: op = rv_op_vrol_vv; break; 3358 case 23: 3359 if (((inst >> 20) & 0b111111) == 32) 3360 op = rv_op_vmv_v_v; 3361 else if (((inst >> 25) & 1) == 0) 3362 op = rv_op_vmerge_vvm; 3363 break; 3364 case 24: op = rv_op_vmseq_vv; break; 3365 case 25: op = rv_op_vmsne_vv; break; 3366 case 26: op = rv_op_vmsltu_vv; break; 3367 case 27: op = rv_op_vmslt_vv; break; 3368 case 28: op = rv_op_vmsleu_vv; break; 3369 case 29: op = rv_op_vmsle_vv; break; 3370 case 32: op = rv_op_vsaddu_vv; break; 3371 case 33: op = rv_op_vsadd_vv; break; 3372 case 34: op = rv_op_vssubu_vv; break; 3373 case 35: op = rv_op_vssub_vv; break; 3374 case 37: op = rv_op_vsll_vv; break; 3375 case 39: op = rv_op_vsmul_vv; break; 3376 case 40: op = rv_op_vsrl_vv; break; 3377 case 41: op = rv_op_vsra_vv; break; 3378 case 42: op = rv_op_vssrl_vv; break; 3379 case 43: op = rv_op_vssra_vv; break; 3380 case 44: op = rv_op_vnsrl_wv; break; 3381 case 45: op = rv_op_vnsra_wv; break; 3382 case 46: op = rv_op_vnclipu_wv; break; 3383 case 47: op = rv_op_vnclip_wv; break; 3384 case 48: op = rv_op_vwredsumu_vs; break; 3385 case 49: op = rv_op_vwredsum_vs; break; 3386 case 53: op = rv_op_vwsll_vv; break; 3387 } 3388 break; 3389 case 1: 3390 switch ((inst >> 26) & 0b111111) { 3391 case 0: op = rv_op_vfadd_vv; break; 3392 case 1: op = rv_op_vfredusum_vs; break; 3393 case 2: op = rv_op_vfsub_vv; break; 3394 case 3: op = rv_op_vfredosum_vs; break; 3395 case 4: op = rv_op_vfmin_vv; break; 3396 case 5: op = rv_op_vfredmin_vs; break; 3397 case 6: op = rv_op_vfmax_vv; break; 3398 case 7: op = rv_op_vfredmax_vs; break; 3399 case 8: op = rv_op_vfsgnj_vv; break; 3400 case 9: op = rv_op_vfsgnjn_vv; break; 3401 case 10: op = rv_op_vfsgnjx_vv; break; 3402 case 16: 3403 switch ((inst >> 15) & 0b11111) { 3404 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break; 3405 } 3406 break; 3407 case 18: 3408 switch ((inst >> 15) & 0b11111) { 3409 case 0: op = rv_op_vfcvt_xu_f_v; break; 3410 case 1: op = rv_op_vfcvt_x_f_v; break; 3411 case 2: op = rv_op_vfcvt_f_xu_v; break; 3412 case 3: op = rv_op_vfcvt_f_x_v; break; 3413 case 6: op = rv_op_vfcvt_rtz_xu_f_v; break; 3414 case 7: op = rv_op_vfcvt_rtz_x_f_v; break; 3415 case 8: op = rv_op_vfwcvt_xu_f_v; break; 3416 case 9: op = rv_op_vfwcvt_x_f_v; break; 3417 case 10: op = rv_op_vfwcvt_f_xu_v; break; 3418 case 11: op = rv_op_vfwcvt_f_x_v; break; 3419 case 12: op = rv_op_vfwcvt_f_f_v; break; 3420 case 13: op = rv_op_vfwcvtbf16_f_f_v; break; 3421 case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break; 3422 case 15: op = rv_op_vfwcvt_rtz_x_f_v; break; 3423 case 16: op = rv_op_vfncvt_xu_f_w; break; 3424 case 17: op = rv_op_vfncvt_x_f_w; break; 3425 case 18: op = rv_op_vfncvt_f_xu_w; break; 3426 case 19: op = rv_op_vfncvt_f_x_w; break; 3427 case 20: op = rv_op_vfncvt_f_f_w; break; 3428 case 21: op = rv_op_vfncvt_rod_f_f_w; break; 3429 case 22: op = rv_op_vfncvt_rtz_xu_f_w; break; 3430 case 23: op = rv_op_vfncvt_rtz_x_f_w; break; 3431 case 29: op = rv_op_vfncvtbf16_f_f_w; break; 3432 } 3433 break; 3434 case 19: 3435 switch ((inst >> 15) & 0b11111) { 3436 case 0: op = rv_op_vfsqrt_v; break; 3437 case 4: op = rv_op_vfrsqrt7_v; break; 3438 case 5: op = rv_op_vfrec7_v; break; 3439 case 16: op = rv_op_vfclass_v; break; 3440 } 3441 break; 3442 case 24: op = rv_op_vmfeq_vv; break; 3443 case 25: op = rv_op_vmfle_vv; break; 3444 case 27: op = rv_op_vmflt_vv; break; 3445 case 28: op = rv_op_vmfne_vv; break; 3446 case 32: op = rv_op_vfdiv_vv; break; 3447 case 36: op = rv_op_vfmul_vv; break; 3448 case 40: op = rv_op_vfmadd_vv; break; 3449 case 41: op = rv_op_vfnmadd_vv; break; 3450 case 42: op = rv_op_vfmsub_vv; break; 3451 case 43: op = rv_op_vfnmsub_vv; break; 3452 case 44: op = rv_op_vfmacc_vv; break; 3453 case 45: op = rv_op_vfnmacc_vv; break; 3454 case 46: op = rv_op_vfmsac_vv; break; 3455 case 47: op = rv_op_vfnmsac_vv; break; 3456 case 48: op = rv_op_vfwadd_vv; break; 3457 case 49: op = rv_op_vfwredusum_vs; break; 3458 case 50: op = rv_op_vfwsub_vv; break; 3459 case 51: op = rv_op_vfwredosum_vs; break; 3460 case 52: op = rv_op_vfwadd_wv; break; 3461 case 54: op = rv_op_vfwsub_wv; break; 3462 case 56: op = rv_op_vfwmul_vv; break; 3463 case 59: op = rv_op_vfwmaccbf16_vv; break; 3464 case 60: op = rv_op_vfwmacc_vv; break; 3465 case 61: op = rv_op_vfwnmacc_vv; break; 3466 case 62: op = rv_op_vfwmsac_vv; break; 3467 case 63: op = rv_op_vfwnmsac_vv; break; 3468 } 3469 break; 3470 case 2: 3471 switch ((inst >> 26) & 0b111111) { 3472 case 0: op = rv_op_vredsum_vs; break; 3473 case 1: op = rv_op_vredand_vs; break; 3474 case 2: op = rv_op_vredor_vs; break; 3475 case 3: op = rv_op_vredxor_vs; break; 3476 case 4: op = rv_op_vredminu_vs; break; 3477 case 5: op = rv_op_vredmin_vs; break; 3478 case 6: op = rv_op_vredmaxu_vs; break; 3479 case 7: op = rv_op_vredmax_vs; break; 3480 case 8: op = rv_op_vaaddu_vv; break; 3481 case 9: op = rv_op_vaadd_vv; break; 3482 case 10: op = rv_op_vasubu_vv; break; 3483 case 11: op = rv_op_vasub_vv; break; 3484 case 12: op = rv_op_vclmul_vv; break; 3485 case 13: op = rv_op_vclmulh_vv; break; 3486 case 16: 3487 switch ((inst >> 15) & 0b11111) { 3488 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break; 3489 case 16: op = rv_op_vcpop_m; break; 3490 case 17: op = rv_op_vfirst_m; break; 3491 } 3492 break; 3493 case 18: 3494 switch ((inst >> 15) & 0b11111) { 3495 case 2: op = rv_op_vzext_vf8; break; 3496 case 3: op = rv_op_vsext_vf8; break; 3497 case 4: op = rv_op_vzext_vf4; break; 3498 case 5: op = rv_op_vsext_vf4; break; 3499 case 6: op = rv_op_vzext_vf2; break; 3500 case 7: op = rv_op_vsext_vf2; break; 3501 case 8: op = rv_op_vbrev8_v; break; 3502 case 9: op = rv_op_vrev8_v; break; 3503 case 10: op = rv_op_vbrev_v; break; 3504 case 12: op = rv_op_vclz_v; break; 3505 case 13: op = rv_op_vctz_v; break; 3506 case 14: op = rv_op_vcpop_v; break; 3507 } 3508 break; 3509 case 20: 3510 switch ((inst >> 15) & 0b11111) { 3511 case 1: op = rv_op_vmsbf_m; break; 3512 case 2: op = rv_op_vmsof_m; break; 3513 case 3: op = rv_op_vmsif_m; break; 3514 case 16: op = rv_op_viota_m; break; 3515 case 17: 3516 if (((inst >> 20) & 0b11111) == 0) { 3517 op = rv_op_vid_v; 3518 } 3519 break; 3520 } 3521 break; 3522 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break; 3523 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break; 3524 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break; 3525 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break; 3526 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break; 3527 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break; 3528 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break; 3529 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break; 3530 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break; 3531 case 32: op = rv_op_vdivu_vv; break; 3532 case 33: op = rv_op_vdiv_vv; break; 3533 case 34: op = rv_op_vremu_vv; break; 3534 case 35: op = rv_op_vrem_vv; break; 3535 case 36: op = rv_op_vmulhu_vv; break; 3536 case 37: op = rv_op_vmul_vv; break; 3537 case 38: op = rv_op_vmulhsu_vv; break; 3538 case 39: op = rv_op_vmulh_vv; break; 3539 case 41: op = rv_op_vmadd_vv; break; 3540 case 43: op = rv_op_vnmsub_vv; break; 3541 case 45: op = rv_op_vmacc_vv; break; 3542 case 47: op = rv_op_vnmsac_vv; break; 3543 case 48: op = rv_op_vwaddu_vv; break; 3544 case 49: op = rv_op_vwadd_vv; break; 3545 case 50: op = rv_op_vwsubu_vv; break; 3546 case 51: op = rv_op_vwsub_vv; break; 3547 case 52: op = rv_op_vwaddu_wv; break; 3548 case 53: op = rv_op_vwadd_wv; break; 3549 case 54: op = rv_op_vwsubu_wv; break; 3550 case 55: op = rv_op_vwsub_wv; break; 3551 case 56: op = rv_op_vwmulu_vv; break; 3552 case 58: op = rv_op_vwmulsu_vv; break; 3553 case 59: op = rv_op_vwmul_vv; break; 3554 case 60: op = rv_op_vwmaccu_vv; break; 3555 case 61: op = rv_op_vwmacc_vv; break; 3556 case 63: op = rv_op_vwmaccsu_vv; break; 3557 } 3558 break; 3559 case 3: 3560 switch ((inst >> 26) & 0b111111) { 3561 case 0: op = rv_op_vadd_vi; break; 3562 case 3: op = rv_op_vrsub_vi; break; 3563 case 9: op = rv_op_vand_vi; break; 3564 case 10: op = rv_op_vor_vi; break; 3565 case 11: op = rv_op_vxor_vi; break; 3566 case 12: op = rv_op_vrgather_vi; break; 3567 case 14: op = rv_op_vslideup_vi; break; 3568 case 15: op = rv_op_vslidedown_vi; break; 3569 case 16: 3570 if (((inst >> 25) & 1) == 0) { 3571 op = rv_op_vadc_vim; 3572 } 3573 break; 3574 case 17: op = rv_op_vmadc_vim; break; 3575 case 20: case 21: op = rv_op_vror_vi; break; 3576 case 23: 3577 if (((inst >> 20) & 0b111111) == 32) 3578 op = rv_op_vmv_v_i; 3579 else if (((inst >> 25) & 1) == 0) 3580 op = rv_op_vmerge_vim; 3581 break; 3582 case 24: op = rv_op_vmseq_vi; break; 3583 case 25: op = rv_op_vmsne_vi; break; 3584 case 28: op = rv_op_vmsleu_vi; break; 3585 case 29: op = rv_op_vmsle_vi; break; 3586 case 30: op = rv_op_vmsgtu_vi; break; 3587 case 31: op = rv_op_vmsgt_vi; break; 3588 case 32: op = rv_op_vsaddu_vi; break; 3589 case 33: op = rv_op_vsadd_vi; break; 3590 case 37: op = rv_op_vsll_vi; break; 3591 case 39: 3592 switch ((inst >> 15) & 0b11111) { 3593 case 0: op = rv_op_vmv1r_v; break; 3594 case 1: op = rv_op_vmv2r_v; break; 3595 case 3: op = rv_op_vmv4r_v; break; 3596 case 7: op = rv_op_vmv8r_v; break; 3597 } 3598 break; 3599 case 40: op = rv_op_vsrl_vi; break; 3600 case 41: op = rv_op_vsra_vi; break; 3601 case 42: op = rv_op_vssrl_vi; break; 3602 case 43: op = rv_op_vssra_vi; break; 3603 case 44: op = rv_op_vnsrl_wi; break; 3604 case 45: op = rv_op_vnsra_wi; break; 3605 case 46: op = rv_op_vnclipu_wi; break; 3606 case 47: op = rv_op_vnclip_wi; break; 3607 case 53: op = rv_op_vwsll_vi; break; 3608 } 3609 break; 3610 case 4: 3611 switch ((inst >> 26) & 0b111111) { 3612 case 0: op = rv_op_vadd_vx; break; 3613 case 1: op = rv_op_vandn_vx; break; 3614 case 2: op = rv_op_vsub_vx; break; 3615 case 3: op = rv_op_vrsub_vx; break; 3616 case 4: op = rv_op_vminu_vx; break; 3617 case 5: op = rv_op_vmin_vx; break; 3618 case 6: op = rv_op_vmaxu_vx; break; 3619 case 7: op = rv_op_vmax_vx; break; 3620 case 9: op = rv_op_vand_vx; break; 3621 case 10: op = rv_op_vor_vx; break; 3622 case 11: op = rv_op_vxor_vx; break; 3623 case 12: op = rv_op_vrgather_vx; break; 3624 case 14: op = rv_op_vslideup_vx; break; 3625 case 15: op = rv_op_vslidedown_vx; break; 3626 case 16: 3627 if (((inst >> 25) & 1) == 0) { 3628 op = rv_op_vadc_vxm; 3629 } 3630 break; 3631 case 17: op = rv_op_vmadc_vxm; break; 3632 case 18: 3633 if (((inst >> 25) & 1) == 0) { 3634 op = rv_op_vsbc_vxm; 3635 } 3636 break; 3637 case 19: op = rv_op_vmsbc_vxm; break; 3638 case 20: op = rv_op_vror_vx; break; 3639 case 21: op = rv_op_vrol_vx; break; 3640 case 23: 3641 if (((inst >> 20) & 0b111111) == 32) 3642 op = rv_op_vmv_v_x; 3643 else if (((inst >> 25) & 1) == 0) 3644 op = rv_op_vmerge_vxm; 3645 break; 3646 case 24: op = rv_op_vmseq_vx; break; 3647 case 25: op = rv_op_vmsne_vx; break; 3648 case 26: op = rv_op_vmsltu_vx; break; 3649 case 27: op = rv_op_vmslt_vx; break; 3650 case 28: op = rv_op_vmsleu_vx; break; 3651 case 29: op = rv_op_vmsle_vx; break; 3652 case 30: op = rv_op_vmsgtu_vx; break; 3653 case 31: op = rv_op_vmsgt_vx; break; 3654 case 32: op = rv_op_vsaddu_vx; break; 3655 case 33: op = rv_op_vsadd_vx; break; 3656 case 34: op = rv_op_vssubu_vx; break; 3657 case 35: op = rv_op_vssub_vx; break; 3658 case 37: op = rv_op_vsll_vx; break; 3659 case 39: op = rv_op_vsmul_vx; break; 3660 case 40: op = rv_op_vsrl_vx; break; 3661 case 41: op = rv_op_vsra_vx; break; 3662 case 42: op = rv_op_vssrl_vx; break; 3663 case 43: op = rv_op_vssra_vx; break; 3664 case 44: op = rv_op_vnsrl_wx; break; 3665 case 45: op = rv_op_vnsra_wx; break; 3666 case 46: op = rv_op_vnclipu_wx; break; 3667 case 47: op = rv_op_vnclip_wx; break; 3668 case 53: op = rv_op_vwsll_vx; break; 3669 } 3670 break; 3671 case 5: 3672 switch ((inst >> 26) & 0b111111) { 3673 case 0: op = rv_op_vfadd_vf; break; 3674 case 2: op = rv_op_vfsub_vf; break; 3675 case 4: op = rv_op_vfmin_vf; break; 3676 case 6: op = rv_op_vfmax_vf; break; 3677 case 8: op = rv_op_vfsgnj_vf; break; 3678 case 9: op = rv_op_vfsgnjn_vf; break; 3679 case 10: op = rv_op_vfsgnjx_vf; break; 3680 case 14: op = rv_op_vfslide1up_vf; break; 3681 case 15: op = rv_op_vfslide1down_vf; break; 3682 case 16: 3683 switch ((inst >> 20) & 0b11111) { 3684 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break; 3685 } 3686 break; 3687 case 23: 3688 if (((inst >> 25) & 1) == 0) 3689 op = rv_op_vfmerge_vfm; 3690 else if (((inst >> 20) & 0b111111) == 32) 3691 op = rv_op_vfmv_v_f; 3692 break; 3693 case 24: op = rv_op_vmfeq_vf; break; 3694 case 25: op = rv_op_vmfle_vf; break; 3695 case 27: op = rv_op_vmflt_vf; break; 3696 case 28: op = rv_op_vmfne_vf; break; 3697 case 29: op = rv_op_vmfgt_vf; break; 3698 case 31: op = rv_op_vmfge_vf; break; 3699 case 32: op = rv_op_vfdiv_vf; break; 3700 case 33: op = rv_op_vfrdiv_vf; break; 3701 case 36: op = rv_op_vfmul_vf; break; 3702 case 39: op = rv_op_vfrsub_vf; break; 3703 case 40: op = rv_op_vfmadd_vf; break; 3704 case 41: op = rv_op_vfnmadd_vf; break; 3705 case 42: op = rv_op_vfmsub_vf; break; 3706 case 43: op = rv_op_vfnmsub_vf; break; 3707 case 44: op = rv_op_vfmacc_vf; break; 3708 case 45: op = rv_op_vfnmacc_vf; break; 3709 case 46: op = rv_op_vfmsac_vf; break; 3710 case 47: op = rv_op_vfnmsac_vf; break; 3711 case 48: op = rv_op_vfwadd_vf; break; 3712 case 50: op = rv_op_vfwsub_vf; break; 3713 case 52: op = rv_op_vfwadd_wf; break; 3714 case 54: op = rv_op_vfwsub_wf; break; 3715 case 56: op = rv_op_vfwmul_vf; break; 3716 case 59: op = rv_op_vfwmaccbf16_vf; break; 3717 case 60: op = rv_op_vfwmacc_vf; break; 3718 case 61: op = rv_op_vfwnmacc_vf; break; 3719 case 62: op = rv_op_vfwmsac_vf; break; 3720 case 63: op = rv_op_vfwnmsac_vf; break; 3721 } 3722 break; 3723 case 6: 3724 switch ((inst >> 26) & 0b111111) { 3725 case 8: op = rv_op_vaaddu_vx; break; 3726 case 9: op = rv_op_vaadd_vx; break; 3727 case 10: op = rv_op_vasubu_vx; break; 3728 case 11: op = rv_op_vasub_vx; break; 3729 case 12: op = rv_op_vclmul_vx; break; 3730 case 13: op = rv_op_vclmulh_vx; break; 3731 case 14: op = rv_op_vslide1up_vx; break; 3732 case 15: op = rv_op_vslide1down_vx; break; 3733 case 16: 3734 switch ((inst >> 20) & 0b11111) { 3735 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break; 3736 } 3737 break; 3738 case 32: op = rv_op_vdivu_vx; break; 3739 case 33: op = rv_op_vdiv_vx; break; 3740 case 34: op = rv_op_vremu_vx; break; 3741 case 35: op = rv_op_vrem_vx; break; 3742 case 36: op = rv_op_vmulhu_vx; break; 3743 case 37: op = rv_op_vmul_vx; break; 3744 case 38: op = rv_op_vmulhsu_vx; break; 3745 case 39: op = rv_op_vmulh_vx; break; 3746 case 41: op = rv_op_vmadd_vx; break; 3747 case 43: op = rv_op_vnmsub_vx; break; 3748 case 45: op = rv_op_vmacc_vx; break; 3749 case 47: op = rv_op_vnmsac_vx; break; 3750 case 48: op = rv_op_vwaddu_vx; break; 3751 case 49: op = rv_op_vwadd_vx; break; 3752 case 50: op = rv_op_vwsubu_vx; break; 3753 case 51: op = rv_op_vwsub_vx; break; 3754 case 52: op = rv_op_vwaddu_wx; break; 3755 case 53: op = rv_op_vwadd_wx; break; 3756 case 54: op = rv_op_vwsubu_wx; break; 3757 case 55: op = rv_op_vwsub_wx; break; 3758 case 56: op = rv_op_vwmulu_vx; break; 3759 case 58: op = rv_op_vwmulsu_vx; break; 3760 case 59: op = rv_op_vwmul_vx; break; 3761 case 60: op = rv_op_vwmaccu_vx; break; 3762 case 61: op = rv_op_vwmacc_vx; break; 3763 case 62: op = rv_op_vwmaccus_vx; break; 3764 case 63: op = rv_op_vwmaccsu_vx; break; 3765 } 3766 break; 3767 case 7: 3768 if (((inst >> 31) & 1) == 0) { 3769 op = rv_op_vsetvli; 3770 } else if ((inst >> 30) & 1) { 3771 op = rv_op_vsetivli; 3772 } else if (((inst >> 25) & 0b11111) == 0) { 3773 op = rv_op_vsetvl; 3774 } 3775 break; 3776 } 3777 break; 3778 case 22: 3779 switch ((inst >> 12) & 0b111) { 3780 case 0: op = rv_op_addid; break; 3781 case 1: 3782 switch ((inst >> 26) & 0b111111) { 3783 case 0: op = rv_op_sllid; break; 3784 } 3785 break; 3786 case 5: 3787 switch ((inst >> 26) & 0b111111) { 3788 case 0: op = rv_op_srlid; break; 3789 case 16: op = rv_op_sraid; break; 3790 } 3791 break; 3792 } 3793 break; 3794 case 24: 3795 switch ((inst >> 12) & 0b111) { 3796 case 0: op = rv_op_beq; break; 3797 case 1: op = rv_op_bne; break; 3798 case 4: op = rv_op_blt; break; 3799 case 5: op = rv_op_bge; break; 3800 case 6: op = rv_op_bltu; break; 3801 case 7: op = rv_op_bgeu; break; 3802 } 3803 break; 3804 case 25: 3805 switch ((inst >> 12) & 0b111) { 3806 case 0: op = rv_op_jalr; break; 3807 } 3808 break; 3809 case 27: op = rv_op_jal; break; 3810 case 28: 3811 switch ((inst >> 12) & 0b111) { 3812 case 0: 3813 switch (((inst >> 20) & 0b111111100000) | 3814 ((inst >> 7) & 0b000000011111)) { 3815 case 0: 3816 switch ((inst >> 15) & 0b1111111111) { 3817 case 0: op = rv_op_ecall; break; 3818 case 32: op = rv_op_ebreak; break; 3819 case 64: op = rv_op_uret; break; 3820 } 3821 break; 3822 case 256: 3823 switch ((inst >> 20) & 0b11111) { 3824 case 2: 3825 switch ((inst >> 15) & 0b11111) { 3826 case 0: op = rv_op_sret; break; 3827 } 3828 break; 3829 case 4: op = rv_op_sfence_vm; break; 3830 case 5: 3831 switch ((inst >> 15) & 0b11111) { 3832 case 0: op = rv_op_wfi; break; 3833 } 3834 break; 3835 } 3836 break; 3837 case 288: op = rv_op_sfence_vma; break; 3838 case 512: 3839 switch ((inst >> 15) & 0b1111111111) { 3840 case 64: op = rv_op_hret; break; 3841 } 3842 break; 3843 case 768: 3844 switch ((inst >> 15) & 0b1111111111) { 3845 case 64: op = rv_op_mret; break; 3846 } 3847 break; 3848 case 1952: 3849 switch ((inst >> 15) & 0b1111111111) { 3850 case 576: op = rv_op_dret; break; 3851 } 3852 break; 3853 } 3854 break; 3855 case 1: op = rv_op_csrrw; break; 3856 case 2: op = rv_op_csrrs; break; 3857 case 3: op = rv_op_csrrc; break; 3858 case 5: op = rv_op_csrrwi; break; 3859 case 6: op = rv_op_csrrsi; break; 3860 case 7: op = rv_op_csrrci; break; 3861 } 3862 break; 3863 case 29: 3864 if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) { 3865 switch ((inst >> 26) & 0b111111) { 3866 case 32: op = rv_op_vsm3me_vv; break; 3867 case 33: op = rv_op_vsm4k_vi; break; 3868 case 34: op = rv_op_vaeskf1_vi; break; 3869 case 40: 3870 switch ((inst >> 15) & 0b11111) { 3871 case 0: op = rv_op_vaesdm_vv; break; 3872 case 1: op = rv_op_vaesdf_vv; break; 3873 case 2: op = rv_op_vaesem_vv; break; 3874 case 3: op = rv_op_vaesef_vv; break; 3875 case 16: op = rv_op_vsm4r_vv; break; 3876 case 17: op = rv_op_vgmul_vv; break; 3877 } 3878 break; 3879 case 41: 3880 switch ((inst >> 15) & 0b11111) { 3881 case 0: op = rv_op_vaesdm_vs; break; 3882 case 1: op = rv_op_vaesdf_vs; break; 3883 case 2: op = rv_op_vaesem_vs; break; 3884 case 3: op = rv_op_vaesef_vs; break; 3885 case 7: op = rv_op_vaesz_vs; break; 3886 case 16: op = rv_op_vsm4r_vs; break; 3887 } 3888 break; 3889 case 42: op = rv_op_vaeskf2_vi; break; 3890 case 43: op = rv_op_vsm3c_vi; break; 3891 case 44: op = rv_op_vghsh_vv; break; 3892 case 45: op = rv_op_vsha2ms_vv; break; 3893 case 46: op = rv_op_vsha2ch_vv; break; 3894 case 47: op = rv_op_vsha2cl_vv; break; 3895 } 3896 } 3897 break; 3898 case 30: 3899 switch (((inst >> 22) & 0b1111111000) | 3900 ((inst >> 12) & 0b0000000111)) { 3901 case 0: op = rv_op_addd; break; 3902 case 1: op = rv_op_slld; break; 3903 case 5: op = rv_op_srld; break; 3904 case 8: op = rv_op_muld; break; 3905 case 12: op = rv_op_divd; break; 3906 case 13: op = rv_op_divud; break; 3907 case 14: op = rv_op_remd; break; 3908 case 15: op = rv_op_remud; break; 3909 case 256: op = rv_op_subd; break; 3910 case 261: op = rv_op_srad; break; 3911 } 3912 break; 3913 } 3914 break; 3915 } 3916 dec->op = op; 3917 } 3918 3919 /* operand extractors */ 3920 3921 static uint32_t operand_rd(rv_inst inst) 3922 { 3923 return (inst << 52) >> 59; 3924 } 3925 3926 static uint32_t operand_rs1(rv_inst inst) 3927 { 3928 return (inst << 44) >> 59; 3929 } 3930 3931 static uint32_t operand_rs2(rv_inst inst) 3932 { 3933 return (inst << 39) >> 59; 3934 } 3935 3936 static uint32_t operand_rs3(rv_inst inst) 3937 { 3938 return (inst << 32) >> 59; 3939 } 3940 3941 static uint32_t operand_aq(rv_inst inst) 3942 { 3943 return (inst << 37) >> 63; 3944 } 3945 3946 static uint32_t operand_rl(rv_inst inst) 3947 { 3948 return (inst << 38) >> 63; 3949 } 3950 3951 static uint32_t operand_pred(rv_inst inst) 3952 { 3953 return (inst << 36) >> 60; 3954 } 3955 3956 static uint32_t operand_succ(rv_inst inst) 3957 { 3958 return (inst << 40) >> 60; 3959 } 3960 3961 static uint32_t operand_rm(rv_inst inst) 3962 { 3963 return (inst << 49) >> 61; 3964 } 3965 3966 static uint32_t operand_shamt5(rv_inst inst) 3967 { 3968 return (inst << 39) >> 59; 3969 } 3970 3971 static uint32_t operand_shamt6(rv_inst inst) 3972 { 3973 return (inst << 38) >> 58; 3974 } 3975 3976 static uint32_t operand_shamt7(rv_inst inst) 3977 { 3978 return (inst << 37) >> 57; 3979 } 3980 3981 static uint32_t operand_crdq(rv_inst inst) 3982 { 3983 return (inst << 59) >> 61; 3984 } 3985 3986 static uint32_t operand_crs1q(rv_inst inst) 3987 { 3988 return (inst << 54) >> 61; 3989 } 3990 3991 static uint32_t operand_crs1rdq(rv_inst inst) 3992 { 3993 return (inst << 54) >> 61; 3994 } 3995 3996 static uint32_t operand_crs2q(rv_inst inst) 3997 { 3998 return (inst << 59) >> 61; 3999 } 4000 4001 static uint32_t calculate_xreg(uint32_t sreg) 4002 { 4003 return sreg < 2 ? sreg + 8 : sreg + 16; 4004 } 4005 4006 static uint32_t operand_sreg1(rv_inst inst) 4007 { 4008 return calculate_xreg((inst << 54) >> 61); 4009 } 4010 4011 static uint32_t operand_sreg2(rv_inst inst) 4012 { 4013 return calculate_xreg((inst << 59) >> 61); 4014 } 4015 4016 static uint32_t operand_crd(rv_inst inst) 4017 { 4018 return (inst << 52) >> 59; 4019 } 4020 4021 static uint32_t operand_crs1(rv_inst inst) 4022 { 4023 return (inst << 52) >> 59; 4024 } 4025 4026 static uint32_t operand_crs1rd(rv_inst inst) 4027 { 4028 return (inst << 52) >> 59; 4029 } 4030 4031 static uint32_t operand_crs2(rv_inst inst) 4032 { 4033 return (inst << 57) >> 59; 4034 } 4035 4036 static uint32_t operand_cimmsh5(rv_inst inst) 4037 { 4038 return (inst << 57) >> 59; 4039 } 4040 4041 static uint32_t operand_csr12(rv_inst inst) 4042 { 4043 return (inst << 32) >> 52; 4044 } 4045 4046 static int32_t operand_imm12(rv_inst inst) 4047 { 4048 return ((int64_t)inst << 32) >> 52; 4049 } 4050 4051 static int32_t operand_imm20(rv_inst inst) 4052 { 4053 return (((int64_t)inst << 32) >> 44) << 12; 4054 } 4055 4056 static int32_t operand_jimm20(rv_inst inst) 4057 { 4058 return (((int64_t)inst << 32) >> 63) << 20 | 4059 ((inst << 33) >> 54) << 1 | 4060 ((inst << 43) >> 63) << 11 | 4061 ((inst << 44) >> 56) << 12; 4062 } 4063 4064 static int32_t operand_simm12(rv_inst inst) 4065 { 4066 return (((int64_t)inst << 32) >> 57) << 5 | 4067 (inst << 52) >> 59; 4068 } 4069 4070 static int32_t operand_sbimm12(rv_inst inst) 4071 { 4072 return (((int64_t)inst << 32) >> 63) << 12 | 4073 ((inst << 33) >> 58) << 5 | 4074 ((inst << 52) >> 60) << 1 | 4075 ((inst << 56) >> 63) << 11; 4076 } 4077 4078 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) 4079 { 4080 int imm = ((inst << 51) >> 63) << 5 | 4081 (inst << 57) >> 59; 4082 if (isa == rv128) { 4083 imm = imm ? imm : 64; 4084 } 4085 return imm; 4086 } 4087 4088 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) 4089 { 4090 int imm = ((inst << 51) >> 63) << 5 | 4091 (inst << 57) >> 59; 4092 if (isa == rv128) { 4093 imm = imm | (imm & 32) << 1; 4094 imm = imm ? imm : 64; 4095 } 4096 return imm; 4097 } 4098 4099 static int32_t operand_cimmi(rv_inst inst) 4100 { 4101 return (((int64_t)inst << 51) >> 63) << 5 | 4102 (inst << 57) >> 59; 4103 } 4104 4105 static int32_t operand_cimmui(rv_inst inst) 4106 { 4107 return (((int64_t)inst << 51) >> 63) << 17 | 4108 ((inst << 57) >> 59) << 12; 4109 } 4110 4111 static uint32_t operand_cimmlwsp(rv_inst inst) 4112 { 4113 return ((inst << 51) >> 63) << 5 | 4114 ((inst << 57) >> 61) << 2 | 4115 ((inst << 60) >> 62) << 6; 4116 } 4117 4118 static uint32_t operand_cimmldsp(rv_inst inst) 4119 { 4120 return ((inst << 51) >> 63) << 5 | 4121 ((inst << 57) >> 62) << 3 | 4122 ((inst << 59) >> 61) << 6; 4123 } 4124 4125 static uint32_t operand_cimmlqsp(rv_inst inst) 4126 { 4127 return ((inst << 51) >> 63) << 5 | 4128 ((inst << 57) >> 63) << 4 | 4129 ((inst << 58) >> 60) << 6; 4130 } 4131 4132 static int32_t operand_cimm16sp(rv_inst inst) 4133 { 4134 return (((int64_t)inst << 51) >> 63) << 9 | 4135 ((inst << 57) >> 63) << 4 | 4136 ((inst << 58) >> 63) << 6 | 4137 ((inst << 59) >> 62) << 7 | 4138 ((inst << 61) >> 63) << 5; 4139 } 4140 4141 static int32_t operand_cimmj(rv_inst inst) 4142 { 4143 return (((int64_t)inst << 51) >> 63) << 11 | 4144 ((inst << 52) >> 63) << 4 | 4145 ((inst << 53) >> 62) << 8 | 4146 ((inst << 55) >> 63) << 10 | 4147 ((inst << 56) >> 63) << 6 | 4148 ((inst << 57) >> 63) << 7 | 4149 ((inst << 58) >> 61) << 1 | 4150 ((inst << 61) >> 63) << 5; 4151 } 4152 4153 static int32_t operand_cimmb(rv_inst inst) 4154 { 4155 return (((int64_t)inst << 51) >> 63) << 8 | 4156 ((inst << 52) >> 62) << 3 | 4157 ((inst << 57) >> 62) << 6 | 4158 ((inst << 59) >> 62) << 1 | 4159 ((inst << 61) >> 63) << 5; 4160 } 4161 4162 static uint32_t operand_cimmswsp(rv_inst inst) 4163 { 4164 return ((inst << 51) >> 60) << 2 | 4165 ((inst << 55) >> 62) << 6; 4166 } 4167 4168 static uint32_t operand_cimmsdsp(rv_inst inst) 4169 { 4170 return ((inst << 51) >> 61) << 3 | 4171 ((inst << 54) >> 61) << 6; 4172 } 4173 4174 static uint32_t operand_cimmsqsp(rv_inst inst) 4175 { 4176 return ((inst << 51) >> 62) << 4 | 4177 ((inst << 53) >> 60) << 6; 4178 } 4179 4180 static uint32_t operand_cimm4spn(rv_inst inst) 4181 { 4182 return ((inst << 51) >> 62) << 4 | 4183 ((inst << 53) >> 60) << 6 | 4184 ((inst << 57) >> 63) << 2 | 4185 ((inst << 58) >> 63) << 3; 4186 } 4187 4188 static uint32_t operand_cimmw(rv_inst inst) 4189 { 4190 return ((inst << 51) >> 61) << 3 | 4191 ((inst << 57) >> 63) << 2 | 4192 ((inst << 58) >> 63) << 6; 4193 } 4194 4195 static uint32_t operand_cimmd(rv_inst inst) 4196 { 4197 return ((inst << 51) >> 61) << 3 | 4198 ((inst << 57) >> 62) << 6; 4199 } 4200 4201 static uint32_t operand_cimmq(rv_inst inst) 4202 { 4203 return ((inst << 51) >> 62) << 4 | 4204 ((inst << 53) >> 63) << 8 | 4205 ((inst << 57) >> 62) << 6; 4206 } 4207 4208 static uint32_t operand_vimm(rv_inst inst) 4209 { 4210 return (int64_t)(inst << 44) >> 59; 4211 } 4212 4213 static uint32_t operand_vzimm11(rv_inst inst) 4214 { 4215 return (inst << 33) >> 53; 4216 } 4217 4218 static uint32_t operand_vzimm10(rv_inst inst) 4219 { 4220 return (inst << 34) >> 54; 4221 } 4222 4223 static uint32_t operand_vzimm6(rv_inst inst) 4224 { 4225 return ((inst << 37) >> 63) << 5 | 4226 ((inst << 44) >> 59); 4227 } 4228 4229 static uint32_t operand_bs(rv_inst inst) 4230 { 4231 return (inst << 32) >> 62; 4232 } 4233 4234 static uint32_t operand_rnum(rv_inst inst) 4235 { 4236 return (inst << 40) >> 60; 4237 } 4238 4239 static uint32_t operand_vm(rv_inst inst) 4240 { 4241 return (inst << 38) >> 63; 4242 } 4243 4244 static uint32_t operand_uimm_c_lb(rv_inst inst) 4245 { 4246 return (((inst << 58) >> 63) << 1) | 4247 ((inst << 57) >> 63); 4248 } 4249 4250 static uint32_t operand_uimm_c_lh(rv_inst inst) 4251 { 4252 return (((inst << 58) >> 63) << 1); 4253 } 4254 4255 static uint32_t operand_zcmp_spimm(rv_inst inst) 4256 { 4257 return ((inst << 60) >> 62) << 4; 4258 } 4259 4260 static uint32_t operand_zcmp_rlist(rv_inst inst) 4261 { 4262 return ((inst << 56) >> 60); 4263 } 4264 4265 static uint32_t operand_imm6(rv_inst inst) 4266 { 4267 return (inst << 38) >> 60; 4268 } 4269 4270 static uint32_t operand_imm2(rv_inst inst) 4271 { 4272 return (inst << 37) >> 62; 4273 } 4274 4275 static uint32_t operand_immh(rv_inst inst) 4276 { 4277 return (inst << 32) >> 58; 4278 } 4279 4280 static uint32_t operand_imml(rv_inst inst) 4281 { 4282 return (inst << 38) >> 58; 4283 } 4284 4285 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm) 4286 { 4287 int xlen_bytes_log2 = isa == rv64 ? 3 : 2; 4288 int regs = rlist == 15 ? 13 : rlist - 3; 4289 uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16); 4290 return stack_adj_base + spimm; 4291 } 4292 4293 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa) 4294 { 4295 return calculate_stack_adj(isa, operand_zcmp_rlist(inst), 4296 operand_zcmp_spimm(inst)); 4297 } 4298 4299 static uint32_t operand_tbl_index(rv_inst inst) 4300 { 4301 return ((inst << 54) >> 56); 4302 } 4303 4304 /* decode operands */ 4305 4306 static void decode_inst_operands(rv_decode *dec, rv_isa isa) 4307 { 4308 const rv_opcode_data *opcode_data = dec->opcode_data; 4309 rv_inst inst = dec->inst; 4310 dec->codec = opcode_data[dec->op].codec; 4311 switch (dec->codec) { 4312 case rv_codec_none: 4313 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4314 dec->imm = 0; 4315 break; 4316 case rv_codec_u: 4317 dec->rd = operand_rd(inst); 4318 dec->rs1 = dec->rs2 = rv_ireg_zero; 4319 dec->imm = operand_imm20(inst); 4320 break; 4321 case rv_codec_uj: 4322 dec->rd = operand_rd(inst); 4323 dec->rs1 = dec->rs2 = rv_ireg_zero; 4324 dec->imm = operand_jimm20(inst); 4325 break; 4326 case rv_codec_i: 4327 dec->rd = operand_rd(inst); 4328 dec->rs1 = operand_rs1(inst); 4329 dec->rs2 = rv_ireg_zero; 4330 dec->imm = operand_imm12(inst); 4331 break; 4332 case rv_codec_i_sh5: 4333 dec->rd = operand_rd(inst); 4334 dec->rs1 = operand_rs1(inst); 4335 dec->rs2 = rv_ireg_zero; 4336 dec->imm = operand_shamt5(inst); 4337 break; 4338 case rv_codec_i_sh6: 4339 dec->rd = operand_rd(inst); 4340 dec->rs1 = operand_rs1(inst); 4341 dec->rs2 = rv_ireg_zero; 4342 dec->imm = operand_shamt6(inst); 4343 break; 4344 case rv_codec_i_sh7: 4345 dec->rd = operand_rd(inst); 4346 dec->rs1 = operand_rs1(inst); 4347 dec->rs2 = rv_ireg_zero; 4348 dec->imm = operand_shamt7(inst); 4349 break; 4350 case rv_codec_i_csr: 4351 dec->rd = operand_rd(inst); 4352 dec->rs1 = operand_rs1(inst); 4353 dec->rs2 = rv_ireg_zero; 4354 dec->imm = operand_csr12(inst); 4355 break; 4356 case rv_codec_s: 4357 dec->rd = rv_ireg_zero; 4358 dec->rs1 = operand_rs1(inst); 4359 dec->rs2 = operand_rs2(inst); 4360 dec->imm = operand_simm12(inst); 4361 break; 4362 case rv_codec_sb: 4363 dec->rd = rv_ireg_zero; 4364 dec->rs1 = operand_rs1(inst); 4365 dec->rs2 = operand_rs2(inst); 4366 dec->imm = operand_sbimm12(inst); 4367 break; 4368 case rv_codec_r: 4369 dec->rd = operand_rd(inst); 4370 dec->rs1 = operand_rs1(inst); 4371 dec->rs2 = operand_rs2(inst); 4372 dec->imm = 0; 4373 break; 4374 case rv_codec_r_m: 4375 dec->rd = operand_rd(inst); 4376 dec->rs1 = operand_rs1(inst); 4377 dec->rs2 = operand_rs2(inst); 4378 dec->imm = 0; 4379 dec->rm = operand_rm(inst); 4380 break; 4381 case rv_codec_r4_m: 4382 dec->rd = operand_rd(inst); 4383 dec->rs1 = operand_rs1(inst); 4384 dec->rs2 = operand_rs2(inst); 4385 dec->rs3 = operand_rs3(inst); 4386 dec->imm = 0; 4387 dec->rm = operand_rm(inst); 4388 break; 4389 case rv_codec_r_a: 4390 dec->rd = operand_rd(inst); 4391 dec->rs1 = operand_rs1(inst); 4392 dec->rs2 = operand_rs2(inst); 4393 dec->imm = 0; 4394 dec->aq = operand_aq(inst); 4395 dec->rl = operand_rl(inst); 4396 break; 4397 case rv_codec_r_l: 4398 dec->rd = operand_rd(inst); 4399 dec->rs1 = operand_rs1(inst); 4400 dec->rs2 = rv_ireg_zero; 4401 dec->imm = 0; 4402 dec->aq = operand_aq(inst); 4403 dec->rl = operand_rl(inst); 4404 break; 4405 case rv_codec_r_f: 4406 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4407 dec->pred = operand_pred(inst); 4408 dec->succ = operand_succ(inst); 4409 dec->imm = 0; 4410 break; 4411 case rv_codec_cb: 4412 dec->rd = rv_ireg_zero; 4413 dec->rs1 = operand_crs1q(inst) + 8; 4414 dec->rs2 = rv_ireg_zero; 4415 dec->imm = operand_cimmb(inst); 4416 break; 4417 case rv_codec_cb_imm: 4418 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4419 dec->rs2 = rv_ireg_zero; 4420 dec->imm = operand_cimmi(inst); 4421 break; 4422 case rv_codec_cb_sh5: 4423 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4424 dec->rs2 = rv_ireg_zero; 4425 dec->imm = operand_cimmsh5(inst); 4426 break; 4427 case rv_codec_cb_sh6: 4428 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4429 dec->rs2 = rv_ireg_zero; 4430 dec->imm = operand_cimmshr6(inst, isa); 4431 break; 4432 case rv_codec_ci: 4433 dec->rd = dec->rs1 = operand_crs1rd(inst); 4434 dec->rs2 = rv_ireg_zero; 4435 dec->imm = operand_cimmi(inst); 4436 break; 4437 case rv_codec_ci_sh5: 4438 dec->rd = dec->rs1 = operand_crs1rd(inst); 4439 dec->rs2 = rv_ireg_zero; 4440 dec->imm = operand_cimmsh5(inst); 4441 break; 4442 case rv_codec_ci_sh6: 4443 dec->rd = dec->rs1 = operand_crs1rd(inst); 4444 dec->rs2 = rv_ireg_zero; 4445 dec->imm = operand_cimmshl6(inst, isa); 4446 break; 4447 case rv_codec_ci_16sp: 4448 dec->rd = rv_ireg_sp; 4449 dec->rs1 = rv_ireg_sp; 4450 dec->rs2 = rv_ireg_zero; 4451 dec->imm = operand_cimm16sp(inst); 4452 break; 4453 case rv_codec_ci_lwsp: 4454 dec->rd = operand_crd(inst); 4455 dec->rs1 = rv_ireg_sp; 4456 dec->rs2 = rv_ireg_zero; 4457 dec->imm = operand_cimmlwsp(inst); 4458 break; 4459 case rv_codec_ci_ldsp: 4460 dec->rd = operand_crd(inst); 4461 dec->rs1 = rv_ireg_sp; 4462 dec->rs2 = rv_ireg_zero; 4463 dec->imm = operand_cimmldsp(inst); 4464 break; 4465 case rv_codec_ci_lqsp: 4466 dec->rd = operand_crd(inst); 4467 dec->rs1 = rv_ireg_sp; 4468 dec->rs2 = rv_ireg_zero; 4469 dec->imm = operand_cimmlqsp(inst); 4470 break; 4471 case rv_codec_ci_li: 4472 dec->rd = operand_crd(inst); 4473 dec->rs1 = rv_ireg_zero; 4474 dec->rs2 = rv_ireg_zero; 4475 dec->imm = operand_cimmi(inst); 4476 break; 4477 case rv_codec_ci_lui: 4478 dec->rd = operand_crd(inst); 4479 dec->rs1 = rv_ireg_zero; 4480 dec->rs2 = rv_ireg_zero; 4481 dec->imm = operand_cimmui(inst); 4482 break; 4483 case rv_codec_ci_none: 4484 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4485 dec->imm = 0; 4486 break; 4487 case rv_codec_ciw_4spn: 4488 dec->rd = operand_crdq(inst) + 8; 4489 dec->rs1 = rv_ireg_sp; 4490 dec->rs2 = rv_ireg_zero; 4491 dec->imm = operand_cimm4spn(inst); 4492 break; 4493 case rv_codec_cj: 4494 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4495 dec->imm = operand_cimmj(inst); 4496 break; 4497 case rv_codec_cj_jal: 4498 dec->rd = rv_ireg_ra; 4499 dec->rs1 = dec->rs2 = rv_ireg_zero; 4500 dec->imm = operand_cimmj(inst); 4501 break; 4502 case rv_codec_cl_lw: 4503 dec->rd = operand_crdq(inst) + 8; 4504 dec->rs1 = operand_crs1q(inst) + 8; 4505 dec->rs2 = rv_ireg_zero; 4506 dec->imm = operand_cimmw(inst); 4507 break; 4508 case rv_codec_cl_ld: 4509 dec->rd = operand_crdq(inst) + 8; 4510 dec->rs1 = operand_crs1q(inst) + 8; 4511 dec->rs2 = rv_ireg_zero; 4512 dec->imm = operand_cimmd(inst); 4513 break; 4514 case rv_codec_cl_lq: 4515 dec->rd = operand_crdq(inst) + 8; 4516 dec->rs1 = operand_crs1q(inst) + 8; 4517 dec->rs2 = rv_ireg_zero; 4518 dec->imm = operand_cimmq(inst); 4519 break; 4520 case rv_codec_cr: 4521 dec->rd = dec->rs1 = operand_crs1rd(inst); 4522 dec->rs2 = operand_crs2(inst); 4523 dec->imm = 0; 4524 break; 4525 case rv_codec_cr_mv: 4526 dec->rd = operand_crd(inst); 4527 dec->rs1 = operand_crs2(inst); 4528 dec->rs2 = rv_ireg_zero; 4529 dec->imm = 0; 4530 break; 4531 case rv_codec_cr_jalr: 4532 dec->rd = rv_ireg_ra; 4533 dec->rs1 = operand_crs1(inst); 4534 dec->rs2 = rv_ireg_zero; 4535 dec->imm = 0; 4536 break; 4537 case rv_codec_cr_jr: 4538 dec->rd = rv_ireg_zero; 4539 dec->rs1 = operand_crs1(inst); 4540 dec->rs2 = rv_ireg_zero; 4541 dec->imm = 0; 4542 break; 4543 case rv_codec_cs: 4544 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4545 dec->rs2 = operand_crs2q(inst) + 8; 4546 dec->imm = 0; 4547 break; 4548 case rv_codec_cs_sw: 4549 dec->rd = rv_ireg_zero; 4550 dec->rs1 = operand_crs1q(inst) + 8; 4551 dec->rs2 = operand_crs2q(inst) + 8; 4552 dec->imm = operand_cimmw(inst); 4553 break; 4554 case rv_codec_cs_sd: 4555 dec->rd = rv_ireg_zero; 4556 dec->rs1 = operand_crs1q(inst) + 8; 4557 dec->rs2 = operand_crs2q(inst) + 8; 4558 dec->imm = operand_cimmd(inst); 4559 break; 4560 case rv_codec_cs_sq: 4561 dec->rd = rv_ireg_zero; 4562 dec->rs1 = operand_crs1q(inst) + 8; 4563 dec->rs2 = operand_crs2q(inst) + 8; 4564 dec->imm = operand_cimmq(inst); 4565 break; 4566 case rv_codec_css_swsp: 4567 dec->rd = rv_ireg_zero; 4568 dec->rs1 = rv_ireg_sp; 4569 dec->rs2 = operand_crs2(inst); 4570 dec->imm = operand_cimmswsp(inst); 4571 break; 4572 case rv_codec_css_sdsp: 4573 dec->rd = rv_ireg_zero; 4574 dec->rs1 = rv_ireg_sp; 4575 dec->rs2 = operand_crs2(inst); 4576 dec->imm = operand_cimmsdsp(inst); 4577 break; 4578 case rv_codec_css_sqsp: 4579 dec->rd = rv_ireg_zero; 4580 dec->rs1 = rv_ireg_sp; 4581 dec->rs2 = operand_crs2(inst); 4582 dec->imm = operand_cimmsqsp(inst); 4583 break; 4584 case rv_codec_k_bs: 4585 dec->rs1 = operand_rs1(inst); 4586 dec->rs2 = operand_rs2(inst); 4587 dec->bs = operand_bs(inst); 4588 break; 4589 case rv_codec_k_rnum: 4590 dec->rd = operand_rd(inst); 4591 dec->rs1 = operand_rs1(inst); 4592 dec->rnum = operand_rnum(inst); 4593 break; 4594 case rv_codec_v_r: 4595 dec->rd = operand_rd(inst); 4596 dec->rs1 = operand_rs1(inst); 4597 dec->rs2 = operand_rs2(inst); 4598 dec->vm = operand_vm(inst); 4599 break; 4600 case rv_codec_v_ldst: 4601 dec->rd = operand_rd(inst); 4602 dec->rs1 = operand_rs1(inst); 4603 dec->vm = operand_vm(inst); 4604 break; 4605 case rv_codec_v_i: 4606 dec->rd = operand_rd(inst); 4607 dec->rs2 = operand_rs2(inst); 4608 dec->imm = operand_vimm(inst); 4609 dec->vm = operand_vm(inst); 4610 break; 4611 case rv_codec_vror_vi: 4612 dec->rd = operand_rd(inst); 4613 dec->rs2 = operand_rs2(inst); 4614 dec->imm = operand_vzimm6(inst); 4615 dec->vm = operand_vm(inst); 4616 break; 4617 case rv_codec_vsetvli: 4618 dec->rd = operand_rd(inst); 4619 dec->rs1 = operand_rs1(inst); 4620 dec->vzimm = operand_vzimm11(inst); 4621 break; 4622 case rv_codec_vsetivli: 4623 dec->rd = operand_rd(inst); 4624 dec->imm = operand_vimm(inst); 4625 dec->vzimm = operand_vzimm10(inst); 4626 break; 4627 case rv_codec_zcb_lb: 4628 dec->rs1 = operand_crs1q(inst) + 8; 4629 dec->rs2 = operand_crs2q(inst) + 8; 4630 dec->imm = operand_uimm_c_lb(inst); 4631 break; 4632 case rv_codec_zcb_lh: 4633 dec->rs1 = operand_crs1q(inst) + 8; 4634 dec->rs2 = operand_crs2q(inst) + 8; 4635 dec->imm = operand_uimm_c_lh(inst); 4636 break; 4637 case rv_codec_zcb_ext: 4638 dec->rd = operand_crs1q(inst) + 8; 4639 break; 4640 case rv_codec_zcb_mul: 4641 dec->rd = operand_crs1rdq(inst) + 8; 4642 dec->rs2 = operand_crs2q(inst) + 8; 4643 break; 4644 case rv_codec_zcmp_cm_pushpop: 4645 dec->imm = operand_zcmp_stack_adj(inst, isa); 4646 dec->rlist = operand_zcmp_rlist(inst); 4647 break; 4648 case rv_codec_zcmp_cm_mv: 4649 dec->rd = operand_sreg1(inst); 4650 dec->rs2 = operand_sreg2(inst); 4651 break; 4652 case rv_codec_zcmt_jt: 4653 dec->imm = operand_tbl_index(inst); 4654 break; 4655 case rv_codec_fli: 4656 dec->rd = operand_rd(inst); 4657 dec->imm = operand_rs1(inst); 4658 break; 4659 case rv_codec_r2_imm5: 4660 dec->rd = operand_rd(inst); 4661 dec->rs1 = operand_rs1(inst); 4662 dec->imm = operand_rs2(inst); 4663 break; 4664 case rv_codec_r2: 4665 dec->rd = operand_rd(inst); 4666 dec->rs1 = operand_rs1(inst); 4667 break; 4668 case rv_codec_r2_imm6: 4669 dec->rd = operand_rd(inst); 4670 dec->rs1 = operand_rs1(inst); 4671 dec->imm = operand_imm6(inst); 4672 break; 4673 case rv_codec_r_imm2: 4674 dec->rd = operand_rd(inst); 4675 dec->rs1 = operand_rs1(inst); 4676 dec->rs2 = operand_rs2(inst); 4677 dec->imm = operand_imm2(inst); 4678 break; 4679 case rv_codec_r2_immhl: 4680 dec->rd = operand_rd(inst); 4681 dec->rs1 = operand_rs1(inst); 4682 dec->imm = operand_immh(inst); 4683 dec->imm1 = operand_imml(inst); 4684 break; 4685 case rv_codec_r2_imm2_imm5: 4686 dec->rd = operand_rd(inst); 4687 dec->rs1 = operand_rs1(inst); 4688 dec->imm = sextract32(operand_rs2(inst), 0, 5); 4689 dec->imm1 = operand_imm2(inst); 4690 break; 4691 }; 4692 } 4693 4694 /* check constraint */ 4695 4696 static bool check_constraints(rv_decode *dec, const rvc_constraint *c) 4697 { 4698 int32_t imm = dec->imm; 4699 uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2; 4700 while (*c != rvc_end) { 4701 switch (*c) { 4702 case rvc_rd_eq_ra: 4703 if (!(rd == 1)) { 4704 return false; 4705 } 4706 break; 4707 case rvc_rd_eq_x0: 4708 if (!(rd == 0)) { 4709 return false; 4710 } 4711 break; 4712 case rvc_rs1_eq_x0: 4713 if (!(rs1 == 0)) { 4714 return false; 4715 } 4716 break; 4717 case rvc_rs2_eq_x0: 4718 if (!(rs2 == 0)) { 4719 return false; 4720 } 4721 break; 4722 case rvc_rs2_eq_rs1: 4723 if (!(rs2 == rs1)) { 4724 return false; 4725 } 4726 break; 4727 case rvc_rs1_eq_ra: 4728 if (!(rs1 == 1)) { 4729 return false; 4730 } 4731 break; 4732 case rvc_imm_eq_zero: 4733 if (!(imm == 0)) { 4734 return false; 4735 } 4736 break; 4737 case rvc_imm_eq_n1: 4738 if (!(imm == -1)) { 4739 return false; 4740 } 4741 break; 4742 case rvc_imm_eq_p1: 4743 if (!(imm == 1)) { 4744 return false; 4745 } 4746 break; 4747 case rvc_csr_eq_0x001: 4748 if (!(imm == 0x001)) { 4749 return false; 4750 } 4751 break; 4752 case rvc_csr_eq_0x002: 4753 if (!(imm == 0x002)) { 4754 return false; 4755 } 4756 break; 4757 case rvc_csr_eq_0x003: 4758 if (!(imm == 0x003)) { 4759 return false; 4760 } 4761 break; 4762 case rvc_csr_eq_0xc00: 4763 if (!(imm == 0xc00)) { 4764 return false; 4765 } 4766 break; 4767 case rvc_csr_eq_0xc01: 4768 if (!(imm == 0xc01)) { 4769 return false; 4770 } 4771 break; 4772 case rvc_csr_eq_0xc02: 4773 if (!(imm == 0xc02)) { 4774 return false; 4775 } 4776 break; 4777 case rvc_csr_eq_0xc80: 4778 if (!(imm == 0xc80)) { 4779 return false; 4780 } 4781 break; 4782 case rvc_csr_eq_0xc81: 4783 if (!(imm == 0xc81)) { 4784 return false; 4785 } 4786 break; 4787 case rvc_csr_eq_0xc82: 4788 if (!(imm == 0xc82)) { 4789 return false; 4790 } 4791 break; 4792 default: break; 4793 } 4794 c++; 4795 } 4796 return true; 4797 } 4798 4799 /* instruction length */ 4800 4801 static size_t inst_length(rv_inst inst) 4802 { 4803 /* NOTE: supports maximum instruction size of 64-bits */ 4804 4805 /* 4806 * instruction length coding 4807 * 4808 * aa - 16 bit aa != 11 4809 * bbb11 - 32 bit bbb != 111 4810 * 011111 - 48 bit 4811 * 0111111 - 64 bit 4812 */ 4813 4814 return (inst & 0b11) != 0b11 ? 2 4815 : (inst & 0b11100) != 0b11100 ? 4 4816 : (inst & 0b111111) == 0b011111 ? 6 4817 : (inst & 0b1111111) == 0b0111111 ? 8 4818 : 0; 4819 } 4820 4821 /* format instruction */ 4822 4823 static GString *format_inst(size_t tab, rv_decode *dec) 4824 { 4825 const rv_opcode_data *opcode_data = dec->opcode_data; 4826 GString *buf = g_string_sized_new(64); 4827 const char *fmt; 4828 4829 fmt = opcode_data[dec->op].format; 4830 while (*fmt) { 4831 switch (*fmt) { 4832 case 'O': 4833 g_string_append(buf, opcode_data[dec->op].name); 4834 break; 4835 case '(': 4836 case ',': 4837 case ')': 4838 case '-': 4839 g_string_append_c(buf, *fmt); 4840 break; 4841 case 'b': 4842 g_string_append_printf(buf, "%d", dec->bs); 4843 break; 4844 case 'n': 4845 g_string_append_printf(buf, "%d", dec->rnum); 4846 break; 4847 case '0': 4848 g_string_append(buf, rv_ireg_name_sym[dec->rd]); 4849 break; 4850 case '1': 4851 g_string_append(buf, rv_ireg_name_sym[dec->rs1]); 4852 break; 4853 case '2': 4854 g_string_append(buf, rv_ireg_name_sym[dec->rs2]); 4855 break; 4856 case '3': 4857 if (dec->cfg->ext_zfinx) { 4858 g_string_append(buf, rv_ireg_name_sym[dec->rd]); 4859 } else { 4860 g_string_append(buf, rv_freg_name_sym[dec->rd]); 4861 } 4862 break; 4863 case '4': 4864 if (dec->cfg->ext_zfinx) { 4865 g_string_append(buf, rv_ireg_name_sym[dec->rs1]); 4866 } else { 4867 g_string_append(buf, rv_freg_name_sym[dec->rs1]); 4868 } 4869 break; 4870 case '5': 4871 if (dec->cfg->ext_zfinx) { 4872 g_string_append(buf, rv_ireg_name_sym[dec->rs2]); 4873 } else { 4874 g_string_append(buf, rv_freg_name_sym[dec->rs2]); 4875 } 4876 break; 4877 case '6': 4878 if (dec->cfg->ext_zfinx) { 4879 g_string_append(buf, rv_ireg_name_sym[dec->rs3]); 4880 } else { 4881 g_string_append(buf, rv_freg_name_sym[dec->rs3]); 4882 } 4883 break; 4884 case '7': 4885 g_string_append_printf(buf, "%d", dec->rs1); 4886 break; 4887 case 'i': 4888 g_string_append_printf(buf, "%d", dec->imm); 4889 break; 4890 case 'u': 4891 g_string_append_printf(buf, "%u", ((uint32_t)dec->imm & 0b111111)); 4892 break; 4893 case 'j': 4894 g_string_append_printf(buf, "%d", dec->imm1); 4895 break; 4896 case 'o': 4897 g_string_append_printf(buf, "%d", dec->imm); 4898 while (buf->len < tab * 2) { 4899 g_string_append_c(buf, ' '); 4900 } 4901 g_string_append_printf(buf, "# 0x%" PRIx64, dec->pc + dec->imm); 4902 break; 4903 case 'U': 4904 fmt++; 4905 g_string_append_printf(buf, "%d", dec->imm >> 12); 4906 if (*fmt == 'o') { 4907 while (buf->len < tab * 2) { 4908 g_string_append_c(buf, ' '); 4909 } 4910 g_string_append_printf(buf, "# 0x%" PRIx64, dec->pc + dec->imm); 4911 } 4912 break; 4913 case 'c': { 4914 const char *name = csr_name(dec->imm & 0xfff); 4915 if (name) { 4916 g_string_append(buf, name); 4917 } else { 4918 g_string_append_printf(buf, "0x%03x", dec->imm & 0xfff); 4919 } 4920 break; 4921 } 4922 case 'r': 4923 switch (dec->rm) { 4924 case rv_rm_rne: 4925 g_string_append(buf, "rne"); 4926 break; 4927 case rv_rm_rtz: 4928 g_string_append(buf, "rtz"); 4929 break; 4930 case rv_rm_rdn: 4931 g_string_append(buf, "rdn"); 4932 break; 4933 case rv_rm_rup: 4934 g_string_append(buf, "rup"); 4935 break; 4936 case rv_rm_rmm: 4937 g_string_append(buf, "rmm"); 4938 break; 4939 case rv_rm_dyn: 4940 g_string_append(buf, "dyn"); 4941 break; 4942 default: 4943 g_string_append(buf, "inv"); 4944 break; 4945 } 4946 break; 4947 case 'p': 4948 if (dec->pred & rv_fence_i) { 4949 g_string_append_c(buf, 'i'); 4950 } 4951 if (dec->pred & rv_fence_o) { 4952 g_string_append_c(buf, 'o'); 4953 } 4954 if (dec->pred & rv_fence_r) { 4955 g_string_append_c(buf, 'r'); 4956 } 4957 if (dec->pred & rv_fence_w) { 4958 g_string_append_c(buf, 'w'); 4959 } 4960 break; 4961 case 's': 4962 if (dec->succ & rv_fence_i) { 4963 g_string_append_c(buf, 'i'); 4964 } 4965 if (dec->succ & rv_fence_o) { 4966 g_string_append_c(buf, 'o'); 4967 } 4968 if (dec->succ & rv_fence_r) { 4969 g_string_append_c(buf, 'r'); 4970 } 4971 if (dec->succ & rv_fence_w) { 4972 g_string_append_c(buf, 'w'); 4973 } 4974 break; 4975 case '\t': 4976 while (buf->len < tab) { 4977 g_string_append_c(buf, ' '); 4978 } 4979 break; 4980 case 'A': 4981 if (dec->aq) { 4982 g_string_append(buf, ".aq"); 4983 } 4984 break; 4985 case 'R': 4986 if (dec->rl) { 4987 g_string_append(buf, ".rl"); 4988 } 4989 break; 4990 case 'l': 4991 g_string_append(buf, ",v0"); 4992 break; 4993 case 'm': 4994 if (dec->vm == 0) { 4995 g_string_append(buf, ",v0.t"); 4996 } 4997 break; 4998 case 'D': 4999 g_string_append(buf, rv_vreg_name_sym[dec->rd]); 5000 break; 5001 case 'E': 5002 g_string_append(buf, rv_vreg_name_sym[dec->rs1]); 5003 break; 5004 case 'F': 5005 g_string_append(buf, rv_vreg_name_sym[dec->rs2]); 5006 break; 5007 case 'G': 5008 g_string_append(buf, rv_vreg_name_sym[dec->rs3]); 5009 break; 5010 case 'v': { 5011 const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3); 5012 const int lmul = dec->vzimm & 0b11; 5013 const int flmul = (dec->vzimm >> 2) & 1; 5014 const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu"; 5015 const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu"; 5016 5017 g_string_append_printf(buf, "e%d,m", sew); 5018 if (flmul) { 5019 switch (lmul) { 5020 case 3: 5021 g_string_append(buf, "f2"); 5022 break; 5023 case 2: 5024 g_string_append(buf, "f4"); 5025 break; 5026 case 1: 5027 g_string_append(buf, "f8"); 5028 break; 5029 } 5030 } else { 5031 g_string_append_printf(buf, "%d", 1 << lmul); 5032 } 5033 g_string_append_c(buf, ','); 5034 g_string_append(buf, vta); 5035 g_string_append_c(buf, ','); 5036 g_string_append(buf, vma); 5037 break; 5038 } 5039 case 'x': { 5040 switch (dec->rlist) { 5041 case 4: 5042 g_string_append(buf, "{ra}"); 5043 break; 5044 case 5: 5045 g_string_append(buf, "{ra, s0}"); 5046 break; 5047 case 15: 5048 g_string_append(buf, "{ra, s0-s11}"); 5049 break; 5050 default: 5051 g_string_append_printf(buf, "{ra, s0-s%d}", dec->rlist - 5); 5052 break; 5053 } 5054 break; 5055 } 5056 case 'h': 5057 g_string_append(buf, rv_fli_name_const[dec->imm]); 5058 break; 5059 default: 5060 break; 5061 } 5062 fmt++; 5063 } 5064 5065 return buf; 5066 } 5067 5068 /* lift instruction to pseudo-instruction */ 5069 5070 static void decode_inst_lift_pseudo(rv_decode *dec) 5071 { 5072 const rv_opcode_data *opcode_data = dec->opcode_data; 5073 const rv_comp_data *comp_data = opcode_data[dec->op].pseudo; 5074 if (!comp_data) { 5075 return; 5076 } 5077 while (comp_data->constraints) { 5078 if (check_constraints(dec, comp_data->constraints)) { 5079 dec->op = comp_data->op; 5080 dec->codec = opcode_data[dec->op].codec; 5081 return; 5082 } 5083 comp_data++; 5084 } 5085 } 5086 5087 /* decompress instruction */ 5088 5089 static void decode_inst_decompress_rv32(rv_decode *dec) 5090 { 5091 const rv_opcode_data *opcode_data = dec->opcode_data; 5092 int decomp_op = opcode_data[dec->op].decomp_rv32; 5093 if (decomp_op != rv_op_illegal) { 5094 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5095 && dec->imm == 0) { 5096 dec->op = rv_op_illegal; 5097 } else { 5098 dec->op = decomp_op; 5099 dec->codec = opcode_data[decomp_op].codec; 5100 } 5101 } 5102 } 5103 5104 static void decode_inst_decompress_rv64(rv_decode *dec) 5105 { 5106 const rv_opcode_data *opcode_data = dec->opcode_data; 5107 int decomp_op = opcode_data[dec->op].decomp_rv64; 5108 if (decomp_op != rv_op_illegal) { 5109 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5110 && dec->imm == 0) { 5111 dec->op = rv_op_illegal; 5112 } else { 5113 dec->op = decomp_op; 5114 dec->codec = opcode_data[decomp_op].codec; 5115 } 5116 } 5117 } 5118 5119 static void decode_inst_decompress_rv128(rv_decode *dec) 5120 { 5121 const rv_opcode_data *opcode_data = dec->opcode_data; 5122 int decomp_op = opcode_data[dec->op].decomp_rv128; 5123 if (decomp_op != rv_op_illegal) { 5124 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5125 && dec->imm == 0) { 5126 dec->op = rv_op_illegal; 5127 } else { 5128 dec->op = decomp_op; 5129 dec->codec = opcode_data[decomp_op].codec; 5130 } 5131 } 5132 } 5133 5134 static void decode_inst_decompress(rv_decode *dec, rv_isa isa) 5135 { 5136 switch (isa) { 5137 case rv32: 5138 decode_inst_decompress_rv32(dec); 5139 break; 5140 case rv64: 5141 decode_inst_decompress_rv64(dec); 5142 break; 5143 case rv128: 5144 decode_inst_decompress_rv128(dec); 5145 break; 5146 } 5147 } 5148 5149 /* disassemble instruction */ 5150 5151 static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst, 5152 RISCVCPUConfig *cfg) 5153 { 5154 rv_decode dec = { 0 }; 5155 dec.pc = pc; 5156 dec.inst = inst; 5157 dec.cfg = cfg; 5158 5159 static const struct { 5160 bool (*guard_func)(const RISCVCPUConfig *); 5161 const rv_opcode_data *opcode_data; 5162 void (*decode_func)(rv_decode *, rv_isa); 5163 } decoders[] = { 5164 { always_true_p, rvi_opcode_data, decode_inst_opcode }, 5165 { has_xtheadba_p, xthead_opcode_data, decode_xtheadba }, 5166 { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb }, 5167 { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs }, 5168 { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo }, 5169 { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov }, 5170 { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx }, 5171 { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv }, 5172 { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac }, 5173 { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx }, 5174 { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair }, 5175 { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync }, 5176 { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops }, 5177 }; 5178 5179 for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { 5180 bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func; 5181 const rv_opcode_data *opcode_data = decoders[i].opcode_data; 5182 void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func; 5183 5184 if (guard_func(cfg)) { 5185 dec.opcode_data = opcode_data; 5186 decode_func(&dec, isa); 5187 if (dec.op != rv_op_illegal) 5188 break; 5189 } 5190 } 5191 5192 if (dec.op == rv_op_illegal) { 5193 dec.opcode_data = rvi_opcode_data; 5194 } 5195 5196 decode_inst_operands(&dec, isa); 5197 decode_inst_decompress(&dec, isa); 5198 decode_inst_lift_pseudo(&dec); 5199 return format_inst(24, &dec); 5200 } 5201 5202 #define INST_FMT_2 "%04" PRIx64 " " 5203 #define INST_FMT_4 "%08" PRIx64 " " 5204 #define INST_FMT_6 "%012" PRIx64 " " 5205 #define INST_FMT_8 "%016" PRIx64 " " 5206 5207 static int 5208 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) 5209 { 5210 bfd_byte packet[2]; 5211 rv_inst inst = 0; 5212 size_t len = 2; 5213 bfd_vma n; 5214 int status; 5215 5216 /* Instructions are made of 2-byte packets in little-endian order */ 5217 for (n = 0; n < len; n += 2) { 5218 status = (*info->read_memory_func)(memaddr + n, packet, 2, info); 5219 if (status != 0) { 5220 /* Don't fail just because we fell off the end. */ 5221 if (n > 0) { 5222 break; 5223 } 5224 (*info->memory_error_func)(status, memaddr, info); 5225 return status; 5226 } 5227 inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n); 5228 if (n == 0) { 5229 len = inst_length(inst); 5230 } 5231 } 5232 5233 if (info->show_opcodes) { 5234 switch (len) { 5235 case 2: 5236 (*info->fprintf_func)(info->stream, INST_FMT_2, inst); 5237 break; 5238 case 4: 5239 (*info->fprintf_func)(info->stream, INST_FMT_4, inst); 5240 break; 5241 case 6: 5242 (*info->fprintf_func)(info->stream, INST_FMT_6, inst); 5243 break; 5244 default: 5245 (*info->fprintf_func)(info->stream, INST_FMT_8, inst); 5246 break; 5247 } 5248 } 5249 5250 g_autoptr(GString) str = 5251 disasm_inst(isa, memaddr, inst, (RISCVCPUConfig *)info->target_info); 5252 (*info->fprintf_func)(info->stream, "%s", str->str); 5253 5254 return len; 5255 } 5256 5257 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info) 5258 { 5259 return print_insn_riscv(memaddr, info, rv32); 5260 } 5261 5262 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info) 5263 { 5264 return print_insn_riscv(memaddr, info, rv64); 5265 } 5266 5267 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info) 5268 { 5269 return print_insn_riscv(memaddr, info, rv128); 5270 } 5271