1 /* 2 * QEMU RISC-V Disassembler 3 * 4 * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com> 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/bitops.h" 22 #include "disas/dis-asm.h" 23 #include "target/riscv/cpu_cfg.h" 24 #include "disas/riscv.h" 25 26 /* Vendor extensions */ 27 #include "disas/riscv-xthead.h" 28 #include "disas/riscv-xventana.h" 29 30 typedef enum { 31 /* 0 is reserved for rv_op_illegal. */ 32 rv_op_lui = 1, 33 rv_op_auipc = 2, 34 rv_op_jal = 3, 35 rv_op_jalr = 4, 36 rv_op_beq = 5, 37 rv_op_bne = 6, 38 rv_op_blt = 7, 39 rv_op_bge = 8, 40 rv_op_bltu = 9, 41 rv_op_bgeu = 10, 42 rv_op_lb = 11, 43 rv_op_lh = 12, 44 rv_op_lw = 13, 45 rv_op_lbu = 14, 46 rv_op_lhu = 15, 47 rv_op_sb = 16, 48 rv_op_sh = 17, 49 rv_op_sw = 18, 50 rv_op_addi = 19, 51 rv_op_slti = 20, 52 rv_op_sltiu = 21, 53 rv_op_xori = 22, 54 rv_op_ori = 23, 55 rv_op_andi = 24, 56 rv_op_slli = 25, 57 rv_op_srli = 26, 58 rv_op_srai = 27, 59 rv_op_add = 28, 60 rv_op_sub = 29, 61 rv_op_sll = 30, 62 rv_op_slt = 31, 63 rv_op_sltu = 32, 64 rv_op_xor = 33, 65 rv_op_srl = 34, 66 rv_op_sra = 35, 67 rv_op_or = 36, 68 rv_op_and = 37, 69 rv_op_fence = 38, 70 rv_op_fence_i = 39, 71 rv_op_lwu = 40, 72 rv_op_ld = 41, 73 rv_op_sd = 42, 74 rv_op_addiw = 43, 75 rv_op_slliw = 44, 76 rv_op_srliw = 45, 77 rv_op_sraiw = 46, 78 rv_op_addw = 47, 79 rv_op_subw = 48, 80 rv_op_sllw = 49, 81 rv_op_srlw = 50, 82 rv_op_sraw = 51, 83 rv_op_ldu = 52, 84 rv_op_lq = 53, 85 rv_op_sq = 54, 86 rv_op_addid = 55, 87 rv_op_sllid = 56, 88 rv_op_srlid = 57, 89 rv_op_sraid = 58, 90 rv_op_addd = 59, 91 rv_op_subd = 60, 92 rv_op_slld = 61, 93 rv_op_srld = 62, 94 rv_op_srad = 63, 95 rv_op_mul = 64, 96 rv_op_mulh = 65, 97 rv_op_mulhsu = 66, 98 rv_op_mulhu = 67, 99 rv_op_div = 68, 100 rv_op_divu = 69, 101 rv_op_rem = 70, 102 rv_op_remu = 71, 103 rv_op_mulw = 72, 104 rv_op_divw = 73, 105 rv_op_divuw = 74, 106 rv_op_remw = 75, 107 rv_op_remuw = 76, 108 rv_op_muld = 77, 109 rv_op_divd = 78, 110 rv_op_divud = 79, 111 rv_op_remd = 80, 112 rv_op_remud = 81, 113 rv_op_lr_w = 82, 114 rv_op_sc_w = 83, 115 rv_op_amoswap_w = 84, 116 rv_op_amoadd_w = 85, 117 rv_op_amoxor_w = 86, 118 rv_op_amoor_w = 87, 119 rv_op_amoand_w = 88, 120 rv_op_amomin_w = 89, 121 rv_op_amomax_w = 90, 122 rv_op_amominu_w = 91, 123 rv_op_amomaxu_w = 92, 124 rv_op_lr_d = 93, 125 rv_op_sc_d = 94, 126 rv_op_amoswap_d = 95, 127 rv_op_amoadd_d = 96, 128 rv_op_amoxor_d = 97, 129 rv_op_amoor_d = 98, 130 rv_op_amoand_d = 99, 131 rv_op_amomin_d = 100, 132 rv_op_amomax_d = 101, 133 rv_op_amominu_d = 102, 134 rv_op_amomaxu_d = 103, 135 rv_op_lr_q = 104, 136 rv_op_sc_q = 105, 137 rv_op_amoswap_q = 106, 138 rv_op_amoadd_q = 107, 139 rv_op_amoxor_q = 108, 140 rv_op_amoor_q = 109, 141 rv_op_amoand_q = 110, 142 rv_op_amomin_q = 111, 143 rv_op_amomax_q = 112, 144 rv_op_amominu_q = 113, 145 rv_op_amomaxu_q = 114, 146 rv_op_ecall = 115, 147 rv_op_ebreak = 116, 148 rv_op_uret = 117, 149 rv_op_sret = 118, 150 rv_op_hret = 119, 151 rv_op_mret = 120, 152 rv_op_dret = 121, 153 rv_op_sfence_vm = 122, 154 rv_op_sfence_vma = 123, 155 rv_op_wfi = 124, 156 rv_op_csrrw = 125, 157 rv_op_csrrs = 126, 158 rv_op_csrrc = 127, 159 rv_op_csrrwi = 128, 160 rv_op_csrrsi = 129, 161 rv_op_csrrci = 130, 162 rv_op_flw = 131, 163 rv_op_fsw = 132, 164 rv_op_fmadd_s = 133, 165 rv_op_fmsub_s = 134, 166 rv_op_fnmsub_s = 135, 167 rv_op_fnmadd_s = 136, 168 rv_op_fadd_s = 137, 169 rv_op_fsub_s = 138, 170 rv_op_fmul_s = 139, 171 rv_op_fdiv_s = 140, 172 rv_op_fsgnj_s = 141, 173 rv_op_fsgnjn_s = 142, 174 rv_op_fsgnjx_s = 143, 175 rv_op_fmin_s = 144, 176 rv_op_fmax_s = 145, 177 rv_op_fsqrt_s = 146, 178 rv_op_fle_s = 147, 179 rv_op_flt_s = 148, 180 rv_op_feq_s = 149, 181 rv_op_fcvt_w_s = 150, 182 rv_op_fcvt_wu_s = 151, 183 rv_op_fcvt_s_w = 152, 184 rv_op_fcvt_s_wu = 153, 185 rv_op_fmv_x_s = 154, 186 rv_op_fclass_s = 155, 187 rv_op_fmv_s_x = 156, 188 rv_op_fcvt_l_s = 157, 189 rv_op_fcvt_lu_s = 158, 190 rv_op_fcvt_s_l = 159, 191 rv_op_fcvt_s_lu = 160, 192 rv_op_fld = 161, 193 rv_op_fsd = 162, 194 rv_op_fmadd_d = 163, 195 rv_op_fmsub_d = 164, 196 rv_op_fnmsub_d = 165, 197 rv_op_fnmadd_d = 166, 198 rv_op_fadd_d = 167, 199 rv_op_fsub_d = 168, 200 rv_op_fmul_d = 169, 201 rv_op_fdiv_d = 170, 202 rv_op_fsgnj_d = 171, 203 rv_op_fsgnjn_d = 172, 204 rv_op_fsgnjx_d = 173, 205 rv_op_fmin_d = 174, 206 rv_op_fmax_d = 175, 207 rv_op_fcvt_s_d = 176, 208 rv_op_fcvt_d_s = 177, 209 rv_op_fsqrt_d = 178, 210 rv_op_fle_d = 179, 211 rv_op_flt_d = 180, 212 rv_op_feq_d = 181, 213 rv_op_fcvt_w_d = 182, 214 rv_op_fcvt_wu_d = 183, 215 rv_op_fcvt_d_w = 184, 216 rv_op_fcvt_d_wu = 185, 217 rv_op_fclass_d = 186, 218 rv_op_fcvt_l_d = 187, 219 rv_op_fcvt_lu_d = 188, 220 rv_op_fmv_x_d = 189, 221 rv_op_fcvt_d_l = 190, 222 rv_op_fcvt_d_lu = 191, 223 rv_op_fmv_d_x = 192, 224 rv_op_flq = 193, 225 rv_op_fsq = 194, 226 rv_op_fmadd_q = 195, 227 rv_op_fmsub_q = 196, 228 rv_op_fnmsub_q = 197, 229 rv_op_fnmadd_q = 198, 230 rv_op_fadd_q = 199, 231 rv_op_fsub_q = 200, 232 rv_op_fmul_q = 201, 233 rv_op_fdiv_q = 202, 234 rv_op_fsgnj_q = 203, 235 rv_op_fsgnjn_q = 204, 236 rv_op_fsgnjx_q = 205, 237 rv_op_fmin_q = 206, 238 rv_op_fmax_q = 207, 239 rv_op_fcvt_s_q = 208, 240 rv_op_fcvt_q_s = 209, 241 rv_op_fcvt_d_q = 210, 242 rv_op_fcvt_q_d = 211, 243 rv_op_fsqrt_q = 212, 244 rv_op_fle_q = 213, 245 rv_op_flt_q = 214, 246 rv_op_feq_q = 215, 247 rv_op_fcvt_w_q = 216, 248 rv_op_fcvt_wu_q = 217, 249 rv_op_fcvt_q_w = 218, 250 rv_op_fcvt_q_wu = 219, 251 rv_op_fclass_q = 220, 252 rv_op_fcvt_l_q = 221, 253 rv_op_fcvt_lu_q = 222, 254 rv_op_fcvt_q_l = 223, 255 rv_op_fcvt_q_lu = 224, 256 rv_op_fmv_x_q = 225, 257 rv_op_fmv_q_x = 226, 258 rv_op_c_addi4spn = 227, 259 rv_op_c_fld = 228, 260 rv_op_c_lw = 229, 261 rv_op_c_flw = 230, 262 rv_op_c_fsd = 231, 263 rv_op_c_sw = 232, 264 rv_op_c_fsw = 233, 265 rv_op_c_nop = 234, 266 rv_op_c_addi = 235, 267 rv_op_c_jal = 236, 268 rv_op_c_li = 237, 269 rv_op_c_addi16sp = 238, 270 rv_op_c_lui = 239, 271 rv_op_c_srli = 240, 272 rv_op_c_srai = 241, 273 rv_op_c_andi = 242, 274 rv_op_c_sub = 243, 275 rv_op_c_xor = 244, 276 rv_op_c_or = 245, 277 rv_op_c_and = 246, 278 rv_op_c_subw = 247, 279 rv_op_c_addw = 248, 280 rv_op_c_j = 249, 281 rv_op_c_beqz = 250, 282 rv_op_c_bnez = 251, 283 rv_op_c_slli = 252, 284 rv_op_c_fldsp = 253, 285 rv_op_c_lwsp = 254, 286 rv_op_c_flwsp = 255, 287 rv_op_c_jr = 256, 288 rv_op_c_mv = 257, 289 rv_op_c_ebreak = 258, 290 rv_op_c_jalr = 259, 291 rv_op_c_add = 260, 292 rv_op_c_fsdsp = 261, 293 rv_op_c_swsp = 262, 294 rv_op_c_fswsp = 263, 295 rv_op_c_ld = 264, 296 rv_op_c_sd = 265, 297 rv_op_c_addiw = 266, 298 rv_op_c_ldsp = 267, 299 rv_op_c_sdsp = 268, 300 rv_op_c_lq = 269, 301 rv_op_c_sq = 270, 302 rv_op_c_lqsp = 271, 303 rv_op_c_sqsp = 272, 304 rv_op_nop = 273, 305 rv_op_mv = 274, 306 rv_op_not = 275, 307 rv_op_neg = 276, 308 rv_op_negw = 277, 309 rv_op_sext_w = 278, 310 rv_op_seqz = 279, 311 rv_op_snez = 280, 312 rv_op_sltz = 281, 313 rv_op_sgtz = 282, 314 rv_op_fmv_s = 283, 315 rv_op_fabs_s = 284, 316 rv_op_fneg_s = 285, 317 rv_op_fmv_d = 286, 318 rv_op_fabs_d = 287, 319 rv_op_fneg_d = 288, 320 rv_op_fmv_q = 289, 321 rv_op_fabs_q = 290, 322 rv_op_fneg_q = 291, 323 rv_op_beqz = 292, 324 rv_op_bnez = 293, 325 rv_op_blez = 294, 326 rv_op_bgez = 295, 327 rv_op_bltz = 296, 328 rv_op_bgtz = 297, 329 rv_op_ble = 298, 330 rv_op_bleu = 299, 331 rv_op_bgt = 300, 332 rv_op_bgtu = 301, 333 rv_op_j = 302, 334 rv_op_ret = 303, 335 rv_op_jr = 304, 336 rv_op_rdcycle = 305, 337 rv_op_rdtime = 306, 338 rv_op_rdinstret = 307, 339 rv_op_rdcycleh = 308, 340 rv_op_rdtimeh = 309, 341 rv_op_rdinstreth = 310, 342 rv_op_frcsr = 311, 343 rv_op_frrm = 312, 344 rv_op_frflags = 313, 345 rv_op_fscsr = 314, 346 rv_op_fsrm = 315, 347 rv_op_fsflags = 316, 348 rv_op_fsrmi = 317, 349 rv_op_fsflagsi = 318, 350 rv_op_bseti = 319, 351 rv_op_bclri = 320, 352 rv_op_binvi = 321, 353 rv_op_bexti = 322, 354 rv_op_rori = 323, 355 rv_op_clz = 324, 356 rv_op_ctz = 325, 357 rv_op_cpop = 326, 358 rv_op_sext_h = 327, 359 rv_op_sext_b = 328, 360 rv_op_xnor = 329, 361 rv_op_orn = 330, 362 rv_op_andn = 331, 363 rv_op_rol = 332, 364 rv_op_ror = 333, 365 rv_op_sh1add = 334, 366 rv_op_sh2add = 335, 367 rv_op_sh3add = 336, 368 rv_op_sh1add_uw = 337, 369 rv_op_sh2add_uw = 338, 370 rv_op_sh3add_uw = 339, 371 rv_op_clmul = 340, 372 rv_op_clmulr = 341, 373 rv_op_clmulh = 342, 374 rv_op_min = 343, 375 rv_op_minu = 344, 376 rv_op_max = 345, 377 rv_op_maxu = 346, 378 rv_op_clzw = 347, 379 rv_op_ctzw = 348, 380 rv_op_cpopw = 349, 381 rv_op_slli_uw = 350, 382 rv_op_add_uw = 351, 383 rv_op_rolw = 352, 384 rv_op_rorw = 353, 385 rv_op_rev8 = 354, 386 rv_op_zext_h = 355, 387 rv_op_roriw = 356, 388 rv_op_orc_b = 357, 389 rv_op_bset = 358, 390 rv_op_bclr = 359, 391 rv_op_binv = 360, 392 rv_op_bext = 361, 393 rv_op_aes32esmi = 362, 394 rv_op_aes32esi = 363, 395 rv_op_aes32dsmi = 364, 396 rv_op_aes32dsi = 365, 397 rv_op_aes64ks1i = 366, 398 rv_op_aes64ks2 = 367, 399 rv_op_aes64im = 368, 400 rv_op_aes64esm = 369, 401 rv_op_aes64es = 370, 402 rv_op_aes64dsm = 371, 403 rv_op_aes64ds = 372, 404 rv_op_sha256sig0 = 373, 405 rv_op_sha256sig1 = 374, 406 rv_op_sha256sum0 = 375, 407 rv_op_sha256sum1 = 376, 408 rv_op_sha512sig0 = 377, 409 rv_op_sha512sig1 = 378, 410 rv_op_sha512sum0 = 379, 411 rv_op_sha512sum1 = 380, 412 rv_op_sha512sum0r = 381, 413 rv_op_sha512sum1r = 382, 414 rv_op_sha512sig0l = 383, 415 rv_op_sha512sig0h = 384, 416 rv_op_sha512sig1l = 385, 417 rv_op_sha512sig1h = 386, 418 rv_op_sm3p0 = 387, 419 rv_op_sm3p1 = 388, 420 rv_op_sm4ed = 389, 421 rv_op_sm4ks = 390, 422 rv_op_brev8 = 391, 423 rv_op_pack = 392, 424 rv_op_packh = 393, 425 rv_op_packw = 394, 426 rv_op_unzip = 395, 427 rv_op_zip = 396, 428 rv_op_xperm4 = 397, 429 rv_op_xperm8 = 398, 430 rv_op_vle8_v = 399, 431 rv_op_vle16_v = 400, 432 rv_op_vle32_v = 401, 433 rv_op_vle64_v = 402, 434 rv_op_vse8_v = 403, 435 rv_op_vse16_v = 404, 436 rv_op_vse32_v = 405, 437 rv_op_vse64_v = 406, 438 rv_op_vlm_v = 407, 439 rv_op_vsm_v = 408, 440 rv_op_vlse8_v = 409, 441 rv_op_vlse16_v = 410, 442 rv_op_vlse32_v = 411, 443 rv_op_vlse64_v = 412, 444 rv_op_vsse8_v = 413, 445 rv_op_vsse16_v = 414, 446 rv_op_vsse32_v = 415, 447 rv_op_vsse64_v = 416, 448 rv_op_vluxei8_v = 417, 449 rv_op_vluxei16_v = 418, 450 rv_op_vluxei32_v = 419, 451 rv_op_vluxei64_v = 420, 452 rv_op_vloxei8_v = 421, 453 rv_op_vloxei16_v = 422, 454 rv_op_vloxei32_v = 423, 455 rv_op_vloxei64_v = 424, 456 rv_op_vsuxei8_v = 425, 457 rv_op_vsuxei16_v = 426, 458 rv_op_vsuxei32_v = 427, 459 rv_op_vsuxei64_v = 428, 460 rv_op_vsoxei8_v = 429, 461 rv_op_vsoxei16_v = 430, 462 rv_op_vsoxei32_v = 431, 463 rv_op_vsoxei64_v = 432, 464 rv_op_vle8ff_v = 433, 465 rv_op_vle16ff_v = 434, 466 rv_op_vle32ff_v = 435, 467 rv_op_vle64ff_v = 436, 468 rv_op_vl1re8_v = 437, 469 rv_op_vl1re16_v = 438, 470 rv_op_vl1re32_v = 439, 471 rv_op_vl1re64_v = 440, 472 rv_op_vl2re8_v = 441, 473 rv_op_vl2re16_v = 442, 474 rv_op_vl2re32_v = 443, 475 rv_op_vl2re64_v = 444, 476 rv_op_vl4re8_v = 445, 477 rv_op_vl4re16_v = 446, 478 rv_op_vl4re32_v = 447, 479 rv_op_vl4re64_v = 448, 480 rv_op_vl8re8_v = 449, 481 rv_op_vl8re16_v = 450, 482 rv_op_vl8re32_v = 451, 483 rv_op_vl8re64_v = 452, 484 rv_op_vs1r_v = 453, 485 rv_op_vs2r_v = 454, 486 rv_op_vs4r_v = 455, 487 rv_op_vs8r_v = 456, 488 rv_op_vadd_vv = 457, 489 rv_op_vadd_vx = 458, 490 rv_op_vadd_vi = 459, 491 rv_op_vsub_vv = 460, 492 rv_op_vsub_vx = 461, 493 rv_op_vrsub_vx = 462, 494 rv_op_vrsub_vi = 463, 495 rv_op_vwaddu_vv = 464, 496 rv_op_vwaddu_vx = 465, 497 rv_op_vwadd_vv = 466, 498 rv_op_vwadd_vx = 467, 499 rv_op_vwsubu_vv = 468, 500 rv_op_vwsubu_vx = 469, 501 rv_op_vwsub_vv = 470, 502 rv_op_vwsub_vx = 471, 503 rv_op_vwaddu_wv = 472, 504 rv_op_vwaddu_wx = 473, 505 rv_op_vwadd_wv = 474, 506 rv_op_vwadd_wx = 475, 507 rv_op_vwsubu_wv = 476, 508 rv_op_vwsubu_wx = 477, 509 rv_op_vwsub_wv = 478, 510 rv_op_vwsub_wx = 479, 511 rv_op_vadc_vvm = 480, 512 rv_op_vadc_vxm = 481, 513 rv_op_vadc_vim = 482, 514 rv_op_vmadc_vvm = 483, 515 rv_op_vmadc_vxm = 484, 516 rv_op_vmadc_vim = 485, 517 rv_op_vsbc_vvm = 486, 518 rv_op_vsbc_vxm = 487, 519 rv_op_vmsbc_vvm = 488, 520 rv_op_vmsbc_vxm = 489, 521 rv_op_vand_vv = 490, 522 rv_op_vand_vx = 491, 523 rv_op_vand_vi = 492, 524 rv_op_vor_vv = 493, 525 rv_op_vor_vx = 494, 526 rv_op_vor_vi = 495, 527 rv_op_vxor_vv = 496, 528 rv_op_vxor_vx = 497, 529 rv_op_vxor_vi = 498, 530 rv_op_vsll_vv = 499, 531 rv_op_vsll_vx = 500, 532 rv_op_vsll_vi = 501, 533 rv_op_vsrl_vv = 502, 534 rv_op_vsrl_vx = 503, 535 rv_op_vsrl_vi = 504, 536 rv_op_vsra_vv = 505, 537 rv_op_vsra_vx = 506, 538 rv_op_vsra_vi = 507, 539 rv_op_vnsrl_wv = 508, 540 rv_op_vnsrl_wx = 509, 541 rv_op_vnsrl_wi = 510, 542 rv_op_vnsra_wv = 511, 543 rv_op_vnsra_wx = 512, 544 rv_op_vnsra_wi = 513, 545 rv_op_vmseq_vv = 514, 546 rv_op_vmseq_vx = 515, 547 rv_op_vmseq_vi = 516, 548 rv_op_vmsne_vv = 517, 549 rv_op_vmsne_vx = 518, 550 rv_op_vmsne_vi = 519, 551 rv_op_vmsltu_vv = 520, 552 rv_op_vmsltu_vx = 521, 553 rv_op_vmslt_vv = 522, 554 rv_op_vmslt_vx = 523, 555 rv_op_vmsleu_vv = 524, 556 rv_op_vmsleu_vx = 525, 557 rv_op_vmsleu_vi = 526, 558 rv_op_vmsle_vv = 527, 559 rv_op_vmsle_vx = 528, 560 rv_op_vmsle_vi = 529, 561 rv_op_vmsgtu_vx = 530, 562 rv_op_vmsgtu_vi = 531, 563 rv_op_vmsgt_vx = 532, 564 rv_op_vmsgt_vi = 533, 565 rv_op_vminu_vv = 534, 566 rv_op_vminu_vx = 535, 567 rv_op_vmin_vv = 536, 568 rv_op_vmin_vx = 537, 569 rv_op_vmaxu_vv = 538, 570 rv_op_vmaxu_vx = 539, 571 rv_op_vmax_vv = 540, 572 rv_op_vmax_vx = 541, 573 rv_op_vmul_vv = 542, 574 rv_op_vmul_vx = 543, 575 rv_op_vmulh_vv = 544, 576 rv_op_vmulh_vx = 545, 577 rv_op_vmulhu_vv = 546, 578 rv_op_vmulhu_vx = 547, 579 rv_op_vmulhsu_vv = 548, 580 rv_op_vmulhsu_vx = 549, 581 rv_op_vdivu_vv = 550, 582 rv_op_vdivu_vx = 551, 583 rv_op_vdiv_vv = 552, 584 rv_op_vdiv_vx = 553, 585 rv_op_vremu_vv = 554, 586 rv_op_vremu_vx = 555, 587 rv_op_vrem_vv = 556, 588 rv_op_vrem_vx = 557, 589 rv_op_vwmulu_vv = 558, 590 rv_op_vwmulu_vx = 559, 591 rv_op_vwmulsu_vv = 560, 592 rv_op_vwmulsu_vx = 561, 593 rv_op_vwmul_vv = 562, 594 rv_op_vwmul_vx = 563, 595 rv_op_vmacc_vv = 564, 596 rv_op_vmacc_vx = 565, 597 rv_op_vnmsac_vv = 566, 598 rv_op_vnmsac_vx = 567, 599 rv_op_vmadd_vv = 568, 600 rv_op_vmadd_vx = 569, 601 rv_op_vnmsub_vv = 570, 602 rv_op_vnmsub_vx = 571, 603 rv_op_vwmaccu_vv = 572, 604 rv_op_vwmaccu_vx = 573, 605 rv_op_vwmacc_vv = 574, 606 rv_op_vwmacc_vx = 575, 607 rv_op_vwmaccsu_vv = 576, 608 rv_op_vwmaccsu_vx = 577, 609 rv_op_vwmaccus_vx = 578, 610 rv_op_vmv_v_v = 579, 611 rv_op_vmv_v_x = 580, 612 rv_op_vmv_v_i = 581, 613 rv_op_vmerge_vvm = 582, 614 rv_op_vmerge_vxm = 583, 615 rv_op_vmerge_vim = 584, 616 rv_op_vsaddu_vv = 585, 617 rv_op_vsaddu_vx = 586, 618 rv_op_vsaddu_vi = 587, 619 rv_op_vsadd_vv = 588, 620 rv_op_vsadd_vx = 589, 621 rv_op_vsadd_vi = 590, 622 rv_op_vssubu_vv = 591, 623 rv_op_vssubu_vx = 592, 624 rv_op_vssub_vv = 593, 625 rv_op_vssub_vx = 594, 626 rv_op_vaadd_vv = 595, 627 rv_op_vaadd_vx = 596, 628 rv_op_vaaddu_vv = 597, 629 rv_op_vaaddu_vx = 598, 630 rv_op_vasub_vv = 599, 631 rv_op_vasub_vx = 600, 632 rv_op_vasubu_vv = 601, 633 rv_op_vasubu_vx = 602, 634 rv_op_vsmul_vv = 603, 635 rv_op_vsmul_vx = 604, 636 rv_op_vssrl_vv = 605, 637 rv_op_vssrl_vx = 606, 638 rv_op_vssrl_vi = 607, 639 rv_op_vssra_vv = 608, 640 rv_op_vssra_vx = 609, 641 rv_op_vssra_vi = 610, 642 rv_op_vnclipu_wv = 611, 643 rv_op_vnclipu_wx = 612, 644 rv_op_vnclipu_wi = 613, 645 rv_op_vnclip_wv = 614, 646 rv_op_vnclip_wx = 615, 647 rv_op_vnclip_wi = 616, 648 rv_op_vfadd_vv = 617, 649 rv_op_vfadd_vf = 618, 650 rv_op_vfsub_vv = 619, 651 rv_op_vfsub_vf = 620, 652 rv_op_vfrsub_vf = 621, 653 rv_op_vfwadd_vv = 622, 654 rv_op_vfwadd_vf = 623, 655 rv_op_vfwadd_wv = 624, 656 rv_op_vfwadd_wf = 625, 657 rv_op_vfwsub_vv = 626, 658 rv_op_vfwsub_vf = 627, 659 rv_op_vfwsub_wv = 628, 660 rv_op_vfwsub_wf = 629, 661 rv_op_vfmul_vv = 630, 662 rv_op_vfmul_vf = 631, 663 rv_op_vfdiv_vv = 632, 664 rv_op_vfdiv_vf = 633, 665 rv_op_vfrdiv_vf = 634, 666 rv_op_vfwmul_vv = 635, 667 rv_op_vfwmul_vf = 636, 668 rv_op_vfmacc_vv = 637, 669 rv_op_vfmacc_vf = 638, 670 rv_op_vfnmacc_vv = 639, 671 rv_op_vfnmacc_vf = 640, 672 rv_op_vfmsac_vv = 641, 673 rv_op_vfmsac_vf = 642, 674 rv_op_vfnmsac_vv = 643, 675 rv_op_vfnmsac_vf = 644, 676 rv_op_vfmadd_vv = 645, 677 rv_op_vfmadd_vf = 646, 678 rv_op_vfnmadd_vv = 647, 679 rv_op_vfnmadd_vf = 648, 680 rv_op_vfmsub_vv = 649, 681 rv_op_vfmsub_vf = 650, 682 rv_op_vfnmsub_vv = 651, 683 rv_op_vfnmsub_vf = 652, 684 rv_op_vfwmacc_vv = 653, 685 rv_op_vfwmacc_vf = 654, 686 rv_op_vfwnmacc_vv = 655, 687 rv_op_vfwnmacc_vf = 656, 688 rv_op_vfwmsac_vv = 657, 689 rv_op_vfwmsac_vf = 658, 690 rv_op_vfwnmsac_vv = 659, 691 rv_op_vfwnmsac_vf = 660, 692 rv_op_vfsqrt_v = 661, 693 rv_op_vfrsqrt7_v = 662, 694 rv_op_vfrec7_v = 663, 695 rv_op_vfmin_vv = 664, 696 rv_op_vfmin_vf = 665, 697 rv_op_vfmax_vv = 666, 698 rv_op_vfmax_vf = 667, 699 rv_op_vfsgnj_vv = 668, 700 rv_op_vfsgnj_vf = 669, 701 rv_op_vfsgnjn_vv = 670, 702 rv_op_vfsgnjn_vf = 671, 703 rv_op_vfsgnjx_vv = 672, 704 rv_op_vfsgnjx_vf = 673, 705 rv_op_vfslide1up_vf = 674, 706 rv_op_vfslide1down_vf = 675, 707 rv_op_vmfeq_vv = 676, 708 rv_op_vmfeq_vf = 677, 709 rv_op_vmfne_vv = 678, 710 rv_op_vmfne_vf = 679, 711 rv_op_vmflt_vv = 680, 712 rv_op_vmflt_vf = 681, 713 rv_op_vmfle_vv = 682, 714 rv_op_vmfle_vf = 683, 715 rv_op_vmfgt_vf = 684, 716 rv_op_vmfge_vf = 685, 717 rv_op_vfclass_v = 686, 718 rv_op_vfmerge_vfm = 687, 719 rv_op_vfmv_v_f = 688, 720 rv_op_vfcvt_xu_f_v = 689, 721 rv_op_vfcvt_x_f_v = 690, 722 rv_op_vfcvt_f_xu_v = 691, 723 rv_op_vfcvt_f_x_v = 692, 724 rv_op_vfcvt_rtz_xu_f_v = 693, 725 rv_op_vfcvt_rtz_x_f_v = 694, 726 rv_op_vfwcvt_xu_f_v = 695, 727 rv_op_vfwcvt_x_f_v = 696, 728 rv_op_vfwcvt_f_xu_v = 697, 729 rv_op_vfwcvt_f_x_v = 698, 730 rv_op_vfwcvt_f_f_v = 699, 731 rv_op_vfwcvt_rtz_xu_f_v = 700, 732 rv_op_vfwcvt_rtz_x_f_v = 701, 733 rv_op_vfncvt_xu_f_w = 702, 734 rv_op_vfncvt_x_f_w = 703, 735 rv_op_vfncvt_f_xu_w = 704, 736 rv_op_vfncvt_f_x_w = 705, 737 rv_op_vfncvt_f_f_w = 706, 738 rv_op_vfncvt_rod_f_f_w = 707, 739 rv_op_vfncvt_rtz_xu_f_w = 708, 740 rv_op_vfncvt_rtz_x_f_w = 709, 741 rv_op_vredsum_vs = 710, 742 rv_op_vredand_vs = 711, 743 rv_op_vredor_vs = 712, 744 rv_op_vredxor_vs = 713, 745 rv_op_vredminu_vs = 714, 746 rv_op_vredmin_vs = 715, 747 rv_op_vredmaxu_vs = 716, 748 rv_op_vredmax_vs = 717, 749 rv_op_vwredsumu_vs = 718, 750 rv_op_vwredsum_vs = 719, 751 rv_op_vfredusum_vs = 720, 752 rv_op_vfredosum_vs = 721, 753 rv_op_vfredmin_vs = 722, 754 rv_op_vfredmax_vs = 723, 755 rv_op_vfwredusum_vs = 724, 756 rv_op_vfwredosum_vs = 725, 757 rv_op_vmand_mm = 726, 758 rv_op_vmnand_mm = 727, 759 rv_op_vmandn_mm = 728, 760 rv_op_vmxor_mm = 729, 761 rv_op_vmor_mm = 730, 762 rv_op_vmnor_mm = 731, 763 rv_op_vmorn_mm = 732, 764 rv_op_vmxnor_mm = 733, 765 rv_op_vcpop_m = 734, 766 rv_op_vfirst_m = 735, 767 rv_op_vmsbf_m = 736, 768 rv_op_vmsif_m = 737, 769 rv_op_vmsof_m = 738, 770 rv_op_viota_m = 739, 771 rv_op_vid_v = 740, 772 rv_op_vmv_x_s = 741, 773 rv_op_vmv_s_x = 742, 774 rv_op_vfmv_f_s = 743, 775 rv_op_vfmv_s_f = 744, 776 rv_op_vslideup_vx = 745, 777 rv_op_vslideup_vi = 746, 778 rv_op_vslide1up_vx = 747, 779 rv_op_vslidedown_vx = 748, 780 rv_op_vslidedown_vi = 749, 781 rv_op_vslide1down_vx = 750, 782 rv_op_vrgather_vv = 751, 783 rv_op_vrgatherei16_vv = 752, 784 rv_op_vrgather_vx = 753, 785 rv_op_vrgather_vi = 754, 786 rv_op_vcompress_vm = 755, 787 rv_op_vmv1r_v = 756, 788 rv_op_vmv2r_v = 757, 789 rv_op_vmv4r_v = 758, 790 rv_op_vmv8r_v = 759, 791 rv_op_vzext_vf2 = 760, 792 rv_op_vzext_vf4 = 761, 793 rv_op_vzext_vf8 = 762, 794 rv_op_vsext_vf2 = 763, 795 rv_op_vsext_vf4 = 764, 796 rv_op_vsext_vf8 = 765, 797 rv_op_vsetvli = 766, 798 rv_op_vsetivli = 767, 799 rv_op_vsetvl = 768, 800 rv_op_c_zext_b = 769, 801 rv_op_c_sext_b = 770, 802 rv_op_c_zext_h = 771, 803 rv_op_c_sext_h = 772, 804 rv_op_c_zext_w = 773, 805 rv_op_c_not = 774, 806 rv_op_c_mul = 775, 807 rv_op_c_lbu = 776, 808 rv_op_c_lhu = 777, 809 rv_op_c_lh = 778, 810 rv_op_c_sb = 779, 811 rv_op_c_sh = 780, 812 rv_op_cm_push = 781, 813 rv_op_cm_pop = 782, 814 rv_op_cm_popret = 783, 815 rv_op_cm_popretz = 784, 816 rv_op_cm_mva01s = 785, 817 rv_op_cm_mvsa01 = 786, 818 rv_op_cm_jt = 787, 819 rv_op_cm_jalt = 788, 820 rv_op_czero_eqz = 789, 821 rv_op_czero_nez = 790, 822 rv_op_fcvt_bf16_s = 791, 823 rv_op_fcvt_s_bf16 = 792, 824 rv_op_vfncvtbf16_f_f_w = 793, 825 rv_op_vfwcvtbf16_f_f_v = 794, 826 rv_op_vfwmaccbf16_vv = 795, 827 rv_op_vfwmaccbf16_vf = 796, 828 rv_op_flh = 797, 829 rv_op_fsh = 798, 830 rv_op_fmv_h_x = 799, 831 rv_op_fmv_x_h = 800, 832 rv_op_fli_s = 801, 833 rv_op_fli_d = 802, 834 rv_op_fli_q = 803, 835 rv_op_fli_h = 804, 836 rv_op_fminm_s = 805, 837 rv_op_fmaxm_s = 806, 838 rv_op_fminm_d = 807, 839 rv_op_fmaxm_d = 808, 840 rv_op_fminm_q = 809, 841 rv_op_fmaxm_q = 810, 842 rv_op_fminm_h = 811, 843 rv_op_fmaxm_h = 812, 844 rv_op_fround_s = 813, 845 rv_op_froundnx_s = 814, 846 rv_op_fround_d = 815, 847 rv_op_froundnx_d = 816, 848 rv_op_fround_q = 817, 849 rv_op_froundnx_q = 818, 850 rv_op_fround_h = 819, 851 rv_op_froundnx_h = 820, 852 rv_op_fcvtmod_w_d = 821, 853 rv_op_fmvh_x_d = 822, 854 rv_op_fmvp_d_x = 823, 855 rv_op_fmvh_x_q = 824, 856 rv_op_fmvp_q_x = 825, 857 rv_op_fleq_s = 826, 858 rv_op_fltq_s = 827, 859 rv_op_fleq_d = 828, 860 rv_op_fltq_d = 829, 861 rv_op_fleq_q = 830, 862 rv_op_fltq_q = 831, 863 rv_op_fleq_h = 832, 864 rv_op_fltq_h = 833, 865 } rv_op; 866 867 /* register names */ 868 869 static const char rv_ireg_name_sym[32][5] = { 870 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 871 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 872 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 873 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", 874 }; 875 876 static const char rv_freg_name_sym[32][5] = { 877 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", 878 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", 879 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", 880 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11", 881 }; 882 883 static const char rv_vreg_name_sym[32][4] = { 884 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 885 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 886 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 887 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 888 }; 889 890 /* The FLI.[HSDQ] numeric constants (0.0 for symbolic constants). 891 * The constants use the hex floating-point literal representation 892 * that is printed when using the printf %a format specifier, 893 * which matches the output that is generated by the disassembler. 894 */ 895 static const char rv_fli_name_const[32][9] = 896 { 897 "0x1p+0", "min", "0x1p-16", "0x1p-15", 898 "0x1p-8", "0x1p-7", "0x1p-4", "0x1p-3", 899 "0x1p-2", "0x1.4p-2", "0x1.8p-2", "0x1.cp-2", 900 "0x1p-1", "0x1.4p-1", "0x1.8p-1", "0x1.cp-1", 901 "0x1p+0", "0x1.4p+0", "0x1.8p+0", "0x1.cp+0", 902 "0x1p+1", "0x1.4p+1", "0x1.8p+1", "0x1p+2", 903 "0x1p+3", "0x1p+4", "0x1p+7", "0x1p+8", 904 "0x1p+15", "0x1p+16", "inf", "nan" 905 }; 906 907 /* pseudo-instruction constraints */ 908 909 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end }; 910 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, 911 rvc_end }; 912 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, 913 rvc_imm_eq_zero, rvc_end }; 914 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; 915 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end }; 916 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end }; 917 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end }; 918 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end }; 919 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end }; 920 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end }; 921 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end }; 922 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end }; 923 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end }; 924 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end }; 925 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end }; 926 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end }; 927 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end }; 928 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end }; 929 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end }; 930 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end }; 931 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end }; 932 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end }; 933 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end }; 934 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end }; 935 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end }; 936 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end }; 937 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end }; 938 static const rvc_constraint rvcc_ble[] = { rvc_end }; 939 static const rvc_constraint rvcc_bleu[] = { rvc_end }; 940 static const rvc_constraint rvcc_bgt[] = { rvc_end }; 941 static const rvc_constraint rvcc_bgtu[] = { rvc_end }; 942 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end }; 943 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, 944 rvc_end }; 945 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, 946 rvc_end }; 947 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, 948 rvc_end }; 949 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, 950 rvc_end }; 951 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, 952 rvc_csr_eq_0xc02, rvc_end }; 953 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, 954 rvc_csr_eq_0xc80, rvc_end }; 955 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, 956 rvc_end }; 957 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, 958 rvc_csr_eq_0xc82, rvc_end }; 959 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, 960 rvc_end }; 961 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, 962 rvc_end }; 963 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, 964 rvc_end }; 965 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end }; 966 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end }; 967 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end }; 968 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end }; 969 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end }; 970 971 /* pseudo-instruction metadata */ 972 973 static const rv_comp_data rvcp_jal[] = { 974 { rv_op_j, rvcc_j }, 975 { rv_op_jal, rvcc_jal }, 976 { rv_op_illegal, NULL } 977 }; 978 979 static const rv_comp_data rvcp_jalr[] = { 980 { rv_op_ret, rvcc_ret }, 981 { rv_op_jr, rvcc_jr }, 982 { rv_op_jalr, rvcc_jalr }, 983 { rv_op_illegal, NULL } 984 }; 985 986 static const rv_comp_data rvcp_beq[] = { 987 { rv_op_beqz, rvcc_beqz }, 988 { rv_op_illegal, NULL } 989 }; 990 991 static const rv_comp_data rvcp_bne[] = { 992 { rv_op_bnez, rvcc_bnez }, 993 { rv_op_illegal, NULL } 994 }; 995 996 static const rv_comp_data rvcp_blt[] = { 997 { rv_op_bltz, rvcc_bltz }, 998 { rv_op_bgtz, rvcc_bgtz }, 999 { rv_op_bgt, rvcc_bgt }, 1000 { rv_op_illegal, NULL } 1001 }; 1002 1003 static const rv_comp_data rvcp_bge[] = { 1004 { rv_op_blez, rvcc_blez }, 1005 { rv_op_bgez, rvcc_bgez }, 1006 { rv_op_ble, rvcc_ble }, 1007 { rv_op_illegal, NULL } 1008 }; 1009 1010 static const rv_comp_data rvcp_bltu[] = { 1011 { rv_op_bgtu, rvcc_bgtu }, 1012 { rv_op_illegal, NULL } 1013 }; 1014 1015 static const rv_comp_data rvcp_bgeu[] = { 1016 { rv_op_bleu, rvcc_bleu }, 1017 { rv_op_illegal, NULL } 1018 }; 1019 1020 static const rv_comp_data rvcp_addi[] = { 1021 { rv_op_nop, rvcc_nop }, 1022 { rv_op_mv, rvcc_mv }, 1023 { rv_op_illegal, NULL } 1024 }; 1025 1026 static const rv_comp_data rvcp_sltiu[] = { 1027 { rv_op_seqz, rvcc_seqz }, 1028 { rv_op_illegal, NULL } 1029 }; 1030 1031 static const rv_comp_data rvcp_xori[] = { 1032 { rv_op_not, rvcc_not }, 1033 { rv_op_illegal, NULL } 1034 }; 1035 1036 static const rv_comp_data rvcp_sub[] = { 1037 { rv_op_neg, rvcc_neg }, 1038 { rv_op_illegal, NULL } 1039 }; 1040 1041 static const rv_comp_data rvcp_slt[] = { 1042 { rv_op_sltz, rvcc_sltz }, 1043 { rv_op_sgtz, rvcc_sgtz }, 1044 { rv_op_illegal, NULL } 1045 }; 1046 1047 static const rv_comp_data rvcp_sltu[] = { 1048 { rv_op_snez, rvcc_snez }, 1049 { rv_op_illegal, NULL } 1050 }; 1051 1052 static const rv_comp_data rvcp_addiw[] = { 1053 { rv_op_sext_w, rvcc_sext_w }, 1054 { rv_op_illegal, NULL } 1055 }; 1056 1057 static const rv_comp_data rvcp_subw[] = { 1058 { rv_op_negw, rvcc_negw }, 1059 { rv_op_illegal, NULL } 1060 }; 1061 1062 static const rv_comp_data rvcp_csrrw[] = { 1063 { rv_op_fscsr, rvcc_fscsr }, 1064 { rv_op_fsrm, rvcc_fsrm }, 1065 { rv_op_fsflags, rvcc_fsflags }, 1066 { rv_op_illegal, NULL } 1067 }; 1068 1069 1070 static const rv_comp_data rvcp_csrrs[] = { 1071 { rv_op_rdcycle, rvcc_rdcycle }, 1072 { rv_op_rdtime, rvcc_rdtime }, 1073 { rv_op_rdinstret, rvcc_rdinstret }, 1074 { rv_op_rdcycleh, rvcc_rdcycleh }, 1075 { rv_op_rdtimeh, rvcc_rdtimeh }, 1076 { rv_op_rdinstreth, rvcc_rdinstreth }, 1077 { rv_op_frcsr, rvcc_frcsr }, 1078 { rv_op_frrm, rvcc_frrm }, 1079 { rv_op_frflags, rvcc_frflags }, 1080 { rv_op_illegal, NULL } 1081 }; 1082 1083 static const rv_comp_data rvcp_csrrwi[] = { 1084 { rv_op_fsrmi, rvcc_fsrmi }, 1085 { rv_op_fsflagsi, rvcc_fsflagsi }, 1086 { rv_op_illegal, NULL } 1087 }; 1088 1089 static const rv_comp_data rvcp_fsgnj_s[] = { 1090 { rv_op_fmv_s, rvcc_fmv_s }, 1091 { rv_op_illegal, NULL } 1092 }; 1093 1094 static const rv_comp_data rvcp_fsgnjn_s[] = { 1095 { rv_op_fneg_s, rvcc_fneg_s }, 1096 { rv_op_illegal, NULL } 1097 }; 1098 1099 static const rv_comp_data rvcp_fsgnjx_s[] = { 1100 { rv_op_fabs_s, rvcc_fabs_s }, 1101 { rv_op_illegal, NULL } 1102 }; 1103 1104 static const rv_comp_data rvcp_fsgnj_d[] = { 1105 { rv_op_fmv_d, rvcc_fmv_d }, 1106 { rv_op_illegal, NULL } 1107 }; 1108 1109 static const rv_comp_data rvcp_fsgnjn_d[] = { 1110 { rv_op_fneg_d, rvcc_fneg_d }, 1111 { rv_op_illegal, NULL } 1112 }; 1113 1114 static const rv_comp_data rvcp_fsgnjx_d[] = { 1115 { rv_op_fabs_d, rvcc_fabs_d }, 1116 { rv_op_illegal, NULL } 1117 }; 1118 1119 static const rv_comp_data rvcp_fsgnj_q[] = { 1120 { rv_op_fmv_q, rvcc_fmv_q }, 1121 { rv_op_illegal, NULL } 1122 }; 1123 1124 static const rv_comp_data rvcp_fsgnjn_q[] = { 1125 { rv_op_fneg_q, rvcc_fneg_q }, 1126 { rv_op_illegal, NULL } 1127 }; 1128 1129 static const rv_comp_data rvcp_fsgnjx_q[] = { 1130 { rv_op_fabs_q, rvcc_fabs_q }, 1131 { rv_op_illegal, NULL } 1132 }; 1133 1134 /* instruction metadata */ 1135 1136 const rv_opcode_data rvi_opcode_data[] = { 1137 { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, 1138 { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 }, 1139 { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 }, 1140 { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 }, 1141 { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 }, 1142 { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 }, 1143 { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 }, 1144 { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 }, 1145 { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 }, 1146 { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 }, 1147 { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 }, 1148 { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1149 { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1150 { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1151 { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1152 { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1153 { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1154 { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1155 { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1156 { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 }, 1157 { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1158 { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 }, 1159 { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 }, 1160 { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1161 { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1162 { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1163 { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1164 { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1165 { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1166 { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 }, 1167 { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1168 { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 }, 1169 { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 }, 1170 { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1171 { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1172 { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1173 { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1174 { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1175 { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 }, 1176 { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1177 { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1178 { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1179 { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1180 { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 }, 1181 { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1182 { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1183 { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1184 { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1185 { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 }, 1186 { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1187 { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1188 { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1189 { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1190 { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1191 { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1192 { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1193 { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1194 { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1195 { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1196 { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1197 { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1198 { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1199 { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1200 { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1201 { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1202 { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1203 { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1204 { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1205 { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1206 { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1207 { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1208 { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1209 { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1210 { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1211 { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1212 { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1213 { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1214 { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1215 { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1216 { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1217 { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1218 { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1219 { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1220 { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1221 { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1222 { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1223 { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1224 { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1225 { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1226 { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1227 { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1228 { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1229 { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1230 { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1231 { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1232 { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1233 { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1234 { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1235 { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1236 { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1237 { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1238 { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1239 { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1240 { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1241 { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1242 { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1243 { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1244 { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1245 { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1246 { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1247 { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1248 { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1249 { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1250 { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1251 { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1252 { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1253 { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1254 { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1255 { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1256 { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1257 { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1258 { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1259 { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, 1260 { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 }, 1261 { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1262 { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 }, 1263 { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 }, 1264 { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 }, 1265 { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 }, 1266 { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1267 { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1268 { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1269 { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1270 { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1271 { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1272 { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1273 { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1274 { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1275 { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1276 { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1277 { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1278 { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 }, 1279 { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 }, 1280 { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 }, 1281 { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1282 { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1283 { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1284 { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1285 { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1286 { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1287 { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1288 { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1289 { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1290 { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1291 { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1292 { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1293 { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1294 { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1295 { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1296 { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1297 { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1298 { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1299 { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1300 { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1301 { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1302 { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1303 { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1304 { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1305 { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1306 { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1307 { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1308 { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 }, 1309 { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 }, 1310 { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 }, 1311 { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1312 { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1313 { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1314 { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1315 { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1316 { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1317 { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1318 { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1319 { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1320 { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1321 { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1322 { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1323 { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1324 { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1325 { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1326 { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1327 { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1328 { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1329 { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1330 { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1331 { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1332 { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1333 { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1334 { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1335 { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1336 { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1337 { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1338 { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1339 { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1340 { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 }, 1341 { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 }, 1342 { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 }, 1343 { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1344 { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1345 { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1346 { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1347 { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1348 { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1349 { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1350 { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1351 { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1352 { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1353 { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1354 { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1355 { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1356 { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1357 { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1358 { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1359 { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1360 { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1361 { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1362 { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1363 { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1364 { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1365 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1366 { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1367 rv_op_fld, 0 }, 1368 { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, 1369 rv_op_lw }, 1370 { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, 1371 { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1372 rv_op_fsd, 0 }, 1373 { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, 1374 rv_op_sw }, 1375 { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, 1376 { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, 1377 rv_op_addi }, 1378 { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1379 rv_op_addi, rvcd_imm_nz }, 1380 { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 }, 1381 { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1382 rv_op_addi }, 1383 { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1384 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1385 { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui, 1386 rv_op_lui, rvcd_imm_nz }, 1387 { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, 1388 rv_op_srli, rv_op_srli, rvcd_imm_nz }, 1389 { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, 1390 rv_op_srai, rv_op_srai, rvcd_imm_nz }, 1391 { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, 1392 rv_op_andi, rv_op_andi }, 1393 { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, 1394 rv_op_sub }, 1395 { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, 1396 rv_op_xor }, 1397 { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, 1398 rv_op_or }, 1399 { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, 1400 rv_op_and }, 1401 { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, 1402 rv_op_subw }, 1403 { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, 1404 rv_op_addw }, 1405 { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, 1406 rv_op_jal }, 1407 { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, 1408 rv_op_beq }, 1409 { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, 1410 rv_op_bne }, 1411 { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, 1412 rv_op_slli, rv_op_slli, rvcd_imm_nz }, 1413 { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1414 rv_op_fld, rv_op_fld }, 1415 { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, 1416 rv_op_lw, rv_op_lw }, 1417 { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 1418 0 }, 1419 { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1420 rv_op_jalr, rv_op_jalr }, 1421 { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, 1422 rv_op_addi }, 1423 { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, 1424 rv_op_ebreak, rv_op_ebreak }, 1425 { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1426 rv_op_jalr, rv_op_jalr }, 1427 { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, 1428 rv_op_add }, 1429 { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1430 rv_op_fsd, rv_op_fsd }, 1431 { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, 1432 rv_op_sw, rv_op_sw }, 1433 { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 1434 0 }, 1435 { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1436 rv_op_ld }, 1437 { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1438 rv_op_sd }, 1439 { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, 1440 rv_op_addiw }, 1441 { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1442 rv_op_ld }, 1443 { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1444 rv_op_sd }, 1445 { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1446 { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, 1447 { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1448 { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 1449 rv_op_sq }, 1450 { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1451 { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1452 { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1453 { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1454 { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1455 { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1456 { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1457 { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1458 { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1459 { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1460 { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1461 { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1462 { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1463 { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1464 { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1465 { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1466 { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1467 { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1468 { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1469 { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1470 { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1471 { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1472 { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1473 { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1474 { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1475 { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1476 { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1477 { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1478 { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1479 { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 }, 1480 { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1481 { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 }, 1482 { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1483 { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1484 { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1485 { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1486 { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1487 { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1488 { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1489 { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1490 { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1491 { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1492 { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1493 { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1494 { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1495 { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1496 { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1497 { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1498 { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1499 { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1500 { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1501 { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1502 { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1503 { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1504 { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1505 { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1506 { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1507 { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1508 { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1509 { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1510 { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1511 { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1512 { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1513 { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1514 { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1515 { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1516 { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1517 { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1518 { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1519 { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1520 { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1521 { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1522 { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1523 { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1524 { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1525 { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1526 { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1527 { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1528 { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1529 { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1530 { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1531 { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1532 { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1533 { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1534 { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1535 { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1536 { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1537 { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1538 { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1539 { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1540 { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1541 { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1542 { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1543 { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 }, 1544 { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1545 { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1546 { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1547 { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1548 { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1549 { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1550 { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1551 { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1552 { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1553 { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1554 { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1555 { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1556 { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1557 { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1558 { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1559 { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1560 { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1561 { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1562 { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1563 { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1564 { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1565 { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1566 { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1567 { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1568 { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1569 { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1570 { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1571 { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1572 { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1573 { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1574 { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1575 { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1576 { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1577 { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1578 { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1579 { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1580 { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1581 { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1582 { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1583 { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1584 { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1585 { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1586 { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1587 { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1588 { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1589 { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1590 { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1591 { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1592 { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1593 { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1594 { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1595 { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1596 { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1597 { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1598 { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1599 { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1600 { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1601 { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1602 { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1603 { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1604 { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1605 { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1606 { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1607 { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1608 { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1609 { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1610 { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1611 { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1612 { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1613 { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1614 { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1615 { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1616 { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1617 { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1618 { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1619 { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1620 { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1621 { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1622 { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1623 { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1624 { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1625 { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1626 { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1627 { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1628 { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1629 { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1630 { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1631 { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1632 { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1633 { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1634 { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1635 { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1636 { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1637 { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1638 { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1639 { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1640 { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1641 { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1642 { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1643 { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1644 { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1645 { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1646 { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1647 { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1648 { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1649 { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1650 { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1651 { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1652 { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1653 { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1654 { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1655 { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1656 { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1657 { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1658 { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1659 { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1660 { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1661 { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1662 { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1663 { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1664 { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1665 { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1666 { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1667 { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1668 { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1669 { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1670 { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1671 { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1672 { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1673 { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1674 { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1675 { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1676 { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1677 { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1678 { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1679 { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1680 { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1681 { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1682 { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1683 { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1684 { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1685 { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1686 { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1687 { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1688 { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1689 { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1690 { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1691 { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1692 { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1693 { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1694 { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1695 { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1696 { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1697 { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1698 { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1699 { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1700 { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1701 { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1702 { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1703 { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1704 { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1705 { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1706 { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1707 { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1708 { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1709 { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1710 { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1711 { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1712 { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1713 { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1714 { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1715 { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1716 { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1717 { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1718 { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1719 { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1720 { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1721 { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1722 { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1723 { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1724 { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1725 { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1726 { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1727 { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1728 { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1729 { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1730 { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1731 { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1732 { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1733 { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1734 { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1735 { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1736 { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1737 { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1738 { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1739 { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1740 { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1741 { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1742 { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1743 { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1744 { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1745 { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1746 { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1747 { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1748 { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1749 { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1750 { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1751 { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1752 { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1753 { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1754 { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1755 { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1756 { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 }, 1757 { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 1758 { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 }, 1759 { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1760 { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1761 { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1762 { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1763 { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1764 { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1765 { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1766 { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1767 { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1768 { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1769 { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1770 { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1771 { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1772 { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1773 { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1774 { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1775 { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1776 { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1777 { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1778 { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1779 { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1780 { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1781 { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1782 { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1783 { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1784 { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1785 { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1786 { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1787 { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1788 { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1789 { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1790 { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1791 { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1792 { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1793 { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1794 { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1795 { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1796 { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1797 { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1798 { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1799 { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1800 { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1801 { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1802 { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1803 { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1804 { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1805 { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1806 { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1807 { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1808 { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1809 { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1810 { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1811 { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1812 { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1813 { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1814 { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1815 { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1816 { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1817 { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1818 { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1819 { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1820 { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1821 { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1822 { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1823 { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1824 { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1825 { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1826 { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1827 { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1828 { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1829 { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1830 { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1831 { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1832 { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1833 { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1834 { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1835 { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1836 { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1837 { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1838 { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1839 { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1840 { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1841 { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1842 { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1843 { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1844 { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1845 { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1846 { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1847 { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1848 { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1849 { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1850 { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1851 { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1852 { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1853 { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1854 { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1855 { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1856 { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1857 { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1858 { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1859 { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1860 { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1861 { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1862 { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1863 { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1864 { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 }, 1865 { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 1866 { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1867 { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1868 { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1869 { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1870 { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1871 { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1872 { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1873 { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1874 { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1875 { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1876 { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1877 { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1878 { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1879 { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1880 { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1881 { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1882 { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1883 { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1884 { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1885 { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1886 { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1887 { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1888 { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1889 { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1890 { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1891 { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1892 { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1893 { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1894 { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1895 { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1896 { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1897 { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1898 { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1899 { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1900 { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1901 { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1902 { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1903 { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1904 { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1905 { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1906 { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1907 { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1908 { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1909 { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1910 { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1911 { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 1912 { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 1913 { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1914 { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1915 { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1916 { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1917 { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 }, 1918 { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 }, 1919 { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 1920 { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 }, 1921 { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 1922 { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1923 { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1924 { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1925 { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1926 { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1927 { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1928 { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1929 { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1930 { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1931 { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1932 { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 1933 { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1934 { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1935 { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1936 { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1937 { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1938 { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1939 { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1940 { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1941 { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1942 { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1943 { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 }, 1944 { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 }, 1945 { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1946 { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1947 { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1948 { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1949 { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1950 { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1951 { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 1952 { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 }, 1953 { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1954 { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1955 { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1956 { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1957 { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 1958 { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 }, 1959 { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 1960 { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 }, 1961 { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 1962 { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1963 { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1964 { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 1965 { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 1966 { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1967 { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1968 { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1969 { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1970 { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1971 { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1972 { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1973 { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1974 { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1975 { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1976 { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1977 { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1978 { "fli.s", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 1979 { "fli.d", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 1980 { "fli.q", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 1981 { "fli.h", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 1982 { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1983 { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1984 { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1985 { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1986 { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1987 { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1988 { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1989 { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1990 { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1991 { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1992 { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1993 { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1994 { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1995 { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1996 { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1997 { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1998 { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1999 { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2000 { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2001 { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2002 { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2003 { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2004 { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2005 { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2006 { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2007 { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2008 { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2009 { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2010 { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2011 }; 2012 2013 /* CSR names */ 2014 2015 static const char *csr_name(int csrno) 2016 { 2017 switch (csrno) { 2018 case 0x0000: return "ustatus"; 2019 case 0x0001: return "fflags"; 2020 case 0x0002: return "frm"; 2021 case 0x0003: return "fcsr"; 2022 case 0x0004: return "uie"; 2023 case 0x0005: return "utvec"; 2024 case 0x0008: return "vstart"; 2025 case 0x0009: return "vxsat"; 2026 case 0x000a: return "vxrm"; 2027 case 0x000f: return "vcsr"; 2028 case 0x0015: return "seed"; 2029 case 0x0017: return "jvt"; 2030 case 0x0040: return "uscratch"; 2031 case 0x0041: return "uepc"; 2032 case 0x0042: return "ucause"; 2033 case 0x0043: return "utval"; 2034 case 0x0044: return "uip"; 2035 case 0x0100: return "sstatus"; 2036 case 0x0104: return "sie"; 2037 case 0x0105: return "stvec"; 2038 case 0x0106: return "scounteren"; 2039 case 0x0140: return "sscratch"; 2040 case 0x0141: return "sepc"; 2041 case 0x0142: return "scause"; 2042 case 0x0143: return "stval"; 2043 case 0x0144: return "sip"; 2044 case 0x0180: return "satp"; 2045 case 0x0200: return "hstatus"; 2046 case 0x0202: return "hedeleg"; 2047 case 0x0203: return "hideleg"; 2048 case 0x0204: return "hie"; 2049 case 0x0205: return "htvec"; 2050 case 0x0240: return "hscratch"; 2051 case 0x0241: return "hepc"; 2052 case 0x0242: return "hcause"; 2053 case 0x0243: return "hbadaddr"; 2054 case 0x0244: return "hip"; 2055 case 0x0300: return "mstatus"; 2056 case 0x0301: return "misa"; 2057 case 0x0302: return "medeleg"; 2058 case 0x0303: return "mideleg"; 2059 case 0x0304: return "mie"; 2060 case 0x0305: return "mtvec"; 2061 case 0x0306: return "mcounteren"; 2062 case 0x0320: return "mucounteren"; 2063 case 0x0321: return "mscounteren"; 2064 case 0x0322: return "mhcounteren"; 2065 case 0x0323: return "mhpmevent3"; 2066 case 0x0324: return "mhpmevent4"; 2067 case 0x0325: return "mhpmevent5"; 2068 case 0x0326: return "mhpmevent6"; 2069 case 0x0327: return "mhpmevent7"; 2070 case 0x0328: return "mhpmevent8"; 2071 case 0x0329: return "mhpmevent9"; 2072 case 0x032a: return "mhpmevent10"; 2073 case 0x032b: return "mhpmevent11"; 2074 case 0x032c: return "mhpmevent12"; 2075 case 0x032d: return "mhpmevent13"; 2076 case 0x032e: return "mhpmevent14"; 2077 case 0x032f: return "mhpmevent15"; 2078 case 0x0330: return "mhpmevent16"; 2079 case 0x0331: return "mhpmevent17"; 2080 case 0x0332: return "mhpmevent18"; 2081 case 0x0333: return "mhpmevent19"; 2082 case 0x0334: return "mhpmevent20"; 2083 case 0x0335: return "mhpmevent21"; 2084 case 0x0336: return "mhpmevent22"; 2085 case 0x0337: return "mhpmevent23"; 2086 case 0x0338: return "mhpmevent24"; 2087 case 0x0339: return "mhpmevent25"; 2088 case 0x033a: return "mhpmevent26"; 2089 case 0x033b: return "mhpmevent27"; 2090 case 0x033c: return "mhpmevent28"; 2091 case 0x033d: return "mhpmevent29"; 2092 case 0x033e: return "mhpmevent30"; 2093 case 0x033f: return "mhpmevent31"; 2094 case 0x0340: return "mscratch"; 2095 case 0x0341: return "mepc"; 2096 case 0x0342: return "mcause"; 2097 case 0x0343: return "mtval"; 2098 case 0x0344: return "mip"; 2099 case 0x0380: return "mbase"; 2100 case 0x0381: return "mbound"; 2101 case 0x0382: return "mibase"; 2102 case 0x0383: return "mibound"; 2103 case 0x0384: return "mdbase"; 2104 case 0x0385: return "mdbound"; 2105 case 0x03a0: return "pmpcfg3"; 2106 case 0x03b0: return "pmpaddr0"; 2107 case 0x03b1: return "pmpaddr1"; 2108 case 0x03b2: return "pmpaddr2"; 2109 case 0x03b3: return "pmpaddr3"; 2110 case 0x03b4: return "pmpaddr4"; 2111 case 0x03b5: return "pmpaddr5"; 2112 case 0x03b6: return "pmpaddr6"; 2113 case 0x03b7: return "pmpaddr7"; 2114 case 0x03b8: return "pmpaddr8"; 2115 case 0x03b9: return "pmpaddr9"; 2116 case 0x03ba: return "pmpaddr10"; 2117 case 0x03bb: return "pmpaddr11"; 2118 case 0x03bc: return "pmpaddr12"; 2119 case 0x03bd: return "pmpaddr14"; 2120 case 0x03be: return "pmpaddr13"; 2121 case 0x03bf: return "pmpaddr15"; 2122 case 0x0780: return "mtohost"; 2123 case 0x0781: return "mfromhost"; 2124 case 0x0782: return "mreset"; 2125 case 0x0783: return "mipi"; 2126 case 0x0784: return "miobase"; 2127 case 0x07a0: return "tselect"; 2128 case 0x07a1: return "tdata1"; 2129 case 0x07a2: return "tdata2"; 2130 case 0x07a3: return "tdata3"; 2131 case 0x07b0: return "dcsr"; 2132 case 0x07b1: return "dpc"; 2133 case 0x07b2: return "dscratch"; 2134 case 0x0b00: return "mcycle"; 2135 case 0x0b01: return "mtime"; 2136 case 0x0b02: return "minstret"; 2137 case 0x0b03: return "mhpmcounter3"; 2138 case 0x0b04: return "mhpmcounter4"; 2139 case 0x0b05: return "mhpmcounter5"; 2140 case 0x0b06: return "mhpmcounter6"; 2141 case 0x0b07: return "mhpmcounter7"; 2142 case 0x0b08: return "mhpmcounter8"; 2143 case 0x0b09: return "mhpmcounter9"; 2144 case 0x0b0a: return "mhpmcounter10"; 2145 case 0x0b0b: return "mhpmcounter11"; 2146 case 0x0b0c: return "mhpmcounter12"; 2147 case 0x0b0d: return "mhpmcounter13"; 2148 case 0x0b0e: return "mhpmcounter14"; 2149 case 0x0b0f: return "mhpmcounter15"; 2150 case 0x0b10: return "mhpmcounter16"; 2151 case 0x0b11: return "mhpmcounter17"; 2152 case 0x0b12: return "mhpmcounter18"; 2153 case 0x0b13: return "mhpmcounter19"; 2154 case 0x0b14: return "mhpmcounter20"; 2155 case 0x0b15: return "mhpmcounter21"; 2156 case 0x0b16: return "mhpmcounter22"; 2157 case 0x0b17: return "mhpmcounter23"; 2158 case 0x0b18: return "mhpmcounter24"; 2159 case 0x0b19: return "mhpmcounter25"; 2160 case 0x0b1a: return "mhpmcounter26"; 2161 case 0x0b1b: return "mhpmcounter27"; 2162 case 0x0b1c: return "mhpmcounter28"; 2163 case 0x0b1d: return "mhpmcounter29"; 2164 case 0x0b1e: return "mhpmcounter30"; 2165 case 0x0b1f: return "mhpmcounter31"; 2166 case 0x0b80: return "mcycleh"; 2167 case 0x0b81: return "mtimeh"; 2168 case 0x0b82: return "minstreth"; 2169 case 0x0b83: return "mhpmcounter3h"; 2170 case 0x0b84: return "mhpmcounter4h"; 2171 case 0x0b85: return "mhpmcounter5h"; 2172 case 0x0b86: return "mhpmcounter6h"; 2173 case 0x0b87: return "mhpmcounter7h"; 2174 case 0x0b88: return "mhpmcounter8h"; 2175 case 0x0b89: return "mhpmcounter9h"; 2176 case 0x0b8a: return "mhpmcounter10h"; 2177 case 0x0b8b: return "mhpmcounter11h"; 2178 case 0x0b8c: return "mhpmcounter12h"; 2179 case 0x0b8d: return "mhpmcounter13h"; 2180 case 0x0b8e: return "mhpmcounter14h"; 2181 case 0x0b8f: return "mhpmcounter15h"; 2182 case 0x0b90: return "mhpmcounter16h"; 2183 case 0x0b91: return "mhpmcounter17h"; 2184 case 0x0b92: return "mhpmcounter18h"; 2185 case 0x0b93: return "mhpmcounter19h"; 2186 case 0x0b94: return "mhpmcounter20h"; 2187 case 0x0b95: return "mhpmcounter21h"; 2188 case 0x0b96: return "mhpmcounter22h"; 2189 case 0x0b97: return "mhpmcounter23h"; 2190 case 0x0b98: return "mhpmcounter24h"; 2191 case 0x0b99: return "mhpmcounter25h"; 2192 case 0x0b9a: return "mhpmcounter26h"; 2193 case 0x0b9b: return "mhpmcounter27h"; 2194 case 0x0b9c: return "mhpmcounter28h"; 2195 case 0x0b9d: return "mhpmcounter29h"; 2196 case 0x0b9e: return "mhpmcounter30h"; 2197 case 0x0b9f: return "mhpmcounter31h"; 2198 case 0x0c00: return "cycle"; 2199 case 0x0c01: return "time"; 2200 case 0x0c02: return "instret"; 2201 case 0x0c20: return "vl"; 2202 case 0x0c21: return "vtype"; 2203 case 0x0c22: return "vlenb"; 2204 case 0x0c80: return "cycleh"; 2205 case 0x0c81: return "timeh"; 2206 case 0x0c82: return "instreth"; 2207 case 0x0d00: return "scycle"; 2208 case 0x0d01: return "stime"; 2209 case 0x0d02: return "sinstret"; 2210 case 0x0d80: return "scycleh"; 2211 case 0x0d81: return "stimeh"; 2212 case 0x0d82: return "sinstreth"; 2213 case 0x0e00: return "hcycle"; 2214 case 0x0e01: return "htime"; 2215 case 0x0e02: return "hinstret"; 2216 case 0x0e80: return "hcycleh"; 2217 case 0x0e81: return "htimeh"; 2218 case 0x0e82: return "hinstreth"; 2219 case 0x0f11: return "mvendorid"; 2220 case 0x0f12: return "marchid"; 2221 case 0x0f13: return "mimpid"; 2222 case 0x0f14: return "mhartid"; 2223 default: return NULL; 2224 } 2225 } 2226 2227 /* decode opcode */ 2228 2229 static void decode_inst_opcode(rv_decode *dec, rv_isa isa) 2230 { 2231 rv_inst inst = dec->inst; 2232 rv_opcode op = rv_op_illegal; 2233 switch ((inst >> 0) & 0b11) { 2234 case 0: 2235 switch ((inst >> 13) & 0b111) { 2236 case 0: op = rv_op_c_addi4spn; break; 2237 case 1: 2238 if (isa == rv128) { 2239 op = rv_op_c_lq; 2240 } else { 2241 op = rv_op_c_fld; 2242 } 2243 break; 2244 case 2: op = rv_op_c_lw; break; 2245 case 3: 2246 if (isa == rv32) { 2247 op = rv_op_c_flw; 2248 } else { 2249 op = rv_op_c_ld; 2250 } 2251 break; 2252 case 4: 2253 switch ((inst >> 10) & 0b111) { 2254 case 0: op = rv_op_c_lbu; break; 2255 case 1: 2256 if (((inst >> 6) & 1) == 0) { 2257 op = rv_op_c_lhu; 2258 } else { 2259 op = rv_op_c_lh; 2260 } 2261 break; 2262 case 2: op = rv_op_c_sb; break; 2263 case 3: 2264 if (((inst >> 6) & 1) == 0) { 2265 op = rv_op_c_sh; 2266 } 2267 break; 2268 } 2269 break; 2270 case 5: 2271 if (isa == rv128) { 2272 op = rv_op_c_sq; 2273 } else { 2274 op = rv_op_c_fsd; 2275 } 2276 break; 2277 case 6: op = rv_op_c_sw; break; 2278 case 7: 2279 if (isa == rv32) { 2280 op = rv_op_c_fsw; 2281 } else { 2282 op = rv_op_c_sd; 2283 } 2284 break; 2285 } 2286 break; 2287 case 1: 2288 switch ((inst >> 13) & 0b111) { 2289 case 0: 2290 switch ((inst >> 2) & 0b11111111111) { 2291 case 0: op = rv_op_c_nop; break; 2292 default: op = rv_op_c_addi; break; 2293 } 2294 break; 2295 case 1: 2296 if (isa == rv32) { 2297 op = rv_op_c_jal; 2298 } else { 2299 op = rv_op_c_addiw; 2300 } 2301 break; 2302 case 2: op = rv_op_c_li; break; 2303 case 3: 2304 switch ((inst >> 7) & 0b11111) { 2305 case 2: op = rv_op_c_addi16sp; break; 2306 default: op = rv_op_c_lui; break; 2307 } 2308 break; 2309 case 4: 2310 switch ((inst >> 10) & 0b11) { 2311 case 0: 2312 op = rv_op_c_srli; 2313 break; 2314 case 1: 2315 op = rv_op_c_srai; 2316 break; 2317 case 2: op = rv_op_c_andi; break; 2318 case 3: 2319 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) { 2320 case 0: op = rv_op_c_sub; break; 2321 case 1: op = rv_op_c_xor; break; 2322 case 2: op = rv_op_c_or; break; 2323 case 3: op = rv_op_c_and; break; 2324 case 4: op = rv_op_c_subw; break; 2325 case 5: op = rv_op_c_addw; break; 2326 case 6: op = rv_op_c_mul; break; 2327 case 7: 2328 switch ((inst >> 2) & 0b111) { 2329 case 0: op = rv_op_c_zext_b; break; 2330 case 1: op = rv_op_c_sext_b; break; 2331 case 2: op = rv_op_c_zext_h; break; 2332 case 3: op = rv_op_c_sext_h; break; 2333 case 4: op = rv_op_c_zext_w; break; 2334 case 5: op = rv_op_c_not; break; 2335 } 2336 break; 2337 } 2338 break; 2339 } 2340 break; 2341 case 5: op = rv_op_c_j; break; 2342 case 6: op = rv_op_c_beqz; break; 2343 case 7: op = rv_op_c_bnez; break; 2344 } 2345 break; 2346 case 2: 2347 switch ((inst >> 13) & 0b111) { 2348 case 0: 2349 op = rv_op_c_slli; 2350 break; 2351 case 1: 2352 if (isa == rv128) { 2353 op = rv_op_c_lqsp; 2354 } else { 2355 op = rv_op_c_fldsp; 2356 } 2357 break; 2358 case 2: op = rv_op_c_lwsp; break; 2359 case 3: 2360 if (isa == rv32) { 2361 op = rv_op_c_flwsp; 2362 } else { 2363 op = rv_op_c_ldsp; 2364 } 2365 break; 2366 case 4: 2367 switch ((inst >> 12) & 0b1) { 2368 case 0: 2369 switch ((inst >> 2) & 0b11111) { 2370 case 0: op = rv_op_c_jr; break; 2371 default: op = rv_op_c_mv; break; 2372 } 2373 break; 2374 case 1: 2375 switch ((inst >> 2) & 0b11111) { 2376 case 0: 2377 switch ((inst >> 7) & 0b11111) { 2378 case 0: op = rv_op_c_ebreak; break; 2379 default: op = rv_op_c_jalr; break; 2380 } 2381 break; 2382 default: op = rv_op_c_add; break; 2383 } 2384 break; 2385 } 2386 break; 2387 case 5: 2388 if (isa == rv128) { 2389 op = rv_op_c_sqsp; 2390 } else { 2391 op = rv_op_c_fsdsp; 2392 if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { 2393 switch ((inst >> 8) & 0b01111) { 2394 case 8: 2395 if (((inst >> 4) & 0b01111) >= 4) { 2396 op = rv_op_cm_push; 2397 } 2398 break; 2399 case 10: 2400 if (((inst >> 4) & 0b01111) >= 4) { 2401 op = rv_op_cm_pop; 2402 } 2403 break; 2404 case 12: 2405 if (((inst >> 4) & 0b01111) >= 4) { 2406 op = rv_op_cm_popretz; 2407 } 2408 break; 2409 case 14: 2410 if (((inst >> 4) & 0b01111) >= 4) { 2411 op = rv_op_cm_popret; 2412 } 2413 break; 2414 } 2415 } else { 2416 switch ((inst >> 10) & 0b011) { 2417 case 0: 2418 if (!dec->cfg->ext_zcmt) { 2419 break; 2420 } 2421 if (((inst >> 2) & 0xFF) >= 32) { 2422 op = rv_op_cm_jalt; 2423 } else { 2424 op = rv_op_cm_jt; 2425 } 2426 break; 2427 case 3: 2428 if (!dec->cfg->ext_zcmp) { 2429 break; 2430 } 2431 switch ((inst >> 5) & 0b011) { 2432 case 1: op = rv_op_cm_mvsa01; break; 2433 case 3: op = rv_op_cm_mva01s; break; 2434 } 2435 break; 2436 } 2437 } 2438 } 2439 break; 2440 case 6: op = rv_op_c_swsp; break; 2441 case 7: 2442 if (isa == rv32) { 2443 op = rv_op_c_fswsp; 2444 } else { 2445 op = rv_op_c_sdsp; 2446 } 2447 break; 2448 } 2449 break; 2450 case 3: 2451 switch ((inst >> 2) & 0b11111) { 2452 case 0: 2453 switch ((inst >> 12) & 0b111) { 2454 case 0: op = rv_op_lb; break; 2455 case 1: op = rv_op_lh; break; 2456 case 2: op = rv_op_lw; break; 2457 case 3: op = rv_op_ld; break; 2458 case 4: op = rv_op_lbu; break; 2459 case 5: op = rv_op_lhu; break; 2460 case 6: op = rv_op_lwu; break; 2461 case 7: op = rv_op_ldu; break; 2462 } 2463 break; 2464 case 1: 2465 switch ((inst >> 12) & 0b111) { 2466 case 0: 2467 switch ((inst >> 20) & 0b111111111111) { 2468 case 40: op = rv_op_vl1re8_v; break; 2469 case 552: op = rv_op_vl2re8_v; break; 2470 case 1576: op = rv_op_vl4re8_v; break; 2471 case 3624: op = rv_op_vl8re8_v; break; 2472 } 2473 switch ((inst >> 26) & 0b111) { 2474 case 0: 2475 switch ((inst >> 20) & 0b11111) { 2476 case 0: op = rv_op_vle8_v; break; 2477 case 11: op = rv_op_vlm_v; break; 2478 case 16: op = rv_op_vle8ff_v; break; 2479 } 2480 break; 2481 case 1: op = rv_op_vluxei8_v; break; 2482 case 2: op = rv_op_vlse8_v; break; 2483 case 3: op = rv_op_vloxei8_v; break; 2484 } 2485 break; 2486 case 1: op = rv_op_flh; break; 2487 case 2: op = rv_op_flw; break; 2488 case 3: op = rv_op_fld; break; 2489 case 4: op = rv_op_flq; break; 2490 case 5: 2491 switch ((inst >> 20) & 0b111111111111) { 2492 case 40: op = rv_op_vl1re16_v; break; 2493 case 552: op = rv_op_vl2re16_v; break; 2494 case 1576: op = rv_op_vl4re16_v; break; 2495 case 3624: op = rv_op_vl8re16_v; break; 2496 } 2497 switch ((inst >> 26) & 0b111) { 2498 case 0: 2499 switch ((inst >> 20) & 0b11111) { 2500 case 0: op = rv_op_vle16_v; break; 2501 case 16: op = rv_op_vle16ff_v; break; 2502 } 2503 break; 2504 case 1: op = rv_op_vluxei16_v; break; 2505 case 2: op = rv_op_vlse16_v; break; 2506 case 3: op = rv_op_vloxei16_v; break; 2507 } 2508 break; 2509 case 6: 2510 switch ((inst >> 20) & 0b111111111111) { 2511 case 40: op = rv_op_vl1re32_v; break; 2512 case 552: op = rv_op_vl2re32_v; break; 2513 case 1576: op = rv_op_vl4re32_v; break; 2514 case 3624: op = rv_op_vl8re32_v; break; 2515 } 2516 switch ((inst >> 26) & 0b111) { 2517 case 0: 2518 switch ((inst >> 20) & 0b11111) { 2519 case 0: op = rv_op_vle32_v; break; 2520 case 16: op = rv_op_vle32ff_v; break; 2521 } 2522 break; 2523 case 1: op = rv_op_vluxei32_v; break; 2524 case 2: op = rv_op_vlse32_v; break; 2525 case 3: op = rv_op_vloxei32_v; break; 2526 } 2527 break; 2528 case 7: 2529 switch ((inst >> 20) & 0b111111111111) { 2530 case 40: op = rv_op_vl1re64_v; break; 2531 case 552: op = rv_op_vl2re64_v; break; 2532 case 1576: op = rv_op_vl4re64_v; break; 2533 case 3624: op = rv_op_vl8re64_v; break; 2534 } 2535 switch ((inst >> 26) & 0b111) { 2536 case 0: 2537 switch ((inst >> 20) & 0b11111) { 2538 case 0: op = rv_op_vle64_v; break; 2539 case 16: op = rv_op_vle64ff_v; break; 2540 } 2541 break; 2542 case 1: op = rv_op_vluxei64_v; break; 2543 case 2: op = rv_op_vlse64_v; break; 2544 case 3: op = rv_op_vloxei64_v; break; 2545 } 2546 break; 2547 } 2548 break; 2549 case 3: 2550 switch ((inst >> 12) & 0b111) { 2551 case 0: op = rv_op_fence; break; 2552 case 1: op = rv_op_fence_i; break; 2553 case 2: op = rv_op_lq; break; 2554 } 2555 break; 2556 case 4: 2557 switch ((inst >> 12) & 0b111) { 2558 case 0: op = rv_op_addi; break; 2559 case 1: 2560 switch ((inst >> 27) & 0b11111) { 2561 case 0b00000: op = rv_op_slli; break; 2562 case 0b00001: 2563 switch ((inst >> 20) & 0b1111111) { 2564 case 0b0001111: op = rv_op_zip; break; 2565 } 2566 break; 2567 case 0b00010: 2568 switch ((inst >> 20) & 0b1111111) { 2569 case 0b0000000: op = rv_op_sha256sum0; break; 2570 case 0b0000001: op = rv_op_sha256sum1; break; 2571 case 0b0000010: op = rv_op_sha256sig0; break; 2572 case 0b0000011: op = rv_op_sha256sig1; break; 2573 case 0b0000100: op = rv_op_sha512sum0; break; 2574 case 0b0000101: op = rv_op_sha512sum1; break; 2575 case 0b0000110: op = rv_op_sha512sig0; break; 2576 case 0b0000111: op = rv_op_sha512sig1; break; 2577 case 0b0001000: op = rv_op_sm3p0; break; 2578 case 0b0001001: op = rv_op_sm3p1; break; 2579 } 2580 break; 2581 case 0b00101: op = rv_op_bseti; break; 2582 case 0b00110: 2583 switch ((inst >> 20) & 0b1111111) { 2584 case 0b0000000: op = rv_op_aes64im; break; 2585 default: 2586 if (((inst >> 24) & 0b0111) == 0b001) { 2587 op = rv_op_aes64ks1i; 2588 } 2589 break; 2590 } 2591 break; 2592 case 0b01001: op = rv_op_bclri; break; 2593 case 0b01101: op = rv_op_binvi; break; 2594 case 0b01100: 2595 switch ((inst >> 20) & 0b1111111) { 2596 case 0b0000000: op = rv_op_clz; break; 2597 case 0b0000001: op = rv_op_ctz; break; 2598 case 0b0000010: op = rv_op_cpop; break; 2599 /* 0b0000011 */ 2600 case 0b0000100: op = rv_op_sext_b; break; 2601 case 0b0000101: op = rv_op_sext_h; break; 2602 } 2603 break; 2604 } 2605 break; 2606 case 2: op = rv_op_slti; break; 2607 case 3: op = rv_op_sltiu; break; 2608 case 4: op = rv_op_xori; break; 2609 case 5: 2610 switch ((inst >> 27) & 0b11111) { 2611 case 0b00000: op = rv_op_srli; break; 2612 case 0b00001: 2613 switch ((inst >> 20) & 0b1111111) { 2614 case 0b0001111: op = rv_op_unzip; break; 2615 } 2616 break; 2617 case 0b00101: op = rv_op_orc_b; break; 2618 case 0b01000: op = rv_op_srai; break; 2619 case 0b01001: op = rv_op_bexti; break; 2620 case 0b01100: op = rv_op_rori; break; 2621 case 0b01101: 2622 switch ((inst >> 20) & 0b1111111) { 2623 case 0b0011000: op = rv_op_rev8; break; 2624 case 0b0111000: op = rv_op_rev8; break; 2625 case 0b0000111: op = rv_op_brev8; break; 2626 } 2627 break; 2628 } 2629 break; 2630 case 6: op = rv_op_ori; break; 2631 case 7: op = rv_op_andi; break; 2632 } 2633 break; 2634 case 5: op = rv_op_auipc; break; 2635 case 6: 2636 switch ((inst >> 12) & 0b111) { 2637 case 0: op = rv_op_addiw; break; 2638 case 1: 2639 switch ((inst >> 26) & 0b111111) { 2640 case 0: op = rv_op_slliw; break; 2641 case 2: op = rv_op_slli_uw; break; 2642 case 24: 2643 switch ((inst >> 20) & 0b11111) { 2644 case 0b00000: op = rv_op_clzw; break; 2645 case 0b00001: op = rv_op_ctzw; break; 2646 case 0b00010: op = rv_op_cpopw; break; 2647 } 2648 break; 2649 } 2650 break; 2651 case 5: 2652 switch ((inst >> 25) & 0b1111111) { 2653 case 0: op = rv_op_srliw; break; 2654 case 32: op = rv_op_sraiw; break; 2655 case 48: op = rv_op_roriw; break; 2656 } 2657 break; 2658 } 2659 break; 2660 case 8: 2661 switch ((inst >> 12) & 0b111) { 2662 case 0: op = rv_op_sb; break; 2663 case 1: op = rv_op_sh; break; 2664 case 2: op = rv_op_sw; break; 2665 case 3: op = rv_op_sd; break; 2666 case 4: op = rv_op_sq; break; 2667 } 2668 break; 2669 case 9: 2670 switch ((inst >> 12) & 0b111) { 2671 case 0: 2672 switch ((inst >> 20) & 0b111111111111) { 2673 case 40: op = rv_op_vs1r_v; break; 2674 case 552: op = rv_op_vs2r_v; break; 2675 case 1576: op = rv_op_vs4r_v; break; 2676 case 3624: op = rv_op_vs8r_v; break; 2677 } 2678 switch ((inst >> 26) & 0b111) { 2679 case 0: 2680 switch ((inst >> 20) & 0b11111) { 2681 case 0: op = rv_op_vse8_v; break; 2682 case 11: op = rv_op_vsm_v; break; 2683 } 2684 break; 2685 case 1: op = rv_op_vsuxei8_v; break; 2686 case 2: op = rv_op_vsse8_v; break; 2687 case 3: op = rv_op_vsoxei8_v; break; 2688 } 2689 break; 2690 case 1: op = rv_op_fsh; break; 2691 case 2: op = rv_op_fsw; break; 2692 case 3: op = rv_op_fsd; break; 2693 case 4: op = rv_op_fsq; break; 2694 case 5: 2695 switch ((inst >> 26) & 0b111) { 2696 case 0: 2697 switch ((inst >> 20) & 0b11111) { 2698 case 0: op = rv_op_vse16_v; break; 2699 } 2700 break; 2701 case 1: op = rv_op_vsuxei16_v; break; 2702 case 2: op = rv_op_vsse16_v; break; 2703 case 3: op = rv_op_vsoxei16_v; break; 2704 } 2705 break; 2706 case 6: 2707 switch ((inst >> 26) & 0b111) { 2708 case 0: 2709 switch ((inst >> 20) & 0b11111) { 2710 case 0: op = rv_op_vse32_v; break; 2711 } 2712 break; 2713 case 1: op = rv_op_vsuxei32_v; break; 2714 case 2: op = rv_op_vsse32_v; break; 2715 case 3: op = rv_op_vsoxei32_v; break; 2716 } 2717 break; 2718 case 7: 2719 switch ((inst >> 26) & 0b111) { 2720 case 0: 2721 switch ((inst >> 20) & 0b11111) { 2722 case 0: op = rv_op_vse64_v; break; 2723 } 2724 break; 2725 case 1: op = rv_op_vsuxei64_v; break; 2726 case 2: op = rv_op_vsse64_v; break; 2727 case 3: op = rv_op_vsoxei64_v; break; 2728 } 2729 break; 2730 } 2731 break; 2732 case 11: 2733 switch (((inst >> 24) & 0b11111000) | 2734 ((inst >> 12) & 0b00000111)) { 2735 case 2: op = rv_op_amoadd_w; break; 2736 case 3: op = rv_op_amoadd_d; break; 2737 case 4: op = rv_op_amoadd_q; break; 2738 case 10: op = rv_op_amoswap_w; break; 2739 case 11: op = rv_op_amoswap_d; break; 2740 case 12: op = rv_op_amoswap_q; break; 2741 case 18: 2742 switch ((inst >> 20) & 0b11111) { 2743 case 0: op = rv_op_lr_w; break; 2744 } 2745 break; 2746 case 19: 2747 switch ((inst >> 20) & 0b11111) { 2748 case 0: op = rv_op_lr_d; break; 2749 } 2750 break; 2751 case 20: 2752 switch ((inst >> 20) & 0b11111) { 2753 case 0: op = rv_op_lr_q; break; 2754 } 2755 break; 2756 case 26: op = rv_op_sc_w; break; 2757 case 27: op = rv_op_sc_d; break; 2758 case 28: op = rv_op_sc_q; break; 2759 case 34: op = rv_op_amoxor_w; break; 2760 case 35: op = rv_op_amoxor_d; break; 2761 case 36: op = rv_op_amoxor_q; break; 2762 case 66: op = rv_op_amoor_w; break; 2763 case 67: op = rv_op_amoor_d; break; 2764 case 68: op = rv_op_amoor_q; break; 2765 case 98: op = rv_op_amoand_w; break; 2766 case 99: op = rv_op_amoand_d; break; 2767 case 100: op = rv_op_amoand_q; break; 2768 case 130: op = rv_op_amomin_w; break; 2769 case 131: op = rv_op_amomin_d; break; 2770 case 132: op = rv_op_amomin_q; break; 2771 case 162: op = rv_op_amomax_w; break; 2772 case 163: op = rv_op_amomax_d; break; 2773 case 164: op = rv_op_amomax_q; break; 2774 case 194: op = rv_op_amominu_w; break; 2775 case 195: op = rv_op_amominu_d; break; 2776 case 196: op = rv_op_amominu_q; break; 2777 case 226: op = rv_op_amomaxu_w; break; 2778 case 227: op = rv_op_amomaxu_d; break; 2779 case 228: op = rv_op_amomaxu_q; break; 2780 } 2781 break; 2782 case 12: 2783 switch (((inst >> 22) & 0b1111111000) | 2784 ((inst >> 12) & 0b0000000111)) { 2785 case 0: op = rv_op_add; break; 2786 case 1: op = rv_op_sll; break; 2787 case 2: op = rv_op_slt; break; 2788 case 3: op = rv_op_sltu; break; 2789 case 4: op = rv_op_xor; break; 2790 case 5: op = rv_op_srl; break; 2791 case 6: op = rv_op_or; break; 2792 case 7: op = rv_op_and; break; 2793 case 8: op = rv_op_mul; break; 2794 case 9: op = rv_op_mulh; break; 2795 case 10: op = rv_op_mulhsu; break; 2796 case 11: op = rv_op_mulhu; break; 2797 case 12: op = rv_op_div; break; 2798 case 13: op = rv_op_divu; break; 2799 case 14: op = rv_op_rem; break; 2800 case 15: op = rv_op_remu; break; 2801 case 36: 2802 switch ((inst >> 20) & 0b11111) { 2803 case 0: op = rv_op_zext_h; break; 2804 default: op = rv_op_pack; break; 2805 } 2806 break; 2807 case 39: op = rv_op_packh; break; 2808 2809 case 41: op = rv_op_clmul; break; 2810 case 42: op = rv_op_clmulr; break; 2811 case 43: op = rv_op_clmulh; break; 2812 case 44: op = rv_op_min; break; 2813 case 45: op = rv_op_minu; break; 2814 case 46: op = rv_op_max; break; 2815 case 47: op = rv_op_maxu; break; 2816 case 075: op = rv_op_czero_eqz; break; 2817 case 077: op = rv_op_czero_nez; break; 2818 case 130: op = rv_op_sh1add; break; 2819 case 132: op = rv_op_sh2add; break; 2820 case 134: op = rv_op_sh3add; break; 2821 case 161: op = rv_op_bset; break; 2822 case 162: op = rv_op_xperm4; break; 2823 case 164: op = rv_op_xperm8; break; 2824 case 200: op = rv_op_aes64es; break; 2825 case 216: op = rv_op_aes64esm; break; 2826 case 232: op = rv_op_aes64ds; break; 2827 case 248: op = rv_op_aes64dsm; break; 2828 case 256: op = rv_op_sub; break; 2829 case 260: op = rv_op_xnor; break; 2830 case 261: op = rv_op_sra; break; 2831 case 262: op = rv_op_orn; break; 2832 case 263: op = rv_op_andn; break; 2833 case 289: op = rv_op_bclr; break; 2834 case 293: op = rv_op_bext; break; 2835 case 320: op = rv_op_sha512sum0r; break; 2836 case 328: op = rv_op_sha512sum1r; break; 2837 case 336: op = rv_op_sha512sig0l; break; 2838 case 344: op = rv_op_sha512sig1l; break; 2839 case 368: op = rv_op_sha512sig0h; break; 2840 case 376: op = rv_op_sha512sig1h; break; 2841 case 385: op = rv_op_rol; break; 2842 case 389: op = rv_op_ror; break; 2843 case 417: op = rv_op_binv; break; 2844 case 504: op = rv_op_aes64ks2; break; 2845 } 2846 switch ((inst >> 25) & 0b0011111) { 2847 case 17: op = rv_op_aes32esi; break; 2848 case 19: op = rv_op_aes32esmi; break; 2849 case 21: op = rv_op_aes32dsi; break; 2850 case 23: op = rv_op_aes32dsmi; break; 2851 case 24: op = rv_op_sm4ed; break; 2852 case 26: op = rv_op_sm4ks; break; 2853 } 2854 break; 2855 case 13: op = rv_op_lui; break; 2856 case 14: 2857 switch (((inst >> 22) & 0b1111111000) | 2858 ((inst >> 12) & 0b0000000111)) { 2859 case 0: op = rv_op_addw; break; 2860 case 1: op = rv_op_sllw; break; 2861 case 5: op = rv_op_srlw; break; 2862 case 8: op = rv_op_mulw; break; 2863 case 12: op = rv_op_divw; break; 2864 case 13: op = rv_op_divuw; break; 2865 case 14: op = rv_op_remw; break; 2866 case 15: op = rv_op_remuw; break; 2867 case 32: op = rv_op_add_uw; break; 2868 case 36: 2869 switch ((inst >> 20) & 0b11111) { 2870 case 0: op = rv_op_zext_h; break; 2871 default: op = rv_op_packw; break; 2872 } 2873 break; 2874 case 130: op = rv_op_sh1add_uw; break; 2875 case 132: op = rv_op_sh2add_uw; break; 2876 case 134: op = rv_op_sh3add_uw; break; 2877 case 256: op = rv_op_subw; break; 2878 case 261: op = rv_op_sraw; break; 2879 case 385: op = rv_op_rolw; break; 2880 case 389: op = rv_op_rorw; break; 2881 } 2882 break; 2883 case 16: 2884 switch ((inst >> 25) & 0b11) { 2885 case 0: op = rv_op_fmadd_s; break; 2886 case 1: op = rv_op_fmadd_d; break; 2887 case 3: op = rv_op_fmadd_q; break; 2888 } 2889 break; 2890 case 17: 2891 switch ((inst >> 25) & 0b11) { 2892 case 0: op = rv_op_fmsub_s; break; 2893 case 1: op = rv_op_fmsub_d; break; 2894 case 3: op = rv_op_fmsub_q; break; 2895 } 2896 break; 2897 case 18: 2898 switch ((inst >> 25) & 0b11) { 2899 case 0: op = rv_op_fnmsub_s; break; 2900 case 1: op = rv_op_fnmsub_d; break; 2901 case 3: op = rv_op_fnmsub_q; break; 2902 } 2903 break; 2904 case 19: 2905 switch ((inst >> 25) & 0b11) { 2906 case 0: op = rv_op_fnmadd_s; break; 2907 case 1: op = rv_op_fnmadd_d; break; 2908 case 3: op = rv_op_fnmadd_q; break; 2909 } 2910 break; 2911 case 20: 2912 switch ((inst >> 25) & 0b1111111) { 2913 case 0: op = rv_op_fadd_s; break; 2914 case 1: op = rv_op_fadd_d; break; 2915 case 3: op = rv_op_fadd_q; break; 2916 case 4: op = rv_op_fsub_s; break; 2917 case 5: op = rv_op_fsub_d; break; 2918 case 7: op = rv_op_fsub_q; break; 2919 case 8: op = rv_op_fmul_s; break; 2920 case 9: op = rv_op_fmul_d; break; 2921 case 11: op = rv_op_fmul_q; break; 2922 case 12: op = rv_op_fdiv_s; break; 2923 case 13: op = rv_op_fdiv_d; break; 2924 case 15: op = rv_op_fdiv_q; break; 2925 case 16: 2926 switch ((inst >> 12) & 0b111) { 2927 case 0: op = rv_op_fsgnj_s; break; 2928 case 1: op = rv_op_fsgnjn_s; break; 2929 case 2: op = rv_op_fsgnjx_s; break; 2930 } 2931 break; 2932 case 17: 2933 switch ((inst >> 12) & 0b111) { 2934 case 0: op = rv_op_fsgnj_d; break; 2935 case 1: op = rv_op_fsgnjn_d; break; 2936 case 2: op = rv_op_fsgnjx_d; break; 2937 } 2938 break; 2939 case 19: 2940 switch ((inst >> 12) & 0b111) { 2941 case 0: op = rv_op_fsgnj_q; break; 2942 case 1: op = rv_op_fsgnjn_q; break; 2943 case 2: op = rv_op_fsgnjx_q; break; 2944 } 2945 break; 2946 case 20: 2947 switch ((inst >> 12) & 0b111) { 2948 case 0: op = rv_op_fmin_s; break; 2949 case 1: op = rv_op_fmax_s; break; 2950 case 2: op = rv_op_fminm_s; break; 2951 case 3: op = rv_op_fmaxm_s; break; 2952 } 2953 break; 2954 case 21: 2955 switch ((inst >> 12) & 0b111) { 2956 case 0: op = rv_op_fmin_d; break; 2957 case 1: op = rv_op_fmax_d; break; 2958 case 2: op = rv_op_fminm_d; break; 2959 case 3: op = rv_op_fmaxm_d; break; 2960 } 2961 break; 2962 case 22: 2963 switch (((inst >> 12) & 0b111)) { 2964 case 2: op = rv_op_fminm_h; break; 2965 case 3: op = rv_op_fmaxm_h; break; 2966 } 2967 break; 2968 case 23: 2969 switch ((inst >> 12) & 0b111) { 2970 case 0: op = rv_op_fmin_q; break; 2971 case 1: op = rv_op_fmax_q; break; 2972 case 2: op = rv_op_fminm_q; break; 2973 case 3: op = rv_op_fmaxm_q; break; 2974 } 2975 break; 2976 case 32: 2977 switch ((inst >> 20) & 0b11111) { 2978 case 1: op = rv_op_fcvt_s_d; break; 2979 case 3: op = rv_op_fcvt_s_q; break; 2980 case 4: op = rv_op_fround_s; break; 2981 case 5: op = rv_op_froundnx_s; break; 2982 case 6: op = rv_op_fcvt_s_bf16; break; 2983 } 2984 break; 2985 case 33: 2986 switch ((inst >> 20) & 0b11111) { 2987 case 0: op = rv_op_fcvt_d_s; break; 2988 case 3: op = rv_op_fcvt_d_q; break; 2989 case 4: op = rv_op_fround_d; break; 2990 case 5: op = rv_op_froundnx_d; break; 2991 } 2992 break; 2993 case 34: 2994 switch (((inst >> 20) & 0b11111)) { 2995 case 4: op = rv_op_fround_h; break; 2996 case 5: op = rv_op_froundnx_h; break; 2997 case 8: op = rv_op_fcvt_bf16_s; break; 2998 } 2999 break; 3000 case 35: 3001 switch ((inst >> 20) & 0b11111) { 3002 case 0: op = rv_op_fcvt_q_s; break; 3003 case 1: op = rv_op_fcvt_q_d; break; 3004 case 4: op = rv_op_fround_q; break; 3005 case 5: op = rv_op_froundnx_q; break; 3006 } 3007 break; 3008 case 44: 3009 switch ((inst >> 20) & 0b11111) { 3010 case 0: op = rv_op_fsqrt_s; break; 3011 } 3012 break; 3013 case 45: 3014 switch ((inst >> 20) & 0b11111) { 3015 case 0: op = rv_op_fsqrt_d; break; 3016 } 3017 break; 3018 case 47: 3019 switch ((inst >> 20) & 0b11111) { 3020 case 0: op = rv_op_fsqrt_q; break; 3021 } 3022 break; 3023 case 80: 3024 switch ((inst >> 12) & 0b111) { 3025 case 0: op = rv_op_fle_s; break; 3026 case 1: op = rv_op_flt_s; break; 3027 case 2: op = rv_op_feq_s; break; 3028 case 4: op = rv_op_fleq_s; break; 3029 case 5: op = rv_op_fltq_s; break; 3030 } 3031 break; 3032 case 81: 3033 switch ((inst >> 12) & 0b111) { 3034 case 0: op = rv_op_fle_d; break; 3035 case 1: op = rv_op_flt_d; break; 3036 case 2: op = rv_op_feq_d; break; 3037 case 4: op = rv_op_fleq_d; break; 3038 case 5: op = rv_op_fltq_d; break; 3039 } 3040 break; 3041 case 82: 3042 switch (((inst >> 12) & 0b111)) { 3043 case 4: op = rv_op_fleq_h; break; 3044 case 5: op = rv_op_fltq_h; break; 3045 } 3046 break; 3047 case 83: 3048 switch ((inst >> 12) & 0b111) { 3049 case 0: op = rv_op_fle_q; break; 3050 case 1: op = rv_op_flt_q; break; 3051 case 2: op = rv_op_feq_q; break; 3052 case 4: op = rv_op_fleq_q; break; 3053 case 5: op = rv_op_fltq_q; break; 3054 } 3055 break; 3056 case 89: 3057 switch (((inst >> 12) & 0b111)) { 3058 case 0: op = rv_op_fmvp_d_x; break; 3059 } 3060 break; 3061 case 91: 3062 switch (((inst >> 12) & 0b111)) { 3063 case 0: op = rv_op_fmvp_q_x; break; 3064 } 3065 break; 3066 case 96: 3067 switch ((inst >> 20) & 0b11111) { 3068 case 0: op = rv_op_fcvt_w_s; break; 3069 case 1: op = rv_op_fcvt_wu_s; break; 3070 case 2: op = rv_op_fcvt_l_s; break; 3071 case 3: op = rv_op_fcvt_lu_s; break; 3072 } 3073 break; 3074 case 97: 3075 switch ((inst >> 20) & 0b11111) { 3076 case 0: op = rv_op_fcvt_w_d; break; 3077 case 1: op = rv_op_fcvt_wu_d; break; 3078 case 2: op = rv_op_fcvt_l_d; break; 3079 case 3: op = rv_op_fcvt_lu_d; break; 3080 case 8: op = rv_op_fcvtmod_w_d; break; 3081 } 3082 break; 3083 case 99: 3084 switch ((inst >> 20) & 0b11111) { 3085 case 0: op = rv_op_fcvt_w_q; break; 3086 case 1: op = rv_op_fcvt_wu_q; break; 3087 case 2: op = rv_op_fcvt_l_q; break; 3088 case 3: op = rv_op_fcvt_lu_q; break; 3089 } 3090 break; 3091 case 104: 3092 switch ((inst >> 20) & 0b11111) { 3093 case 0: op = rv_op_fcvt_s_w; break; 3094 case 1: op = rv_op_fcvt_s_wu; break; 3095 case 2: op = rv_op_fcvt_s_l; break; 3096 case 3: op = rv_op_fcvt_s_lu; break; 3097 } 3098 break; 3099 case 105: 3100 switch ((inst >> 20) & 0b11111) { 3101 case 0: op = rv_op_fcvt_d_w; break; 3102 case 1: op = rv_op_fcvt_d_wu; break; 3103 case 2: op = rv_op_fcvt_d_l; break; 3104 case 3: op = rv_op_fcvt_d_lu; break; 3105 } 3106 break; 3107 case 107: 3108 switch ((inst >> 20) & 0b11111) { 3109 case 0: op = rv_op_fcvt_q_w; break; 3110 case 1: op = rv_op_fcvt_q_wu; break; 3111 case 2: op = rv_op_fcvt_q_l; break; 3112 case 3: op = rv_op_fcvt_q_lu; break; 3113 } 3114 break; 3115 case 112: 3116 switch (((inst >> 17) & 0b11111000) | 3117 ((inst >> 12) & 0b00000111)) { 3118 case 0: op = rv_op_fmv_x_s; break; 3119 case 1: op = rv_op_fclass_s; break; 3120 } 3121 break; 3122 case 113: 3123 switch (((inst >> 17) & 0b11111000) | 3124 ((inst >> 12) & 0b00000111)) { 3125 case 0: op = rv_op_fmv_x_d; break; 3126 case 1: op = rv_op_fclass_d; break; 3127 case 8: op = rv_op_fmvh_x_d; break; 3128 } 3129 break; 3130 case 114: 3131 switch (((inst >> 17) & 0b11111000) | 3132 ((inst >> 12) & 0b00000111)) { 3133 case 0: op = rv_op_fmv_x_h; break; 3134 } 3135 break; 3136 case 115: 3137 switch (((inst >> 17) & 0b11111000) | 3138 ((inst >> 12) & 0b00000111)) { 3139 case 0: op = rv_op_fmv_x_q; break; 3140 case 1: op = rv_op_fclass_q; break; 3141 case 8: op = rv_op_fmvh_x_q; break; 3142 } 3143 break; 3144 case 120: 3145 switch (((inst >> 17) & 0b11111000) | 3146 ((inst >> 12) & 0b00000111)) { 3147 case 0: op = rv_op_fmv_s_x; break; 3148 case 8: op = rv_op_fli_s; break; 3149 } 3150 break; 3151 case 121: 3152 switch (((inst >> 17) & 0b11111000) | 3153 ((inst >> 12) & 0b00000111)) { 3154 case 0: op = rv_op_fmv_d_x; break; 3155 case 8: op = rv_op_fli_d; break; 3156 } 3157 break; 3158 case 122: 3159 switch (((inst >> 17) & 0b11111000) | 3160 ((inst >> 12) & 0b00000111)) { 3161 case 0: op = rv_op_fmv_h_x; break; 3162 case 8: op = rv_op_fli_h; break; 3163 } 3164 break; 3165 case 123: 3166 switch (((inst >> 17) & 0b11111000) | 3167 ((inst >> 12) & 0b00000111)) { 3168 case 0: op = rv_op_fmv_q_x; break; 3169 case 8: op = rv_op_fli_q; break; 3170 } 3171 break; 3172 } 3173 break; 3174 case 21: 3175 switch ((inst >> 12) & 0b111) { 3176 case 0: 3177 switch ((inst >> 26) & 0b111111) { 3178 case 0: op = rv_op_vadd_vv; break; 3179 case 2: op = rv_op_vsub_vv; break; 3180 case 4: op = rv_op_vminu_vv; break; 3181 case 5: op = rv_op_vmin_vv; break; 3182 case 6: op = rv_op_vmaxu_vv; break; 3183 case 7: op = rv_op_vmax_vv; break; 3184 case 9: op = rv_op_vand_vv; break; 3185 case 10: op = rv_op_vor_vv; break; 3186 case 11: op = rv_op_vxor_vv; break; 3187 case 12: op = rv_op_vrgather_vv; break; 3188 case 14: op = rv_op_vrgatherei16_vv; break; 3189 case 16: 3190 if (((inst >> 25) & 1) == 0) { 3191 op = rv_op_vadc_vvm; 3192 } 3193 break; 3194 case 17: op = rv_op_vmadc_vvm; break; 3195 case 18: 3196 if (((inst >> 25) & 1) == 0) { 3197 op = rv_op_vsbc_vvm; 3198 } 3199 break; 3200 case 19: op = rv_op_vmsbc_vvm; break; 3201 case 23: 3202 if (((inst >> 20) & 0b111111) == 32) 3203 op = rv_op_vmv_v_v; 3204 else if (((inst >> 25) & 1) == 0) 3205 op = rv_op_vmerge_vvm; 3206 break; 3207 case 24: op = rv_op_vmseq_vv; break; 3208 case 25: op = rv_op_vmsne_vv; break; 3209 case 26: op = rv_op_vmsltu_vv; break; 3210 case 27: op = rv_op_vmslt_vv; break; 3211 case 28: op = rv_op_vmsleu_vv; break; 3212 case 29: op = rv_op_vmsle_vv; break; 3213 case 32: op = rv_op_vsaddu_vv; break; 3214 case 33: op = rv_op_vsadd_vv; break; 3215 case 34: op = rv_op_vssubu_vv; break; 3216 case 35: op = rv_op_vssub_vv; break; 3217 case 37: op = rv_op_vsll_vv; break; 3218 case 39: op = rv_op_vsmul_vv; break; 3219 case 40: op = rv_op_vsrl_vv; break; 3220 case 41: op = rv_op_vsra_vv; break; 3221 case 42: op = rv_op_vssrl_vv; break; 3222 case 43: op = rv_op_vssra_vv; break; 3223 case 44: op = rv_op_vnsrl_wv; break; 3224 case 45: op = rv_op_vnsra_wv; break; 3225 case 46: op = rv_op_vnclipu_wv; break; 3226 case 47: op = rv_op_vnclip_wv; break; 3227 case 48: op = rv_op_vwredsumu_vs; break; 3228 case 49: op = rv_op_vwredsum_vs; break; 3229 } 3230 break; 3231 case 1: 3232 switch ((inst >> 26) & 0b111111) { 3233 case 0: op = rv_op_vfadd_vv; break; 3234 case 1: op = rv_op_vfredusum_vs; break; 3235 case 2: op = rv_op_vfsub_vv; break; 3236 case 3: op = rv_op_vfredosum_vs; break; 3237 case 4: op = rv_op_vfmin_vv; break; 3238 case 5: op = rv_op_vfredmin_vs; break; 3239 case 6: op = rv_op_vfmax_vv; break; 3240 case 7: op = rv_op_vfredmax_vs; break; 3241 case 8: op = rv_op_vfsgnj_vv; break; 3242 case 9: op = rv_op_vfsgnjn_vv; break; 3243 case 10: op = rv_op_vfsgnjx_vv; break; 3244 case 16: 3245 switch ((inst >> 15) & 0b11111) { 3246 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break; 3247 } 3248 break; 3249 case 18: 3250 switch ((inst >> 15) & 0b11111) { 3251 case 0: op = rv_op_vfcvt_xu_f_v; break; 3252 case 1: op = rv_op_vfcvt_x_f_v; break; 3253 case 2: op = rv_op_vfcvt_f_xu_v; break; 3254 case 3: op = rv_op_vfcvt_f_x_v; break; 3255 case 6: op = rv_op_vfcvt_rtz_xu_f_v; break; 3256 case 7: op = rv_op_vfcvt_rtz_x_f_v; break; 3257 case 8: op = rv_op_vfwcvt_xu_f_v; break; 3258 case 9: op = rv_op_vfwcvt_x_f_v; break; 3259 case 10: op = rv_op_vfwcvt_f_xu_v; break; 3260 case 11: op = rv_op_vfwcvt_f_x_v; break; 3261 case 12: op = rv_op_vfwcvt_f_f_v; break; 3262 case 13: op = rv_op_vfwcvtbf16_f_f_v; break; 3263 case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break; 3264 case 15: op = rv_op_vfwcvt_rtz_x_f_v; break; 3265 case 16: op = rv_op_vfncvt_xu_f_w; break; 3266 case 17: op = rv_op_vfncvt_x_f_w; break; 3267 case 18: op = rv_op_vfncvt_f_xu_w; break; 3268 case 19: op = rv_op_vfncvt_f_x_w; break; 3269 case 20: op = rv_op_vfncvt_f_f_w; break; 3270 case 21: op = rv_op_vfncvt_rod_f_f_w; break; 3271 case 22: op = rv_op_vfncvt_rtz_xu_f_w; break; 3272 case 23: op = rv_op_vfncvt_rtz_x_f_w; break; 3273 case 29: op = rv_op_vfncvtbf16_f_f_w; break; 3274 } 3275 break; 3276 case 19: 3277 switch ((inst >> 15) & 0b11111) { 3278 case 0: op = rv_op_vfsqrt_v; break; 3279 case 4: op = rv_op_vfrsqrt7_v; break; 3280 case 5: op = rv_op_vfrec7_v; break; 3281 case 16: op = rv_op_vfclass_v; break; 3282 } 3283 break; 3284 case 24: op = rv_op_vmfeq_vv; break; 3285 case 25: op = rv_op_vmfle_vv; break; 3286 case 27: op = rv_op_vmflt_vv; break; 3287 case 28: op = rv_op_vmfne_vv; break; 3288 case 32: op = rv_op_vfdiv_vv; break; 3289 case 36: op = rv_op_vfmul_vv; break; 3290 case 40: op = rv_op_vfmadd_vv; break; 3291 case 41: op = rv_op_vfnmadd_vv; break; 3292 case 42: op = rv_op_vfmsub_vv; break; 3293 case 43: op = rv_op_vfnmsub_vv; break; 3294 case 44: op = rv_op_vfmacc_vv; break; 3295 case 45: op = rv_op_vfnmacc_vv; break; 3296 case 46: op = rv_op_vfmsac_vv; break; 3297 case 47: op = rv_op_vfnmsac_vv; break; 3298 case 48: op = rv_op_vfwadd_vv; break; 3299 case 49: op = rv_op_vfwredusum_vs; break; 3300 case 50: op = rv_op_vfwsub_vv; break; 3301 case 51: op = rv_op_vfwredosum_vs; break; 3302 case 52: op = rv_op_vfwadd_wv; break; 3303 case 54: op = rv_op_vfwsub_wv; break; 3304 case 56: op = rv_op_vfwmul_vv; break; 3305 case 59: op = rv_op_vfwmaccbf16_vv; break; 3306 case 60: op = rv_op_vfwmacc_vv; break; 3307 case 61: op = rv_op_vfwnmacc_vv; break; 3308 case 62: op = rv_op_vfwmsac_vv; break; 3309 case 63: op = rv_op_vfwnmsac_vv; break; 3310 } 3311 break; 3312 case 2: 3313 switch ((inst >> 26) & 0b111111) { 3314 case 0: op = rv_op_vredsum_vs; break; 3315 case 1: op = rv_op_vredand_vs; break; 3316 case 2: op = rv_op_vredor_vs; break; 3317 case 3: op = rv_op_vredxor_vs; break; 3318 case 4: op = rv_op_vredminu_vs; break; 3319 case 5: op = rv_op_vredmin_vs; break; 3320 case 6: op = rv_op_vredmaxu_vs; break; 3321 case 7: op = rv_op_vredmax_vs; break; 3322 case 8: op = rv_op_vaaddu_vv; break; 3323 case 9: op = rv_op_vaadd_vv; break; 3324 case 10: op = rv_op_vasubu_vv; break; 3325 case 11: op = rv_op_vasub_vv; break; 3326 case 16: 3327 switch ((inst >> 15) & 0b11111) { 3328 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break; 3329 case 16: op = rv_op_vcpop_m; break; 3330 case 17: op = rv_op_vfirst_m; break; 3331 } 3332 break; 3333 case 18: 3334 switch ((inst >> 15) & 0b11111) { 3335 case 2: op = rv_op_vzext_vf8; break; 3336 case 3: op = rv_op_vsext_vf8; break; 3337 case 4: op = rv_op_vzext_vf4; break; 3338 case 5: op = rv_op_vsext_vf4; break; 3339 case 6: op = rv_op_vzext_vf2; break; 3340 case 7: op = rv_op_vsext_vf2; break; 3341 } 3342 break; 3343 case 20: 3344 switch ((inst >> 15) & 0b11111) { 3345 case 1: op = rv_op_vmsbf_m; break; 3346 case 2: op = rv_op_vmsof_m; break; 3347 case 3: op = rv_op_vmsif_m; break; 3348 case 16: op = rv_op_viota_m; break; 3349 case 17: 3350 if (((inst >> 20) & 0b11111) == 0) { 3351 op = rv_op_vid_v; 3352 } 3353 break; 3354 } 3355 break; 3356 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break; 3357 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break; 3358 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break; 3359 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break; 3360 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break; 3361 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break; 3362 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break; 3363 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break; 3364 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break; 3365 case 32: op = rv_op_vdivu_vv; break; 3366 case 33: op = rv_op_vdiv_vv; break; 3367 case 34: op = rv_op_vremu_vv; break; 3368 case 35: op = rv_op_vrem_vv; break; 3369 case 36: op = rv_op_vmulhu_vv; break; 3370 case 37: op = rv_op_vmul_vv; break; 3371 case 38: op = rv_op_vmulhsu_vv; break; 3372 case 39: op = rv_op_vmulh_vv; break; 3373 case 41: op = rv_op_vmadd_vv; break; 3374 case 43: op = rv_op_vnmsub_vv; break; 3375 case 45: op = rv_op_vmacc_vv; break; 3376 case 47: op = rv_op_vnmsac_vv; break; 3377 case 48: op = rv_op_vwaddu_vv; break; 3378 case 49: op = rv_op_vwadd_vv; break; 3379 case 50: op = rv_op_vwsubu_vv; break; 3380 case 51: op = rv_op_vwsub_vv; break; 3381 case 52: op = rv_op_vwaddu_wv; break; 3382 case 53: op = rv_op_vwadd_wv; break; 3383 case 54: op = rv_op_vwsubu_wv; break; 3384 case 55: op = rv_op_vwsub_wv; break; 3385 case 56: op = rv_op_vwmulu_vv; break; 3386 case 58: op = rv_op_vwmulsu_vv; break; 3387 case 59: op = rv_op_vwmul_vv; break; 3388 case 60: op = rv_op_vwmaccu_vv; break; 3389 case 61: op = rv_op_vwmacc_vv; break; 3390 case 63: op = rv_op_vwmaccsu_vv; break; 3391 } 3392 break; 3393 case 3: 3394 switch ((inst >> 26) & 0b111111) { 3395 case 0: op = rv_op_vadd_vi; break; 3396 case 3: op = rv_op_vrsub_vi; break; 3397 case 9: op = rv_op_vand_vi; break; 3398 case 10: op = rv_op_vor_vi; break; 3399 case 11: op = rv_op_vxor_vi; break; 3400 case 12: op = rv_op_vrgather_vi; break; 3401 case 14: op = rv_op_vslideup_vi; break; 3402 case 15: op = rv_op_vslidedown_vi; break; 3403 case 16: 3404 if (((inst >> 25) & 1) == 0) { 3405 op = rv_op_vadc_vim; 3406 } 3407 break; 3408 case 17: op = rv_op_vmadc_vim; break; 3409 case 23: 3410 if (((inst >> 20) & 0b111111) == 32) 3411 op = rv_op_vmv_v_i; 3412 else if (((inst >> 25) & 1) == 0) 3413 op = rv_op_vmerge_vim; 3414 break; 3415 case 24: op = rv_op_vmseq_vi; break; 3416 case 25: op = rv_op_vmsne_vi; break; 3417 case 28: op = rv_op_vmsleu_vi; break; 3418 case 29: op = rv_op_vmsle_vi; break; 3419 case 30: op = rv_op_vmsgtu_vi; break; 3420 case 31: op = rv_op_vmsgt_vi; break; 3421 case 32: op = rv_op_vsaddu_vi; break; 3422 case 33: op = rv_op_vsadd_vi; break; 3423 case 37: op = rv_op_vsll_vi; break; 3424 case 39: 3425 switch ((inst >> 15) & 0b11111) { 3426 case 0: op = rv_op_vmv1r_v; break; 3427 case 1: op = rv_op_vmv2r_v; break; 3428 case 3: op = rv_op_vmv4r_v; break; 3429 case 7: op = rv_op_vmv8r_v; break; 3430 } 3431 break; 3432 case 40: op = rv_op_vsrl_vi; break; 3433 case 41: op = rv_op_vsra_vi; break; 3434 case 42: op = rv_op_vssrl_vi; break; 3435 case 43: op = rv_op_vssra_vi; break; 3436 case 44: op = rv_op_vnsrl_wi; break; 3437 case 45: op = rv_op_vnsra_wi; break; 3438 case 46: op = rv_op_vnclipu_wi; break; 3439 case 47: op = rv_op_vnclip_wi; break; 3440 } 3441 break; 3442 case 4: 3443 switch ((inst >> 26) & 0b111111) { 3444 case 0: op = rv_op_vadd_vx; break; 3445 case 2: op = rv_op_vsub_vx; break; 3446 case 3: op = rv_op_vrsub_vx; break; 3447 case 4: op = rv_op_vminu_vx; break; 3448 case 5: op = rv_op_vmin_vx; break; 3449 case 6: op = rv_op_vmaxu_vx; break; 3450 case 7: op = rv_op_vmax_vx; break; 3451 case 9: op = rv_op_vand_vx; break; 3452 case 10: op = rv_op_vor_vx; break; 3453 case 11: op = rv_op_vxor_vx; break; 3454 case 12: op = rv_op_vrgather_vx; break; 3455 case 14: op = rv_op_vslideup_vx; break; 3456 case 15: op = rv_op_vslidedown_vx; break; 3457 case 16: 3458 if (((inst >> 25) & 1) == 0) { 3459 op = rv_op_vadc_vxm; 3460 } 3461 break; 3462 case 17: op = rv_op_vmadc_vxm; break; 3463 case 18: 3464 if (((inst >> 25) & 1) == 0) { 3465 op = rv_op_vsbc_vxm; 3466 } 3467 break; 3468 case 19: op = rv_op_vmsbc_vxm; break; 3469 case 23: 3470 if (((inst >> 20) & 0b111111) == 32) 3471 op = rv_op_vmv_v_x; 3472 else if (((inst >> 25) & 1) == 0) 3473 op = rv_op_vmerge_vxm; 3474 break; 3475 case 24: op = rv_op_vmseq_vx; break; 3476 case 25: op = rv_op_vmsne_vx; break; 3477 case 26: op = rv_op_vmsltu_vx; break; 3478 case 27: op = rv_op_vmslt_vx; break; 3479 case 28: op = rv_op_vmsleu_vx; break; 3480 case 29: op = rv_op_vmsle_vx; break; 3481 case 30: op = rv_op_vmsgtu_vx; break; 3482 case 31: op = rv_op_vmsgt_vx; break; 3483 case 32: op = rv_op_vsaddu_vx; break; 3484 case 33: op = rv_op_vsadd_vx; break; 3485 case 34: op = rv_op_vssubu_vx; break; 3486 case 35: op = rv_op_vssub_vx; break; 3487 case 37: op = rv_op_vsll_vx; break; 3488 case 39: op = rv_op_vsmul_vx; break; 3489 case 40: op = rv_op_vsrl_vx; break; 3490 case 41: op = rv_op_vsra_vx; break; 3491 case 42: op = rv_op_vssrl_vx; break; 3492 case 43: op = rv_op_vssra_vx; break; 3493 case 44: op = rv_op_vnsrl_wx; break; 3494 case 45: op = rv_op_vnsra_wx; break; 3495 case 46: op = rv_op_vnclipu_wx; break; 3496 case 47: op = rv_op_vnclip_wx; break; 3497 } 3498 break; 3499 case 5: 3500 switch ((inst >> 26) & 0b111111) { 3501 case 0: op = rv_op_vfadd_vf; break; 3502 case 2: op = rv_op_vfsub_vf; break; 3503 case 4: op = rv_op_vfmin_vf; break; 3504 case 6: op = rv_op_vfmax_vf; break; 3505 case 8: op = rv_op_vfsgnj_vf; break; 3506 case 9: op = rv_op_vfsgnjn_vf; break; 3507 case 10: op = rv_op_vfsgnjx_vf; break; 3508 case 14: op = rv_op_vfslide1up_vf; break; 3509 case 15: op = rv_op_vfslide1down_vf; break; 3510 case 16: 3511 switch ((inst >> 20) & 0b11111) { 3512 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break; 3513 } 3514 break; 3515 case 23: 3516 if (((inst >> 25) & 1) == 0) 3517 op = rv_op_vfmerge_vfm; 3518 else if (((inst >> 20) & 0b111111) == 32) 3519 op = rv_op_vfmv_v_f; 3520 break; 3521 case 24: op = rv_op_vmfeq_vf; break; 3522 case 25: op = rv_op_vmfle_vf; break; 3523 case 27: op = rv_op_vmflt_vf; break; 3524 case 28: op = rv_op_vmfne_vf; break; 3525 case 29: op = rv_op_vmfgt_vf; break; 3526 case 31: op = rv_op_vmfge_vf; break; 3527 case 32: op = rv_op_vfdiv_vf; break; 3528 case 33: op = rv_op_vfrdiv_vf; break; 3529 case 36: op = rv_op_vfmul_vf; break; 3530 case 39: op = rv_op_vfrsub_vf; break; 3531 case 40: op = rv_op_vfmadd_vf; break; 3532 case 41: op = rv_op_vfnmadd_vf; break; 3533 case 42: op = rv_op_vfmsub_vf; break; 3534 case 43: op = rv_op_vfnmsub_vf; break; 3535 case 44: op = rv_op_vfmacc_vf; break; 3536 case 45: op = rv_op_vfnmacc_vf; break; 3537 case 46: op = rv_op_vfmsac_vf; break; 3538 case 47: op = rv_op_vfnmsac_vf; break; 3539 case 48: op = rv_op_vfwadd_vf; break; 3540 case 50: op = rv_op_vfwsub_vf; break; 3541 case 52: op = rv_op_vfwadd_wf; break; 3542 case 54: op = rv_op_vfwsub_wf; break; 3543 case 56: op = rv_op_vfwmul_vf; break; 3544 case 59: op = rv_op_vfwmaccbf16_vf; break; 3545 case 60: op = rv_op_vfwmacc_vf; break; 3546 case 61: op = rv_op_vfwnmacc_vf; break; 3547 case 62: op = rv_op_vfwmsac_vf; break; 3548 case 63: op = rv_op_vfwnmsac_vf; break; 3549 } 3550 break; 3551 case 6: 3552 switch ((inst >> 26) & 0b111111) { 3553 case 8: op = rv_op_vaaddu_vx; break; 3554 case 9: op = rv_op_vaadd_vx; break; 3555 case 10: op = rv_op_vasubu_vx; break; 3556 case 11: op = rv_op_vasub_vx; break; 3557 case 14: op = rv_op_vslide1up_vx; break; 3558 case 15: op = rv_op_vslide1down_vx; break; 3559 case 16: 3560 switch ((inst >> 20) & 0b11111) { 3561 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break; 3562 } 3563 break; 3564 case 32: op = rv_op_vdivu_vx; break; 3565 case 33: op = rv_op_vdiv_vx; break; 3566 case 34: op = rv_op_vremu_vx; break; 3567 case 35: op = rv_op_vrem_vx; break; 3568 case 36: op = rv_op_vmulhu_vx; break; 3569 case 37: op = rv_op_vmul_vx; break; 3570 case 38: op = rv_op_vmulhsu_vx; break; 3571 case 39: op = rv_op_vmulh_vx; break; 3572 case 41: op = rv_op_vmadd_vx; break; 3573 case 43: op = rv_op_vnmsub_vx; break; 3574 case 45: op = rv_op_vmacc_vx; break; 3575 case 47: op = rv_op_vnmsac_vx; break; 3576 case 48: op = rv_op_vwaddu_vx; break; 3577 case 49: op = rv_op_vwadd_vx; break; 3578 case 50: op = rv_op_vwsubu_vx; break; 3579 case 51: op = rv_op_vwsub_vx; break; 3580 case 52: op = rv_op_vwaddu_wx; break; 3581 case 53: op = rv_op_vwadd_wx; break; 3582 case 54: op = rv_op_vwsubu_wx; break; 3583 case 55: op = rv_op_vwsub_wx; break; 3584 case 56: op = rv_op_vwmulu_vx; break; 3585 case 58: op = rv_op_vwmulsu_vx; break; 3586 case 59: op = rv_op_vwmul_vx; break; 3587 case 60: op = rv_op_vwmaccu_vx; break; 3588 case 61: op = rv_op_vwmacc_vx; break; 3589 case 62: op = rv_op_vwmaccus_vx; break; 3590 case 63: op = rv_op_vwmaccsu_vx; break; 3591 } 3592 break; 3593 case 7: 3594 if (((inst >> 31) & 1) == 0) { 3595 op = rv_op_vsetvli; 3596 } else if ((inst >> 30) & 1) { 3597 op = rv_op_vsetivli; 3598 } else if (((inst >> 25) & 0b11111) == 0) { 3599 op = rv_op_vsetvl; 3600 } 3601 break; 3602 } 3603 break; 3604 case 22: 3605 switch ((inst >> 12) & 0b111) { 3606 case 0: op = rv_op_addid; break; 3607 case 1: 3608 switch ((inst >> 26) & 0b111111) { 3609 case 0: op = rv_op_sllid; break; 3610 } 3611 break; 3612 case 5: 3613 switch ((inst >> 26) & 0b111111) { 3614 case 0: op = rv_op_srlid; break; 3615 case 16: op = rv_op_sraid; break; 3616 } 3617 break; 3618 } 3619 break; 3620 case 24: 3621 switch ((inst >> 12) & 0b111) { 3622 case 0: op = rv_op_beq; break; 3623 case 1: op = rv_op_bne; break; 3624 case 4: op = rv_op_blt; break; 3625 case 5: op = rv_op_bge; break; 3626 case 6: op = rv_op_bltu; break; 3627 case 7: op = rv_op_bgeu; break; 3628 } 3629 break; 3630 case 25: 3631 switch ((inst >> 12) & 0b111) { 3632 case 0: op = rv_op_jalr; break; 3633 } 3634 break; 3635 case 27: op = rv_op_jal; break; 3636 case 28: 3637 switch ((inst >> 12) & 0b111) { 3638 case 0: 3639 switch (((inst >> 20) & 0b111111100000) | 3640 ((inst >> 7) & 0b000000011111)) { 3641 case 0: 3642 switch ((inst >> 15) & 0b1111111111) { 3643 case 0: op = rv_op_ecall; break; 3644 case 32: op = rv_op_ebreak; break; 3645 case 64: op = rv_op_uret; break; 3646 } 3647 break; 3648 case 256: 3649 switch ((inst >> 20) & 0b11111) { 3650 case 2: 3651 switch ((inst >> 15) & 0b11111) { 3652 case 0: op = rv_op_sret; break; 3653 } 3654 break; 3655 case 4: op = rv_op_sfence_vm; break; 3656 case 5: 3657 switch ((inst >> 15) & 0b11111) { 3658 case 0: op = rv_op_wfi; break; 3659 } 3660 break; 3661 } 3662 break; 3663 case 288: op = rv_op_sfence_vma; break; 3664 case 512: 3665 switch ((inst >> 15) & 0b1111111111) { 3666 case 64: op = rv_op_hret; break; 3667 } 3668 break; 3669 case 768: 3670 switch ((inst >> 15) & 0b1111111111) { 3671 case 64: op = rv_op_mret; break; 3672 } 3673 break; 3674 case 1952: 3675 switch ((inst >> 15) & 0b1111111111) { 3676 case 576: op = rv_op_dret; break; 3677 } 3678 break; 3679 } 3680 break; 3681 case 1: op = rv_op_csrrw; break; 3682 case 2: op = rv_op_csrrs; break; 3683 case 3: op = rv_op_csrrc; break; 3684 case 5: op = rv_op_csrrwi; break; 3685 case 6: op = rv_op_csrrsi; break; 3686 case 7: op = rv_op_csrrci; break; 3687 } 3688 break; 3689 case 30: 3690 switch (((inst >> 22) & 0b1111111000) | 3691 ((inst >> 12) & 0b0000000111)) { 3692 case 0: op = rv_op_addd; break; 3693 case 1: op = rv_op_slld; break; 3694 case 5: op = rv_op_srld; break; 3695 case 8: op = rv_op_muld; break; 3696 case 12: op = rv_op_divd; break; 3697 case 13: op = rv_op_divud; break; 3698 case 14: op = rv_op_remd; break; 3699 case 15: op = rv_op_remud; break; 3700 case 256: op = rv_op_subd; break; 3701 case 261: op = rv_op_srad; break; 3702 } 3703 break; 3704 } 3705 break; 3706 } 3707 dec->op = op; 3708 } 3709 3710 /* operand extractors */ 3711 3712 static uint32_t operand_rd(rv_inst inst) 3713 { 3714 return (inst << 52) >> 59; 3715 } 3716 3717 static uint32_t operand_rs1(rv_inst inst) 3718 { 3719 return (inst << 44) >> 59; 3720 } 3721 3722 static uint32_t operand_rs2(rv_inst inst) 3723 { 3724 return (inst << 39) >> 59; 3725 } 3726 3727 static uint32_t operand_rs3(rv_inst inst) 3728 { 3729 return (inst << 32) >> 59; 3730 } 3731 3732 static uint32_t operand_aq(rv_inst inst) 3733 { 3734 return (inst << 37) >> 63; 3735 } 3736 3737 static uint32_t operand_rl(rv_inst inst) 3738 { 3739 return (inst << 38) >> 63; 3740 } 3741 3742 static uint32_t operand_pred(rv_inst inst) 3743 { 3744 return (inst << 36) >> 60; 3745 } 3746 3747 static uint32_t operand_succ(rv_inst inst) 3748 { 3749 return (inst << 40) >> 60; 3750 } 3751 3752 static uint32_t operand_rm(rv_inst inst) 3753 { 3754 return (inst << 49) >> 61; 3755 } 3756 3757 static uint32_t operand_shamt5(rv_inst inst) 3758 { 3759 return (inst << 39) >> 59; 3760 } 3761 3762 static uint32_t operand_shamt6(rv_inst inst) 3763 { 3764 return (inst << 38) >> 58; 3765 } 3766 3767 static uint32_t operand_shamt7(rv_inst inst) 3768 { 3769 return (inst << 37) >> 57; 3770 } 3771 3772 static uint32_t operand_crdq(rv_inst inst) 3773 { 3774 return (inst << 59) >> 61; 3775 } 3776 3777 static uint32_t operand_crs1q(rv_inst inst) 3778 { 3779 return (inst << 54) >> 61; 3780 } 3781 3782 static uint32_t operand_crs1rdq(rv_inst inst) 3783 { 3784 return (inst << 54) >> 61; 3785 } 3786 3787 static uint32_t operand_crs2q(rv_inst inst) 3788 { 3789 return (inst << 59) >> 61; 3790 } 3791 3792 static uint32_t calculate_xreg(uint32_t sreg) 3793 { 3794 return sreg < 2 ? sreg + 8 : sreg + 16; 3795 } 3796 3797 static uint32_t operand_sreg1(rv_inst inst) 3798 { 3799 return calculate_xreg((inst << 54) >> 61); 3800 } 3801 3802 static uint32_t operand_sreg2(rv_inst inst) 3803 { 3804 return calculate_xreg((inst << 59) >> 61); 3805 } 3806 3807 static uint32_t operand_crd(rv_inst inst) 3808 { 3809 return (inst << 52) >> 59; 3810 } 3811 3812 static uint32_t operand_crs1(rv_inst inst) 3813 { 3814 return (inst << 52) >> 59; 3815 } 3816 3817 static uint32_t operand_crs1rd(rv_inst inst) 3818 { 3819 return (inst << 52) >> 59; 3820 } 3821 3822 static uint32_t operand_crs2(rv_inst inst) 3823 { 3824 return (inst << 57) >> 59; 3825 } 3826 3827 static uint32_t operand_cimmsh5(rv_inst inst) 3828 { 3829 return (inst << 57) >> 59; 3830 } 3831 3832 static uint32_t operand_csr12(rv_inst inst) 3833 { 3834 return (inst << 32) >> 52; 3835 } 3836 3837 static int32_t operand_imm12(rv_inst inst) 3838 { 3839 return ((int64_t)inst << 32) >> 52; 3840 } 3841 3842 static int32_t operand_imm20(rv_inst inst) 3843 { 3844 return (((int64_t)inst << 32) >> 44) << 12; 3845 } 3846 3847 static int32_t operand_jimm20(rv_inst inst) 3848 { 3849 return (((int64_t)inst << 32) >> 63) << 20 | 3850 ((inst << 33) >> 54) << 1 | 3851 ((inst << 43) >> 63) << 11 | 3852 ((inst << 44) >> 56) << 12; 3853 } 3854 3855 static int32_t operand_simm12(rv_inst inst) 3856 { 3857 return (((int64_t)inst << 32) >> 57) << 5 | 3858 (inst << 52) >> 59; 3859 } 3860 3861 static int32_t operand_sbimm12(rv_inst inst) 3862 { 3863 return (((int64_t)inst << 32) >> 63) << 12 | 3864 ((inst << 33) >> 58) << 5 | 3865 ((inst << 52) >> 60) << 1 | 3866 ((inst << 56) >> 63) << 11; 3867 } 3868 3869 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) 3870 { 3871 int imm = ((inst << 51) >> 63) << 5 | 3872 (inst << 57) >> 59; 3873 if (isa == rv128) { 3874 imm = imm ? imm : 64; 3875 } 3876 return imm; 3877 } 3878 3879 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) 3880 { 3881 int imm = ((inst << 51) >> 63) << 5 | 3882 (inst << 57) >> 59; 3883 if (isa == rv128) { 3884 imm = imm | (imm & 32) << 1; 3885 imm = imm ? imm : 64; 3886 } 3887 return imm; 3888 } 3889 3890 static int32_t operand_cimmi(rv_inst inst) 3891 { 3892 return (((int64_t)inst << 51) >> 63) << 5 | 3893 (inst << 57) >> 59; 3894 } 3895 3896 static int32_t operand_cimmui(rv_inst inst) 3897 { 3898 return (((int64_t)inst << 51) >> 63) << 17 | 3899 ((inst << 57) >> 59) << 12; 3900 } 3901 3902 static uint32_t operand_cimmlwsp(rv_inst inst) 3903 { 3904 return ((inst << 51) >> 63) << 5 | 3905 ((inst << 57) >> 61) << 2 | 3906 ((inst << 60) >> 62) << 6; 3907 } 3908 3909 static uint32_t operand_cimmldsp(rv_inst inst) 3910 { 3911 return ((inst << 51) >> 63) << 5 | 3912 ((inst << 57) >> 62) << 3 | 3913 ((inst << 59) >> 61) << 6; 3914 } 3915 3916 static uint32_t operand_cimmlqsp(rv_inst inst) 3917 { 3918 return ((inst << 51) >> 63) << 5 | 3919 ((inst << 57) >> 63) << 4 | 3920 ((inst << 58) >> 60) << 6; 3921 } 3922 3923 static int32_t operand_cimm16sp(rv_inst inst) 3924 { 3925 return (((int64_t)inst << 51) >> 63) << 9 | 3926 ((inst << 57) >> 63) << 4 | 3927 ((inst << 58) >> 63) << 6 | 3928 ((inst << 59) >> 62) << 7 | 3929 ((inst << 61) >> 63) << 5; 3930 } 3931 3932 static int32_t operand_cimmj(rv_inst inst) 3933 { 3934 return (((int64_t)inst << 51) >> 63) << 11 | 3935 ((inst << 52) >> 63) << 4 | 3936 ((inst << 53) >> 62) << 8 | 3937 ((inst << 55) >> 63) << 10 | 3938 ((inst << 56) >> 63) << 6 | 3939 ((inst << 57) >> 63) << 7 | 3940 ((inst << 58) >> 61) << 1 | 3941 ((inst << 61) >> 63) << 5; 3942 } 3943 3944 static int32_t operand_cimmb(rv_inst inst) 3945 { 3946 return (((int64_t)inst << 51) >> 63) << 8 | 3947 ((inst << 52) >> 62) << 3 | 3948 ((inst << 57) >> 62) << 6 | 3949 ((inst << 59) >> 62) << 1 | 3950 ((inst << 61) >> 63) << 5; 3951 } 3952 3953 static uint32_t operand_cimmswsp(rv_inst inst) 3954 { 3955 return ((inst << 51) >> 60) << 2 | 3956 ((inst << 55) >> 62) << 6; 3957 } 3958 3959 static uint32_t operand_cimmsdsp(rv_inst inst) 3960 { 3961 return ((inst << 51) >> 61) << 3 | 3962 ((inst << 54) >> 61) << 6; 3963 } 3964 3965 static uint32_t operand_cimmsqsp(rv_inst inst) 3966 { 3967 return ((inst << 51) >> 62) << 4 | 3968 ((inst << 53) >> 60) << 6; 3969 } 3970 3971 static uint32_t operand_cimm4spn(rv_inst inst) 3972 { 3973 return ((inst << 51) >> 62) << 4 | 3974 ((inst << 53) >> 60) << 6 | 3975 ((inst << 57) >> 63) << 2 | 3976 ((inst << 58) >> 63) << 3; 3977 } 3978 3979 static uint32_t operand_cimmw(rv_inst inst) 3980 { 3981 return ((inst << 51) >> 61) << 3 | 3982 ((inst << 57) >> 63) << 2 | 3983 ((inst << 58) >> 63) << 6; 3984 } 3985 3986 static uint32_t operand_cimmd(rv_inst inst) 3987 { 3988 return ((inst << 51) >> 61) << 3 | 3989 ((inst << 57) >> 62) << 6; 3990 } 3991 3992 static uint32_t operand_cimmq(rv_inst inst) 3993 { 3994 return ((inst << 51) >> 62) << 4 | 3995 ((inst << 53) >> 63) << 8 | 3996 ((inst << 57) >> 62) << 6; 3997 } 3998 3999 static uint32_t operand_vimm(rv_inst inst) 4000 { 4001 return (int64_t)(inst << 44) >> 59; 4002 } 4003 4004 static uint32_t operand_vzimm11(rv_inst inst) 4005 { 4006 return (inst << 33) >> 53; 4007 } 4008 4009 static uint32_t operand_vzimm10(rv_inst inst) 4010 { 4011 return (inst << 34) >> 54; 4012 } 4013 4014 static uint32_t operand_bs(rv_inst inst) 4015 { 4016 return (inst << 32) >> 62; 4017 } 4018 4019 static uint32_t operand_rnum(rv_inst inst) 4020 { 4021 return (inst << 40) >> 60; 4022 } 4023 4024 static uint32_t operand_vm(rv_inst inst) 4025 { 4026 return (inst << 38) >> 63; 4027 } 4028 4029 static uint32_t operand_uimm_c_lb(rv_inst inst) 4030 { 4031 return (((inst << 58) >> 63) << 1) | 4032 ((inst << 57) >> 63); 4033 } 4034 4035 static uint32_t operand_uimm_c_lh(rv_inst inst) 4036 { 4037 return (((inst << 58) >> 63) << 1); 4038 } 4039 4040 static uint32_t operand_zcmp_spimm(rv_inst inst) 4041 { 4042 return ((inst << 60) >> 62) << 4; 4043 } 4044 4045 static uint32_t operand_zcmp_rlist(rv_inst inst) 4046 { 4047 return ((inst << 56) >> 60); 4048 } 4049 4050 static uint32_t operand_imm6(rv_inst inst) 4051 { 4052 return (inst << 38) >> 60; 4053 } 4054 4055 static uint32_t operand_imm2(rv_inst inst) 4056 { 4057 return (inst << 37) >> 62; 4058 } 4059 4060 static uint32_t operand_immh(rv_inst inst) 4061 { 4062 return (inst << 32) >> 58; 4063 } 4064 4065 static uint32_t operand_imml(rv_inst inst) 4066 { 4067 return (inst << 38) >> 58; 4068 } 4069 4070 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm) 4071 { 4072 int xlen_bytes_log2 = isa == rv64 ? 3 : 2; 4073 int regs = rlist == 15 ? 13 : rlist - 3; 4074 uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16); 4075 return stack_adj_base + spimm; 4076 } 4077 4078 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa) 4079 { 4080 return calculate_stack_adj(isa, operand_zcmp_rlist(inst), 4081 operand_zcmp_spimm(inst)); 4082 } 4083 4084 static uint32_t operand_tbl_index(rv_inst inst) 4085 { 4086 return ((inst << 54) >> 56); 4087 } 4088 4089 /* decode operands */ 4090 4091 static void decode_inst_operands(rv_decode *dec, rv_isa isa) 4092 { 4093 const rv_opcode_data *opcode_data = dec->opcode_data; 4094 rv_inst inst = dec->inst; 4095 dec->codec = opcode_data[dec->op].codec; 4096 switch (dec->codec) { 4097 case rv_codec_none: 4098 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4099 dec->imm = 0; 4100 break; 4101 case rv_codec_u: 4102 dec->rd = operand_rd(inst); 4103 dec->rs1 = dec->rs2 = rv_ireg_zero; 4104 dec->imm = operand_imm20(inst); 4105 break; 4106 case rv_codec_uj: 4107 dec->rd = operand_rd(inst); 4108 dec->rs1 = dec->rs2 = rv_ireg_zero; 4109 dec->imm = operand_jimm20(inst); 4110 break; 4111 case rv_codec_i: 4112 dec->rd = operand_rd(inst); 4113 dec->rs1 = operand_rs1(inst); 4114 dec->rs2 = rv_ireg_zero; 4115 dec->imm = operand_imm12(inst); 4116 break; 4117 case rv_codec_i_sh5: 4118 dec->rd = operand_rd(inst); 4119 dec->rs1 = operand_rs1(inst); 4120 dec->rs2 = rv_ireg_zero; 4121 dec->imm = operand_shamt5(inst); 4122 break; 4123 case rv_codec_i_sh6: 4124 dec->rd = operand_rd(inst); 4125 dec->rs1 = operand_rs1(inst); 4126 dec->rs2 = rv_ireg_zero; 4127 dec->imm = operand_shamt6(inst); 4128 break; 4129 case rv_codec_i_sh7: 4130 dec->rd = operand_rd(inst); 4131 dec->rs1 = operand_rs1(inst); 4132 dec->rs2 = rv_ireg_zero; 4133 dec->imm = operand_shamt7(inst); 4134 break; 4135 case rv_codec_i_csr: 4136 dec->rd = operand_rd(inst); 4137 dec->rs1 = operand_rs1(inst); 4138 dec->rs2 = rv_ireg_zero; 4139 dec->imm = operand_csr12(inst); 4140 break; 4141 case rv_codec_s: 4142 dec->rd = rv_ireg_zero; 4143 dec->rs1 = operand_rs1(inst); 4144 dec->rs2 = operand_rs2(inst); 4145 dec->imm = operand_simm12(inst); 4146 break; 4147 case rv_codec_sb: 4148 dec->rd = rv_ireg_zero; 4149 dec->rs1 = operand_rs1(inst); 4150 dec->rs2 = operand_rs2(inst); 4151 dec->imm = operand_sbimm12(inst); 4152 break; 4153 case rv_codec_r: 4154 dec->rd = operand_rd(inst); 4155 dec->rs1 = operand_rs1(inst); 4156 dec->rs2 = operand_rs2(inst); 4157 dec->imm = 0; 4158 break; 4159 case rv_codec_r_m: 4160 dec->rd = operand_rd(inst); 4161 dec->rs1 = operand_rs1(inst); 4162 dec->rs2 = operand_rs2(inst); 4163 dec->imm = 0; 4164 dec->rm = operand_rm(inst); 4165 break; 4166 case rv_codec_r4_m: 4167 dec->rd = operand_rd(inst); 4168 dec->rs1 = operand_rs1(inst); 4169 dec->rs2 = operand_rs2(inst); 4170 dec->rs3 = operand_rs3(inst); 4171 dec->imm = 0; 4172 dec->rm = operand_rm(inst); 4173 break; 4174 case rv_codec_r_a: 4175 dec->rd = operand_rd(inst); 4176 dec->rs1 = operand_rs1(inst); 4177 dec->rs2 = operand_rs2(inst); 4178 dec->imm = 0; 4179 dec->aq = operand_aq(inst); 4180 dec->rl = operand_rl(inst); 4181 break; 4182 case rv_codec_r_l: 4183 dec->rd = operand_rd(inst); 4184 dec->rs1 = operand_rs1(inst); 4185 dec->rs2 = rv_ireg_zero; 4186 dec->imm = 0; 4187 dec->aq = operand_aq(inst); 4188 dec->rl = operand_rl(inst); 4189 break; 4190 case rv_codec_r_f: 4191 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4192 dec->pred = operand_pred(inst); 4193 dec->succ = operand_succ(inst); 4194 dec->imm = 0; 4195 break; 4196 case rv_codec_cb: 4197 dec->rd = rv_ireg_zero; 4198 dec->rs1 = operand_crs1q(inst) + 8; 4199 dec->rs2 = rv_ireg_zero; 4200 dec->imm = operand_cimmb(inst); 4201 break; 4202 case rv_codec_cb_imm: 4203 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4204 dec->rs2 = rv_ireg_zero; 4205 dec->imm = operand_cimmi(inst); 4206 break; 4207 case rv_codec_cb_sh5: 4208 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4209 dec->rs2 = rv_ireg_zero; 4210 dec->imm = operand_cimmsh5(inst); 4211 break; 4212 case rv_codec_cb_sh6: 4213 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4214 dec->rs2 = rv_ireg_zero; 4215 dec->imm = operand_cimmshr6(inst, isa); 4216 break; 4217 case rv_codec_ci: 4218 dec->rd = dec->rs1 = operand_crs1rd(inst); 4219 dec->rs2 = rv_ireg_zero; 4220 dec->imm = operand_cimmi(inst); 4221 break; 4222 case rv_codec_ci_sh5: 4223 dec->rd = dec->rs1 = operand_crs1rd(inst); 4224 dec->rs2 = rv_ireg_zero; 4225 dec->imm = operand_cimmsh5(inst); 4226 break; 4227 case rv_codec_ci_sh6: 4228 dec->rd = dec->rs1 = operand_crs1rd(inst); 4229 dec->rs2 = rv_ireg_zero; 4230 dec->imm = operand_cimmshl6(inst, isa); 4231 break; 4232 case rv_codec_ci_16sp: 4233 dec->rd = rv_ireg_sp; 4234 dec->rs1 = rv_ireg_sp; 4235 dec->rs2 = rv_ireg_zero; 4236 dec->imm = operand_cimm16sp(inst); 4237 break; 4238 case rv_codec_ci_lwsp: 4239 dec->rd = operand_crd(inst); 4240 dec->rs1 = rv_ireg_sp; 4241 dec->rs2 = rv_ireg_zero; 4242 dec->imm = operand_cimmlwsp(inst); 4243 break; 4244 case rv_codec_ci_ldsp: 4245 dec->rd = operand_crd(inst); 4246 dec->rs1 = rv_ireg_sp; 4247 dec->rs2 = rv_ireg_zero; 4248 dec->imm = operand_cimmldsp(inst); 4249 break; 4250 case rv_codec_ci_lqsp: 4251 dec->rd = operand_crd(inst); 4252 dec->rs1 = rv_ireg_sp; 4253 dec->rs2 = rv_ireg_zero; 4254 dec->imm = operand_cimmlqsp(inst); 4255 break; 4256 case rv_codec_ci_li: 4257 dec->rd = operand_crd(inst); 4258 dec->rs1 = rv_ireg_zero; 4259 dec->rs2 = rv_ireg_zero; 4260 dec->imm = operand_cimmi(inst); 4261 break; 4262 case rv_codec_ci_lui: 4263 dec->rd = operand_crd(inst); 4264 dec->rs1 = rv_ireg_zero; 4265 dec->rs2 = rv_ireg_zero; 4266 dec->imm = operand_cimmui(inst); 4267 break; 4268 case rv_codec_ci_none: 4269 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4270 dec->imm = 0; 4271 break; 4272 case rv_codec_ciw_4spn: 4273 dec->rd = operand_crdq(inst) + 8; 4274 dec->rs1 = rv_ireg_sp; 4275 dec->rs2 = rv_ireg_zero; 4276 dec->imm = operand_cimm4spn(inst); 4277 break; 4278 case rv_codec_cj: 4279 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4280 dec->imm = operand_cimmj(inst); 4281 break; 4282 case rv_codec_cj_jal: 4283 dec->rd = rv_ireg_ra; 4284 dec->rs1 = dec->rs2 = rv_ireg_zero; 4285 dec->imm = operand_cimmj(inst); 4286 break; 4287 case rv_codec_cl_lw: 4288 dec->rd = operand_crdq(inst) + 8; 4289 dec->rs1 = operand_crs1q(inst) + 8; 4290 dec->rs2 = rv_ireg_zero; 4291 dec->imm = operand_cimmw(inst); 4292 break; 4293 case rv_codec_cl_ld: 4294 dec->rd = operand_crdq(inst) + 8; 4295 dec->rs1 = operand_crs1q(inst) + 8; 4296 dec->rs2 = rv_ireg_zero; 4297 dec->imm = operand_cimmd(inst); 4298 break; 4299 case rv_codec_cl_lq: 4300 dec->rd = operand_crdq(inst) + 8; 4301 dec->rs1 = operand_crs1q(inst) + 8; 4302 dec->rs2 = rv_ireg_zero; 4303 dec->imm = operand_cimmq(inst); 4304 break; 4305 case rv_codec_cr: 4306 dec->rd = dec->rs1 = operand_crs1rd(inst); 4307 dec->rs2 = operand_crs2(inst); 4308 dec->imm = 0; 4309 break; 4310 case rv_codec_cr_mv: 4311 dec->rd = operand_crd(inst); 4312 dec->rs1 = operand_crs2(inst); 4313 dec->rs2 = rv_ireg_zero; 4314 dec->imm = 0; 4315 break; 4316 case rv_codec_cr_jalr: 4317 dec->rd = rv_ireg_ra; 4318 dec->rs1 = operand_crs1(inst); 4319 dec->rs2 = rv_ireg_zero; 4320 dec->imm = 0; 4321 break; 4322 case rv_codec_cr_jr: 4323 dec->rd = rv_ireg_zero; 4324 dec->rs1 = operand_crs1(inst); 4325 dec->rs2 = rv_ireg_zero; 4326 dec->imm = 0; 4327 break; 4328 case rv_codec_cs: 4329 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4330 dec->rs2 = operand_crs2q(inst) + 8; 4331 dec->imm = 0; 4332 break; 4333 case rv_codec_cs_sw: 4334 dec->rd = rv_ireg_zero; 4335 dec->rs1 = operand_crs1q(inst) + 8; 4336 dec->rs2 = operand_crs2q(inst) + 8; 4337 dec->imm = operand_cimmw(inst); 4338 break; 4339 case rv_codec_cs_sd: 4340 dec->rd = rv_ireg_zero; 4341 dec->rs1 = operand_crs1q(inst) + 8; 4342 dec->rs2 = operand_crs2q(inst) + 8; 4343 dec->imm = operand_cimmd(inst); 4344 break; 4345 case rv_codec_cs_sq: 4346 dec->rd = rv_ireg_zero; 4347 dec->rs1 = operand_crs1q(inst) + 8; 4348 dec->rs2 = operand_crs2q(inst) + 8; 4349 dec->imm = operand_cimmq(inst); 4350 break; 4351 case rv_codec_css_swsp: 4352 dec->rd = rv_ireg_zero; 4353 dec->rs1 = rv_ireg_sp; 4354 dec->rs2 = operand_crs2(inst); 4355 dec->imm = operand_cimmswsp(inst); 4356 break; 4357 case rv_codec_css_sdsp: 4358 dec->rd = rv_ireg_zero; 4359 dec->rs1 = rv_ireg_sp; 4360 dec->rs2 = operand_crs2(inst); 4361 dec->imm = operand_cimmsdsp(inst); 4362 break; 4363 case rv_codec_css_sqsp: 4364 dec->rd = rv_ireg_zero; 4365 dec->rs1 = rv_ireg_sp; 4366 dec->rs2 = operand_crs2(inst); 4367 dec->imm = operand_cimmsqsp(inst); 4368 break; 4369 case rv_codec_k_bs: 4370 dec->rs1 = operand_rs1(inst); 4371 dec->rs2 = operand_rs2(inst); 4372 dec->bs = operand_bs(inst); 4373 break; 4374 case rv_codec_k_rnum: 4375 dec->rd = operand_rd(inst); 4376 dec->rs1 = operand_rs1(inst); 4377 dec->rnum = operand_rnum(inst); 4378 break; 4379 case rv_codec_v_r: 4380 dec->rd = operand_rd(inst); 4381 dec->rs1 = operand_rs1(inst); 4382 dec->rs2 = operand_rs2(inst); 4383 dec->vm = operand_vm(inst); 4384 break; 4385 case rv_codec_v_ldst: 4386 dec->rd = operand_rd(inst); 4387 dec->rs1 = operand_rs1(inst); 4388 dec->vm = operand_vm(inst); 4389 break; 4390 case rv_codec_v_i: 4391 dec->rd = operand_rd(inst); 4392 dec->rs2 = operand_rs2(inst); 4393 dec->imm = operand_vimm(inst); 4394 dec->vm = operand_vm(inst); 4395 break; 4396 case rv_codec_vsetvli: 4397 dec->rd = operand_rd(inst); 4398 dec->rs1 = operand_rs1(inst); 4399 dec->vzimm = operand_vzimm11(inst); 4400 break; 4401 case rv_codec_vsetivli: 4402 dec->rd = operand_rd(inst); 4403 dec->imm = operand_vimm(inst); 4404 dec->vzimm = operand_vzimm10(inst); 4405 break; 4406 case rv_codec_zcb_lb: 4407 dec->rs1 = operand_crs1q(inst) + 8; 4408 dec->rs2 = operand_crs2q(inst) + 8; 4409 dec->imm = operand_uimm_c_lb(inst); 4410 break; 4411 case rv_codec_zcb_lh: 4412 dec->rs1 = operand_crs1q(inst) + 8; 4413 dec->rs2 = operand_crs2q(inst) + 8; 4414 dec->imm = operand_uimm_c_lh(inst); 4415 break; 4416 case rv_codec_zcb_ext: 4417 dec->rd = operand_crs1q(inst) + 8; 4418 break; 4419 case rv_codec_zcb_mul: 4420 dec->rd = operand_crs1rdq(inst) + 8; 4421 dec->rs2 = operand_crs2q(inst) + 8; 4422 break; 4423 case rv_codec_zcmp_cm_pushpop: 4424 dec->imm = operand_zcmp_stack_adj(inst, isa); 4425 dec->rlist = operand_zcmp_rlist(inst); 4426 break; 4427 case rv_codec_zcmp_cm_mv: 4428 dec->rd = operand_sreg1(inst); 4429 dec->rs2 = operand_sreg2(inst); 4430 break; 4431 case rv_codec_zcmt_jt: 4432 dec->imm = operand_tbl_index(inst); 4433 break; 4434 case rv_codec_fli: 4435 dec->rd = operand_rd(inst); 4436 dec->imm = operand_rs1(inst); 4437 break; 4438 case rv_codec_r2_imm5: 4439 dec->rd = operand_rd(inst); 4440 dec->rs1 = operand_rs1(inst); 4441 dec->imm = operand_rs2(inst); 4442 break; 4443 case rv_codec_r2: 4444 dec->rd = operand_rd(inst); 4445 dec->rs1 = operand_rs1(inst); 4446 break; 4447 case rv_codec_r2_imm6: 4448 dec->rd = operand_rd(inst); 4449 dec->rs1 = operand_rs1(inst); 4450 dec->imm = operand_imm6(inst); 4451 break; 4452 case rv_codec_r_imm2: 4453 dec->rd = operand_rd(inst); 4454 dec->rs1 = operand_rs1(inst); 4455 dec->rs2 = operand_rs2(inst); 4456 dec->imm = operand_imm2(inst); 4457 break; 4458 case rv_codec_r2_immhl: 4459 dec->rd = operand_rd(inst); 4460 dec->rs1 = operand_rs1(inst); 4461 dec->imm = operand_immh(inst); 4462 dec->imm1 = operand_imml(inst); 4463 break; 4464 case rv_codec_r2_imm2_imm5: 4465 dec->rd = operand_rd(inst); 4466 dec->rs1 = operand_rs1(inst); 4467 dec->imm = sextract32(operand_rs2(inst), 0, 5); 4468 dec->imm1 = operand_imm2(inst); 4469 break; 4470 }; 4471 } 4472 4473 /* check constraint */ 4474 4475 static bool check_constraints(rv_decode *dec, const rvc_constraint *c) 4476 { 4477 int32_t imm = dec->imm; 4478 uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2; 4479 while (*c != rvc_end) { 4480 switch (*c) { 4481 case rvc_rd_eq_ra: 4482 if (!(rd == 1)) { 4483 return false; 4484 } 4485 break; 4486 case rvc_rd_eq_x0: 4487 if (!(rd == 0)) { 4488 return false; 4489 } 4490 break; 4491 case rvc_rs1_eq_x0: 4492 if (!(rs1 == 0)) { 4493 return false; 4494 } 4495 break; 4496 case rvc_rs2_eq_x0: 4497 if (!(rs2 == 0)) { 4498 return false; 4499 } 4500 break; 4501 case rvc_rs2_eq_rs1: 4502 if (!(rs2 == rs1)) { 4503 return false; 4504 } 4505 break; 4506 case rvc_rs1_eq_ra: 4507 if (!(rs1 == 1)) { 4508 return false; 4509 } 4510 break; 4511 case rvc_imm_eq_zero: 4512 if (!(imm == 0)) { 4513 return false; 4514 } 4515 break; 4516 case rvc_imm_eq_n1: 4517 if (!(imm == -1)) { 4518 return false; 4519 } 4520 break; 4521 case rvc_imm_eq_p1: 4522 if (!(imm == 1)) { 4523 return false; 4524 } 4525 break; 4526 case rvc_csr_eq_0x001: 4527 if (!(imm == 0x001)) { 4528 return false; 4529 } 4530 break; 4531 case rvc_csr_eq_0x002: 4532 if (!(imm == 0x002)) { 4533 return false; 4534 } 4535 break; 4536 case rvc_csr_eq_0x003: 4537 if (!(imm == 0x003)) { 4538 return false; 4539 } 4540 break; 4541 case rvc_csr_eq_0xc00: 4542 if (!(imm == 0xc00)) { 4543 return false; 4544 } 4545 break; 4546 case rvc_csr_eq_0xc01: 4547 if (!(imm == 0xc01)) { 4548 return false; 4549 } 4550 break; 4551 case rvc_csr_eq_0xc02: 4552 if (!(imm == 0xc02)) { 4553 return false; 4554 } 4555 break; 4556 case rvc_csr_eq_0xc80: 4557 if (!(imm == 0xc80)) { 4558 return false; 4559 } 4560 break; 4561 case rvc_csr_eq_0xc81: 4562 if (!(imm == 0xc81)) { 4563 return false; 4564 } 4565 break; 4566 case rvc_csr_eq_0xc82: 4567 if (!(imm == 0xc82)) { 4568 return false; 4569 } 4570 break; 4571 default: break; 4572 } 4573 c++; 4574 } 4575 return true; 4576 } 4577 4578 /* instruction length */ 4579 4580 static size_t inst_length(rv_inst inst) 4581 { 4582 /* NOTE: supports maximum instruction size of 64-bits */ 4583 4584 /* 4585 * instruction length coding 4586 * 4587 * aa - 16 bit aa != 11 4588 * bbb11 - 32 bit bbb != 111 4589 * 011111 - 48 bit 4590 * 0111111 - 64 bit 4591 */ 4592 4593 return (inst & 0b11) != 0b11 ? 2 4594 : (inst & 0b11100) != 0b11100 ? 4 4595 : (inst & 0b111111) == 0b011111 ? 6 4596 : (inst & 0b1111111) == 0b0111111 ? 8 4597 : 0; 4598 } 4599 4600 /* format instruction */ 4601 4602 static void append(char *s1, const char *s2, size_t n) 4603 { 4604 size_t l1 = strlen(s1); 4605 if (n - l1 - 1 > 0) { 4606 strncat(s1, s2, n - l1); 4607 } 4608 } 4609 4610 static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) 4611 { 4612 const rv_opcode_data *opcode_data = dec->opcode_data; 4613 char tmp[64]; 4614 const char *fmt; 4615 4616 fmt = opcode_data[dec->op].format; 4617 while (*fmt) { 4618 switch (*fmt) { 4619 case 'O': 4620 append(buf, opcode_data[dec->op].name, buflen); 4621 break; 4622 case '(': 4623 append(buf, "(", buflen); 4624 break; 4625 case ',': 4626 append(buf, ",", buflen); 4627 break; 4628 case ')': 4629 append(buf, ")", buflen); 4630 break; 4631 case '-': 4632 append(buf, "-", buflen); 4633 break; 4634 case 'b': 4635 snprintf(tmp, sizeof(tmp), "%d", dec->bs); 4636 append(buf, tmp, buflen); 4637 break; 4638 case 'n': 4639 snprintf(tmp, sizeof(tmp), "%d", dec->rnum); 4640 append(buf, tmp, buflen); 4641 break; 4642 case '0': 4643 append(buf, rv_ireg_name_sym[dec->rd], buflen); 4644 break; 4645 case '1': 4646 append(buf, rv_ireg_name_sym[dec->rs1], buflen); 4647 break; 4648 case '2': 4649 append(buf, rv_ireg_name_sym[dec->rs2], buflen); 4650 break; 4651 case '3': 4652 append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rd] : 4653 rv_freg_name_sym[dec->rd], 4654 buflen); 4655 break; 4656 case '4': 4657 append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs1] : 4658 rv_freg_name_sym[dec->rs1], 4659 buflen); 4660 break; 4661 case '5': 4662 append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs2] : 4663 rv_freg_name_sym[dec->rs2], 4664 buflen); 4665 break; 4666 case '6': 4667 append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs3] : 4668 rv_freg_name_sym[dec->rs3], 4669 buflen); 4670 break; 4671 case '7': 4672 snprintf(tmp, sizeof(tmp), "%d", dec->rs1); 4673 append(buf, tmp, buflen); 4674 break; 4675 case 'i': 4676 snprintf(tmp, sizeof(tmp), "%d", dec->imm); 4677 append(buf, tmp, buflen); 4678 break; 4679 case 'u': 4680 snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111)); 4681 append(buf, tmp, buflen); 4682 break; 4683 case 'j': 4684 snprintf(tmp, sizeof(tmp), "%d", dec->imm1); 4685 append(buf, tmp, buflen); 4686 break; 4687 case 'o': 4688 snprintf(tmp, sizeof(tmp), "%d", dec->imm); 4689 append(buf, tmp, buflen); 4690 while (strlen(buf) < tab * 2) { 4691 append(buf, " ", buflen); 4692 } 4693 snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64, 4694 dec->pc + dec->imm); 4695 append(buf, tmp, buflen); 4696 break; 4697 case 'U': 4698 fmt++; 4699 snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12); 4700 append(buf, tmp, buflen); 4701 if (*fmt == 'o') { 4702 while (strlen(buf) < tab * 2) { 4703 append(buf, " ", buflen); 4704 } 4705 snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64, 4706 dec->pc + dec->imm); 4707 append(buf, tmp, buflen); 4708 } 4709 break; 4710 case 'c': { 4711 const char *name = csr_name(dec->imm & 0xfff); 4712 if (name) { 4713 append(buf, name, buflen); 4714 } else { 4715 snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff); 4716 append(buf, tmp, buflen); 4717 } 4718 break; 4719 } 4720 case 'r': 4721 switch (dec->rm) { 4722 case rv_rm_rne: 4723 append(buf, "rne", buflen); 4724 break; 4725 case rv_rm_rtz: 4726 append(buf, "rtz", buflen); 4727 break; 4728 case rv_rm_rdn: 4729 append(buf, "rdn", buflen); 4730 break; 4731 case rv_rm_rup: 4732 append(buf, "rup", buflen); 4733 break; 4734 case rv_rm_rmm: 4735 append(buf, "rmm", buflen); 4736 break; 4737 case rv_rm_dyn: 4738 append(buf, "dyn", buflen); 4739 break; 4740 default: 4741 append(buf, "inv", buflen); 4742 break; 4743 } 4744 break; 4745 case 'p': 4746 if (dec->pred & rv_fence_i) { 4747 append(buf, "i", buflen); 4748 } 4749 if (dec->pred & rv_fence_o) { 4750 append(buf, "o", buflen); 4751 } 4752 if (dec->pred & rv_fence_r) { 4753 append(buf, "r", buflen); 4754 } 4755 if (dec->pred & rv_fence_w) { 4756 append(buf, "w", buflen); 4757 } 4758 break; 4759 case 's': 4760 if (dec->succ & rv_fence_i) { 4761 append(buf, "i", buflen); 4762 } 4763 if (dec->succ & rv_fence_o) { 4764 append(buf, "o", buflen); 4765 } 4766 if (dec->succ & rv_fence_r) { 4767 append(buf, "r", buflen); 4768 } 4769 if (dec->succ & rv_fence_w) { 4770 append(buf, "w", buflen); 4771 } 4772 break; 4773 case '\t': 4774 while (strlen(buf) < tab) { 4775 append(buf, " ", buflen); 4776 } 4777 break; 4778 case 'A': 4779 if (dec->aq) { 4780 append(buf, ".aq", buflen); 4781 } 4782 break; 4783 case 'R': 4784 if (dec->rl) { 4785 append(buf, ".rl", buflen); 4786 } 4787 break; 4788 case 'l': 4789 append(buf, ",v0", buflen); 4790 break; 4791 case 'm': 4792 if (dec->vm == 0) { 4793 append(buf, ",v0.t", buflen); 4794 } 4795 break; 4796 case 'D': 4797 append(buf, rv_vreg_name_sym[dec->rd], buflen); 4798 break; 4799 case 'E': 4800 append(buf, rv_vreg_name_sym[dec->rs1], buflen); 4801 break; 4802 case 'F': 4803 append(buf, rv_vreg_name_sym[dec->rs2], buflen); 4804 break; 4805 case 'G': 4806 append(buf, rv_vreg_name_sym[dec->rs3], buflen); 4807 break; 4808 case 'v': { 4809 char nbuf[32] = {0}; 4810 const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3); 4811 sprintf(nbuf, "%d", sew); 4812 const int lmul = dec->vzimm & 0b11; 4813 const int flmul = (dec->vzimm >> 2) & 1; 4814 const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu"; 4815 const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu"; 4816 append(buf, "e", buflen); 4817 append(buf, nbuf, buflen); 4818 append(buf, ",m", buflen); 4819 if (flmul) { 4820 switch (lmul) { 4821 case 3: 4822 sprintf(nbuf, "f2"); 4823 break; 4824 case 2: 4825 sprintf(nbuf, "f4"); 4826 break; 4827 case 1: 4828 sprintf(nbuf, "f8"); 4829 break; 4830 } 4831 append(buf, nbuf, buflen); 4832 } else { 4833 sprintf(nbuf, "%d", 1 << lmul); 4834 append(buf, nbuf, buflen); 4835 } 4836 append(buf, ",", buflen); 4837 append(buf, vta, buflen); 4838 append(buf, ",", buflen); 4839 append(buf, vma, buflen); 4840 break; 4841 } 4842 case 'x': { 4843 switch (dec->rlist) { 4844 case 4: 4845 snprintf(tmp, sizeof(tmp), "{ra}"); 4846 break; 4847 case 5: 4848 snprintf(tmp, sizeof(tmp), "{ra, s0}"); 4849 break; 4850 case 15: 4851 snprintf(tmp, sizeof(tmp), "{ra, s0-s11}"); 4852 break; 4853 default: 4854 snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5); 4855 break; 4856 } 4857 append(buf, tmp, buflen); 4858 break; 4859 } 4860 case 'h': 4861 append(buf, rv_fli_name_const[dec->imm], buflen); 4862 break; 4863 default: 4864 break; 4865 } 4866 fmt++; 4867 } 4868 } 4869 4870 /* lift instruction to pseudo-instruction */ 4871 4872 static void decode_inst_lift_pseudo(rv_decode *dec) 4873 { 4874 const rv_opcode_data *opcode_data = dec->opcode_data; 4875 const rv_comp_data *comp_data = opcode_data[dec->op].pseudo; 4876 if (!comp_data) { 4877 return; 4878 } 4879 while (comp_data->constraints) { 4880 if (check_constraints(dec, comp_data->constraints)) { 4881 dec->op = comp_data->op; 4882 dec->codec = opcode_data[dec->op].codec; 4883 return; 4884 } 4885 comp_data++; 4886 } 4887 } 4888 4889 /* decompress instruction */ 4890 4891 static void decode_inst_decompress_rv32(rv_decode *dec) 4892 { 4893 const rv_opcode_data *opcode_data = dec->opcode_data; 4894 int decomp_op = opcode_data[dec->op].decomp_rv32; 4895 if (decomp_op != rv_op_illegal) { 4896 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 4897 && dec->imm == 0) { 4898 dec->op = rv_op_illegal; 4899 } else { 4900 dec->op = decomp_op; 4901 dec->codec = opcode_data[decomp_op].codec; 4902 } 4903 } 4904 } 4905 4906 static void decode_inst_decompress_rv64(rv_decode *dec) 4907 { 4908 const rv_opcode_data *opcode_data = dec->opcode_data; 4909 int decomp_op = opcode_data[dec->op].decomp_rv64; 4910 if (decomp_op != rv_op_illegal) { 4911 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 4912 && dec->imm == 0) { 4913 dec->op = rv_op_illegal; 4914 } else { 4915 dec->op = decomp_op; 4916 dec->codec = opcode_data[decomp_op].codec; 4917 } 4918 } 4919 } 4920 4921 static void decode_inst_decompress_rv128(rv_decode *dec) 4922 { 4923 const rv_opcode_data *opcode_data = dec->opcode_data; 4924 int decomp_op = opcode_data[dec->op].decomp_rv128; 4925 if (decomp_op != rv_op_illegal) { 4926 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 4927 && dec->imm == 0) { 4928 dec->op = rv_op_illegal; 4929 } else { 4930 dec->op = decomp_op; 4931 dec->codec = opcode_data[decomp_op].codec; 4932 } 4933 } 4934 } 4935 4936 static void decode_inst_decompress(rv_decode *dec, rv_isa isa) 4937 { 4938 switch (isa) { 4939 case rv32: 4940 decode_inst_decompress_rv32(dec); 4941 break; 4942 case rv64: 4943 decode_inst_decompress_rv64(dec); 4944 break; 4945 case rv128: 4946 decode_inst_decompress_rv128(dec); 4947 break; 4948 } 4949 } 4950 4951 /* disassemble instruction */ 4952 4953 static void 4954 disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst, 4955 RISCVCPUConfig *cfg) 4956 { 4957 rv_decode dec = { 0 }; 4958 dec.pc = pc; 4959 dec.inst = inst; 4960 dec.cfg = cfg; 4961 4962 static const struct { 4963 bool (*guard_func)(const RISCVCPUConfig *); 4964 const rv_opcode_data *opcode_data; 4965 void (*decode_func)(rv_decode *, rv_isa); 4966 } decoders[] = { 4967 { always_true_p, rvi_opcode_data, decode_inst_opcode }, 4968 { has_xtheadba_p, xthead_opcode_data, decode_xtheadba }, 4969 { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb }, 4970 { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs }, 4971 { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo }, 4972 { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov }, 4973 { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx }, 4974 { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv }, 4975 { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac }, 4976 { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx }, 4977 { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair }, 4978 { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync }, 4979 { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops }, 4980 }; 4981 4982 for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { 4983 bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func; 4984 const rv_opcode_data *opcode_data = decoders[i].opcode_data; 4985 void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func; 4986 4987 if (guard_func(cfg)) { 4988 dec.opcode_data = opcode_data; 4989 decode_func(&dec, isa); 4990 if (dec.op != rv_op_illegal) 4991 break; 4992 } 4993 } 4994 4995 if (dec.op == rv_op_illegal) { 4996 dec.opcode_data = rvi_opcode_data; 4997 } 4998 4999 decode_inst_operands(&dec, isa); 5000 decode_inst_decompress(&dec, isa); 5001 decode_inst_lift_pseudo(&dec); 5002 format_inst(buf, buflen, 24, &dec); 5003 } 5004 5005 #define INST_FMT_2 "%04" PRIx64 " " 5006 #define INST_FMT_4 "%08" PRIx64 " " 5007 #define INST_FMT_6 "%012" PRIx64 " " 5008 #define INST_FMT_8 "%016" PRIx64 " " 5009 5010 static int 5011 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) 5012 { 5013 char buf[128] = { 0 }; 5014 bfd_byte packet[2]; 5015 rv_inst inst = 0; 5016 size_t len = 2; 5017 bfd_vma n; 5018 int status; 5019 5020 /* Instructions are made of 2-byte packets in little-endian order */ 5021 for (n = 0; n < len; n += 2) { 5022 status = (*info->read_memory_func)(memaddr + n, packet, 2, info); 5023 if (status != 0) { 5024 /* Don't fail just because we fell off the end. */ 5025 if (n > 0) { 5026 break; 5027 } 5028 (*info->memory_error_func)(status, memaddr, info); 5029 return status; 5030 } 5031 inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n); 5032 if (n == 0) { 5033 len = inst_length(inst); 5034 } 5035 } 5036 5037 switch (len) { 5038 case 2: 5039 (*info->fprintf_func)(info->stream, INST_FMT_2, inst); 5040 break; 5041 case 4: 5042 (*info->fprintf_func)(info->stream, INST_FMT_4, inst); 5043 break; 5044 case 6: 5045 (*info->fprintf_func)(info->stream, INST_FMT_6, inst); 5046 break; 5047 default: 5048 (*info->fprintf_func)(info->stream, INST_FMT_8, inst); 5049 break; 5050 } 5051 5052 disasm_inst(buf, sizeof(buf), isa, memaddr, inst, 5053 (RISCVCPUConfig *)info->target_info); 5054 (*info->fprintf_func)(info->stream, "%s", buf); 5055 5056 return len; 5057 } 5058 5059 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info) 5060 { 5061 return print_insn_riscv(memaddr, info, rv32); 5062 } 5063 5064 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info) 5065 { 5066 return print_insn_riscv(memaddr, info, rv64); 5067 } 5068 5069 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info) 5070 { 5071 return print_insn_riscv(memaddr, info, rv128); 5072 } 5073