1 /* 2 * QEMU RISC-V Disassembler 3 * 4 * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com> 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "disas/dis-asm.h" 22 23 24 /* types */ 25 26 typedef uint64_t rv_inst; 27 typedef uint16_t rv_opcode; 28 29 /* enums */ 30 31 typedef enum { 32 rv32, 33 rv64, 34 rv128 35 } rv_isa; 36 37 typedef enum { 38 rv_rm_rne = 0, 39 rv_rm_rtz = 1, 40 rv_rm_rdn = 2, 41 rv_rm_rup = 3, 42 rv_rm_rmm = 4, 43 rv_rm_dyn = 7, 44 } rv_rm; 45 46 typedef enum { 47 rv_fence_i = 8, 48 rv_fence_o = 4, 49 rv_fence_r = 2, 50 rv_fence_w = 1, 51 } rv_fence; 52 53 typedef enum { 54 rv_ireg_zero, 55 rv_ireg_ra, 56 rv_ireg_sp, 57 rv_ireg_gp, 58 rv_ireg_tp, 59 rv_ireg_t0, 60 rv_ireg_t1, 61 rv_ireg_t2, 62 rv_ireg_s0, 63 rv_ireg_s1, 64 rv_ireg_a0, 65 rv_ireg_a1, 66 rv_ireg_a2, 67 rv_ireg_a3, 68 rv_ireg_a4, 69 rv_ireg_a5, 70 rv_ireg_a6, 71 rv_ireg_a7, 72 rv_ireg_s2, 73 rv_ireg_s3, 74 rv_ireg_s4, 75 rv_ireg_s5, 76 rv_ireg_s6, 77 rv_ireg_s7, 78 rv_ireg_s8, 79 rv_ireg_s9, 80 rv_ireg_s10, 81 rv_ireg_s11, 82 rv_ireg_t3, 83 rv_ireg_t4, 84 rv_ireg_t5, 85 rv_ireg_t6, 86 } rv_ireg; 87 88 typedef enum { 89 rvc_end, 90 rvc_rd_eq_ra, 91 rvc_rd_eq_x0, 92 rvc_rs1_eq_x0, 93 rvc_rs2_eq_x0, 94 rvc_rs2_eq_rs1, 95 rvc_rs1_eq_ra, 96 rvc_imm_eq_zero, 97 rvc_imm_eq_n1, 98 rvc_imm_eq_p1, 99 rvc_csr_eq_0x001, 100 rvc_csr_eq_0x002, 101 rvc_csr_eq_0x003, 102 rvc_csr_eq_0xc00, 103 rvc_csr_eq_0xc01, 104 rvc_csr_eq_0xc02, 105 rvc_csr_eq_0xc80, 106 rvc_csr_eq_0xc81, 107 rvc_csr_eq_0xc82, 108 } rvc_constraint; 109 110 typedef enum { 111 rv_codec_illegal, 112 rv_codec_none, 113 rv_codec_u, 114 rv_codec_uj, 115 rv_codec_i, 116 rv_codec_i_sh5, 117 rv_codec_i_sh6, 118 rv_codec_i_sh7, 119 rv_codec_i_csr, 120 rv_codec_s, 121 rv_codec_sb, 122 rv_codec_r, 123 rv_codec_r_m, 124 rv_codec_r4_m, 125 rv_codec_r_a, 126 rv_codec_r_l, 127 rv_codec_r_f, 128 rv_codec_cb, 129 rv_codec_cb_imm, 130 rv_codec_cb_sh5, 131 rv_codec_cb_sh6, 132 rv_codec_ci, 133 rv_codec_ci_sh5, 134 rv_codec_ci_sh6, 135 rv_codec_ci_16sp, 136 rv_codec_ci_lwsp, 137 rv_codec_ci_ldsp, 138 rv_codec_ci_lqsp, 139 rv_codec_ci_li, 140 rv_codec_ci_lui, 141 rv_codec_ci_none, 142 rv_codec_ciw_4spn, 143 rv_codec_cj, 144 rv_codec_cj_jal, 145 rv_codec_cl_lw, 146 rv_codec_cl_ld, 147 rv_codec_cl_lq, 148 rv_codec_cr, 149 rv_codec_cr_mv, 150 rv_codec_cr_jalr, 151 rv_codec_cr_jr, 152 rv_codec_cs, 153 rv_codec_cs_sw, 154 rv_codec_cs_sd, 155 rv_codec_cs_sq, 156 rv_codec_css_swsp, 157 rv_codec_css_sdsp, 158 rv_codec_css_sqsp, 159 rv_codec_k_bs, 160 rv_codec_k_rnum, 161 rv_codec_v_r, 162 rv_codec_v_ldst, 163 rv_codec_v_i, 164 rv_codec_vsetvli, 165 rv_codec_vsetivli, 166 rv_codec_zcb_ext, 167 rv_codec_zcb_mul, 168 rv_codec_zcb_lb, 169 rv_codec_zcb_lh, 170 rv_codec_zcmp_cm_pushpop, 171 rv_codec_zcmp_cm_mv, 172 rv_codec_zcmt_jt, 173 } rv_codec; 174 175 typedef enum { 176 rv_op_illegal = 0, 177 rv_op_lui = 1, 178 rv_op_auipc = 2, 179 rv_op_jal = 3, 180 rv_op_jalr = 4, 181 rv_op_beq = 5, 182 rv_op_bne = 6, 183 rv_op_blt = 7, 184 rv_op_bge = 8, 185 rv_op_bltu = 9, 186 rv_op_bgeu = 10, 187 rv_op_lb = 11, 188 rv_op_lh = 12, 189 rv_op_lw = 13, 190 rv_op_lbu = 14, 191 rv_op_lhu = 15, 192 rv_op_sb = 16, 193 rv_op_sh = 17, 194 rv_op_sw = 18, 195 rv_op_addi = 19, 196 rv_op_slti = 20, 197 rv_op_sltiu = 21, 198 rv_op_xori = 22, 199 rv_op_ori = 23, 200 rv_op_andi = 24, 201 rv_op_slli = 25, 202 rv_op_srli = 26, 203 rv_op_srai = 27, 204 rv_op_add = 28, 205 rv_op_sub = 29, 206 rv_op_sll = 30, 207 rv_op_slt = 31, 208 rv_op_sltu = 32, 209 rv_op_xor = 33, 210 rv_op_srl = 34, 211 rv_op_sra = 35, 212 rv_op_or = 36, 213 rv_op_and = 37, 214 rv_op_fence = 38, 215 rv_op_fence_i = 39, 216 rv_op_lwu = 40, 217 rv_op_ld = 41, 218 rv_op_sd = 42, 219 rv_op_addiw = 43, 220 rv_op_slliw = 44, 221 rv_op_srliw = 45, 222 rv_op_sraiw = 46, 223 rv_op_addw = 47, 224 rv_op_subw = 48, 225 rv_op_sllw = 49, 226 rv_op_srlw = 50, 227 rv_op_sraw = 51, 228 rv_op_ldu = 52, 229 rv_op_lq = 53, 230 rv_op_sq = 54, 231 rv_op_addid = 55, 232 rv_op_sllid = 56, 233 rv_op_srlid = 57, 234 rv_op_sraid = 58, 235 rv_op_addd = 59, 236 rv_op_subd = 60, 237 rv_op_slld = 61, 238 rv_op_srld = 62, 239 rv_op_srad = 63, 240 rv_op_mul = 64, 241 rv_op_mulh = 65, 242 rv_op_mulhsu = 66, 243 rv_op_mulhu = 67, 244 rv_op_div = 68, 245 rv_op_divu = 69, 246 rv_op_rem = 70, 247 rv_op_remu = 71, 248 rv_op_mulw = 72, 249 rv_op_divw = 73, 250 rv_op_divuw = 74, 251 rv_op_remw = 75, 252 rv_op_remuw = 76, 253 rv_op_muld = 77, 254 rv_op_divd = 78, 255 rv_op_divud = 79, 256 rv_op_remd = 80, 257 rv_op_remud = 81, 258 rv_op_lr_w = 82, 259 rv_op_sc_w = 83, 260 rv_op_amoswap_w = 84, 261 rv_op_amoadd_w = 85, 262 rv_op_amoxor_w = 86, 263 rv_op_amoor_w = 87, 264 rv_op_amoand_w = 88, 265 rv_op_amomin_w = 89, 266 rv_op_amomax_w = 90, 267 rv_op_amominu_w = 91, 268 rv_op_amomaxu_w = 92, 269 rv_op_lr_d = 93, 270 rv_op_sc_d = 94, 271 rv_op_amoswap_d = 95, 272 rv_op_amoadd_d = 96, 273 rv_op_amoxor_d = 97, 274 rv_op_amoor_d = 98, 275 rv_op_amoand_d = 99, 276 rv_op_amomin_d = 100, 277 rv_op_amomax_d = 101, 278 rv_op_amominu_d = 102, 279 rv_op_amomaxu_d = 103, 280 rv_op_lr_q = 104, 281 rv_op_sc_q = 105, 282 rv_op_amoswap_q = 106, 283 rv_op_amoadd_q = 107, 284 rv_op_amoxor_q = 108, 285 rv_op_amoor_q = 109, 286 rv_op_amoand_q = 110, 287 rv_op_amomin_q = 111, 288 rv_op_amomax_q = 112, 289 rv_op_amominu_q = 113, 290 rv_op_amomaxu_q = 114, 291 rv_op_ecall = 115, 292 rv_op_ebreak = 116, 293 rv_op_uret = 117, 294 rv_op_sret = 118, 295 rv_op_hret = 119, 296 rv_op_mret = 120, 297 rv_op_dret = 121, 298 rv_op_sfence_vm = 122, 299 rv_op_sfence_vma = 123, 300 rv_op_wfi = 124, 301 rv_op_csrrw = 125, 302 rv_op_csrrs = 126, 303 rv_op_csrrc = 127, 304 rv_op_csrrwi = 128, 305 rv_op_csrrsi = 129, 306 rv_op_csrrci = 130, 307 rv_op_flw = 131, 308 rv_op_fsw = 132, 309 rv_op_fmadd_s = 133, 310 rv_op_fmsub_s = 134, 311 rv_op_fnmsub_s = 135, 312 rv_op_fnmadd_s = 136, 313 rv_op_fadd_s = 137, 314 rv_op_fsub_s = 138, 315 rv_op_fmul_s = 139, 316 rv_op_fdiv_s = 140, 317 rv_op_fsgnj_s = 141, 318 rv_op_fsgnjn_s = 142, 319 rv_op_fsgnjx_s = 143, 320 rv_op_fmin_s = 144, 321 rv_op_fmax_s = 145, 322 rv_op_fsqrt_s = 146, 323 rv_op_fle_s = 147, 324 rv_op_flt_s = 148, 325 rv_op_feq_s = 149, 326 rv_op_fcvt_w_s = 150, 327 rv_op_fcvt_wu_s = 151, 328 rv_op_fcvt_s_w = 152, 329 rv_op_fcvt_s_wu = 153, 330 rv_op_fmv_x_s = 154, 331 rv_op_fclass_s = 155, 332 rv_op_fmv_s_x = 156, 333 rv_op_fcvt_l_s = 157, 334 rv_op_fcvt_lu_s = 158, 335 rv_op_fcvt_s_l = 159, 336 rv_op_fcvt_s_lu = 160, 337 rv_op_fld = 161, 338 rv_op_fsd = 162, 339 rv_op_fmadd_d = 163, 340 rv_op_fmsub_d = 164, 341 rv_op_fnmsub_d = 165, 342 rv_op_fnmadd_d = 166, 343 rv_op_fadd_d = 167, 344 rv_op_fsub_d = 168, 345 rv_op_fmul_d = 169, 346 rv_op_fdiv_d = 170, 347 rv_op_fsgnj_d = 171, 348 rv_op_fsgnjn_d = 172, 349 rv_op_fsgnjx_d = 173, 350 rv_op_fmin_d = 174, 351 rv_op_fmax_d = 175, 352 rv_op_fcvt_s_d = 176, 353 rv_op_fcvt_d_s = 177, 354 rv_op_fsqrt_d = 178, 355 rv_op_fle_d = 179, 356 rv_op_flt_d = 180, 357 rv_op_feq_d = 181, 358 rv_op_fcvt_w_d = 182, 359 rv_op_fcvt_wu_d = 183, 360 rv_op_fcvt_d_w = 184, 361 rv_op_fcvt_d_wu = 185, 362 rv_op_fclass_d = 186, 363 rv_op_fcvt_l_d = 187, 364 rv_op_fcvt_lu_d = 188, 365 rv_op_fmv_x_d = 189, 366 rv_op_fcvt_d_l = 190, 367 rv_op_fcvt_d_lu = 191, 368 rv_op_fmv_d_x = 192, 369 rv_op_flq = 193, 370 rv_op_fsq = 194, 371 rv_op_fmadd_q = 195, 372 rv_op_fmsub_q = 196, 373 rv_op_fnmsub_q = 197, 374 rv_op_fnmadd_q = 198, 375 rv_op_fadd_q = 199, 376 rv_op_fsub_q = 200, 377 rv_op_fmul_q = 201, 378 rv_op_fdiv_q = 202, 379 rv_op_fsgnj_q = 203, 380 rv_op_fsgnjn_q = 204, 381 rv_op_fsgnjx_q = 205, 382 rv_op_fmin_q = 206, 383 rv_op_fmax_q = 207, 384 rv_op_fcvt_s_q = 208, 385 rv_op_fcvt_q_s = 209, 386 rv_op_fcvt_d_q = 210, 387 rv_op_fcvt_q_d = 211, 388 rv_op_fsqrt_q = 212, 389 rv_op_fle_q = 213, 390 rv_op_flt_q = 214, 391 rv_op_feq_q = 215, 392 rv_op_fcvt_w_q = 216, 393 rv_op_fcvt_wu_q = 217, 394 rv_op_fcvt_q_w = 218, 395 rv_op_fcvt_q_wu = 219, 396 rv_op_fclass_q = 220, 397 rv_op_fcvt_l_q = 221, 398 rv_op_fcvt_lu_q = 222, 399 rv_op_fcvt_q_l = 223, 400 rv_op_fcvt_q_lu = 224, 401 rv_op_fmv_x_q = 225, 402 rv_op_fmv_q_x = 226, 403 rv_op_c_addi4spn = 227, 404 rv_op_c_fld = 228, 405 rv_op_c_lw = 229, 406 rv_op_c_flw = 230, 407 rv_op_c_fsd = 231, 408 rv_op_c_sw = 232, 409 rv_op_c_fsw = 233, 410 rv_op_c_nop = 234, 411 rv_op_c_addi = 235, 412 rv_op_c_jal = 236, 413 rv_op_c_li = 237, 414 rv_op_c_addi16sp = 238, 415 rv_op_c_lui = 239, 416 rv_op_c_srli = 240, 417 rv_op_c_srai = 241, 418 rv_op_c_andi = 242, 419 rv_op_c_sub = 243, 420 rv_op_c_xor = 244, 421 rv_op_c_or = 245, 422 rv_op_c_and = 246, 423 rv_op_c_subw = 247, 424 rv_op_c_addw = 248, 425 rv_op_c_j = 249, 426 rv_op_c_beqz = 250, 427 rv_op_c_bnez = 251, 428 rv_op_c_slli = 252, 429 rv_op_c_fldsp = 253, 430 rv_op_c_lwsp = 254, 431 rv_op_c_flwsp = 255, 432 rv_op_c_jr = 256, 433 rv_op_c_mv = 257, 434 rv_op_c_ebreak = 258, 435 rv_op_c_jalr = 259, 436 rv_op_c_add = 260, 437 rv_op_c_fsdsp = 261, 438 rv_op_c_swsp = 262, 439 rv_op_c_fswsp = 263, 440 rv_op_c_ld = 264, 441 rv_op_c_sd = 265, 442 rv_op_c_addiw = 266, 443 rv_op_c_ldsp = 267, 444 rv_op_c_sdsp = 268, 445 rv_op_c_lq = 269, 446 rv_op_c_sq = 270, 447 rv_op_c_lqsp = 271, 448 rv_op_c_sqsp = 272, 449 rv_op_nop = 273, 450 rv_op_mv = 274, 451 rv_op_not = 275, 452 rv_op_neg = 276, 453 rv_op_negw = 277, 454 rv_op_sext_w = 278, 455 rv_op_seqz = 279, 456 rv_op_snez = 280, 457 rv_op_sltz = 281, 458 rv_op_sgtz = 282, 459 rv_op_fmv_s = 283, 460 rv_op_fabs_s = 284, 461 rv_op_fneg_s = 285, 462 rv_op_fmv_d = 286, 463 rv_op_fabs_d = 287, 464 rv_op_fneg_d = 288, 465 rv_op_fmv_q = 289, 466 rv_op_fabs_q = 290, 467 rv_op_fneg_q = 291, 468 rv_op_beqz = 292, 469 rv_op_bnez = 293, 470 rv_op_blez = 294, 471 rv_op_bgez = 295, 472 rv_op_bltz = 296, 473 rv_op_bgtz = 297, 474 rv_op_ble = 298, 475 rv_op_bleu = 299, 476 rv_op_bgt = 300, 477 rv_op_bgtu = 301, 478 rv_op_j = 302, 479 rv_op_ret = 303, 480 rv_op_jr = 304, 481 rv_op_rdcycle = 305, 482 rv_op_rdtime = 306, 483 rv_op_rdinstret = 307, 484 rv_op_rdcycleh = 308, 485 rv_op_rdtimeh = 309, 486 rv_op_rdinstreth = 310, 487 rv_op_frcsr = 311, 488 rv_op_frrm = 312, 489 rv_op_frflags = 313, 490 rv_op_fscsr = 314, 491 rv_op_fsrm = 315, 492 rv_op_fsflags = 316, 493 rv_op_fsrmi = 317, 494 rv_op_fsflagsi = 318, 495 rv_op_bseti = 319, 496 rv_op_bclri = 320, 497 rv_op_binvi = 321, 498 rv_op_bexti = 322, 499 rv_op_rori = 323, 500 rv_op_clz = 324, 501 rv_op_ctz = 325, 502 rv_op_cpop = 326, 503 rv_op_sext_h = 327, 504 rv_op_sext_b = 328, 505 rv_op_xnor = 329, 506 rv_op_orn = 330, 507 rv_op_andn = 331, 508 rv_op_rol = 332, 509 rv_op_ror = 333, 510 rv_op_sh1add = 334, 511 rv_op_sh2add = 335, 512 rv_op_sh3add = 336, 513 rv_op_sh1add_uw = 337, 514 rv_op_sh2add_uw = 338, 515 rv_op_sh3add_uw = 339, 516 rv_op_clmul = 340, 517 rv_op_clmulr = 341, 518 rv_op_clmulh = 342, 519 rv_op_min = 343, 520 rv_op_minu = 344, 521 rv_op_max = 345, 522 rv_op_maxu = 346, 523 rv_op_clzw = 347, 524 rv_op_ctzw = 348, 525 rv_op_cpopw = 349, 526 rv_op_slli_uw = 350, 527 rv_op_add_uw = 351, 528 rv_op_rolw = 352, 529 rv_op_rorw = 353, 530 rv_op_rev8 = 354, 531 rv_op_zext_h = 355, 532 rv_op_roriw = 356, 533 rv_op_orc_b = 357, 534 rv_op_bset = 358, 535 rv_op_bclr = 359, 536 rv_op_binv = 360, 537 rv_op_bext = 361, 538 rv_op_aes32esmi = 362, 539 rv_op_aes32esi = 363, 540 rv_op_aes32dsmi = 364, 541 rv_op_aes32dsi = 365, 542 rv_op_aes64ks1i = 366, 543 rv_op_aes64ks2 = 367, 544 rv_op_aes64im = 368, 545 rv_op_aes64esm = 369, 546 rv_op_aes64es = 370, 547 rv_op_aes64dsm = 371, 548 rv_op_aes64ds = 372, 549 rv_op_sha256sig0 = 373, 550 rv_op_sha256sig1 = 374, 551 rv_op_sha256sum0 = 375, 552 rv_op_sha256sum1 = 376, 553 rv_op_sha512sig0 = 377, 554 rv_op_sha512sig1 = 378, 555 rv_op_sha512sum0 = 379, 556 rv_op_sha512sum1 = 380, 557 rv_op_sha512sum0r = 381, 558 rv_op_sha512sum1r = 382, 559 rv_op_sha512sig0l = 383, 560 rv_op_sha512sig0h = 384, 561 rv_op_sha512sig1l = 385, 562 rv_op_sha512sig1h = 386, 563 rv_op_sm3p0 = 387, 564 rv_op_sm3p1 = 388, 565 rv_op_sm4ed = 389, 566 rv_op_sm4ks = 390, 567 rv_op_brev8 = 391, 568 rv_op_pack = 392, 569 rv_op_packh = 393, 570 rv_op_packw = 394, 571 rv_op_unzip = 395, 572 rv_op_zip = 396, 573 rv_op_xperm4 = 397, 574 rv_op_xperm8 = 398, 575 rv_op_vle8_v = 399, 576 rv_op_vle16_v = 400, 577 rv_op_vle32_v = 401, 578 rv_op_vle64_v = 402, 579 rv_op_vse8_v = 403, 580 rv_op_vse16_v = 404, 581 rv_op_vse32_v = 405, 582 rv_op_vse64_v = 406, 583 rv_op_vlm_v = 407, 584 rv_op_vsm_v = 408, 585 rv_op_vlse8_v = 409, 586 rv_op_vlse16_v = 410, 587 rv_op_vlse32_v = 411, 588 rv_op_vlse64_v = 412, 589 rv_op_vsse8_v = 413, 590 rv_op_vsse16_v = 414, 591 rv_op_vsse32_v = 415, 592 rv_op_vsse64_v = 416, 593 rv_op_vluxei8_v = 417, 594 rv_op_vluxei16_v = 418, 595 rv_op_vluxei32_v = 419, 596 rv_op_vluxei64_v = 420, 597 rv_op_vloxei8_v = 421, 598 rv_op_vloxei16_v = 422, 599 rv_op_vloxei32_v = 423, 600 rv_op_vloxei64_v = 424, 601 rv_op_vsuxei8_v = 425, 602 rv_op_vsuxei16_v = 426, 603 rv_op_vsuxei32_v = 427, 604 rv_op_vsuxei64_v = 428, 605 rv_op_vsoxei8_v = 429, 606 rv_op_vsoxei16_v = 430, 607 rv_op_vsoxei32_v = 431, 608 rv_op_vsoxei64_v = 432, 609 rv_op_vle8ff_v = 433, 610 rv_op_vle16ff_v = 434, 611 rv_op_vle32ff_v = 435, 612 rv_op_vle64ff_v = 436, 613 rv_op_vl1re8_v = 437, 614 rv_op_vl1re16_v = 438, 615 rv_op_vl1re32_v = 439, 616 rv_op_vl1re64_v = 440, 617 rv_op_vl2re8_v = 441, 618 rv_op_vl2re16_v = 442, 619 rv_op_vl2re32_v = 443, 620 rv_op_vl2re64_v = 444, 621 rv_op_vl4re8_v = 445, 622 rv_op_vl4re16_v = 446, 623 rv_op_vl4re32_v = 447, 624 rv_op_vl4re64_v = 448, 625 rv_op_vl8re8_v = 449, 626 rv_op_vl8re16_v = 450, 627 rv_op_vl8re32_v = 451, 628 rv_op_vl8re64_v = 452, 629 rv_op_vs1r_v = 453, 630 rv_op_vs2r_v = 454, 631 rv_op_vs4r_v = 455, 632 rv_op_vs8r_v = 456, 633 rv_op_vadd_vv = 457, 634 rv_op_vadd_vx = 458, 635 rv_op_vadd_vi = 459, 636 rv_op_vsub_vv = 460, 637 rv_op_vsub_vx = 461, 638 rv_op_vrsub_vx = 462, 639 rv_op_vrsub_vi = 463, 640 rv_op_vwaddu_vv = 464, 641 rv_op_vwaddu_vx = 465, 642 rv_op_vwadd_vv = 466, 643 rv_op_vwadd_vx = 467, 644 rv_op_vwsubu_vv = 468, 645 rv_op_vwsubu_vx = 469, 646 rv_op_vwsub_vv = 470, 647 rv_op_vwsub_vx = 471, 648 rv_op_vwaddu_wv = 472, 649 rv_op_vwaddu_wx = 473, 650 rv_op_vwadd_wv = 474, 651 rv_op_vwadd_wx = 475, 652 rv_op_vwsubu_wv = 476, 653 rv_op_vwsubu_wx = 477, 654 rv_op_vwsub_wv = 478, 655 rv_op_vwsub_wx = 479, 656 rv_op_vadc_vvm = 480, 657 rv_op_vadc_vxm = 481, 658 rv_op_vadc_vim = 482, 659 rv_op_vmadc_vvm = 483, 660 rv_op_vmadc_vxm = 484, 661 rv_op_vmadc_vim = 485, 662 rv_op_vsbc_vvm = 486, 663 rv_op_vsbc_vxm = 487, 664 rv_op_vmsbc_vvm = 488, 665 rv_op_vmsbc_vxm = 489, 666 rv_op_vand_vv = 490, 667 rv_op_vand_vx = 491, 668 rv_op_vand_vi = 492, 669 rv_op_vor_vv = 493, 670 rv_op_vor_vx = 494, 671 rv_op_vor_vi = 495, 672 rv_op_vxor_vv = 496, 673 rv_op_vxor_vx = 497, 674 rv_op_vxor_vi = 498, 675 rv_op_vsll_vv = 499, 676 rv_op_vsll_vx = 500, 677 rv_op_vsll_vi = 501, 678 rv_op_vsrl_vv = 502, 679 rv_op_vsrl_vx = 503, 680 rv_op_vsrl_vi = 504, 681 rv_op_vsra_vv = 505, 682 rv_op_vsra_vx = 506, 683 rv_op_vsra_vi = 507, 684 rv_op_vnsrl_wv = 508, 685 rv_op_vnsrl_wx = 509, 686 rv_op_vnsrl_wi = 510, 687 rv_op_vnsra_wv = 511, 688 rv_op_vnsra_wx = 512, 689 rv_op_vnsra_wi = 513, 690 rv_op_vmseq_vv = 514, 691 rv_op_vmseq_vx = 515, 692 rv_op_vmseq_vi = 516, 693 rv_op_vmsne_vv = 517, 694 rv_op_vmsne_vx = 518, 695 rv_op_vmsne_vi = 519, 696 rv_op_vmsltu_vv = 520, 697 rv_op_vmsltu_vx = 521, 698 rv_op_vmslt_vv = 522, 699 rv_op_vmslt_vx = 523, 700 rv_op_vmsleu_vv = 524, 701 rv_op_vmsleu_vx = 525, 702 rv_op_vmsleu_vi = 526, 703 rv_op_vmsle_vv = 527, 704 rv_op_vmsle_vx = 528, 705 rv_op_vmsle_vi = 529, 706 rv_op_vmsgtu_vx = 530, 707 rv_op_vmsgtu_vi = 531, 708 rv_op_vmsgt_vx = 532, 709 rv_op_vmsgt_vi = 533, 710 rv_op_vminu_vv = 534, 711 rv_op_vminu_vx = 535, 712 rv_op_vmin_vv = 536, 713 rv_op_vmin_vx = 537, 714 rv_op_vmaxu_vv = 538, 715 rv_op_vmaxu_vx = 539, 716 rv_op_vmax_vv = 540, 717 rv_op_vmax_vx = 541, 718 rv_op_vmul_vv = 542, 719 rv_op_vmul_vx = 543, 720 rv_op_vmulh_vv = 544, 721 rv_op_vmulh_vx = 545, 722 rv_op_vmulhu_vv = 546, 723 rv_op_vmulhu_vx = 547, 724 rv_op_vmulhsu_vv = 548, 725 rv_op_vmulhsu_vx = 549, 726 rv_op_vdivu_vv = 550, 727 rv_op_vdivu_vx = 551, 728 rv_op_vdiv_vv = 552, 729 rv_op_vdiv_vx = 553, 730 rv_op_vremu_vv = 554, 731 rv_op_vremu_vx = 555, 732 rv_op_vrem_vv = 556, 733 rv_op_vrem_vx = 557, 734 rv_op_vwmulu_vv = 558, 735 rv_op_vwmulu_vx = 559, 736 rv_op_vwmulsu_vv = 560, 737 rv_op_vwmulsu_vx = 561, 738 rv_op_vwmul_vv = 562, 739 rv_op_vwmul_vx = 563, 740 rv_op_vmacc_vv = 564, 741 rv_op_vmacc_vx = 565, 742 rv_op_vnmsac_vv = 566, 743 rv_op_vnmsac_vx = 567, 744 rv_op_vmadd_vv = 568, 745 rv_op_vmadd_vx = 569, 746 rv_op_vnmsub_vv = 570, 747 rv_op_vnmsub_vx = 571, 748 rv_op_vwmaccu_vv = 572, 749 rv_op_vwmaccu_vx = 573, 750 rv_op_vwmacc_vv = 574, 751 rv_op_vwmacc_vx = 575, 752 rv_op_vwmaccsu_vv = 576, 753 rv_op_vwmaccsu_vx = 577, 754 rv_op_vwmaccus_vx = 578, 755 rv_op_vmv_v_v = 579, 756 rv_op_vmv_v_x = 580, 757 rv_op_vmv_v_i = 581, 758 rv_op_vmerge_vvm = 582, 759 rv_op_vmerge_vxm = 583, 760 rv_op_vmerge_vim = 584, 761 rv_op_vsaddu_vv = 585, 762 rv_op_vsaddu_vx = 586, 763 rv_op_vsaddu_vi = 587, 764 rv_op_vsadd_vv = 588, 765 rv_op_vsadd_vx = 589, 766 rv_op_vsadd_vi = 590, 767 rv_op_vssubu_vv = 591, 768 rv_op_vssubu_vx = 592, 769 rv_op_vssub_vv = 593, 770 rv_op_vssub_vx = 594, 771 rv_op_vaadd_vv = 595, 772 rv_op_vaadd_vx = 596, 773 rv_op_vaaddu_vv = 597, 774 rv_op_vaaddu_vx = 598, 775 rv_op_vasub_vv = 599, 776 rv_op_vasub_vx = 600, 777 rv_op_vasubu_vv = 601, 778 rv_op_vasubu_vx = 602, 779 rv_op_vsmul_vv = 603, 780 rv_op_vsmul_vx = 604, 781 rv_op_vssrl_vv = 605, 782 rv_op_vssrl_vx = 606, 783 rv_op_vssrl_vi = 607, 784 rv_op_vssra_vv = 608, 785 rv_op_vssra_vx = 609, 786 rv_op_vssra_vi = 610, 787 rv_op_vnclipu_wv = 611, 788 rv_op_vnclipu_wx = 612, 789 rv_op_vnclipu_wi = 613, 790 rv_op_vnclip_wv = 614, 791 rv_op_vnclip_wx = 615, 792 rv_op_vnclip_wi = 616, 793 rv_op_vfadd_vv = 617, 794 rv_op_vfadd_vf = 618, 795 rv_op_vfsub_vv = 619, 796 rv_op_vfsub_vf = 620, 797 rv_op_vfrsub_vf = 621, 798 rv_op_vfwadd_vv = 622, 799 rv_op_vfwadd_vf = 623, 800 rv_op_vfwadd_wv = 624, 801 rv_op_vfwadd_wf = 625, 802 rv_op_vfwsub_vv = 626, 803 rv_op_vfwsub_vf = 627, 804 rv_op_vfwsub_wv = 628, 805 rv_op_vfwsub_wf = 629, 806 rv_op_vfmul_vv = 630, 807 rv_op_vfmul_vf = 631, 808 rv_op_vfdiv_vv = 632, 809 rv_op_vfdiv_vf = 633, 810 rv_op_vfrdiv_vf = 634, 811 rv_op_vfwmul_vv = 635, 812 rv_op_vfwmul_vf = 636, 813 rv_op_vfmacc_vv = 637, 814 rv_op_vfmacc_vf = 638, 815 rv_op_vfnmacc_vv = 639, 816 rv_op_vfnmacc_vf = 640, 817 rv_op_vfmsac_vv = 641, 818 rv_op_vfmsac_vf = 642, 819 rv_op_vfnmsac_vv = 643, 820 rv_op_vfnmsac_vf = 644, 821 rv_op_vfmadd_vv = 645, 822 rv_op_vfmadd_vf = 646, 823 rv_op_vfnmadd_vv = 647, 824 rv_op_vfnmadd_vf = 648, 825 rv_op_vfmsub_vv = 649, 826 rv_op_vfmsub_vf = 650, 827 rv_op_vfnmsub_vv = 651, 828 rv_op_vfnmsub_vf = 652, 829 rv_op_vfwmacc_vv = 653, 830 rv_op_vfwmacc_vf = 654, 831 rv_op_vfwnmacc_vv = 655, 832 rv_op_vfwnmacc_vf = 656, 833 rv_op_vfwmsac_vv = 657, 834 rv_op_vfwmsac_vf = 658, 835 rv_op_vfwnmsac_vv = 659, 836 rv_op_vfwnmsac_vf = 660, 837 rv_op_vfsqrt_v = 661, 838 rv_op_vfrsqrt7_v = 662, 839 rv_op_vfrec7_v = 663, 840 rv_op_vfmin_vv = 664, 841 rv_op_vfmin_vf = 665, 842 rv_op_vfmax_vv = 666, 843 rv_op_vfmax_vf = 667, 844 rv_op_vfsgnj_vv = 668, 845 rv_op_vfsgnj_vf = 669, 846 rv_op_vfsgnjn_vv = 670, 847 rv_op_vfsgnjn_vf = 671, 848 rv_op_vfsgnjx_vv = 672, 849 rv_op_vfsgnjx_vf = 673, 850 rv_op_vfslide1up_vf = 674, 851 rv_op_vfslide1down_vf = 675, 852 rv_op_vmfeq_vv = 676, 853 rv_op_vmfeq_vf = 677, 854 rv_op_vmfne_vv = 678, 855 rv_op_vmfne_vf = 679, 856 rv_op_vmflt_vv = 680, 857 rv_op_vmflt_vf = 681, 858 rv_op_vmfle_vv = 682, 859 rv_op_vmfle_vf = 683, 860 rv_op_vmfgt_vf = 684, 861 rv_op_vmfge_vf = 685, 862 rv_op_vfclass_v = 686, 863 rv_op_vfmerge_vfm = 687, 864 rv_op_vfmv_v_f = 688, 865 rv_op_vfcvt_xu_f_v = 689, 866 rv_op_vfcvt_x_f_v = 690, 867 rv_op_vfcvt_f_xu_v = 691, 868 rv_op_vfcvt_f_x_v = 692, 869 rv_op_vfcvt_rtz_xu_f_v = 693, 870 rv_op_vfcvt_rtz_x_f_v = 694, 871 rv_op_vfwcvt_xu_f_v = 695, 872 rv_op_vfwcvt_x_f_v = 696, 873 rv_op_vfwcvt_f_xu_v = 697, 874 rv_op_vfwcvt_f_x_v = 698, 875 rv_op_vfwcvt_f_f_v = 699, 876 rv_op_vfwcvt_rtz_xu_f_v = 700, 877 rv_op_vfwcvt_rtz_x_f_v = 701, 878 rv_op_vfncvt_xu_f_w = 702, 879 rv_op_vfncvt_x_f_w = 703, 880 rv_op_vfncvt_f_xu_w = 704, 881 rv_op_vfncvt_f_x_w = 705, 882 rv_op_vfncvt_f_f_w = 706, 883 rv_op_vfncvt_rod_f_f_w = 707, 884 rv_op_vfncvt_rtz_xu_f_w = 708, 885 rv_op_vfncvt_rtz_x_f_w = 709, 886 rv_op_vredsum_vs = 710, 887 rv_op_vredand_vs = 711, 888 rv_op_vredor_vs = 712, 889 rv_op_vredxor_vs = 713, 890 rv_op_vredminu_vs = 714, 891 rv_op_vredmin_vs = 715, 892 rv_op_vredmaxu_vs = 716, 893 rv_op_vredmax_vs = 717, 894 rv_op_vwredsumu_vs = 718, 895 rv_op_vwredsum_vs = 719, 896 rv_op_vfredusum_vs = 720, 897 rv_op_vfredosum_vs = 721, 898 rv_op_vfredmin_vs = 722, 899 rv_op_vfredmax_vs = 723, 900 rv_op_vfwredusum_vs = 724, 901 rv_op_vfwredosum_vs = 725, 902 rv_op_vmand_mm = 726, 903 rv_op_vmnand_mm = 727, 904 rv_op_vmandn_mm = 728, 905 rv_op_vmxor_mm = 729, 906 rv_op_vmor_mm = 730, 907 rv_op_vmnor_mm = 731, 908 rv_op_vmorn_mm = 732, 909 rv_op_vmxnor_mm = 733, 910 rv_op_vcpop_m = 734, 911 rv_op_vfirst_m = 735, 912 rv_op_vmsbf_m = 736, 913 rv_op_vmsif_m = 737, 914 rv_op_vmsof_m = 738, 915 rv_op_viota_m = 739, 916 rv_op_vid_v = 740, 917 rv_op_vmv_x_s = 741, 918 rv_op_vmv_s_x = 742, 919 rv_op_vfmv_f_s = 743, 920 rv_op_vfmv_s_f = 744, 921 rv_op_vslideup_vx = 745, 922 rv_op_vslideup_vi = 746, 923 rv_op_vslide1up_vx = 747, 924 rv_op_vslidedown_vx = 748, 925 rv_op_vslidedown_vi = 749, 926 rv_op_vslide1down_vx = 750, 927 rv_op_vrgather_vv = 751, 928 rv_op_vrgatherei16_vv = 752, 929 rv_op_vrgather_vx = 753, 930 rv_op_vrgather_vi = 754, 931 rv_op_vcompress_vm = 755, 932 rv_op_vmv1r_v = 756, 933 rv_op_vmv2r_v = 757, 934 rv_op_vmv4r_v = 758, 935 rv_op_vmv8r_v = 759, 936 rv_op_vzext_vf2 = 760, 937 rv_op_vzext_vf4 = 761, 938 rv_op_vzext_vf8 = 762, 939 rv_op_vsext_vf2 = 763, 940 rv_op_vsext_vf4 = 764, 941 rv_op_vsext_vf8 = 765, 942 rv_op_vsetvli = 766, 943 rv_op_vsetivli = 767, 944 rv_op_vsetvl = 768, 945 rv_op_c_zext_b = 769, 946 rv_op_c_sext_b = 770, 947 rv_op_c_zext_h = 771, 948 rv_op_c_sext_h = 772, 949 rv_op_c_zext_w = 773, 950 rv_op_c_not = 774, 951 rv_op_c_mul = 775, 952 rv_op_c_lbu = 776, 953 rv_op_c_lhu = 777, 954 rv_op_c_lh = 778, 955 rv_op_c_sb = 779, 956 rv_op_c_sh = 780, 957 rv_op_cm_push = 781, 958 rv_op_cm_pop = 782, 959 rv_op_cm_popret = 783, 960 rv_op_cm_popretz = 784, 961 rv_op_cm_mva01s = 785, 962 rv_op_cm_mvsa01 = 786, 963 rv_op_cm_jt = 787, 964 rv_op_cm_jalt = 788, 965 } rv_op; 966 967 /* structures */ 968 969 typedef struct { 970 uint64_t pc; 971 uint64_t inst; 972 int32_t imm; 973 uint16_t op; 974 uint8_t codec; 975 uint8_t rd; 976 uint8_t rs1; 977 uint8_t rs2; 978 uint8_t rs3; 979 uint8_t rm; 980 uint8_t pred; 981 uint8_t succ; 982 uint8_t aq; 983 uint8_t rl; 984 uint8_t bs; 985 uint8_t rnum; 986 uint8_t vm; 987 uint32_t vzimm; 988 uint8_t rlist; 989 } rv_decode; 990 991 typedef struct { 992 const int op; 993 const rvc_constraint *constraints; 994 } rv_comp_data; 995 996 enum { 997 rvcd_imm_nz = 0x1 998 }; 999 1000 typedef struct { 1001 const char * const name; 1002 const rv_codec codec; 1003 const char * const format; 1004 const rv_comp_data *pseudo; 1005 const short decomp_rv32; 1006 const short decomp_rv64; 1007 const short decomp_rv128; 1008 const short decomp_data; 1009 } rv_opcode_data; 1010 1011 /* register names */ 1012 1013 static const char rv_ireg_name_sym[32][5] = { 1014 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 1015 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 1016 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 1017 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", 1018 }; 1019 1020 static const char rv_freg_name_sym[32][5] = { 1021 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", 1022 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", 1023 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", 1024 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11", 1025 }; 1026 1027 static const char rv_vreg_name_sym[32][4] = { 1028 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1029 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1030 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1031 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 1032 }; 1033 1034 /* instruction formats */ 1035 1036 #define rv_fmt_none "O\t" 1037 #define rv_fmt_rs1 "O\t1" 1038 #define rv_fmt_offset "O\to" 1039 #define rv_fmt_pred_succ "O\tp,s" 1040 #define rv_fmt_rs1_rs2 "O\t1,2" 1041 #define rv_fmt_rd_imm "O\t0,i" 1042 #define rv_fmt_rd_offset "O\t0,o" 1043 #define rv_fmt_rd_rs1_rs2 "O\t0,1,2" 1044 #define rv_fmt_frd_rs1 "O\t3,1" 1045 #define rv_fmt_frd_frs1 "O\t3,4" 1046 #define rv_fmt_rd_frs1 "O\t0,4" 1047 #define rv_fmt_rd_frs1_frs2 "O\t0,4,5" 1048 #define rv_fmt_frd_frs1_frs2 "O\t3,4,5" 1049 #define rv_fmt_rm_frd_frs1 "O\tr,3,4" 1050 #define rv_fmt_rm_frd_rs1 "O\tr,3,1" 1051 #define rv_fmt_rm_rd_frs1 "O\tr,0,4" 1052 #define rv_fmt_rm_frd_frs1_frs2 "O\tr,3,4,5" 1053 #define rv_fmt_rm_frd_frs1_frs2_frs3 "O\tr,3,4,5,6" 1054 #define rv_fmt_rd_rs1_imm "O\t0,1,i" 1055 #define rv_fmt_rd_rs1_offset "O\t0,1,i" 1056 #define rv_fmt_rd_offset_rs1 "O\t0,i(1)" 1057 #define rv_fmt_frd_offset_rs1 "O\t3,i(1)" 1058 #define rv_fmt_rd_csr_rs1 "O\t0,c,1" 1059 #define rv_fmt_rd_csr_zimm "O\t0,c,7" 1060 #define rv_fmt_rs2_offset_rs1 "O\t2,i(1)" 1061 #define rv_fmt_frs2_offset_rs1 "O\t5,i(1)" 1062 #define rv_fmt_rs1_rs2_offset "O\t1,2,o" 1063 #define rv_fmt_rs2_rs1_offset "O\t2,1,o" 1064 #define rv_fmt_aqrl_rd_rs2_rs1 "OAR\t0,2,(1)" 1065 #define rv_fmt_aqrl_rd_rs1 "OAR\t0,(1)" 1066 #define rv_fmt_rd "O\t0" 1067 #define rv_fmt_rd_zimm "O\t0,7" 1068 #define rv_fmt_rd_rs1 "O\t0,1" 1069 #define rv_fmt_rd_rs2 "O\t0,2" 1070 #define rv_fmt_rs1_offset "O\t1,o" 1071 #define rv_fmt_rs2_offset "O\t2,o" 1072 #define rv_fmt_rs1_rs2_bs "O\t1,2,b" 1073 #define rv_fmt_rd_rs1_rnum "O\t0,1,n" 1074 #define rv_fmt_ldst_vd_rs1_vm "O\tD,(1)m" 1075 #define rv_fmt_ldst_vd_rs1_rs2_vm "O\tD,(1),2m" 1076 #define rv_fmt_ldst_vd_rs1_vs2_vm "O\tD,(1),Fm" 1077 #define rv_fmt_vd_vs2_vs1 "O\tD,F,E" 1078 #define rv_fmt_vd_vs2_vs1_vl "O\tD,F,El" 1079 #define rv_fmt_vd_vs2_vs1_vm "O\tD,F,Em" 1080 #define rv_fmt_vd_vs2_rs1_vl "O\tD,F,1l" 1081 #define rv_fmt_vd_vs2_fs1_vl "O\tD,F,4l" 1082 #define rv_fmt_vd_vs2_rs1_vm "O\tD,F,1m" 1083 #define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m" 1084 #define rv_fmt_vd_vs2_imm_vl "O\tD,F,il" 1085 #define rv_fmt_vd_vs2_imm_vm "O\tD,F,im" 1086 #define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um" 1087 #define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm" 1088 #define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm" 1089 #define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm" 1090 #define rv_fmt_vd_vs1 "O\tD,E" 1091 #define rv_fmt_vd_rs1 "O\tD,1" 1092 #define rv_fmt_vd_fs1 "O\tD,4" 1093 #define rv_fmt_vd_imm "O\tD,i" 1094 #define rv_fmt_vd_vs2 "O\tD,F" 1095 #define rv_fmt_vd_vs2_vm "O\tD,Fm" 1096 #define rv_fmt_rd_vs2_vm "O\t0,Fm" 1097 #define rv_fmt_rd_vs2 "O\t0,F" 1098 #define rv_fmt_fd_vs2 "O\t3,F" 1099 #define rv_fmt_vd_vm "O\tDm" 1100 #define rv_fmt_vsetvli "O\t0,1,v" 1101 #define rv_fmt_vsetivli "O\t0,u,v" 1102 #define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)" 1103 #define rv_fmt_push_rlist "O\tx,-i" 1104 #define rv_fmt_pop_rlist "O\tx,i" 1105 #define rv_fmt_zcmt_index "O\ti" 1106 1107 /* pseudo-instruction constraints */ 1108 1109 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end }; 1110 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end }; 1111 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end }; 1112 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; 1113 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end }; 1114 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end }; 1115 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end }; 1116 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end }; 1117 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end }; 1118 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end }; 1119 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end }; 1120 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end }; 1121 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1122 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1123 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1124 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1125 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1126 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1127 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1128 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1129 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1130 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end }; 1131 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end }; 1132 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end }; 1133 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end }; 1134 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end }; 1135 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end }; 1136 static const rvc_constraint rvcc_ble[] = { rvc_end }; 1137 static const rvc_constraint rvcc_bleu[] = { rvc_end }; 1138 static const rvc_constraint rvcc_bgt[] = { rvc_end }; 1139 static const rvc_constraint rvcc_bgtu[] = { rvc_end }; 1140 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end }; 1141 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end }; 1142 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end }; 1143 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end }; 1144 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end }; 1145 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end }; 1146 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end }; 1147 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end }; 1148 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, 1149 rvc_csr_eq_0xc82, rvc_end }; 1150 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end }; 1151 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end }; 1152 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end }; 1153 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end }; 1154 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end }; 1155 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end }; 1156 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end }; 1157 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end }; 1158 1159 /* pseudo-instruction metadata */ 1160 1161 static const rv_comp_data rvcp_jal[] = { 1162 { rv_op_j, rvcc_j }, 1163 { rv_op_jal, rvcc_jal }, 1164 { rv_op_illegal, NULL } 1165 }; 1166 1167 static const rv_comp_data rvcp_jalr[] = { 1168 { rv_op_ret, rvcc_ret }, 1169 { rv_op_jr, rvcc_jr }, 1170 { rv_op_jalr, rvcc_jalr }, 1171 { rv_op_illegal, NULL } 1172 }; 1173 1174 static const rv_comp_data rvcp_beq[] = { 1175 { rv_op_beqz, rvcc_beqz }, 1176 { rv_op_illegal, NULL } 1177 }; 1178 1179 static const rv_comp_data rvcp_bne[] = { 1180 { rv_op_bnez, rvcc_bnez }, 1181 { rv_op_illegal, NULL } 1182 }; 1183 1184 static const rv_comp_data rvcp_blt[] = { 1185 { rv_op_bltz, rvcc_bltz }, 1186 { rv_op_bgtz, rvcc_bgtz }, 1187 { rv_op_bgt, rvcc_bgt }, 1188 { rv_op_illegal, NULL } 1189 }; 1190 1191 static const rv_comp_data rvcp_bge[] = { 1192 { rv_op_blez, rvcc_blez }, 1193 { rv_op_bgez, rvcc_bgez }, 1194 { rv_op_ble, rvcc_ble }, 1195 { rv_op_illegal, NULL } 1196 }; 1197 1198 static const rv_comp_data rvcp_bltu[] = { 1199 { rv_op_bgtu, rvcc_bgtu }, 1200 { rv_op_illegal, NULL } 1201 }; 1202 1203 static const rv_comp_data rvcp_bgeu[] = { 1204 { rv_op_bleu, rvcc_bleu }, 1205 { rv_op_illegal, NULL } 1206 }; 1207 1208 static const rv_comp_data rvcp_addi[] = { 1209 { rv_op_nop, rvcc_nop }, 1210 { rv_op_mv, rvcc_mv }, 1211 { rv_op_illegal, NULL } 1212 }; 1213 1214 static const rv_comp_data rvcp_sltiu[] = { 1215 { rv_op_seqz, rvcc_seqz }, 1216 { rv_op_illegal, NULL } 1217 }; 1218 1219 static const rv_comp_data rvcp_xori[] = { 1220 { rv_op_not, rvcc_not }, 1221 { rv_op_illegal, NULL } 1222 }; 1223 1224 static const rv_comp_data rvcp_sub[] = { 1225 { rv_op_neg, rvcc_neg }, 1226 { rv_op_illegal, NULL } 1227 }; 1228 1229 static const rv_comp_data rvcp_slt[] = { 1230 { rv_op_sltz, rvcc_sltz }, 1231 { rv_op_sgtz, rvcc_sgtz }, 1232 { rv_op_illegal, NULL } 1233 }; 1234 1235 static const rv_comp_data rvcp_sltu[] = { 1236 { rv_op_snez, rvcc_snez }, 1237 { rv_op_illegal, NULL } 1238 }; 1239 1240 static const rv_comp_data rvcp_addiw[] = { 1241 { rv_op_sext_w, rvcc_sext_w }, 1242 { rv_op_illegal, NULL } 1243 }; 1244 1245 static const rv_comp_data rvcp_subw[] = { 1246 { rv_op_negw, rvcc_negw }, 1247 { rv_op_illegal, NULL } 1248 }; 1249 1250 static const rv_comp_data rvcp_csrrw[] = { 1251 { rv_op_fscsr, rvcc_fscsr }, 1252 { rv_op_fsrm, rvcc_fsrm }, 1253 { rv_op_fsflags, rvcc_fsflags }, 1254 { rv_op_illegal, NULL } 1255 }; 1256 1257 1258 static const rv_comp_data rvcp_csrrs[] = { 1259 { rv_op_rdcycle, rvcc_rdcycle }, 1260 { rv_op_rdtime, rvcc_rdtime }, 1261 { rv_op_rdinstret, rvcc_rdinstret }, 1262 { rv_op_rdcycleh, rvcc_rdcycleh }, 1263 { rv_op_rdtimeh, rvcc_rdtimeh }, 1264 { rv_op_rdinstreth, rvcc_rdinstreth }, 1265 { rv_op_frcsr, rvcc_frcsr }, 1266 { rv_op_frrm, rvcc_frrm }, 1267 { rv_op_frflags, rvcc_frflags }, 1268 { rv_op_illegal, NULL } 1269 }; 1270 1271 static const rv_comp_data rvcp_csrrwi[] = { 1272 { rv_op_fsrmi, rvcc_fsrmi }, 1273 { rv_op_fsflagsi, rvcc_fsflagsi }, 1274 { rv_op_illegal, NULL } 1275 }; 1276 1277 static const rv_comp_data rvcp_fsgnj_s[] = { 1278 { rv_op_fmv_s, rvcc_fmv_s }, 1279 { rv_op_illegal, NULL } 1280 }; 1281 1282 static const rv_comp_data rvcp_fsgnjn_s[] = { 1283 { rv_op_fneg_s, rvcc_fneg_s }, 1284 { rv_op_illegal, NULL } 1285 }; 1286 1287 static const rv_comp_data rvcp_fsgnjx_s[] = { 1288 { rv_op_fabs_s, rvcc_fabs_s }, 1289 { rv_op_illegal, NULL } 1290 }; 1291 1292 static const rv_comp_data rvcp_fsgnj_d[] = { 1293 { rv_op_fmv_d, rvcc_fmv_d }, 1294 { rv_op_illegal, NULL } 1295 }; 1296 1297 static const rv_comp_data rvcp_fsgnjn_d[] = { 1298 { rv_op_fneg_d, rvcc_fneg_d }, 1299 { rv_op_illegal, NULL } 1300 }; 1301 1302 static const rv_comp_data rvcp_fsgnjx_d[] = { 1303 { rv_op_fabs_d, rvcc_fabs_d }, 1304 { rv_op_illegal, NULL } 1305 }; 1306 1307 static const rv_comp_data rvcp_fsgnj_q[] = { 1308 { rv_op_fmv_q, rvcc_fmv_q }, 1309 { rv_op_illegal, NULL } 1310 }; 1311 1312 static const rv_comp_data rvcp_fsgnjn_q[] = { 1313 { rv_op_fneg_q, rvcc_fneg_q }, 1314 { rv_op_illegal, NULL } 1315 }; 1316 1317 static const rv_comp_data rvcp_fsgnjx_q[] = { 1318 { rv_op_fabs_q, rvcc_fabs_q }, 1319 { rv_op_illegal, NULL } 1320 }; 1321 1322 /* instruction metadata */ 1323 1324 const rv_opcode_data opcode_data[] = { 1325 { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, 1326 { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 }, 1327 { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 }, 1328 { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 }, 1329 { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 }, 1330 { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 }, 1331 { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 }, 1332 { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 }, 1333 { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 }, 1334 { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 }, 1335 { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 }, 1336 { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1337 { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1338 { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1339 { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1340 { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1341 { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1342 { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1343 { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1344 { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 }, 1345 { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1346 { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 }, 1347 { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 }, 1348 { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1349 { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1350 { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1351 { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1352 { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1353 { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1354 { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 }, 1355 { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1356 { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 }, 1357 { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 }, 1358 { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1359 { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1360 { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1361 { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1362 { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1363 { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 }, 1364 { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1365 { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1366 { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1367 { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1368 { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 }, 1369 { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1370 { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1371 { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1372 { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1373 { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 }, 1374 { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1375 { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1376 { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1377 { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1378 { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1379 { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1380 { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1381 { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1382 { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1383 { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1384 { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1385 { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1386 { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1387 { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1388 { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1389 { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1390 { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1391 { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1392 { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1393 { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1394 { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1395 { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1396 { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1397 { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1398 { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1399 { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1400 { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1401 { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1402 { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1403 { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1404 { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1405 { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1406 { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1407 { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1408 { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1409 { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1410 { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1411 { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1412 { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1413 { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1414 { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1415 { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1416 { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1417 { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1418 { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1419 { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1420 { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1421 { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1422 { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1423 { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1424 { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1425 { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1426 { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1427 { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1428 { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1429 { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1430 { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1431 { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1432 { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1433 { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1434 { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1435 { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1436 { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1437 { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1438 { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1439 { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1440 { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1441 { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1442 { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1443 { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1444 { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1445 { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1446 { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1447 { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, 1448 { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 }, 1449 { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1450 { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 }, 1451 { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 }, 1452 { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 }, 1453 { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 }, 1454 { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1455 { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1456 { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1457 { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1458 { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1459 { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1460 { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1461 { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1462 { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1463 { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1464 { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1465 { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1466 { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 }, 1467 { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 }, 1468 { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 }, 1469 { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1470 { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1471 { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1472 { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1473 { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1474 { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1475 { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1476 { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1477 { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1478 { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1479 { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1480 { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1481 { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1482 { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1483 { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1484 { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1485 { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1486 { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1487 { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1488 { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1489 { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1490 { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1491 { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1492 { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1493 { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1494 { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1495 { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1496 { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 }, 1497 { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 }, 1498 { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 }, 1499 { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1500 { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1501 { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1502 { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1503 { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1504 { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1505 { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1506 { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1507 { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1508 { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1509 { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1510 { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1511 { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1512 { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1513 { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1514 { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1515 { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1516 { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1517 { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1518 { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1519 { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1520 { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1521 { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1522 { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1523 { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1524 { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1525 { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1526 { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1527 { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1528 { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 }, 1529 { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 }, 1530 { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 }, 1531 { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1532 { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1533 { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1534 { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1535 { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1536 { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1537 { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1538 { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1539 { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1540 { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1541 { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1542 { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1543 { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1544 { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1545 { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1546 { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1547 { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1548 { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1549 { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1550 { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1551 { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1552 { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1553 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1554 { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 }, 1555 { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw }, 1556 { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, 1557 { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 }, 1558 { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw }, 1559 { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, 1560 { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, 1561 { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1562 rv_op_addi, rvcd_imm_nz }, 1563 { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 }, 1564 { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, 1565 { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1566 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1567 { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, 1568 rv_op_lui, rvcd_imm_nz }, 1569 { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, 1570 rv_op_srli, rv_op_srli, rvcd_imm_nz }, 1571 { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, 1572 rv_op_srai, rv_op_srai, rvcd_imm_nz }, 1573 { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, 1574 rv_op_andi, rv_op_andi }, 1575 { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub }, 1576 { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor }, 1577 { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or }, 1578 { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and }, 1579 { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw }, 1580 { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw }, 1581 { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal }, 1582 { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq }, 1583 { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne }, 1584 { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, 1585 rv_op_slli, rv_op_slli, rvcd_imm_nz }, 1586 { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld }, 1587 { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw }, 1588 { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, 1589 { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr }, 1590 { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, 1591 { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak }, 1592 { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr }, 1593 { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add }, 1594 { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd }, 1595 { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw }, 1596 { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, 1597 { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld }, 1598 { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd }, 1599 { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw }, 1600 { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld }, 1601 { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd }, 1602 { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1603 { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, 1604 { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1605 { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, 1606 { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1607 { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1608 { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1609 { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1610 { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1611 { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1612 { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1613 { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1614 { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1615 { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1616 { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1617 { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1618 { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1619 { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1620 { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1621 { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1622 { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1623 { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1624 { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1625 { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1626 { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1627 { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1628 { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1629 { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1630 { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1631 { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1632 { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1633 { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1634 { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1635 { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 }, 1636 { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1637 { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 }, 1638 { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1639 { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1640 { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1641 { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1642 { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1643 { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1644 { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1645 { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1646 { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1647 { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1648 { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1649 { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1650 { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1651 { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1652 { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1653 { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1654 { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1655 { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1656 { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1657 { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1658 { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1659 { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1660 { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1661 { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1662 { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1663 { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1664 { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1665 { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1666 { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1667 { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1668 { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1669 { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1670 { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1671 { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1672 { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1673 { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1674 { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1675 { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1676 { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1677 { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1678 { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1679 { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1680 { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1681 { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1682 { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1683 { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1684 { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1685 { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1686 { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1687 { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1688 { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1689 { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1690 { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1691 { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1692 { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1693 { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1694 { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1695 { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1696 { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1697 { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1698 { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1699 { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 }, 1700 { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1701 { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1702 { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1703 { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1704 { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1705 { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1706 { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1707 { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1708 { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1709 { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1710 { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1711 { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1712 { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1713 { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1714 { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1715 { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1716 { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1717 { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1718 { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1719 { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1720 { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1721 { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1722 { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1723 { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1724 { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1725 { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1726 { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1727 { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1728 { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1729 { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1730 { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1731 { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1732 { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8_v, rv_op_vle8_v, 0 }, 1733 { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16_v, rv_op_vle16_v, 0 }, 1734 { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32_v, rv_op_vle32_v, 0 }, 1735 { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64_v, rv_op_vle64_v, 0 }, 1736 { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse8_v, rv_op_vse8_v, 0 }, 1737 { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse16_v, rv_op_vse16_v, 0 }, 1738 { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse32_v, rv_op_vse32_v, 0 }, 1739 { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse64_v, rv_op_vse64_v, 0 }, 1740 { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vlm_v, rv_op_vlm_v, 0 }, 1741 { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vsm_v, rv_op_vsm_v, 0 }, 1742 { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse8_v, rv_op_vlse8_v, 0 }, 1743 { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse16_v, rv_op_vlse16_v, 0 }, 1744 { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse32_v, rv_op_vlse32_v, 0 }, 1745 { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse64_v, rv_op_vlse64_v, 0 }, 1746 { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse8_v, rv_op_vsse8_v, 0 }, 1747 { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse16_v, rv_op_vsse16_v, 0 }, 1748 { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse32_v, rv_op_vsse32_v, 0 }, 1749 { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse64_v, rv_op_vsse64_v, 0 }, 1750 { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei8_v, rv_op_vluxei8_v, 0 }, 1751 { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei16_v, rv_op_vluxei16_v, 0 }, 1752 { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei32_v, rv_op_vluxei32_v, 0 }, 1753 { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei64_v, rv_op_vluxei64_v, 0 }, 1754 { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei8_v, rv_op_vloxei8_v, 0 }, 1755 { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei16_v, rv_op_vloxei16_v, 0 }, 1756 { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei32_v, rv_op_vloxei32_v, 0 }, 1757 { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei64_v, rv_op_vloxei64_v, 0 }, 1758 { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei8_v, rv_op_vsuxei8_v, 0 }, 1759 { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei16_v, rv_op_vsuxei16_v, 0 }, 1760 { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei32_v, rv_op_vsuxei32_v, 0 }, 1761 { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei64_v, rv_op_vsuxei64_v, 0 }, 1762 { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei8_v, rv_op_vsoxei8_v, 0 }, 1763 { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei16_v, rv_op_vsoxei16_v, 0 }, 1764 { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei32_v, rv_op_vsoxei32_v, 0 }, 1765 { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei64_v, rv_op_vsoxei64_v, 0 }, 1766 { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8ff_v, rv_op_vle8ff_v, 0 }, 1767 { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16ff_v, rv_op_vle16ff_v, 0 }, 1768 { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32ff_v, rv_op_vle32ff_v, 0 }, 1769 { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64ff_v, rv_op_vle64ff_v, 0 }, 1770 { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re8_v, rv_op_vl1re8_v, 0 }, 1771 { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re16_v, rv_op_vl1re16_v, 0 }, 1772 { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re32_v, rv_op_vl1re32_v, 0 }, 1773 { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re64_v, rv_op_vl1re64_v, 0 }, 1774 { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re8_v, rv_op_vl2re8_v, 0 }, 1775 { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re16_v, rv_op_vl2re16_v, 0 }, 1776 { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re32_v, rv_op_vl2re32_v, 0 }, 1777 { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re64_v, rv_op_vl2re64_v, 0 }, 1778 { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re8_v, rv_op_vl4re8_v, 0 }, 1779 { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re16_v, rv_op_vl4re16_v, 0 }, 1780 { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re32_v, rv_op_vl4re32_v, 0 }, 1781 { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re64_v, rv_op_vl4re64_v, 0 }, 1782 { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re8_v, rv_op_vl8re8_v, 0 }, 1783 { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re16_v, rv_op_vl8re16_v, 0 }, 1784 { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re32_v, rv_op_vl8re32_v, 0 }, 1785 { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re64_v, rv_op_vl8re64_v, 0 }, 1786 { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs1r_v, rv_op_vs1r_v, 0 }, 1787 { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs2r_v, rv_op_vs2r_v, 0 }, 1788 { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs4r_v, rv_op_vs4r_v, 0 }, 1789 { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs8r_v, rv_op_vs8r_v, 0 }, 1790 { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vadd_vv, rv_op_vadd_vv, 0 }, 1791 { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vadd_vx, rv_op_vadd_vx, 0 }, 1792 { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vadd_vi, rv_op_vadd_vi, 0 }, 1793 { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsub_vv, rv_op_vsub_vv, 0 }, 1794 { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsub_vx, rv_op_vsub_vx, 0 }, 1795 { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrsub_vx, rv_op_vrsub_vx, 0 }, 1796 { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vrsub_vi, rv_op_vrsub_vi, 0 }, 1797 { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_vv, rv_op_vwaddu_vv, 0 }, 1798 { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_vx, rv_op_vwaddu_vx, 0 }, 1799 { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_vv, rv_op_vwadd_vv, 0 }, 1800 { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_vx, rv_op_vwadd_vx, 0 }, 1801 { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_vv, rv_op_vwsubu_vv, 0 }, 1802 { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_vx, rv_op_vwsubu_vx, 0 }, 1803 { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_vv, rv_op_vwsub_vv, 0 }, 1804 { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_vx, rv_op_vwsub_vx, 0 }, 1805 { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_wv, rv_op_vwaddu_wv, 0 }, 1806 { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_wx, rv_op_vwaddu_wx, 0 }, 1807 { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_wv, rv_op_vwadd_wv, 0 }, 1808 { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_wx, rv_op_vwadd_wx, 0 }, 1809 { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_wv, rv_op_vwsubu_wv, 0 }, 1810 { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_wx, rv_op_vwsubu_wx, 0 }, 1811 { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_wv, rv_op_vwsub_wv, 0 }, 1812 { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_wx, rv_op_vwsub_wx, 0 }, 1813 { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vadc_vvm, rv_op_vadc_vvm, 0 }, 1814 { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vadc_vxm, rv_op_vadc_vxm, 0 }, 1815 { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vadc_vim, rv_op_vadc_vim, 0 }, 1816 { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmadc_vvm, rv_op_vmadc_vvm, 0 }, 1817 { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmadc_vxm, rv_op_vmadc_vxm, 0 }, 1818 { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmadc_vim, rv_op_vmadc_vim, 0 }, 1819 { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vsbc_vvm, rv_op_vsbc_vvm, 0 }, 1820 { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vsbc_vxm, rv_op_vsbc_vxm, 0 }, 1821 { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmsbc_vvm, rv_op_vmsbc_vvm, 0 }, 1822 { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmsbc_vxm, rv_op_vmsbc_vxm, 0 }, 1823 { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vand_vv, rv_op_vand_vv, 0 }, 1824 { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vand_vx, rv_op_vand_vx, 0 }, 1825 { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vand_vi, rv_op_vand_vi, 0 }, 1826 { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vor_vv, rv_op_vor_vv, 0 }, 1827 { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vor_vx, rv_op_vor_vx, 0 }, 1828 { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vor_vi, rv_op_vor_vi, 0 }, 1829 { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vxor_vv, rv_op_vxor_vv, 0 }, 1830 { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vxor_vx, rv_op_vxor_vx, 0 }, 1831 { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vxor_vi, rv_op_vxor_vi, 0 }, 1832 { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsll_vv, rv_op_vsll_vv, 0 }, 1833 { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsll_vx, rv_op_vsll_vx, 0 }, 1834 { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsll_vi, rv_op_vsll_vi, 0 }, 1835 { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsrl_vv, rv_op_vsrl_vv, 0 }, 1836 { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsrl_vx, rv_op_vsrl_vx, 0 }, 1837 { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsrl_vi, rv_op_vsrl_vi, 0 }, 1838 { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsra_vv, rv_op_vsra_vv, 0 }, 1839 { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsra_vx, rv_op_vsra_vx, 0 }, 1840 { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsra_vi, rv_op_vsra_vi, 0 }, 1841 { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsrl_wv, rv_op_vnsrl_wv, 0 }, 1842 { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsrl_wx, rv_op_vnsrl_wx, 0 }, 1843 { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsrl_wi, rv_op_vnsrl_wi, 0 }, 1844 { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsra_wv, rv_op_vnsra_wv, 0 }, 1845 { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsra_wx, rv_op_vnsra_wx, 0 }, 1846 { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsra_wi, rv_op_vnsra_wi, 0 }, 1847 { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmseq_vv, rv_op_vmseq_vv, 0 }, 1848 { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmseq_vx, rv_op_vmseq_vx, 0 }, 1849 { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmseq_vi, rv_op_vmseq_vi, 0 }, 1850 { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsne_vv, rv_op_vmsne_vv, 0 }, 1851 { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsne_vx, rv_op_vmsne_vx, 0 }, 1852 { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsne_vi, rv_op_vmsne_vi, 0 }, 1853 { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsltu_vv, rv_op_vmsltu_vv, 0 }, 1854 { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsltu_vx, rv_op_vmsltu_vx, 0 }, 1855 { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmslt_vv, rv_op_vmslt_vv, 0 }, 1856 { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmslt_vx, rv_op_vmslt_vx, 0 }, 1857 { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsleu_vv, rv_op_vmsleu_vv, 0 }, 1858 { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsleu_vx, rv_op_vmsleu_vx, 0 }, 1859 { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsleu_vi, rv_op_vmsleu_vi, 0 }, 1860 { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsle_vv, rv_op_vmsle_vv, 0 }, 1861 { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsle_vx, rv_op_vmsle_vx, 0 }, 1862 { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsle_vi, rv_op_vmsle_vi, 0 }, 1863 { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgtu_vx, rv_op_vmsgtu_vx, 0 }, 1864 { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgtu_vi, rv_op_vmsgtu_vi, 0 }, 1865 { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgt_vx, rv_op_vmsgt_vx, 0 }, 1866 { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgt_vi, rv_op_vmsgt_vi, 0 }, 1867 { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vminu_vv, rv_op_vminu_vv, 0 }, 1868 { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vminu_vx, rv_op_vminu_vx, 0 }, 1869 { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmin_vv, rv_op_vmin_vv, 0 }, 1870 { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmin_vx, rv_op_vmin_vx, 0 }, 1871 { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmaxu_vv, rv_op_vmaxu_vv, 0 }, 1872 { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmaxu_vx, rv_op_vmaxu_vx, 0 }, 1873 { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmax_vv, rv_op_vmax_vv, 0 }, 1874 { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmax_vx, rv_op_vmax_vx, 0 }, 1875 { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmul_vv, rv_op_vmul_vv, 0 }, 1876 { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmul_vx, rv_op_vmul_vx, 0 }, 1877 { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulh_vv, rv_op_vmulh_vv, 0 }, 1878 { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulh_vx, rv_op_vmulh_vx, 0 }, 1879 { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhu_vv, rv_op_vmulhu_vv, 0 }, 1880 { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhu_vx, rv_op_vmulhu_vx, 0 }, 1881 { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhsu_vv, rv_op_vmulhsu_vv, 0 }, 1882 { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhsu_vx, rv_op_vmulhsu_vx, 0 }, 1883 { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdivu_vv, rv_op_vdivu_vv, 0 }, 1884 { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdivu_vx, rv_op_vdivu_vx, 0 }, 1885 { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdiv_vv, rv_op_vdiv_vv, 0 }, 1886 { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdiv_vx, rv_op_vdiv_vx, 0 }, 1887 { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vremu_vv, rv_op_vremu_vv, 0 }, 1888 { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vremu_vx, rv_op_vremu_vx, 0 }, 1889 { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrem_vv, rv_op_vrem_vv, 0 }, 1890 { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrem_vx, rv_op_vrem_vx, 0 }, 1891 { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulu_vv, rv_op_vwmulu_vv, 0 }, 1892 { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulu_vx, rv_op_vwmulu_vx, 0 }, 1893 { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulsu_vv, rv_op_vwmulsu_vv, 0 }, 1894 { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulsu_vx, rv_op_vwmulsu_vx, 0 }, 1895 { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmul_vv, rv_op_vwmul_vv, 0 }, 1896 { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmul_vx, rv_op_vwmul_vx, 0 }, 1897 { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmacc_vv, rv_op_vmacc_vv, 0 }, 1898 { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmacc_vx, rv_op_vmacc_vx, 0 }, 1899 { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsac_vv, rv_op_vnmsac_vv, 0 }, 1900 { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsac_vx, rv_op_vnmsac_vx, 0 }, 1901 { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmadd_vv, rv_op_vmadd_vv, 0 }, 1902 { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmadd_vx, rv_op_vmadd_vx, 0 }, 1903 { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsub_vv, rv_op_vnmsub_vv, 0 }, 1904 { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsub_vx, rv_op_vnmsub_vx, 0 }, 1905 { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccu_vv, rv_op_vwmaccu_vv, 0 }, 1906 { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccu_vx, rv_op_vwmaccu_vx, 0 }, 1907 { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmacc_vv, rv_op_vwmacc_vv, 0 }, 1908 { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmacc_vx, rv_op_vwmacc_vx, 0 }, 1909 { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccsu_vv, rv_op_vwmaccsu_vv, 0 }, 1910 { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccsu_vx, rv_op_vwmaccsu_vx, 0 }, 1911 { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccus_vx, rv_op_vwmaccus_vx, 0 }, 1912 { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, rv_op_vmv_v_v, rv_op_vmv_v_v, 0 }, 1913 { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_v_x, rv_op_vmv_v_x, 0 }, 1914 { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, rv_op_vmv_v_i, rv_op_vmv_v_i, 0 }, 1915 { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmerge_vvm, rv_op_vmerge_vvm, 0 }, 1916 { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmerge_vxm, rv_op_vmerge_vxm, 0 }, 1917 { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmerge_vim, rv_op_vmerge_vim, 0 }, 1918 { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsaddu_vv, rv_op_vsaddu_vv, 0 }, 1919 { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsaddu_vx, rv_op_vsaddu_vx, 0 }, 1920 { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsaddu_vi, rv_op_vsaddu_vi, 0 }, 1921 { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsadd_vv, rv_op_vsadd_vv, 0 }, 1922 { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsadd_vx, rv_op_vsadd_vx, 0 }, 1923 { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsadd_vi, rv_op_vsadd_vi, 0 }, 1924 { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssubu_vv, rv_op_vssubu_vv, 0 }, 1925 { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssubu_vx, rv_op_vssubu_vx, 0 }, 1926 { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssub_vv, rv_op_vssub_vv, 0 }, 1927 { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssub_vx, rv_op_vssub_vx, 0 }, 1928 { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaadd_vv, rv_op_vaadd_vv, 0 }, 1929 { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaadd_vx, rv_op_vaadd_vx, 0 }, 1930 { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaaddu_vv, rv_op_vaaddu_vv, 0 }, 1931 { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaaddu_vx, rv_op_vaaddu_vx, 0 }, 1932 { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasub_vv, rv_op_vasub_vv, 0 }, 1933 { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasub_vx, rv_op_vasub_vx, 0 }, 1934 { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasubu_vv, rv_op_vasubu_vv, 0 }, 1935 { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasubu_vx, rv_op_vasubu_vx, 0 }, 1936 { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsmul_vv, rv_op_vsmul_vv, 0 }, 1937 { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsmul_vx, rv_op_vsmul_vx, 0 }, 1938 { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssrl_vv, rv_op_vssrl_vv, 0 }, 1939 { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssrl_vx, rv_op_vssrl_vx, 0 }, 1940 { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssrl_vi, rv_op_vssrl_vi, 0 }, 1941 { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssra_vv, rv_op_vssra_vv, 0 }, 1942 { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssra_vx, rv_op_vssra_vx, 0 }, 1943 { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssra_vi, rv_op_vssra_vi, 0 }, 1944 { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclipu_wv, rv_op_vnclipu_wv, 0 }, 1945 { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclipu_wx, rv_op_vnclipu_wx, 0 }, 1946 { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclipu_wi, rv_op_vnclipu_wi, 0 }, 1947 { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclip_wv, rv_op_vnclip_wv, 0 }, 1948 { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclip_wx, rv_op_vnclip_wx, 0 }, 1949 { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclip_wi, rv_op_vnclip_wi, 0 }, 1950 { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfadd_vv, rv_op_vfadd_vv, 0 }, 1951 { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfadd_vf, rv_op_vfadd_vf, 0 }, 1952 { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsub_vv, rv_op_vfsub_vv, 0 }, 1953 { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsub_vf, rv_op_vfsub_vf, 0 }, 1954 { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrsub_vf, rv_op_vfrsub_vf, 0 }, 1955 { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_vv, rv_op_vfwadd_vv, 0 }, 1956 { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_vf, rv_op_vfwadd_vf, 0 }, 1957 { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_wv, rv_op_vfwadd_wv, 0 }, 1958 { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_wf, rv_op_vfwadd_wf, 0 }, 1959 { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_vv, rv_op_vfwsub_vv, 0 }, 1960 { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_vf, rv_op_vfwsub_vf, 0 }, 1961 { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_wv, rv_op_vfwsub_wv, 0 }, 1962 { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_wf, rv_op_vfwsub_wf, 0 }, 1963 { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmul_vv, rv_op_vfmul_vv, 0 }, 1964 { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmul_vf, rv_op_vfmul_vf, 0 }, 1965 { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfdiv_vv, rv_op_vfdiv_vv, 0 }, 1966 { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfdiv_vf, rv_op_vfdiv_vf, 0 }, 1967 { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrdiv_vf, rv_op_vfrdiv_vf, 0 }, 1968 { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwmul_vv, rv_op_vfwmul_vv, 0 }, 1969 { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwmul_vf, rv_op_vfwmul_vf, 0 }, 1970 { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmacc_vv, rv_op_vfmacc_vv, 0 }, 1971 { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmacc_vf, rv_op_vfmacc_vf, 0 }, 1972 { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmacc_vv, rv_op_vfnmacc_vv, 0 }, 1973 { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmacc_vf, rv_op_vfnmacc_vf, 0 }, 1974 { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsac_vv, rv_op_vfmsac_vv, 0 }, 1975 { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsac_vf, rv_op_vfmsac_vf, 0 }, 1976 { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsac_vv, rv_op_vfnmsac_vv, 0 }, 1977 { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsac_vf, rv_op_vfnmsac_vf, 0 }, 1978 { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmadd_vv, rv_op_vfmadd_vv, 0 }, 1979 { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmadd_vf, rv_op_vfmadd_vf, 0 }, 1980 { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmadd_vv, rv_op_vfnmadd_vv, 0 }, 1981 { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmadd_vf, rv_op_vfnmadd_vf, 0 }, 1982 { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsub_vv, rv_op_vfmsub_vv, 0 }, 1983 { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsub_vf, rv_op_vfmsub_vf, 0 }, 1984 { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsub_vv, rv_op_vfnmsub_vv, 0 }, 1985 { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsub_vf, rv_op_vfnmsub_vf, 0 }, 1986 { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmacc_vv, rv_op_vfwmacc_vv, 0 }, 1987 { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmacc_vf, rv_op_vfwmacc_vf, 0 }, 1988 { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmacc_vv, rv_op_vfwnmacc_vv, 0 }, 1989 { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmacc_vf, rv_op_vfwnmacc_vf, 0 }, 1990 { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmsac_vv, rv_op_vfwmsac_vv, 0 }, 1991 { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmsac_vf, rv_op_vfwmsac_vf, 0 }, 1992 { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmsac_vv, rv_op_vfwnmsac_vv, 0 }, 1993 { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmsac_vf, rv_op_vfwnmsac_vf, 0 }, 1994 { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfsqrt_v, rv_op_vfsqrt_v, 0 }, 1995 { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrsqrt7_v, rv_op_vfrsqrt7_v, 0 }, 1996 { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrec7_v, rv_op_vfrec7_v, 0 }, 1997 { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmin_vv, rv_op_vfmin_vv, 0 }, 1998 { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmin_vf, rv_op_vfmin_vf, 0 }, 1999 { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmax_vv, rv_op_vfmax_vv, 0 }, 2000 { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmax_vf, rv_op_vfmax_vf, 0 }, 2001 { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnj_vv, rv_op_vfsgnj_vv, 0 }, 2002 { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnj_vf, rv_op_vfsgnj_vf, 0 }, 2003 { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjn_vv, rv_op_vfsgnjn_vv, 0 }, 2004 { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjn_vf, rv_op_vfsgnjn_vf, 0 }, 2005 { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjx_vv, rv_op_vfsgnjx_vv, 0 }, 2006 { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjx_vf, rv_op_vfsgnjx_vf, 0 }, 2007 { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1up_vf, rv_op_vfslide1up_vf, 0 }, 2008 { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1down_vf, rv_op_vfslide1down_vf, 0 }, 2009 { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfeq_vv, rv_op_vmfeq_vv, 0 }, 2010 { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfeq_vf, rv_op_vmfeq_vf, 0 }, 2011 { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfne_vv, rv_op_vmfne_vv, 0 }, 2012 { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfne_vf, rv_op_vmfne_vf, 0 }, 2013 { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmflt_vv, rv_op_vmflt_vv, 0 }, 2014 { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmflt_vf, rv_op_vmflt_vf, 0 }, 2015 { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfle_vv, rv_op_vmfle_vv, 0 }, 2016 { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfle_vf, rv_op_vmfle_vf, 0 }, 2017 { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfgt_vf, rv_op_vmfgt_vf, 0 }, 2018 { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfge_vf, rv_op_vmfge_vf, 0 }, 2019 { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfclass_v, rv_op_vfclass_v, 0 }, 2020 { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, rv_op_vfmerge_vfm, rv_op_vfmerge_vfm, 0 }, 2021 { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_v_f, rv_op_vfmv_v_f, 0 }, 2022 { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_xu_f_v, rv_op_vfcvt_xu_f_v, 0 }, 2023 { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_x_f_v, rv_op_vfcvt_x_f_v, 0 }, 2024 { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_xu_v, rv_op_vfcvt_f_xu_v, 0 }, 2025 { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_x_v, rv_op_vfcvt_f_x_v, 0 }, 2026 { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_xu_f_v, rv_op_vfcvt_rtz_xu_f_v, 0 }, 2027 { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_x_f_v, rv_op_vfcvt_rtz_x_f_v, 0 }, 2028 { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_xu_f_v, rv_op_vfwcvt_xu_f_v, 0 }, 2029 { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_x_f_v, rv_op_vfwcvt_x_f_v, 0 }, 2030 { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_xu_v, rv_op_vfwcvt_f_xu_v, 0 }, 2031 { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_x_v, rv_op_vfwcvt_f_x_v, 0 }, 2032 { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_f_v, rv_op_vfwcvt_f_f_v, 0 }, 2033 { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_xu_f_v, rv_op_vfwcvt_rtz_xu_f_v, 0 }, 2034 { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_x_f_v, rv_op_vfwcvt_rtz_x_f_v, 0 }, 2035 { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_xu_f_w, rv_op_vfncvt_xu_f_w, 0 }, 2036 { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_x_f_w, rv_op_vfncvt_x_f_w, 0 }, 2037 { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_xu_w, rv_op_vfncvt_f_xu_w, 0 }, 2038 { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_x_w, rv_op_vfncvt_f_x_w, 0 }, 2039 { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_f_w, rv_op_vfncvt_f_f_w, 0 }, 2040 { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rod_f_f_w, rv_op_vfncvt_rod_f_f_w, 0 }, 2041 { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_xu_f_w, rv_op_vfncvt_rtz_xu_f_w, 0 }, 2042 { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_x_f_w, rv_op_vfncvt_rtz_x_f_w, 0 }, 2043 { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredsum_vs, rv_op_vredsum_vs, 0 }, 2044 { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredand_vs, rv_op_vredand_vs, 0 }, 2045 { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredor_vs, rv_op_vredor_vs, 0 }, 2046 { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredxor_vs, rv_op_vredxor_vs, 0 }, 2047 { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredminu_vs, rv_op_vredminu_vs, 0 }, 2048 { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmin_vs, rv_op_vredmin_vs, 0 }, 2049 { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmaxu_vs, rv_op_vredmaxu_vs, 0 }, 2050 { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmax_vs, rv_op_vredmax_vs, 0 }, 2051 { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsumu_vs, rv_op_vwredsumu_vs, 0 }, 2052 { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsum_vs, rv_op_vwredsum_vs, 0 }, 2053 { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredusum_vs, rv_op_vfredusum_vs, 0 }, 2054 { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredosum_vs, rv_op_vfredosum_vs, 0 }, 2055 { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmin_vs, rv_op_vfredmin_vs, 0 }, 2056 { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmax_vs, rv_op_vfredmax_vs, 0 }, 2057 { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredusum_vs, rv_op_vfwredusum_vs, 0 }, 2058 { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredosum_vs, rv_op_vfwredosum_vs, 0 }, 2059 { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmand_mm, rv_op_vmand_mm, 0 }, 2060 { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnand_mm, rv_op_vmnand_mm, 0 }, 2061 { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmandn_mm, rv_op_vmandn_mm, 0 }, 2062 { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxor_mm, rv_op_vmxor_mm, 0 }, 2063 { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmor_mm, rv_op_vmor_mm, 0 }, 2064 { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnor_mm, rv_op_vmnor_mm, 0 }, 2065 { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmorn_mm, rv_op_vmorn_mm, 0 }, 2066 { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxnor_mm, rv_op_vmxnor_mm, 0 }, 2067 { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vcpop_m, rv_op_vcpop_m, 0 }, 2068 { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vfirst_m, rv_op_vfirst_m, 0 }, 2069 { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsbf_m, rv_op_vmsbf_m, 0 }, 2070 { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsif_m, rv_op_vmsif_m, 0 }, 2071 { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsof_m, rv_op_vmsof_m, 0 }, 2072 { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_viota_m, rv_op_viota_m, 0 }, 2073 { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, rv_op_vid_v, rv_op_vid_v, 0 }, 2074 { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, rv_op_vmv_x_s, rv_op_vmv_x_s, 0 }, 2075 { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_s_x, rv_op_vmv_s_x, 0 }, 2076 { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, rv_op_vfmv_f_s, rv_op_vfmv_f_s, 0 }, 2077 { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_s_f, rv_op_vfmv_s_f, 0 }, 2078 { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslideup_vx, rv_op_vslideup_vx, 0 }, 2079 { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslideup_vi, rv_op_vslideup_vi, 0 }, 2080 { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1up_vx, rv_op_vslide1up_vx, 0 }, 2081 { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslidedown_vx, rv_op_vslidedown_vx, 0 }, 2082 { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslidedown_vi, rv_op_vslidedown_vi, 0 }, 2083 { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1down_vx, rv_op_vslide1down_vx, 0 }, 2084 { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgather_vv, rv_op_vrgather_vv, 0 }, 2085 { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgatherei16_vv, rv_op_vrgatherei16_vv, 0 }, 2086 { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrgather_vx, rv_op_vrgather_vx, 0 }, 2087 { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vrgather_vi, rv_op_vrgather_vi, 0 }, 2088 { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, rv_op_vcompress_vm, rv_op_vcompress_vm, 0 }, 2089 { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv1r_v, rv_op_vmv1r_v, 0 }, 2090 { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv2r_v, rv_op_vmv2r_v, 0 }, 2091 { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv4r_v, rv_op_vmv4r_v, 0 }, 2092 { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv8r_v, rv_op_vmv8r_v, 0 }, 2093 { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf2, rv_op_vzext_vf2, 0 }, 2094 { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf4, rv_op_vzext_vf4, 0 }, 2095 { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf8, rv_op_vzext_vf8, 0 }, 2096 { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf2, rv_op_vsext_vf2, 0 }, 2097 { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf4, rv_op_vsext_vf4, 0 }, 2098 { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 }, 2099 { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 }, 2100 { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 }, 2101 { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }, 2102 { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2103 { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2104 { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2105 { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2106 { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2107 { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2108 { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 }, 2109 { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2110 { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2111 { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2112 { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2113 { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2114 { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 }, 2115 { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2116 { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 }, 2117 { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2118 { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2119 { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2120 { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2121 { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2122 }; 2123 2124 /* CSR names */ 2125 2126 static const char *csr_name(int csrno) 2127 { 2128 switch (csrno) { 2129 case 0x0000: return "ustatus"; 2130 case 0x0001: return "fflags"; 2131 case 0x0002: return "frm"; 2132 case 0x0003: return "fcsr"; 2133 case 0x0004: return "uie"; 2134 case 0x0005: return "utvec"; 2135 case 0x0008: return "vstart"; 2136 case 0x0009: return "vxsat"; 2137 case 0x000a: return "vxrm"; 2138 case 0x000f: return "vcsr"; 2139 case 0x0015: return "seed"; 2140 case 0x0017: return "jvt"; 2141 case 0x0040: return "uscratch"; 2142 case 0x0041: return "uepc"; 2143 case 0x0042: return "ucause"; 2144 case 0x0043: return "utval"; 2145 case 0x0044: return "uip"; 2146 case 0x0100: return "sstatus"; 2147 case 0x0104: return "sie"; 2148 case 0x0105: return "stvec"; 2149 case 0x0106: return "scounteren"; 2150 case 0x0140: return "sscratch"; 2151 case 0x0141: return "sepc"; 2152 case 0x0142: return "scause"; 2153 case 0x0143: return "stval"; 2154 case 0x0144: return "sip"; 2155 case 0x0180: return "satp"; 2156 case 0x0200: return "hstatus"; 2157 case 0x0202: return "hedeleg"; 2158 case 0x0203: return "hideleg"; 2159 case 0x0204: return "hie"; 2160 case 0x0205: return "htvec"; 2161 case 0x0240: return "hscratch"; 2162 case 0x0241: return "hepc"; 2163 case 0x0242: return "hcause"; 2164 case 0x0243: return "hbadaddr"; 2165 case 0x0244: return "hip"; 2166 case 0x0300: return "mstatus"; 2167 case 0x0301: return "misa"; 2168 case 0x0302: return "medeleg"; 2169 case 0x0303: return "mideleg"; 2170 case 0x0304: return "mie"; 2171 case 0x0305: return "mtvec"; 2172 case 0x0306: return "mcounteren"; 2173 case 0x0320: return "mucounteren"; 2174 case 0x0321: return "mscounteren"; 2175 case 0x0322: return "mhcounteren"; 2176 case 0x0323: return "mhpmevent3"; 2177 case 0x0324: return "mhpmevent4"; 2178 case 0x0325: return "mhpmevent5"; 2179 case 0x0326: return "mhpmevent6"; 2180 case 0x0327: return "mhpmevent7"; 2181 case 0x0328: return "mhpmevent8"; 2182 case 0x0329: return "mhpmevent9"; 2183 case 0x032a: return "mhpmevent10"; 2184 case 0x032b: return "mhpmevent11"; 2185 case 0x032c: return "mhpmevent12"; 2186 case 0x032d: return "mhpmevent13"; 2187 case 0x032e: return "mhpmevent14"; 2188 case 0x032f: return "mhpmevent15"; 2189 case 0x0330: return "mhpmevent16"; 2190 case 0x0331: return "mhpmevent17"; 2191 case 0x0332: return "mhpmevent18"; 2192 case 0x0333: return "mhpmevent19"; 2193 case 0x0334: return "mhpmevent20"; 2194 case 0x0335: return "mhpmevent21"; 2195 case 0x0336: return "mhpmevent22"; 2196 case 0x0337: return "mhpmevent23"; 2197 case 0x0338: return "mhpmevent24"; 2198 case 0x0339: return "mhpmevent25"; 2199 case 0x033a: return "mhpmevent26"; 2200 case 0x033b: return "mhpmevent27"; 2201 case 0x033c: return "mhpmevent28"; 2202 case 0x033d: return "mhpmevent29"; 2203 case 0x033e: return "mhpmevent30"; 2204 case 0x033f: return "mhpmevent31"; 2205 case 0x0340: return "mscratch"; 2206 case 0x0341: return "mepc"; 2207 case 0x0342: return "mcause"; 2208 case 0x0343: return "mtval"; 2209 case 0x0344: return "mip"; 2210 case 0x0380: return "mbase"; 2211 case 0x0381: return "mbound"; 2212 case 0x0382: return "mibase"; 2213 case 0x0383: return "mibound"; 2214 case 0x0384: return "mdbase"; 2215 case 0x0385: return "mdbound"; 2216 case 0x03a0: return "pmpcfg3"; 2217 case 0x03b0: return "pmpaddr0"; 2218 case 0x03b1: return "pmpaddr1"; 2219 case 0x03b2: return "pmpaddr2"; 2220 case 0x03b3: return "pmpaddr3"; 2221 case 0x03b4: return "pmpaddr4"; 2222 case 0x03b5: return "pmpaddr5"; 2223 case 0x03b6: return "pmpaddr6"; 2224 case 0x03b7: return "pmpaddr7"; 2225 case 0x03b8: return "pmpaddr8"; 2226 case 0x03b9: return "pmpaddr9"; 2227 case 0x03ba: return "pmpaddr10"; 2228 case 0x03bb: return "pmpaddr11"; 2229 case 0x03bc: return "pmpaddr12"; 2230 case 0x03bd: return "pmpaddr14"; 2231 case 0x03be: return "pmpaddr13"; 2232 case 0x03bf: return "pmpaddr15"; 2233 case 0x0780: return "mtohost"; 2234 case 0x0781: return "mfromhost"; 2235 case 0x0782: return "mreset"; 2236 case 0x0783: return "mipi"; 2237 case 0x0784: return "miobase"; 2238 case 0x07a0: return "tselect"; 2239 case 0x07a1: return "tdata1"; 2240 case 0x07a2: return "tdata2"; 2241 case 0x07a3: return "tdata3"; 2242 case 0x07b0: return "dcsr"; 2243 case 0x07b1: return "dpc"; 2244 case 0x07b2: return "dscratch"; 2245 case 0x0b00: return "mcycle"; 2246 case 0x0b01: return "mtime"; 2247 case 0x0b02: return "minstret"; 2248 case 0x0b03: return "mhpmcounter3"; 2249 case 0x0b04: return "mhpmcounter4"; 2250 case 0x0b05: return "mhpmcounter5"; 2251 case 0x0b06: return "mhpmcounter6"; 2252 case 0x0b07: return "mhpmcounter7"; 2253 case 0x0b08: return "mhpmcounter8"; 2254 case 0x0b09: return "mhpmcounter9"; 2255 case 0x0b0a: return "mhpmcounter10"; 2256 case 0x0b0b: return "mhpmcounter11"; 2257 case 0x0b0c: return "mhpmcounter12"; 2258 case 0x0b0d: return "mhpmcounter13"; 2259 case 0x0b0e: return "mhpmcounter14"; 2260 case 0x0b0f: return "mhpmcounter15"; 2261 case 0x0b10: return "mhpmcounter16"; 2262 case 0x0b11: return "mhpmcounter17"; 2263 case 0x0b12: return "mhpmcounter18"; 2264 case 0x0b13: return "mhpmcounter19"; 2265 case 0x0b14: return "mhpmcounter20"; 2266 case 0x0b15: return "mhpmcounter21"; 2267 case 0x0b16: return "mhpmcounter22"; 2268 case 0x0b17: return "mhpmcounter23"; 2269 case 0x0b18: return "mhpmcounter24"; 2270 case 0x0b19: return "mhpmcounter25"; 2271 case 0x0b1a: return "mhpmcounter26"; 2272 case 0x0b1b: return "mhpmcounter27"; 2273 case 0x0b1c: return "mhpmcounter28"; 2274 case 0x0b1d: return "mhpmcounter29"; 2275 case 0x0b1e: return "mhpmcounter30"; 2276 case 0x0b1f: return "mhpmcounter31"; 2277 case 0x0b80: return "mcycleh"; 2278 case 0x0b81: return "mtimeh"; 2279 case 0x0b82: return "minstreth"; 2280 case 0x0b83: return "mhpmcounter3h"; 2281 case 0x0b84: return "mhpmcounter4h"; 2282 case 0x0b85: return "mhpmcounter5h"; 2283 case 0x0b86: return "mhpmcounter6h"; 2284 case 0x0b87: return "mhpmcounter7h"; 2285 case 0x0b88: return "mhpmcounter8h"; 2286 case 0x0b89: return "mhpmcounter9h"; 2287 case 0x0b8a: return "mhpmcounter10h"; 2288 case 0x0b8b: return "mhpmcounter11h"; 2289 case 0x0b8c: return "mhpmcounter12h"; 2290 case 0x0b8d: return "mhpmcounter13h"; 2291 case 0x0b8e: return "mhpmcounter14h"; 2292 case 0x0b8f: return "mhpmcounter15h"; 2293 case 0x0b90: return "mhpmcounter16h"; 2294 case 0x0b91: return "mhpmcounter17h"; 2295 case 0x0b92: return "mhpmcounter18h"; 2296 case 0x0b93: return "mhpmcounter19h"; 2297 case 0x0b94: return "mhpmcounter20h"; 2298 case 0x0b95: return "mhpmcounter21h"; 2299 case 0x0b96: return "mhpmcounter22h"; 2300 case 0x0b97: return "mhpmcounter23h"; 2301 case 0x0b98: return "mhpmcounter24h"; 2302 case 0x0b99: return "mhpmcounter25h"; 2303 case 0x0b9a: return "mhpmcounter26h"; 2304 case 0x0b9b: return "mhpmcounter27h"; 2305 case 0x0b9c: return "mhpmcounter28h"; 2306 case 0x0b9d: return "mhpmcounter29h"; 2307 case 0x0b9e: return "mhpmcounter30h"; 2308 case 0x0b9f: return "mhpmcounter31h"; 2309 case 0x0c00: return "cycle"; 2310 case 0x0c01: return "time"; 2311 case 0x0c02: return "instret"; 2312 case 0x0c20: return "vl"; 2313 case 0x0c21: return "vtype"; 2314 case 0x0c22: return "vlenb"; 2315 case 0x0c80: return "cycleh"; 2316 case 0x0c81: return "timeh"; 2317 case 0x0c82: return "instreth"; 2318 case 0x0d00: return "scycle"; 2319 case 0x0d01: return "stime"; 2320 case 0x0d02: return "sinstret"; 2321 case 0x0d80: return "scycleh"; 2322 case 0x0d81: return "stimeh"; 2323 case 0x0d82: return "sinstreth"; 2324 case 0x0e00: return "hcycle"; 2325 case 0x0e01: return "htime"; 2326 case 0x0e02: return "hinstret"; 2327 case 0x0e80: return "hcycleh"; 2328 case 0x0e81: return "htimeh"; 2329 case 0x0e82: return "hinstreth"; 2330 case 0x0f11: return "mvendorid"; 2331 case 0x0f12: return "marchid"; 2332 case 0x0f13: return "mimpid"; 2333 case 0x0f14: return "mhartid"; 2334 default: return NULL; 2335 } 2336 } 2337 2338 /* decode opcode */ 2339 2340 static void decode_inst_opcode(rv_decode *dec, rv_isa isa) 2341 { 2342 rv_inst inst = dec->inst; 2343 rv_opcode op = rv_op_illegal; 2344 switch (((inst >> 0) & 0b11)) { 2345 case 0: 2346 switch (((inst >> 13) & 0b111)) { 2347 case 0: op = rv_op_c_addi4spn; break; 2348 case 1: 2349 if (isa == rv128) { 2350 op = rv_op_c_lq; 2351 } else { 2352 op = rv_op_c_fld; 2353 } 2354 break; 2355 case 2: op = rv_op_c_lw; break; 2356 case 3: 2357 if (isa == rv32) { 2358 op = rv_op_c_flw; 2359 } else { 2360 op = rv_op_c_ld; 2361 } 2362 break; 2363 case 4: 2364 switch ((inst >> 10) & 0b111) { 2365 case 0: op = rv_op_c_lbu; break; 2366 case 1: 2367 if (((inst >> 6) & 1) == 0) { 2368 op = rv_op_c_lhu; 2369 } else { 2370 op = rv_op_c_lh; 2371 } 2372 break; 2373 case 2: op = rv_op_c_sb; break; 2374 case 3: 2375 if (((inst >> 6) & 1) == 0) { 2376 op = rv_op_c_sh; 2377 } 2378 break; 2379 } 2380 break; 2381 case 5: 2382 if (isa == rv128) { 2383 op = rv_op_c_sq; 2384 } else { 2385 op = rv_op_c_fsd; 2386 } 2387 break; 2388 case 6: op = rv_op_c_sw; break; 2389 case 7: 2390 if (isa == rv32) { 2391 op = rv_op_c_fsw; 2392 } else { 2393 op = rv_op_c_sd; 2394 } 2395 break; 2396 } 2397 break; 2398 case 1: 2399 switch (((inst >> 13) & 0b111)) { 2400 case 0: 2401 switch (((inst >> 2) & 0b11111111111)) { 2402 case 0: op = rv_op_c_nop; break; 2403 default: op = rv_op_c_addi; break; 2404 } 2405 break; 2406 case 1: 2407 if (isa == rv32) { 2408 op = rv_op_c_jal; 2409 } else { 2410 op = rv_op_c_addiw; 2411 } 2412 break; 2413 case 2: op = rv_op_c_li; break; 2414 case 3: 2415 switch (((inst >> 7) & 0b11111)) { 2416 case 2: op = rv_op_c_addi16sp; break; 2417 default: op = rv_op_c_lui; break; 2418 } 2419 break; 2420 case 4: 2421 switch (((inst >> 10) & 0b11)) { 2422 case 0: 2423 op = rv_op_c_srli; 2424 break; 2425 case 1: 2426 op = rv_op_c_srai; 2427 break; 2428 case 2: op = rv_op_c_andi; break; 2429 case 3: 2430 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) { 2431 case 0: op = rv_op_c_sub; break; 2432 case 1: op = rv_op_c_xor; break; 2433 case 2: op = rv_op_c_or; break; 2434 case 3: op = rv_op_c_and; break; 2435 case 4: op = rv_op_c_subw; break; 2436 case 5: op = rv_op_c_addw; break; 2437 case 6: op = rv_op_c_mul; break; 2438 case 7: 2439 switch ((inst >> 2) & 0b111) { 2440 case 0: op = rv_op_c_zext_b; break; 2441 case 1: op = rv_op_c_sext_b; break; 2442 case 2: op = rv_op_c_zext_h; break; 2443 case 3: op = rv_op_c_sext_h; break; 2444 case 4: op = rv_op_c_zext_w; break; 2445 case 5: op = rv_op_c_not; break; 2446 } 2447 break; 2448 } 2449 break; 2450 } 2451 break; 2452 case 5: op = rv_op_c_j; break; 2453 case 6: op = rv_op_c_beqz; break; 2454 case 7: op = rv_op_c_bnez; break; 2455 } 2456 break; 2457 case 2: 2458 switch (((inst >> 13) & 0b111)) { 2459 case 0: 2460 op = rv_op_c_slli; 2461 break; 2462 case 1: 2463 if (isa == rv128) { 2464 op = rv_op_c_lqsp; 2465 } else { 2466 op = rv_op_c_fldsp; 2467 } 2468 break; 2469 case 2: op = rv_op_c_lwsp; break; 2470 case 3: 2471 if (isa == rv32) { 2472 op = rv_op_c_flwsp; 2473 } else { 2474 op = rv_op_c_ldsp; 2475 } 2476 break; 2477 case 4: 2478 switch (((inst >> 12) & 0b1)) { 2479 case 0: 2480 switch (((inst >> 2) & 0b11111)) { 2481 case 0: op = rv_op_c_jr; break; 2482 default: op = rv_op_c_mv; break; 2483 } 2484 break; 2485 case 1: 2486 switch (((inst >> 2) & 0b11111)) { 2487 case 0: 2488 switch (((inst >> 7) & 0b11111)) { 2489 case 0: op = rv_op_c_ebreak; break; 2490 default: op = rv_op_c_jalr; break; 2491 } 2492 break; 2493 default: op = rv_op_c_add; break; 2494 } 2495 break; 2496 } 2497 break; 2498 case 5: 2499 if (isa == rv128) { 2500 op = rv_op_c_sqsp; 2501 } else { 2502 op = rv_op_c_fsdsp; 2503 if (((inst >> 12) & 0b01)) { 2504 switch ((inst >> 8) & 0b01111) { 2505 case 8: 2506 if (((inst >> 4) & 0b01111) >= 4) { 2507 op = rv_op_cm_push; 2508 } 2509 break; 2510 case 10: 2511 if (((inst >> 4) & 0b01111) >= 4) { 2512 op = rv_op_cm_pop; 2513 } 2514 break; 2515 case 12: 2516 if (((inst >> 4) & 0b01111) >= 4) { 2517 op = rv_op_cm_popretz; 2518 } 2519 break; 2520 case 14: 2521 if (((inst >> 4) & 0b01111) >= 4) { 2522 op = rv_op_cm_popret; 2523 } 2524 break; 2525 } 2526 } else { 2527 switch ((inst >> 10) & 0b011) { 2528 case 0: 2529 if (((inst >> 2) & 0xFF) >= 32) { 2530 op = rv_op_cm_jalt; 2531 } else { 2532 op = rv_op_cm_jt; 2533 } 2534 break; 2535 case 3: 2536 switch ((inst >> 5) & 0b011) { 2537 case 1: op = rv_op_cm_mvsa01; break; 2538 case 3: op = rv_op_cm_mva01s; break; 2539 } 2540 break; 2541 } 2542 } 2543 } 2544 break; 2545 case 6: op = rv_op_c_swsp; break; 2546 case 7: 2547 if (isa == rv32) { 2548 op = rv_op_c_fswsp; 2549 } else { 2550 op = rv_op_c_sdsp; 2551 } 2552 break; 2553 } 2554 break; 2555 case 3: 2556 switch (((inst >> 2) & 0b11111)) { 2557 case 0: 2558 switch (((inst >> 12) & 0b111)) { 2559 case 0: op = rv_op_lb; break; 2560 case 1: op = rv_op_lh; break; 2561 case 2: op = rv_op_lw; break; 2562 case 3: op = rv_op_ld; break; 2563 case 4: op = rv_op_lbu; break; 2564 case 5: op = rv_op_lhu; break; 2565 case 6: op = rv_op_lwu; break; 2566 case 7: op = rv_op_ldu; break; 2567 } 2568 break; 2569 case 1: 2570 switch (((inst >> 12) & 0b111)) { 2571 case 0: 2572 switch (((inst >> 20) & 0b111111111111)) { 2573 case 40: op = rv_op_vl1re8_v; break; 2574 case 552: op = rv_op_vl2re8_v; break; 2575 case 1576: op = rv_op_vl4re8_v; break; 2576 case 3624: op = rv_op_vl8re8_v; break; 2577 } 2578 switch (((inst >> 26) & 0b111)) { 2579 case 0: 2580 switch (((inst >> 20) & 0b11111)) { 2581 case 0: op = rv_op_vle8_v; break; 2582 case 11: op = rv_op_vlm_v; break; 2583 case 16: op = rv_op_vle8ff_v; break; 2584 } 2585 break; 2586 case 1: op = rv_op_vluxei8_v; break; 2587 case 2: op = rv_op_vlse8_v; break; 2588 case 3: op = rv_op_vloxei8_v; break; 2589 } 2590 break; 2591 case 2: op = rv_op_flw; break; 2592 case 3: op = rv_op_fld; break; 2593 case 4: op = rv_op_flq; break; 2594 case 5: 2595 switch (((inst >> 20) & 0b111111111111)) { 2596 case 40: op = rv_op_vl1re16_v; break; 2597 case 552: op = rv_op_vl2re16_v; break; 2598 case 1576: op = rv_op_vl4re16_v; break; 2599 case 3624: op = rv_op_vl8re16_v; break; 2600 } 2601 switch (((inst >> 26) & 0b111)) { 2602 case 0: 2603 switch (((inst >> 20) & 0b11111)) { 2604 case 0: op = rv_op_vle16_v; break; 2605 case 16: op = rv_op_vle16ff_v; break; 2606 } 2607 break; 2608 case 1: op = rv_op_vluxei16_v; break; 2609 case 2: op = rv_op_vlse16_v; break; 2610 case 3: op = rv_op_vloxei16_v; break; 2611 } 2612 break; 2613 case 6: 2614 switch (((inst >> 20) & 0b111111111111)) { 2615 case 40: op = rv_op_vl1re32_v; break; 2616 case 552: op = rv_op_vl2re32_v; break; 2617 case 1576: op = rv_op_vl4re32_v; break; 2618 case 3624: op = rv_op_vl8re32_v; break; 2619 } 2620 switch (((inst >> 26) & 0b111)) { 2621 case 0: 2622 switch (((inst >> 20) & 0b11111)) { 2623 case 0: op = rv_op_vle32_v; break; 2624 case 16: op = rv_op_vle32ff_v; break; 2625 } 2626 break; 2627 case 1: op = rv_op_vluxei32_v; break; 2628 case 2: op = rv_op_vlse32_v; break; 2629 case 3: op = rv_op_vloxei32_v; break; 2630 } 2631 break; 2632 case 7: 2633 switch (((inst >> 20) & 0b111111111111)) { 2634 case 40: op = rv_op_vl1re64_v; break; 2635 case 552: op = rv_op_vl2re64_v; break; 2636 case 1576: op = rv_op_vl4re64_v; break; 2637 case 3624: op = rv_op_vl8re64_v; break; 2638 } 2639 switch (((inst >> 26) & 0b111)) { 2640 case 0: 2641 switch (((inst >> 20) & 0b11111)) { 2642 case 0: op = rv_op_vle64_v; break; 2643 case 16: op = rv_op_vle64ff_v; break; 2644 } 2645 break; 2646 case 1: op = rv_op_vluxei64_v; break; 2647 case 2: op = rv_op_vlse64_v; break; 2648 case 3: op = rv_op_vloxei64_v; break; 2649 } 2650 break; 2651 } 2652 break; 2653 case 3: 2654 switch (((inst >> 12) & 0b111)) { 2655 case 0: op = rv_op_fence; break; 2656 case 1: op = rv_op_fence_i; break; 2657 case 2: op = rv_op_lq; break; 2658 } 2659 break; 2660 case 4: 2661 switch (((inst >> 12) & 0b111)) { 2662 case 0: op = rv_op_addi; break; 2663 case 1: 2664 switch (((inst >> 27) & 0b11111)) { 2665 case 0b00000: op = rv_op_slli; break; 2666 case 0b00001: 2667 switch (((inst >> 20) & 0b1111111)) { 2668 case 0b0001111: op = rv_op_zip; break; 2669 } 2670 break; 2671 case 0b00010: 2672 switch (((inst >> 20) & 0b1111111)) { 2673 case 0b0000000: op = rv_op_sha256sum0; break; 2674 case 0b0000001: op = rv_op_sha256sum1; break; 2675 case 0b0000010: op = rv_op_sha256sig0; break; 2676 case 0b0000011: op = rv_op_sha256sig1; break; 2677 case 0b0000100: op = rv_op_sha512sum0; break; 2678 case 0b0000101: op = rv_op_sha512sum1; break; 2679 case 0b0000110: op = rv_op_sha512sig0; break; 2680 case 0b0000111: op = rv_op_sha512sig1; break; 2681 case 0b0001000: op = rv_op_sm3p0; break; 2682 case 0b0001001: op = rv_op_sm3p1; break; 2683 } 2684 break; 2685 case 0b00101: op = rv_op_bseti; break; 2686 case 0b00110: 2687 switch (((inst >> 20) & 0b1111111)) { 2688 case 0b0000000: op = rv_op_aes64im; break; 2689 default: 2690 if (((inst >> 24) & 0b0111) == 0b001) { 2691 op = rv_op_aes64ks1i; 2692 } 2693 break; 2694 } 2695 break; 2696 case 0b01001: op = rv_op_bclri; break; 2697 case 0b01101: op = rv_op_binvi; break; 2698 case 0b01100: 2699 switch (((inst >> 20) & 0b1111111)) { 2700 case 0b0000000: op = rv_op_clz; break; 2701 case 0b0000001: op = rv_op_ctz; break; 2702 case 0b0000010: op = rv_op_cpop; break; 2703 /* 0b0000011 */ 2704 case 0b0000100: op = rv_op_sext_b; break; 2705 case 0b0000101: op = rv_op_sext_h; break; 2706 } 2707 break; 2708 } 2709 break; 2710 case 2: op = rv_op_slti; break; 2711 case 3: op = rv_op_sltiu; break; 2712 case 4: op = rv_op_xori; break; 2713 case 5: 2714 switch (((inst >> 27) & 0b11111)) { 2715 case 0b00000: op = rv_op_srli; break; 2716 case 0b00001: 2717 switch (((inst >> 20) & 0b1111111)) { 2718 case 0b0001111: op = rv_op_unzip; break; 2719 } 2720 break; 2721 case 0b00101: op = rv_op_orc_b; break; 2722 case 0b01000: op = rv_op_srai; break; 2723 case 0b01001: op = rv_op_bexti; break; 2724 case 0b01100: op = rv_op_rori; break; 2725 case 0b01101: 2726 switch ((inst >> 20) & 0b1111111) { 2727 case 0b0011000: op = rv_op_rev8; break; 2728 case 0b0111000: op = rv_op_rev8; break; 2729 case 0b0000111: op = rv_op_brev8; break; 2730 } 2731 break; 2732 } 2733 break; 2734 case 6: op = rv_op_ori; break; 2735 case 7: op = rv_op_andi; break; 2736 } 2737 break; 2738 case 5: op = rv_op_auipc; break; 2739 case 6: 2740 switch (((inst >> 12) & 0b111)) { 2741 case 0: op = rv_op_addiw; break; 2742 case 1: 2743 switch (((inst >> 26) & 0b111111)) { 2744 case 0: op = rv_op_slliw; break; 2745 case 2: op = rv_op_slli_uw; break; 2746 case 24: 2747 switch ((inst >> 20) & 0b11111) { 2748 case 0b00000: op = rv_op_clzw; break; 2749 case 0b00001: op = rv_op_ctzw; break; 2750 case 0b00010: op = rv_op_cpopw; break; 2751 } 2752 break; 2753 } 2754 break; 2755 case 5: 2756 switch (((inst >> 25) & 0b1111111)) { 2757 case 0: op = rv_op_srliw; break; 2758 case 32: op = rv_op_sraiw; break; 2759 case 48: op = rv_op_roriw; break; 2760 } 2761 break; 2762 } 2763 break; 2764 case 8: 2765 switch (((inst >> 12) & 0b111)) { 2766 case 0: op = rv_op_sb; break; 2767 case 1: op = rv_op_sh; break; 2768 case 2: op = rv_op_sw; break; 2769 case 3: op = rv_op_sd; break; 2770 case 4: op = rv_op_sq; break; 2771 } 2772 break; 2773 case 9: 2774 switch (((inst >> 12) & 0b111)) { 2775 case 0: 2776 switch (((inst >> 20) & 0b111111111111)) { 2777 case 40: op = rv_op_vs1r_v; break; 2778 case 552: op = rv_op_vs2r_v; break; 2779 case 1576: op = rv_op_vs4r_v; break; 2780 case 3624: op = rv_op_vs8r_v; break; 2781 } 2782 switch (((inst >> 26) & 0b111)) { 2783 case 0: 2784 switch (((inst >> 20) & 0b11111)) { 2785 case 0: op = rv_op_vse8_v; break; 2786 case 11: op = rv_op_vsm_v; break; 2787 } 2788 break; 2789 case 1: op = rv_op_vsuxei8_v; break; 2790 case 2: op = rv_op_vsse8_v; break; 2791 case 3: op = rv_op_vsoxei8_v; break; 2792 } 2793 break; 2794 case 2: op = rv_op_fsw; break; 2795 case 3: op = rv_op_fsd; break; 2796 case 4: op = rv_op_fsq; break; 2797 case 5: 2798 switch (((inst >> 26) & 0b111)) { 2799 case 0: 2800 switch (((inst >> 20) & 0b11111)) { 2801 case 0: op = rv_op_vse16_v; break; 2802 } 2803 break; 2804 case 1: op = rv_op_vsuxei16_v; break; 2805 case 2: op = rv_op_vsse16_v; break; 2806 case 3: op = rv_op_vsoxei16_v; break; 2807 } 2808 break; 2809 case 6: 2810 switch (((inst >> 26) & 0b111)) { 2811 case 0: 2812 switch (((inst >> 20) & 0b11111)) { 2813 case 0: op = rv_op_vse32_v; break; 2814 } 2815 break; 2816 case 1: op = rv_op_vsuxei32_v; break; 2817 case 2: op = rv_op_vsse32_v; break; 2818 case 3: op = rv_op_vsoxei32_v; break; 2819 } 2820 break; 2821 case 7: 2822 switch (((inst >> 26) & 0b111)) { 2823 case 0: 2824 switch (((inst >> 20) & 0b11111)) { 2825 case 0: op = rv_op_vse64_v; break; 2826 } 2827 break; 2828 case 1: op = rv_op_vsuxei64_v; break; 2829 case 2: op = rv_op_vsse64_v; break; 2830 case 3: op = rv_op_vsoxei64_v; break; 2831 } 2832 break; 2833 } 2834 break; 2835 case 11: 2836 switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 2837 case 2: op = rv_op_amoadd_w; break; 2838 case 3: op = rv_op_amoadd_d; break; 2839 case 4: op = rv_op_amoadd_q; break; 2840 case 10: op = rv_op_amoswap_w; break; 2841 case 11: op = rv_op_amoswap_d; break; 2842 case 12: op = rv_op_amoswap_q; break; 2843 case 18: 2844 switch (((inst >> 20) & 0b11111)) { 2845 case 0: op = rv_op_lr_w; break; 2846 } 2847 break; 2848 case 19: 2849 switch (((inst >> 20) & 0b11111)) { 2850 case 0: op = rv_op_lr_d; break; 2851 } 2852 break; 2853 case 20: 2854 switch (((inst >> 20) & 0b11111)) { 2855 case 0: op = rv_op_lr_q; break; 2856 } 2857 break; 2858 case 26: op = rv_op_sc_w; break; 2859 case 27: op = rv_op_sc_d; break; 2860 case 28: op = rv_op_sc_q; break; 2861 case 34: op = rv_op_amoxor_w; break; 2862 case 35: op = rv_op_amoxor_d; break; 2863 case 36: op = rv_op_amoxor_q; break; 2864 case 66: op = rv_op_amoor_w; break; 2865 case 67: op = rv_op_amoor_d; break; 2866 case 68: op = rv_op_amoor_q; break; 2867 case 98: op = rv_op_amoand_w; break; 2868 case 99: op = rv_op_amoand_d; break; 2869 case 100: op = rv_op_amoand_q; break; 2870 case 130: op = rv_op_amomin_w; break; 2871 case 131: op = rv_op_amomin_d; break; 2872 case 132: op = rv_op_amomin_q; break; 2873 case 162: op = rv_op_amomax_w; break; 2874 case 163: op = rv_op_amomax_d; break; 2875 case 164: op = rv_op_amomax_q; break; 2876 case 194: op = rv_op_amominu_w; break; 2877 case 195: op = rv_op_amominu_d; break; 2878 case 196: op = rv_op_amominu_q; break; 2879 case 226: op = rv_op_amomaxu_w; break; 2880 case 227: op = rv_op_amomaxu_d; break; 2881 case 228: op = rv_op_amomaxu_q; break; 2882 } 2883 break; 2884 case 12: 2885 switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { 2886 case 0: op = rv_op_add; break; 2887 case 1: op = rv_op_sll; break; 2888 case 2: op = rv_op_slt; break; 2889 case 3: op = rv_op_sltu; break; 2890 case 4: op = rv_op_xor; break; 2891 case 5: op = rv_op_srl; break; 2892 case 6: op = rv_op_or; break; 2893 case 7: op = rv_op_and; break; 2894 case 8: op = rv_op_mul; break; 2895 case 9: op = rv_op_mulh; break; 2896 case 10: op = rv_op_mulhsu; break; 2897 case 11: op = rv_op_mulhu; break; 2898 case 12: op = rv_op_div; break; 2899 case 13: op = rv_op_divu; break; 2900 case 14: op = rv_op_rem; break; 2901 case 15: op = rv_op_remu; break; 2902 case 36: 2903 switch ((inst >> 20) & 0b11111) { 2904 case 0: op = rv_op_zext_h; break; 2905 default: op = rv_op_pack; break; 2906 } 2907 break; 2908 case 39: op = rv_op_packh; break; 2909 2910 case 41: op = rv_op_clmul; break; 2911 case 42: op = rv_op_clmulr; break; 2912 case 43: op = rv_op_clmulh; break; 2913 case 44: op = rv_op_min; break; 2914 case 45: op = rv_op_minu; break; 2915 case 46: op = rv_op_max; break; 2916 case 47: op = rv_op_maxu; break; 2917 case 130: op = rv_op_sh1add; break; 2918 case 132: op = rv_op_sh2add; break; 2919 case 134: op = rv_op_sh3add; break; 2920 case 161: op = rv_op_bset; break; 2921 case 162: op = rv_op_xperm4; break; 2922 case 164: op = rv_op_xperm8; break; 2923 case 200: op = rv_op_aes64es; break; 2924 case 216: op = rv_op_aes64esm; break; 2925 case 232: op = rv_op_aes64ds; break; 2926 case 248: op = rv_op_aes64dsm; break; 2927 case 256: op = rv_op_sub; break; 2928 case 260: op = rv_op_xnor; break; 2929 case 261: op = rv_op_sra; break; 2930 case 262: op = rv_op_orn; break; 2931 case 263: op = rv_op_andn; break; 2932 case 289: op = rv_op_bclr; break; 2933 case 293: op = rv_op_bext; break; 2934 case 320: op = rv_op_sha512sum0r; break; 2935 case 328: op = rv_op_sha512sum1r; break; 2936 case 336: op = rv_op_sha512sig0l; break; 2937 case 344: op = rv_op_sha512sig1l; break; 2938 case 368: op = rv_op_sha512sig0h; break; 2939 case 376: op = rv_op_sha512sig1h; break; 2940 case 385: op = rv_op_rol; break; 2941 case 389: op = rv_op_ror; break; 2942 case 417: op = rv_op_binv; break; 2943 case 504: op = rv_op_aes64ks2; break; 2944 } 2945 switch ((inst >> 25) & 0b0011111) { 2946 case 17: op = rv_op_aes32esi; break; 2947 case 19: op = rv_op_aes32esmi; break; 2948 case 21: op = rv_op_aes32dsi; break; 2949 case 23: op = rv_op_aes32dsmi; break; 2950 case 24: op = rv_op_sm4ed; break; 2951 case 26: op = rv_op_sm4ks; break; 2952 } 2953 break; 2954 case 13: op = rv_op_lui; break; 2955 case 14: 2956 switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { 2957 case 0: op = rv_op_addw; break; 2958 case 1: op = rv_op_sllw; break; 2959 case 5: op = rv_op_srlw; break; 2960 case 8: op = rv_op_mulw; break; 2961 case 12: op = rv_op_divw; break; 2962 case 13: op = rv_op_divuw; break; 2963 case 14: op = rv_op_remw; break; 2964 case 15: op = rv_op_remuw; break; 2965 case 32: op = rv_op_add_uw; break; 2966 case 36: 2967 switch ((inst >> 20) & 0b11111) { 2968 case 0: op = rv_op_zext_h; break; 2969 default: op = rv_op_packw; break; 2970 } 2971 break; 2972 case 130: op = rv_op_sh1add_uw; break; 2973 case 132: op = rv_op_sh2add_uw; break; 2974 case 134: op = rv_op_sh3add_uw; break; 2975 case 256: op = rv_op_subw; break; 2976 case 261: op = rv_op_sraw; break; 2977 case 385: op = rv_op_rolw; break; 2978 case 389: op = rv_op_rorw; break; 2979 } 2980 break; 2981 case 16: 2982 switch (((inst >> 25) & 0b11)) { 2983 case 0: op = rv_op_fmadd_s; break; 2984 case 1: op = rv_op_fmadd_d; break; 2985 case 3: op = rv_op_fmadd_q; break; 2986 } 2987 break; 2988 case 17: 2989 switch (((inst >> 25) & 0b11)) { 2990 case 0: op = rv_op_fmsub_s; break; 2991 case 1: op = rv_op_fmsub_d; break; 2992 case 3: op = rv_op_fmsub_q; break; 2993 } 2994 break; 2995 case 18: 2996 switch (((inst >> 25) & 0b11)) { 2997 case 0: op = rv_op_fnmsub_s; break; 2998 case 1: op = rv_op_fnmsub_d; break; 2999 case 3: op = rv_op_fnmsub_q; break; 3000 } 3001 break; 3002 case 19: 3003 switch (((inst >> 25) & 0b11)) { 3004 case 0: op = rv_op_fnmadd_s; break; 3005 case 1: op = rv_op_fnmadd_d; break; 3006 case 3: op = rv_op_fnmadd_q; break; 3007 } 3008 break; 3009 case 20: 3010 switch (((inst >> 25) & 0b1111111)) { 3011 case 0: op = rv_op_fadd_s; break; 3012 case 1: op = rv_op_fadd_d; break; 3013 case 3: op = rv_op_fadd_q; break; 3014 case 4: op = rv_op_fsub_s; break; 3015 case 5: op = rv_op_fsub_d; break; 3016 case 7: op = rv_op_fsub_q; break; 3017 case 8: op = rv_op_fmul_s; break; 3018 case 9: op = rv_op_fmul_d; break; 3019 case 11: op = rv_op_fmul_q; break; 3020 case 12: op = rv_op_fdiv_s; break; 3021 case 13: op = rv_op_fdiv_d; break; 3022 case 15: op = rv_op_fdiv_q; break; 3023 case 16: 3024 switch (((inst >> 12) & 0b111)) { 3025 case 0: op = rv_op_fsgnj_s; break; 3026 case 1: op = rv_op_fsgnjn_s; break; 3027 case 2: op = rv_op_fsgnjx_s; break; 3028 } 3029 break; 3030 case 17: 3031 switch (((inst >> 12) & 0b111)) { 3032 case 0: op = rv_op_fsgnj_d; break; 3033 case 1: op = rv_op_fsgnjn_d; break; 3034 case 2: op = rv_op_fsgnjx_d; break; 3035 } 3036 break; 3037 case 19: 3038 switch (((inst >> 12) & 0b111)) { 3039 case 0: op = rv_op_fsgnj_q; break; 3040 case 1: op = rv_op_fsgnjn_q; break; 3041 case 2: op = rv_op_fsgnjx_q; break; 3042 } 3043 break; 3044 case 20: 3045 switch (((inst >> 12) & 0b111)) { 3046 case 0: op = rv_op_fmin_s; break; 3047 case 1: op = rv_op_fmax_s; break; 3048 } 3049 break; 3050 case 21: 3051 switch (((inst >> 12) & 0b111)) { 3052 case 0: op = rv_op_fmin_d; break; 3053 case 1: op = rv_op_fmax_d; break; 3054 } 3055 break; 3056 case 23: 3057 switch (((inst >> 12) & 0b111)) { 3058 case 0: op = rv_op_fmin_q; break; 3059 case 1: op = rv_op_fmax_q; break; 3060 } 3061 break; 3062 case 32: 3063 switch (((inst >> 20) & 0b11111)) { 3064 case 1: op = rv_op_fcvt_s_d; break; 3065 case 3: op = rv_op_fcvt_s_q; break; 3066 } 3067 break; 3068 case 33: 3069 switch (((inst >> 20) & 0b11111)) { 3070 case 0: op = rv_op_fcvt_d_s; break; 3071 case 3: op = rv_op_fcvt_d_q; break; 3072 } 3073 break; 3074 case 35: 3075 switch (((inst >> 20) & 0b11111)) { 3076 case 0: op = rv_op_fcvt_q_s; break; 3077 case 1: op = rv_op_fcvt_q_d; break; 3078 } 3079 break; 3080 case 44: 3081 switch (((inst >> 20) & 0b11111)) { 3082 case 0: op = rv_op_fsqrt_s; break; 3083 } 3084 break; 3085 case 45: 3086 switch (((inst >> 20) & 0b11111)) { 3087 case 0: op = rv_op_fsqrt_d; break; 3088 } 3089 break; 3090 case 47: 3091 switch (((inst >> 20) & 0b11111)) { 3092 case 0: op = rv_op_fsqrt_q; break; 3093 } 3094 break; 3095 case 80: 3096 switch (((inst >> 12) & 0b111)) { 3097 case 0: op = rv_op_fle_s; break; 3098 case 1: op = rv_op_flt_s; break; 3099 case 2: op = rv_op_feq_s; break; 3100 } 3101 break; 3102 case 81: 3103 switch (((inst >> 12) & 0b111)) { 3104 case 0: op = rv_op_fle_d; break; 3105 case 1: op = rv_op_flt_d; break; 3106 case 2: op = rv_op_feq_d; break; 3107 } 3108 break; 3109 case 83: 3110 switch (((inst >> 12) & 0b111)) { 3111 case 0: op = rv_op_fle_q; break; 3112 case 1: op = rv_op_flt_q; break; 3113 case 2: op = rv_op_feq_q; break; 3114 } 3115 break; 3116 case 96: 3117 switch (((inst >> 20) & 0b11111)) { 3118 case 0: op = rv_op_fcvt_w_s; break; 3119 case 1: op = rv_op_fcvt_wu_s; break; 3120 case 2: op = rv_op_fcvt_l_s; break; 3121 case 3: op = rv_op_fcvt_lu_s; break; 3122 } 3123 break; 3124 case 97: 3125 switch (((inst >> 20) & 0b11111)) { 3126 case 0: op = rv_op_fcvt_w_d; break; 3127 case 1: op = rv_op_fcvt_wu_d; break; 3128 case 2: op = rv_op_fcvt_l_d; break; 3129 case 3: op = rv_op_fcvt_lu_d; break; 3130 } 3131 break; 3132 case 99: 3133 switch (((inst >> 20) & 0b11111)) { 3134 case 0: op = rv_op_fcvt_w_q; break; 3135 case 1: op = rv_op_fcvt_wu_q; break; 3136 case 2: op = rv_op_fcvt_l_q; break; 3137 case 3: op = rv_op_fcvt_lu_q; break; 3138 } 3139 break; 3140 case 104: 3141 switch (((inst >> 20) & 0b11111)) { 3142 case 0: op = rv_op_fcvt_s_w; break; 3143 case 1: op = rv_op_fcvt_s_wu; break; 3144 case 2: op = rv_op_fcvt_s_l; break; 3145 case 3: op = rv_op_fcvt_s_lu; break; 3146 } 3147 break; 3148 case 105: 3149 switch (((inst >> 20) & 0b11111)) { 3150 case 0: op = rv_op_fcvt_d_w; break; 3151 case 1: op = rv_op_fcvt_d_wu; break; 3152 case 2: op = rv_op_fcvt_d_l; break; 3153 case 3: op = rv_op_fcvt_d_lu; break; 3154 } 3155 break; 3156 case 107: 3157 switch (((inst >> 20) & 0b11111)) { 3158 case 0: op = rv_op_fcvt_q_w; break; 3159 case 1: op = rv_op_fcvt_q_wu; break; 3160 case 2: op = rv_op_fcvt_q_l; break; 3161 case 3: op = rv_op_fcvt_q_lu; break; 3162 } 3163 break; 3164 case 112: 3165 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3166 case 0: op = rv_op_fmv_x_s; break; 3167 case 1: op = rv_op_fclass_s; break; 3168 } 3169 break; 3170 case 113: 3171 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3172 case 0: op = rv_op_fmv_x_d; break; 3173 case 1: op = rv_op_fclass_d; break; 3174 } 3175 break; 3176 case 115: 3177 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3178 case 0: op = rv_op_fmv_x_q; break; 3179 case 1: op = rv_op_fclass_q; break; 3180 } 3181 break; 3182 case 120: 3183 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3184 case 0: op = rv_op_fmv_s_x; break; 3185 } 3186 break; 3187 case 121: 3188 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3189 case 0: op = rv_op_fmv_d_x; break; 3190 } 3191 break; 3192 case 123: 3193 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3194 case 0: op = rv_op_fmv_q_x; break; 3195 } 3196 break; 3197 } 3198 break; 3199 case 21: 3200 switch (((inst >> 12) & 0b111)) { 3201 case 0: 3202 switch (((inst >> 26) & 0b111111)) { 3203 case 0: op = rv_op_vadd_vv; break; 3204 case 2: op = rv_op_vsub_vv; break; 3205 case 4: op = rv_op_vminu_vv; break; 3206 case 5: op = rv_op_vmin_vv; break; 3207 case 6: op = rv_op_vmaxu_vv; break; 3208 case 7: op = rv_op_vmax_vv; break; 3209 case 9: op = rv_op_vand_vv; break; 3210 case 10: op = rv_op_vor_vv; break; 3211 case 11: op = rv_op_vxor_vv; break; 3212 case 12: op = rv_op_vrgather_vv; break; 3213 case 14: op = rv_op_vrgatherei16_vv; break; 3214 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break; 3215 case 17: op = rv_op_vmadc_vvm; break; 3216 case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break; 3217 case 19: op = rv_op_vmsbc_vvm; break; 3218 case 23: 3219 if (((inst >> 20) & 0b111111) == 32) 3220 op = rv_op_vmv_v_v; 3221 else if (((inst >> 25) & 1) == 0) 3222 op = rv_op_vmerge_vvm; 3223 break; 3224 case 24: op = rv_op_vmseq_vv; break; 3225 case 25: op = rv_op_vmsne_vv; break; 3226 case 26: op = rv_op_vmsltu_vv; break; 3227 case 27: op = rv_op_vmslt_vv; break; 3228 case 28: op = rv_op_vmsleu_vv; break; 3229 case 29: op = rv_op_vmsle_vv; break; 3230 case 32: op = rv_op_vsaddu_vv; break; 3231 case 33: op = rv_op_vsadd_vv; break; 3232 case 34: op = rv_op_vssubu_vv; break; 3233 case 35: op = rv_op_vssub_vv; break; 3234 case 37: op = rv_op_vsll_vv; break; 3235 case 39: op = rv_op_vsmul_vv; break; 3236 case 40: op = rv_op_vsrl_vv; break; 3237 case 41: op = rv_op_vsra_vv; break; 3238 case 42: op = rv_op_vssrl_vv; break; 3239 case 43: op = rv_op_vssra_vv; break; 3240 case 44: op = rv_op_vnsrl_wv; break; 3241 case 45: op = rv_op_vnsra_wv; break; 3242 case 46: op = rv_op_vnclipu_wv; break; 3243 case 47: op = rv_op_vnclip_wv; break; 3244 case 48: op = rv_op_vwredsumu_vs; break; 3245 case 49: op = rv_op_vwredsum_vs; break; 3246 } 3247 break; 3248 case 1: 3249 switch (((inst >> 26) & 0b111111)) { 3250 case 0: op = rv_op_vfadd_vv; break; 3251 case 1: op = rv_op_vfredusum_vs; break; 3252 case 2: op = rv_op_vfsub_vv; break; 3253 case 3: op = rv_op_vfredosum_vs; break; 3254 case 4: op = rv_op_vfmin_vv; break; 3255 case 5: op = rv_op_vfredmin_vs; break; 3256 case 6: op = rv_op_vfmax_vv; break; 3257 case 7: op = rv_op_vfredmax_vs; break; 3258 case 8: op = rv_op_vfsgnj_vv; break; 3259 case 9: op = rv_op_vfsgnjn_vv; break; 3260 case 10: op = rv_op_vfsgnjx_vv; break; 3261 case 16: 3262 switch (((inst >> 15) & 0b11111)) { 3263 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break; 3264 } 3265 break; 3266 case 18: 3267 switch (((inst >> 15) & 0b11111)) { 3268 case 0: op = rv_op_vfcvt_xu_f_v; break; 3269 case 1: op = rv_op_vfcvt_x_f_v; break; 3270 case 2: op = rv_op_vfcvt_f_xu_v; break; 3271 case 3: op = rv_op_vfcvt_f_x_v; break; 3272 case 6: op = rv_op_vfcvt_rtz_xu_f_v; break; 3273 case 7: op = rv_op_vfcvt_rtz_x_f_v; break; 3274 case 8: op = rv_op_vfwcvt_xu_f_v; break; 3275 case 9: op = rv_op_vfwcvt_x_f_v; break; 3276 case 10: op = rv_op_vfwcvt_f_xu_v; break; 3277 case 11: op = rv_op_vfwcvt_f_x_v; break; 3278 case 12: op = rv_op_vfwcvt_f_f_v; break; 3279 case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break; 3280 case 15: op = rv_op_vfwcvt_rtz_x_f_v; break; 3281 case 16: op = rv_op_vfncvt_xu_f_w; break; 3282 case 17: op = rv_op_vfncvt_x_f_w; break; 3283 case 18: op = rv_op_vfncvt_f_xu_w; break; 3284 case 19: op = rv_op_vfncvt_f_x_w; break; 3285 case 20: op = rv_op_vfncvt_f_f_w; break; 3286 case 21: op = rv_op_vfncvt_rod_f_f_w; break; 3287 case 22: op = rv_op_vfncvt_rtz_xu_f_w; break; 3288 case 23: op = rv_op_vfncvt_rtz_x_f_w; break; 3289 } 3290 break; 3291 case 19: 3292 switch (((inst >> 15) & 0b11111)) { 3293 case 0: op = rv_op_vfsqrt_v; break; 3294 case 4: op = rv_op_vfrsqrt7_v; break; 3295 case 5: op = rv_op_vfrec7_v; break; 3296 case 16: op = rv_op_vfclass_v; break; 3297 } 3298 break; 3299 case 24: op = rv_op_vmfeq_vv; break; 3300 case 25: op = rv_op_vmfle_vv; break; 3301 case 27: op = rv_op_vmflt_vv; break; 3302 case 28: op = rv_op_vmfne_vv; break; 3303 case 32: op = rv_op_vfdiv_vv; break; 3304 case 36: op = rv_op_vfmul_vv; break; 3305 case 40: op = rv_op_vfmadd_vv; break; 3306 case 41: op = rv_op_vfnmadd_vv; break; 3307 case 42: op = rv_op_vfmsub_vv; break; 3308 case 43: op = rv_op_vfnmsub_vv; break; 3309 case 44: op = rv_op_vfmacc_vv; break; 3310 case 45: op = rv_op_vfnmacc_vv; break; 3311 case 46: op = rv_op_vfmsac_vv; break; 3312 case 47: op = rv_op_vfnmsac_vv; break; 3313 case 48: op = rv_op_vfwadd_vv; break; 3314 case 49: op = rv_op_vfwredusum_vs; break; 3315 case 50: op = rv_op_vfwsub_vv; break; 3316 case 51: op = rv_op_vfwredosum_vs; break; 3317 case 52: op = rv_op_vfwadd_wv; break; 3318 case 54: op = rv_op_vfwsub_wv; break; 3319 case 56: op = rv_op_vfwmul_vv; break; 3320 case 60: op = rv_op_vfwmacc_vv; break; 3321 case 61: op = rv_op_vfwnmacc_vv; break; 3322 case 62: op = rv_op_vfwmsac_vv; break; 3323 case 63: op = rv_op_vfwnmsac_vv; break; 3324 } 3325 break; 3326 case 2: 3327 switch (((inst >> 26) & 0b111111)) { 3328 case 0: op = rv_op_vredsum_vs; break; 3329 case 1: op = rv_op_vredand_vs; break; 3330 case 2: op = rv_op_vredor_vs; break; 3331 case 3: op = rv_op_vredxor_vs; break; 3332 case 4: op = rv_op_vredminu_vs; break; 3333 case 5: op = rv_op_vredmin_vs; break; 3334 case 6: op = rv_op_vredmaxu_vs; break; 3335 case 7: op = rv_op_vredmax_vs; break; 3336 case 8: op = rv_op_vaaddu_vv; break; 3337 case 9: op = rv_op_vaadd_vv; break; 3338 case 10: op = rv_op_vasubu_vv; break; 3339 case 11: op = rv_op_vasub_vv; break; 3340 case 16: 3341 switch (((inst >> 15) & 0b11111)) { 3342 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break; 3343 case 16: op = rv_op_vcpop_m; break; 3344 case 17: op = rv_op_vfirst_m; break; 3345 } 3346 break; 3347 case 18: 3348 switch (((inst >> 15) & 0b11111)) { 3349 case 2: op = rv_op_vzext_vf8; break; 3350 case 3: op = rv_op_vsext_vf8; break; 3351 case 4: op = rv_op_vzext_vf4; break; 3352 case 5: op = rv_op_vsext_vf4; break; 3353 case 6: op = rv_op_vzext_vf2; break; 3354 case 7: op = rv_op_vsext_vf2; break; 3355 } 3356 break; 3357 case 20: 3358 switch (((inst >> 15) & 0b11111)) { 3359 case 1: op = rv_op_vmsbf_m; break; 3360 case 2: op = rv_op_vmsof_m; break; 3361 case 3: op = rv_op_vmsif_m; break; 3362 case 16: op = rv_op_viota_m; break; 3363 case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break; 3364 } 3365 break; 3366 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break; 3367 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break; 3368 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break; 3369 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break; 3370 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break; 3371 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break; 3372 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break; 3373 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break; 3374 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break; 3375 case 32: op = rv_op_vdivu_vv; break; 3376 case 33: op = rv_op_vdiv_vv; break; 3377 case 34: op = rv_op_vremu_vv; break; 3378 case 35: op = rv_op_vrem_vv; break; 3379 case 36: op = rv_op_vmulhu_vv; break; 3380 case 37: op = rv_op_vmul_vv; break; 3381 case 38: op = rv_op_vmulhsu_vv; break; 3382 case 39: op = rv_op_vmulh_vv; break; 3383 case 41: op = rv_op_vmadd_vv; break; 3384 case 43: op = rv_op_vnmsub_vv; break; 3385 case 45: op = rv_op_vmacc_vv; break; 3386 case 47: op = rv_op_vnmsac_vv; break; 3387 case 48: op = rv_op_vwaddu_vv; break; 3388 case 49: op = rv_op_vwadd_vv; break; 3389 case 50: op = rv_op_vwsubu_vv; break; 3390 case 51: op = rv_op_vwsub_vv; break; 3391 case 52: op = rv_op_vwaddu_wv; break; 3392 case 53: op = rv_op_vwadd_wv; break; 3393 case 54: op = rv_op_vwsubu_wv; break; 3394 case 55: op = rv_op_vwsub_wv; break; 3395 case 56: op = rv_op_vwmulu_vv; break; 3396 case 58: op = rv_op_vwmulsu_vv; break; 3397 case 59: op = rv_op_vwmul_vv; break; 3398 case 60: op = rv_op_vwmaccu_vv; break; 3399 case 61: op = rv_op_vwmacc_vv; break; 3400 case 63: op = rv_op_vwmaccsu_vv; break; 3401 } 3402 break; 3403 case 3: 3404 switch (((inst >> 26) & 0b111111)) { 3405 case 0: op = rv_op_vadd_vi; break; 3406 case 3: op = rv_op_vrsub_vi; break; 3407 case 9: op = rv_op_vand_vi; break; 3408 case 10: op = rv_op_vor_vi; break; 3409 case 11: op = rv_op_vxor_vi; break; 3410 case 12: op = rv_op_vrgather_vi; break; 3411 case 14: op = rv_op_vslideup_vi; break; 3412 case 15: op = rv_op_vslidedown_vi; break; 3413 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break; 3414 case 17: op = rv_op_vmadc_vim; break; 3415 case 23: 3416 if (((inst >> 20) & 0b111111) == 32) 3417 op = rv_op_vmv_v_i; 3418 else if (((inst >> 25) & 1) == 0) 3419 op = rv_op_vmerge_vim; 3420 break; 3421 case 24: op = rv_op_vmseq_vi; break; 3422 case 25: op = rv_op_vmsne_vi; break; 3423 case 28: op = rv_op_vmsleu_vi; break; 3424 case 29: op = rv_op_vmsle_vi; break; 3425 case 30: op = rv_op_vmsgtu_vi; break; 3426 case 31: op = rv_op_vmsgt_vi; break; 3427 case 32: op = rv_op_vsaddu_vi; break; 3428 case 33: op = rv_op_vsadd_vi; break; 3429 case 37: op = rv_op_vsll_vi; break; 3430 case 39: 3431 switch (((inst >> 15) & 0b11111)) { 3432 case 0: op = rv_op_vmv1r_v; break; 3433 case 1: op = rv_op_vmv2r_v; break; 3434 case 3: op = rv_op_vmv4r_v; break; 3435 case 7: op = rv_op_vmv8r_v; break; 3436 } 3437 break; 3438 case 40: op = rv_op_vsrl_vi; break; 3439 case 41: op = rv_op_vsra_vi; break; 3440 case 42: op = rv_op_vssrl_vi; break; 3441 case 43: op = rv_op_vssra_vi; break; 3442 case 44: op = rv_op_vnsrl_wi; break; 3443 case 45: op = rv_op_vnsra_wi; break; 3444 case 46: op = rv_op_vnclipu_wi; break; 3445 case 47: op = rv_op_vnclip_wi; break; 3446 } 3447 break; 3448 case 4: 3449 switch (((inst >> 26) & 0b111111)) { 3450 case 0: op = rv_op_vadd_vx; break; 3451 case 2: op = rv_op_vsub_vx; break; 3452 case 3: op = rv_op_vrsub_vx; break; 3453 case 4: op = rv_op_vminu_vx; break; 3454 case 5: op = rv_op_vmin_vx; break; 3455 case 6: op = rv_op_vmaxu_vx; break; 3456 case 7: op = rv_op_vmax_vx; break; 3457 case 9: op = rv_op_vand_vx; break; 3458 case 10: op = rv_op_vor_vx; break; 3459 case 11: op = rv_op_vxor_vx; break; 3460 case 12: op = rv_op_vrgather_vx; break; 3461 case 14: op = rv_op_vslideup_vx; break; 3462 case 15: op = rv_op_vslidedown_vx; break; 3463 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break; 3464 case 17: op = rv_op_vmadc_vxm; break; 3465 case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break; 3466 case 19: op = rv_op_vmsbc_vxm; break; 3467 case 23: 3468 if (((inst >> 20) & 0b111111) == 32) 3469 op = rv_op_vmv_v_x; 3470 else if (((inst >> 25) & 1) == 0) 3471 op = rv_op_vmerge_vxm; 3472 break; 3473 case 24: op = rv_op_vmseq_vx; break; 3474 case 25: op = rv_op_vmsne_vx; break; 3475 case 26: op = rv_op_vmsltu_vx; break; 3476 case 27: op = rv_op_vmslt_vx; break; 3477 case 28: op = rv_op_vmsleu_vx; break; 3478 case 29: op = rv_op_vmsle_vx; break; 3479 case 30: op = rv_op_vmsgtu_vx; break; 3480 case 31: op = rv_op_vmsgt_vx; break; 3481 case 32: op = rv_op_vsaddu_vx; break; 3482 case 33: op = rv_op_vsadd_vx; break; 3483 case 34: op = rv_op_vssubu_vx; break; 3484 case 35: op = rv_op_vssub_vx; break; 3485 case 37: op = rv_op_vsll_vx; break; 3486 case 39: op = rv_op_vsmul_vx; break; 3487 case 40: op = rv_op_vsrl_vx; break; 3488 case 41: op = rv_op_vsra_vx; break; 3489 case 42: op = rv_op_vssrl_vx; break; 3490 case 43: op = rv_op_vssra_vx; break; 3491 case 44: op = rv_op_vnsrl_wx; break; 3492 case 45: op = rv_op_vnsra_wx; break; 3493 case 46: op = rv_op_vnclipu_wx; break; 3494 case 47: op = rv_op_vnclip_wx; break; 3495 } 3496 break; 3497 case 5: 3498 switch (((inst >> 26) & 0b111111)) { 3499 case 0: op = rv_op_vfadd_vf; break; 3500 case 2: op = rv_op_vfsub_vf; break; 3501 case 4: op = rv_op_vfmin_vf; break; 3502 case 6: op = rv_op_vfmax_vf; break; 3503 case 8: op = rv_op_vfsgnj_vf; break; 3504 case 9: op = rv_op_vfsgnjn_vf; break; 3505 case 10: op = rv_op_vfsgnjx_vf; break; 3506 case 14: op = rv_op_vfslide1up_vf; break; 3507 case 15: op = rv_op_vfslide1down_vf; break; 3508 case 16: 3509 switch (((inst >> 20) & 0b11111)) { 3510 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break; 3511 } 3512 break; 3513 case 23: 3514 if (((inst >> 25) & 1) == 0) 3515 op = rv_op_vfmerge_vfm; 3516 else if (((inst >> 20) & 0b111111) == 32) 3517 op = rv_op_vfmv_v_f; 3518 break; 3519 case 24: op = rv_op_vmfeq_vf; break; 3520 case 25: op = rv_op_vmfle_vf; break; 3521 case 27: op = rv_op_vmflt_vf; break; 3522 case 28: op = rv_op_vmfne_vf; break; 3523 case 29: op = rv_op_vmfgt_vf; break; 3524 case 31: op = rv_op_vmfge_vf; break; 3525 case 32: op = rv_op_vfdiv_vf; break; 3526 case 33: op = rv_op_vfrdiv_vf; break; 3527 case 36: op = rv_op_vfmul_vf; break; 3528 case 39: op = rv_op_vfrsub_vf; break; 3529 case 40: op = rv_op_vfmadd_vf; break; 3530 case 41: op = rv_op_vfnmadd_vf; break; 3531 case 42: op = rv_op_vfmsub_vf; break; 3532 case 43: op = rv_op_vfnmsub_vf; break; 3533 case 44: op = rv_op_vfmacc_vf; break; 3534 case 45: op = rv_op_vfnmacc_vf; break; 3535 case 46: op = rv_op_vfmsac_vf; break; 3536 case 47: op = rv_op_vfnmsac_vf; break; 3537 case 48: op = rv_op_vfwadd_vf; break; 3538 case 50: op = rv_op_vfwsub_vf; break; 3539 case 52: op = rv_op_vfwadd_wf; break; 3540 case 54: op = rv_op_vfwsub_wf; break; 3541 case 56: op = rv_op_vfwmul_vf; break; 3542 case 60: op = rv_op_vfwmacc_vf; break; 3543 case 61: op = rv_op_vfwnmacc_vf; break; 3544 case 62: op = rv_op_vfwmsac_vf; break; 3545 case 63: op = rv_op_vfwnmsac_vf; break; 3546 } 3547 break; 3548 case 6: 3549 switch (((inst >> 26) & 0b111111)) { 3550 case 8: op = rv_op_vaaddu_vx; break; 3551 case 9: op = rv_op_vaadd_vx; break; 3552 case 10: op = rv_op_vasubu_vx; break; 3553 case 11: op = rv_op_vasub_vx; break; 3554 case 14: op = rv_op_vslide1up_vx; break; 3555 case 15: op = rv_op_vslide1down_vx; break; 3556 case 16: 3557 switch (((inst >> 20) & 0b11111)) { 3558 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break; 3559 } 3560 break; 3561 case 32: op = rv_op_vdivu_vx; break; 3562 case 33: op = rv_op_vdiv_vx; break; 3563 case 34: op = rv_op_vremu_vx; break; 3564 case 35: op = rv_op_vrem_vx; break; 3565 case 36: op = rv_op_vmulhu_vx; break; 3566 case 37: op = rv_op_vmul_vx; break; 3567 case 38: op = rv_op_vmulhsu_vx; break; 3568 case 39: op = rv_op_vmulh_vx; break; 3569 case 41: op = rv_op_vmadd_vx; break; 3570 case 43: op = rv_op_vnmsub_vx; break; 3571 case 45: op = rv_op_vmacc_vx; break; 3572 case 47: op = rv_op_vnmsac_vx; break; 3573 case 48: op = rv_op_vwaddu_vx; break; 3574 case 49: op = rv_op_vwadd_vx; break; 3575 case 50: op = rv_op_vwsubu_vx; break; 3576 case 51: op = rv_op_vwsub_vx; break; 3577 case 52: op = rv_op_vwaddu_wx; break; 3578 case 53: op = rv_op_vwadd_wx; break; 3579 case 54: op = rv_op_vwsubu_wx; break; 3580 case 55: op = rv_op_vwsub_wx; break; 3581 case 56: op = rv_op_vwmulu_vx; break; 3582 case 58: op = rv_op_vwmulsu_vx; break; 3583 case 59: op = rv_op_vwmul_vx; break; 3584 case 60: op = rv_op_vwmaccu_vx; break; 3585 case 61: op = rv_op_vwmacc_vx; break; 3586 case 62: op = rv_op_vwmaccus_vx; break; 3587 case 63: op = rv_op_vwmaccsu_vx; break; 3588 } 3589 break; 3590 case 7: 3591 if (((inst >> 31) & 1) == 0) { 3592 op = rv_op_vsetvli; 3593 } else if ((inst >> 30) & 1) { 3594 op = rv_op_vsetivli; 3595 } else if (((inst >> 25) & 0b11111) == 0) { 3596 op = rv_op_vsetvl; 3597 } 3598 break; 3599 } 3600 break; 3601 case 22: 3602 switch (((inst >> 12) & 0b111)) { 3603 case 0: op = rv_op_addid; break; 3604 case 1: 3605 switch (((inst >> 26) & 0b111111)) { 3606 case 0: op = rv_op_sllid; break; 3607 } 3608 break; 3609 case 5: 3610 switch (((inst >> 26) & 0b111111)) { 3611 case 0: op = rv_op_srlid; break; 3612 case 16: op = rv_op_sraid; break; 3613 } 3614 break; 3615 } 3616 break; 3617 case 24: 3618 switch (((inst >> 12) & 0b111)) { 3619 case 0: op = rv_op_beq; break; 3620 case 1: op = rv_op_bne; break; 3621 case 4: op = rv_op_blt; break; 3622 case 5: op = rv_op_bge; break; 3623 case 6: op = rv_op_bltu; break; 3624 case 7: op = rv_op_bgeu; break; 3625 } 3626 break; 3627 case 25: 3628 switch (((inst >> 12) & 0b111)) { 3629 case 0: op = rv_op_jalr; break; 3630 } 3631 break; 3632 case 27: op = rv_op_jal; break; 3633 case 28: 3634 switch (((inst >> 12) & 0b111)) { 3635 case 0: 3636 switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) { 3637 case 0: 3638 switch (((inst >> 15) & 0b1111111111)) { 3639 case 0: op = rv_op_ecall; break; 3640 case 32: op = rv_op_ebreak; break; 3641 case 64: op = rv_op_uret; break; 3642 } 3643 break; 3644 case 256: 3645 switch (((inst >> 20) & 0b11111)) { 3646 case 2: 3647 switch (((inst >> 15) & 0b11111)) { 3648 case 0: op = rv_op_sret; break; 3649 } 3650 break; 3651 case 4: op = rv_op_sfence_vm; break; 3652 case 5: 3653 switch (((inst >> 15) & 0b11111)) { 3654 case 0: op = rv_op_wfi; break; 3655 } 3656 break; 3657 } 3658 break; 3659 case 288: op = rv_op_sfence_vma; break; 3660 case 512: 3661 switch (((inst >> 15) & 0b1111111111)) { 3662 case 64: op = rv_op_hret; break; 3663 } 3664 break; 3665 case 768: 3666 switch (((inst >> 15) & 0b1111111111)) { 3667 case 64: op = rv_op_mret; break; 3668 } 3669 break; 3670 case 1952: 3671 switch (((inst >> 15) & 0b1111111111)) { 3672 case 576: op = rv_op_dret; break; 3673 } 3674 break; 3675 } 3676 break; 3677 case 1: op = rv_op_csrrw; break; 3678 case 2: op = rv_op_csrrs; break; 3679 case 3: op = rv_op_csrrc; break; 3680 case 5: op = rv_op_csrrwi; break; 3681 case 6: op = rv_op_csrrsi; break; 3682 case 7: op = rv_op_csrrci; break; 3683 } 3684 break; 3685 case 30: 3686 switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { 3687 case 0: op = rv_op_addd; break; 3688 case 1: op = rv_op_slld; break; 3689 case 5: op = rv_op_srld; break; 3690 case 8: op = rv_op_muld; break; 3691 case 12: op = rv_op_divd; break; 3692 case 13: op = rv_op_divud; break; 3693 case 14: op = rv_op_remd; break; 3694 case 15: op = rv_op_remud; break; 3695 case 256: op = rv_op_subd; break; 3696 case 261: op = rv_op_srad; break; 3697 } 3698 break; 3699 } 3700 break; 3701 } 3702 dec->op = op; 3703 } 3704 3705 /* operand extractors */ 3706 3707 static uint32_t operand_rd(rv_inst inst) 3708 { 3709 return (inst << 52) >> 59; 3710 } 3711 3712 static uint32_t operand_rs1(rv_inst inst) 3713 { 3714 return (inst << 44) >> 59; 3715 } 3716 3717 static uint32_t operand_rs2(rv_inst inst) 3718 { 3719 return (inst << 39) >> 59; 3720 } 3721 3722 static uint32_t operand_rs3(rv_inst inst) 3723 { 3724 return (inst << 32) >> 59; 3725 } 3726 3727 static uint32_t operand_aq(rv_inst inst) 3728 { 3729 return (inst << 37) >> 63; 3730 } 3731 3732 static uint32_t operand_rl(rv_inst inst) 3733 { 3734 return (inst << 38) >> 63; 3735 } 3736 3737 static uint32_t operand_pred(rv_inst inst) 3738 { 3739 return (inst << 36) >> 60; 3740 } 3741 3742 static uint32_t operand_succ(rv_inst inst) 3743 { 3744 return (inst << 40) >> 60; 3745 } 3746 3747 static uint32_t operand_rm(rv_inst inst) 3748 { 3749 return (inst << 49) >> 61; 3750 } 3751 3752 static uint32_t operand_shamt5(rv_inst inst) 3753 { 3754 return (inst << 39) >> 59; 3755 } 3756 3757 static uint32_t operand_shamt6(rv_inst inst) 3758 { 3759 return (inst << 38) >> 58; 3760 } 3761 3762 static uint32_t operand_shamt7(rv_inst inst) 3763 { 3764 return (inst << 37) >> 57; 3765 } 3766 3767 static uint32_t operand_crdq(rv_inst inst) 3768 { 3769 return (inst << 59) >> 61; 3770 } 3771 3772 static uint32_t operand_crs1q(rv_inst inst) 3773 { 3774 return (inst << 54) >> 61; 3775 } 3776 3777 static uint32_t operand_crs1rdq(rv_inst inst) 3778 { 3779 return (inst << 54) >> 61; 3780 } 3781 3782 static uint32_t operand_crs2q(rv_inst inst) 3783 { 3784 return (inst << 59) >> 61; 3785 } 3786 3787 static uint32_t calculate_xreg(uint32_t sreg) 3788 { 3789 return sreg < 2 ? sreg + 8 : sreg + 16; 3790 } 3791 3792 static uint32_t operand_sreg1(rv_inst inst) 3793 { 3794 return calculate_xreg((inst << 54) >> 61); 3795 } 3796 3797 static uint32_t operand_sreg2(rv_inst inst) 3798 { 3799 return calculate_xreg((inst << 59) >> 61); 3800 } 3801 3802 static uint32_t operand_crd(rv_inst inst) 3803 { 3804 return (inst << 52) >> 59; 3805 } 3806 3807 static uint32_t operand_crs1(rv_inst inst) 3808 { 3809 return (inst << 52) >> 59; 3810 } 3811 3812 static uint32_t operand_crs1rd(rv_inst inst) 3813 { 3814 return (inst << 52) >> 59; 3815 } 3816 3817 static uint32_t operand_crs2(rv_inst inst) 3818 { 3819 return (inst << 57) >> 59; 3820 } 3821 3822 static uint32_t operand_cimmsh5(rv_inst inst) 3823 { 3824 return (inst << 57) >> 59; 3825 } 3826 3827 static uint32_t operand_csr12(rv_inst inst) 3828 { 3829 return (inst << 32) >> 52; 3830 } 3831 3832 static int32_t operand_imm12(rv_inst inst) 3833 { 3834 return ((int64_t)inst << 32) >> 52; 3835 } 3836 3837 static int32_t operand_imm20(rv_inst inst) 3838 { 3839 return (((int64_t)inst << 32) >> 44) << 12; 3840 } 3841 3842 static int32_t operand_jimm20(rv_inst inst) 3843 { 3844 return (((int64_t)inst << 32) >> 63) << 20 | 3845 ((inst << 33) >> 54) << 1 | 3846 ((inst << 43) >> 63) << 11 | 3847 ((inst << 44) >> 56) << 12; 3848 } 3849 3850 static int32_t operand_simm12(rv_inst inst) 3851 { 3852 return (((int64_t)inst << 32) >> 57) << 5 | 3853 (inst << 52) >> 59; 3854 } 3855 3856 static int32_t operand_sbimm12(rv_inst inst) 3857 { 3858 return (((int64_t)inst << 32) >> 63) << 12 | 3859 ((inst << 33) >> 58) << 5 | 3860 ((inst << 52) >> 60) << 1 | 3861 ((inst << 56) >> 63) << 11; 3862 } 3863 3864 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) 3865 { 3866 int imm = ((inst << 51) >> 63) << 5 | 3867 (inst << 57) >> 59; 3868 if (isa == rv128) { 3869 imm = imm ? imm : 64; 3870 } 3871 return imm; 3872 } 3873 3874 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) 3875 { 3876 int imm = ((inst << 51) >> 63) << 5 | 3877 (inst << 57) >> 59; 3878 if (isa == rv128) { 3879 imm = imm | (imm & 32) << 1; 3880 imm = imm ? imm : 64; 3881 } 3882 return imm; 3883 } 3884 3885 static int32_t operand_cimmi(rv_inst inst) 3886 { 3887 return (((int64_t)inst << 51) >> 63) << 5 | 3888 (inst << 57) >> 59; 3889 } 3890 3891 static int32_t operand_cimmui(rv_inst inst) 3892 { 3893 return (((int64_t)inst << 51) >> 63) << 17 | 3894 ((inst << 57) >> 59) << 12; 3895 } 3896 3897 static uint32_t operand_cimmlwsp(rv_inst inst) 3898 { 3899 return ((inst << 51) >> 63) << 5 | 3900 ((inst << 57) >> 61) << 2 | 3901 ((inst << 60) >> 62) << 6; 3902 } 3903 3904 static uint32_t operand_cimmldsp(rv_inst inst) 3905 { 3906 return ((inst << 51) >> 63) << 5 | 3907 ((inst << 57) >> 62) << 3 | 3908 ((inst << 59) >> 61) << 6; 3909 } 3910 3911 static uint32_t operand_cimmlqsp(rv_inst inst) 3912 { 3913 return ((inst << 51) >> 63) << 5 | 3914 ((inst << 57) >> 63) << 4 | 3915 ((inst << 58) >> 60) << 6; 3916 } 3917 3918 static int32_t operand_cimm16sp(rv_inst inst) 3919 { 3920 return (((int64_t)inst << 51) >> 63) << 9 | 3921 ((inst << 57) >> 63) << 4 | 3922 ((inst << 58) >> 63) << 6 | 3923 ((inst << 59) >> 62) << 7 | 3924 ((inst << 61) >> 63) << 5; 3925 } 3926 3927 static int32_t operand_cimmj(rv_inst inst) 3928 { 3929 return (((int64_t)inst << 51) >> 63) << 11 | 3930 ((inst << 52) >> 63) << 4 | 3931 ((inst << 53) >> 62) << 8 | 3932 ((inst << 55) >> 63) << 10 | 3933 ((inst << 56) >> 63) << 6 | 3934 ((inst << 57) >> 63) << 7 | 3935 ((inst << 58) >> 61) << 1 | 3936 ((inst << 61) >> 63) << 5; 3937 } 3938 3939 static int32_t operand_cimmb(rv_inst inst) 3940 { 3941 return (((int64_t)inst << 51) >> 63) << 8 | 3942 ((inst << 52) >> 62) << 3 | 3943 ((inst << 57) >> 62) << 6 | 3944 ((inst << 59) >> 62) << 1 | 3945 ((inst << 61) >> 63) << 5; 3946 } 3947 3948 static uint32_t operand_cimmswsp(rv_inst inst) 3949 { 3950 return ((inst << 51) >> 60) << 2 | 3951 ((inst << 55) >> 62) << 6; 3952 } 3953 3954 static uint32_t operand_cimmsdsp(rv_inst inst) 3955 { 3956 return ((inst << 51) >> 61) << 3 | 3957 ((inst << 54) >> 61) << 6; 3958 } 3959 3960 static uint32_t operand_cimmsqsp(rv_inst inst) 3961 { 3962 return ((inst << 51) >> 62) << 4 | 3963 ((inst << 53) >> 60) << 6; 3964 } 3965 3966 static uint32_t operand_cimm4spn(rv_inst inst) 3967 { 3968 return ((inst << 51) >> 62) << 4 | 3969 ((inst << 53) >> 60) << 6 | 3970 ((inst << 57) >> 63) << 2 | 3971 ((inst << 58) >> 63) << 3; 3972 } 3973 3974 static uint32_t operand_cimmw(rv_inst inst) 3975 { 3976 return ((inst << 51) >> 61) << 3 | 3977 ((inst << 57) >> 63) << 2 | 3978 ((inst << 58) >> 63) << 6; 3979 } 3980 3981 static uint32_t operand_cimmd(rv_inst inst) 3982 { 3983 return ((inst << 51) >> 61) << 3 | 3984 ((inst << 57) >> 62) << 6; 3985 } 3986 3987 static uint32_t operand_cimmq(rv_inst inst) 3988 { 3989 return ((inst << 51) >> 62) << 4 | 3990 ((inst << 53) >> 63) << 8 | 3991 ((inst << 57) >> 62) << 6; 3992 } 3993 3994 static uint32_t operand_vimm(rv_inst inst) 3995 { 3996 return (int64_t)(inst << 44) >> 59; 3997 } 3998 3999 static uint32_t operand_vzimm11(rv_inst inst) 4000 { 4001 return (inst << 33) >> 53; 4002 } 4003 4004 static uint32_t operand_vzimm10(rv_inst inst) 4005 { 4006 return (inst << 34) >> 54; 4007 } 4008 4009 static uint32_t operand_bs(rv_inst inst) 4010 { 4011 return (inst << 32) >> 62; 4012 } 4013 4014 static uint32_t operand_rnum(rv_inst inst) 4015 { 4016 return (inst << 40) >> 60; 4017 } 4018 4019 static uint32_t operand_vm(rv_inst inst) 4020 { 4021 return (inst << 38) >> 63; 4022 } 4023 4024 static uint32_t operand_uimm_c_lb(rv_inst inst) 4025 { 4026 return (((inst << 58) >> 63) << 1) | 4027 ((inst << 57) >> 63); 4028 } 4029 4030 static uint32_t operand_uimm_c_lh(rv_inst inst) 4031 { 4032 return (((inst << 58) >> 63) << 1); 4033 } 4034 4035 static uint32_t operand_zcmp_spimm(rv_inst inst) 4036 { 4037 return ((inst << 60) >> 62) << 4; 4038 } 4039 4040 static uint32_t operand_zcmp_rlist(rv_inst inst) 4041 { 4042 return ((inst << 56) >> 60); 4043 } 4044 4045 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm) 4046 { 4047 int xlen_bytes_log2 = isa == rv64 ? 3 : 2; 4048 int regs = rlist == 15 ? 13 : rlist - 3; 4049 uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16); 4050 return stack_adj_base + spimm; 4051 } 4052 4053 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa) 4054 { 4055 return calculate_stack_adj(isa, operand_zcmp_rlist(inst), 4056 operand_zcmp_spimm(inst)); 4057 } 4058 4059 static uint32_t operand_tbl_index(rv_inst inst) 4060 { 4061 return ((inst << 54) >> 56); 4062 } 4063 4064 /* decode operands */ 4065 4066 static void decode_inst_operands(rv_decode *dec, rv_isa isa) 4067 { 4068 rv_inst inst = dec->inst; 4069 dec->codec = opcode_data[dec->op].codec; 4070 switch (dec->codec) { 4071 case rv_codec_none: 4072 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4073 dec->imm = 0; 4074 break; 4075 case rv_codec_u: 4076 dec->rd = operand_rd(inst); 4077 dec->rs1 = dec->rs2 = rv_ireg_zero; 4078 dec->imm = operand_imm20(inst); 4079 break; 4080 case rv_codec_uj: 4081 dec->rd = operand_rd(inst); 4082 dec->rs1 = dec->rs2 = rv_ireg_zero; 4083 dec->imm = operand_jimm20(inst); 4084 break; 4085 case rv_codec_i: 4086 dec->rd = operand_rd(inst); 4087 dec->rs1 = operand_rs1(inst); 4088 dec->rs2 = rv_ireg_zero; 4089 dec->imm = operand_imm12(inst); 4090 break; 4091 case rv_codec_i_sh5: 4092 dec->rd = operand_rd(inst); 4093 dec->rs1 = operand_rs1(inst); 4094 dec->rs2 = rv_ireg_zero; 4095 dec->imm = operand_shamt5(inst); 4096 break; 4097 case rv_codec_i_sh6: 4098 dec->rd = operand_rd(inst); 4099 dec->rs1 = operand_rs1(inst); 4100 dec->rs2 = rv_ireg_zero; 4101 dec->imm = operand_shamt6(inst); 4102 break; 4103 case rv_codec_i_sh7: 4104 dec->rd = operand_rd(inst); 4105 dec->rs1 = operand_rs1(inst); 4106 dec->rs2 = rv_ireg_zero; 4107 dec->imm = operand_shamt7(inst); 4108 break; 4109 case rv_codec_i_csr: 4110 dec->rd = operand_rd(inst); 4111 dec->rs1 = operand_rs1(inst); 4112 dec->rs2 = rv_ireg_zero; 4113 dec->imm = operand_csr12(inst); 4114 break; 4115 case rv_codec_s: 4116 dec->rd = rv_ireg_zero; 4117 dec->rs1 = operand_rs1(inst); 4118 dec->rs2 = operand_rs2(inst); 4119 dec->imm = operand_simm12(inst); 4120 break; 4121 case rv_codec_sb: 4122 dec->rd = rv_ireg_zero; 4123 dec->rs1 = operand_rs1(inst); 4124 dec->rs2 = operand_rs2(inst); 4125 dec->imm = operand_sbimm12(inst); 4126 break; 4127 case rv_codec_r: 4128 dec->rd = operand_rd(inst); 4129 dec->rs1 = operand_rs1(inst); 4130 dec->rs2 = operand_rs2(inst); 4131 dec->imm = 0; 4132 break; 4133 case rv_codec_r_m: 4134 dec->rd = operand_rd(inst); 4135 dec->rs1 = operand_rs1(inst); 4136 dec->rs2 = operand_rs2(inst); 4137 dec->imm = 0; 4138 dec->rm = operand_rm(inst); 4139 break; 4140 case rv_codec_r4_m: 4141 dec->rd = operand_rd(inst); 4142 dec->rs1 = operand_rs1(inst); 4143 dec->rs2 = operand_rs2(inst); 4144 dec->rs3 = operand_rs3(inst); 4145 dec->imm = 0; 4146 dec->rm = operand_rm(inst); 4147 break; 4148 case rv_codec_r_a: 4149 dec->rd = operand_rd(inst); 4150 dec->rs1 = operand_rs1(inst); 4151 dec->rs2 = operand_rs2(inst); 4152 dec->imm = 0; 4153 dec->aq = operand_aq(inst); 4154 dec->rl = operand_rl(inst); 4155 break; 4156 case rv_codec_r_l: 4157 dec->rd = operand_rd(inst); 4158 dec->rs1 = operand_rs1(inst); 4159 dec->rs2 = rv_ireg_zero; 4160 dec->imm = 0; 4161 dec->aq = operand_aq(inst); 4162 dec->rl = operand_rl(inst); 4163 break; 4164 case rv_codec_r_f: 4165 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4166 dec->pred = operand_pred(inst); 4167 dec->succ = operand_succ(inst); 4168 dec->imm = 0; 4169 break; 4170 case rv_codec_cb: 4171 dec->rd = rv_ireg_zero; 4172 dec->rs1 = operand_crs1q(inst) + 8; 4173 dec->rs2 = rv_ireg_zero; 4174 dec->imm = operand_cimmb(inst); 4175 break; 4176 case rv_codec_cb_imm: 4177 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4178 dec->rs2 = rv_ireg_zero; 4179 dec->imm = operand_cimmi(inst); 4180 break; 4181 case rv_codec_cb_sh5: 4182 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4183 dec->rs2 = rv_ireg_zero; 4184 dec->imm = operand_cimmsh5(inst); 4185 break; 4186 case rv_codec_cb_sh6: 4187 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4188 dec->rs2 = rv_ireg_zero; 4189 dec->imm = operand_cimmshr6(inst, isa); 4190 break; 4191 case rv_codec_ci: 4192 dec->rd = dec->rs1 = operand_crs1rd(inst); 4193 dec->rs2 = rv_ireg_zero; 4194 dec->imm = operand_cimmi(inst); 4195 break; 4196 case rv_codec_ci_sh5: 4197 dec->rd = dec->rs1 = operand_crs1rd(inst); 4198 dec->rs2 = rv_ireg_zero; 4199 dec->imm = operand_cimmsh5(inst); 4200 break; 4201 case rv_codec_ci_sh6: 4202 dec->rd = dec->rs1 = operand_crs1rd(inst); 4203 dec->rs2 = rv_ireg_zero; 4204 dec->imm = operand_cimmshl6(inst, isa); 4205 break; 4206 case rv_codec_ci_16sp: 4207 dec->rd = rv_ireg_sp; 4208 dec->rs1 = rv_ireg_sp; 4209 dec->rs2 = rv_ireg_zero; 4210 dec->imm = operand_cimm16sp(inst); 4211 break; 4212 case rv_codec_ci_lwsp: 4213 dec->rd = operand_crd(inst); 4214 dec->rs1 = rv_ireg_sp; 4215 dec->rs2 = rv_ireg_zero; 4216 dec->imm = operand_cimmlwsp(inst); 4217 break; 4218 case rv_codec_ci_ldsp: 4219 dec->rd = operand_crd(inst); 4220 dec->rs1 = rv_ireg_sp; 4221 dec->rs2 = rv_ireg_zero; 4222 dec->imm = operand_cimmldsp(inst); 4223 break; 4224 case rv_codec_ci_lqsp: 4225 dec->rd = operand_crd(inst); 4226 dec->rs1 = rv_ireg_sp; 4227 dec->rs2 = rv_ireg_zero; 4228 dec->imm = operand_cimmlqsp(inst); 4229 break; 4230 case rv_codec_ci_li: 4231 dec->rd = operand_crd(inst); 4232 dec->rs1 = rv_ireg_zero; 4233 dec->rs2 = rv_ireg_zero; 4234 dec->imm = operand_cimmi(inst); 4235 break; 4236 case rv_codec_ci_lui: 4237 dec->rd = operand_crd(inst); 4238 dec->rs1 = rv_ireg_zero; 4239 dec->rs2 = rv_ireg_zero; 4240 dec->imm = operand_cimmui(inst); 4241 break; 4242 case rv_codec_ci_none: 4243 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4244 dec->imm = 0; 4245 break; 4246 case rv_codec_ciw_4spn: 4247 dec->rd = operand_crdq(inst) + 8; 4248 dec->rs1 = rv_ireg_sp; 4249 dec->rs2 = rv_ireg_zero; 4250 dec->imm = operand_cimm4spn(inst); 4251 break; 4252 case rv_codec_cj: 4253 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4254 dec->imm = operand_cimmj(inst); 4255 break; 4256 case rv_codec_cj_jal: 4257 dec->rd = rv_ireg_ra; 4258 dec->rs1 = dec->rs2 = rv_ireg_zero; 4259 dec->imm = operand_cimmj(inst); 4260 break; 4261 case rv_codec_cl_lw: 4262 dec->rd = operand_crdq(inst) + 8; 4263 dec->rs1 = operand_crs1q(inst) + 8; 4264 dec->rs2 = rv_ireg_zero; 4265 dec->imm = operand_cimmw(inst); 4266 break; 4267 case rv_codec_cl_ld: 4268 dec->rd = operand_crdq(inst) + 8; 4269 dec->rs1 = operand_crs1q(inst) + 8; 4270 dec->rs2 = rv_ireg_zero; 4271 dec->imm = operand_cimmd(inst); 4272 break; 4273 case rv_codec_cl_lq: 4274 dec->rd = operand_crdq(inst) + 8; 4275 dec->rs1 = operand_crs1q(inst) + 8; 4276 dec->rs2 = rv_ireg_zero; 4277 dec->imm = operand_cimmq(inst); 4278 break; 4279 case rv_codec_cr: 4280 dec->rd = dec->rs1 = operand_crs1rd(inst); 4281 dec->rs2 = operand_crs2(inst); 4282 dec->imm = 0; 4283 break; 4284 case rv_codec_cr_mv: 4285 dec->rd = operand_crd(inst); 4286 dec->rs1 = operand_crs2(inst); 4287 dec->rs2 = rv_ireg_zero; 4288 dec->imm = 0; 4289 break; 4290 case rv_codec_cr_jalr: 4291 dec->rd = rv_ireg_ra; 4292 dec->rs1 = operand_crs1(inst); 4293 dec->rs2 = rv_ireg_zero; 4294 dec->imm = 0; 4295 break; 4296 case rv_codec_cr_jr: 4297 dec->rd = rv_ireg_zero; 4298 dec->rs1 = operand_crs1(inst); 4299 dec->rs2 = rv_ireg_zero; 4300 dec->imm = 0; 4301 break; 4302 case rv_codec_cs: 4303 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4304 dec->rs2 = operand_crs2q(inst) + 8; 4305 dec->imm = 0; 4306 break; 4307 case rv_codec_cs_sw: 4308 dec->rd = rv_ireg_zero; 4309 dec->rs1 = operand_crs1q(inst) + 8; 4310 dec->rs2 = operand_crs2q(inst) + 8; 4311 dec->imm = operand_cimmw(inst); 4312 break; 4313 case rv_codec_cs_sd: 4314 dec->rd = rv_ireg_zero; 4315 dec->rs1 = operand_crs1q(inst) + 8; 4316 dec->rs2 = operand_crs2q(inst) + 8; 4317 dec->imm = operand_cimmd(inst); 4318 break; 4319 case rv_codec_cs_sq: 4320 dec->rd = rv_ireg_zero; 4321 dec->rs1 = operand_crs1q(inst) + 8; 4322 dec->rs2 = operand_crs2q(inst) + 8; 4323 dec->imm = operand_cimmq(inst); 4324 break; 4325 case rv_codec_css_swsp: 4326 dec->rd = rv_ireg_zero; 4327 dec->rs1 = rv_ireg_sp; 4328 dec->rs2 = operand_crs2(inst); 4329 dec->imm = operand_cimmswsp(inst); 4330 break; 4331 case rv_codec_css_sdsp: 4332 dec->rd = rv_ireg_zero; 4333 dec->rs1 = rv_ireg_sp; 4334 dec->rs2 = operand_crs2(inst); 4335 dec->imm = operand_cimmsdsp(inst); 4336 break; 4337 case rv_codec_css_sqsp: 4338 dec->rd = rv_ireg_zero; 4339 dec->rs1 = rv_ireg_sp; 4340 dec->rs2 = operand_crs2(inst); 4341 dec->imm = operand_cimmsqsp(inst); 4342 break; 4343 case rv_codec_k_bs: 4344 dec->rs1 = operand_rs1(inst); 4345 dec->rs2 = operand_rs2(inst); 4346 dec->bs = operand_bs(inst); 4347 break; 4348 case rv_codec_k_rnum: 4349 dec->rd = operand_rd(inst); 4350 dec->rs1 = operand_rs1(inst); 4351 dec->rnum = operand_rnum(inst); 4352 break; 4353 case rv_codec_v_r: 4354 dec->rd = operand_rd(inst); 4355 dec->rs1 = operand_rs1(inst); 4356 dec->rs2 = operand_rs2(inst); 4357 dec->vm = operand_vm(inst); 4358 break; 4359 case rv_codec_v_ldst: 4360 dec->rd = operand_rd(inst); 4361 dec->rs1 = operand_rs1(inst); 4362 dec->vm = operand_vm(inst); 4363 break; 4364 case rv_codec_v_i: 4365 dec->rd = operand_rd(inst); 4366 dec->rs2 = operand_rs2(inst); 4367 dec->imm = operand_vimm(inst); 4368 dec->vm = operand_vm(inst); 4369 break; 4370 case rv_codec_vsetvli: 4371 dec->rd = operand_rd(inst); 4372 dec->rs1 = operand_rs1(inst); 4373 dec->vzimm = operand_vzimm11(inst); 4374 break; 4375 case rv_codec_vsetivli: 4376 dec->rd = operand_rd(inst); 4377 dec->imm = operand_vimm(inst); 4378 dec->vzimm = operand_vzimm10(inst); 4379 break; 4380 case rv_codec_zcb_lb: 4381 dec->rs1 = operand_crs1q(inst) + 8; 4382 dec->rs2 = operand_crs2q(inst) + 8; 4383 dec->imm = operand_uimm_c_lb(inst); 4384 break; 4385 case rv_codec_zcb_lh: 4386 dec->rs1 = operand_crs1q(inst) + 8; 4387 dec->rs2 = operand_crs2q(inst) + 8; 4388 dec->imm = operand_uimm_c_lh(inst); 4389 break; 4390 case rv_codec_zcb_ext: 4391 dec->rd = operand_crs1q(inst) + 8; 4392 break; 4393 case rv_codec_zcb_mul: 4394 dec->rd = operand_crs1rdq(inst) + 8; 4395 dec->rs2 = operand_crs2q(inst) + 8; 4396 break; 4397 case rv_codec_zcmp_cm_pushpop: 4398 dec->imm = operand_zcmp_stack_adj(inst, isa); 4399 dec->rlist = operand_zcmp_rlist(inst); 4400 break; 4401 case rv_codec_zcmp_cm_mv: 4402 dec->rd = operand_sreg1(inst); 4403 dec->rs2 = operand_sreg2(inst); 4404 break; 4405 case rv_codec_zcmt_jt: 4406 dec->imm = operand_tbl_index(inst); 4407 break; 4408 }; 4409 } 4410 4411 /* check constraint */ 4412 4413 static bool check_constraints(rv_decode *dec, const rvc_constraint *c) 4414 { 4415 int32_t imm = dec->imm; 4416 uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2; 4417 while (*c != rvc_end) { 4418 switch (*c) { 4419 case rvc_rd_eq_ra: 4420 if (!(rd == 1)) { 4421 return false; 4422 } 4423 break; 4424 case rvc_rd_eq_x0: 4425 if (!(rd == 0)) { 4426 return false; 4427 } 4428 break; 4429 case rvc_rs1_eq_x0: 4430 if (!(rs1 == 0)) { 4431 return false; 4432 } 4433 break; 4434 case rvc_rs2_eq_x0: 4435 if (!(rs2 == 0)) { 4436 return false; 4437 } 4438 break; 4439 case rvc_rs2_eq_rs1: 4440 if (!(rs2 == rs1)) { 4441 return false; 4442 } 4443 break; 4444 case rvc_rs1_eq_ra: 4445 if (!(rs1 == 1)) { 4446 return false; 4447 } 4448 break; 4449 case rvc_imm_eq_zero: 4450 if (!(imm == 0)) { 4451 return false; 4452 } 4453 break; 4454 case rvc_imm_eq_n1: 4455 if (!(imm == -1)) { 4456 return false; 4457 } 4458 break; 4459 case rvc_imm_eq_p1: 4460 if (!(imm == 1)) { 4461 return false; 4462 } 4463 break; 4464 case rvc_csr_eq_0x001: 4465 if (!(imm == 0x001)) { 4466 return false; 4467 } 4468 break; 4469 case rvc_csr_eq_0x002: 4470 if (!(imm == 0x002)) { 4471 return false; 4472 } 4473 break; 4474 case rvc_csr_eq_0x003: 4475 if (!(imm == 0x003)) { 4476 return false; 4477 } 4478 break; 4479 case rvc_csr_eq_0xc00: 4480 if (!(imm == 0xc00)) { 4481 return false; 4482 } 4483 break; 4484 case rvc_csr_eq_0xc01: 4485 if (!(imm == 0xc01)) { 4486 return false; 4487 } 4488 break; 4489 case rvc_csr_eq_0xc02: 4490 if (!(imm == 0xc02)) { 4491 return false; 4492 } 4493 break; 4494 case rvc_csr_eq_0xc80: 4495 if (!(imm == 0xc80)) { 4496 return false; 4497 } 4498 break; 4499 case rvc_csr_eq_0xc81: 4500 if (!(imm == 0xc81)) { 4501 return false; 4502 } 4503 break; 4504 case rvc_csr_eq_0xc82: 4505 if (!(imm == 0xc82)) { 4506 return false; 4507 } 4508 break; 4509 default: break; 4510 } 4511 c++; 4512 } 4513 return true; 4514 } 4515 4516 /* instruction length */ 4517 4518 static size_t inst_length(rv_inst inst) 4519 { 4520 /* NOTE: supports maximum instruction size of 64-bits */ 4521 4522 /* instruction length coding 4523 * 4524 * aa - 16 bit aa != 11 4525 * bbb11 - 32 bit bbb != 111 4526 * 011111 - 48 bit 4527 * 0111111 - 64 bit 4528 */ 4529 4530 return (inst & 0b11) != 0b11 ? 2 4531 : (inst & 0b11100) != 0b11100 ? 4 4532 : (inst & 0b111111) == 0b011111 ? 6 4533 : (inst & 0b1111111) == 0b0111111 ? 8 4534 : 0; 4535 } 4536 4537 /* format instruction */ 4538 4539 static void append(char *s1, const char *s2, size_t n) 4540 { 4541 size_t l1 = strlen(s1); 4542 if (n - l1 - 1 > 0) { 4543 strncat(s1, s2, n - l1); 4544 } 4545 } 4546 4547 static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) 4548 { 4549 char tmp[64]; 4550 const char *fmt; 4551 4552 fmt = opcode_data[dec->op].format; 4553 while (*fmt) { 4554 switch (*fmt) { 4555 case 'O': 4556 append(buf, opcode_data[dec->op].name, buflen); 4557 break; 4558 case '(': 4559 append(buf, "(", buflen); 4560 break; 4561 case ',': 4562 append(buf, ",", buflen); 4563 break; 4564 case ')': 4565 append(buf, ")", buflen); 4566 break; 4567 case '-': 4568 append(buf, "-", buflen); 4569 break; 4570 case 'b': 4571 snprintf(tmp, sizeof(tmp), "%d", dec->bs); 4572 append(buf, tmp, buflen); 4573 break; 4574 case 'n': 4575 snprintf(tmp, sizeof(tmp), "%d", dec->rnum); 4576 append(buf, tmp, buflen); 4577 break; 4578 case '0': 4579 append(buf, rv_ireg_name_sym[dec->rd], buflen); 4580 break; 4581 case '1': 4582 append(buf, rv_ireg_name_sym[dec->rs1], buflen); 4583 break; 4584 case '2': 4585 append(buf, rv_ireg_name_sym[dec->rs2], buflen); 4586 break; 4587 case '3': 4588 append(buf, rv_freg_name_sym[dec->rd], buflen); 4589 break; 4590 case '4': 4591 append(buf, rv_freg_name_sym[dec->rs1], buflen); 4592 break; 4593 case '5': 4594 append(buf, rv_freg_name_sym[dec->rs2], buflen); 4595 break; 4596 case '6': 4597 append(buf, rv_freg_name_sym[dec->rs3], buflen); 4598 break; 4599 case '7': 4600 snprintf(tmp, sizeof(tmp), "%d", dec->rs1); 4601 append(buf, tmp, buflen); 4602 break; 4603 case 'i': 4604 snprintf(tmp, sizeof(tmp), "%d", dec->imm); 4605 append(buf, tmp, buflen); 4606 break; 4607 case 'u': 4608 snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111)); 4609 append(buf, tmp, buflen); 4610 break; 4611 case 'o': 4612 snprintf(tmp, sizeof(tmp), "%d", dec->imm); 4613 append(buf, tmp, buflen); 4614 while (strlen(buf) < tab * 2) { 4615 append(buf, " ", buflen); 4616 } 4617 snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64, 4618 dec->pc + dec->imm); 4619 append(buf, tmp, buflen); 4620 break; 4621 case 'c': { 4622 const char *name = csr_name(dec->imm & 0xfff); 4623 if (name) { 4624 append(buf, name, buflen); 4625 } else { 4626 snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff); 4627 append(buf, tmp, buflen); 4628 } 4629 break; 4630 } 4631 case 'r': 4632 switch (dec->rm) { 4633 case rv_rm_rne: 4634 append(buf, "rne", buflen); 4635 break; 4636 case rv_rm_rtz: 4637 append(buf, "rtz", buflen); 4638 break; 4639 case rv_rm_rdn: 4640 append(buf, "rdn", buflen); 4641 break; 4642 case rv_rm_rup: 4643 append(buf, "rup", buflen); 4644 break; 4645 case rv_rm_rmm: 4646 append(buf, "rmm", buflen); 4647 break; 4648 case rv_rm_dyn: 4649 append(buf, "dyn", buflen); 4650 break; 4651 default: 4652 append(buf, "inv", buflen); 4653 break; 4654 } 4655 break; 4656 case 'p': 4657 if (dec->pred & rv_fence_i) { 4658 append(buf, "i", buflen); 4659 } 4660 if (dec->pred & rv_fence_o) { 4661 append(buf, "o", buflen); 4662 } 4663 if (dec->pred & rv_fence_r) { 4664 append(buf, "r", buflen); 4665 } 4666 if (dec->pred & rv_fence_w) { 4667 append(buf, "w", buflen); 4668 } 4669 break; 4670 case 's': 4671 if (dec->succ & rv_fence_i) { 4672 append(buf, "i", buflen); 4673 } 4674 if (dec->succ & rv_fence_o) { 4675 append(buf, "o", buflen); 4676 } 4677 if (dec->succ & rv_fence_r) { 4678 append(buf, "r", buflen); 4679 } 4680 if (dec->succ & rv_fence_w) { 4681 append(buf, "w", buflen); 4682 } 4683 break; 4684 case '\t': 4685 while (strlen(buf) < tab) { 4686 append(buf, " ", buflen); 4687 } 4688 break; 4689 case 'A': 4690 if (dec->aq) { 4691 append(buf, ".aq", buflen); 4692 } 4693 break; 4694 case 'R': 4695 if (dec->rl) { 4696 append(buf, ".rl", buflen); 4697 } 4698 break; 4699 case 'l': 4700 append(buf, ",v0", buflen); 4701 break; 4702 case 'm': 4703 if (dec->vm == 0) { 4704 append(buf, ",v0.t", buflen); 4705 } 4706 break; 4707 case 'D': 4708 append(buf, rv_vreg_name_sym[dec->rd], buflen); 4709 break; 4710 case 'E': 4711 append(buf, rv_vreg_name_sym[dec->rs1], buflen); 4712 break; 4713 case 'F': 4714 append(buf, rv_vreg_name_sym[dec->rs2], buflen); 4715 break; 4716 case 'G': 4717 append(buf, rv_vreg_name_sym[dec->rs3], buflen); 4718 break; 4719 case 'v': { 4720 char nbuf[32] = {0}; 4721 const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3); 4722 sprintf(nbuf, "%d", sew); 4723 const int lmul = dec->vzimm & 0b11; 4724 const int flmul = (dec->vzimm >> 2) & 1; 4725 const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu"; 4726 const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu"; 4727 append(buf, "e", buflen); 4728 append(buf, nbuf, buflen); 4729 append(buf, ",m", buflen); 4730 if (flmul) { 4731 switch (lmul) { 4732 case 3: 4733 sprintf(nbuf, "f2"); 4734 break; 4735 case 2: 4736 sprintf(nbuf, "f4"); 4737 break; 4738 case 1: 4739 sprintf(nbuf, "f8"); 4740 break; 4741 } 4742 append(buf, nbuf, buflen); 4743 } else { 4744 sprintf(nbuf, "%d", 1 << lmul); 4745 append(buf, nbuf, buflen); 4746 } 4747 append(buf, ",", buflen); 4748 append(buf, vta, buflen); 4749 append(buf, ",", buflen); 4750 append(buf, vma, buflen); 4751 break; 4752 } 4753 case 'x': { 4754 switch (dec->rlist) { 4755 case 4: 4756 snprintf(tmp, sizeof(tmp), "{ra}"); 4757 break; 4758 case 5: 4759 snprintf(tmp, sizeof(tmp), "{ra, s0}"); 4760 break; 4761 case 15: 4762 snprintf(tmp, sizeof(tmp), "{ra, s0-s11}"); 4763 break; 4764 default: 4765 snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5); 4766 break; 4767 } 4768 append(buf, tmp, buflen); 4769 break; 4770 } 4771 default: 4772 break; 4773 } 4774 fmt++; 4775 } 4776 } 4777 4778 /* lift instruction to pseudo-instruction */ 4779 4780 static void decode_inst_lift_pseudo(rv_decode *dec) 4781 { 4782 const rv_comp_data *comp_data = opcode_data[dec->op].pseudo; 4783 if (!comp_data) { 4784 return; 4785 } 4786 while (comp_data->constraints) { 4787 if (check_constraints(dec, comp_data->constraints)) { 4788 dec->op = comp_data->op; 4789 dec->codec = opcode_data[dec->op].codec; 4790 return; 4791 } 4792 comp_data++; 4793 } 4794 } 4795 4796 /* decompress instruction */ 4797 4798 static void decode_inst_decompress_rv32(rv_decode *dec) 4799 { 4800 int decomp_op = opcode_data[dec->op].decomp_rv32; 4801 if (decomp_op != rv_op_illegal) { 4802 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 4803 && dec->imm == 0) { 4804 dec->op = rv_op_illegal; 4805 } else { 4806 dec->op = decomp_op; 4807 dec->codec = opcode_data[decomp_op].codec; 4808 } 4809 } 4810 } 4811 4812 static void decode_inst_decompress_rv64(rv_decode *dec) 4813 { 4814 int decomp_op = opcode_data[dec->op].decomp_rv64; 4815 if (decomp_op != rv_op_illegal) { 4816 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 4817 && dec->imm == 0) { 4818 dec->op = rv_op_illegal; 4819 } else { 4820 dec->op = decomp_op; 4821 dec->codec = opcode_data[decomp_op].codec; 4822 } 4823 } 4824 } 4825 4826 static void decode_inst_decompress_rv128(rv_decode *dec) 4827 { 4828 int decomp_op = opcode_data[dec->op].decomp_rv128; 4829 if (decomp_op != rv_op_illegal) { 4830 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 4831 && dec->imm == 0) { 4832 dec->op = rv_op_illegal; 4833 } else { 4834 dec->op = decomp_op; 4835 dec->codec = opcode_data[decomp_op].codec; 4836 } 4837 } 4838 } 4839 4840 static void decode_inst_decompress(rv_decode *dec, rv_isa isa) 4841 { 4842 switch (isa) { 4843 case rv32: 4844 decode_inst_decompress_rv32(dec); 4845 break; 4846 case rv64: 4847 decode_inst_decompress_rv64(dec); 4848 break; 4849 case rv128: 4850 decode_inst_decompress_rv128(dec); 4851 break; 4852 } 4853 } 4854 4855 /* disassemble instruction */ 4856 4857 static void 4858 disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst) 4859 { 4860 rv_decode dec = { 0 }; 4861 dec.pc = pc; 4862 dec.inst = inst; 4863 decode_inst_opcode(&dec, isa); 4864 decode_inst_operands(&dec, isa); 4865 decode_inst_decompress(&dec, isa); 4866 decode_inst_lift_pseudo(&dec); 4867 format_inst(buf, buflen, 24, &dec); 4868 } 4869 4870 #define INST_FMT_2 "%04" PRIx64 " " 4871 #define INST_FMT_4 "%08" PRIx64 " " 4872 #define INST_FMT_6 "%012" PRIx64 " " 4873 #define INST_FMT_8 "%016" PRIx64 " " 4874 4875 static int 4876 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) 4877 { 4878 char buf[128] = { 0 }; 4879 bfd_byte packet[2]; 4880 rv_inst inst = 0; 4881 size_t len = 2; 4882 bfd_vma n; 4883 int status; 4884 4885 /* Instructions are made of 2-byte packets in little-endian order */ 4886 for (n = 0; n < len; n += 2) { 4887 status = (*info->read_memory_func)(memaddr + n, packet, 2, info); 4888 if (status != 0) { 4889 /* Don't fail just because we fell off the end. */ 4890 if (n > 0) { 4891 break; 4892 } 4893 (*info->memory_error_func)(status, memaddr, info); 4894 return status; 4895 } 4896 inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n); 4897 if (n == 0) { 4898 len = inst_length(inst); 4899 } 4900 } 4901 4902 switch (len) { 4903 case 2: 4904 (*info->fprintf_func)(info->stream, INST_FMT_2, inst); 4905 break; 4906 case 4: 4907 (*info->fprintf_func)(info->stream, INST_FMT_4, inst); 4908 break; 4909 case 6: 4910 (*info->fprintf_func)(info->stream, INST_FMT_6, inst); 4911 break; 4912 default: 4913 (*info->fprintf_func)(info->stream, INST_FMT_8, inst); 4914 break; 4915 } 4916 4917 disasm_inst(buf, sizeof(buf), isa, memaddr, inst); 4918 (*info->fprintf_func)(info->stream, "%s", buf); 4919 4920 return len; 4921 } 4922 4923 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info) 4924 { 4925 return print_insn_riscv(memaddr, info, rv32); 4926 } 4927 4928 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info) 4929 { 4930 return print_insn_riscv(memaddr, info, rv64); 4931 } 4932 4933 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info) 4934 { 4935 return print_insn_riscv(memaddr, info, rv128); 4936 } 4937