1 /* 2 * QEMU RISC-V Disassembler 3 * 4 * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com> 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/bitops.h" 22 #include "disas/dis-asm.h" 23 #include "target/riscv/cpu_cfg.h" 24 #include "disas/riscv.h" 25 26 /* Vendor extensions */ 27 #include "disas/riscv-xthead.h" 28 #include "disas/riscv-xventana.h" 29 30 typedef enum { 31 /* 0 is reserved for rv_op_illegal. */ 32 rv_op_lui = 1, 33 rv_op_auipc = 2, 34 rv_op_jal = 3, 35 rv_op_jalr = 4, 36 rv_op_beq = 5, 37 rv_op_bne = 6, 38 rv_op_blt = 7, 39 rv_op_bge = 8, 40 rv_op_bltu = 9, 41 rv_op_bgeu = 10, 42 rv_op_lb = 11, 43 rv_op_lh = 12, 44 rv_op_lw = 13, 45 rv_op_lbu = 14, 46 rv_op_lhu = 15, 47 rv_op_sb = 16, 48 rv_op_sh = 17, 49 rv_op_sw = 18, 50 rv_op_addi = 19, 51 rv_op_slti = 20, 52 rv_op_sltiu = 21, 53 rv_op_xori = 22, 54 rv_op_ori = 23, 55 rv_op_andi = 24, 56 rv_op_slli = 25, 57 rv_op_srli = 26, 58 rv_op_srai = 27, 59 rv_op_add = 28, 60 rv_op_sub = 29, 61 rv_op_sll = 30, 62 rv_op_slt = 31, 63 rv_op_sltu = 32, 64 rv_op_xor = 33, 65 rv_op_srl = 34, 66 rv_op_sra = 35, 67 rv_op_or = 36, 68 rv_op_and = 37, 69 rv_op_fence = 38, 70 rv_op_fence_i = 39, 71 rv_op_lwu = 40, 72 rv_op_ld = 41, 73 rv_op_sd = 42, 74 rv_op_addiw = 43, 75 rv_op_slliw = 44, 76 rv_op_srliw = 45, 77 rv_op_sraiw = 46, 78 rv_op_addw = 47, 79 rv_op_subw = 48, 80 rv_op_sllw = 49, 81 rv_op_srlw = 50, 82 rv_op_sraw = 51, 83 rv_op_ldu = 52, 84 rv_op_lq = 53, 85 rv_op_sq = 54, 86 rv_op_addid = 55, 87 rv_op_sllid = 56, 88 rv_op_srlid = 57, 89 rv_op_sraid = 58, 90 rv_op_addd = 59, 91 rv_op_subd = 60, 92 rv_op_slld = 61, 93 rv_op_srld = 62, 94 rv_op_srad = 63, 95 rv_op_mul = 64, 96 rv_op_mulh = 65, 97 rv_op_mulhsu = 66, 98 rv_op_mulhu = 67, 99 rv_op_div = 68, 100 rv_op_divu = 69, 101 rv_op_rem = 70, 102 rv_op_remu = 71, 103 rv_op_mulw = 72, 104 rv_op_divw = 73, 105 rv_op_divuw = 74, 106 rv_op_remw = 75, 107 rv_op_remuw = 76, 108 rv_op_muld = 77, 109 rv_op_divd = 78, 110 rv_op_divud = 79, 111 rv_op_remd = 80, 112 rv_op_remud = 81, 113 rv_op_lr_w = 82, 114 rv_op_sc_w = 83, 115 rv_op_amoswap_w = 84, 116 rv_op_amoadd_w = 85, 117 rv_op_amoxor_w = 86, 118 rv_op_amoor_w = 87, 119 rv_op_amoand_w = 88, 120 rv_op_amomin_w = 89, 121 rv_op_amomax_w = 90, 122 rv_op_amominu_w = 91, 123 rv_op_amomaxu_w = 92, 124 rv_op_lr_d = 93, 125 rv_op_sc_d = 94, 126 rv_op_amoswap_d = 95, 127 rv_op_amoadd_d = 96, 128 rv_op_amoxor_d = 97, 129 rv_op_amoor_d = 98, 130 rv_op_amoand_d = 99, 131 rv_op_amomin_d = 100, 132 rv_op_amomax_d = 101, 133 rv_op_amominu_d = 102, 134 rv_op_amomaxu_d = 103, 135 rv_op_lr_q = 104, 136 rv_op_sc_q = 105, 137 rv_op_amoswap_q = 106, 138 rv_op_amoadd_q = 107, 139 rv_op_amoxor_q = 108, 140 rv_op_amoor_q = 109, 141 rv_op_amoand_q = 110, 142 rv_op_amomin_q = 111, 143 rv_op_amomax_q = 112, 144 rv_op_amominu_q = 113, 145 rv_op_amomaxu_q = 114, 146 rv_op_ecall = 115, 147 rv_op_ebreak = 116, 148 rv_op_uret = 117, 149 rv_op_sret = 118, 150 rv_op_hret = 119, 151 rv_op_mret = 120, 152 rv_op_dret = 121, 153 rv_op_sfence_vm = 122, 154 rv_op_sfence_vma = 123, 155 rv_op_wfi = 124, 156 rv_op_csrrw = 125, 157 rv_op_csrrs = 126, 158 rv_op_csrrc = 127, 159 rv_op_csrrwi = 128, 160 rv_op_csrrsi = 129, 161 rv_op_csrrci = 130, 162 rv_op_flw = 131, 163 rv_op_fsw = 132, 164 rv_op_fmadd_s = 133, 165 rv_op_fmsub_s = 134, 166 rv_op_fnmsub_s = 135, 167 rv_op_fnmadd_s = 136, 168 rv_op_fadd_s = 137, 169 rv_op_fsub_s = 138, 170 rv_op_fmul_s = 139, 171 rv_op_fdiv_s = 140, 172 rv_op_fsgnj_s = 141, 173 rv_op_fsgnjn_s = 142, 174 rv_op_fsgnjx_s = 143, 175 rv_op_fmin_s = 144, 176 rv_op_fmax_s = 145, 177 rv_op_fsqrt_s = 146, 178 rv_op_fle_s = 147, 179 rv_op_flt_s = 148, 180 rv_op_feq_s = 149, 181 rv_op_fcvt_w_s = 150, 182 rv_op_fcvt_wu_s = 151, 183 rv_op_fcvt_s_w = 152, 184 rv_op_fcvt_s_wu = 153, 185 rv_op_fmv_x_s = 154, 186 rv_op_fclass_s = 155, 187 rv_op_fmv_s_x = 156, 188 rv_op_fcvt_l_s = 157, 189 rv_op_fcvt_lu_s = 158, 190 rv_op_fcvt_s_l = 159, 191 rv_op_fcvt_s_lu = 160, 192 rv_op_fld = 161, 193 rv_op_fsd = 162, 194 rv_op_fmadd_d = 163, 195 rv_op_fmsub_d = 164, 196 rv_op_fnmsub_d = 165, 197 rv_op_fnmadd_d = 166, 198 rv_op_fadd_d = 167, 199 rv_op_fsub_d = 168, 200 rv_op_fmul_d = 169, 201 rv_op_fdiv_d = 170, 202 rv_op_fsgnj_d = 171, 203 rv_op_fsgnjn_d = 172, 204 rv_op_fsgnjx_d = 173, 205 rv_op_fmin_d = 174, 206 rv_op_fmax_d = 175, 207 rv_op_fcvt_s_d = 176, 208 rv_op_fcvt_d_s = 177, 209 rv_op_fsqrt_d = 178, 210 rv_op_fle_d = 179, 211 rv_op_flt_d = 180, 212 rv_op_feq_d = 181, 213 rv_op_fcvt_w_d = 182, 214 rv_op_fcvt_wu_d = 183, 215 rv_op_fcvt_d_w = 184, 216 rv_op_fcvt_d_wu = 185, 217 rv_op_fclass_d = 186, 218 rv_op_fcvt_l_d = 187, 219 rv_op_fcvt_lu_d = 188, 220 rv_op_fmv_x_d = 189, 221 rv_op_fcvt_d_l = 190, 222 rv_op_fcvt_d_lu = 191, 223 rv_op_fmv_d_x = 192, 224 rv_op_flq = 193, 225 rv_op_fsq = 194, 226 rv_op_fmadd_q = 195, 227 rv_op_fmsub_q = 196, 228 rv_op_fnmsub_q = 197, 229 rv_op_fnmadd_q = 198, 230 rv_op_fadd_q = 199, 231 rv_op_fsub_q = 200, 232 rv_op_fmul_q = 201, 233 rv_op_fdiv_q = 202, 234 rv_op_fsgnj_q = 203, 235 rv_op_fsgnjn_q = 204, 236 rv_op_fsgnjx_q = 205, 237 rv_op_fmin_q = 206, 238 rv_op_fmax_q = 207, 239 rv_op_fcvt_s_q = 208, 240 rv_op_fcvt_q_s = 209, 241 rv_op_fcvt_d_q = 210, 242 rv_op_fcvt_q_d = 211, 243 rv_op_fsqrt_q = 212, 244 rv_op_fle_q = 213, 245 rv_op_flt_q = 214, 246 rv_op_feq_q = 215, 247 rv_op_fcvt_w_q = 216, 248 rv_op_fcvt_wu_q = 217, 249 rv_op_fcvt_q_w = 218, 250 rv_op_fcvt_q_wu = 219, 251 rv_op_fclass_q = 220, 252 rv_op_fcvt_l_q = 221, 253 rv_op_fcvt_lu_q = 222, 254 rv_op_fcvt_q_l = 223, 255 rv_op_fcvt_q_lu = 224, 256 rv_op_fmv_x_q = 225, 257 rv_op_fmv_q_x = 226, 258 rv_op_c_addi4spn = 227, 259 rv_op_c_fld = 228, 260 rv_op_c_lw = 229, 261 rv_op_c_flw = 230, 262 rv_op_c_fsd = 231, 263 rv_op_c_sw = 232, 264 rv_op_c_fsw = 233, 265 rv_op_c_nop = 234, 266 rv_op_c_addi = 235, 267 rv_op_c_jal = 236, 268 rv_op_c_li = 237, 269 rv_op_c_addi16sp = 238, 270 rv_op_c_lui = 239, 271 rv_op_c_srli = 240, 272 rv_op_c_srai = 241, 273 rv_op_c_andi = 242, 274 rv_op_c_sub = 243, 275 rv_op_c_xor = 244, 276 rv_op_c_or = 245, 277 rv_op_c_and = 246, 278 rv_op_c_subw = 247, 279 rv_op_c_addw = 248, 280 rv_op_c_j = 249, 281 rv_op_c_beqz = 250, 282 rv_op_c_bnez = 251, 283 rv_op_c_slli = 252, 284 rv_op_c_fldsp = 253, 285 rv_op_c_lwsp = 254, 286 rv_op_c_flwsp = 255, 287 rv_op_c_jr = 256, 288 rv_op_c_mv = 257, 289 rv_op_c_ebreak = 258, 290 rv_op_c_jalr = 259, 291 rv_op_c_add = 260, 292 rv_op_c_fsdsp = 261, 293 rv_op_c_swsp = 262, 294 rv_op_c_fswsp = 263, 295 rv_op_c_ld = 264, 296 rv_op_c_sd = 265, 297 rv_op_c_addiw = 266, 298 rv_op_c_ldsp = 267, 299 rv_op_c_sdsp = 268, 300 rv_op_c_lq = 269, 301 rv_op_c_sq = 270, 302 rv_op_c_lqsp = 271, 303 rv_op_c_sqsp = 272, 304 rv_op_nop = 273, 305 rv_op_mv = 274, 306 rv_op_not = 275, 307 rv_op_neg = 276, 308 rv_op_negw = 277, 309 rv_op_sext_w = 278, 310 rv_op_seqz = 279, 311 rv_op_snez = 280, 312 rv_op_sltz = 281, 313 rv_op_sgtz = 282, 314 rv_op_fmv_s = 283, 315 rv_op_fabs_s = 284, 316 rv_op_fneg_s = 285, 317 rv_op_fmv_d = 286, 318 rv_op_fabs_d = 287, 319 rv_op_fneg_d = 288, 320 rv_op_fmv_q = 289, 321 rv_op_fabs_q = 290, 322 rv_op_fneg_q = 291, 323 rv_op_beqz = 292, 324 rv_op_bnez = 293, 325 rv_op_blez = 294, 326 rv_op_bgez = 295, 327 rv_op_bltz = 296, 328 rv_op_bgtz = 297, 329 rv_op_ble = 298, 330 rv_op_bleu = 299, 331 rv_op_bgt = 300, 332 rv_op_bgtu = 301, 333 rv_op_j = 302, 334 rv_op_ret = 303, 335 rv_op_jr = 304, 336 rv_op_rdcycle = 305, 337 rv_op_rdtime = 306, 338 rv_op_rdinstret = 307, 339 rv_op_rdcycleh = 308, 340 rv_op_rdtimeh = 309, 341 rv_op_rdinstreth = 310, 342 rv_op_frcsr = 311, 343 rv_op_frrm = 312, 344 rv_op_frflags = 313, 345 rv_op_fscsr = 314, 346 rv_op_fsrm = 315, 347 rv_op_fsflags = 316, 348 rv_op_fsrmi = 317, 349 rv_op_fsflagsi = 318, 350 rv_op_bseti = 319, 351 rv_op_bclri = 320, 352 rv_op_binvi = 321, 353 rv_op_bexti = 322, 354 rv_op_rori = 323, 355 rv_op_clz = 324, 356 rv_op_ctz = 325, 357 rv_op_cpop = 326, 358 rv_op_sext_h = 327, 359 rv_op_sext_b = 328, 360 rv_op_xnor = 329, 361 rv_op_orn = 330, 362 rv_op_andn = 331, 363 rv_op_rol = 332, 364 rv_op_ror = 333, 365 rv_op_sh1add = 334, 366 rv_op_sh2add = 335, 367 rv_op_sh3add = 336, 368 rv_op_sh1add_uw = 337, 369 rv_op_sh2add_uw = 338, 370 rv_op_sh3add_uw = 339, 371 rv_op_clmul = 340, 372 rv_op_clmulr = 341, 373 rv_op_clmulh = 342, 374 rv_op_min = 343, 375 rv_op_minu = 344, 376 rv_op_max = 345, 377 rv_op_maxu = 346, 378 rv_op_clzw = 347, 379 rv_op_ctzw = 348, 380 rv_op_cpopw = 349, 381 rv_op_slli_uw = 350, 382 rv_op_add_uw = 351, 383 rv_op_rolw = 352, 384 rv_op_rorw = 353, 385 rv_op_rev8 = 354, 386 rv_op_zext_h = 355, 387 rv_op_roriw = 356, 388 rv_op_orc_b = 357, 389 rv_op_bset = 358, 390 rv_op_bclr = 359, 391 rv_op_binv = 360, 392 rv_op_bext = 361, 393 rv_op_aes32esmi = 362, 394 rv_op_aes32esi = 363, 395 rv_op_aes32dsmi = 364, 396 rv_op_aes32dsi = 365, 397 rv_op_aes64ks1i = 366, 398 rv_op_aes64ks2 = 367, 399 rv_op_aes64im = 368, 400 rv_op_aes64esm = 369, 401 rv_op_aes64es = 370, 402 rv_op_aes64dsm = 371, 403 rv_op_aes64ds = 372, 404 rv_op_sha256sig0 = 373, 405 rv_op_sha256sig1 = 374, 406 rv_op_sha256sum0 = 375, 407 rv_op_sha256sum1 = 376, 408 rv_op_sha512sig0 = 377, 409 rv_op_sha512sig1 = 378, 410 rv_op_sha512sum0 = 379, 411 rv_op_sha512sum1 = 380, 412 rv_op_sha512sum0r = 381, 413 rv_op_sha512sum1r = 382, 414 rv_op_sha512sig0l = 383, 415 rv_op_sha512sig0h = 384, 416 rv_op_sha512sig1l = 385, 417 rv_op_sha512sig1h = 386, 418 rv_op_sm3p0 = 387, 419 rv_op_sm3p1 = 388, 420 rv_op_sm4ed = 389, 421 rv_op_sm4ks = 390, 422 rv_op_brev8 = 391, 423 rv_op_pack = 392, 424 rv_op_packh = 393, 425 rv_op_packw = 394, 426 rv_op_unzip = 395, 427 rv_op_zip = 396, 428 rv_op_xperm4 = 397, 429 rv_op_xperm8 = 398, 430 rv_op_vle8_v = 399, 431 rv_op_vle16_v = 400, 432 rv_op_vle32_v = 401, 433 rv_op_vle64_v = 402, 434 rv_op_vse8_v = 403, 435 rv_op_vse16_v = 404, 436 rv_op_vse32_v = 405, 437 rv_op_vse64_v = 406, 438 rv_op_vlm_v = 407, 439 rv_op_vsm_v = 408, 440 rv_op_vlse8_v = 409, 441 rv_op_vlse16_v = 410, 442 rv_op_vlse32_v = 411, 443 rv_op_vlse64_v = 412, 444 rv_op_vsse8_v = 413, 445 rv_op_vsse16_v = 414, 446 rv_op_vsse32_v = 415, 447 rv_op_vsse64_v = 416, 448 rv_op_vluxei8_v = 417, 449 rv_op_vluxei16_v = 418, 450 rv_op_vluxei32_v = 419, 451 rv_op_vluxei64_v = 420, 452 rv_op_vloxei8_v = 421, 453 rv_op_vloxei16_v = 422, 454 rv_op_vloxei32_v = 423, 455 rv_op_vloxei64_v = 424, 456 rv_op_vsuxei8_v = 425, 457 rv_op_vsuxei16_v = 426, 458 rv_op_vsuxei32_v = 427, 459 rv_op_vsuxei64_v = 428, 460 rv_op_vsoxei8_v = 429, 461 rv_op_vsoxei16_v = 430, 462 rv_op_vsoxei32_v = 431, 463 rv_op_vsoxei64_v = 432, 464 rv_op_vle8ff_v = 433, 465 rv_op_vle16ff_v = 434, 466 rv_op_vle32ff_v = 435, 467 rv_op_vle64ff_v = 436, 468 rv_op_vl1re8_v = 437, 469 rv_op_vl1re16_v = 438, 470 rv_op_vl1re32_v = 439, 471 rv_op_vl1re64_v = 440, 472 rv_op_vl2re8_v = 441, 473 rv_op_vl2re16_v = 442, 474 rv_op_vl2re32_v = 443, 475 rv_op_vl2re64_v = 444, 476 rv_op_vl4re8_v = 445, 477 rv_op_vl4re16_v = 446, 478 rv_op_vl4re32_v = 447, 479 rv_op_vl4re64_v = 448, 480 rv_op_vl8re8_v = 449, 481 rv_op_vl8re16_v = 450, 482 rv_op_vl8re32_v = 451, 483 rv_op_vl8re64_v = 452, 484 rv_op_vs1r_v = 453, 485 rv_op_vs2r_v = 454, 486 rv_op_vs4r_v = 455, 487 rv_op_vs8r_v = 456, 488 rv_op_vadd_vv = 457, 489 rv_op_vadd_vx = 458, 490 rv_op_vadd_vi = 459, 491 rv_op_vsub_vv = 460, 492 rv_op_vsub_vx = 461, 493 rv_op_vrsub_vx = 462, 494 rv_op_vrsub_vi = 463, 495 rv_op_vwaddu_vv = 464, 496 rv_op_vwaddu_vx = 465, 497 rv_op_vwadd_vv = 466, 498 rv_op_vwadd_vx = 467, 499 rv_op_vwsubu_vv = 468, 500 rv_op_vwsubu_vx = 469, 501 rv_op_vwsub_vv = 470, 502 rv_op_vwsub_vx = 471, 503 rv_op_vwaddu_wv = 472, 504 rv_op_vwaddu_wx = 473, 505 rv_op_vwadd_wv = 474, 506 rv_op_vwadd_wx = 475, 507 rv_op_vwsubu_wv = 476, 508 rv_op_vwsubu_wx = 477, 509 rv_op_vwsub_wv = 478, 510 rv_op_vwsub_wx = 479, 511 rv_op_vadc_vvm = 480, 512 rv_op_vadc_vxm = 481, 513 rv_op_vadc_vim = 482, 514 rv_op_vmadc_vvm = 483, 515 rv_op_vmadc_vxm = 484, 516 rv_op_vmadc_vim = 485, 517 rv_op_vsbc_vvm = 486, 518 rv_op_vsbc_vxm = 487, 519 rv_op_vmsbc_vvm = 488, 520 rv_op_vmsbc_vxm = 489, 521 rv_op_vand_vv = 490, 522 rv_op_vand_vx = 491, 523 rv_op_vand_vi = 492, 524 rv_op_vor_vv = 493, 525 rv_op_vor_vx = 494, 526 rv_op_vor_vi = 495, 527 rv_op_vxor_vv = 496, 528 rv_op_vxor_vx = 497, 529 rv_op_vxor_vi = 498, 530 rv_op_vsll_vv = 499, 531 rv_op_vsll_vx = 500, 532 rv_op_vsll_vi = 501, 533 rv_op_vsrl_vv = 502, 534 rv_op_vsrl_vx = 503, 535 rv_op_vsrl_vi = 504, 536 rv_op_vsra_vv = 505, 537 rv_op_vsra_vx = 506, 538 rv_op_vsra_vi = 507, 539 rv_op_vnsrl_wv = 508, 540 rv_op_vnsrl_wx = 509, 541 rv_op_vnsrl_wi = 510, 542 rv_op_vnsra_wv = 511, 543 rv_op_vnsra_wx = 512, 544 rv_op_vnsra_wi = 513, 545 rv_op_vmseq_vv = 514, 546 rv_op_vmseq_vx = 515, 547 rv_op_vmseq_vi = 516, 548 rv_op_vmsne_vv = 517, 549 rv_op_vmsne_vx = 518, 550 rv_op_vmsne_vi = 519, 551 rv_op_vmsltu_vv = 520, 552 rv_op_vmsltu_vx = 521, 553 rv_op_vmslt_vv = 522, 554 rv_op_vmslt_vx = 523, 555 rv_op_vmsleu_vv = 524, 556 rv_op_vmsleu_vx = 525, 557 rv_op_vmsleu_vi = 526, 558 rv_op_vmsle_vv = 527, 559 rv_op_vmsle_vx = 528, 560 rv_op_vmsle_vi = 529, 561 rv_op_vmsgtu_vx = 530, 562 rv_op_vmsgtu_vi = 531, 563 rv_op_vmsgt_vx = 532, 564 rv_op_vmsgt_vi = 533, 565 rv_op_vminu_vv = 534, 566 rv_op_vminu_vx = 535, 567 rv_op_vmin_vv = 536, 568 rv_op_vmin_vx = 537, 569 rv_op_vmaxu_vv = 538, 570 rv_op_vmaxu_vx = 539, 571 rv_op_vmax_vv = 540, 572 rv_op_vmax_vx = 541, 573 rv_op_vmul_vv = 542, 574 rv_op_vmul_vx = 543, 575 rv_op_vmulh_vv = 544, 576 rv_op_vmulh_vx = 545, 577 rv_op_vmulhu_vv = 546, 578 rv_op_vmulhu_vx = 547, 579 rv_op_vmulhsu_vv = 548, 580 rv_op_vmulhsu_vx = 549, 581 rv_op_vdivu_vv = 550, 582 rv_op_vdivu_vx = 551, 583 rv_op_vdiv_vv = 552, 584 rv_op_vdiv_vx = 553, 585 rv_op_vremu_vv = 554, 586 rv_op_vremu_vx = 555, 587 rv_op_vrem_vv = 556, 588 rv_op_vrem_vx = 557, 589 rv_op_vwmulu_vv = 558, 590 rv_op_vwmulu_vx = 559, 591 rv_op_vwmulsu_vv = 560, 592 rv_op_vwmulsu_vx = 561, 593 rv_op_vwmul_vv = 562, 594 rv_op_vwmul_vx = 563, 595 rv_op_vmacc_vv = 564, 596 rv_op_vmacc_vx = 565, 597 rv_op_vnmsac_vv = 566, 598 rv_op_vnmsac_vx = 567, 599 rv_op_vmadd_vv = 568, 600 rv_op_vmadd_vx = 569, 601 rv_op_vnmsub_vv = 570, 602 rv_op_vnmsub_vx = 571, 603 rv_op_vwmaccu_vv = 572, 604 rv_op_vwmaccu_vx = 573, 605 rv_op_vwmacc_vv = 574, 606 rv_op_vwmacc_vx = 575, 607 rv_op_vwmaccsu_vv = 576, 608 rv_op_vwmaccsu_vx = 577, 609 rv_op_vwmaccus_vx = 578, 610 rv_op_vmv_v_v = 579, 611 rv_op_vmv_v_x = 580, 612 rv_op_vmv_v_i = 581, 613 rv_op_vmerge_vvm = 582, 614 rv_op_vmerge_vxm = 583, 615 rv_op_vmerge_vim = 584, 616 rv_op_vsaddu_vv = 585, 617 rv_op_vsaddu_vx = 586, 618 rv_op_vsaddu_vi = 587, 619 rv_op_vsadd_vv = 588, 620 rv_op_vsadd_vx = 589, 621 rv_op_vsadd_vi = 590, 622 rv_op_vssubu_vv = 591, 623 rv_op_vssubu_vx = 592, 624 rv_op_vssub_vv = 593, 625 rv_op_vssub_vx = 594, 626 rv_op_vaadd_vv = 595, 627 rv_op_vaadd_vx = 596, 628 rv_op_vaaddu_vv = 597, 629 rv_op_vaaddu_vx = 598, 630 rv_op_vasub_vv = 599, 631 rv_op_vasub_vx = 600, 632 rv_op_vasubu_vv = 601, 633 rv_op_vasubu_vx = 602, 634 rv_op_vsmul_vv = 603, 635 rv_op_vsmul_vx = 604, 636 rv_op_vssrl_vv = 605, 637 rv_op_vssrl_vx = 606, 638 rv_op_vssrl_vi = 607, 639 rv_op_vssra_vv = 608, 640 rv_op_vssra_vx = 609, 641 rv_op_vssra_vi = 610, 642 rv_op_vnclipu_wv = 611, 643 rv_op_vnclipu_wx = 612, 644 rv_op_vnclipu_wi = 613, 645 rv_op_vnclip_wv = 614, 646 rv_op_vnclip_wx = 615, 647 rv_op_vnclip_wi = 616, 648 rv_op_vfadd_vv = 617, 649 rv_op_vfadd_vf = 618, 650 rv_op_vfsub_vv = 619, 651 rv_op_vfsub_vf = 620, 652 rv_op_vfrsub_vf = 621, 653 rv_op_vfwadd_vv = 622, 654 rv_op_vfwadd_vf = 623, 655 rv_op_vfwadd_wv = 624, 656 rv_op_vfwadd_wf = 625, 657 rv_op_vfwsub_vv = 626, 658 rv_op_vfwsub_vf = 627, 659 rv_op_vfwsub_wv = 628, 660 rv_op_vfwsub_wf = 629, 661 rv_op_vfmul_vv = 630, 662 rv_op_vfmul_vf = 631, 663 rv_op_vfdiv_vv = 632, 664 rv_op_vfdiv_vf = 633, 665 rv_op_vfrdiv_vf = 634, 666 rv_op_vfwmul_vv = 635, 667 rv_op_vfwmul_vf = 636, 668 rv_op_vfmacc_vv = 637, 669 rv_op_vfmacc_vf = 638, 670 rv_op_vfnmacc_vv = 639, 671 rv_op_vfnmacc_vf = 640, 672 rv_op_vfmsac_vv = 641, 673 rv_op_vfmsac_vf = 642, 674 rv_op_vfnmsac_vv = 643, 675 rv_op_vfnmsac_vf = 644, 676 rv_op_vfmadd_vv = 645, 677 rv_op_vfmadd_vf = 646, 678 rv_op_vfnmadd_vv = 647, 679 rv_op_vfnmadd_vf = 648, 680 rv_op_vfmsub_vv = 649, 681 rv_op_vfmsub_vf = 650, 682 rv_op_vfnmsub_vv = 651, 683 rv_op_vfnmsub_vf = 652, 684 rv_op_vfwmacc_vv = 653, 685 rv_op_vfwmacc_vf = 654, 686 rv_op_vfwnmacc_vv = 655, 687 rv_op_vfwnmacc_vf = 656, 688 rv_op_vfwmsac_vv = 657, 689 rv_op_vfwmsac_vf = 658, 690 rv_op_vfwnmsac_vv = 659, 691 rv_op_vfwnmsac_vf = 660, 692 rv_op_vfsqrt_v = 661, 693 rv_op_vfrsqrt7_v = 662, 694 rv_op_vfrec7_v = 663, 695 rv_op_vfmin_vv = 664, 696 rv_op_vfmin_vf = 665, 697 rv_op_vfmax_vv = 666, 698 rv_op_vfmax_vf = 667, 699 rv_op_vfsgnj_vv = 668, 700 rv_op_vfsgnj_vf = 669, 701 rv_op_vfsgnjn_vv = 670, 702 rv_op_vfsgnjn_vf = 671, 703 rv_op_vfsgnjx_vv = 672, 704 rv_op_vfsgnjx_vf = 673, 705 rv_op_vfslide1up_vf = 674, 706 rv_op_vfslide1down_vf = 675, 707 rv_op_vmfeq_vv = 676, 708 rv_op_vmfeq_vf = 677, 709 rv_op_vmfne_vv = 678, 710 rv_op_vmfne_vf = 679, 711 rv_op_vmflt_vv = 680, 712 rv_op_vmflt_vf = 681, 713 rv_op_vmfle_vv = 682, 714 rv_op_vmfle_vf = 683, 715 rv_op_vmfgt_vf = 684, 716 rv_op_vmfge_vf = 685, 717 rv_op_vfclass_v = 686, 718 rv_op_vfmerge_vfm = 687, 719 rv_op_vfmv_v_f = 688, 720 rv_op_vfcvt_xu_f_v = 689, 721 rv_op_vfcvt_x_f_v = 690, 722 rv_op_vfcvt_f_xu_v = 691, 723 rv_op_vfcvt_f_x_v = 692, 724 rv_op_vfcvt_rtz_xu_f_v = 693, 725 rv_op_vfcvt_rtz_x_f_v = 694, 726 rv_op_vfwcvt_xu_f_v = 695, 727 rv_op_vfwcvt_x_f_v = 696, 728 rv_op_vfwcvt_f_xu_v = 697, 729 rv_op_vfwcvt_f_x_v = 698, 730 rv_op_vfwcvt_f_f_v = 699, 731 rv_op_vfwcvt_rtz_xu_f_v = 700, 732 rv_op_vfwcvt_rtz_x_f_v = 701, 733 rv_op_vfncvt_xu_f_w = 702, 734 rv_op_vfncvt_x_f_w = 703, 735 rv_op_vfncvt_f_xu_w = 704, 736 rv_op_vfncvt_f_x_w = 705, 737 rv_op_vfncvt_f_f_w = 706, 738 rv_op_vfncvt_rod_f_f_w = 707, 739 rv_op_vfncvt_rtz_xu_f_w = 708, 740 rv_op_vfncvt_rtz_x_f_w = 709, 741 rv_op_vredsum_vs = 710, 742 rv_op_vredand_vs = 711, 743 rv_op_vredor_vs = 712, 744 rv_op_vredxor_vs = 713, 745 rv_op_vredminu_vs = 714, 746 rv_op_vredmin_vs = 715, 747 rv_op_vredmaxu_vs = 716, 748 rv_op_vredmax_vs = 717, 749 rv_op_vwredsumu_vs = 718, 750 rv_op_vwredsum_vs = 719, 751 rv_op_vfredusum_vs = 720, 752 rv_op_vfredosum_vs = 721, 753 rv_op_vfredmin_vs = 722, 754 rv_op_vfredmax_vs = 723, 755 rv_op_vfwredusum_vs = 724, 756 rv_op_vfwredosum_vs = 725, 757 rv_op_vmand_mm = 726, 758 rv_op_vmnand_mm = 727, 759 rv_op_vmandn_mm = 728, 760 rv_op_vmxor_mm = 729, 761 rv_op_vmor_mm = 730, 762 rv_op_vmnor_mm = 731, 763 rv_op_vmorn_mm = 732, 764 rv_op_vmxnor_mm = 733, 765 rv_op_vcpop_m = 734, 766 rv_op_vfirst_m = 735, 767 rv_op_vmsbf_m = 736, 768 rv_op_vmsif_m = 737, 769 rv_op_vmsof_m = 738, 770 rv_op_viota_m = 739, 771 rv_op_vid_v = 740, 772 rv_op_vmv_x_s = 741, 773 rv_op_vmv_s_x = 742, 774 rv_op_vfmv_f_s = 743, 775 rv_op_vfmv_s_f = 744, 776 rv_op_vslideup_vx = 745, 777 rv_op_vslideup_vi = 746, 778 rv_op_vslide1up_vx = 747, 779 rv_op_vslidedown_vx = 748, 780 rv_op_vslidedown_vi = 749, 781 rv_op_vslide1down_vx = 750, 782 rv_op_vrgather_vv = 751, 783 rv_op_vrgatherei16_vv = 752, 784 rv_op_vrgather_vx = 753, 785 rv_op_vrgather_vi = 754, 786 rv_op_vcompress_vm = 755, 787 rv_op_vmv1r_v = 756, 788 rv_op_vmv2r_v = 757, 789 rv_op_vmv4r_v = 758, 790 rv_op_vmv8r_v = 759, 791 rv_op_vzext_vf2 = 760, 792 rv_op_vzext_vf4 = 761, 793 rv_op_vzext_vf8 = 762, 794 rv_op_vsext_vf2 = 763, 795 rv_op_vsext_vf4 = 764, 796 rv_op_vsext_vf8 = 765, 797 rv_op_vsetvli = 766, 798 rv_op_vsetivli = 767, 799 rv_op_vsetvl = 768, 800 rv_op_c_zext_b = 769, 801 rv_op_c_sext_b = 770, 802 rv_op_c_zext_h = 771, 803 rv_op_c_sext_h = 772, 804 rv_op_c_zext_w = 773, 805 rv_op_c_not = 774, 806 rv_op_c_mul = 775, 807 rv_op_c_lbu = 776, 808 rv_op_c_lhu = 777, 809 rv_op_c_lh = 778, 810 rv_op_c_sb = 779, 811 rv_op_c_sh = 780, 812 rv_op_cm_push = 781, 813 rv_op_cm_pop = 782, 814 rv_op_cm_popret = 783, 815 rv_op_cm_popretz = 784, 816 rv_op_cm_mva01s = 785, 817 rv_op_cm_mvsa01 = 786, 818 rv_op_cm_jt = 787, 819 rv_op_cm_jalt = 788, 820 rv_op_czero_eqz = 789, 821 rv_op_czero_nez = 790, 822 rv_op_fcvt_bf16_s = 791, 823 rv_op_fcvt_s_bf16 = 792, 824 rv_op_vfncvtbf16_f_f_w = 793, 825 rv_op_vfwcvtbf16_f_f_v = 794, 826 rv_op_vfwmaccbf16_vv = 795, 827 rv_op_vfwmaccbf16_vf = 796, 828 rv_op_flh = 797, 829 rv_op_fsh = 798, 830 rv_op_fmv_h_x = 799, 831 rv_op_fmv_x_h = 800, 832 rv_op_fli_s = 801, 833 rv_op_fli_d = 802, 834 rv_op_fli_q = 803, 835 rv_op_fli_h = 804, 836 rv_op_fminm_s = 805, 837 rv_op_fmaxm_s = 806, 838 rv_op_fminm_d = 807, 839 rv_op_fmaxm_d = 808, 840 rv_op_fminm_q = 809, 841 rv_op_fmaxm_q = 810, 842 rv_op_fminm_h = 811, 843 rv_op_fmaxm_h = 812, 844 rv_op_fround_s = 813, 845 rv_op_froundnx_s = 814, 846 rv_op_fround_d = 815, 847 rv_op_froundnx_d = 816, 848 rv_op_fround_q = 817, 849 rv_op_froundnx_q = 818, 850 rv_op_fround_h = 819, 851 rv_op_froundnx_h = 820, 852 rv_op_fcvtmod_w_d = 821, 853 rv_op_fmvh_x_d = 822, 854 rv_op_fmvp_d_x = 823, 855 rv_op_fmvh_x_q = 824, 856 rv_op_fmvp_q_x = 825, 857 rv_op_fleq_s = 826, 858 rv_op_fltq_s = 827, 859 rv_op_fleq_d = 828, 860 rv_op_fltq_d = 829, 861 rv_op_fleq_q = 830, 862 rv_op_fltq_q = 831, 863 rv_op_fleq_h = 832, 864 rv_op_fltq_h = 833, 865 rv_op_vaesdf_vv = 834, 866 rv_op_vaesdf_vs = 835, 867 rv_op_vaesdm_vv = 836, 868 rv_op_vaesdm_vs = 837, 869 rv_op_vaesef_vv = 838, 870 rv_op_vaesef_vs = 839, 871 rv_op_vaesem_vv = 840, 872 rv_op_vaesem_vs = 841, 873 rv_op_vaeskf1_vi = 842, 874 rv_op_vaeskf2_vi = 843, 875 rv_op_vaesz_vs = 844, 876 rv_op_vandn_vv = 845, 877 rv_op_vandn_vx = 846, 878 rv_op_vbrev_v = 847, 879 rv_op_vbrev8_v = 848, 880 rv_op_vclmul_vv = 849, 881 rv_op_vclmul_vx = 850, 882 rv_op_vclmulh_vv = 851, 883 rv_op_vclmulh_vx = 852, 884 rv_op_vclz_v = 853, 885 rv_op_vcpop_v = 854, 886 rv_op_vctz_v = 855, 887 rv_op_vghsh_vv = 856, 888 rv_op_vgmul_vv = 857, 889 rv_op_vrev8_v = 858, 890 rv_op_vrol_vv = 859, 891 rv_op_vrol_vx = 860, 892 rv_op_vror_vv = 861, 893 rv_op_vror_vx = 862, 894 rv_op_vror_vi = 863, 895 rv_op_vsha2ch_vv = 864, 896 rv_op_vsha2cl_vv = 865, 897 rv_op_vsha2ms_vv = 866, 898 rv_op_vsm3c_vi = 867, 899 rv_op_vsm3me_vv = 868, 900 rv_op_vsm4k_vi = 869, 901 rv_op_vsm4r_vv = 870, 902 rv_op_vsm4r_vs = 871, 903 rv_op_vwsll_vv = 872, 904 rv_op_vwsll_vx = 873, 905 rv_op_vwsll_vi = 874, 906 rv_op_amocas_w = 875, 907 rv_op_amocas_d = 876, 908 rv_op_amocas_q = 877, 909 rv_mop_r_0 = 878, 910 rv_mop_r_1 = 879, 911 rv_mop_r_2 = 880, 912 rv_mop_r_3 = 881, 913 rv_mop_r_4 = 882, 914 rv_mop_r_5 = 883, 915 rv_mop_r_6 = 884, 916 rv_mop_r_7 = 885, 917 rv_mop_r_8 = 886, 918 rv_mop_r_9 = 887, 919 rv_mop_r_10 = 888, 920 rv_mop_r_11 = 889, 921 rv_mop_r_12 = 890, 922 rv_mop_r_13 = 891, 923 rv_mop_r_14 = 892, 924 rv_mop_r_15 = 893, 925 rv_mop_r_16 = 894, 926 rv_mop_r_17 = 895, 927 rv_mop_r_18 = 896, 928 rv_mop_r_19 = 897, 929 rv_mop_r_20 = 898, 930 rv_mop_r_21 = 899, 931 rv_mop_r_22 = 900, 932 rv_mop_r_23 = 901, 933 rv_mop_r_24 = 902, 934 rv_mop_r_25 = 903, 935 rv_mop_r_26 = 904, 936 rv_mop_r_27 = 905, 937 rv_mop_r_28 = 906, 938 rv_mop_r_29 = 907, 939 rv_mop_r_30 = 908, 940 rv_mop_r_31 = 909, 941 rv_mop_rr_0 = 910, 942 rv_mop_rr_1 = 911, 943 rv_mop_rr_2 = 912, 944 rv_mop_rr_3 = 913, 945 rv_mop_rr_4 = 914, 946 rv_mop_rr_5 = 915, 947 rv_mop_rr_6 = 916, 948 rv_mop_rr_7 = 917, 949 rv_c_mop_1 = 918, 950 rv_c_mop_3 = 919, 951 rv_c_mop_5 = 920, 952 rv_c_mop_7 = 921, 953 rv_c_mop_9 = 922, 954 rv_c_mop_11 = 923, 955 rv_c_mop_13 = 924, 956 rv_c_mop_15 = 925, 957 rv_op_amoswap_b = 926, 958 rv_op_amoadd_b = 927, 959 rv_op_amoxor_b = 928, 960 rv_op_amoor_b = 929, 961 rv_op_amoand_b = 930, 962 rv_op_amomin_b = 931, 963 rv_op_amomax_b = 932, 964 rv_op_amominu_b = 933, 965 rv_op_amomaxu_b = 934, 966 rv_op_amoswap_h = 935, 967 rv_op_amoadd_h = 936, 968 rv_op_amoxor_h = 937, 969 rv_op_amoor_h = 938, 970 rv_op_amoand_h = 939, 971 rv_op_amomin_h = 940, 972 rv_op_amomax_h = 941, 973 rv_op_amominu_h = 942, 974 rv_op_amomaxu_h = 943, 975 rv_op_amocas_b = 944, 976 rv_op_amocas_h = 945, 977 rv_op_wrs_sto = 946, 978 rv_op_wrs_nto = 947, 979 rv_op_lpad = 948, 980 rv_op_sspush = 949, 981 rv_op_sspopchk = 950, 982 rv_op_ssrdp = 951, 983 rv_op_ssamoswap_w = 952, 984 rv_op_ssamoswap_d = 953, 985 rv_op_c_sspush = 954, 986 rv_op_c_sspopchk = 955, 987 } rv_op; 988 989 /* register names */ 990 991 static const char rv_ireg_name_sym[32][5] = { 992 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 993 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 994 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 995 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", 996 }; 997 998 static const char rv_freg_name_sym[32][5] = { 999 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", 1000 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", 1001 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", 1002 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11", 1003 }; 1004 1005 static const char rv_vreg_name_sym[32][4] = { 1006 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1007 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1008 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1009 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 1010 }; 1011 1012 /* The FLI.[HSDQ] numeric constants (0.0 for symbolic constants). 1013 * The constants use the hex floating-point literal representation 1014 * that is printed when using the printf %a format specifier, 1015 * which matches the output that is generated by the disassembler. 1016 */ 1017 static const char rv_fli_name_const[32][9] = 1018 { 1019 "0x1p+0", "min", "0x1p-16", "0x1p-15", 1020 "0x1p-8", "0x1p-7", "0x1p-4", "0x1p-3", 1021 "0x1p-2", "0x1.4p-2", "0x1.8p-2", "0x1.cp-2", 1022 "0x1p-1", "0x1.4p-1", "0x1.8p-1", "0x1.cp-1", 1023 "0x1p+0", "0x1.4p+0", "0x1.8p+0", "0x1.cp+0", 1024 "0x1p+1", "0x1.4p+1", "0x1.8p+1", "0x1p+2", 1025 "0x1p+3", "0x1p+4", "0x1p+7", "0x1p+8", 1026 "0x1p+15", "0x1p+16", "inf", "nan" 1027 }; 1028 1029 /* pseudo-instruction constraints */ 1030 1031 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end }; 1032 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, 1033 rvc_end }; 1034 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, 1035 rvc_imm_eq_zero, rvc_end }; 1036 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; 1037 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end }; 1038 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end }; 1039 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end }; 1040 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end }; 1041 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end }; 1042 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end }; 1043 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end }; 1044 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end }; 1045 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1046 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1047 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1048 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1049 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1050 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1051 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1052 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1053 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1054 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end }; 1055 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end }; 1056 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end }; 1057 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end }; 1058 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end }; 1059 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end }; 1060 static const rvc_constraint rvcc_ble[] = { rvc_end }; 1061 static const rvc_constraint rvcc_bleu[] = { rvc_end }; 1062 static const rvc_constraint rvcc_bgt[] = { rvc_end }; 1063 static const rvc_constraint rvcc_bgtu[] = { rvc_end }; 1064 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end }; 1065 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, 1066 rvc_end }; 1067 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, 1068 rvc_end }; 1069 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, 1070 rvc_end }; 1071 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, 1072 rvc_end }; 1073 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, 1074 rvc_csr_eq_0xc02, rvc_end }; 1075 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, 1076 rvc_csr_eq_0xc80, rvc_end }; 1077 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, 1078 rvc_end }; 1079 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, 1080 rvc_csr_eq_0xc82, rvc_end }; 1081 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, 1082 rvc_end }; 1083 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, 1084 rvc_end }; 1085 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, 1086 rvc_end }; 1087 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end }; 1088 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end }; 1089 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end }; 1090 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end }; 1091 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end }; 1092 1093 /* pseudo-instruction metadata */ 1094 1095 static const rv_comp_data rvcp_jal[] = { 1096 { rv_op_j, rvcc_j }, 1097 { rv_op_jal, rvcc_jal }, 1098 { rv_op_illegal, NULL } 1099 }; 1100 1101 static const rv_comp_data rvcp_jalr[] = { 1102 { rv_op_ret, rvcc_ret }, 1103 { rv_op_jr, rvcc_jr }, 1104 { rv_op_jalr, rvcc_jalr }, 1105 { rv_op_illegal, NULL } 1106 }; 1107 1108 static const rv_comp_data rvcp_beq[] = { 1109 { rv_op_beqz, rvcc_beqz }, 1110 { rv_op_illegal, NULL } 1111 }; 1112 1113 static const rv_comp_data rvcp_bne[] = { 1114 { rv_op_bnez, rvcc_bnez }, 1115 { rv_op_illegal, NULL } 1116 }; 1117 1118 static const rv_comp_data rvcp_blt[] = { 1119 { rv_op_bltz, rvcc_bltz }, 1120 { rv_op_bgtz, rvcc_bgtz }, 1121 { rv_op_bgt, rvcc_bgt }, 1122 { rv_op_illegal, NULL } 1123 }; 1124 1125 static const rv_comp_data rvcp_bge[] = { 1126 { rv_op_blez, rvcc_blez }, 1127 { rv_op_bgez, rvcc_bgez }, 1128 { rv_op_ble, rvcc_ble }, 1129 { rv_op_illegal, NULL } 1130 }; 1131 1132 static const rv_comp_data rvcp_bltu[] = { 1133 { rv_op_bgtu, rvcc_bgtu }, 1134 { rv_op_illegal, NULL } 1135 }; 1136 1137 static const rv_comp_data rvcp_bgeu[] = { 1138 { rv_op_bleu, rvcc_bleu }, 1139 { rv_op_illegal, NULL } 1140 }; 1141 1142 static const rv_comp_data rvcp_addi[] = { 1143 { rv_op_nop, rvcc_nop }, 1144 { rv_op_mv, rvcc_mv }, 1145 { rv_op_illegal, NULL } 1146 }; 1147 1148 static const rv_comp_data rvcp_sltiu[] = { 1149 { rv_op_seqz, rvcc_seqz }, 1150 { rv_op_illegal, NULL } 1151 }; 1152 1153 static const rv_comp_data rvcp_xori[] = { 1154 { rv_op_not, rvcc_not }, 1155 { rv_op_illegal, NULL } 1156 }; 1157 1158 static const rv_comp_data rvcp_sub[] = { 1159 { rv_op_neg, rvcc_neg }, 1160 { rv_op_illegal, NULL } 1161 }; 1162 1163 static const rv_comp_data rvcp_slt[] = { 1164 { rv_op_sltz, rvcc_sltz }, 1165 { rv_op_sgtz, rvcc_sgtz }, 1166 { rv_op_illegal, NULL } 1167 }; 1168 1169 static const rv_comp_data rvcp_sltu[] = { 1170 { rv_op_snez, rvcc_snez }, 1171 { rv_op_illegal, NULL } 1172 }; 1173 1174 static const rv_comp_data rvcp_addiw[] = { 1175 { rv_op_sext_w, rvcc_sext_w }, 1176 { rv_op_illegal, NULL } 1177 }; 1178 1179 static const rv_comp_data rvcp_subw[] = { 1180 { rv_op_negw, rvcc_negw }, 1181 { rv_op_illegal, NULL } 1182 }; 1183 1184 static const rv_comp_data rvcp_csrrw[] = { 1185 { rv_op_fscsr, rvcc_fscsr }, 1186 { rv_op_fsrm, rvcc_fsrm }, 1187 { rv_op_fsflags, rvcc_fsflags }, 1188 { rv_op_illegal, NULL } 1189 }; 1190 1191 1192 static const rv_comp_data rvcp_csrrs[] = { 1193 { rv_op_rdcycle, rvcc_rdcycle }, 1194 { rv_op_rdtime, rvcc_rdtime }, 1195 { rv_op_rdinstret, rvcc_rdinstret }, 1196 { rv_op_rdcycleh, rvcc_rdcycleh }, 1197 { rv_op_rdtimeh, rvcc_rdtimeh }, 1198 { rv_op_rdinstreth, rvcc_rdinstreth }, 1199 { rv_op_frcsr, rvcc_frcsr }, 1200 { rv_op_frrm, rvcc_frrm }, 1201 { rv_op_frflags, rvcc_frflags }, 1202 { rv_op_illegal, NULL } 1203 }; 1204 1205 static const rv_comp_data rvcp_csrrwi[] = { 1206 { rv_op_fsrmi, rvcc_fsrmi }, 1207 { rv_op_fsflagsi, rvcc_fsflagsi }, 1208 { rv_op_illegal, NULL } 1209 }; 1210 1211 static const rv_comp_data rvcp_fsgnj_s[] = { 1212 { rv_op_fmv_s, rvcc_fmv_s }, 1213 { rv_op_illegal, NULL } 1214 }; 1215 1216 static const rv_comp_data rvcp_fsgnjn_s[] = { 1217 { rv_op_fneg_s, rvcc_fneg_s }, 1218 { rv_op_illegal, NULL } 1219 }; 1220 1221 static const rv_comp_data rvcp_fsgnjx_s[] = { 1222 { rv_op_fabs_s, rvcc_fabs_s }, 1223 { rv_op_illegal, NULL } 1224 }; 1225 1226 static const rv_comp_data rvcp_fsgnj_d[] = { 1227 { rv_op_fmv_d, rvcc_fmv_d }, 1228 { rv_op_illegal, NULL } 1229 }; 1230 1231 static const rv_comp_data rvcp_fsgnjn_d[] = { 1232 { rv_op_fneg_d, rvcc_fneg_d }, 1233 { rv_op_illegal, NULL } 1234 }; 1235 1236 static const rv_comp_data rvcp_fsgnjx_d[] = { 1237 { rv_op_fabs_d, rvcc_fabs_d }, 1238 { rv_op_illegal, NULL } 1239 }; 1240 1241 static const rv_comp_data rvcp_fsgnj_q[] = { 1242 { rv_op_fmv_q, rvcc_fmv_q }, 1243 { rv_op_illegal, NULL } 1244 }; 1245 1246 static const rv_comp_data rvcp_fsgnjn_q[] = { 1247 { rv_op_fneg_q, rvcc_fneg_q }, 1248 { rv_op_illegal, NULL } 1249 }; 1250 1251 static const rv_comp_data rvcp_fsgnjx_q[] = { 1252 { rv_op_fabs_q, rvcc_fabs_q }, 1253 { rv_op_illegal, NULL } 1254 }; 1255 1256 /* instruction metadata */ 1257 1258 const rv_opcode_data rvi_opcode_data[] = { 1259 { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, 1260 { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 }, 1261 { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 }, 1262 { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 }, 1263 { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 }, 1264 { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 }, 1265 { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 }, 1266 { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 }, 1267 { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 }, 1268 { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 }, 1269 { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 }, 1270 { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1271 { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1272 { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1273 { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1274 { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1275 { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1276 { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1277 { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1278 { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 }, 1279 { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1280 { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 }, 1281 { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 }, 1282 { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1283 { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1284 { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1285 { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1286 { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1287 { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1288 { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 }, 1289 { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1290 { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 }, 1291 { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 }, 1292 { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1293 { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1294 { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1295 { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1296 { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1297 { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 }, 1298 { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1299 { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1300 { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1301 { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1302 { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 }, 1303 { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1304 { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1305 { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1306 { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1307 { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 }, 1308 { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1309 { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1310 { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1311 { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1312 { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1313 { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1314 { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1315 { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1316 { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1317 { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1318 { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1319 { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1320 { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1321 { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1322 { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1323 { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1324 { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1325 { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1326 { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1327 { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1328 { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1329 { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1330 { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1331 { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1332 { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1333 { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1334 { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1335 { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1336 { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1337 { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1338 { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1339 { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1340 { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1341 { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1342 { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1343 { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1344 { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1345 { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1346 { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1347 { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1348 { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1349 { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1350 { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1351 { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1352 { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1353 { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1354 { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1355 { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1356 { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1357 { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1358 { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1359 { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1360 { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1361 { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1362 { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1363 { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1364 { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1365 { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1366 { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1367 { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1368 { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1369 { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1370 { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1371 { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1372 { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1373 { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1374 { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1375 { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1376 { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1377 { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1378 { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1379 { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1380 { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1381 { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, 1382 { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 }, 1383 { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1384 { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 }, 1385 { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 }, 1386 { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 }, 1387 { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 }, 1388 { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1389 { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1390 { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1391 { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1392 { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1393 { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1394 { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1395 { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1396 { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1397 { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1398 { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1399 { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1400 { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 }, 1401 { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 }, 1402 { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 }, 1403 { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1404 { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1405 { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1406 { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1407 { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1408 { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1409 { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1410 { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1411 { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1412 { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1413 { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1414 { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1415 { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1416 { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1417 { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1418 { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1419 { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1420 { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1421 { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1422 { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1423 { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1424 { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1425 { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1426 { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1427 { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1428 { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1429 { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1430 { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 }, 1431 { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 }, 1432 { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 }, 1433 { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1434 { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1435 { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1436 { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1437 { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1438 { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1439 { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1440 { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1441 { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1442 { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1443 { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1444 { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1445 { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1446 { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1447 { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1448 { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1449 { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1450 { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1451 { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1452 { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1453 { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1454 { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1455 { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1456 { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1457 { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1458 { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1459 { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1460 { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1461 { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1462 { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 }, 1463 { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 }, 1464 { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 }, 1465 { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1466 { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1467 { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1468 { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1469 { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1470 { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1471 { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1472 { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1473 { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1474 { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1475 { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1476 { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1477 { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1478 { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1479 { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1480 { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1481 { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1482 { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1483 { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1484 { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1485 { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1486 { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1487 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1488 { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1489 rv_op_fld, 0 }, 1490 { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, 1491 rv_op_lw }, 1492 { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, 1493 { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1494 rv_op_fsd, 0 }, 1495 { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, 1496 rv_op_sw }, 1497 { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, 1498 { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, 1499 rv_op_addi }, 1500 { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1501 rv_op_addi, rvcd_imm_nz }, 1502 { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 }, 1503 { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1504 rv_op_addi }, 1505 { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1506 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1507 { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui, 1508 rv_op_lui, rvcd_imm_nz }, 1509 { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, 1510 rv_op_srli, rv_op_srli, rvcd_imm_nz }, 1511 { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, 1512 rv_op_srai, rv_op_srai, rvcd_imm_nz }, 1513 { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, 1514 rv_op_andi, rv_op_andi }, 1515 { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, 1516 rv_op_sub }, 1517 { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, 1518 rv_op_xor }, 1519 { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, 1520 rv_op_or }, 1521 { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, 1522 rv_op_and }, 1523 { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, 1524 rv_op_subw }, 1525 { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, 1526 rv_op_addw }, 1527 { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, 1528 rv_op_jal }, 1529 { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, 1530 rv_op_beq }, 1531 { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, 1532 rv_op_bne }, 1533 { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, 1534 rv_op_slli, rv_op_slli, rvcd_imm_nz }, 1535 { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, 1536 rv_op_fld, rv_op_fld }, 1537 { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, 1538 rv_op_lw, rv_op_lw }, 1539 { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 1540 0 }, 1541 { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1542 rv_op_jalr, rv_op_jalr }, 1543 { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, 1544 rv_op_addi }, 1545 { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, 1546 rv_op_ebreak, rv_op_ebreak }, 1547 { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, 1548 rv_op_jalr, rv_op_jalr }, 1549 { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, 1550 rv_op_add }, 1551 { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, 1552 rv_op_fsd, rv_op_fsd }, 1553 { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, 1554 rv_op_sw, rv_op_sw }, 1555 { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 1556 0 }, 1557 { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1558 rv_op_ld }, 1559 { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1560 rv_op_sd }, 1561 { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, 1562 rv_op_addiw }, 1563 { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, 1564 rv_op_ld }, 1565 { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, 1566 rv_op_sd }, 1567 { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1568 { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, 1569 { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1570 { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 1571 rv_op_sq }, 1572 { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1573 { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1574 { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1575 { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1576 { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1577 { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1578 { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1579 { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1580 { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1581 { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1582 { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1583 { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1584 { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1585 { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1586 { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1587 { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1588 { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1589 { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1590 { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1591 { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1592 { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1593 { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1594 { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1595 { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1596 { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1597 { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1598 { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1599 { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1600 { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1601 { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 }, 1602 { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1603 { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 }, 1604 { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1605 { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1606 { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1607 { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1608 { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1609 { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1610 { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1611 { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1612 { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1613 { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1614 { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1615 { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1616 { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1617 { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1618 { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1619 { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1620 { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1621 { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1622 { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1623 { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1624 { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1625 { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1626 { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1627 { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1628 { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1629 { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1630 { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1631 { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1632 { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1633 { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1634 { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1635 { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1636 { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1637 { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1638 { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1639 { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1640 { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1641 { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1642 { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1643 { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1644 { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1645 { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1646 { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1647 { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1648 { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1649 { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1650 { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1651 { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1652 { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1653 { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1654 { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1655 { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1656 { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1657 { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1658 { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1659 { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1660 { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1661 { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1662 { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1663 { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1664 { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1665 { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 }, 1666 { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1667 { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1668 { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1669 { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1670 { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1671 { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1672 { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1673 { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1674 { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1675 { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1676 { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1677 { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1678 { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1679 { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1680 { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1681 { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1682 { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1683 { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1684 { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1685 { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1686 { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1687 { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1688 { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1689 { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1690 { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1691 { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1692 { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1693 { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1694 { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1695 { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1696 { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1697 { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1698 { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1699 { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1700 { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1701 { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1702 { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1703 { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1704 { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1705 { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1706 { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1707 { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1708 { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1709 { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1710 { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1711 { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1712 { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1713 { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1714 { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1715 { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 }, 1716 { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1717 { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1718 { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1719 { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1720 { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1721 { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1722 { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1723 { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1724 { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1725 { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1726 { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1727 { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1728 { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1729 { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1730 { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1731 { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1732 { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1733 { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1734 { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1735 { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1736 { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1737 { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1738 { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1739 { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1740 { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1741 { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1742 { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1743 { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1744 { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1745 { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1746 { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1747 { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1748 { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1749 { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1750 { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1751 { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1752 { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1753 { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1754 { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1755 { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 }, 1756 { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1757 { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1758 { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1759 { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1760 { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1761 { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1762 { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1763 { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1764 { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1765 { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1766 { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1767 { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1768 { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1769 { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1770 { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1771 { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1772 { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1773 { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1774 { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1775 { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1776 { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1777 { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1778 { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1779 { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1780 { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1781 { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1782 { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1783 { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1784 { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1785 { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1786 { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1787 { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1788 { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1789 { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1790 { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1791 { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1792 { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1793 { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1794 { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1795 { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1796 { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1797 { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1798 { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1799 { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1800 { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1801 { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1802 { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1803 { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1804 { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1805 { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1806 { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1807 { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1808 { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1809 { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1810 { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1811 { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1812 { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1813 { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1814 { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1815 { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1816 { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1817 { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1818 { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1819 { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1820 { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1821 { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1822 { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1823 { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1824 { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1825 { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1826 { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1827 { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1828 { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1829 { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1830 { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1831 { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1832 { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1833 { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1834 { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1835 { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1836 { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1837 { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1838 { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1839 { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1840 { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1841 { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1842 { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1843 { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1844 { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1845 { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1846 { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1847 { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1848 { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1849 { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1850 { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1851 { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1852 { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1853 { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1854 { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1855 { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1856 { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1857 { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1858 { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1859 { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1860 { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1861 { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1862 { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1863 { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1864 { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1865 { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1866 { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1867 { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1868 { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1869 { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1870 { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1871 { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1872 { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1873 { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1874 { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1875 { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1876 { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1877 { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 }, 1878 { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 }, 1879 { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 1880 { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 }, 1881 { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 }, 1882 { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 }, 1883 { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 }, 1884 { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1885 { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1886 { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1887 { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1888 { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1889 { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 }, 1890 { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1891 { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1892 { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1893 { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1894 { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1895 { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1896 { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1897 { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1898 { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1899 { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1900 { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1901 { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1902 { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1903 { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1904 { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1905 { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1906 { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1907 { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1908 { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1909 { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1910 { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1911 { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1912 { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1913 { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1914 { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 1915 { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 1916 { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1917 { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1918 { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1919 { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1920 { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1921 { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1922 { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1923 { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1924 { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1925 { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1926 { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1927 { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1928 { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1929 { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1930 { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1931 { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1932 { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1933 { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1934 { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1935 { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1936 { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1937 { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1938 { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1939 { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1940 { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1941 { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1942 { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1943 { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1944 { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1945 { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1946 { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1947 { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1948 { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1949 { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1950 { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1951 { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1952 { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1953 { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1954 { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1955 { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1956 { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1957 { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1958 { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 1959 { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 1960 { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1961 { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1962 { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 1963 { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1964 { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1965 { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1966 { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1967 { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1968 { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1969 { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1970 { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1971 { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1972 { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1973 { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1974 { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1975 { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1976 { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1977 { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1978 { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1979 { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1980 { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1981 { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 1982 { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1983 { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1984 { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 }, 1985 { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1986 { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 }, 1987 { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 1988 { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1989 { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1990 { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1991 { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1992 { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1993 { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1994 { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1995 { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1996 { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1997 { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1998 { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 1999 { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2000 { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2001 { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2002 { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2003 { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2004 { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2005 { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2006 { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2007 { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2008 { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2009 { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2010 { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2011 { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2012 { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2013 { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2014 { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2015 { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2016 { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2017 { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2018 { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2019 { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2020 { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2021 { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2022 { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2023 { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2024 { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2025 { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2026 { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2027 { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2028 { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2029 { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2030 { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2031 { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2032 { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2033 { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 2034 { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 }, 2035 { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2036 { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2037 { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2038 { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2039 { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 }, 2040 { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 }, 2041 { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 }, 2042 { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 }, 2043 { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 }, 2044 { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2045 { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2046 { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2047 { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2048 { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2049 { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2050 { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2051 { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2052 { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2053 { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2054 { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2055 { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2056 { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2057 { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2058 { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2059 { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2060 { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2061 { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2062 { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2063 { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2064 { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2065 { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 }, 2066 { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 }, 2067 { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2068 { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2069 { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2070 { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2071 { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2072 { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2073 { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, 2074 { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 }, 2075 { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2076 { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2077 { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2078 { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2079 { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, 2080 { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 }, 2081 { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2082 { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 }, 2083 { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, 2084 { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2085 { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 2086 { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2087 { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, 2088 { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2089 { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2090 { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2091 { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2092 { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2093 { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2094 { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 }, 2095 { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 }, 2096 { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 2097 { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 2098 { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 2099 { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2100 { "fli.s", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2101 { "fli.d", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2102 { "fli.q", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2103 { "fli.h", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 }, 2104 { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2105 { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2106 { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2107 { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2108 { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2109 { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2110 { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2111 { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 2112 { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2113 { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2114 { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2115 { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2116 { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2117 { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2118 { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2119 { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 2120 { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 2121 { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2122 { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2123 { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 2124 { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 }, 2125 { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2126 { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2127 { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2128 { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2129 { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2130 { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2131 { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2132 { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 2133 { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2134 { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2135 { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2136 { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2137 { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2138 { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2139 { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2140 { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2141 { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2142 { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2143 { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2144 { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2145 { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2146 { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2147 { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2148 { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2149 { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2150 { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2151 { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2152 { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2153 { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2154 { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2155 { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2156 { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2157 { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, 2158 { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2159 { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2160 { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2161 { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2162 { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2163 { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2164 { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2165 { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2166 { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2167 { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, 2168 { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, 2169 { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2170 { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, 2171 { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, 2172 { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, 2173 { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, 2174 { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2175 { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2176 { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2177 { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2178 { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2179 { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2180 { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2181 { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2182 { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2183 { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2184 { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2185 { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2186 { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2187 { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2188 { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2189 { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2190 { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2191 { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2192 { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2193 { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2194 { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2195 { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2196 { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2197 { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2198 { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2199 { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2200 { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2201 { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2202 { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2203 { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2204 { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2205 { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2206 { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2207 { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2208 { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 2209 { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2210 { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2211 { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2212 { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2213 { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2214 { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2215 { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2216 { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 2217 { "c.mop.1", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2218 { "c.mop.3", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2219 { "c.mop.5", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2220 { "c.mop.7", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2221 { "c.mop.9", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2222 { "c.mop.11", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2223 { "c.mop.13", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2224 { "c.mop.15", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 }, 2225 { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2226 { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2227 { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2228 { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2229 { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2230 { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2231 { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2232 { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2233 { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2234 { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2235 { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2236 { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2237 { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2238 { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2239 { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2240 { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2241 { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2242 { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2243 { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2244 { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2245 { "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 2246 { "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 2247 { "lpad", rv_codec_lp, rv_fmt_imm, NULL, 0, 0, 0 }, 2248 { "sspush", rv_codec_r, rv_fmt_rs2, NULL, 0, 0, 0 }, 2249 { "sspopchk", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, 2250 { "ssrdp", rv_codec_r, rv_fmt_rd, NULL, 0, 0, 0 }, 2251 { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2252 { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 2253 { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush, 2254 rv_op_sspush, 0 }, 2255 { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk, 2256 rv_op_sspopchk, 0 }, 2257 }; 2258 2259 /* CSR names */ 2260 2261 static const char *csr_name(int csrno) 2262 { 2263 switch (csrno) { 2264 case 0x0000: return "ustatus"; 2265 case 0x0001: return "fflags"; 2266 case 0x0002: return "frm"; 2267 case 0x0003: return "fcsr"; 2268 case 0x0004: return "uie"; 2269 case 0x0005: return "utvec"; 2270 case 0x0008: return "vstart"; 2271 case 0x0009: return "vxsat"; 2272 case 0x000a: return "vxrm"; 2273 case 0x000f: return "vcsr"; 2274 case 0x0011: return "ssp"; 2275 case 0x0015: return "seed"; 2276 case 0x0017: return "jvt"; 2277 case 0x0040: return "uscratch"; 2278 case 0x0041: return "uepc"; 2279 case 0x0042: return "ucause"; 2280 case 0x0043: return "utval"; 2281 case 0x0044: return "uip"; 2282 case 0x0100: return "sstatus"; 2283 case 0x0104: return "sie"; 2284 case 0x0105: return "stvec"; 2285 case 0x0106: return "scounteren"; 2286 case 0x0140: return "sscratch"; 2287 case 0x0141: return "sepc"; 2288 case 0x0142: return "scause"; 2289 case 0x0143: return "stval"; 2290 case 0x0144: return "sip"; 2291 case 0x0180: return "satp"; 2292 case 0x0200: return "hstatus"; 2293 case 0x0202: return "hedeleg"; 2294 case 0x0203: return "hideleg"; 2295 case 0x0204: return "hie"; 2296 case 0x0205: return "htvec"; 2297 case 0x0240: return "hscratch"; 2298 case 0x0241: return "hepc"; 2299 case 0x0242: return "hcause"; 2300 case 0x0243: return "hbadaddr"; 2301 case 0x0244: return "hip"; 2302 case 0x0300: return "mstatus"; 2303 case 0x0301: return "misa"; 2304 case 0x0302: return "medeleg"; 2305 case 0x0303: return "mideleg"; 2306 case 0x0304: return "mie"; 2307 case 0x0305: return "mtvec"; 2308 case 0x0306: return "mcounteren"; 2309 case 0x0320: return "mucounteren"; 2310 case 0x0321: return "mscounteren"; 2311 case 0x0322: return "mhcounteren"; 2312 case 0x0323: return "mhpmevent3"; 2313 case 0x0324: return "mhpmevent4"; 2314 case 0x0325: return "mhpmevent5"; 2315 case 0x0326: return "mhpmevent6"; 2316 case 0x0327: return "mhpmevent7"; 2317 case 0x0328: return "mhpmevent8"; 2318 case 0x0329: return "mhpmevent9"; 2319 case 0x032a: return "mhpmevent10"; 2320 case 0x032b: return "mhpmevent11"; 2321 case 0x032c: return "mhpmevent12"; 2322 case 0x032d: return "mhpmevent13"; 2323 case 0x032e: return "mhpmevent14"; 2324 case 0x032f: return "mhpmevent15"; 2325 case 0x0330: return "mhpmevent16"; 2326 case 0x0331: return "mhpmevent17"; 2327 case 0x0332: return "mhpmevent18"; 2328 case 0x0333: return "mhpmevent19"; 2329 case 0x0334: return "mhpmevent20"; 2330 case 0x0335: return "mhpmevent21"; 2331 case 0x0336: return "mhpmevent22"; 2332 case 0x0337: return "mhpmevent23"; 2333 case 0x0338: return "mhpmevent24"; 2334 case 0x0339: return "mhpmevent25"; 2335 case 0x033a: return "mhpmevent26"; 2336 case 0x033b: return "mhpmevent27"; 2337 case 0x033c: return "mhpmevent28"; 2338 case 0x033d: return "mhpmevent29"; 2339 case 0x033e: return "mhpmevent30"; 2340 case 0x033f: return "mhpmevent31"; 2341 case 0x0340: return "mscratch"; 2342 case 0x0341: return "mepc"; 2343 case 0x0342: return "mcause"; 2344 case 0x0343: return "mtval"; 2345 case 0x0344: return "mip"; 2346 case 0x0380: return "mbase"; 2347 case 0x0381: return "mbound"; 2348 case 0x0382: return "mibase"; 2349 case 0x0383: return "mibound"; 2350 case 0x0384: return "mdbase"; 2351 case 0x0385: return "mdbound"; 2352 case 0x03a0: return "pmpcfg0"; 2353 case 0x03a1: return "pmpcfg1"; 2354 case 0x03a2: return "pmpcfg2"; 2355 case 0x03a3: return "pmpcfg3"; 2356 case 0x03a4: return "pmpcfg4"; 2357 case 0x03a5: return "pmpcfg5"; 2358 case 0x03a6: return "pmpcfg6"; 2359 case 0x03a7: return "pmpcfg7"; 2360 case 0x03a8: return "pmpcfg8"; 2361 case 0x03a9: return "pmpcfg9"; 2362 case 0x03aa: return "pmpcfg10"; 2363 case 0x03ab: return "pmpcfg11"; 2364 case 0x03ac: return "pmpcfg12"; 2365 case 0x03ad: return "pmpcfg13"; 2366 case 0x03ae: return "pmpcfg14"; 2367 case 0x03af: return "pmpcfg15"; 2368 case 0x03b0: return "pmpaddr0"; 2369 case 0x03b1: return "pmpaddr1"; 2370 case 0x03b2: return "pmpaddr2"; 2371 case 0x03b3: return "pmpaddr3"; 2372 case 0x03b4: return "pmpaddr4"; 2373 case 0x03b5: return "pmpaddr5"; 2374 case 0x03b6: return "pmpaddr6"; 2375 case 0x03b7: return "pmpaddr7"; 2376 case 0x03b8: return "pmpaddr8"; 2377 case 0x03b9: return "pmpaddr9"; 2378 case 0x03ba: return "pmpaddr10"; 2379 case 0x03bb: return "pmpaddr11"; 2380 case 0x03bc: return "pmpaddr12"; 2381 case 0x03bd: return "pmpaddr13"; 2382 case 0x03be: return "pmpaddr14"; 2383 case 0x03bf: return "pmpaddr15"; 2384 case 0x03c0: return "pmpaddr16"; 2385 case 0x03c1: return "pmpaddr17"; 2386 case 0x03c2: return "pmpaddr18"; 2387 case 0x03c3: return "pmpaddr19"; 2388 case 0x03c4: return "pmpaddr20"; 2389 case 0x03c5: return "pmpaddr21"; 2390 case 0x03c6: return "pmpaddr22"; 2391 case 0x03c7: return "pmpaddr23"; 2392 case 0x03c8: return "pmpaddr24"; 2393 case 0x03c9: return "pmpaddr25"; 2394 case 0x03ca: return "pmpaddr26"; 2395 case 0x03cb: return "pmpaddr27"; 2396 case 0x03cc: return "pmpaddr28"; 2397 case 0x03cd: return "pmpaddr29"; 2398 case 0x03ce: return "pmpaddr30"; 2399 case 0x03cf: return "pmpaddr31"; 2400 case 0x03d0: return "pmpaddr32"; 2401 case 0x03d1: return "pmpaddr33"; 2402 case 0x03d2: return "pmpaddr34"; 2403 case 0x03d3: return "pmpaddr35"; 2404 case 0x03d4: return "pmpaddr36"; 2405 case 0x03d5: return "pmpaddr37"; 2406 case 0x03d6: return "pmpaddr38"; 2407 case 0x03d7: return "pmpaddr39"; 2408 case 0x03d8: return "pmpaddr40"; 2409 case 0x03d9: return "pmpaddr41"; 2410 case 0x03da: return "pmpaddr42"; 2411 case 0x03db: return "pmpaddr43"; 2412 case 0x03dc: return "pmpaddr44"; 2413 case 0x03dd: return "pmpaddr45"; 2414 case 0x03de: return "pmpaddr46"; 2415 case 0x03df: return "pmpaddr47"; 2416 case 0x03e0: return "pmpaddr48"; 2417 case 0x03e1: return "pmpaddr49"; 2418 case 0x03e2: return "pmpaddr50"; 2419 case 0x03e3: return "pmpaddr51"; 2420 case 0x03e4: return "pmpaddr52"; 2421 case 0x03e5: return "pmpaddr53"; 2422 case 0x03e6: return "pmpaddr54"; 2423 case 0x03e7: return "pmpaddr55"; 2424 case 0x03e8: return "pmpaddr56"; 2425 case 0x03e9: return "pmpaddr57"; 2426 case 0x03ea: return "pmpaddr58"; 2427 case 0x03eb: return "pmpaddr59"; 2428 case 0x03ec: return "pmpaddr60"; 2429 case 0x03ed: return "pmpaddr61"; 2430 case 0x03ee: return "pmpaddr62"; 2431 case 0x03ef: return "pmpaddr63"; 2432 case 0x0780: return "mtohost"; 2433 case 0x0781: return "mfromhost"; 2434 case 0x0782: return "mreset"; 2435 case 0x0783: return "mipi"; 2436 case 0x0784: return "miobase"; 2437 case 0x07a0: return "tselect"; 2438 case 0x07a1: return "tdata1"; 2439 case 0x07a2: return "tdata2"; 2440 case 0x07a3: return "tdata3"; 2441 case 0x07b0: return "dcsr"; 2442 case 0x07b1: return "dpc"; 2443 case 0x07b2: return "dscratch"; 2444 case 0x0b00: return "mcycle"; 2445 case 0x0b01: return "mtime"; 2446 case 0x0b02: return "minstret"; 2447 case 0x0b03: return "mhpmcounter3"; 2448 case 0x0b04: return "mhpmcounter4"; 2449 case 0x0b05: return "mhpmcounter5"; 2450 case 0x0b06: return "mhpmcounter6"; 2451 case 0x0b07: return "mhpmcounter7"; 2452 case 0x0b08: return "mhpmcounter8"; 2453 case 0x0b09: return "mhpmcounter9"; 2454 case 0x0b0a: return "mhpmcounter10"; 2455 case 0x0b0b: return "mhpmcounter11"; 2456 case 0x0b0c: return "mhpmcounter12"; 2457 case 0x0b0d: return "mhpmcounter13"; 2458 case 0x0b0e: return "mhpmcounter14"; 2459 case 0x0b0f: return "mhpmcounter15"; 2460 case 0x0b10: return "mhpmcounter16"; 2461 case 0x0b11: return "mhpmcounter17"; 2462 case 0x0b12: return "mhpmcounter18"; 2463 case 0x0b13: return "mhpmcounter19"; 2464 case 0x0b14: return "mhpmcounter20"; 2465 case 0x0b15: return "mhpmcounter21"; 2466 case 0x0b16: return "mhpmcounter22"; 2467 case 0x0b17: return "mhpmcounter23"; 2468 case 0x0b18: return "mhpmcounter24"; 2469 case 0x0b19: return "mhpmcounter25"; 2470 case 0x0b1a: return "mhpmcounter26"; 2471 case 0x0b1b: return "mhpmcounter27"; 2472 case 0x0b1c: return "mhpmcounter28"; 2473 case 0x0b1d: return "mhpmcounter29"; 2474 case 0x0b1e: return "mhpmcounter30"; 2475 case 0x0b1f: return "mhpmcounter31"; 2476 case 0x0b80: return "mcycleh"; 2477 case 0x0b81: return "mtimeh"; 2478 case 0x0b82: return "minstreth"; 2479 case 0x0b83: return "mhpmcounter3h"; 2480 case 0x0b84: return "mhpmcounter4h"; 2481 case 0x0b85: return "mhpmcounter5h"; 2482 case 0x0b86: return "mhpmcounter6h"; 2483 case 0x0b87: return "mhpmcounter7h"; 2484 case 0x0b88: return "mhpmcounter8h"; 2485 case 0x0b89: return "mhpmcounter9h"; 2486 case 0x0b8a: return "mhpmcounter10h"; 2487 case 0x0b8b: return "mhpmcounter11h"; 2488 case 0x0b8c: return "mhpmcounter12h"; 2489 case 0x0b8d: return "mhpmcounter13h"; 2490 case 0x0b8e: return "mhpmcounter14h"; 2491 case 0x0b8f: return "mhpmcounter15h"; 2492 case 0x0b90: return "mhpmcounter16h"; 2493 case 0x0b91: return "mhpmcounter17h"; 2494 case 0x0b92: return "mhpmcounter18h"; 2495 case 0x0b93: return "mhpmcounter19h"; 2496 case 0x0b94: return "mhpmcounter20h"; 2497 case 0x0b95: return "mhpmcounter21h"; 2498 case 0x0b96: return "mhpmcounter22h"; 2499 case 0x0b97: return "mhpmcounter23h"; 2500 case 0x0b98: return "mhpmcounter24h"; 2501 case 0x0b99: return "mhpmcounter25h"; 2502 case 0x0b9a: return "mhpmcounter26h"; 2503 case 0x0b9b: return "mhpmcounter27h"; 2504 case 0x0b9c: return "mhpmcounter28h"; 2505 case 0x0b9d: return "mhpmcounter29h"; 2506 case 0x0b9e: return "mhpmcounter30h"; 2507 case 0x0b9f: return "mhpmcounter31h"; 2508 case 0x0c00: return "cycle"; 2509 case 0x0c01: return "time"; 2510 case 0x0c02: return "instret"; 2511 case 0x0c20: return "vl"; 2512 case 0x0c21: return "vtype"; 2513 case 0x0c22: return "vlenb"; 2514 case 0x0c80: return "cycleh"; 2515 case 0x0c81: return "timeh"; 2516 case 0x0c82: return "instreth"; 2517 case 0x0d00: return "scycle"; 2518 case 0x0d01: return "stime"; 2519 case 0x0d02: return "sinstret"; 2520 case 0x0d80: return "scycleh"; 2521 case 0x0d81: return "stimeh"; 2522 case 0x0d82: return "sinstreth"; 2523 case 0x0e00: return "hcycle"; 2524 case 0x0e01: return "htime"; 2525 case 0x0e02: return "hinstret"; 2526 case 0x0e80: return "hcycleh"; 2527 case 0x0e81: return "htimeh"; 2528 case 0x0e82: return "hinstreth"; 2529 case 0x0f11: return "mvendorid"; 2530 case 0x0f12: return "marchid"; 2531 case 0x0f13: return "mimpid"; 2532 case 0x0f14: return "mhartid"; 2533 default: return NULL; 2534 } 2535 } 2536 2537 /* decode opcode */ 2538 2539 static void decode_inst_opcode(rv_decode *dec, rv_isa isa) 2540 { 2541 rv_inst inst = dec->inst; 2542 rv_opcode op = rv_op_illegal; 2543 switch ((inst >> 0) & 0b11) { 2544 case 0: 2545 switch ((inst >> 13) & 0b111) { 2546 case 0: op = rv_op_c_addi4spn; break; 2547 case 1: 2548 if (isa == rv128) { 2549 op = rv_op_c_lq; 2550 } else { 2551 op = rv_op_c_fld; 2552 } 2553 break; 2554 case 2: op = rv_op_c_lw; break; 2555 case 3: 2556 if (isa == rv32) { 2557 op = rv_op_c_flw; 2558 } else { 2559 op = rv_op_c_ld; 2560 } 2561 break; 2562 case 4: 2563 switch ((inst >> 10) & 0b111) { 2564 case 0: op = rv_op_c_lbu; break; 2565 case 1: 2566 if (((inst >> 6) & 1) == 0) { 2567 op = rv_op_c_lhu; 2568 } else { 2569 op = rv_op_c_lh; 2570 } 2571 break; 2572 case 2: op = rv_op_c_sb; break; 2573 case 3: 2574 if (((inst >> 6) & 1) == 0) { 2575 op = rv_op_c_sh; 2576 } 2577 break; 2578 } 2579 break; 2580 case 5: 2581 if (isa == rv128) { 2582 op = rv_op_c_sq; 2583 } else { 2584 op = rv_op_c_fsd; 2585 } 2586 break; 2587 case 6: op = rv_op_c_sw; break; 2588 case 7: 2589 if (isa == rv32) { 2590 op = rv_op_c_fsw; 2591 } else { 2592 op = rv_op_c_sd; 2593 } 2594 break; 2595 } 2596 break; 2597 case 1: 2598 switch ((inst >> 13) & 0b111) { 2599 case 0: 2600 switch ((inst >> 2) & 0b11111111111) { 2601 case 0: op = rv_op_c_nop; break; 2602 default: op = rv_op_c_addi; break; 2603 } 2604 break; 2605 case 1: 2606 if (isa == rv32) { 2607 op = rv_op_c_jal; 2608 } else { 2609 op = rv_op_c_addiw; 2610 } 2611 break; 2612 case 2: op = rv_op_c_li; break; 2613 case 3: 2614 if (dec->cfg->ext_zcmop) { 2615 if ((((inst >> 2) & 0b111111) == 0b100000) && 2616 (((inst >> 11) & 0b11) == 0b0)) { 2617 unsigned int cmop_code = 0; 2618 cmop_code = ((inst >> 8) & 0b111); 2619 op = rv_c_mop_1 + cmop_code; 2620 if (dec->cfg->ext_zicfiss) { 2621 op = (cmop_code == 0) ? rv_op_c_sspush : op; 2622 op = (cmop_code == 2) ? rv_op_c_sspopchk : op; 2623 } 2624 break; 2625 } 2626 } 2627 switch ((inst >> 7) & 0b11111) { 2628 case 2: op = rv_op_c_addi16sp; break; 2629 default: op = rv_op_c_lui; break; 2630 } 2631 break; 2632 case 4: 2633 switch ((inst >> 10) & 0b11) { 2634 case 0: 2635 op = rv_op_c_srli; 2636 break; 2637 case 1: 2638 op = rv_op_c_srai; 2639 break; 2640 case 2: op = rv_op_c_andi; break; 2641 case 3: 2642 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) { 2643 case 0: op = rv_op_c_sub; break; 2644 case 1: op = rv_op_c_xor; break; 2645 case 2: op = rv_op_c_or; break; 2646 case 3: op = rv_op_c_and; break; 2647 case 4: op = rv_op_c_subw; break; 2648 case 5: op = rv_op_c_addw; break; 2649 case 6: op = rv_op_c_mul; break; 2650 case 7: 2651 switch ((inst >> 2) & 0b111) { 2652 case 0: op = rv_op_c_zext_b; break; 2653 case 1: op = rv_op_c_sext_b; break; 2654 case 2: op = rv_op_c_zext_h; break; 2655 case 3: op = rv_op_c_sext_h; break; 2656 case 4: op = rv_op_c_zext_w; break; 2657 case 5: op = rv_op_c_not; break; 2658 } 2659 break; 2660 } 2661 break; 2662 } 2663 break; 2664 case 5: op = rv_op_c_j; break; 2665 case 6: op = rv_op_c_beqz; break; 2666 case 7: op = rv_op_c_bnez; break; 2667 } 2668 break; 2669 case 2: 2670 switch ((inst >> 13) & 0b111) { 2671 case 0: 2672 op = rv_op_c_slli; 2673 break; 2674 case 1: 2675 if (isa == rv128) { 2676 op = rv_op_c_lqsp; 2677 } else { 2678 op = rv_op_c_fldsp; 2679 } 2680 break; 2681 case 2: op = rv_op_c_lwsp; break; 2682 case 3: 2683 if (isa == rv32) { 2684 op = rv_op_c_flwsp; 2685 } else { 2686 op = rv_op_c_ldsp; 2687 } 2688 break; 2689 case 4: 2690 switch ((inst >> 12) & 0b1) { 2691 case 0: 2692 switch ((inst >> 2) & 0b11111) { 2693 case 0: op = rv_op_c_jr; break; 2694 default: op = rv_op_c_mv; break; 2695 } 2696 break; 2697 case 1: 2698 switch ((inst >> 2) & 0b11111) { 2699 case 0: 2700 switch ((inst >> 7) & 0b11111) { 2701 case 0: op = rv_op_c_ebreak; break; 2702 default: op = rv_op_c_jalr; break; 2703 } 2704 break; 2705 default: op = rv_op_c_add; break; 2706 } 2707 break; 2708 } 2709 break; 2710 case 5: 2711 if (isa == rv128) { 2712 op = rv_op_c_sqsp; 2713 } else { 2714 op = rv_op_c_fsdsp; 2715 if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { 2716 switch ((inst >> 8) & 0b01111) { 2717 case 8: 2718 if (((inst >> 4) & 0b01111) >= 4) { 2719 op = rv_op_cm_push; 2720 } 2721 break; 2722 case 10: 2723 if (((inst >> 4) & 0b01111) >= 4) { 2724 op = rv_op_cm_pop; 2725 } 2726 break; 2727 case 12: 2728 if (((inst >> 4) & 0b01111) >= 4) { 2729 op = rv_op_cm_popretz; 2730 } 2731 break; 2732 case 14: 2733 if (((inst >> 4) & 0b01111) >= 4) { 2734 op = rv_op_cm_popret; 2735 } 2736 break; 2737 } 2738 } else { 2739 switch ((inst >> 10) & 0b011) { 2740 case 0: 2741 if (!dec->cfg->ext_zcmt) { 2742 break; 2743 } 2744 if (((inst >> 2) & 0xFF) >= 32) { 2745 op = rv_op_cm_jalt; 2746 } else { 2747 op = rv_op_cm_jt; 2748 } 2749 break; 2750 case 3: 2751 if (!dec->cfg->ext_zcmp) { 2752 break; 2753 } 2754 switch ((inst >> 5) & 0b011) { 2755 case 1: op = rv_op_cm_mvsa01; break; 2756 case 3: op = rv_op_cm_mva01s; break; 2757 } 2758 break; 2759 } 2760 } 2761 } 2762 break; 2763 case 6: op = rv_op_c_swsp; break; 2764 case 7: 2765 if (isa == rv32) { 2766 op = rv_op_c_fswsp; 2767 } else { 2768 op = rv_op_c_sdsp; 2769 } 2770 break; 2771 } 2772 break; 2773 case 3: 2774 switch ((inst >> 2) & 0b11111) { 2775 case 0: 2776 switch ((inst >> 12) & 0b111) { 2777 case 0: op = rv_op_lb; break; 2778 case 1: op = rv_op_lh; break; 2779 case 2: op = rv_op_lw; break; 2780 case 3: op = rv_op_ld; break; 2781 case 4: op = rv_op_lbu; break; 2782 case 5: op = rv_op_lhu; break; 2783 case 6: op = rv_op_lwu; break; 2784 case 7: op = rv_op_ldu; break; 2785 } 2786 break; 2787 case 1: 2788 switch ((inst >> 12) & 0b111) { 2789 case 0: 2790 switch ((inst >> 20) & 0b111111111111) { 2791 case 40: op = rv_op_vl1re8_v; break; 2792 case 552: op = rv_op_vl2re8_v; break; 2793 case 1576: op = rv_op_vl4re8_v; break; 2794 case 3624: op = rv_op_vl8re8_v; break; 2795 } 2796 switch ((inst >> 26) & 0b111) { 2797 case 0: 2798 switch ((inst >> 20) & 0b11111) { 2799 case 0: op = rv_op_vle8_v; break; 2800 case 11: op = rv_op_vlm_v; break; 2801 case 16: op = rv_op_vle8ff_v; break; 2802 } 2803 break; 2804 case 1: op = rv_op_vluxei8_v; break; 2805 case 2: op = rv_op_vlse8_v; break; 2806 case 3: op = rv_op_vloxei8_v; break; 2807 } 2808 break; 2809 case 1: op = rv_op_flh; break; 2810 case 2: op = rv_op_flw; break; 2811 case 3: op = rv_op_fld; break; 2812 case 4: op = rv_op_flq; break; 2813 case 5: 2814 switch ((inst >> 20) & 0b111111111111) { 2815 case 40: op = rv_op_vl1re16_v; break; 2816 case 552: op = rv_op_vl2re16_v; break; 2817 case 1576: op = rv_op_vl4re16_v; break; 2818 case 3624: op = rv_op_vl8re16_v; break; 2819 } 2820 switch ((inst >> 26) & 0b111) { 2821 case 0: 2822 switch ((inst >> 20) & 0b11111) { 2823 case 0: op = rv_op_vle16_v; break; 2824 case 16: op = rv_op_vle16ff_v; break; 2825 } 2826 break; 2827 case 1: op = rv_op_vluxei16_v; break; 2828 case 2: op = rv_op_vlse16_v; break; 2829 case 3: op = rv_op_vloxei16_v; break; 2830 } 2831 break; 2832 case 6: 2833 switch ((inst >> 20) & 0b111111111111) { 2834 case 40: op = rv_op_vl1re32_v; break; 2835 case 552: op = rv_op_vl2re32_v; break; 2836 case 1576: op = rv_op_vl4re32_v; break; 2837 case 3624: op = rv_op_vl8re32_v; break; 2838 } 2839 switch ((inst >> 26) & 0b111) { 2840 case 0: 2841 switch ((inst >> 20) & 0b11111) { 2842 case 0: op = rv_op_vle32_v; break; 2843 case 16: op = rv_op_vle32ff_v; break; 2844 } 2845 break; 2846 case 1: op = rv_op_vluxei32_v; break; 2847 case 2: op = rv_op_vlse32_v; break; 2848 case 3: op = rv_op_vloxei32_v; break; 2849 } 2850 break; 2851 case 7: 2852 switch ((inst >> 20) & 0b111111111111) { 2853 case 40: op = rv_op_vl1re64_v; break; 2854 case 552: op = rv_op_vl2re64_v; break; 2855 case 1576: op = rv_op_vl4re64_v; break; 2856 case 3624: op = rv_op_vl8re64_v; break; 2857 } 2858 switch ((inst >> 26) & 0b111) { 2859 case 0: 2860 switch ((inst >> 20) & 0b11111) { 2861 case 0: op = rv_op_vle64_v; break; 2862 case 16: op = rv_op_vle64ff_v; break; 2863 } 2864 break; 2865 case 1: op = rv_op_vluxei64_v; break; 2866 case 2: op = rv_op_vlse64_v; break; 2867 case 3: op = rv_op_vloxei64_v; break; 2868 } 2869 break; 2870 } 2871 break; 2872 case 3: 2873 switch ((inst >> 12) & 0b111) { 2874 case 0: op = rv_op_fence; break; 2875 case 1: op = rv_op_fence_i; break; 2876 case 2: op = rv_op_lq; break; 2877 } 2878 break; 2879 case 4: 2880 switch ((inst >> 12) & 0b111) { 2881 case 0: op = rv_op_addi; break; 2882 case 1: 2883 switch ((inst >> 27) & 0b11111) { 2884 case 0b00000: op = rv_op_slli; break; 2885 case 0b00001: 2886 switch ((inst >> 20) & 0b1111111) { 2887 case 0b0001111: op = rv_op_zip; break; 2888 } 2889 break; 2890 case 0b00010: 2891 switch ((inst >> 20) & 0b1111111) { 2892 case 0b0000000: op = rv_op_sha256sum0; break; 2893 case 0b0000001: op = rv_op_sha256sum1; break; 2894 case 0b0000010: op = rv_op_sha256sig0; break; 2895 case 0b0000011: op = rv_op_sha256sig1; break; 2896 case 0b0000100: op = rv_op_sha512sum0; break; 2897 case 0b0000101: op = rv_op_sha512sum1; break; 2898 case 0b0000110: op = rv_op_sha512sig0; break; 2899 case 0b0000111: op = rv_op_sha512sig1; break; 2900 case 0b0001000: op = rv_op_sm3p0; break; 2901 case 0b0001001: op = rv_op_sm3p1; break; 2902 } 2903 break; 2904 case 0b00101: op = rv_op_bseti; break; 2905 case 0b00110: 2906 switch ((inst >> 20) & 0b1111111) { 2907 case 0b0000000: op = rv_op_aes64im; break; 2908 default: 2909 if (((inst >> 24) & 0b0111) == 0b001) { 2910 op = rv_op_aes64ks1i; 2911 } 2912 break; 2913 } 2914 break; 2915 case 0b01001: op = rv_op_bclri; break; 2916 case 0b01101: op = rv_op_binvi; break; 2917 case 0b01100: 2918 switch ((inst >> 20) & 0b1111111) { 2919 case 0b0000000: op = rv_op_clz; break; 2920 case 0b0000001: op = rv_op_ctz; break; 2921 case 0b0000010: op = rv_op_cpop; break; 2922 /* 0b0000011 */ 2923 case 0b0000100: op = rv_op_sext_b; break; 2924 case 0b0000101: op = rv_op_sext_h; break; 2925 } 2926 break; 2927 } 2928 break; 2929 case 2: op = rv_op_slti; break; 2930 case 3: op = rv_op_sltiu; break; 2931 case 4: op = rv_op_xori; break; 2932 case 5: 2933 switch ((inst >> 27) & 0b11111) { 2934 case 0b00000: op = rv_op_srli; break; 2935 case 0b00001: 2936 switch ((inst >> 20) & 0b1111111) { 2937 case 0b0001111: op = rv_op_unzip; break; 2938 } 2939 break; 2940 case 0b00101: op = rv_op_orc_b; break; 2941 case 0b01000: op = rv_op_srai; break; 2942 case 0b01001: op = rv_op_bexti; break; 2943 case 0b01100: op = rv_op_rori; break; 2944 case 0b01101: 2945 switch ((inst >> 20) & 0b1111111) { 2946 case 0b0011000: op = rv_op_rev8; break; 2947 case 0b0111000: op = rv_op_rev8; break; 2948 case 0b0000111: op = rv_op_brev8; break; 2949 } 2950 break; 2951 } 2952 break; 2953 case 6: op = rv_op_ori; break; 2954 case 7: op = rv_op_andi; break; 2955 } 2956 break; 2957 case 5: 2958 op = rv_op_auipc; 2959 if (dec->cfg->ext_zicfilp && 2960 (((inst >> 7) & 0b11111) == 0b00000)) { 2961 op = rv_op_lpad; 2962 } 2963 break; 2964 case 6: 2965 switch ((inst >> 12) & 0b111) { 2966 case 0: op = rv_op_addiw; break; 2967 case 1: 2968 switch ((inst >> 26) & 0b111111) { 2969 case 0: op = rv_op_slliw; break; 2970 case 2: op = rv_op_slli_uw; break; 2971 case 24: 2972 switch ((inst >> 20) & 0b11111) { 2973 case 0b00000: op = rv_op_clzw; break; 2974 case 0b00001: op = rv_op_ctzw; break; 2975 case 0b00010: op = rv_op_cpopw; break; 2976 } 2977 break; 2978 } 2979 break; 2980 case 5: 2981 switch ((inst >> 25) & 0b1111111) { 2982 case 0: op = rv_op_srliw; break; 2983 case 32: op = rv_op_sraiw; break; 2984 case 48: op = rv_op_roriw; break; 2985 } 2986 break; 2987 } 2988 break; 2989 case 8: 2990 switch ((inst >> 12) & 0b111) { 2991 case 0: op = rv_op_sb; break; 2992 case 1: op = rv_op_sh; break; 2993 case 2: op = rv_op_sw; break; 2994 case 3: op = rv_op_sd; break; 2995 case 4: op = rv_op_sq; break; 2996 } 2997 break; 2998 case 9: 2999 switch ((inst >> 12) & 0b111) { 3000 case 0: 3001 switch ((inst >> 20) & 0b111111111111) { 3002 case 40: op = rv_op_vs1r_v; break; 3003 case 552: op = rv_op_vs2r_v; break; 3004 case 1576: op = rv_op_vs4r_v; break; 3005 case 3624: op = rv_op_vs8r_v; break; 3006 } 3007 switch ((inst >> 26) & 0b111) { 3008 case 0: 3009 switch ((inst >> 20) & 0b11111) { 3010 case 0: op = rv_op_vse8_v; break; 3011 case 11: op = rv_op_vsm_v; break; 3012 } 3013 break; 3014 case 1: op = rv_op_vsuxei8_v; break; 3015 case 2: op = rv_op_vsse8_v; break; 3016 case 3: op = rv_op_vsoxei8_v; break; 3017 } 3018 break; 3019 case 1: op = rv_op_fsh; break; 3020 case 2: op = rv_op_fsw; break; 3021 case 3: op = rv_op_fsd; break; 3022 case 4: op = rv_op_fsq; break; 3023 case 5: 3024 switch ((inst >> 26) & 0b111) { 3025 case 0: 3026 switch ((inst >> 20) & 0b11111) { 3027 case 0: op = rv_op_vse16_v; break; 3028 } 3029 break; 3030 case 1: op = rv_op_vsuxei16_v; break; 3031 case 2: op = rv_op_vsse16_v; break; 3032 case 3: op = rv_op_vsoxei16_v; break; 3033 } 3034 break; 3035 case 6: 3036 switch ((inst >> 26) & 0b111) { 3037 case 0: 3038 switch ((inst >> 20) & 0b11111) { 3039 case 0: op = rv_op_vse32_v; break; 3040 } 3041 break; 3042 case 1: op = rv_op_vsuxei32_v; break; 3043 case 2: op = rv_op_vsse32_v; break; 3044 case 3: op = rv_op_vsoxei32_v; break; 3045 } 3046 break; 3047 case 7: 3048 switch ((inst >> 26) & 0b111) { 3049 case 0: 3050 switch ((inst >> 20) & 0b11111) { 3051 case 0: op = rv_op_vse64_v; break; 3052 } 3053 break; 3054 case 1: op = rv_op_vsuxei64_v; break; 3055 case 2: op = rv_op_vsse64_v; break; 3056 case 3: op = rv_op_vsoxei64_v; break; 3057 } 3058 break; 3059 } 3060 break; 3061 case 11: 3062 switch (((inst >> 24) & 0b11111000) | 3063 ((inst >> 12) & 0b00000111)) { 3064 case 0: op = rv_op_amoadd_b; break; 3065 case 1: op = rv_op_amoadd_h; break; 3066 case 2: op = rv_op_amoadd_w; break; 3067 case 3: op = rv_op_amoadd_d; break; 3068 case 4: op = rv_op_amoadd_q; break; 3069 case 8: op = rv_op_amoswap_b; break; 3070 case 9: op = rv_op_amoswap_h; break; 3071 case 10: op = rv_op_amoswap_w; break; 3072 case 11: op = rv_op_amoswap_d; break; 3073 case 12: op = rv_op_amoswap_q; break; 3074 case 18: 3075 switch ((inst >> 20) & 0b11111) { 3076 case 0: op = rv_op_lr_w; break; 3077 } 3078 break; 3079 case 19: 3080 switch ((inst >> 20) & 0b11111) { 3081 case 0: op = rv_op_lr_d; break; 3082 } 3083 break; 3084 case 20: 3085 switch ((inst >> 20) & 0b11111) { 3086 case 0: op = rv_op_lr_q; break; 3087 } 3088 break; 3089 case 26: op = rv_op_sc_w; break; 3090 case 27: op = rv_op_sc_d; break; 3091 case 28: op = rv_op_sc_q; break; 3092 case 32: op = rv_op_amoxor_b; break; 3093 case 33: op = rv_op_amoxor_h; break; 3094 case 34: op = rv_op_amoxor_w; break; 3095 case 35: op = rv_op_amoxor_d; break; 3096 case 36: op = rv_op_amoxor_q; break; 3097 case 40: op = rv_op_amocas_b; break; 3098 case 41: op = rv_op_amocas_h; break; 3099 case 42: op = rv_op_amocas_w; break; 3100 case 43: op = rv_op_amocas_d; break; 3101 case 44: op = rv_op_amocas_q; break; 3102 case 64: op = rv_op_amoor_b; break; 3103 case 65: op = rv_op_amoor_h; break; 3104 case 66: op = rv_op_amoor_w; break; 3105 case 67: op = rv_op_amoor_d; break; 3106 case 68: op = rv_op_amoor_q; break; 3107 case 74: op = rv_op_ssamoswap_w; break; 3108 case 75: op = rv_op_ssamoswap_d; break; 3109 case 96: op = rv_op_amoand_b; break; 3110 case 97: op = rv_op_amoand_h; break; 3111 case 98: op = rv_op_amoand_w; break; 3112 case 99: op = rv_op_amoand_d; break; 3113 case 100: op = rv_op_amoand_q; break; 3114 case 128: op = rv_op_amomin_b; break; 3115 case 129: op = rv_op_amomin_h; break; 3116 case 130: op = rv_op_amomin_w; break; 3117 case 131: op = rv_op_amomin_d; break; 3118 case 132: op = rv_op_amomin_q; break; 3119 case 160: op = rv_op_amomax_b; break; 3120 case 161: op = rv_op_amomax_h; break; 3121 case 162: op = rv_op_amomax_w; break; 3122 case 163: op = rv_op_amomax_d; break; 3123 case 164: op = rv_op_amomax_q; break; 3124 case 192: op = rv_op_amominu_b; break; 3125 case 193: op = rv_op_amominu_h; break; 3126 case 194: op = rv_op_amominu_w; break; 3127 case 195: op = rv_op_amominu_d; break; 3128 case 196: op = rv_op_amominu_q; break; 3129 case 224: op = rv_op_amomaxu_b; break; 3130 case 225: op = rv_op_amomaxu_h; break; 3131 case 226: op = rv_op_amomaxu_w; break; 3132 case 227: op = rv_op_amomaxu_d; break; 3133 case 228: op = rv_op_amomaxu_q; break; 3134 } 3135 break; 3136 case 12: 3137 switch (((inst >> 22) & 0b1111111000) | 3138 ((inst >> 12) & 0b0000000111)) { 3139 case 0: op = rv_op_add; break; 3140 case 1: op = rv_op_sll; break; 3141 case 2: op = rv_op_slt; break; 3142 case 3: op = rv_op_sltu; break; 3143 case 4: op = rv_op_xor; break; 3144 case 5: op = rv_op_srl; break; 3145 case 6: op = rv_op_or; break; 3146 case 7: op = rv_op_and; break; 3147 case 8: op = rv_op_mul; break; 3148 case 9: op = rv_op_mulh; break; 3149 case 10: op = rv_op_mulhsu; break; 3150 case 11: op = rv_op_mulhu; break; 3151 case 12: op = rv_op_div; break; 3152 case 13: op = rv_op_divu; break; 3153 case 14: op = rv_op_rem; break; 3154 case 15: op = rv_op_remu; break; 3155 case 36: 3156 switch ((inst >> 20) & 0b11111) { 3157 case 0: op = rv_op_zext_h; break; 3158 default: op = rv_op_pack; break; 3159 } 3160 break; 3161 case 39: op = rv_op_packh; break; 3162 3163 case 41: op = rv_op_clmul; break; 3164 case 42: op = rv_op_clmulr; break; 3165 case 43: op = rv_op_clmulh; break; 3166 case 44: op = rv_op_min; break; 3167 case 45: op = rv_op_minu; break; 3168 case 46: op = rv_op_max; break; 3169 case 47: op = rv_op_maxu; break; 3170 case 075: op = rv_op_czero_eqz; break; 3171 case 077: op = rv_op_czero_nez; break; 3172 case 130: op = rv_op_sh1add; break; 3173 case 132: op = rv_op_sh2add; break; 3174 case 134: op = rv_op_sh3add; break; 3175 case 161: op = rv_op_bset; break; 3176 case 162: op = rv_op_xperm4; break; 3177 case 164: op = rv_op_xperm8; break; 3178 case 200: op = rv_op_aes64es; break; 3179 case 216: op = rv_op_aes64esm; break; 3180 case 232: op = rv_op_aes64ds; break; 3181 case 248: op = rv_op_aes64dsm; break; 3182 case 256: op = rv_op_sub; break; 3183 case 260: op = rv_op_xnor; break; 3184 case 261: op = rv_op_sra; break; 3185 case 262: op = rv_op_orn; break; 3186 case 263: op = rv_op_andn; break; 3187 case 289: op = rv_op_bclr; break; 3188 case 293: op = rv_op_bext; break; 3189 case 320: op = rv_op_sha512sum0r; break; 3190 case 328: op = rv_op_sha512sum1r; break; 3191 case 336: op = rv_op_sha512sig0l; break; 3192 case 344: op = rv_op_sha512sig1l; break; 3193 case 368: op = rv_op_sha512sig0h; break; 3194 case 376: op = rv_op_sha512sig1h; break; 3195 case 385: op = rv_op_rol; break; 3196 case 389: op = rv_op_ror; break; 3197 case 417: op = rv_op_binv; break; 3198 case 504: op = rv_op_aes64ks2; break; 3199 } 3200 switch ((inst >> 25) & 0b0011111) { 3201 case 17: op = rv_op_aes32esi; break; 3202 case 19: op = rv_op_aes32esmi; break; 3203 case 21: op = rv_op_aes32dsi; break; 3204 case 23: op = rv_op_aes32dsmi; break; 3205 case 24: op = rv_op_sm4ed; break; 3206 case 26: op = rv_op_sm4ks; break; 3207 } 3208 break; 3209 case 13: op = rv_op_lui; break; 3210 case 14: 3211 switch (((inst >> 22) & 0b1111111000) | 3212 ((inst >> 12) & 0b0000000111)) { 3213 case 0: op = rv_op_addw; break; 3214 case 1: op = rv_op_sllw; break; 3215 case 5: op = rv_op_srlw; break; 3216 case 8: op = rv_op_mulw; break; 3217 case 12: op = rv_op_divw; break; 3218 case 13: op = rv_op_divuw; break; 3219 case 14: op = rv_op_remw; break; 3220 case 15: op = rv_op_remuw; break; 3221 case 32: op = rv_op_add_uw; break; 3222 case 36: 3223 switch ((inst >> 20) & 0b11111) { 3224 case 0: op = rv_op_zext_h; break; 3225 default: op = rv_op_packw; break; 3226 } 3227 break; 3228 case 130: op = rv_op_sh1add_uw; break; 3229 case 132: op = rv_op_sh2add_uw; break; 3230 case 134: op = rv_op_sh3add_uw; break; 3231 case 256: op = rv_op_subw; break; 3232 case 261: op = rv_op_sraw; break; 3233 case 385: op = rv_op_rolw; break; 3234 case 389: op = rv_op_rorw; break; 3235 } 3236 break; 3237 case 16: 3238 switch ((inst >> 25) & 0b11) { 3239 case 0: op = rv_op_fmadd_s; break; 3240 case 1: op = rv_op_fmadd_d; break; 3241 case 3: op = rv_op_fmadd_q; break; 3242 } 3243 break; 3244 case 17: 3245 switch ((inst >> 25) & 0b11) { 3246 case 0: op = rv_op_fmsub_s; break; 3247 case 1: op = rv_op_fmsub_d; break; 3248 case 3: op = rv_op_fmsub_q; break; 3249 } 3250 break; 3251 case 18: 3252 switch ((inst >> 25) & 0b11) { 3253 case 0: op = rv_op_fnmsub_s; break; 3254 case 1: op = rv_op_fnmsub_d; break; 3255 case 3: op = rv_op_fnmsub_q; break; 3256 } 3257 break; 3258 case 19: 3259 switch ((inst >> 25) & 0b11) { 3260 case 0: op = rv_op_fnmadd_s; break; 3261 case 1: op = rv_op_fnmadd_d; break; 3262 case 3: op = rv_op_fnmadd_q; break; 3263 } 3264 break; 3265 case 20: 3266 switch ((inst >> 25) & 0b1111111) { 3267 case 0: op = rv_op_fadd_s; break; 3268 case 1: op = rv_op_fadd_d; break; 3269 case 3: op = rv_op_fadd_q; break; 3270 case 4: op = rv_op_fsub_s; break; 3271 case 5: op = rv_op_fsub_d; break; 3272 case 7: op = rv_op_fsub_q; break; 3273 case 8: op = rv_op_fmul_s; break; 3274 case 9: op = rv_op_fmul_d; break; 3275 case 11: op = rv_op_fmul_q; break; 3276 case 12: op = rv_op_fdiv_s; break; 3277 case 13: op = rv_op_fdiv_d; break; 3278 case 15: op = rv_op_fdiv_q; break; 3279 case 16: 3280 switch ((inst >> 12) & 0b111) { 3281 case 0: op = rv_op_fsgnj_s; break; 3282 case 1: op = rv_op_fsgnjn_s; break; 3283 case 2: op = rv_op_fsgnjx_s; break; 3284 } 3285 break; 3286 case 17: 3287 switch ((inst >> 12) & 0b111) { 3288 case 0: op = rv_op_fsgnj_d; break; 3289 case 1: op = rv_op_fsgnjn_d; break; 3290 case 2: op = rv_op_fsgnjx_d; break; 3291 } 3292 break; 3293 case 19: 3294 switch ((inst >> 12) & 0b111) { 3295 case 0: op = rv_op_fsgnj_q; break; 3296 case 1: op = rv_op_fsgnjn_q; break; 3297 case 2: op = rv_op_fsgnjx_q; break; 3298 } 3299 break; 3300 case 20: 3301 switch ((inst >> 12) & 0b111) { 3302 case 0: op = rv_op_fmin_s; break; 3303 case 1: op = rv_op_fmax_s; break; 3304 case 2: op = rv_op_fminm_s; break; 3305 case 3: op = rv_op_fmaxm_s; break; 3306 } 3307 break; 3308 case 21: 3309 switch ((inst >> 12) & 0b111) { 3310 case 0: op = rv_op_fmin_d; break; 3311 case 1: op = rv_op_fmax_d; break; 3312 case 2: op = rv_op_fminm_d; break; 3313 case 3: op = rv_op_fmaxm_d; break; 3314 } 3315 break; 3316 case 22: 3317 switch (((inst >> 12) & 0b111)) { 3318 case 2: op = rv_op_fminm_h; break; 3319 case 3: op = rv_op_fmaxm_h; break; 3320 } 3321 break; 3322 case 23: 3323 switch ((inst >> 12) & 0b111) { 3324 case 0: op = rv_op_fmin_q; break; 3325 case 1: op = rv_op_fmax_q; break; 3326 case 2: op = rv_op_fminm_q; break; 3327 case 3: op = rv_op_fmaxm_q; break; 3328 } 3329 break; 3330 case 32: 3331 switch ((inst >> 20) & 0b11111) { 3332 case 1: op = rv_op_fcvt_s_d; break; 3333 case 3: op = rv_op_fcvt_s_q; break; 3334 case 4: op = rv_op_fround_s; break; 3335 case 5: op = rv_op_froundnx_s; break; 3336 case 6: op = rv_op_fcvt_s_bf16; break; 3337 } 3338 break; 3339 case 33: 3340 switch ((inst >> 20) & 0b11111) { 3341 case 0: op = rv_op_fcvt_d_s; break; 3342 case 3: op = rv_op_fcvt_d_q; break; 3343 case 4: op = rv_op_fround_d; break; 3344 case 5: op = rv_op_froundnx_d; break; 3345 } 3346 break; 3347 case 34: 3348 switch (((inst >> 20) & 0b11111)) { 3349 case 4: op = rv_op_fround_h; break; 3350 case 5: op = rv_op_froundnx_h; break; 3351 case 8: op = rv_op_fcvt_bf16_s; break; 3352 } 3353 break; 3354 case 35: 3355 switch ((inst >> 20) & 0b11111) { 3356 case 0: op = rv_op_fcvt_q_s; break; 3357 case 1: op = rv_op_fcvt_q_d; break; 3358 case 4: op = rv_op_fround_q; break; 3359 case 5: op = rv_op_froundnx_q; break; 3360 } 3361 break; 3362 case 44: 3363 switch ((inst >> 20) & 0b11111) { 3364 case 0: op = rv_op_fsqrt_s; break; 3365 } 3366 break; 3367 case 45: 3368 switch ((inst >> 20) & 0b11111) { 3369 case 0: op = rv_op_fsqrt_d; break; 3370 } 3371 break; 3372 case 47: 3373 switch ((inst >> 20) & 0b11111) { 3374 case 0: op = rv_op_fsqrt_q; break; 3375 } 3376 break; 3377 case 80: 3378 switch ((inst >> 12) & 0b111) { 3379 case 0: op = rv_op_fle_s; break; 3380 case 1: op = rv_op_flt_s; break; 3381 case 2: op = rv_op_feq_s; break; 3382 case 4: op = rv_op_fleq_s; break; 3383 case 5: op = rv_op_fltq_s; break; 3384 } 3385 break; 3386 case 81: 3387 switch ((inst >> 12) & 0b111) { 3388 case 0: op = rv_op_fle_d; break; 3389 case 1: op = rv_op_flt_d; break; 3390 case 2: op = rv_op_feq_d; break; 3391 case 4: op = rv_op_fleq_d; break; 3392 case 5: op = rv_op_fltq_d; break; 3393 } 3394 break; 3395 case 82: 3396 switch (((inst >> 12) & 0b111)) { 3397 case 4: op = rv_op_fleq_h; break; 3398 case 5: op = rv_op_fltq_h; break; 3399 } 3400 break; 3401 case 83: 3402 switch ((inst >> 12) & 0b111) { 3403 case 0: op = rv_op_fle_q; break; 3404 case 1: op = rv_op_flt_q; break; 3405 case 2: op = rv_op_feq_q; break; 3406 case 4: op = rv_op_fleq_q; break; 3407 case 5: op = rv_op_fltq_q; break; 3408 } 3409 break; 3410 case 89: 3411 switch (((inst >> 12) & 0b111)) { 3412 case 0: op = rv_op_fmvp_d_x; break; 3413 } 3414 break; 3415 case 91: 3416 switch (((inst >> 12) & 0b111)) { 3417 case 0: op = rv_op_fmvp_q_x; break; 3418 } 3419 break; 3420 case 96: 3421 switch ((inst >> 20) & 0b11111) { 3422 case 0: op = rv_op_fcvt_w_s; break; 3423 case 1: op = rv_op_fcvt_wu_s; break; 3424 case 2: op = rv_op_fcvt_l_s; break; 3425 case 3: op = rv_op_fcvt_lu_s; break; 3426 } 3427 break; 3428 case 97: 3429 switch ((inst >> 20) & 0b11111) { 3430 case 0: op = rv_op_fcvt_w_d; break; 3431 case 1: op = rv_op_fcvt_wu_d; break; 3432 case 2: op = rv_op_fcvt_l_d; break; 3433 case 3: op = rv_op_fcvt_lu_d; break; 3434 case 8: op = rv_op_fcvtmod_w_d; break; 3435 } 3436 break; 3437 case 99: 3438 switch ((inst >> 20) & 0b11111) { 3439 case 0: op = rv_op_fcvt_w_q; break; 3440 case 1: op = rv_op_fcvt_wu_q; break; 3441 case 2: op = rv_op_fcvt_l_q; break; 3442 case 3: op = rv_op_fcvt_lu_q; break; 3443 } 3444 break; 3445 case 104: 3446 switch ((inst >> 20) & 0b11111) { 3447 case 0: op = rv_op_fcvt_s_w; break; 3448 case 1: op = rv_op_fcvt_s_wu; break; 3449 case 2: op = rv_op_fcvt_s_l; break; 3450 case 3: op = rv_op_fcvt_s_lu; break; 3451 } 3452 break; 3453 case 105: 3454 switch ((inst >> 20) & 0b11111) { 3455 case 0: op = rv_op_fcvt_d_w; break; 3456 case 1: op = rv_op_fcvt_d_wu; break; 3457 case 2: op = rv_op_fcvt_d_l; break; 3458 case 3: op = rv_op_fcvt_d_lu; break; 3459 } 3460 break; 3461 case 107: 3462 switch ((inst >> 20) & 0b11111) { 3463 case 0: op = rv_op_fcvt_q_w; break; 3464 case 1: op = rv_op_fcvt_q_wu; break; 3465 case 2: op = rv_op_fcvt_q_l; break; 3466 case 3: op = rv_op_fcvt_q_lu; break; 3467 } 3468 break; 3469 case 112: 3470 switch (((inst >> 17) & 0b11111000) | 3471 ((inst >> 12) & 0b00000111)) { 3472 case 0: op = rv_op_fmv_x_s; break; 3473 case 1: op = rv_op_fclass_s; break; 3474 } 3475 break; 3476 case 113: 3477 switch (((inst >> 17) & 0b11111000) | 3478 ((inst >> 12) & 0b00000111)) { 3479 case 0: op = rv_op_fmv_x_d; break; 3480 case 1: op = rv_op_fclass_d; break; 3481 case 8: op = rv_op_fmvh_x_d; break; 3482 } 3483 break; 3484 case 114: 3485 switch (((inst >> 17) & 0b11111000) | 3486 ((inst >> 12) & 0b00000111)) { 3487 case 0: op = rv_op_fmv_x_h; break; 3488 } 3489 break; 3490 case 115: 3491 switch (((inst >> 17) & 0b11111000) | 3492 ((inst >> 12) & 0b00000111)) { 3493 case 0: op = rv_op_fmv_x_q; break; 3494 case 1: op = rv_op_fclass_q; break; 3495 case 8: op = rv_op_fmvh_x_q; break; 3496 } 3497 break; 3498 case 120: 3499 switch (((inst >> 17) & 0b11111000) | 3500 ((inst >> 12) & 0b00000111)) { 3501 case 0: op = rv_op_fmv_s_x; break; 3502 case 8: op = rv_op_fli_s; break; 3503 } 3504 break; 3505 case 121: 3506 switch (((inst >> 17) & 0b11111000) | 3507 ((inst >> 12) & 0b00000111)) { 3508 case 0: op = rv_op_fmv_d_x; break; 3509 case 8: op = rv_op_fli_d; break; 3510 } 3511 break; 3512 case 122: 3513 switch (((inst >> 17) & 0b11111000) | 3514 ((inst >> 12) & 0b00000111)) { 3515 case 0: op = rv_op_fmv_h_x; break; 3516 case 8: op = rv_op_fli_h; break; 3517 } 3518 break; 3519 case 123: 3520 switch (((inst >> 17) & 0b11111000) | 3521 ((inst >> 12) & 0b00000111)) { 3522 case 0: op = rv_op_fmv_q_x; break; 3523 case 8: op = rv_op_fli_q; break; 3524 } 3525 break; 3526 } 3527 break; 3528 case 21: 3529 switch ((inst >> 12) & 0b111) { 3530 case 0: 3531 switch ((inst >> 26) & 0b111111) { 3532 case 0: op = rv_op_vadd_vv; break; 3533 case 1: op = rv_op_vandn_vv; break; 3534 case 2: op = rv_op_vsub_vv; break; 3535 case 4: op = rv_op_vminu_vv; break; 3536 case 5: op = rv_op_vmin_vv; break; 3537 case 6: op = rv_op_vmaxu_vv; break; 3538 case 7: op = rv_op_vmax_vv; break; 3539 case 9: op = rv_op_vand_vv; break; 3540 case 10: op = rv_op_vor_vv; break; 3541 case 11: op = rv_op_vxor_vv; break; 3542 case 12: op = rv_op_vrgather_vv; break; 3543 case 14: op = rv_op_vrgatherei16_vv; break; 3544 case 16: 3545 if (((inst >> 25) & 1) == 0) { 3546 op = rv_op_vadc_vvm; 3547 } 3548 break; 3549 case 17: op = rv_op_vmadc_vvm; break; 3550 case 18: 3551 if (((inst >> 25) & 1) == 0) { 3552 op = rv_op_vsbc_vvm; 3553 } 3554 break; 3555 case 19: op = rv_op_vmsbc_vvm; break; 3556 case 20: op = rv_op_vror_vv; break; 3557 case 21: op = rv_op_vrol_vv; break; 3558 case 23: 3559 if (((inst >> 20) & 0b111111) == 32) 3560 op = rv_op_vmv_v_v; 3561 else if (((inst >> 25) & 1) == 0) 3562 op = rv_op_vmerge_vvm; 3563 break; 3564 case 24: op = rv_op_vmseq_vv; break; 3565 case 25: op = rv_op_vmsne_vv; break; 3566 case 26: op = rv_op_vmsltu_vv; break; 3567 case 27: op = rv_op_vmslt_vv; break; 3568 case 28: op = rv_op_vmsleu_vv; break; 3569 case 29: op = rv_op_vmsle_vv; break; 3570 case 32: op = rv_op_vsaddu_vv; break; 3571 case 33: op = rv_op_vsadd_vv; break; 3572 case 34: op = rv_op_vssubu_vv; break; 3573 case 35: op = rv_op_vssub_vv; break; 3574 case 37: op = rv_op_vsll_vv; break; 3575 case 39: op = rv_op_vsmul_vv; break; 3576 case 40: op = rv_op_vsrl_vv; break; 3577 case 41: op = rv_op_vsra_vv; break; 3578 case 42: op = rv_op_vssrl_vv; break; 3579 case 43: op = rv_op_vssra_vv; break; 3580 case 44: op = rv_op_vnsrl_wv; break; 3581 case 45: op = rv_op_vnsra_wv; break; 3582 case 46: op = rv_op_vnclipu_wv; break; 3583 case 47: op = rv_op_vnclip_wv; break; 3584 case 48: op = rv_op_vwredsumu_vs; break; 3585 case 49: op = rv_op_vwredsum_vs; break; 3586 case 53: op = rv_op_vwsll_vv; break; 3587 } 3588 break; 3589 case 1: 3590 switch ((inst >> 26) & 0b111111) { 3591 case 0: op = rv_op_vfadd_vv; break; 3592 case 1: op = rv_op_vfredusum_vs; break; 3593 case 2: op = rv_op_vfsub_vv; break; 3594 case 3: op = rv_op_vfredosum_vs; break; 3595 case 4: op = rv_op_vfmin_vv; break; 3596 case 5: op = rv_op_vfredmin_vs; break; 3597 case 6: op = rv_op_vfmax_vv; break; 3598 case 7: op = rv_op_vfredmax_vs; break; 3599 case 8: op = rv_op_vfsgnj_vv; break; 3600 case 9: op = rv_op_vfsgnjn_vv; break; 3601 case 10: op = rv_op_vfsgnjx_vv; break; 3602 case 16: 3603 switch ((inst >> 15) & 0b11111) { 3604 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break; 3605 } 3606 break; 3607 case 18: 3608 switch ((inst >> 15) & 0b11111) { 3609 case 0: op = rv_op_vfcvt_xu_f_v; break; 3610 case 1: op = rv_op_vfcvt_x_f_v; break; 3611 case 2: op = rv_op_vfcvt_f_xu_v; break; 3612 case 3: op = rv_op_vfcvt_f_x_v; break; 3613 case 6: op = rv_op_vfcvt_rtz_xu_f_v; break; 3614 case 7: op = rv_op_vfcvt_rtz_x_f_v; break; 3615 case 8: op = rv_op_vfwcvt_xu_f_v; break; 3616 case 9: op = rv_op_vfwcvt_x_f_v; break; 3617 case 10: op = rv_op_vfwcvt_f_xu_v; break; 3618 case 11: op = rv_op_vfwcvt_f_x_v; break; 3619 case 12: op = rv_op_vfwcvt_f_f_v; break; 3620 case 13: op = rv_op_vfwcvtbf16_f_f_v; break; 3621 case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break; 3622 case 15: op = rv_op_vfwcvt_rtz_x_f_v; break; 3623 case 16: op = rv_op_vfncvt_xu_f_w; break; 3624 case 17: op = rv_op_vfncvt_x_f_w; break; 3625 case 18: op = rv_op_vfncvt_f_xu_w; break; 3626 case 19: op = rv_op_vfncvt_f_x_w; break; 3627 case 20: op = rv_op_vfncvt_f_f_w; break; 3628 case 21: op = rv_op_vfncvt_rod_f_f_w; break; 3629 case 22: op = rv_op_vfncvt_rtz_xu_f_w; break; 3630 case 23: op = rv_op_vfncvt_rtz_x_f_w; break; 3631 case 29: op = rv_op_vfncvtbf16_f_f_w; break; 3632 } 3633 break; 3634 case 19: 3635 switch ((inst >> 15) & 0b11111) { 3636 case 0: op = rv_op_vfsqrt_v; break; 3637 case 4: op = rv_op_vfrsqrt7_v; break; 3638 case 5: op = rv_op_vfrec7_v; break; 3639 case 16: op = rv_op_vfclass_v; break; 3640 } 3641 break; 3642 case 24: op = rv_op_vmfeq_vv; break; 3643 case 25: op = rv_op_vmfle_vv; break; 3644 case 27: op = rv_op_vmflt_vv; break; 3645 case 28: op = rv_op_vmfne_vv; break; 3646 case 32: op = rv_op_vfdiv_vv; break; 3647 case 36: op = rv_op_vfmul_vv; break; 3648 case 40: op = rv_op_vfmadd_vv; break; 3649 case 41: op = rv_op_vfnmadd_vv; break; 3650 case 42: op = rv_op_vfmsub_vv; break; 3651 case 43: op = rv_op_vfnmsub_vv; break; 3652 case 44: op = rv_op_vfmacc_vv; break; 3653 case 45: op = rv_op_vfnmacc_vv; break; 3654 case 46: op = rv_op_vfmsac_vv; break; 3655 case 47: op = rv_op_vfnmsac_vv; break; 3656 case 48: op = rv_op_vfwadd_vv; break; 3657 case 49: op = rv_op_vfwredusum_vs; break; 3658 case 50: op = rv_op_vfwsub_vv; break; 3659 case 51: op = rv_op_vfwredosum_vs; break; 3660 case 52: op = rv_op_vfwadd_wv; break; 3661 case 54: op = rv_op_vfwsub_wv; break; 3662 case 56: op = rv_op_vfwmul_vv; break; 3663 case 59: op = rv_op_vfwmaccbf16_vv; break; 3664 case 60: op = rv_op_vfwmacc_vv; break; 3665 case 61: op = rv_op_vfwnmacc_vv; break; 3666 case 62: op = rv_op_vfwmsac_vv; break; 3667 case 63: op = rv_op_vfwnmsac_vv; break; 3668 } 3669 break; 3670 case 2: 3671 switch ((inst >> 26) & 0b111111) { 3672 case 0: op = rv_op_vredsum_vs; break; 3673 case 1: op = rv_op_vredand_vs; break; 3674 case 2: op = rv_op_vredor_vs; break; 3675 case 3: op = rv_op_vredxor_vs; break; 3676 case 4: op = rv_op_vredminu_vs; break; 3677 case 5: op = rv_op_vredmin_vs; break; 3678 case 6: op = rv_op_vredmaxu_vs; break; 3679 case 7: op = rv_op_vredmax_vs; break; 3680 case 8: op = rv_op_vaaddu_vv; break; 3681 case 9: op = rv_op_vaadd_vv; break; 3682 case 10: op = rv_op_vasubu_vv; break; 3683 case 11: op = rv_op_vasub_vv; break; 3684 case 12: op = rv_op_vclmul_vv; break; 3685 case 13: op = rv_op_vclmulh_vv; break; 3686 case 16: 3687 switch ((inst >> 15) & 0b11111) { 3688 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break; 3689 case 16: op = rv_op_vcpop_m; break; 3690 case 17: op = rv_op_vfirst_m; break; 3691 } 3692 break; 3693 case 18: 3694 switch ((inst >> 15) & 0b11111) { 3695 case 2: op = rv_op_vzext_vf8; break; 3696 case 3: op = rv_op_vsext_vf8; break; 3697 case 4: op = rv_op_vzext_vf4; break; 3698 case 5: op = rv_op_vsext_vf4; break; 3699 case 6: op = rv_op_vzext_vf2; break; 3700 case 7: op = rv_op_vsext_vf2; break; 3701 case 8: op = rv_op_vbrev8_v; break; 3702 case 9: op = rv_op_vrev8_v; break; 3703 case 10: op = rv_op_vbrev_v; break; 3704 case 12: op = rv_op_vclz_v; break; 3705 case 13: op = rv_op_vctz_v; break; 3706 case 14: op = rv_op_vcpop_v; break; 3707 } 3708 break; 3709 case 20: 3710 switch ((inst >> 15) & 0b11111) { 3711 case 1: op = rv_op_vmsbf_m; break; 3712 case 2: op = rv_op_vmsof_m; break; 3713 case 3: op = rv_op_vmsif_m; break; 3714 case 16: op = rv_op_viota_m; break; 3715 case 17: 3716 if (((inst >> 20) & 0b11111) == 0) { 3717 op = rv_op_vid_v; 3718 } 3719 break; 3720 } 3721 break; 3722 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break; 3723 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break; 3724 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break; 3725 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break; 3726 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break; 3727 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break; 3728 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break; 3729 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break; 3730 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break; 3731 case 32: op = rv_op_vdivu_vv; break; 3732 case 33: op = rv_op_vdiv_vv; break; 3733 case 34: op = rv_op_vremu_vv; break; 3734 case 35: op = rv_op_vrem_vv; break; 3735 case 36: op = rv_op_vmulhu_vv; break; 3736 case 37: op = rv_op_vmul_vv; break; 3737 case 38: op = rv_op_vmulhsu_vv; break; 3738 case 39: op = rv_op_vmulh_vv; break; 3739 case 41: op = rv_op_vmadd_vv; break; 3740 case 43: op = rv_op_vnmsub_vv; break; 3741 case 45: op = rv_op_vmacc_vv; break; 3742 case 47: op = rv_op_vnmsac_vv; break; 3743 case 48: op = rv_op_vwaddu_vv; break; 3744 case 49: op = rv_op_vwadd_vv; break; 3745 case 50: op = rv_op_vwsubu_vv; break; 3746 case 51: op = rv_op_vwsub_vv; break; 3747 case 52: op = rv_op_vwaddu_wv; break; 3748 case 53: op = rv_op_vwadd_wv; break; 3749 case 54: op = rv_op_vwsubu_wv; break; 3750 case 55: op = rv_op_vwsub_wv; break; 3751 case 56: op = rv_op_vwmulu_vv; break; 3752 case 58: op = rv_op_vwmulsu_vv; break; 3753 case 59: op = rv_op_vwmul_vv; break; 3754 case 60: op = rv_op_vwmaccu_vv; break; 3755 case 61: op = rv_op_vwmacc_vv; break; 3756 case 63: op = rv_op_vwmaccsu_vv; break; 3757 } 3758 break; 3759 case 3: 3760 switch ((inst >> 26) & 0b111111) { 3761 case 0: op = rv_op_vadd_vi; break; 3762 case 3: op = rv_op_vrsub_vi; break; 3763 case 9: op = rv_op_vand_vi; break; 3764 case 10: op = rv_op_vor_vi; break; 3765 case 11: op = rv_op_vxor_vi; break; 3766 case 12: op = rv_op_vrgather_vi; break; 3767 case 14: op = rv_op_vslideup_vi; break; 3768 case 15: op = rv_op_vslidedown_vi; break; 3769 case 16: 3770 if (((inst >> 25) & 1) == 0) { 3771 op = rv_op_vadc_vim; 3772 } 3773 break; 3774 case 17: op = rv_op_vmadc_vim; break; 3775 case 20: case 21: op = rv_op_vror_vi; break; 3776 case 23: 3777 if (((inst >> 20) & 0b111111) == 32) 3778 op = rv_op_vmv_v_i; 3779 else if (((inst >> 25) & 1) == 0) 3780 op = rv_op_vmerge_vim; 3781 break; 3782 case 24: op = rv_op_vmseq_vi; break; 3783 case 25: op = rv_op_vmsne_vi; break; 3784 case 28: op = rv_op_vmsleu_vi; break; 3785 case 29: op = rv_op_vmsle_vi; break; 3786 case 30: op = rv_op_vmsgtu_vi; break; 3787 case 31: op = rv_op_vmsgt_vi; break; 3788 case 32: op = rv_op_vsaddu_vi; break; 3789 case 33: op = rv_op_vsadd_vi; break; 3790 case 37: op = rv_op_vsll_vi; break; 3791 case 39: 3792 switch ((inst >> 15) & 0b11111) { 3793 case 0: op = rv_op_vmv1r_v; break; 3794 case 1: op = rv_op_vmv2r_v; break; 3795 case 3: op = rv_op_vmv4r_v; break; 3796 case 7: op = rv_op_vmv8r_v; break; 3797 } 3798 break; 3799 case 40: op = rv_op_vsrl_vi; break; 3800 case 41: op = rv_op_vsra_vi; break; 3801 case 42: op = rv_op_vssrl_vi; break; 3802 case 43: op = rv_op_vssra_vi; break; 3803 case 44: op = rv_op_vnsrl_wi; break; 3804 case 45: op = rv_op_vnsra_wi; break; 3805 case 46: op = rv_op_vnclipu_wi; break; 3806 case 47: op = rv_op_vnclip_wi; break; 3807 case 53: op = rv_op_vwsll_vi; break; 3808 } 3809 break; 3810 case 4: 3811 switch ((inst >> 26) & 0b111111) { 3812 case 0: op = rv_op_vadd_vx; break; 3813 case 1: op = rv_op_vandn_vx; break; 3814 case 2: op = rv_op_vsub_vx; break; 3815 case 3: op = rv_op_vrsub_vx; break; 3816 case 4: op = rv_op_vminu_vx; break; 3817 case 5: op = rv_op_vmin_vx; break; 3818 case 6: op = rv_op_vmaxu_vx; break; 3819 case 7: op = rv_op_vmax_vx; break; 3820 case 9: op = rv_op_vand_vx; break; 3821 case 10: op = rv_op_vor_vx; break; 3822 case 11: op = rv_op_vxor_vx; break; 3823 case 12: op = rv_op_vrgather_vx; break; 3824 case 14: op = rv_op_vslideup_vx; break; 3825 case 15: op = rv_op_vslidedown_vx; break; 3826 case 16: 3827 if (((inst >> 25) & 1) == 0) { 3828 op = rv_op_vadc_vxm; 3829 } 3830 break; 3831 case 17: op = rv_op_vmadc_vxm; break; 3832 case 18: 3833 if (((inst >> 25) & 1) == 0) { 3834 op = rv_op_vsbc_vxm; 3835 } 3836 break; 3837 case 19: op = rv_op_vmsbc_vxm; break; 3838 case 20: op = rv_op_vror_vx; break; 3839 case 21: op = rv_op_vrol_vx; break; 3840 case 23: 3841 if (((inst >> 20) & 0b111111) == 32) 3842 op = rv_op_vmv_v_x; 3843 else if (((inst >> 25) & 1) == 0) 3844 op = rv_op_vmerge_vxm; 3845 break; 3846 case 24: op = rv_op_vmseq_vx; break; 3847 case 25: op = rv_op_vmsne_vx; break; 3848 case 26: op = rv_op_vmsltu_vx; break; 3849 case 27: op = rv_op_vmslt_vx; break; 3850 case 28: op = rv_op_vmsleu_vx; break; 3851 case 29: op = rv_op_vmsle_vx; break; 3852 case 30: op = rv_op_vmsgtu_vx; break; 3853 case 31: op = rv_op_vmsgt_vx; break; 3854 case 32: op = rv_op_vsaddu_vx; break; 3855 case 33: op = rv_op_vsadd_vx; break; 3856 case 34: op = rv_op_vssubu_vx; break; 3857 case 35: op = rv_op_vssub_vx; break; 3858 case 37: op = rv_op_vsll_vx; break; 3859 case 39: op = rv_op_vsmul_vx; break; 3860 case 40: op = rv_op_vsrl_vx; break; 3861 case 41: op = rv_op_vsra_vx; break; 3862 case 42: op = rv_op_vssrl_vx; break; 3863 case 43: op = rv_op_vssra_vx; break; 3864 case 44: op = rv_op_vnsrl_wx; break; 3865 case 45: op = rv_op_vnsra_wx; break; 3866 case 46: op = rv_op_vnclipu_wx; break; 3867 case 47: op = rv_op_vnclip_wx; break; 3868 case 53: op = rv_op_vwsll_vx; break; 3869 } 3870 break; 3871 case 5: 3872 switch ((inst >> 26) & 0b111111) { 3873 case 0: op = rv_op_vfadd_vf; break; 3874 case 2: op = rv_op_vfsub_vf; break; 3875 case 4: op = rv_op_vfmin_vf; break; 3876 case 6: op = rv_op_vfmax_vf; break; 3877 case 8: op = rv_op_vfsgnj_vf; break; 3878 case 9: op = rv_op_vfsgnjn_vf; break; 3879 case 10: op = rv_op_vfsgnjx_vf; break; 3880 case 14: op = rv_op_vfslide1up_vf; break; 3881 case 15: op = rv_op_vfslide1down_vf; break; 3882 case 16: 3883 switch ((inst >> 20) & 0b11111) { 3884 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break; 3885 } 3886 break; 3887 case 23: 3888 if (((inst >> 25) & 1) == 0) 3889 op = rv_op_vfmerge_vfm; 3890 else if (((inst >> 20) & 0b111111) == 32) 3891 op = rv_op_vfmv_v_f; 3892 break; 3893 case 24: op = rv_op_vmfeq_vf; break; 3894 case 25: op = rv_op_vmfle_vf; break; 3895 case 27: op = rv_op_vmflt_vf; break; 3896 case 28: op = rv_op_vmfne_vf; break; 3897 case 29: op = rv_op_vmfgt_vf; break; 3898 case 31: op = rv_op_vmfge_vf; break; 3899 case 32: op = rv_op_vfdiv_vf; break; 3900 case 33: op = rv_op_vfrdiv_vf; break; 3901 case 36: op = rv_op_vfmul_vf; break; 3902 case 39: op = rv_op_vfrsub_vf; break; 3903 case 40: op = rv_op_vfmadd_vf; break; 3904 case 41: op = rv_op_vfnmadd_vf; break; 3905 case 42: op = rv_op_vfmsub_vf; break; 3906 case 43: op = rv_op_vfnmsub_vf; break; 3907 case 44: op = rv_op_vfmacc_vf; break; 3908 case 45: op = rv_op_vfnmacc_vf; break; 3909 case 46: op = rv_op_vfmsac_vf; break; 3910 case 47: op = rv_op_vfnmsac_vf; break; 3911 case 48: op = rv_op_vfwadd_vf; break; 3912 case 50: op = rv_op_vfwsub_vf; break; 3913 case 52: op = rv_op_vfwadd_wf; break; 3914 case 54: op = rv_op_vfwsub_wf; break; 3915 case 56: op = rv_op_vfwmul_vf; break; 3916 case 59: op = rv_op_vfwmaccbf16_vf; break; 3917 case 60: op = rv_op_vfwmacc_vf; break; 3918 case 61: op = rv_op_vfwnmacc_vf; break; 3919 case 62: op = rv_op_vfwmsac_vf; break; 3920 case 63: op = rv_op_vfwnmsac_vf; break; 3921 } 3922 break; 3923 case 6: 3924 switch ((inst >> 26) & 0b111111) { 3925 case 8: op = rv_op_vaaddu_vx; break; 3926 case 9: op = rv_op_vaadd_vx; break; 3927 case 10: op = rv_op_vasubu_vx; break; 3928 case 11: op = rv_op_vasub_vx; break; 3929 case 12: op = rv_op_vclmul_vx; break; 3930 case 13: op = rv_op_vclmulh_vx; break; 3931 case 14: op = rv_op_vslide1up_vx; break; 3932 case 15: op = rv_op_vslide1down_vx; break; 3933 case 16: 3934 switch ((inst >> 20) & 0b11111) { 3935 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break; 3936 } 3937 break; 3938 case 32: op = rv_op_vdivu_vx; break; 3939 case 33: op = rv_op_vdiv_vx; break; 3940 case 34: op = rv_op_vremu_vx; break; 3941 case 35: op = rv_op_vrem_vx; break; 3942 case 36: op = rv_op_vmulhu_vx; break; 3943 case 37: op = rv_op_vmul_vx; break; 3944 case 38: op = rv_op_vmulhsu_vx; break; 3945 case 39: op = rv_op_vmulh_vx; break; 3946 case 41: op = rv_op_vmadd_vx; break; 3947 case 43: op = rv_op_vnmsub_vx; break; 3948 case 45: op = rv_op_vmacc_vx; break; 3949 case 47: op = rv_op_vnmsac_vx; break; 3950 case 48: op = rv_op_vwaddu_vx; break; 3951 case 49: op = rv_op_vwadd_vx; break; 3952 case 50: op = rv_op_vwsubu_vx; break; 3953 case 51: op = rv_op_vwsub_vx; break; 3954 case 52: op = rv_op_vwaddu_wx; break; 3955 case 53: op = rv_op_vwadd_wx; break; 3956 case 54: op = rv_op_vwsubu_wx; break; 3957 case 55: op = rv_op_vwsub_wx; break; 3958 case 56: op = rv_op_vwmulu_vx; break; 3959 case 58: op = rv_op_vwmulsu_vx; break; 3960 case 59: op = rv_op_vwmul_vx; break; 3961 case 60: op = rv_op_vwmaccu_vx; break; 3962 case 61: op = rv_op_vwmacc_vx; break; 3963 case 62: op = rv_op_vwmaccus_vx; break; 3964 case 63: op = rv_op_vwmaccsu_vx; break; 3965 } 3966 break; 3967 case 7: 3968 if (((inst >> 31) & 1) == 0) { 3969 op = rv_op_vsetvli; 3970 } else if ((inst >> 30) & 1) { 3971 op = rv_op_vsetivli; 3972 } else if (((inst >> 25) & 0b11111) == 0) { 3973 op = rv_op_vsetvl; 3974 } 3975 break; 3976 } 3977 break; 3978 case 22: 3979 switch ((inst >> 12) & 0b111) { 3980 case 0: op = rv_op_addid; break; 3981 case 1: 3982 switch ((inst >> 26) & 0b111111) { 3983 case 0: op = rv_op_sllid; break; 3984 } 3985 break; 3986 case 5: 3987 switch ((inst >> 26) & 0b111111) { 3988 case 0: op = rv_op_srlid; break; 3989 case 16: op = rv_op_sraid; break; 3990 } 3991 break; 3992 } 3993 break; 3994 case 24: 3995 switch ((inst >> 12) & 0b111) { 3996 case 0: op = rv_op_beq; break; 3997 case 1: op = rv_op_bne; break; 3998 case 4: op = rv_op_blt; break; 3999 case 5: op = rv_op_bge; break; 4000 case 6: op = rv_op_bltu; break; 4001 case 7: op = rv_op_bgeu; break; 4002 } 4003 break; 4004 case 25: 4005 switch ((inst >> 12) & 0b111) { 4006 case 0: op = rv_op_jalr; break; 4007 } 4008 break; 4009 case 27: op = rv_op_jal; break; 4010 case 28: 4011 switch ((inst >> 12) & 0b111) { 4012 case 0: 4013 switch (((inst >> 20) & 0b111111100000) | 4014 ((inst >> 7) & 0b000000011111)) { 4015 case 0: 4016 switch ((inst >> 15) & 0b1111111111) { 4017 case 0: op = rv_op_ecall; break; 4018 case 32: op = rv_op_ebreak; break; 4019 case 64: op = rv_op_uret; break; 4020 case 416: op = rv_op_wrs_nto; break; 4021 case 928: op = rv_op_wrs_sto; break; 4022 } 4023 break; 4024 case 256: 4025 switch ((inst >> 20) & 0b11111) { 4026 case 2: 4027 switch ((inst >> 15) & 0b11111) { 4028 case 0: op = rv_op_sret; break; 4029 } 4030 break; 4031 case 4: op = rv_op_sfence_vm; break; 4032 case 5: 4033 switch ((inst >> 15) & 0b11111) { 4034 case 0: op = rv_op_wfi; break; 4035 } 4036 break; 4037 } 4038 break; 4039 case 288: op = rv_op_sfence_vma; break; 4040 case 512: 4041 switch ((inst >> 15) & 0b1111111111) { 4042 case 64: op = rv_op_hret; break; 4043 } 4044 break; 4045 case 768: 4046 switch ((inst >> 15) & 0b1111111111) { 4047 case 64: op = rv_op_mret; break; 4048 } 4049 break; 4050 case 1952: 4051 switch ((inst >> 15) & 0b1111111111) { 4052 case 576: op = rv_op_dret; break; 4053 } 4054 break; 4055 } 4056 break; 4057 case 1: op = rv_op_csrrw; break; 4058 case 2: op = rv_op_csrrs; break; 4059 case 3: op = rv_op_csrrc; break; 4060 case 4: 4061 if (dec->cfg->ext_zimop) { 4062 int imm_mop5, imm_mop3, reg_num; 4063 if ((extract32(inst, 22, 10) & 0b1011001111) 4064 == 0b1000000111) { 4065 imm_mop5 = deposit32(deposit32(extract32(inst, 20, 2), 4066 2, 2, 4067 extract32(inst, 26, 2)), 4068 4, 1, extract32(inst, 30, 1)); 4069 op = rv_mop_r_0 + imm_mop5; 4070 /* if zicfiss enabled and mop5 is shadow stack */ 4071 if (dec->cfg->ext_zicfiss && 4072 ((imm_mop5 & 0b11100) == 0b11100)) { 4073 /* rs1=0 means ssrdp */ 4074 if ((inst & (0b011111 << 15)) == 0) { 4075 op = rv_op_ssrdp; 4076 } 4077 /* rd=0 means sspopchk */ 4078 reg_num = (inst >> 15) & 0b011111; 4079 if (((inst & (0b011111 << 7)) == 0) && 4080 ((reg_num == 1) || (reg_num == 5))) { 4081 op = rv_op_sspopchk; 4082 } 4083 } 4084 } else if ((extract32(inst, 25, 7) & 0b1011001) 4085 == 0b1000001) { 4086 imm_mop3 = deposit32(extract32(inst, 26, 2), 4087 2, 1, extract32(inst, 30, 1)); 4088 op = rv_mop_rr_0 + imm_mop3; 4089 /* if zicfiss enabled and mop3 is shadow stack */ 4090 if (dec->cfg->ext_zicfiss && 4091 ((imm_mop3 & 0b111) == 0b111)) { 4092 /* rs1=0 and rd=0 means sspush */ 4093 reg_num = (inst >> 20) & 0b011111; 4094 if (((inst & (0b011111 << 15)) == 0) && 4095 ((inst & (0b011111 << 7)) == 0) && 4096 ((reg_num == 1) || (reg_num == 5))) { 4097 op = rv_op_sspush; 4098 } 4099 } 4100 } 4101 } 4102 break; 4103 case 5: op = rv_op_csrrwi; break; 4104 case 6: op = rv_op_csrrsi; break; 4105 case 7: op = rv_op_csrrci; break; 4106 } 4107 break; 4108 case 29: 4109 if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) { 4110 switch ((inst >> 26) & 0b111111) { 4111 case 32: op = rv_op_vsm3me_vv; break; 4112 case 33: op = rv_op_vsm4k_vi; break; 4113 case 34: op = rv_op_vaeskf1_vi; break; 4114 case 40: 4115 switch ((inst >> 15) & 0b11111) { 4116 case 0: op = rv_op_vaesdm_vv; break; 4117 case 1: op = rv_op_vaesdf_vv; break; 4118 case 2: op = rv_op_vaesem_vv; break; 4119 case 3: op = rv_op_vaesef_vv; break; 4120 case 16: op = rv_op_vsm4r_vv; break; 4121 case 17: op = rv_op_vgmul_vv; break; 4122 } 4123 break; 4124 case 41: 4125 switch ((inst >> 15) & 0b11111) { 4126 case 0: op = rv_op_vaesdm_vs; break; 4127 case 1: op = rv_op_vaesdf_vs; break; 4128 case 2: op = rv_op_vaesem_vs; break; 4129 case 3: op = rv_op_vaesef_vs; break; 4130 case 7: op = rv_op_vaesz_vs; break; 4131 case 16: op = rv_op_vsm4r_vs; break; 4132 } 4133 break; 4134 case 42: op = rv_op_vaeskf2_vi; break; 4135 case 43: op = rv_op_vsm3c_vi; break; 4136 case 44: op = rv_op_vghsh_vv; break; 4137 case 45: op = rv_op_vsha2ms_vv; break; 4138 case 46: op = rv_op_vsha2ch_vv; break; 4139 case 47: op = rv_op_vsha2cl_vv; break; 4140 } 4141 } 4142 break; 4143 case 30: 4144 switch (((inst >> 22) & 0b1111111000) | 4145 ((inst >> 12) & 0b0000000111)) { 4146 case 0: op = rv_op_addd; break; 4147 case 1: op = rv_op_slld; break; 4148 case 5: op = rv_op_srld; break; 4149 case 8: op = rv_op_muld; break; 4150 case 12: op = rv_op_divd; break; 4151 case 13: op = rv_op_divud; break; 4152 case 14: op = rv_op_remd; break; 4153 case 15: op = rv_op_remud; break; 4154 case 256: op = rv_op_subd; break; 4155 case 261: op = rv_op_srad; break; 4156 } 4157 break; 4158 } 4159 break; 4160 } 4161 dec->op = op; 4162 } 4163 4164 /* operand extractors */ 4165 4166 static uint32_t operand_rd(rv_inst inst) 4167 { 4168 return (inst << 52) >> 59; 4169 } 4170 4171 static uint32_t operand_rs1(rv_inst inst) 4172 { 4173 return (inst << 44) >> 59; 4174 } 4175 4176 static uint32_t operand_rs2(rv_inst inst) 4177 { 4178 return (inst << 39) >> 59; 4179 } 4180 4181 static uint32_t operand_rs3(rv_inst inst) 4182 { 4183 return (inst << 32) >> 59; 4184 } 4185 4186 static uint32_t operand_aq(rv_inst inst) 4187 { 4188 return (inst << 37) >> 63; 4189 } 4190 4191 static uint32_t operand_rl(rv_inst inst) 4192 { 4193 return (inst << 38) >> 63; 4194 } 4195 4196 static uint32_t operand_pred(rv_inst inst) 4197 { 4198 return (inst << 36) >> 60; 4199 } 4200 4201 static uint32_t operand_succ(rv_inst inst) 4202 { 4203 return (inst << 40) >> 60; 4204 } 4205 4206 static uint32_t operand_rm(rv_inst inst) 4207 { 4208 return (inst << 49) >> 61; 4209 } 4210 4211 static uint32_t operand_shamt5(rv_inst inst) 4212 { 4213 return (inst << 39) >> 59; 4214 } 4215 4216 static uint32_t operand_shamt6(rv_inst inst) 4217 { 4218 return (inst << 38) >> 58; 4219 } 4220 4221 static uint32_t operand_shamt7(rv_inst inst) 4222 { 4223 return (inst << 37) >> 57; 4224 } 4225 4226 static uint32_t operand_crdq(rv_inst inst) 4227 { 4228 return (inst << 59) >> 61; 4229 } 4230 4231 static uint32_t operand_crs1q(rv_inst inst) 4232 { 4233 return (inst << 54) >> 61; 4234 } 4235 4236 static uint32_t operand_crs1rdq(rv_inst inst) 4237 { 4238 return (inst << 54) >> 61; 4239 } 4240 4241 static uint32_t operand_crs2q(rv_inst inst) 4242 { 4243 return (inst << 59) >> 61; 4244 } 4245 4246 static uint32_t calculate_xreg(uint32_t sreg) 4247 { 4248 return sreg < 2 ? sreg + 8 : sreg + 16; 4249 } 4250 4251 static uint32_t operand_sreg1(rv_inst inst) 4252 { 4253 return calculate_xreg((inst << 54) >> 61); 4254 } 4255 4256 static uint32_t operand_sreg2(rv_inst inst) 4257 { 4258 return calculate_xreg((inst << 59) >> 61); 4259 } 4260 4261 static uint32_t operand_crd(rv_inst inst) 4262 { 4263 return (inst << 52) >> 59; 4264 } 4265 4266 static uint32_t operand_crs1(rv_inst inst) 4267 { 4268 return (inst << 52) >> 59; 4269 } 4270 4271 static uint32_t operand_crs1rd(rv_inst inst) 4272 { 4273 return (inst << 52) >> 59; 4274 } 4275 4276 static uint32_t operand_crs2(rv_inst inst) 4277 { 4278 return (inst << 57) >> 59; 4279 } 4280 4281 static uint32_t operand_cimmsh5(rv_inst inst) 4282 { 4283 return (inst << 57) >> 59; 4284 } 4285 4286 static uint32_t operand_csr12(rv_inst inst) 4287 { 4288 return (inst << 32) >> 52; 4289 } 4290 4291 static int32_t operand_imm12(rv_inst inst) 4292 { 4293 return ((int64_t)inst << 32) >> 52; 4294 } 4295 4296 static int32_t operand_imm20(rv_inst inst) 4297 { 4298 return (((int64_t)inst << 32) >> 44) << 12; 4299 } 4300 4301 static int32_t operand_jimm20(rv_inst inst) 4302 { 4303 return (((int64_t)inst << 32) >> 63) << 20 | 4304 ((inst << 33) >> 54) << 1 | 4305 ((inst << 43) >> 63) << 11 | 4306 ((inst << 44) >> 56) << 12; 4307 } 4308 4309 static int32_t operand_simm12(rv_inst inst) 4310 { 4311 return (((int64_t)inst << 32) >> 57) << 5 | 4312 (inst << 52) >> 59; 4313 } 4314 4315 static int32_t operand_sbimm12(rv_inst inst) 4316 { 4317 return (((int64_t)inst << 32) >> 63) << 12 | 4318 ((inst << 33) >> 58) << 5 | 4319 ((inst << 52) >> 60) << 1 | 4320 ((inst << 56) >> 63) << 11; 4321 } 4322 4323 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) 4324 { 4325 int imm = ((inst << 51) >> 63) << 5 | 4326 (inst << 57) >> 59; 4327 if (isa == rv128) { 4328 imm = imm ? imm : 64; 4329 } 4330 return imm; 4331 } 4332 4333 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) 4334 { 4335 int imm = ((inst << 51) >> 63) << 5 | 4336 (inst << 57) >> 59; 4337 if (isa == rv128) { 4338 imm = imm | (imm & 32) << 1; 4339 imm = imm ? imm : 64; 4340 } 4341 return imm; 4342 } 4343 4344 static int32_t operand_cimmi(rv_inst inst) 4345 { 4346 return (((int64_t)inst << 51) >> 63) << 5 | 4347 (inst << 57) >> 59; 4348 } 4349 4350 static int32_t operand_cimmui(rv_inst inst) 4351 { 4352 return (((int64_t)inst << 51) >> 63) << 17 | 4353 ((inst << 57) >> 59) << 12; 4354 } 4355 4356 static uint32_t operand_cimmlwsp(rv_inst inst) 4357 { 4358 return ((inst << 51) >> 63) << 5 | 4359 ((inst << 57) >> 61) << 2 | 4360 ((inst << 60) >> 62) << 6; 4361 } 4362 4363 static uint32_t operand_cimmldsp(rv_inst inst) 4364 { 4365 return ((inst << 51) >> 63) << 5 | 4366 ((inst << 57) >> 62) << 3 | 4367 ((inst << 59) >> 61) << 6; 4368 } 4369 4370 static uint32_t operand_cimmlqsp(rv_inst inst) 4371 { 4372 return ((inst << 51) >> 63) << 5 | 4373 ((inst << 57) >> 63) << 4 | 4374 ((inst << 58) >> 60) << 6; 4375 } 4376 4377 static int32_t operand_cimm16sp(rv_inst inst) 4378 { 4379 return (((int64_t)inst << 51) >> 63) << 9 | 4380 ((inst << 57) >> 63) << 4 | 4381 ((inst << 58) >> 63) << 6 | 4382 ((inst << 59) >> 62) << 7 | 4383 ((inst << 61) >> 63) << 5; 4384 } 4385 4386 static int32_t operand_cimmj(rv_inst inst) 4387 { 4388 return (((int64_t)inst << 51) >> 63) << 11 | 4389 ((inst << 52) >> 63) << 4 | 4390 ((inst << 53) >> 62) << 8 | 4391 ((inst << 55) >> 63) << 10 | 4392 ((inst << 56) >> 63) << 6 | 4393 ((inst << 57) >> 63) << 7 | 4394 ((inst << 58) >> 61) << 1 | 4395 ((inst << 61) >> 63) << 5; 4396 } 4397 4398 static int32_t operand_cimmb(rv_inst inst) 4399 { 4400 return (((int64_t)inst << 51) >> 63) << 8 | 4401 ((inst << 52) >> 62) << 3 | 4402 ((inst << 57) >> 62) << 6 | 4403 ((inst << 59) >> 62) << 1 | 4404 ((inst << 61) >> 63) << 5; 4405 } 4406 4407 static uint32_t operand_cimmswsp(rv_inst inst) 4408 { 4409 return ((inst << 51) >> 60) << 2 | 4410 ((inst << 55) >> 62) << 6; 4411 } 4412 4413 static uint32_t operand_cimmsdsp(rv_inst inst) 4414 { 4415 return ((inst << 51) >> 61) << 3 | 4416 ((inst << 54) >> 61) << 6; 4417 } 4418 4419 static uint32_t operand_cimmsqsp(rv_inst inst) 4420 { 4421 return ((inst << 51) >> 62) << 4 | 4422 ((inst << 53) >> 60) << 6; 4423 } 4424 4425 static uint32_t operand_cimm4spn(rv_inst inst) 4426 { 4427 return ((inst << 51) >> 62) << 4 | 4428 ((inst << 53) >> 60) << 6 | 4429 ((inst << 57) >> 63) << 2 | 4430 ((inst << 58) >> 63) << 3; 4431 } 4432 4433 static uint32_t operand_cimmw(rv_inst inst) 4434 { 4435 return ((inst << 51) >> 61) << 3 | 4436 ((inst << 57) >> 63) << 2 | 4437 ((inst << 58) >> 63) << 6; 4438 } 4439 4440 static uint32_t operand_cimmd(rv_inst inst) 4441 { 4442 return ((inst << 51) >> 61) << 3 | 4443 ((inst << 57) >> 62) << 6; 4444 } 4445 4446 static uint32_t operand_cimmq(rv_inst inst) 4447 { 4448 return ((inst << 51) >> 62) << 4 | 4449 ((inst << 53) >> 63) << 8 | 4450 ((inst << 57) >> 62) << 6; 4451 } 4452 4453 static uint32_t operand_vimm(rv_inst inst) 4454 { 4455 return (int64_t)(inst << 44) >> 59; 4456 } 4457 4458 static uint32_t operand_vzimm11(rv_inst inst) 4459 { 4460 return (inst << 33) >> 53; 4461 } 4462 4463 static uint32_t operand_vzimm10(rv_inst inst) 4464 { 4465 return (inst << 34) >> 54; 4466 } 4467 4468 static uint32_t operand_vzimm6(rv_inst inst) 4469 { 4470 return ((inst << 37) >> 63) << 5 | 4471 ((inst << 44) >> 59); 4472 } 4473 4474 static uint32_t operand_bs(rv_inst inst) 4475 { 4476 return (inst << 32) >> 62; 4477 } 4478 4479 static uint32_t operand_rnum(rv_inst inst) 4480 { 4481 return (inst << 40) >> 60; 4482 } 4483 4484 static uint32_t operand_vm(rv_inst inst) 4485 { 4486 return (inst << 38) >> 63; 4487 } 4488 4489 static uint32_t operand_uimm_c_lb(rv_inst inst) 4490 { 4491 return (((inst << 58) >> 63) << 1) | 4492 ((inst << 57) >> 63); 4493 } 4494 4495 static uint32_t operand_uimm_c_lh(rv_inst inst) 4496 { 4497 return (((inst << 58) >> 63) << 1); 4498 } 4499 4500 static uint32_t operand_zcmp_spimm(rv_inst inst) 4501 { 4502 return ((inst << 60) >> 62) << 4; 4503 } 4504 4505 static uint32_t operand_zcmp_rlist(rv_inst inst) 4506 { 4507 return ((inst << 56) >> 60); 4508 } 4509 4510 static uint32_t operand_imm6(rv_inst inst) 4511 { 4512 return (inst << 38) >> 60; 4513 } 4514 4515 static uint32_t operand_imm2(rv_inst inst) 4516 { 4517 return (inst << 37) >> 62; 4518 } 4519 4520 static uint32_t operand_immh(rv_inst inst) 4521 { 4522 return (inst << 32) >> 58; 4523 } 4524 4525 static uint32_t operand_imml(rv_inst inst) 4526 { 4527 return (inst << 38) >> 58; 4528 } 4529 4530 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm) 4531 { 4532 int xlen_bytes_log2 = isa == rv64 ? 3 : 2; 4533 int regs = rlist == 15 ? 13 : rlist - 3; 4534 uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16); 4535 return stack_adj_base + spimm; 4536 } 4537 4538 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa) 4539 { 4540 return calculate_stack_adj(isa, operand_zcmp_rlist(inst), 4541 operand_zcmp_spimm(inst)); 4542 } 4543 4544 static uint32_t operand_tbl_index(rv_inst inst) 4545 { 4546 return ((inst << 54) >> 56); 4547 } 4548 4549 static uint32_t operand_lpl(rv_inst inst) 4550 { 4551 return inst >> 12; 4552 } 4553 4554 /* decode operands */ 4555 4556 static void decode_inst_operands(rv_decode *dec, rv_isa isa) 4557 { 4558 const rv_opcode_data *opcode_data = dec->opcode_data; 4559 rv_inst inst = dec->inst; 4560 dec->codec = opcode_data[dec->op].codec; 4561 switch (dec->codec) { 4562 case rv_codec_none: 4563 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4564 dec->imm = 0; 4565 break; 4566 case rv_codec_u: 4567 dec->rd = operand_rd(inst); 4568 dec->rs1 = dec->rs2 = rv_ireg_zero; 4569 dec->imm = operand_imm20(inst); 4570 break; 4571 case rv_codec_uj: 4572 dec->rd = operand_rd(inst); 4573 dec->rs1 = dec->rs2 = rv_ireg_zero; 4574 dec->imm = operand_jimm20(inst); 4575 break; 4576 case rv_codec_i: 4577 dec->rd = operand_rd(inst); 4578 dec->rs1 = operand_rs1(inst); 4579 dec->rs2 = rv_ireg_zero; 4580 dec->imm = operand_imm12(inst); 4581 break; 4582 case rv_codec_i_sh5: 4583 dec->rd = operand_rd(inst); 4584 dec->rs1 = operand_rs1(inst); 4585 dec->rs2 = rv_ireg_zero; 4586 dec->imm = operand_shamt5(inst); 4587 break; 4588 case rv_codec_i_sh6: 4589 dec->rd = operand_rd(inst); 4590 dec->rs1 = operand_rs1(inst); 4591 dec->rs2 = rv_ireg_zero; 4592 dec->imm = operand_shamt6(inst); 4593 break; 4594 case rv_codec_i_sh7: 4595 dec->rd = operand_rd(inst); 4596 dec->rs1 = operand_rs1(inst); 4597 dec->rs2 = rv_ireg_zero; 4598 dec->imm = operand_shamt7(inst); 4599 break; 4600 case rv_codec_i_csr: 4601 dec->rd = operand_rd(inst); 4602 dec->rs1 = operand_rs1(inst); 4603 dec->rs2 = rv_ireg_zero; 4604 dec->imm = operand_csr12(inst); 4605 break; 4606 case rv_codec_s: 4607 dec->rd = rv_ireg_zero; 4608 dec->rs1 = operand_rs1(inst); 4609 dec->rs2 = operand_rs2(inst); 4610 dec->imm = operand_simm12(inst); 4611 break; 4612 case rv_codec_sb: 4613 dec->rd = rv_ireg_zero; 4614 dec->rs1 = operand_rs1(inst); 4615 dec->rs2 = operand_rs2(inst); 4616 dec->imm = operand_sbimm12(inst); 4617 break; 4618 case rv_codec_r: 4619 dec->rd = operand_rd(inst); 4620 dec->rs1 = operand_rs1(inst); 4621 dec->rs2 = operand_rs2(inst); 4622 dec->imm = 0; 4623 break; 4624 case rv_codec_r_m: 4625 dec->rd = operand_rd(inst); 4626 dec->rs1 = operand_rs1(inst); 4627 dec->rs2 = operand_rs2(inst); 4628 dec->imm = 0; 4629 dec->rm = operand_rm(inst); 4630 break; 4631 case rv_codec_r4_m: 4632 dec->rd = operand_rd(inst); 4633 dec->rs1 = operand_rs1(inst); 4634 dec->rs2 = operand_rs2(inst); 4635 dec->rs3 = operand_rs3(inst); 4636 dec->imm = 0; 4637 dec->rm = operand_rm(inst); 4638 break; 4639 case rv_codec_r_a: 4640 dec->rd = operand_rd(inst); 4641 dec->rs1 = operand_rs1(inst); 4642 dec->rs2 = operand_rs2(inst); 4643 dec->imm = 0; 4644 dec->aq = operand_aq(inst); 4645 dec->rl = operand_rl(inst); 4646 break; 4647 case rv_codec_r_l: 4648 dec->rd = operand_rd(inst); 4649 dec->rs1 = operand_rs1(inst); 4650 dec->rs2 = rv_ireg_zero; 4651 dec->imm = 0; 4652 dec->aq = operand_aq(inst); 4653 dec->rl = operand_rl(inst); 4654 break; 4655 case rv_codec_r_f: 4656 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4657 dec->pred = operand_pred(inst); 4658 dec->succ = operand_succ(inst); 4659 dec->imm = 0; 4660 break; 4661 case rv_codec_cb: 4662 dec->rd = rv_ireg_zero; 4663 dec->rs1 = operand_crs1q(inst) + 8; 4664 dec->rs2 = rv_ireg_zero; 4665 dec->imm = operand_cimmb(inst); 4666 break; 4667 case rv_codec_cb_imm: 4668 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4669 dec->rs2 = rv_ireg_zero; 4670 dec->imm = operand_cimmi(inst); 4671 break; 4672 case rv_codec_cb_sh5: 4673 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4674 dec->rs2 = rv_ireg_zero; 4675 dec->imm = operand_cimmsh5(inst); 4676 break; 4677 case rv_codec_cb_sh6: 4678 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4679 dec->rs2 = rv_ireg_zero; 4680 dec->imm = operand_cimmshr6(inst, isa); 4681 break; 4682 case rv_codec_ci: 4683 dec->rd = dec->rs1 = operand_crs1rd(inst); 4684 dec->rs2 = rv_ireg_zero; 4685 dec->imm = operand_cimmi(inst); 4686 break; 4687 case rv_codec_ci_sh5: 4688 dec->rd = dec->rs1 = operand_crs1rd(inst); 4689 dec->rs2 = rv_ireg_zero; 4690 dec->imm = operand_cimmsh5(inst); 4691 break; 4692 case rv_codec_ci_sh6: 4693 dec->rd = dec->rs1 = operand_crs1rd(inst); 4694 dec->rs2 = rv_ireg_zero; 4695 dec->imm = operand_cimmshl6(inst, isa); 4696 break; 4697 case rv_codec_ci_16sp: 4698 dec->rd = rv_ireg_sp; 4699 dec->rs1 = rv_ireg_sp; 4700 dec->rs2 = rv_ireg_zero; 4701 dec->imm = operand_cimm16sp(inst); 4702 break; 4703 case rv_codec_ci_lwsp: 4704 dec->rd = operand_crd(inst); 4705 dec->rs1 = rv_ireg_sp; 4706 dec->rs2 = rv_ireg_zero; 4707 dec->imm = operand_cimmlwsp(inst); 4708 break; 4709 case rv_codec_ci_ldsp: 4710 dec->rd = operand_crd(inst); 4711 dec->rs1 = rv_ireg_sp; 4712 dec->rs2 = rv_ireg_zero; 4713 dec->imm = operand_cimmldsp(inst); 4714 break; 4715 case rv_codec_ci_lqsp: 4716 dec->rd = operand_crd(inst); 4717 dec->rs1 = rv_ireg_sp; 4718 dec->rs2 = rv_ireg_zero; 4719 dec->imm = operand_cimmlqsp(inst); 4720 break; 4721 case rv_codec_ci_li: 4722 dec->rd = operand_crd(inst); 4723 dec->rs1 = rv_ireg_zero; 4724 dec->rs2 = rv_ireg_zero; 4725 dec->imm = operand_cimmi(inst); 4726 break; 4727 case rv_codec_ci_lui: 4728 dec->rd = operand_crd(inst); 4729 dec->rs1 = rv_ireg_zero; 4730 dec->rs2 = rv_ireg_zero; 4731 dec->imm = operand_cimmui(inst); 4732 break; 4733 case rv_codec_ci_none: 4734 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4735 dec->imm = 0; 4736 break; 4737 case rv_codec_ciw_4spn: 4738 dec->rd = operand_crdq(inst) + 8; 4739 dec->rs1 = rv_ireg_sp; 4740 dec->rs2 = rv_ireg_zero; 4741 dec->imm = operand_cimm4spn(inst); 4742 break; 4743 case rv_codec_cj: 4744 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4745 dec->imm = operand_cimmj(inst); 4746 break; 4747 case rv_codec_cj_jal: 4748 dec->rd = rv_ireg_ra; 4749 dec->rs1 = dec->rs2 = rv_ireg_zero; 4750 dec->imm = operand_cimmj(inst); 4751 break; 4752 case rv_codec_cl_lw: 4753 dec->rd = operand_crdq(inst) + 8; 4754 dec->rs1 = operand_crs1q(inst) + 8; 4755 dec->rs2 = rv_ireg_zero; 4756 dec->imm = operand_cimmw(inst); 4757 break; 4758 case rv_codec_cl_ld: 4759 dec->rd = operand_crdq(inst) + 8; 4760 dec->rs1 = operand_crs1q(inst) + 8; 4761 dec->rs2 = rv_ireg_zero; 4762 dec->imm = operand_cimmd(inst); 4763 break; 4764 case rv_codec_cl_lq: 4765 dec->rd = operand_crdq(inst) + 8; 4766 dec->rs1 = operand_crs1q(inst) + 8; 4767 dec->rs2 = rv_ireg_zero; 4768 dec->imm = operand_cimmq(inst); 4769 break; 4770 case rv_codec_cr: 4771 dec->rd = dec->rs1 = operand_crs1rd(inst); 4772 dec->rs2 = operand_crs2(inst); 4773 dec->imm = 0; 4774 break; 4775 case rv_codec_cr_mv: 4776 dec->rd = operand_crd(inst); 4777 dec->rs1 = operand_crs2(inst); 4778 dec->rs2 = rv_ireg_zero; 4779 dec->imm = 0; 4780 break; 4781 case rv_codec_cr_jalr: 4782 dec->rd = rv_ireg_ra; 4783 dec->rs1 = operand_crs1(inst); 4784 dec->rs2 = rv_ireg_zero; 4785 dec->imm = 0; 4786 break; 4787 case rv_codec_cr_jr: 4788 dec->rd = rv_ireg_zero; 4789 dec->rs1 = operand_crs1(inst); 4790 dec->rs2 = rv_ireg_zero; 4791 dec->imm = 0; 4792 break; 4793 case rv_codec_cs: 4794 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4795 dec->rs2 = operand_crs2q(inst) + 8; 4796 dec->imm = 0; 4797 break; 4798 case rv_codec_cs_sw: 4799 dec->rd = rv_ireg_zero; 4800 dec->rs1 = operand_crs1q(inst) + 8; 4801 dec->rs2 = operand_crs2q(inst) + 8; 4802 dec->imm = operand_cimmw(inst); 4803 break; 4804 case rv_codec_cs_sd: 4805 dec->rd = rv_ireg_zero; 4806 dec->rs1 = operand_crs1q(inst) + 8; 4807 dec->rs2 = operand_crs2q(inst) + 8; 4808 dec->imm = operand_cimmd(inst); 4809 break; 4810 case rv_codec_cs_sq: 4811 dec->rd = rv_ireg_zero; 4812 dec->rs1 = operand_crs1q(inst) + 8; 4813 dec->rs2 = operand_crs2q(inst) + 8; 4814 dec->imm = operand_cimmq(inst); 4815 break; 4816 case rv_codec_css_swsp: 4817 dec->rd = rv_ireg_zero; 4818 dec->rs1 = rv_ireg_sp; 4819 dec->rs2 = operand_crs2(inst); 4820 dec->imm = operand_cimmswsp(inst); 4821 break; 4822 case rv_codec_css_sdsp: 4823 dec->rd = rv_ireg_zero; 4824 dec->rs1 = rv_ireg_sp; 4825 dec->rs2 = operand_crs2(inst); 4826 dec->imm = operand_cimmsdsp(inst); 4827 break; 4828 case rv_codec_css_sqsp: 4829 dec->rd = rv_ireg_zero; 4830 dec->rs1 = rv_ireg_sp; 4831 dec->rs2 = operand_crs2(inst); 4832 dec->imm = operand_cimmsqsp(inst); 4833 break; 4834 case rv_codec_k_bs: 4835 dec->rs1 = operand_rs1(inst); 4836 dec->rs2 = operand_rs2(inst); 4837 dec->bs = operand_bs(inst); 4838 break; 4839 case rv_codec_k_rnum: 4840 dec->rd = operand_rd(inst); 4841 dec->rs1 = operand_rs1(inst); 4842 dec->rnum = operand_rnum(inst); 4843 break; 4844 case rv_codec_v_r: 4845 dec->rd = operand_rd(inst); 4846 dec->rs1 = operand_rs1(inst); 4847 dec->rs2 = operand_rs2(inst); 4848 dec->vm = operand_vm(inst); 4849 break; 4850 case rv_codec_v_ldst: 4851 dec->rd = operand_rd(inst); 4852 dec->rs1 = operand_rs1(inst); 4853 dec->vm = operand_vm(inst); 4854 break; 4855 case rv_codec_v_i: 4856 dec->rd = operand_rd(inst); 4857 dec->rs2 = operand_rs2(inst); 4858 dec->imm = operand_vimm(inst); 4859 dec->vm = operand_vm(inst); 4860 break; 4861 case rv_codec_vror_vi: 4862 dec->rd = operand_rd(inst); 4863 dec->rs2 = operand_rs2(inst); 4864 dec->imm = operand_vzimm6(inst); 4865 dec->vm = operand_vm(inst); 4866 break; 4867 case rv_codec_vsetvli: 4868 dec->rd = operand_rd(inst); 4869 dec->rs1 = operand_rs1(inst); 4870 dec->vzimm = operand_vzimm11(inst); 4871 break; 4872 case rv_codec_vsetivli: 4873 dec->rd = operand_rd(inst); 4874 dec->imm = extract32(inst, 15, 5); 4875 dec->vzimm = operand_vzimm10(inst); 4876 break; 4877 case rv_codec_zcb_lb: 4878 dec->rs1 = operand_crs1q(inst) + 8; 4879 dec->rs2 = operand_crs2q(inst) + 8; 4880 dec->imm = operand_uimm_c_lb(inst); 4881 break; 4882 case rv_codec_zcb_lh: 4883 dec->rs1 = operand_crs1q(inst) + 8; 4884 dec->rs2 = operand_crs2q(inst) + 8; 4885 dec->imm = operand_uimm_c_lh(inst); 4886 break; 4887 case rv_codec_zcb_ext: 4888 dec->rd = operand_crs1q(inst) + 8; 4889 break; 4890 case rv_codec_zcb_mul: 4891 dec->rd = operand_crs1rdq(inst) + 8; 4892 dec->rs2 = operand_crs2q(inst) + 8; 4893 break; 4894 case rv_codec_zcmp_cm_pushpop: 4895 dec->imm = operand_zcmp_stack_adj(inst, isa); 4896 dec->rlist = operand_zcmp_rlist(inst); 4897 break; 4898 case rv_codec_zcmp_cm_mv: 4899 dec->rd = operand_sreg1(inst); 4900 dec->rs2 = operand_sreg2(inst); 4901 break; 4902 case rv_codec_zcmt_jt: 4903 dec->imm = operand_tbl_index(inst); 4904 break; 4905 case rv_codec_fli: 4906 dec->rd = operand_rd(inst); 4907 dec->imm = operand_rs1(inst); 4908 break; 4909 case rv_codec_r2_imm5: 4910 dec->rd = operand_rd(inst); 4911 dec->rs1 = operand_rs1(inst); 4912 dec->imm = operand_rs2(inst); 4913 break; 4914 case rv_codec_r2: 4915 dec->rd = operand_rd(inst); 4916 dec->rs1 = operand_rs1(inst); 4917 break; 4918 case rv_codec_r2_imm6: 4919 dec->rd = operand_rd(inst); 4920 dec->rs1 = operand_rs1(inst); 4921 dec->imm = operand_imm6(inst); 4922 break; 4923 case rv_codec_r_imm2: 4924 dec->rd = operand_rd(inst); 4925 dec->rs1 = operand_rs1(inst); 4926 dec->rs2 = operand_rs2(inst); 4927 dec->imm = operand_imm2(inst); 4928 break; 4929 case rv_codec_r2_immhl: 4930 dec->rd = operand_rd(inst); 4931 dec->rs1 = operand_rs1(inst); 4932 dec->imm = operand_immh(inst); 4933 dec->imm1 = operand_imml(inst); 4934 break; 4935 case rv_codec_r2_imm2_imm5: 4936 dec->rd = operand_rd(inst); 4937 dec->rs1 = operand_rs1(inst); 4938 dec->imm = sextract32(operand_rs2(inst), 0, 5); 4939 dec->imm1 = operand_imm2(inst); 4940 break; 4941 case rv_codec_lp: 4942 dec->imm = operand_lpl(inst); 4943 break; 4944 case rv_codec_cmop_ss: 4945 dec->rd = rv_ireg_zero; 4946 dec->rs1 = dec->rs2 = operand_crs1(inst); 4947 dec->imm = 0; 4948 break; 4949 }; 4950 } 4951 4952 /* check constraint */ 4953 4954 static bool check_constraints(rv_decode *dec, const rvc_constraint *c) 4955 { 4956 int32_t imm = dec->imm; 4957 uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2; 4958 while (*c != rvc_end) { 4959 switch (*c) { 4960 case rvc_rd_eq_ra: 4961 if (!(rd == 1)) { 4962 return false; 4963 } 4964 break; 4965 case rvc_rd_eq_x0: 4966 if (!(rd == 0)) { 4967 return false; 4968 } 4969 break; 4970 case rvc_rs1_eq_x0: 4971 if (!(rs1 == 0)) { 4972 return false; 4973 } 4974 break; 4975 case rvc_rs2_eq_x0: 4976 if (!(rs2 == 0)) { 4977 return false; 4978 } 4979 break; 4980 case rvc_rs2_eq_rs1: 4981 if (!(rs2 == rs1)) { 4982 return false; 4983 } 4984 break; 4985 case rvc_rs1_eq_ra: 4986 if (!(rs1 == 1)) { 4987 return false; 4988 } 4989 break; 4990 case rvc_imm_eq_zero: 4991 if (!(imm == 0)) { 4992 return false; 4993 } 4994 break; 4995 case rvc_imm_eq_n1: 4996 if (!(imm == -1)) { 4997 return false; 4998 } 4999 break; 5000 case rvc_imm_eq_p1: 5001 if (!(imm == 1)) { 5002 return false; 5003 } 5004 break; 5005 case rvc_csr_eq_0x001: 5006 if (!(imm == 0x001)) { 5007 return false; 5008 } 5009 break; 5010 case rvc_csr_eq_0x002: 5011 if (!(imm == 0x002)) { 5012 return false; 5013 } 5014 break; 5015 case rvc_csr_eq_0x003: 5016 if (!(imm == 0x003)) { 5017 return false; 5018 } 5019 break; 5020 case rvc_csr_eq_0xc00: 5021 if (!(imm == 0xc00)) { 5022 return false; 5023 } 5024 break; 5025 case rvc_csr_eq_0xc01: 5026 if (!(imm == 0xc01)) { 5027 return false; 5028 } 5029 break; 5030 case rvc_csr_eq_0xc02: 5031 if (!(imm == 0xc02)) { 5032 return false; 5033 } 5034 break; 5035 case rvc_csr_eq_0xc80: 5036 if (!(imm == 0xc80)) { 5037 return false; 5038 } 5039 break; 5040 case rvc_csr_eq_0xc81: 5041 if (!(imm == 0xc81)) { 5042 return false; 5043 } 5044 break; 5045 case rvc_csr_eq_0xc82: 5046 if (!(imm == 0xc82)) { 5047 return false; 5048 } 5049 break; 5050 default: break; 5051 } 5052 c++; 5053 } 5054 return true; 5055 } 5056 5057 /* instruction length */ 5058 5059 static size_t inst_length(rv_inst inst) 5060 { 5061 /* NOTE: supports maximum instruction size of 64-bits */ 5062 5063 /* 5064 * instruction length coding 5065 * 5066 * aa - 16 bit aa != 11 5067 * bbb11 - 32 bit bbb != 111 5068 * 011111 - 48 bit 5069 * 0111111 - 64 bit 5070 */ 5071 5072 return (inst & 0b11) != 0b11 ? 2 5073 : (inst & 0b11100) != 0b11100 ? 4 5074 : (inst & 0b111111) == 0b011111 ? 6 5075 : (inst & 0b1111111) == 0b0111111 ? 8 5076 : 0; 5077 } 5078 5079 /* format instruction */ 5080 5081 static GString *format_inst(size_t tab, rv_decode *dec) 5082 { 5083 const rv_opcode_data *opcode_data = dec->opcode_data; 5084 GString *buf = g_string_sized_new(64); 5085 const char *fmt; 5086 5087 fmt = opcode_data[dec->op].format; 5088 while (*fmt) { 5089 switch (*fmt) { 5090 case 'O': 5091 g_string_append(buf, opcode_data[dec->op].name); 5092 break; 5093 case '(': 5094 case ',': 5095 case ')': 5096 case '-': 5097 g_string_append_c(buf, *fmt); 5098 break; 5099 case 'b': 5100 g_string_append_printf(buf, "%d", dec->bs); 5101 break; 5102 case 'n': 5103 g_string_append_printf(buf, "%d", dec->rnum); 5104 break; 5105 case '0': 5106 g_string_append(buf, rv_ireg_name_sym[dec->rd]); 5107 break; 5108 case '1': 5109 g_string_append(buf, rv_ireg_name_sym[dec->rs1]); 5110 break; 5111 case '2': 5112 g_string_append(buf, rv_ireg_name_sym[dec->rs2]); 5113 break; 5114 case '3': 5115 if (dec->cfg->ext_zfinx) { 5116 g_string_append(buf, rv_ireg_name_sym[dec->rd]); 5117 } else { 5118 g_string_append(buf, rv_freg_name_sym[dec->rd]); 5119 } 5120 break; 5121 case '4': 5122 if (dec->cfg->ext_zfinx) { 5123 g_string_append(buf, rv_ireg_name_sym[dec->rs1]); 5124 } else { 5125 g_string_append(buf, rv_freg_name_sym[dec->rs1]); 5126 } 5127 break; 5128 case '5': 5129 if (dec->cfg->ext_zfinx) { 5130 g_string_append(buf, rv_ireg_name_sym[dec->rs2]); 5131 } else { 5132 g_string_append(buf, rv_freg_name_sym[dec->rs2]); 5133 } 5134 break; 5135 case '6': 5136 if (dec->cfg->ext_zfinx) { 5137 g_string_append(buf, rv_ireg_name_sym[dec->rs3]); 5138 } else { 5139 g_string_append(buf, rv_freg_name_sym[dec->rs3]); 5140 } 5141 break; 5142 case '7': 5143 g_string_append_printf(buf, "%d", dec->rs1); 5144 break; 5145 case 'i': 5146 g_string_append_printf(buf, "%d", dec->imm); 5147 break; 5148 case 'u': 5149 g_string_append_printf(buf, "%u", ((uint32_t)dec->imm & 0b111111)); 5150 break; 5151 case 'j': 5152 g_string_append_printf(buf, "%d", dec->imm1); 5153 break; 5154 case 'o': 5155 g_string_append_printf(buf, "%d", dec->imm); 5156 while (buf->len < tab * 2) { 5157 g_string_append_c(buf, ' '); 5158 } 5159 g_string_append_printf(buf, "# 0x%" PRIx64, dec->pc + dec->imm); 5160 break; 5161 case 'U': 5162 fmt++; 5163 g_string_append_printf(buf, "%d", dec->imm >> 12); 5164 if (*fmt == 'o') { 5165 while (buf->len < tab * 2) { 5166 g_string_append_c(buf, ' '); 5167 } 5168 g_string_append_printf(buf, "# 0x%" PRIx64, dec->pc + dec->imm); 5169 } 5170 break; 5171 case 'c': { 5172 const char *name = csr_name(dec->imm & 0xfff); 5173 if (name) { 5174 g_string_append(buf, name); 5175 } else { 5176 g_string_append_printf(buf, "0x%03x", dec->imm & 0xfff); 5177 } 5178 break; 5179 } 5180 case 'r': 5181 switch (dec->rm) { 5182 case rv_rm_rne: 5183 g_string_append(buf, "rne"); 5184 break; 5185 case rv_rm_rtz: 5186 g_string_append(buf, "rtz"); 5187 break; 5188 case rv_rm_rdn: 5189 g_string_append(buf, "rdn"); 5190 break; 5191 case rv_rm_rup: 5192 g_string_append(buf, "rup"); 5193 break; 5194 case rv_rm_rmm: 5195 g_string_append(buf, "rmm"); 5196 break; 5197 case rv_rm_dyn: 5198 g_string_append(buf, "dyn"); 5199 break; 5200 default: 5201 g_string_append(buf, "inv"); 5202 break; 5203 } 5204 break; 5205 case 'p': 5206 if (dec->pred & rv_fence_i) { 5207 g_string_append_c(buf, 'i'); 5208 } 5209 if (dec->pred & rv_fence_o) { 5210 g_string_append_c(buf, 'o'); 5211 } 5212 if (dec->pred & rv_fence_r) { 5213 g_string_append_c(buf, 'r'); 5214 } 5215 if (dec->pred & rv_fence_w) { 5216 g_string_append_c(buf, 'w'); 5217 } 5218 break; 5219 case 's': 5220 if (dec->succ & rv_fence_i) { 5221 g_string_append_c(buf, 'i'); 5222 } 5223 if (dec->succ & rv_fence_o) { 5224 g_string_append_c(buf, 'o'); 5225 } 5226 if (dec->succ & rv_fence_r) { 5227 g_string_append_c(buf, 'r'); 5228 } 5229 if (dec->succ & rv_fence_w) { 5230 g_string_append_c(buf, 'w'); 5231 } 5232 break; 5233 case '\t': 5234 while (buf->len < tab) { 5235 g_string_append_c(buf, ' '); 5236 } 5237 break; 5238 case 'A': 5239 if (dec->aq) { 5240 g_string_append(buf, ".aq"); 5241 } 5242 break; 5243 case 'R': 5244 if (dec->rl) { 5245 g_string_append(buf, ".rl"); 5246 } 5247 break; 5248 case 'l': 5249 g_string_append(buf, ",v0"); 5250 break; 5251 case 'm': 5252 if (dec->vm == 0) { 5253 g_string_append(buf, ",v0.t"); 5254 } 5255 break; 5256 case 'D': 5257 g_string_append(buf, rv_vreg_name_sym[dec->rd]); 5258 break; 5259 case 'E': 5260 g_string_append(buf, rv_vreg_name_sym[dec->rs1]); 5261 break; 5262 case 'F': 5263 g_string_append(buf, rv_vreg_name_sym[dec->rs2]); 5264 break; 5265 case 'G': 5266 g_string_append(buf, rv_vreg_name_sym[dec->rs3]); 5267 break; 5268 case 'v': { 5269 const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3); 5270 const int lmul = dec->vzimm & 0b11; 5271 const int flmul = (dec->vzimm >> 2) & 1; 5272 const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu"; 5273 const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu"; 5274 5275 g_string_append_printf(buf, "e%d,m", sew); 5276 if (flmul) { 5277 switch (lmul) { 5278 case 3: 5279 g_string_append(buf, "f2"); 5280 break; 5281 case 2: 5282 g_string_append(buf, "f4"); 5283 break; 5284 case 1: 5285 g_string_append(buf, "f8"); 5286 break; 5287 } 5288 } else { 5289 g_string_append_printf(buf, "%d", 1 << lmul); 5290 } 5291 g_string_append_c(buf, ','); 5292 g_string_append(buf, vta); 5293 g_string_append_c(buf, ','); 5294 g_string_append(buf, vma); 5295 break; 5296 } 5297 case 'x': { 5298 switch (dec->rlist) { 5299 case 4: 5300 g_string_append(buf, "{ra}"); 5301 break; 5302 case 5: 5303 g_string_append(buf, "{ra, s0}"); 5304 break; 5305 case 15: 5306 g_string_append(buf, "{ra, s0-s11}"); 5307 break; 5308 default: 5309 g_string_append_printf(buf, "{ra, s0-s%d}", dec->rlist - 5); 5310 break; 5311 } 5312 break; 5313 } 5314 case 'h': 5315 g_string_append(buf, rv_fli_name_const[dec->imm]); 5316 break; 5317 default: 5318 break; 5319 } 5320 fmt++; 5321 } 5322 5323 return buf; 5324 } 5325 5326 /* lift instruction to pseudo-instruction */ 5327 5328 static void decode_inst_lift_pseudo(rv_decode *dec) 5329 { 5330 const rv_opcode_data *opcode_data = dec->opcode_data; 5331 const rv_comp_data *comp_data = opcode_data[dec->op].pseudo; 5332 if (!comp_data) { 5333 return; 5334 } 5335 while (comp_data->constraints) { 5336 if (check_constraints(dec, comp_data->constraints)) { 5337 dec->op = comp_data->op; 5338 dec->codec = opcode_data[dec->op].codec; 5339 return; 5340 } 5341 comp_data++; 5342 } 5343 } 5344 5345 /* decompress instruction */ 5346 5347 static void decode_inst_decompress_rv32(rv_decode *dec) 5348 { 5349 const rv_opcode_data *opcode_data = dec->opcode_data; 5350 int decomp_op = opcode_data[dec->op].decomp_rv32; 5351 if (decomp_op != rv_op_illegal) { 5352 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5353 && dec->imm == 0) { 5354 dec->op = rv_op_illegal; 5355 } else { 5356 dec->op = decomp_op; 5357 dec->codec = opcode_data[decomp_op].codec; 5358 } 5359 } 5360 } 5361 5362 static void decode_inst_decompress_rv64(rv_decode *dec) 5363 { 5364 const rv_opcode_data *opcode_data = dec->opcode_data; 5365 int decomp_op = opcode_data[dec->op].decomp_rv64; 5366 if (decomp_op != rv_op_illegal) { 5367 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5368 && dec->imm == 0) { 5369 dec->op = rv_op_illegal; 5370 } else { 5371 dec->op = decomp_op; 5372 dec->codec = opcode_data[decomp_op].codec; 5373 } 5374 } 5375 } 5376 5377 static void decode_inst_decompress_rv128(rv_decode *dec) 5378 { 5379 const rv_opcode_data *opcode_data = dec->opcode_data; 5380 int decomp_op = opcode_data[dec->op].decomp_rv128; 5381 if (decomp_op != rv_op_illegal) { 5382 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 5383 && dec->imm == 0) { 5384 dec->op = rv_op_illegal; 5385 } else { 5386 dec->op = decomp_op; 5387 dec->codec = opcode_data[decomp_op].codec; 5388 } 5389 } 5390 } 5391 5392 static void decode_inst_decompress(rv_decode *dec, rv_isa isa) 5393 { 5394 switch (isa) { 5395 case rv32: 5396 decode_inst_decompress_rv32(dec); 5397 break; 5398 case rv64: 5399 decode_inst_decompress_rv64(dec); 5400 break; 5401 case rv128: 5402 decode_inst_decompress_rv128(dec); 5403 break; 5404 } 5405 } 5406 5407 /* disassemble instruction */ 5408 5409 static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst, 5410 RISCVCPUConfig *cfg) 5411 { 5412 rv_decode dec = { 0 }; 5413 dec.pc = pc; 5414 dec.inst = inst; 5415 dec.cfg = cfg; 5416 5417 static const struct { 5418 bool (*guard_func)(const RISCVCPUConfig *); 5419 const rv_opcode_data *opcode_data; 5420 void (*decode_func)(rv_decode *, rv_isa); 5421 } decoders[] = { 5422 { always_true_p, rvi_opcode_data, decode_inst_opcode }, 5423 { has_xtheadba_p, xthead_opcode_data, decode_xtheadba }, 5424 { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb }, 5425 { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs }, 5426 { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo }, 5427 { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov }, 5428 { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx }, 5429 { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv }, 5430 { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac }, 5431 { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx }, 5432 { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair }, 5433 { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync }, 5434 { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops }, 5435 }; 5436 5437 for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) { 5438 bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func; 5439 const rv_opcode_data *opcode_data = decoders[i].opcode_data; 5440 void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func; 5441 5442 if (guard_func(cfg)) { 5443 dec.opcode_data = opcode_data; 5444 decode_func(&dec, isa); 5445 if (dec.op != rv_op_illegal) 5446 break; 5447 } 5448 } 5449 5450 if (dec.op == rv_op_illegal) { 5451 dec.opcode_data = rvi_opcode_data; 5452 } 5453 5454 decode_inst_operands(&dec, isa); 5455 decode_inst_decompress(&dec, isa); 5456 decode_inst_lift_pseudo(&dec); 5457 return format_inst(24, &dec); 5458 } 5459 5460 #define INST_FMT_2 "%04" PRIx64 " " 5461 #define INST_FMT_4 "%08" PRIx64 " " 5462 #define INST_FMT_6 "%012" PRIx64 " " 5463 #define INST_FMT_8 "%016" PRIx64 " " 5464 5465 static int 5466 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) 5467 { 5468 bfd_byte packet[2]; 5469 rv_inst inst = 0; 5470 size_t len = 2; 5471 bfd_vma n; 5472 int status; 5473 5474 /* Instructions are made of 2-byte packets in little-endian order */ 5475 for (n = 0; n < len; n += 2) { 5476 status = (*info->read_memory_func)(memaddr + n, packet, 2, info); 5477 if (status != 0) { 5478 /* Don't fail just because we fell off the end. */ 5479 if (n > 0) { 5480 break; 5481 } 5482 (*info->memory_error_func)(status, memaddr, info); 5483 return status; 5484 } 5485 inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n); 5486 if (n == 0) { 5487 len = inst_length(inst); 5488 } 5489 } 5490 5491 if (info->show_opcodes) { 5492 switch (len) { 5493 case 2: 5494 (*info->fprintf_func)(info->stream, INST_FMT_2, inst); 5495 break; 5496 case 4: 5497 (*info->fprintf_func)(info->stream, INST_FMT_4, inst); 5498 break; 5499 case 6: 5500 (*info->fprintf_func)(info->stream, INST_FMT_6, inst); 5501 break; 5502 default: 5503 (*info->fprintf_func)(info->stream, INST_FMT_8, inst); 5504 break; 5505 } 5506 } 5507 5508 g_autoptr(GString) str = 5509 disasm_inst(isa, memaddr, inst, (RISCVCPUConfig *)info->target_info); 5510 (*info->fprintf_func)(info->stream, "%s", str->str); 5511 5512 return len; 5513 } 5514 5515 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info) 5516 { 5517 return print_insn_riscv(memaddr, info, rv32); 5518 } 5519 5520 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info) 5521 { 5522 return print_insn_riscv(memaddr, info, rv64); 5523 } 5524 5525 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info) 5526 { 5527 return print_insn_riscv(memaddr, info, rv128); 5528 } 5529