1 /* 2 * QEMU RISC-V Disassembler 3 * 4 * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com> 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "disas/dis-asm.h" 22 23 24 /* types */ 25 26 typedef uint64_t rv_inst; 27 typedef uint16_t rv_opcode; 28 29 /* enums */ 30 31 typedef enum { 32 rv32, 33 rv64, 34 rv128 35 } rv_isa; 36 37 typedef enum { 38 rv_rm_rne = 0, 39 rv_rm_rtz = 1, 40 rv_rm_rdn = 2, 41 rv_rm_rup = 3, 42 rv_rm_rmm = 4, 43 rv_rm_dyn = 7, 44 } rv_rm; 45 46 typedef enum { 47 rv_fence_i = 8, 48 rv_fence_o = 4, 49 rv_fence_r = 2, 50 rv_fence_w = 1, 51 } rv_fence; 52 53 typedef enum { 54 rv_ireg_zero, 55 rv_ireg_ra, 56 rv_ireg_sp, 57 rv_ireg_gp, 58 rv_ireg_tp, 59 rv_ireg_t0, 60 rv_ireg_t1, 61 rv_ireg_t2, 62 rv_ireg_s0, 63 rv_ireg_s1, 64 rv_ireg_a0, 65 rv_ireg_a1, 66 rv_ireg_a2, 67 rv_ireg_a3, 68 rv_ireg_a4, 69 rv_ireg_a5, 70 rv_ireg_a6, 71 rv_ireg_a7, 72 rv_ireg_s2, 73 rv_ireg_s3, 74 rv_ireg_s4, 75 rv_ireg_s5, 76 rv_ireg_s6, 77 rv_ireg_s7, 78 rv_ireg_s8, 79 rv_ireg_s9, 80 rv_ireg_s10, 81 rv_ireg_s11, 82 rv_ireg_t3, 83 rv_ireg_t4, 84 rv_ireg_t5, 85 rv_ireg_t6, 86 } rv_ireg; 87 88 typedef enum { 89 rvc_end, 90 rvc_rd_eq_ra, 91 rvc_rd_eq_x0, 92 rvc_rs1_eq_x0, 93 rvc_rs2_eq_x0, 94 rvc_rs2_eq_rs1, 95 rvc_rs1_eq_ra, 96 rvc_imm_eq_zero, 97 rvc_imm_eq_n1, 98 rvc_imm_eq_p1, 99 rvc_csr_eq_0x001, 100 rvc_csr_eq_0x002, 101 rvc_csr_eq_0x003, 102 rvc_csr_eq_0xc00, 103 rvc_csr_eq_0xc01, 104 rvc_csr_eq_0xc02, 105 rvc_csr_eq_0xc80, 106 rvc_csr_eq_0xc81, 107 rvc_csr_eq_0xc82, 108 } rvc_constraint; 109 110 typedef enum { 111 rv_codec_illegal, 112 rv_codec_none, 113 rv_codec_u, 114 rv_codec_uj, 115 rv_codec_i, 116 rv_codec_i_sh5, 117 rv_codec_i_sh6, 118 rv_codec_i_sh7, 119 rv_codec_i_csr, 120 rv_codec_s, 121 rv_codec_sb, 122 rv_codec_r, 123 rv_codec_r_m, 124 rv_codec_r4_m, 125 rv_codec_r_a, 126 rv_codec_r_l, 127 rv_codec_r_f, 128 rv_codec_cb, 129 rv_codec_cb_imm, 130 rv_codec_cb_sh5, 131 rv_codec_cb_sh6, 132 rv_codec_ci, 133 rv_codec_ci_sh5, 134 rv_codec_ci_sh6, 135 rv_codec_ci_16sp, 136 rv_codec_ci_lwsp, 137 rv_codec_ci_ldsp, 138 rv_codec_ci_lqsp, 139 rv_codec_ci_li, 140 rv_codec_ci_lui, 141 rv_codec_ci_none, 142 rv_codec_ciw_4spn, 143 rv_codec_cj, 144 rv_codec_cj_jal, 145 rv_codec_cl_lw, 146 rv_codec_cl_ld, 147 rv_codec_cl_lq, 148 rv_codec_cr, 149 rv_codec_cr_mv, 150 rv_codec_cr_jalr, 151 rv_codec_cr_jr, 152 rv_codec_cs, 153 rv_codec_cs_sw, 154 rv_codec_cs_sd, 155 rv_codec_cs_sq, 156 rv_codec_css_swsp, 157 rv_codec_css_sdsp, 158 rv_codec_css_sqsp, 159 rv_codec_k_bs, 160 rv_codec_k_rnum, 161 rv_codec_v_r, 162 rv_codec_v_ldst, 163 rv_codec_v_i, 164 rv_codec_vsetvli, 165 rv_codec_vsetivli, 166 } rv_codec; 167 168 typedef enum { 169 rv_op_illegal = 0, 170 rv_op_lui = 1, 171 rv_op_auipc = 2, 172 rv_op_jal = 3, 173 rv_op_jalr = 4, 174 rv_op_beq = 5, 175 rv_op_bne = 6, 176 rv_op_blt = 7, 177 rv_op_bge = 8, 178 rv_op_bltu = 9, 179 rv_op_bgeu = 10, 180 rv_op_lb = 11, 181 rv_op_lh = 12, 182 rv_op_lw = 13, 183 rv_op_lbu = 14, 184 rv_op_lhu = 15, 185 rv_op_sb = 16, 186 rv_op_sh = 17, 187 rv_op_sw = 18, 188 rv_op_addi = 19, 189 rv_op_slti = 20, 190 rv_op_sltiu = 21, 191 rv_op_xori = 22, 192 rv_op_ori = 23, 193 rv_op_andi = 24, 194 rv_op_slli = 25, 195 rv_op_srli = 26, 196 rv_op_srai = 27, 197 rv_op_add = 28, 198 rv_op_sub = 29, 199 rv_op_sll = 30, 200 rv_op_slt = 31, 201 rv_op_sltu = 32, 202 rv_op_xor = 33, 203 rv_op_srl = 34, 204 rv_op_sra = 35, 205 rv_op_or = 36, 206 rv_op_and = 37, 207 rv_op_fence = 38, 208 rv_op_fence_i = 39, 209 rv_op_lwu = 40, 210 rv_op_ld = 41, 211 rv_op_sd = 42, 212 rv_op_addiw = 43, 213 rv_op_slliw = 44, 214 rv_op_srliw = 45, 215 rv_op_sraiw = 46, 216 rv_op_addw = 47, 217 rv_op_subw = 48, 218 rv_op_sllw = 49, 219 rv_op_srlw = 50, 220 rv_op_sraw = 51, 221 rv_op_ldu = 52, 222 rv_op_lq = 53, 223 rv_op_sq = 54, 224 rv_op_addid = 55, 225 rv_op_sllid = 56, 226 rv_op_srlid = 57, 227 rv_op_sraid = 58, 228 rv_op_addd = 59, 229 rv_op_subd = 60, 230 rv_op_slld = 61, 231 rv_op_srld = 62, 232 rv_op_srad = 63, 233 rv_op_mul = 64, 234 rv_op_mulh = 65, 235 rv_op_mulhsu = 66, 236 rv_op_mulhu = 67, 237 rv_op_div = 68, 238 rv_op_divu = 69, 239 rv_op_rem = 70, 240 rv_op_remu = 71, 241 rv_op_mulw = 72, 242 rv_op_divw = 73, 243 rv_op_divuw = 74, 244 rv_op_remw = 75, 245 rv_op_remuw = 76, 246 rv_op_muld = 77, 247 rv_op_divd = 78, 248 rv_op_divud = 79, 249 rv_op_remd = 80, 250 rv_op_remud = 81, 251 rv_op_lr_w = 82, 252 rv_op_sc_w = 83, 253 rv_op_amoswap_w = 84, 254 rv_op_amoadd_w = 85, 255 rv_op_amoxor_w = 86, 256 rv_op_amoor_w = 87, 257 rv_op_amoand_w = 88, 258 rv_op_amomin_w = 89, 259 rv_op_amomax_w = 90, 260 rv_op_amominu_w = 91, 261 rv_op_amomaxu_w = 92, 262 rv_op_lr_d = 93, 263 rv_op_sc_d = 94, 264 rv_op_amoswap_d = 95, 265 rv_op_amoadd_d = 96, 266 rv_op_amoxor_d = 97, 267 rv_op_amoor_d = 98, 268 rv_op_amoand_d = 99, 269 rv_op_amomin_d = 100, 270 rv_op_amomax_d = 101, 271 rv_op_amominu_d = 102, 272 rv_op_amomaxu_d = 103, 273 rv_op_lr_q = 104, 274 rv_op_sc_q = 105, 275 rv_op_amoswap_q = 106, 276 rv_op_amoadd_q = 107, 277 rv_op_amoxor_q = 108, 278 rv_op_amoor_q = 109, 279 rv_op_amoand_q = 110, 280 rv_op_amomin_q = 111, 281 rv_op_amomax_q = 112, 282 rv_op_amominu_q = 113, 283 rv_op_amomaxu_q = 114, 284 rv_op_ecall = 115, 285 rv_op_ebreak = 116, 286 rv_op_uret = 117, 287 rv_op_sret = 118, 288 rv_op_hret = 119, 289 rv_op_mret = 120, 290 rv_op_dret = 121, 291 rv_op_sfence_vm = 122, 292 rv_op_sfence_vma = 123, 293 rv_op_wfi = 124, 294 rv_op_csrrw = 125, 295 rv_op_csrrs = 126, 296 rv_op_csrrc = 127, 297 rv_op_csrrwi = 128, 298 rv_op_csrrsi = 129, 299 rv_op_csrrci = 130, 300 rv_op_flw = 131, 301 rv_op_fsw = 132, 302 rv_op_fmadd_s = 133, 303 rv_op_fmsub_s = 134, 304 rv_op_fnmsub_s = 135, 305 rv_op_fnmadd_s = 136, 306 rv_op_fadd_s = 137, 307 rv_op_fsub_s = 138, 308 rv_op_fmul_s = 139, 309 rv_op_fdiv_s = 140, 310 rv_op_fsgnj_s = 141, 311 rv_op_fsgnjn_s = 142, 312 rv_op_fsgnjx_s = 143, 313 rv_op_fmin_s = 144, 314 rv_op_fmax_s = 145, 315 rv_op_fsqrt_s = 146, 316 rv_op_fle_s = 147, 317 rv_op_flt_s = 148, 318 rv_op_feq_s = 149, 319 rv_op_fcvt_w_s = 150, 320 rv_op_fcvt_wu_s = 151, 321 rv_op_fcvt_s_w = 152, 322 rv_op_fcvt_s_wu = 153, 323 rv_op_fmv_x_s = 154, 324 rv_op_fclass_s = 155, 325 rv_op_fmv_s_x = 156, 326 rv_op_fcvt_l_s = 157, 327 rv_op_fcvt_lu_s = 158, 328 rv_op_fcvt_s_l = 159, 329 rv_op_fcvt_s_lu = 160, 330 rv_op_fld = 161, 331 rv_op_fsd = 162, 332 rv_op_fmadd_d = 163, 333 rv_op_fmsub_d = 164, 334 rv_op_fnmsub_d = 165, 335 rv_op_fnmadd_d = 166, 336 rv_op_fadd_d = 167, 337 rv_op_fsub_d = 168, 338 rv_op_fmul_d = 169, 339 rv_op_fdiv_d = 170, 340 rv_op_fsgnj_d = 171, 341 rv_op_fsgnjn_d = 172, 342 rv_op_fsgnjx_d = 173, 343 rv_op_fmin_d = 174, 344 rv_op_fmax_d = 175, 345 rv_op_fcvt_s_d = 176, 346 rv_op_fcvt_d_s = 177, 347 rv_op_fsqrt_d = 178, 348 rv_op_fle_d = 179, 349 rv_op_flt_d = 180, 350 rv_op_feq_d = 181, 351 rv_op_fcvt_w_d = 182, 352 rv_op_fcvt_wu_d = 183, 353 rv_op_fcvt_d_w = 184, 354 rv_op_fcvt_d_wu = 185, 355 rv_op_fclass_d = 186, 356 rv_op_fcvt_l_d = 187, 357 rv_op_fcvt_lu_d = 188, 358 rv_op_fmv_x_d = 189, 359 rv_op_fcvt_d_l = 190, 360 rv_op_fcvt_d_lu = 191, 361 rv_op_fmv_d_x = 192, 362 rv_op_flq = 193, 363 rv_op_fsq = 194, 364 rv_op_fmadd_q = 195, 365 rv_op_fmsub_q = 196, 366 rv_op_fnmsub_q = 197, 367 rv_op_fnmadd_q = 198, 368 rv_op_fadd_q = 199, 369 rv_op_fsub_q = 200, 370 rv_op_fmul_q = 201, 371 rv_op_fdiv_q = 202, 372 rv_op_fsgnj_q = 203, 373 rv_op_fsgnjn_q = 204, 374 rv_op_fsgnjx_q = 205, 375 rv_op_fmin_q = 206, 376 rv_op_fmax_q = 207, 377 rv_op_fcvt_s_q = 208, 378 rv_op_fcvt_q_s = 209, 379 rv_op_fcvt_d_q = 210, 380 rv_op_fcvt_q_d = 211, 381 rv_op_fsqrt_q = 212, 382 rv_op_fle_q = 213, 383 rv_op_flt_q = 214, 384 rv_op_feq_q = 215, 385 rv_op_fcvt_w_q = 216, 386 rv_op_fcvt_wu_q = 217, 387 rv_op_fcvt_q_w = 218, 388 rv_op_fcvt_q_wu = 219, 389 rv_op_fclass_q = 220, 390 rv_op_fcvt_l_q = 221, 391 rv_op_fcvt_lu_q = 222, 392 rv_op_fcvt_q_l = 223, 393 rv_op_fcvt_q_lu = 224, 394 rv_op_fmv_x_q = 225, 395 rv_op_fmv_q_x = 226, 396 rv_op_c_addi4spn = 227, 397 rv_op_c_fld = 228, 398 rv_op_c_lw = 229, 399 rv_op_c_flw = 230, 400 rv_op_c_fsd = 231, 401 rv_op_c_sw = 232, 402 rv_op_c_fsw = 233, 403 rv_op_c_nop = 234, 404 rv_op_c_addi = 235, 405 rv_op_c_jal = 236, 406 rv_op_c_li = 237, 407 rv_op_c_addi16sp = 238, 408 rv_op_c_lui = 239, 409 rv_op_c_srli = 240, 410 rv_op_c_srai = 241, 411 rv_op_c_andi = 242, 412 rv_op_c_sub = 243, 413 rv_op_c_xor = 244, 414 rv_op_c_or = 245, 415 rv_op_c_and = 246, 416 rv_op_c_subw = 247, 417 rv_op_c_addw = 248, 418 rv_op_c_j = 249, 419 rv_op_c_beqz = 250, 420 rv_op_c_bnez = 251, 421 rv_op_c_slli = 252, 422 rv_op_c_fldsp = 253, 423 rv_op_c_lwsp = 254, 424 rv_op_c_flwsp = 255, 425 rv_op_c_jr = 256, 426 rv_op_c_mv = 257, 427 rv_op_c_ebreak = 258, 428 rv_op_c_jalr = 259, 429 rv_op_c_add = 260, 430 rv_op_c_fsdsp = 261, 431 rv_op_c_swsp = 262, 432 rv_op_c_fswsp = 263, 433 rv_op_c_ld = 264, 434 rv_op_c_sd = 265, 435 rv_op_c_addiw = 266, 436 rv_op_c_ldsp = 267, 437 rv_op_c_sdsp = 268, 438 rv_op_c_lq = 269, 439 rv_op_c_sq = 270, 440 rv_op_c_lqsp = 271, 441 rv_op_c_sqsp = 272, 442 rv_op_nop = 273, 443 rv_op_mv = 274, 444 rv_op_not = 275, 445 rv_op_neg = 276, 446 rv_op_negw = 277, 447 rv_op_sext_w = 278, 448 rv_op_seqz = 279, 449 rv_op_snez = 280, 450 rv_op_sltz = 281, 451 rv_op_sgtz = 282, 452 rv_op_fmv_s = 283, 453 rv_op_fabs_s = 284, 454 rv_op_fneg_s = 285, 455 rv_op_fmv_d = 286, 456 rv_op_fabs_d = 287, 457 rv_op_fneg_d = 288, 458 rv_op_fmv_q = 289, 459 rv_op_fabs_q = 290, 460 rv_op_fneg_q = 291, 461 rv_op_beqz = 292, 462 rv_op_bnez = 293, 463 rv_op_blez = 294, 464 rv_op_bgez = 295, 465 rv_op_bltz = 296, 466 rv_op_bgtz = 297, 467 rv_op_ble = 298, 468 rv_op_bleu = 299, 469 rv_op_bgt = 300, 470 rv_op_bgtu = 301, 471 rv_op_j = 302, 472 rv_op_ret = 303, 473 rv_op_jr = 304, 474 rv_op_rdcycle = 305, 475 rv_op_rdtime = 306, 476 rv_op_rdinstret = 307, 477 rv_op_rdcycleh = 308, 478 rv_op_rdtimeh = 309, 479 rv_op_rdinstreth = 310, 480 rv_op_frcsr = 311, 481 rv_op_frrm = 312, 482 rv_op_frflags = 313, 483 rv_op_fscsr = 314, 484 rv_op_fsrm = 315, 485 rv_op_fsflags = 316, 486 rv_op_fsrmi = 317, 487 rv_op_fsflagsi = 318, 488 rv_op_bseti = 319, 489 rv_op_bclri = 320, 490 rv_op_binvi = 321, 491 rv_op_bexti = 322, 492 rv_op_rori = 323, 493 rv_op_clz = 324, 494 rv_op_ctz = 325, 495 rv_op_cpop = 326, 496 rv_op_sext_h = 327, 497 rv_op_sext_b = 328, 498 rv_op_xnor = 329, 499 rv_op_orn = 330, 500 rv_op_andn = 331, 501 rv_op_rol = 332, 502 rv_op_ror = 333, 503 rv_op_sh1add = 334, 504 rv_op_sh2add = 335, 505 rv_op_sh3add = 336, 506 rv_op_sh1add_uw = 337, 507 rv_op_sh2add_uw = 338, 508 rv_op_sh3add_uw = 339, 509 rv_op_clmul = 340, 510 rv_op_clmulr = 341, 511 rv_op_clmulh = 342, 512 rv_op_min = 343, 513 rv_op_minu = 344, 514 rv_op_max = 345, 515 rv_op_maxu = 346, 516 rv_op_clzw = 347, 517 rv_op_ctzw = 348, 518 rv_op_cpopw = 349, 519 rv_op_slli_uw = 350, 520 rv_op_add_uw = 351, 521 rv_op_rolw = 352, 522 rv_op_rorw = 353, 523 rv_op_rev8 = 354, 524 rv_op_zext_h = 355, 525 rv_op_roriw = 356, 526 rv_op_orc_b = 357, 527 rv_op_bset = 358, 528 rv_op_bclr = 359, 529 rv_op_binv = 360, 530 rv_op_bext = 361, 531 rv_op_aes32esmi = 362, 532 rv_op_aes32esi = 363, 533 rv_op_aes32dsmi = 364, 534 rv_op_aes32dsi = 365, 535 rv_op_aes64ks1i = 366, 536 rv_op_aes64ks2 = 367, 537 rv_op_aes64im = 368, 538 rv_op_aes64esm = 369, 539 rv_op_aes64es = 370, 540 rv_op_aes64dsm = 371, 541 rv_op_aes64ds = 372, 542 rv_op_sha256sig0 = 373, 543 rv_op_sha256sig1 = 374, 544 rv_op_sha256sum0 = 375, 545 rv_op_sha256sum1 = 376, 546 rv_op_sha512sig0 = 377, 547 rv_op_sha512sig1 = 378, 548 rv_op_sha512sum0 = 379, 549 rv_op_sha512sum1 = 380, 550 rv_op_sha512sum0r = 381, 551 rv_op_sha512sum1r = 382, 552 rv_op_sha512sig0l = 383, 553 rv_op_sha512sig0h = 384, 554 rv_op_sha512sig1l = 385, 555 rv_op_sha512sig1h = 386, 556 rv_op_sm3p0 = 387, 557 rv_op_sm3p1 = 388, 558 rv_op_sm4ed = 389, 559 rv_op_sm4ks = 390, 560 rv_op_brev8 = 391, 561 rv_op_pack = 392, 562 rv_op_packh = 393, 563 rv_op_packw = 394, 564 rv_op_unzip = 395, 565 rv_op_zip = 396, 566 rv_op_xperm4 = 397, 567 rv_op_xperm8 = 398, 568 rv_op_vle8_v = 399, 569 rv_op_vle16_v = 400, 570 rv_op_vle32_v = 401, 571 rv_op_vle64_v = 402, 572 rv_op_vse8_v = 403, 573 rv_op_vse16_v = 404, 574 rv_op_vse32_v = 405, 575 rv_op_vse64_v = 406, 576 rv_op_vlm_v = 407, 577 rv_op_vsm_v = 408, 578 rv_op_vlse8_v = 409, 579 rv_op_vlse16_v = 410, 580 rv_op_vlse32_v = 411, 581 rv_op_vlse64_v = 412, 582 rv_op_vsse8_v = 413, 583 rv_op_vsse16_v = 414, 584 rv_op_vsse32_v = 415, 585 rv_op_vsse64_v = 416, 586 rv_op_vluxei8_v = 417, 587 rv_op_vluxei16_v = 418, 588 rv_op_vluxei32_v = 419, 589 rv_op_vluxei64_v = 420, 590 rv_op_vloxei8_v = 421, 591 rv_op_vloxei16_v = 422, 592 rv_op_vloxei32_v = 423, 593 rv_op_vloxei64_v = 424, 594 rv_op_vsuxei8_v = 425, 595 rv_op_vsuxei16_v = 426, 596 rv_op_vsuxei32_v = 427, 597 rv_op_vsuxei64_v = 428, 598 rv_op_vsoxei8_v = 429, 599 rv_op_vsoxei16_v = 430, 600 rv_op_vsoxei32_v = 431, 601 rv_op_vsoxei64_v = 432, 602 rv_op_vle8ff_v = 433, 603 rv_op_vle16ff_v = 434, 604 rv_op_vle32ff_v = 435, 605 rv_op_vle64ff_v = 436, 606 rv_op_vl1re8_v = 437, 607 rv_op_vl1re16_v = 438, 608 rv_op_vl1re32_v = 439, 609 rv_op_vl1re64_v = 440, 610 rv_op_vl2re8_v = 441, 611 rv_op_vl2re16_v = 442, 612 rv_op_vl2re32_v = 443, 613 rv_op_vl2re64_v = 444, 614 rv_op_vl4re8_v = 445, 615 rv_op_vl4re16_v = 446, 616 rv_op_vl4re32_v = 447, 617 rv_op_vl4re64_v = 448, 618 rv_op_vl8re8_v = 449, 619 rv_op_vl8re16_v = 450, 620 rv_op_vl8re32_v = 451, 621 rv_op_vl8re64_v = 452, 622 rv_op_vs1r_v = 453, 623 rv_op_vs2r_v = 454, 624 rv_op_vs4r_v = 455, 625 rv_op_vs8r_v = 456, 626 rv_op_vadd_vv = 457, 627 rv_op_vadd_vx = 458, 628 rv_op_vadd_vi = 459, 629 rv_op_vsub_vv = 460, 630 rv_op_vsub_vx = 461, 631 rv_op_vrsub_vx = 462, 632 rv_op_vrsub_vi = 463, 633 rv_op_vwaddu_vv = 464, 634 rv_op_vwaddu_vx = 465, 635 rv_op_vwadd_vv = 466, 636 rv_op_vwadd_vx = 467, 637 rv_op_vwsubu_vv = 468, 638 rv_op_vwsubu_vx = 469, 639 rv_op_vwsub_vv = 470, 640 rv_op_vwsub_vx = 471, 641 rv_op_vwaddu_wv = 472, 642 rv_op_vwaddu_wx = 473, 643 rv_op_vwadd_wv = 474, 644 rv_op_vwadd_wx = 475, 645 rv_op_vwsubu_wv = 476, 646 rv_op_vwsubu_wx = 477, 647 rv_op_vwsub_wv = 478, 648 rv_op_vwsub_wx = 479, 649 rv_op_vadc_vvm = 480, 650 rv_op_vadc_vxm = 481, 651 rv_op_vadc_vim = 482, 652 rv_op_vmadc_vvm = 483, 653 rv_op_vmadc_vxm = 484, 654 rv_op_vmadc_vim = 485, 655 rv_op_vsbc_vvm = 486, 656 rv_op_vsbc_vxm = 487, 657 rv_op_vmsbc_vvm = 488, 658 rv_op_vmsbc_vxm = 489, 659 rv_op_vand_vv = 490, 660 rv_op_vand_vx = 491, 661 rv_op_vand_vi = 492, 662 rv_op_vor_vv = 493, 663 rv_op_vor_vx = 494, 664 rv_op_vor_vi = 495, 665 rv_op_vxor_vv = 496, 666 rv_op_vxor_vx = 497, 667 rv_op_vxor_vi = 498, 668 rv_op_vsll_vv = 499, 669 rv_op_vsll_vx = 500, 670 rv_op_vsll_vi = 501, 671 rv_op_vsrl_vv = 502, 672 rv_op_vsrl_vx = 503, 673 rv_op_vsrl_vi = 504, 674 rv_op_vsra_vv = 505, 675 rv_op_vsra_vx = 506, 676 rv_op_vsra_vi = 507, 677 rv_op_vnsrl_wv = 508, 678 rv_op_vnsrl_wx = 509, 679 rv_op_vnsrl_wi = 510, 680 rv_op_vnsra_wv = 511, 681 rv_op_vnsra_wx = 512, 682 rv_op_vnsra_wi = 513, 683 rv_op_vmseq_vv = 514, 684 rv_op_vmseq_vx = 515, 685 rv_op_vmseq_vi = 516, 686 rv_op_vmsne_vv = 517, 687 rv_op_vmsne_vx = 518, 688 rv_op_vmsne_vi = 519, 689 rv_op_vmsltu_vv = 520, 690 rv_op_vmsltu_vx = 521, 691 rv_op_vmslt_vv = 522, 692 rv_op_vmslt_vx = 523, 693 rv_op_vmsleu_vv = 524, 694 rv_op_vmsleu_vx = 525, 695 rv_op_vmsleu_vi = 526, 696 rv_op_vmsle_vv = 527, 697 rv_op_vmsle_vx = 528, 698 rv_op_vmsle_vi = 529, 699 rv_op_vmsgtu_vx = 530, 700 rv_op_vmsgtu_vi = 531, 701 rv_op_vmsgt_vx = 532, 702 rv_op_vmsgt_vi = 533, 703 rv_op_vminu_vv = 534, 704 rv_op_vminu_vx = 535, 705 rv_op_vmin_vv = 536, 706 rv_op_vmin_vx = 537, 707 rv_op_vmaxu_vv = 538, 708 rv_op_vmaxu_vx = 539, 709 rv_op_vmax_vv = 540, 710 rv_op_vmax_vx = 541, 711 rv_op_vmul_vv = 542, 712 rv_op_vmul_vx = 543, 713 rv_op_vmulh_vv = 544, 714 rv_op_vmulh_vx = 545, 715 rv_op_vmulhu_vv = 546, 716 rv_op_vmulhu_vx = 547, 717 rv_op_vmulhsu_vv = 548, 718 rv_op_vmulhsu_vx = 549, 719 rv_op_vdivu_vv = 550, 720 rv_op_vdivu_vx = 551, 721 rv_op_vdiv_vv = 552, 722 rv_op_vdiv_vx = 553, 723 rv_op_vremu_vv = 554, 724 rv_op_vremu_vx = 555, 725 rv_op_vrem_vv = 556, 726 rv_op_vrem_vx = 557, 727 rv_op_vwmulu_vv = 558, 728 rv_op_vwmulu_vx = 559, 729 rv_op_vwmulsu_vv = 560, 730 rv_op_vwmulsu_vx = 561, 731 rv_op_vwmul_vv = 562, 732 rv_op_vwmul_vx = 563, 733 rv_op_vmacc_vv = 564, 734 rv_op_vmacc_vx = 565, 735 rv_op_vnmsac_vv = 566, 736 rv_op_vnmsac_vx = 567, 737 rv_op_vmadd_vv = 568, 738 rv_op_vmadd_vx = 569, 739 rv_op_vnmsub_vv = 570, 740 rv_op_vnmsub_vx = 571, 741 rv_op_vwmaccu_vv = 572, 742 rv_op_vwmaccu_vx = 573, 743 rv_op_vwmacc_vv = 574, 744 rv_op_vwmacc_vx = 575, 745 rv_op_vwmaccsu_vv = 576, 746 rv_op_vwmaccsu_vx = 577, 747 rv_op_vwmaccus_vx = 578, 748 rv_op_vmv_v_v = 579, 749 rv_op_vmv_v_x = 580, 750 rv_op_vmv_v_i = 581, 751 rv_op_vmerge_vvm = 582, 752 rv_op_vmerge_vxm = 583, 753 rv_op_vmerge_vim = 584, 754 rv_op_vsaddu_vv = 585, 755 rv_op_vsaddu_vx = 586, 756 rv_op_vsaddu_vi = 587, 757 rv_op_vsadd_vv = 588, 758 rv_op_vsadd_vx = 589, 759 rv_op_vsadd_vi = 590, 760 rv_op_vssubu_vv = 591, 761 rv_op_vssubu_vx = 592, 762 rv_op_vssub_vv = 593, 763 rv_op_vssub_vx = 594, 764 rv_op_vaadd_vv = 595, 765 rv_op_vaadd_vx = 596, 766 rv_op_vaaddu_vv = 597, 767 rv_op_vaaddu_vx = 598, 768 rv_op_vasub_vv = 599, 769 rv_op_vasub_vx = 600, 770 rv_op_vasubu_vv = 601, 771 rv_op_vasubu_vx = 602, 772 rv_op_vsmul_vv = 603, 773 rv_op_vsmul_vx = 604, 774 rv_op_vssrl_vv = 605, 775 rv_op_vssrl_vx = 606, 776 rv_op_vssrl_vi = 607, 777 rv_op_vssra_vv = 608, 778 rv_op_vssra_vx = 609, 779 rv_op_vssra_vi = 610, 780 rv_op_vnclipu_wv = 611, 781 rv_op_vnclipu_wx = 612, 782 rv_op_vnclipu_wi = 613, 783 rv_op_vnclip_wv = 614, 784 rv_op_vnclip_wx = 615, 785 rv_op_vnclip_wi = 616, 786 rv_op_vfadd_vv = 617, 787 rv_op_vfadd_vf = 618, 788 rv_op_vfsub_vv = 619, 789 rv_op_vfsub_vf = 620, 790 rv_op_vfrsub_vf = 621, 791 rv_op_vfwadd_vv = 622, 792 rv_op_vfwadd_vf = 623, 793 rv_op_vfwadd_wv = 624, 794 rv_op_vfwadd_wf = 625, 795 rv_op_vfwsub_vv = 626, 796 rv_op_vfwsub_vf = 627, 797 rv_op_vfwsub_wv = 628, 798 rv_op_vfwsub_wf = 629, 799 rv_op_vfmul_vv = 630, 800 rv_op_vfmul_vf = 631, 801 rv_op_vfdiv_vv = 632, 802 rv_op_vfdiv_vf = 633, 803 rv_op_vfrdiv_vf = 634, 804 rv_op_vfwmul_vv = 635, 805 rv_op_vfwmul_vf = 636, 806 rv_op_vfmacc_vv = 637, 807 rv_op_vfmacc_vf = 638, 808 rv_op_vfnmacc_vv = 639, 809 rv_op_vfnmacc_vf = 640, 810 rv_op_vfmsac_vv = 641, 811 rv_op_vfmsac_vf = 642, 812 rv_op_vfnmsac_vv = 643, 813 rv_op_vfnmsac_vf = 644, 814 rv_op_vfmadd_vv = 645, 815 rv_op_vfmadd_vf = 646, 816 rv_op_vfnmadd_vv = 647, 817 rv_op_vfnmadd_vf = 648, 818 rv_op_vfmsub_vv = 649, 819 rv_op_vfmsub_vf = 650, 820 rv_op_vfnmsub_vv = 651, 821 rv_op_vfnmsub_vf = 652, 822 rv_op_vfwmacc_vv = 653, 823 rv_op_vfwmacc_vf = 654, 824 rv_op_vfwnmacc_vv = 655, 825 rv_op_vfwnmacc_vf = 656, 826 rv_op_vfwmsac_vv = 657, 827 rv_op_vfwmsac_vf = 658, 828 rv_op_vfwnmsac_vv = 659, 829 rv_op_vfwnmsac_vf = 660, 830 rv_op_vfsqrt_v = 661, 831 rv_op_vfrsqrt7_v = 662, 832 rv_op_vfrec7_v = 663, 833 rv_op_vfmin_vv = 664, 834 rv_op_vfmin_vf = 665, 835 rv_op_vfmax_vv = 666, 836 rv_op_vfmax_vf = 667, 837 rv_op_vfsgnj_vv = 668, 838 rv_op_vfsgnj_vf = 669, 839 rv_op_vfsgnjn_vv = 670, 840 rv_op_vfsgnjn_vf = 671, 841 rv_op_vfsgnjx_vv = 672, 842 rv_op_vfsgnjx_vf = 673, 843 rv_op_vfslide1up_vf = 674, 844 rv_op_vfslide1down_vf = 675, 845 rv_op_vmfeq_vv = 676, 846 rv_op_vmfeq_vf = 677, 847 rv_op_vmfne_vv = 678, 848 rv_op_vmfne_vf = 679, 849 rv_op_vmflt_vv = 680, 850 rv_op_vmflt_vf = 681, 851 rv_op_vmfle_vv = 682, 852 rv_op_vmfle_vf = 683, 853 rv_op_vmfgt_vf = 684, 854 rv_op_vmfge_vf = 685, 855 rv_op_vfclass_v = 686, 856 rv_op_vfmerge_vfm = 687, 857 rv_op_vfmv_v_f = 688, 858 rv_op_vfcvt_xu_f_v = 689, 859 rv_op_vfcvt_x_f_v = 690, 860 rv_op_vfcvt_f_xu_v = 691, 861 rv_op_vfcvt_f_x_v = 692, 862 rv_op_vfcvt_rtz_xu_f_v = 693, 863 rv_op_vfcvt_rtz_x_f_v = 694, 864 rv_op_vfwcvt_xu_f_v = 695, 865 rv_op_vfwcvt_x_f_v = 696, 866 rv_op_vfwcvt_f_xu_v = 697, 867 rv_op_vfwcvt_f_x_v = 698, 868 rv_op_vfwcvt_f_f_v = 699, 869 rv_op_vfwcvt_rtz_xu_f_v = 700, 870 rv_op_vfwcvt_rtz_x_f_v = 701, 871 rv_op_vfncvt_xu_f_w = 702, 872 rv_op_vfncvt_x_f_w = 703, 873 rv_op_vfncvt_f_xu_w = 704, 874 rv_op_vfncvt_f_x_w = 705, 875 rv_op_vfncvt_f_f_w = 706, 876 rv_op_vfncvt_rod_f_f_w = 707, 877 rv_op_vfncvt_rtz_xu_f_w = 708, 878 rv_op_vfncvt_rtz_x_f_w = 709, 879 rv_op_vredsum_vs = 710, 880 rv_op_vredand_vs = 711, 881 rv_op_vredor_vs = 712, 882 rv_op_vredxor_vs = 713, 883 rv_op_vredminu_vs = 714, 884 rv_op_vredmin_vs = 715, 885 rv_op_vredmaxu_vs = 716, 886 rv_op_vredmax_vs = 717, 887 rv_op_vwredsumu_vs = 718, 888 rv_op_vwredsum_vs = 719, 889 rv_op_vfredusum_vs = 720, 890 rv_op_vfredosum_vs = 721, 891 rv_op_vfredmin_vs = 722, 892 rv_op_vfredmax_vs = 723, 893 rv_op_vfwredusum_vs = 724, 894 rv_op_vfwredosum_vs = 725, 895 rv_op_vmand_mm = 726, 896 rv_op_vmnand_mm = 727, 897 rv_op_vmandn_mm = 728, 898 rv_op_vmxor_mm = 729, 899 rv_op_vmor_mm = 730, 900 rv_op_vmnor_mm = 731, 901 rv_op_vmorn_mm = 732, 902 rv_op_vmxnor_mm = 733, 903 rv_op_vcpop_m = 734, 904 rv_op_vfirst_m = 735, 905 rv_op_vmsbf_m = 736, 906 rv_op_vmsif_m = 737, 907 rv_op_vmsof_m = 738, 908 rv_op_viota_m = 739, 909 rv_op_vid_v = 740, 910 rv_op_vmv_x_s = 741, 911 rv_op_vmv_s_x = 742, 912 rv_op_vfmv_f_s = 743, 913 rv_op_vfmv_s_f = 744, 914 rv_op_vslideup_vx = 745, 915 rv_op_vslideup_vi = 746, 916 rv_op_vslide1up_vx = 747, 917 rv_op_vslidedown_vx = 748, 918 rv_op_vslidedown_vi = 749, 919 rv_op_vslide1down_vx = 750, 920 rv_op_vrgather_vv = 751, 921 rv_op_vrgatherei16_vv = 752, 922 rv_op_vrgather_vx = 753, 923 rv_op_vrgather_vi = 754, 924 rv_op_vcompress_vm = 755, 925 rv_op_vmv1r_v = 756, 926 rv_op_vmv2r_v = 757, 927 rv_op_vmv4r_v = 758, 928 rv_op_vmv8r_v = 759, 929 rv_op_vzext_vf2 = 760, 930 rv_op_vzext_vf4 = 761, 931 rv_op_vzext_vf8 = 762, 932 rv_op_vsext_vf2 = 763, 933 rv_op_vsext_vf4 = 764, 934 rv_op_vsext_vf8 = 765, 935 rv_op_vsetvli = 766, 936 rv_op_vsetivli = 767, 937 rv_op_vsetvl = 768, 938 } rv_op; 939 940 /* structures */ 941 942 typedef struct { 943 uint64_t pc; 944 uint64_t inst; 945 int32_t imm; 946 uint16_t op; 947 uint8_t codec; 948 uint8_t rd; 949 uint8_t rs1; 950 uint8_t rs2; 951 uint8_t rs3; 952 uint8_t rm; 953 uint8_t pred; 954 uint8_t succ; 955 uint8_t aq; 956 uint8_t rl; 957 uint8_t bs; 958 uint8_t rnum; 959 uint8_t vm; 960 uint32_t vzimm; 961 } rv_decode; 962 963 typedef struct { 964 const int op; 965 const rvc_constraint *constraints; 966 } rv_comp_data; 967 968 enum { 969 rvcd_imm_nz = 0x1 970 }; 971 972 typedef struct { 973 const char * const name; 974 const rv_codec codec; 975 const char * const format; 976 const rv_comp_data *pseudo; 977 const short decomp_rv32; 978 const short decomp_rv64; 979 const short decomp_rv128; 980 const short decomp_data; 981 } rv_opcode_data; 982 983 /* register names */ 984 985 static const char rv_ireg_name_sym[32][5] = { 986 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 987 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 988 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 989 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", 990 }; 991 992 static const char rv_freg_name_sym[32][5] = { 993 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", 994 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", 995 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", 996 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11", 997 }; 998 999 static const char rv_vreg_name_sym[32][4] = { 1000 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1001 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1002 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1003 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 1004 }; 1005 1006 /* instruction formats */ 1007 1008 #define rv_fmt_none "O\t" 1009 #define rv_fmt_rs1 "O\t1" 1010 #define rv_fmt_offset "O\to" 1011 #define rv_fmt_pred_succ "O\tp,s" 1012 #define rv_fmt_rs1_rs2 "O\t1,2" 1013 #define rv_fmt_rd_imm "O\t0,i" 1014 #define rv_fmt_rd_offset "O\t0,o" 1015 #define rv_fmt_rd_rs1_rs2 "O\t0,1,2" 1016 #define rv_fmt_frd_rs1 "O\t3,1" 1017 #define rv_fmt_frd_frs1 "O\t3,4" 1018 #define rv_fmt_rd_frs1 "O\t0,4" 1019 #define rv_fmt_rd_frs1_frs2 "O\t0,4,5" 1020 #define rv_fmt_frd_frs1_frs2 "O\t3,4,5" 1021 #define rv_fmt_rm_frd_frs1 "O\tr,3,4" 1022 #define rv_fmt_rm_frd_rs1 "O\tr,3,1" 1023 #define rv_fmt_rm_rd_frs1 "O\tr,0,4" 1024 #define rv_fmt_rm_frd_frs1_frs2 "O\tr,3,4,5" 1025 #define rv_fmt_rm_frd_frs1_frs2_frs3 "O\tr,3,4,5,6" 1026 #define rv_fmt_rd_rs1_imm "O\t0,1,i" 1027 #define rv_fmt_rd_rs1_offset "O\t0,1,i" 1028 #define rv_fmt_rd_offset_rs1 "O\t0,i(1)" 1029 #define rv_fmt_frd_offset_rs1 "O\t3,i(1)" 1030 #define rv_fmt_rd_csr_rs1 "O\t0,c,1" 1031 #define rv_fmt_rd_csr_zimm "O\t0,c,7" 1032 #define rv_fmt_rs2_offset_rs1 "O\t2,i(1)" 1033 #define rv_fmt_frs2_offset_rs1 "O\t5,i(1)" 1034 #define rv_fmt_rs1_rs2_offset "O\t1,2,o" 1035 #define rv_fmt_rs2_rs1_offset "O\t2,1,o" 1036 #define rv_fmt_aqrl_rd_rs2_rs1 "OAR\t0,2,(1)" 1037 #define rv_fmt_aqrl_rd_rs1 "OAR\t0,(1)" 1038 #define rv_fmt_rd "O\t0" 1039 #define rv_fmt_rd_zimm "O\t0,7" 1040 #define rv_fmt_rd_rs1 "O\t0,1" 1041 #define rv_fmt_rd_rs2 "O\t0,2" 1042 #define rv_fmt_rs1_offset "O\t1,o" 1043 #define rv_fmt_rs2_offset "O\t2,o" 1044 #define rv_fmt_rs1_rs2_bs "O\t1,2,b" 1045 #define rv_fmt_rd_rs1_rnum "O\t0,1,n" 1046 #define rv_fmt_ldst_vd_rs1_vm "O\tD,(1)m" 1047 #define rv_fmt_ldst_vd_rs1_rs2_vm "O\tD,(1),2m" 1048 #define rv_fmt_ldst_vd_rs1_vs2_vm "O\tD,(1),Fm" 1049 #define rv_fmt_vd_vs2_vs1 "O\tD,F,E" 1050 #define rv_fmt_vd_vs2_vs1_vl "O\tD,F,El" 1051 #define rv_fmt_vd_vs2_vs1_vm "O\tD,F,Em" 1052 #define rv_fmt_vd_vs2_rs1_vl "O\tD,F,1l" 1053 #define rv_fmt_vd_vs2_fs1_vl "O\tD,F,4l" 1054 #define rv_fmt_vd_vs2_rs1_vm "O\tD,F,1m" 1055 #define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m" 1056 #define rv_fmt_vd_vs2_imm_vl "O\tD,F,il" 1057 #define rv_fmt_vd_vs2_imm_vm "O\tD,F,im" 1058 #define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um" 1059 #define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm" 1060 #define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm" 1061 #define rv_fmt_vd_fs1_vs2_vm "O\tD,4,Fm" 1062 #define rv_fmt_vd_vs1 "O\tD,E" 1063 #define rv_fmt_vd_rs1 "O\tD,1" 1064 #define rv_fmt_vd_fs1 "O\tD,4" 1065 #define rv_fmt_vd_imm "O\tD,i" 1066 #define rv_fmt_vd_vs2 "O\tD,F" 1067 #define rv_fmt_vd_vs2_vm "O\tD,Fm" 1068 #define rv_fmt_rd_vs2_vm "O\t0,Fm" 1069 #define rv_fmt_rd_vs2 "O\t0,F" 1070 #define rv_fmt_fd_vs2 "O\t3,F" 1071 #define rv_fmt_vd_vm "O\tDm" 1072 #define rv_fmt_vsetvli "O\t0,1,v" 1073 #define rv_fmt_vsetivli "O\t0,u,v" 1074 1075 /* pseudo-instruction constraints */ 1076 1077 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end }; 1078 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end }; 1079 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end }; 1080 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; 1081 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end }; 1082 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end }; 1083 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end }; 1084 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end }; 1085 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end }; 1086 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end }; 1087 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end }; 1088 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end }; 1089 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1090 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1091 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end }; 1092 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1093 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1094 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end }; 1095 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1096 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1097 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end }; 1098 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end }; 1099 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end }; 1100 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end }; 1101 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end }; 1102 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end }; 1103 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end }; 1104 static const rvc_constraint rvcc_ble[] = { rvc_end }; 1105 static const rvc_constraint rvcc_bleu[] = { rvc_end }; 1106 static const rvc_constraint rvcc_bgt[] = { rvc_end }; 1107 static const rvc_constraint rvcc_bgtu[] = { rvc_end }; 1108 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end }; 1109 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end }; 1110 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end }; 1111 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end }; 1112 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end }; 1113 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end }; 1114 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end }; 1115 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end }; 1116 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, 1117 rvc_csr_eq_0xc82, rvc_end }; 1118 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end }; 1119 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end }; 1120 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end }; 1121 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end }; 1122 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end }; 1123 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end }; 1124 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end }; 1125 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end }; 1126 1127 /* pseudo-instruction metadata */ 1128 1129 static const rv_comp_data rvcp_jal[] = { 1130 { rv_op_j, rvcc_j }, 1131 { rv_op_jal, rvcc_jal }, 1132 { rv_op_illegal, NULL } 1133 }; 1134 1135 static const rv_comp_data rvcp_jalr[] = { 1136 { rv_op_ret, rvcc_ret }, 1137 { rv_op_jr, rvcc_jr }, 1138 { rv_op_jalr, rvcc_jalr }, 1139 { rv_op_illegal, NULL } 1140 }; 1141 1142 static const rv_comp_data rvcp_beq[] = { 1143 { rv_op_beqz, rvcc_beqz }, 1144 { rv_op_illegal, NULL } 1145 }; 1146 1147 static const rv_comp_data rvcp_bne[] = { 1148 { rv_op_bnez, rvcc_bnez }, 1149 { rv_op_illegal, NULL } 1150 }; 1151 1152 static const rv_comp_data rvcp_blt[] = { 1153 { rv_op_bltz, rvcc_bltz }, 1154 { rv_op_bgtz, rvcc_bgtz }, 1155 { rv_op_bgt, rvcc_bgt }, 1156 { rv_op_illegal, NULL } 1157 }; 1158 1159 static const rv_comp_data rvcp_bge[] = { 1160 { rv_op_blez, rvcc_blez }, 1161 { rv_op_bgez, rvcc_bgez }, 1162 { rv_op_ble, rvcc_ble }, 1163 { rv_op_illegal, NULL } 1164 }; 1165 1166 static const rv_comp_data rvcp_bltu[] = { 1167 { rv_op_bgtu, rvcc_bgtu }, 1168 { rv_op_illegal, NULL } 1169 }; 1170 1171 static const rv_comp_data rvcp_bgeu[] = { 1172 { rv_op_bleu, rvcc_bleu }, 1173 { rv_op_illegal, NULL } 1174 }; 1175 1176 static const rv_comp_data rvcp_addi[] = { 1177 { rv_op_nop, rvcc_nop }, 1178 { rv_op_mv, rvcc_mv }, 1179 { rv_op_illegal, NULL } 1180 }; 1181 1182 static const rv_comp_data rvcp_sltiu[] = { 1183 { rv_op_seqz, rvcc_seqz }, 1184 { rv_op_illegal, NULL } 1185 }; 1186 1187 static const rv_comp_data rvcp_xori[] = { 1188 { rv_op_not, rvcc_not }, 1189 { rv_op_illegal, NULL } 1190 }; 1191 1192 static const rv_comp_data rvcp_sub[] = { 1193 { rv_op_neg, rvcc_neg }, 1194 { rv_op_illegal, NULL } 1195 }; 1196 1197 static const rv_comp_data rvcp_slt[] = { 1198 { rv_op_sltz, rvcc_sltz }, 1199 { rv_op_sgtz, rvcc_sgtz }, 1200 { rv_op_illegal, NULL } 1201 }; 1202 1203 static const rv_comp_data rvcp_sltu[] = { 1204 { rv_op_snez, rvcc_snez }, 1205 { rv_op_illegal, NULL } 1206 }; 1207 1208 static const rv_comp_data rvcp_addiw[] = { 1209 { rv_op_sext_w, rvcc_sext_w }, 1210 { rv_op_illegal, NULL } 1211 }; 1212 1213 static const rv_comp_data rvcp_subw[] = { 1214 { rv_op_negw, rvcc_negw }, 1215 { rv_op_illegal, NULL } 1216 }; 1217 1218 static const rv_comp_data rvcp_csrrw[] = { 1219 { rv_op_fscsr, rvcc_fscsr }, 1220 { rv_op_fsrm, rvcc_fsrm }, 1221 { rv_op_fsflags, rvcc_fsflags }, 1222 { rv_op_illegal, NULL } 1223 }; 1224 1225 1226 static const rv_comp_data rvcp_csrrs[] = { 1227 { rv_op_rdcycle, rvcc_rdcycle }, 1228 { rv_op_rdtime, rvcc_rdtime }, 1229 { rv_op_rdinstret, rvcc_rdinstret }, 1230 { rv_op_rdcycleh, rvcc_rdcycleh }, 1231 { rv_op_rdtimeh, rvcc_rdtimeh }, 1232 { rv_op_rdinstreth, rvcc_rdinstreth }, 1233 { rv_op_frcsr, rvcc_frcsr }, 1234 { rv_op_frrm, rvcc_frrm }, 1235 { rv_op_frflags, rvcc_frflags }, 1236 { rv_op_illegal, NULL } 1237 }; 1238 1239 static const rv_comp_data rvcp_csrrwi[] = { 1240 { rv_op_fsrmi, rvcc_fsrmi }, 1241 { rv_op_fsflagsi, rvcc_fsflagsi }, 1242 { rv_op_illegal, NULL } 1243 }; 1244 1245 static const rv_comp_data rvcp_fsgnj_s[] = { 1246 { rv_op_fmv_s, rvcc_fmv_s }, 1247 { rv_op_illegal, NULL } 1248 }; 1249 1250 static const rv_comp_data rvcp_fsgnjn_s[] = { 1251 { rv_op_fneg_s, rvcc_fneg_s }, 1252 { rv_op_illegal, NULL } 1253 }; 1254 1255 static const rv_comp_data rvcp_fsgnjx_s[] = { 1256 { rv_op_fabs_s, rvcc_fabs_s }, 1257 { rv_op_illegal, NULL } 1258 }; 1259 1260 static const rv_comp_data rvcp_fsgnj_d[] = { 1261 { rv_op_fmv_d, rvcc_fmv_d }, 1262 { rv_op_illegal, NULL } 1263 }; 1264 1265 static const rv_comp_data rvcp_fsgnjn_d[] = { 1266 { rv_op_fneg_d, rvcc_fneg_d }, 1267 { rv_op_illegal, NULL } 1268 }; 1269 1270 static const rv_comp_data rvcp_fsgnjx_d[] = { 1271 { rv_op_fabs_d, rvcc_fabs_d }, 1272 { rv_op_illegal, NULL } 1273 }; 1274 1275 static const rv_comp_data rvcp_fsgnj_q[] = { 1276 { rv_op_fmv_q, rvcc_fmv_q }, 1277 { rv_op_illegal, NULL } 1278 }; 1279 1280 static const rv_comp_data rvcp_fsgnjn_q[] = { 1281 { rv_op_fneg_q, rvcc_fneg_q }, 1282 { rv_op_illegal, NULL } 1283 }; 1284 1285 static const rv_comp_data rvcp_fsgnjx_q[] = { 1286 { rv_op_fabs_q, rvcc_fabs_q }, 1287 { rv_op_illegal, NULL } 1288 }; 1289 1290 /* instruction metadata */ 1291 1292 const rv_opcode_data opcode_data[] = { 1293 { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, 1294 { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 }, 1295 { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 }, 1296 { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 }, 1297 { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 }, 1298 { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 }, 1299 { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 }, 1300 { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 }, 1301 { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 }, 1302 { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 }, 1303 { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 }, 1304 { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1305 { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1306 { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1307 { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1308 { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1309 { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1310 { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1311 { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1312 { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 }, 1313 { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1314 { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 }, 1315 { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 }, 1316 { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1317 { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1318 { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1319 { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1320 { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1321 { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1322 { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 }, 1323 { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1324 { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 }, 1325 { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 }, 1326 { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1327 { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1328 { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1329 { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1330 { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1331 { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 }, 1332 { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1333 { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1334 { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1335 { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1336 { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 }, 1337 { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1338 { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1339 { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1340 { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1341 { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 }, 1342 { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1343 { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1344 { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1345 { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1346 { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 }, 1347 { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 }, 1348 { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1349 { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1350 { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1351 { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1352 { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1353 { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1354 { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1355 { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1356 { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1357 { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1358 { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1359 { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1360 { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1361 { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1362 { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1363 { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1364 { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1365 { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1366 { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1367 { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1368 { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1369 { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1370 { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1371 { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1372 { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1373 { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1374 { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1375 { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1376 { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1377 { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1378 { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1379 { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1380 { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1381 { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1382 { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1383 { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1384 { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1385 { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1386 { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1387 { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1388 { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1389 { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1390 { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1391 { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1392 { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1393 { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1394 { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1395 { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1396 { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1397 { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 }, 1398 { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1399 { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1400 { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1401 { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1402 { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1403 { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1404 { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1405 { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1406 { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1407 { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, 1408 { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1409 { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1410 { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1411 { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1412 { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1413 { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1414 { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1415 { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 }, 1416 { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 }, 1417 { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, 1418 { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 }, 1419 { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 }, 1420 { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 }, 1421 { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 }, 1422 { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1423 { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 }, 1424 { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1425 { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1426 { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1427 { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1428 { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1429 { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1430 { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1431 { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1432 { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1433 { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1434 { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 }, 1435 { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 }, 1436 { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 }, 1437 { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1438 { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1439 { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1440 { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1441 { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1442 { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1443 { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1444 { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1445 { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1446 { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1447 { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1448 { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1449 { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1450 { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1451 { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1452 { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1453 { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1454 { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1455 { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1456 { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1457 { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1458 { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1459 { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1460 { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1461 { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1462 { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1463 { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1464 { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 }, 1465 { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 }, 1466 { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 }, 1467 { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1468 { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1469 { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1470 { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1471 { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1472 { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1473 { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1474 { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1475 { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1476 { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1477 { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1478 { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1479 { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1480 { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1481 { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1482 { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1483 { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1484 { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1485 { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1486 { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 }, 1487 { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 }, 1488 { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1489 { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1490 { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1491 { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 }, 1492 { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1493 { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1494 { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1495 { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 }, 1496 { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 }, 1497 { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 }, 1498 { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 }, 1499 { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1500 { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 }, 1501 { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1502 { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1503 { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1504 { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1505 { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 }, 1506 { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1507 { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1508 { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, 1509 { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1510 { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1511 { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1512 { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1513 { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1514 { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1515 { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 }, 1516 { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1517 { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 }, 1518 { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 }, 1519 { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 }, 1520 { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1521 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1522 { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 }, 1523 { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw }, 1524 { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, 1525 { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 }, 1526 { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw }, 1527 { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, 1528 { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, 1529 { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, 1530 rv_op_addi, rvcd_imm_nz }, 1531 { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 }, 1532 { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, 1533 { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, 1534 rv_op_addi, rv_op_addi, rvcd_imm_nz }, 1535 { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, 1536 rv_op_lui, rvcd_imm_nz }, 1537 { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, 1538 rv_op_srli, rv_op_srli, rvcd_imm_nz }, 1539 { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, 1540 rv_op_srai, rv_op_srai, rvcd_imm_nz }, 1541 { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, 1542 rv_op_andi, rv_op_andi }, 1543 { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub }, 1544 { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor }, 1545 { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or }, 1546 { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and }, 1547 { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw }, 1548 { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw }, 1549 { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal }, 1550 { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq }, 1551 { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne }, 1552 { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, 1553 rv_op_slli, rv_op_slli, rvcd_imm_nz }, 1554 { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld }, 1555 { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw }, 1556 { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 }, 1557 { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr }, 1558 { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi }, 1559 { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak }, 1560 { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr }, 1561 { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add }, 1562 { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd }, 1563 { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw }, 1564 { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 }, 1565 { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld }, 1566 { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd }, 1567 { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw }, 1568 { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld }, 1569 { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd }, 1570 { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1571 { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, 1572 { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq }, 1573 { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq }, 1574 { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1575 { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1576 { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1577 { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1578 { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1579 { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1580 { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1581 { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1582 { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1583 { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, 1584 { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1585 { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1586 { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1587 { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1588 { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1589 { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1590 { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1591 { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1592 { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 }, 1593 { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1594 { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1595 { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1596 { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1597 { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 }, 1598 { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 }, 1599 { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1600 { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1601 { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1602 { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 }, 1603 { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 }, 1604 { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 }, 1605 { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 }, 1606 { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1607 { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1608 { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1609 { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1610 { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1611 { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1612 { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1613 { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1614 { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 }, 1615 { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1616 { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1617 { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1618 { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1619 { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 }, 1620 { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1621 { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1622 { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1623 { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1624 { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1625 { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1626 { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1627 { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1628 { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1629 { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1630 { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1631 { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1632 { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1633 { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1634 { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1635 { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1636 { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1637 { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1638 { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1639 { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1640 { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1641 { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1642 { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1643 { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1644 { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1645 { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1646 { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1647 { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1648 { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1649 { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1650 { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1651 { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1652 { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1653 { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1654 { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1655 { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1656 { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1657 { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, 1658 { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1659 { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1660 { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1661 { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1662 { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1663 { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1664 { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1665 { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1666 { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1667 { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 }, 1668 { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1669 { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1670 { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1671 { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1672 { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1673 { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1674 { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1675 { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1676 { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1677 { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1678 { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1679 { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1680 { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1681 { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1682 { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1683 { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1684 { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1685 { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1686 { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1687 { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1688 { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1689 { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 }, 1690 { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1691 { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 }, 1692 { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1693 { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1694 { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1695 { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1696 { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1697 { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1698 { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, 1699 { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, 1700 { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8_v, rv_op_vle8_v, 0 }, 1701 { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16_v, rv_op_vle16_v, 0 }, 1702 { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32_v, rv_op_vle32_v, 0 }, 1703 { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64_v, rv_op_vle64_v, 0 }, 1704 { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse8_v, rv_op_vse8_v, 0 }, 1705 { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse16_v, rv_op_vse16_v, 0 }, 1706 { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse32_v, rv_op_vse32_v, 0 }, 1707 { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse64_v, rv_op_vse64_v, 0 }, 1708 { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vlm_v, rv_op_vlm_v, 0 }, 1709 { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vsm_v, rv_op_vsm_v, 0 }, 1710 { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse8_v, rv_op_vlse8_v, 0 }, 1711 { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse16_v, rv_op_vlse16_v, 0 }, 1712 { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse32_v, rv_op_vlse32_v, 0 }, 1713 { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse64_v, rv_op_vlse64_v, 0 }, 1714 { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse8_v, rv_op_vsse8_v, 0 }, 1715 { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse16_v, rv_op_vsse16_v, 0 }, 1716 { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse32_v, rv_op_vsse32_v, 0 }, 1717 { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse64_v, rv_op_vsse64_v, 0 }, 1718 { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei8_v, rv_op_vluxei8_v, 0 }, 1719 { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei16_v, rv_op_vluxei16_v, 0 }, 1720 { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei32_v, rv_op_vluxei32_v, 0 }, 1721 { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei64_v, rv_op_vluxei64_v, 0 }, 1722 { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei8_v, rv_op_vloxei8_v, 0 }, 1723 { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei16_v, rv_op_vloxei16_v, 0 }, 1724 { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei32_v, rv_op_vloxei32_v, 0 }, 1725 { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei64_v, rv_op_vloxei64_v, 0 }, 1726 { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei8_v, rv_op_vsuxei8_v, 0 }, 1727 { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei16_v, rv_op_vsuxei16_v, 0 }, 1728 { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei32_v, rv_op_vsuxei32_v, 0 }, 1729 { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei64_v, rv_op_vsuxei64_v, 0 }, 1730 { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei8_v, rv_op_vsoxei8_v, 0 }, 1731 { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei16_v, rv_op_vsoxei16_v, 0 }, 1732 { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei32_v, rv_op_vsoxei32_v, 0 }, 1733 { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei64_v, rv_op_vsoxei64_v, 0 }, 1734 { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8ff_v, rv_op_vle8ff_v, 0 }, 1735 { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16ff_v, rv_op_vle16ff_v, 0 }, 1736 { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32ff_v, rv_op_vle32ff_v, 0 }, 1737 { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64ff_v, rv_op_vle64ff_v, 0 }, 1738 { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re8_v, rv_op_vl1re8_v, 0 }, 1739 { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re16_v, rv_op_vl1re16_v, 0 }, 1740 { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re32_v, rv_op_vl1re32_v, 0 }, 1741 { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re64_v, rv_op_vl1re64_v, 0 }, 1742 { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re8_v, rv_op_vl2re8_v, 0 }, 1743 { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re16_v, rv_op_vl2re16_v, 0 }, 1744 { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re32_v, rv_op_vl2re32_v, 0 }, 1745 { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re64_v, rv_op_vl2re64_v, 0 }, 1746 { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re8_v, rv_op_vl4re8_v, 0 }, 1747 { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re16_v, rv_op_vl4re16_v, 0 }, 1748 { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re32_v, rv_op_vl4re32_v, 0 }, 1749 { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re64_v, rv_op_vl4re64_v, 0 }, 1750 { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re8_v, rv_op_vl8re8_v, 0 }, 1751 { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re16_v, rv_op_vl8re16_v, 0 }, 1752 { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re32_v, rv_op_vl8re32_v, 0 }, 1753 { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re64_v, rv_op_vl8re64_v, 0 }, 1754 { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs1r_v, rv_op_vs1r_v, 0 }, 1755 { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs2r_v, rv_op_vs2r_v, 0 }, 1756 { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs4r_v, rv_op_vs4r_v, 0 }, 1757 { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs8r_v, rv_op_vs8r_v, 0 }, 1758 { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vadd_vv, rv_op_vadd_vv, 0 }, 1759 { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vadd_vx, rv_op_vadd_vx, 0 }, 1760 { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vadd_vi, rv_op_vadd_vi, 0 }, 1761 { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsub_vv, rv_op_vsub_vv, 0 }, 1762 { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsub_vx, rv_op_vsub_vx, 0 }, 1763 { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrsub_vx, rv_op_vrsub_vx, 0 }, 1764 { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vrsub_vi, rv_op_vrsub_vi, 0 }, 1765 { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_vv, rv_op_vwaddu_vv, 0 }, 1766 { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_vx, rv_op_vwaddu_vx, 0 }, 1767 { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_vv, rv_op_vwadd_vv, 0 }, 1768 { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_vx, rv_op_vwadd_vx, 0 }, 1769 { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_vv, rv_op_vwsubu_vv, 0 }, 1770 { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_vx, rv_op_vwsubu_vx, 0 }, 1771 { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_vv, rv_op_vwsub_vv, 0 }, 1772 { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_vx, rv_op_vwsub_vx, 0 }, 1773 { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_wv, rv_op_vwaddu_wv, 0 }, 1774 { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_wx, rv_op_vwaddu_wx, 0 }, 1775 { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_wv, rv_op_vwadd_wv, 0 }, 1776 { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_wx, rv_op_vwadd_wx, 0 }, 1777 { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_wv, rv_op_vwsubu_wv, 0 }, 1778 { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_wx, rv_op_vwsubu_wx, 0 }, 1779 { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_wv, rv_op_vwsub_wv, 0 }, 1780 { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_wx, rv_op_vwsub_wx, 0 }, 1781 { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vadc_vvm, rv_op_vadc_vvm, 0 }, 1782 { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vadc_vxm, rv_op_vadc_vxm, 0 }, 1783 { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vadc_vim, rv_op_vadc_vim, 0 }, 1784 { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmadc_vvm, rv_op_vmadc_vvm, 0 }, 1785 { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmadc_vxm, rv_op_vmadc_vxm, 0 }, 1786 { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmadc_vim, rv_op_vmadc_vim, 0 }, 1787 { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vsbc_vvm, rv_op_vsbc_vvm, 0 }, 1788 { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vsbc_vxm, rv_op_vsbc_vxm, 0 }, 1789 { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmsbc_vvm, rv_op_vmsbc_vvm, 0 }, 1790 { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmsbc_vxm, rv_op_vmsbc_vxm, 0 }, 1791 { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vand_vv, rv_op_vand_vv, 0 }, 1792 { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vand_vx, rv_op_vand_vx, 0 }, 1793 { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vand_vi, rv_op_vand_vi, 0 }, 1794 { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vor_vv, rv_op_vor_vv, 0 }, 1795 { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vor_vx, rv_op_vor_vx, 0 }, 1796 { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vor_vi, rv_op_vor_vi, 0 }, 1797 { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vxor_vv, rv_op_vxor_vv, 0 }, 1798 { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vxor_vx, rv_op_vxor_vx, 0 }, 1799 { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vxor_vi, rv_op_vxor_vi, 0 }, 1800 { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsll_vv, rv_op_vsll_vv, 0 }, 1801 { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsll_vx, rv_op_vsll_vx, 0 }, 1802 { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsll_vi, rv_op_vsll_vi, 0 }, 1803 { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsrl_vv, rv_op_vsrl_vv, 0 }, 1804 { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsrl_vx, rv_op_vsrl_vx, 0 }, 1805 { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsrl_vi, rv_op_vsrl_vi, 0 }, 1806 { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsra_vv, rv_op_vsra_vv, 0 }, 1807 { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsra_vx, rv_op_vsra_vx, 0 }, 1808 { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsra_vi, rv_op_vsra_vi, 0 }, 1809 { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsrl_wv, rv_op_vnsrl_wv, 0 }, 1810 { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsrl_wx, rv_op_vnsrl_wx, 0 }, 1811 { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsrl_wi, rv_op_vnsrl_wi, 0 }, 1812 { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsra_wv, rv_op_vnsra_wv, 0 }, 1813 { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsra_wx, rv_op_vnsra_wx, 0 }, 1814 { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsra_wi, rv_op_vnsra_wi, 0 }, 1815 { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmseq_vv, rv_op_vmseq_vv, 0 }, 1816 { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmseq_vx, rv_op_vmseq_vx, 0 }, 1817 { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmseq_vi, rv_op_vmseq_vi, 0 }, 1818 { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsne_vv, rv_op_vmsne_vv, 0 }, 1819 { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsne_vx, rv_op_vmsne_vx, 0 }, 1820 { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsne_vi, rv_op_vmsne_vi, 0 }, 1821 { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsltu_vv, rv_op_vmsltu_vv, 0 }, 1822 { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsltu_vx, rv_op_vmsltu_vx, 0 }, 1823 { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmslt_vv, rv_op_vmslt_vv, 0 }, 1824 { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmslt_vx, rv_op_vmslt_vx, 0 }, 1825 { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsleu_vv, rv_op_vmsleu_vv, 0 }, 1826 { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsleu_vx, rv_op_vmsleu_vx, 0 }, 1827 { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsleu_vi, rv_op_vmsleu_vi, 0 }, 1828 { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsle_vv, rv_op_vmsle_vv, 0 }, 1829 { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsle_vx, rv_op_vmsle_vx, 0 }, 1830 { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsle_vi, rv_op_vmsle_vi, 0 }, 1831 { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgtu_vx, rv_op_vmsgtu_vx, 0 }, 1832 { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgtu_vi, rv_op_vmsgtu_vi, 0 }, 1833 { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgt_vx, rv_op_vmsgt_vx, 0 }, 1834 { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgt_vi, rv_op_vmsgt_vi, 0 }, 1835 { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vminu_vv, rv_op_vminu_vv, 0 }, 1836 { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vminu_vx, rv_op_vminu_vx, 0 }, 1837 { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmin_vv, rv_op_vmin_vv, 0 }, 1838 { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmin_vx, rv_op_vmin_vx, 0 }, 1839 { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmaxu_vv, rv_op_vmaxu_vv, 0 }, 1840 { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmaxu_vx, rv_op_vmaxu_vx, 0 }, 1841 { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmax_vv, rv_op_vmax_vv, 0 }, 1842 { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmax_vx, rv_op_vmax_vx, 0 }, 1843 { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmul_vv, rv_op_vmul_vv, 0 }, 1844 { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmul_vx, rv_op_vmul_vx, 0 }, 1845 { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulh_vv, rv_op_vmulh_vv, 0 }, 1846 { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulh_vx, rv_op_vmulh_vx, 0 }, 1847 { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhu_vv, rv_op_vmulhu_vv, 0 }, 1848 { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhu_vx, rv_op_vmulhu_vx, 0 }, 1849 { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhsu_vv, rv_op_vmulhsu_vv, 0 }, 1850 { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhsu_vx, rv_op_vmulhsu_vx, 0 }, 1851 { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdivu_vv, rv_op_vdivu_vv, 0 }, 1852 { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdivu_vx, rv_op_vdivu_vx, 0 }, 1853 { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdiv_vv, rv_op_vdiv_vv, 0 }, 1854 { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdiv_vx, rv_op_vdiv_vx, 0 }, 1855 { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vremu_vv, rv_op_vremu_vv, 0 }, 1856 { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vremu_vx, rv_op_vremu_vx, 0 }, 1857 { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrem_vv, rv_op_vrem_vv, 0 }, 1858 { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrem_vx, rv_op_vrem_vx, 0 }, 1859 { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulu_vv, rv_op_vwmulu_vv, 0 }, 1860 { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulu_vx, rv_op_vwmulu_vx, 0 }, 1861 { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulsu_vv, rv_op_vwmulsu_vv, 0 }, 1862 { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulsu_vx, rv_op_vwmulsu_vx, 0 }, 1863 { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmul_vv, rv_op_vwmul_vv, 0 }, 1864 { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmul_vx, rv_op_vwmul_vx, 0 }, 1865 { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmacc_vv, rv_op_vmacc_vv, 0 }, 1866 { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmacc_vx, rv_op_vmacc_vx, 0 }, 1867 { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsac_vv, rv_op_vnmsac_vv, 0 }, 1868 { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsac_vx, rv_op_vnmsac_vx, 0 }, 1869 { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmadd_vv, rv_op_vmadd_vv, 0 }, 1870 { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmadd_vx, rv_op_vmadd_vx, 0 }, 1871 { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsub_vv, rv_op_vnmsub_vv, 0 }, 1872 { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsub_vx, rv_op_vnmsub_vx, 0 }, 1873 { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccu_vv, rv_op_vwmaccu_vv, 0 }, 1874 { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccu_vx, rv_op_vwmaccu_vx, 0 }, 1875 { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmacc_vv, rv_op_vwmacc_vv, 0 }, 1876 { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmacc_vx, rv_op_vwmacc_vx, 0 }, 1877 { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccsu_vv, rv_op_vwmaccsu_vv, 0 }, 1878 { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccsu_vx, rv_op_vwmaccsu_vx, 0 }, 1879 { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccus_vx, rv_op_vwmaccus_vx, 0 }, 1880 { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, rv_op_vmv_v_v, rv_op_vmv_v_v, 0 }, 1881 { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_v_x, rv_op_vmv_v_x, 0 }, 1882 { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, rv_op_vmv_v_i, rv_op_vmv_v_i, 0 }, 1883 { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmerge_vvm, rv_op_vmerge_vvm, 0 }, 1884 { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmerge_vxm, rv_op_vmerge_vxm, 0 }, 1885 { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmerge_vim, rv_op_vmerge_vim, 0 }, 1886 { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsaddu_vv, rv_op_vsaddu_vv, 0 }, 1887 { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsaddu_vx, rv_op_vsaddu_vx, 0 }, 1888 { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsaddu_vi, rv_op_vsaddu_vi, 0 }, 1889 { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsadd_vv, rv_op_vsadd_vv, 0 }, 1890 { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsadd_vx, rv_op_vsadd_vx, 0 }, 1891 { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsadd_vi, rv_op_vsadd_vi, 0 }, 1892 { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssubu_vv, rv_op_vssubu_vv, 0 }, 1893 { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssubu_vx, rv_op_vssubu_vx, 0 }, 1894 { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssub_vv, rv_op_vssub_vv, 0 }, 1895 { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssub_vx, rv_op_vssub_vx, 0 }, 1896 { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaadd_vv, rv_op_vaadd_vv, 0 }, 1897 { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaadd_vx, rv_op_vaadd_vx, 0 }, 1898 { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaaddu_vv, rv_op_vaaddu_vv, 0 }, 1899 { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaaddu_vx, rv_op_vaaddu_vx, 0 }, 1900 { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasub_vv, rv_op_vasub_vv, 0 }, 1901 { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasub_vx, rv_op_vasub_vx, 0 }, 1902 { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasubu_vv, rv_op_vasubu_vv, 0 }, 1903 { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasubu_vx, rv_op_vasubu_vx, 0 }, 1904 { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsmul_vv, rv_op_vsmul_vv, 0 }, 1905 { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsmul_vx, rv_op_vsmul_vx, 0 }, 1906 { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssrl_vv, rv_op_vssrl_vv, 0 }, 1907 { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssrl_vx, rv_op_vssrl_vx, 0 }, 1908 { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssrl_vi, rv_op_vssrl_vi, 0 }, 1909 { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssra_vv, rv_op_vssra_vv, 0 }, 1910 { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssra_vx, rv_op_vssra_vx, 0 }, 1911 { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssra_vi, rv_op_vssra_vi, 0 }, 1912 { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclipu_wv, rv_op_vnclipu_wv, 0 }, 1913 { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclipu_wx, rv_op_vnclipu_wx, 0 }, 1914 { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclipu_wi, rv_op_vnclipu_wi, 0 }, 1915 { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclip_wv, rv_op_vnclip_wv, 0 }, 1916 { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclip_wx, rv_op_vnclip_wx, 0 }, 1917 { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclip_wi, rv_op_vnclip_wi, 0 }, 1918 { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfadd_vv, rv_op_vfadd_vv, 0 }, 1919 { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfadd_vf, rv_op_vfadd_vf, 0 }, 1920 { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsub_vv, rv_op_vfsub_vv, 0 }, 1921 { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsub_vf, rv_op_vfsub_vf, 0 }, 1922 { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrsub_vf, rv_op_vfrsub_vf, 0 }, 1923 { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_vv, rv_op_vfwadd_vv, 0 }, 1924 { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_vf, rv_op_vfwadd_vf, 0 }, 1925 { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_wv, rv_op_vfwadd_wv, 0 }, 1926 { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_wf, rv_op_vfwadd_wf, 0 }, 1927 { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_vv, rv_op_vfwsub_vv, 0 }, 1928 { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_vf, rv_op_vfwsub_vf, 0 }, 1929 { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_wv, rv_op_vfwsub_wv, 0 }, 1930 { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_wf, rv_op_vfwsub_wf, 0 }, 1931 { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmul_vv, rv_op_vfmul_vv, 0 }, 1932 { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmul_vf, rv_op_vfmul_vf, 0 }, 1933 { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfdiv_vv, rv_op_vfdiv_vv, 0 }, 1934 { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfdiv_vf, rv_op_vfdiv_vf, 0 }, 1935 { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrdiv_vf, rv_op_vfrdiv_vf, 0 }, 1936 { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwmul_vv, rv_op_vfwmul_vv, 0 }, 1937 { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwmul_vf, rv_op_vfwmul_vf, 0 }, 1938 { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmacc_vv, rv_op_vfmacc_vv, 0 }, 1939 { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmacc_vf, rv_op_vfmacc_vf, 0 }, 1940 { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmacc_vv, rv_op_vfnmacc_vv, 0 }, 1941 { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmacc_vf, rv_op_vfnmacc_vf, 0 }, 1942 { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsac_vv, rv_op_vfmsac_vv, 0 }, 1943 { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsac_vf, rv_op_vfmsac_vf, 0 }, 1944 { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsac_vv, rv_op_vfnmsac_vv, 0 }, 1945 { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsac_vf, rv_op_vfnmsac_vf, 0 }, 1946 { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmadd_vv, rv_op_vfmadd_vv, 0 }, 1947 { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmadd_vf, rv_op_vfmadd_vf, 0 }, 1948 { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmadd_vv, rv_op_vfnmadd_vv, 0 }, 1949 { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmadd_vf, rv_op_vfnmadd_vf, 0 }, 1950 { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsub_vv, rv_op_vfmsub_vv, 0 }, 1951 { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsub_vf, rv_op_vfmsub_vf, 0 }, 1952 { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsub_vv, rv_op_vfnmsub_vv, 0 }, 1953 { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsub_vf, rv_op_vfnmsub_vf, 0 }, 1954 { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmacc_vv, rv_op_vfwmacc_vv, 0 }, 1955 { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmacc_vf, rv_op_vfwmacc_vf, 0 }, 1956 { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmacc_vv, rv_op_vfwnmacc_vv, 0 }, 1957 { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmacc_vf, rv_op_vfwnmacc_vf, 0 }, 1958 { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmsac_vv, rv_op_vfwmsac_vv, 0 }, 1959 { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmsac_vf, rv_op_vfwmsac_vf, 0 }, 1960 { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmsac_vv, rv_op_vfwnmsac_vv, 0 }, 1961 { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmsac_vf, rv_op_vfwnmsac_vf, 0 }, 1962 { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfsqrt_v, rv_op_vfsqrt_v, 0 }, 1963 { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrsqrt7_v, rv_op_vfrsqrt7_v, 0 }, 1964 { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrec7_v, rv_op_vfrec7_v, 0 }, 1965 { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmin_vv, rv_op_vfmin_vv, 0 }, 1966 { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmin_vf, rv_op_vfmin_vf, 0 }, 1967 { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmax_vv, rv_op_vfmax_vv, 0 }, 1968 { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmax_vf, rv_op_vfmax_vf, 0 }, 1969 { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnj_vv, rv_op_vfsgnj_vv, 0 }, 1970 { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnj_vf, rv_op_vfsgnj_vf, 0 }, 1971 { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjn_vv, rv_op_vfsgnjn_vv, 0 }, 1972 { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjn_vf, rv_op_vfsgnjn_vf, 0 }, 1973 { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjx_vv, rv_op_vfsgnjx_vv, 0 }, 1974 { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjx_vf, rv_op_vfsgnjx_vf, 0 }, 1975 { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1up_vf, rv_op_vfslide1up_vf, 0 }, 1976 { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1down_vf, rv_op_vfslide1down_vf, 0 }, 1977 { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfeq_vv, rv_op_vmfeq_vv, 0 }, 1978 { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfeq_vf, rv_op_vmfeq_vf, 0 }, 1979 { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfne_vv, rv_op_vmfne_vv, 0 }, 1980 { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfne_vf, rv_op_vmfne_vf, 0 }, 1981 { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmflt_vv, rv_op_vmflt_vv, 0 }, 1982 { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmflt_vf, rv_op_vmflt_vf, 0 }, 1983 { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfle_vv, rv_op_vmfle_vv, 0 }, 1984 { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfle_vf, rv_op_vmfle_vf, 0 }, 1985 { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfgt_vf, rv_op_vmfgt_vf, 0 }, 1986 { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfge_vf, rv_op_vmfge_vf, 0 }, 1987 { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfclass_v, rv_op_vfclass_v, 0 }, 1988 { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, rv_op_vfmerge_vfm, rv_op_vfmerge_vfm, 0 }, 1989 { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_v_f, rv_op_vfmv_v_f, 0 }, 1990 { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_xu_f_v, rv_op_vfcvt_xu_f_v, 0 }, 1991 { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_x_f_v, rv_op_vfcvt_x_f_v, 0 }, 1992 { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_xu_v, rv_op_vfcvt_f_xu_v, 0 }, 1993 { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_x_v, rv_op_vfcvt_f_x_v, 0 }, 1994 { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_xu_f_v, rv_op_vfcvt_rtz_xu_f_v, 0 }, 1995 { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_x_f_v, rv_op_vfcvt_rtz_x_f_v, 0 }, 1996 { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_xu_f_v, rv_op_vfwcvt_xu_f_v, 0 }, 1997 { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_x_f_v, rv_op_vfwcvt_x_f_v, 0 }, 1998 { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_xu_v, rv_op_vfwcvt_f_xu_v, 0 }, 1999 { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_x_v, rv_op_vfwcvt_f_x_v, 0 }, 2000 { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_f_v, rv_op_vfwcvt_f_f_v, 0 }, 2001 { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_xu_f_v, rv_op_vfwcvt_rtz_xu_f_v, 0 }, 2002 { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_x_f_v, rv_op_vfwcvt_rtz_x_f_v, 0 }, 2003 { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_xu_f_w, rv_op_vfncvt_xu_f_w, 0 }, 2004 { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_x_f_w, rv_op_vfncvt_x_f_w, 0 }, 2005 { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_xu_w, rv_op_vfncvt_f_xu_w, 0 }, 2006 { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_x_w, rv_op_vfncvt_f_x_w, 0 }, 2007 { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_f_w, rv_op_vfncvt_f_f_w, 0 }, 2008 { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rod_f_f_w, rv_op_vfncvt_rod_f_f_w, 0 }, 2009 { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_xu_f_w, rv_op_vfncvt_rtz_xu_f_w, 0 }, 2010 { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_x_f_w, rv_op_vfncvt_rtz_x_f_w, 0 }, 2011 { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredsum_vs, rv_op_vredsum_vs, 0 }, 2012 { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredand_vs, rv_op_vredand_vs, 0 }, 2013 { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredor_vs, rv_op_vredor_vs, 0 }, 2014 { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredxor_vs, rv_op_vredxor_vs, 0 }, 2015 { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredminu_vs, rv_op_vredminu_vs, 0 }, 2016 { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmin_vs, rv_op_vredmin_vs, 0 }, 2017 { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmaxu_vs, rv_op_vredmaxu_vs, 0 }, 2018 { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmax_vs, rv_op_vredmax_vs, 0 }, 2019 { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsumu_vs, rv_op_vwredsumu_vs, 0 }, 2020 { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsum_vs, rv_op_vwredsum_vs, 0 }, 2021 { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredusum_vs, rv_op_vfredusum_vs, 0 }, 2022 { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredosum_vs, rv_op_vfredosum_vs, 0 }, 2023 { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmin_vs, rv_op_vfredmin_vs, 0 }, 2024 { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmax_vs, rv_op_vfredmax_vs, 0 }, 2025 { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredusum_vs, rv_op_vfwredusum_vs, 0 }, 2026 { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredosum_vs, rv_op_vfwredosum_vs, 0 }, 2027 { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmand_mm, rv_op_vmand_mm, 0 }, 2028 { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnand_mm, rv_op_vmnand_mm, 0 }, 2029 { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmandn_mm, rv_op_vmandn_mm, 0 }, 2030 { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxor_mm, rv_op_vmxor_mm, 0 }, 2031 { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmor_mm, rv_op_vmor_mm, 0 }, 2032 { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnor_mm, rv_op_vmnor_mm, 0 }, 2033 { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmorn_mm, rv_op_vmorn_mm, 0 }, 2034 { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxnor_mm, rv_op_vmxnor_mm, 0 }, 2035 { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vcpop_m, rv_op_vcpop_m, 0 }, 2036 { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vfirst_m, rv_op_vfirst_m, 0 }, 2037 { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsbf_m, rv_op_vmsbf_m, 0 }, 2038 { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsif_m, rv_op_vmsif_m, 0 }, 2039 { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsof_m, rv_op_vmsof_m, 0 }, 2040 { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_viota_m, rv_op_viota_m, 0 }, 2041 { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, rv_op_vid_v, rv_op_vid_v, 0 }, 2042 { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, rv_op_vmv_x_s, rv_op_vmv_x_s, 0 }, 2043 { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_s_x, rv_op_vmv_s_x, 0 }, 2044 { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, rv_op_vfmv_f_s, rv_op_vfmv_f_s, 0 }, 2045 { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_s_f, rv_op_vfmv_s_f, 0 }, 2046 { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslideup_vx, rv_op_vslideup_vx, 0 }, 2047 { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslideup_vi, rv_op_vslideup_vi, 0 }, 2048 { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1up_vx, rv_op_vslide1up_vx, 0 }, 2049 { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslidedown_vx, rv_op_vslidedown_vx, 0 }, 2050 { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslidedown_vi, rv_op_vslidedown_vi, 0 }, 2051 { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1down_vx, rv_op_vslide1down_vx, 0 }, 2052 { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgather_vv, rv_op_vrgather_vv, 0 }, 2053 { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgatherei16_vv, rv_op_vrgatherei16_vv, 0 }, 2054 { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrgather_vx, rv_op_vrgather_vx, 0 }, 2055 { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vrgather_vi, rv_op_vrgather_vi, 0 }, 2056 { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, rv_op_vcompress_vm, rv_op_vcompress_vm, 0 }, 2057 { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv1r_v, rv_op_vmv1r_v, 0 }, 2058 { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv2r_v, rv_op_vmv2r_v, 0 }, 2059 { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv4r_v, rv_op_vmv4r_v, 0 }, 2060 { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv8r_v, rv_op_vmv8r_v, 0 }, 2061 { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf2, rv_op_vzext_vf2, 0 }, 2062 { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf4, rv_op_vzext_vf4, 0 }, 2063 { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf8, rv_op_vzext_vf8, 0 }, 2064 { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf2, rv_op_vsext_vf2, 0 }, 2065 { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf4, rv_op_vsext_vf4, 0 }, 2066 { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 }, 2067 { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 }, 2068 { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 }, 2069 { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 } 2070 }; 2071 2072 /* CSR names */ 2073 2074 static const char *csr_name(int csrno) 2075 { 2076 switch (csrno) { 2077 case 0x0000: return "ustatus"; 2078 case 0x0001: return "fflags"; 2079 case 0x0002: return "frm"; 2080 case 0x0003: return "fcsr"; 2081 case 0x0004: return "uie"; 2082 case 0x0005: return "utvec"; 2083 case 0x0008: return "vstart"; 2084 case 0x0009: return "vxsat"; 2085 case 0x000a: return "vxrm"; 2086 case 0x000f: return "vcsr"; 2087 case 0x0015: return "seed"; 2088 case 0x0040: return "uscratch"; 2089 case 0x0041: return "uepc"; 2090 case 0x0042: return "ucause"; 2091 case 0x0043: return "utval"; 2092 case 0x0044: return "uip"; 2093 case 0x0100: return "sstatus"; 2094 case 0x0104: return "sie"; 2095 case 0x0105: return "stvec"; 2096 case 0x0106: return "scounteren"; 2097 case 0x0140: return "sscratch"; 2098 case 0x0141: return "sepc"; 2099 case 0x0142: return "scause"; 2100 case 0x0143: return "stval"; 2101 case 0x0144: return "sip"; 2102 case 0x0180: return "satp"; 2103 case 0x0200: return "hstatus"; 2104 case 0x0202: return "hedeleg"; 2105 case 0x0203: return "hideleg"; 2106 case 0x0204: return "hie"; 2107 case 0x0205: return "htvec"; 2108 case 0x0240: return "hscratch"; 2109 case 0x0241: return "hepc"; 2110 case 0x0242: return "hcause"; 2111 case 0x0243: return "hbadaddr"; 2112 case 0x0244: return "hip"; 2113 case 0x0300: return "mstatus"; 2114 case 0x0301: return "misa"; 2115 case 0x0302: return "medeleg"; 2116 case 0x0303: return "mideleg"; 2117 case 0x0304: return "mie"; 2118 case 0x0305: return "mtvec"; 2119 case 0x0306: return "mcounteren"; 2120 case 0x0320: return "mucounteren"; 2121 case 0x0321: return "mscounteren"; 2122 case 0x0322: return "mhcounteren"; 2123 case 0x0323: return "mhpmevent3"; 2124 case 0x0324: return "mhpmevent4"; 2125 case 0x0325: return "mhpmevent5"; 2126 case 0x0326: return "mhpmevent6"; 2127 case 0x0327: return "mhpmevent7"; 2128 case 0x0328: return "mhpmevent8"; 2129 case 0x0329: return "mhpmevent9"; 2130 case 0x032a: return "mhpmevent10"; 2131 case 0x032b: return "mhpmevent11"; 2132 case 0x032c: return "mhpmevent12"; 2133 case 0x032d: return "mhpmevent13"; 2134 case 0x032e: return "mhpmevent14"; 2135 case 0x032f: return "mhpmevent15"; 2136 case 0x0330: return "mhpmevent16"; 2137 case 0x0331: return "mhpmevent17"; 2138 case 0x0332: return "mhpmevent18"; 2139 case 0x0333: return "mhpmevent19"; 2140 case 0x0334: return "mhpmevent20"; 2141 case 0x0335: return "mhpmevent21"; 2142 case 0x0336: return "mhpmevent22"; 2143 case 0x0337: return "mhpmevent23"; 2144 case 0x0338: return "mhpmevent24"; 2145 case 0x0339: return "mhpmevent25"; 2146 case 0x033a: return "mhpmevent26"; 2147 case 0x033b: return "mhpmevent27"; 2148 case 0x033c: return "mhpmevent28"; 2149 case 0x033d: return "mhpmevent29"; 2150 case 0x033e: return "mhpmevent30"; 2151 case 0x033f: return "mhpmevent31"; 2152 case 0x0340: return "mscratch"; 2153 case 0x0341: return "mepc"; 2154 case 0x0342: return "mcause"; 2155 case 0x0343: return "mtval"; 2156 case 0x0344: return "mip"; 2157 case 0x0380: return "mbase"; 2158 case 0x0381: return "mbound"; 2159 case 0x0382: return "mibase"; 2160 case 0x0383: return "mibound"; 2161 case 0x0384: return "mdbase"; 2162 case 0x0385: return "mdbound"; 2163 case 0x03a0: return "pmpcfg3"; 2164 case 0x03b0: return "pmpaddr0"; 2165 case 0x03b1: return "pmpaddr1"; 2166 case 0x03b2: return "pmpaddr2"; 2167 case 0x03b3: return "pmpaddr3"; 2168 case 0x03b4: return "pmpaddr4"; 2169 case 0x03b5: return "pmpaddr5"; 2170 case 0x03b6: return "pmpaddr6"; 2171 case 0x03b7: return "pmpaddr7"; 2172 case 0x03b8: return "pmpaddr8"; 2173 case 0x03b9: return "pmpaddr9"; 2174 case 0x03ba: return "pmpaddr10"; 2175 case 0x03bb: return "pmpaddr11"; 2176 case 0x03bc: return "pmpaddr12"; 2177 case 0x03bd: return "pmpaddr14"; 2178 case 0x03be: return "pmpaddr13"; 2179 case 0x03bf: return "pmpaddr15"; 2180 case 0x0780: return "mtohost"; 2181 case 0x0781: return "mfromhost"; 2182 case 0x0782: return "mreset"; 2183 case 0x0783: return "mipi"; 2184 case 0x0784: return "miobase"; 2185 case 0x07a0: return "tselect"; 2186 case 0x07a1: return "tdata1"; 2187 case 0x07a2: return "tdata2"; 2188 case 0x07a3: return "tdata3"; 2189 case 0x07b0: return "dcsr"; 2190 case 0x07b1: return "dpc"; 2191 case 0x07b2: return "dscratch"; 2192 case 0x0b00: return "mcycle"; 2193 case 0x0b01: return "mtime"; 2194 case 0x0b02: return "minstret"; 2195 case 0x0b03: return "mhpmcounter3"; 2196 case 0x0b04: return "mhpmcounter4"; 2197 case 0x0b05: return "mhpmcounter5"; 2198 case 0x0b06: return "mhpmcounter6"; 2199 case 0x0b07: return "mhpmcounter7"; 2200 case 0x0b08: return "mhpmcounter8"; 2201 case 0x0b09: return "mhpmcounter9"; 2202 case 0x0b0a: return "mhpmcounter10"; 2203 case 0x0b0b: return "mhpmcounter11"; 2204 case 0x0b0c: return "mhpmcounter12"; 2205 case 0x0b0d: return "mhpmcounter13"; 2206 case 0x0b0e: return "mhpmcounter14"; 2207 case 0x0b0f: return "mhpmcounter15"; 2208 case 0x0b10: return "mhpmcounter16"; 2209 case 0x0b11: return "mhpmcounter17"; 2210 case 0x0b12: return "mhpmcounter18"; 2211 case 0x0b13: return "mhpmcounter19"; 2212 case 0x0b14: return "mhpmcounter20"; 2213 case 0x0b15: return "mhpmcounter21"; 2214 case 0x0b16: return "mhpmcounter22"; 2215 case 0x0b17: return "mhpmcounter23"; 2216 case 0x0b18: return "mhpmcounter24"; 2217 case 0x0b19: return "mhpmcounter25"; 2218 case 0x0b1a: return "mhpmcounter26"; 2219 case 0x0b1b: return "mhpmcounter27"; 2220 case 0x0b1c: return "mhpmcounter28"; 2221 case 0x0b1d: return "mhpmcounter29"; 2222 case 0x0b1e: return "mhpmcounter30"; 2223 case 0x0b1f: return "mhpmcounter31"; 2224 case 0x0b80: return "mcycleh"; 2225 case 0x0b81: return "mtimeh"; 2226 case 0x0b82: return "minstreth"; 2227 case 0x0b83: return "mhpmcounter3h"; 2228 case 0x0b84: return "mhpmcounter4h"; 2229 case 0x0b85: return "mhpmcounter5h"; 2230 case 0x0b86: return "mhpmcounter6h"; 2231 case 0x0b87: return "mhpmcounter7h"; 2232 case 0x0b88: return "mhpmcounter8h"; 2233 case 0x0b89: return "mhpmcounter9h"; 2234 case 0x0b8a: return "mhpmcounter10h"; 2235 case 0x0b8b: return "mhpmcounter11h"; 2236 case 0x0b8c: return "mhpmcounter12h"; 2237 case 0x0b8d: return "mhpmcounter13h"; 2238 case 0x0b8e: return "mhpmcounter14h"; 2239 case 0x0b8f: return "mhpmcounter15h"; 2240 case 0x0b90: return "mhpmcounter16h"; 2241 case 0x0b91: return "mhpmcounter17h"; 2242 case 0x0b92: return "mhpmcounter18h"; 2243 case 0x0b93: return "mhpmcounter19h"; 2244 case 0x0b94: return "mhpmcounter20h"; 2245 case 0x0b95: return "mhpmcounter21h"; 2246 case 0x0b96: return "mhpmcounter22h"; 2247 case 0x0b97: return "mhpmcounter23h"; 2248 case 0x0b98: return "mhpmcounter24h"; 2249 case 0x0b99: return "mhpmcounter25h"; 2250 case 0x0b9a: return "mhpmcounter26h"; 2251 case 0x0b9b: return "mhpmcounter27h"; 2252 case 0x0b9c: return "mhpmcounter28h"; 2253 case 0x0b9d: return "mhpmcounter29h"; 2254 case 0x0b9e: return "mhpmcounter30h"; 2255 case 0x0b9f: return "mhpmcounter31h"; 2256 case 0x0c00: return "cycle"; 2257 case 0x0c01: return "time"; 2258 case 0x0c02: return "instret"; 2259 case 0x0c20: return "vl"; 2260 case 0x0c21: return "vtype"; 2261 case 0x0c22: return "vlenb"; 2262 case 0x0c80: return "cycleh"; 2263 case 0x0c81: return "timeh"; 2264 case 0x0c82: return "instreth"; 2265 case 0x0d00: return "scycle"; 2266 case 0x0d01: return "stime"; 2267 case 0x0d02: return "sinstret"; 2268 case 0x0d80: return "scycleh"; 2269 case 0x0d81: return "stimeh"; 2270 case 0x0d82: return "sinstreth"; 2271 case 0x0e00: return "hcycle"; 2272 case 0x0e01: return "htime"; 2273 case 0x0e02: return "hinstret"; 2274 case 0x0e80: return "hcycleh"; 2275 case 0x0e81: return "htimeh"; 2276 case 0x0e82: return "hinstreth"; 2277 case 0x0f11: return "mvendorid"; 2278 case 0x0f12: return "marchid"; 2279 case 0x0f13: return "mimpid"; 2280 case 0x0f14: return "mhartid"; 2281 default: return NULL; 2282 } 2283 } 2284 2285 /* decode opcode */ 2286 2287 static void decode_inst_opcode(rv_decode *dec, rv_isa isa) 2288 { 2289 rv_inst inst = dec->inst; 2290 rv_opcode op = rv_op_illegal; 2291 switch (((inst >> 0) & 0b11)) { 2292 case 0: 2293 switch (((inst >> 13) & 0b111)) { 2294 case 0: op = rv_op_c_addi4spn; break; 2295 case 1: 2296 if (isa == rv128) { 2297 op = rv_op_c_lq; 2298 } else { 2299 op = rv_op_c_fld; 2300 } 2301 break; 2302 case 2: op = rv_op_c_lw; break; 2303 case 3: 2304 if (isa == rv32) { 2305 op = rv_op_c_flw; 2306 } else { 2307 op = rv_op_c_ld; 2308 } 2309 break; 2310 case 5: 2311 if (isa == rv128) { 2312 op = rv_op_c_sq; 2313 } else { 2314 op = rv_op_c_fsd; 2315 } 2316 break; 2317 case 6: op = rv_op_c_sw; break; 2318 case 7: 2319 if (isa == rv32) { 2320 op = rv_op_c_fsw; 2321 } else { 2322 op = rv_op_c_sd; 2323 } 2324 break; 2325 } 2326 break; 2327 case 1: 2328 switch (((inst >> 13) & 0b111)) { 2329 case 0: 2330 switch (((inst >> 2) & 0b11111111111)) { 2331 case 0: op = rv_op_c_nop; break; 2332 default: op = rv_op_c_addi; break; 2333 } 2334 break; 2335 case 1: 2336 if (isa == rv32) { 2337 op = rv_op_c_jal; 2338 } else { 2339 op = rv_op_c_addiw; 2340 } 2341 break; 2342 case 2: op = rv_op_c_li; break; 2343 case 3: 2344 switch (((inst >> 7) & 0b11111)) { 2345 case 2: op = rv_op_c_addi16sp; break; 2346 default: op = rv_op_c_lui; break; 2347 } 2348 break; 2349 case 4: 2350 switch (((inst >> 10) & 0b11)) { 2351 case 0: 2352 op = rv_op_c_srli; 2353 break; 2354 case 1: 2355 op = rv_op_c_srai; 2356 break; 2357 case 2: op = rv_op_c_andi; break; 2358 case 3: 2359 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) { 2360 case 0: op = rv_op_c_sub; break; 2361 case 1: op = rv_op_c_xor; break; 2362 case 2: op = rv_op_c_or; break; 2363 case 3: op = rv_op_c_and; break; 2364 case 4: op = rv_op_c_subw; break; 2365 case 5: op = rv_op_c_addw; break; 2366 } 2367 break; 2368 } 2369 break; 2370 case 5: op = rv_op_c_j; break; 2371 case 6: op = rv_op_c_beqz; break; 2372 case 7: op = rv_op_c_bnez; break; 2373 } 2374 break; 2375 case 2: 2376 switch (((inst >> 13) & 0b111)) { 2377 case 0: 2378 op = rv_op_c_slli; 2379 break; 2380 case 1: 2381 if (isa == rv128) { 2382 op = rv_op_c_lqsp; 2383 } else { 2384 op = rv_op_c_fldsp; 2385 } 2386 break; 2387 case 2: op = rv_op_c_lwsp; break; 2388 case 3: 2389 if (isa == rv32) { 2390 op = rv_op_c_flwsp; 2391 } else { 2392 op = rv_op_c_ldsp; 2393 } 2394 break; 2395 case 4: 2396 switch (((inst >> 12) & 0b1)) { 2397 case 0: 2398 switch (((inst >> 2) & 0b11111)) { 2399 case 0: op = rv_op_c_jr; break; 2400 default: op = rv_op_c_mv; break; 2401 } 2402 break; 2403 case 1: 2404 switch (((inst >> 2) & 0b11111)) { 2405 case 0: 2406 switch (((inst >> 7) & 0b11111)) { 2407 case 0: op = rv_op_c_ebreak; break; 2408 default: op = rv_op_c_jalr; break; 2409 } 2410 break; 2411 default: op = rv_op_c_add; break; 2412 } 2413 break; 2414 } 2415 break; 2416 case 5: 2417 if (isa == rv128) { 2418 op = rv_op_c_sqsp; 2419 } else { 2420 op = rv_op_c_fsdsp; 2421 } 2422 break; 2423 case 6: op = rv_op_c_swsp; break; 2424 case 7: 2425 if (isa == rv32) { 2426 op = rv_op_c_fswsp; 2427 } else { 2428 op = rv_op_c_sdsp; 2429 } 2430 break; 2431 } 2432 break; 2433 case 3: 2434 switch (((inst >> 2) & 0b11111)) { 2435 case 0: 2436 switch (((inst >> 12) & 0b111)) { 2437 case 0: op = rv_op_lb; break; 2438 case 1: op = rv_op_lh; break; 2439 case 2: op = rv_op_lw; break; 2440 case 3: op = rv_op_ld; break; 2441 case 4: op = rv_op_lbu; break; 2442 case 5: op = rv_op_lhu; break; 2443 case 6: op = rv_op_lwu; break; 2444 case 7: op = rv_op_ldu; break; 2445 } 2446 break; 2447 case 1: 2448 switch (((inst >> 12) & 0b111)) { 2449 case 0: 2450 switch (((inst >> 20) & 0b111111111111)) { 2451 case 40: op = rv_op_vl1re8_v; break; 2452 case 552: op = rv_op_vl2re8_v; break; 2453 case 1576: op = rv_op_vl4re8_v; break; 2454 case 3624: op = rv_op_vl8re8_v; break; 2455 } 2456 switch (((inst >> 26) & 0b111)) { 2457 case 0: 2458 switch (((inst >> 20) & 0b11111)) { 2459 case 0: op = rv_op_vle8_v; break; 2460 case 11: op = rv_op_vlm_v; break; 2461 case 16: op = rv_op_vle8ff_v; break; 2462 } 2463 break; 2464 case 1: op = rv_op_vluxei8_v; break; 2465 case 2: op = rv_op_vlse8_v; break; 2466 case 3: op = rv_op_vloxei8_v; break; 2467 } 2468 break; 2469 case 2: op = rv_op_flw; break; 2470 case 3: op = rv_op_fld; break; 2471 case 4: op = rv_op_flq; break; 2472 case 5: 2473 switch (((inst >> 20) & 0b111111111111)) { 2474 case 40: op = rv_op_vl1re16_v; break; 2475 case 552: op = rv_op_vl2re16_v; break; 2476 case 1576: op = rv_op_vl4re16_v; break; 2477 case 3624: op = rv_op_vl8re16_v; break; 2478 } 2479 switch (((inst >> 26) & 0b111)) { 2480 case 0: 2481 switch (((inst >> 20) & 0b11111)) { 2482 case 0: op = rv_op_vle16_v; break; 2483 case 16: op = rv_op_vle16ff_v; break; 2484 } 2485 break; 2486 case 1: op = rv_op_vluxei16_v; break; 2487 case 2: op = rv_op_vlse16_v; break; 2488 case 3: op = rv_op_vloxei16_v; break; 2489 } 2490 break; 2491 case 6: 2492 switch (((inst >> 20) & 0b111111111111)) { 2493 case 40: op = rv_op_vl1re32_v; break; 2494 case 552: op = rv_op_vl2re32_v; break; 2495 case 1576: op = rv_op_vl4re32_v; break; 2496 case 3624: op = rv_op_vl8re32_v; break; 2497 } 2498 switch (((inst >> 26) & 0b111)) { 2499 case 0: 2500 switch (((inst >> 20) & 0b11111)) { 2501 case 0: op = rv_op_vle32_v; break; 2502 case 16: op = rv_op_vle32ff_v; break; 2503 } 2504 break; 2505 case 1: op = rv_op_vluxei32_v; break; 2506 case 2: op = rv_op_vlse32_v; break; 2507 case 3: op = rv_op_vloxei32_v; break; 2508 } 2509 break; 2510 case 7: 2511 switch (((inst >> 20) & 0b111111111111)) { 2512 case 40: op = rv_op_vl1re64_v; break; 2513 case 552: op = rv_op_vl2re64_v; break; 2514 case 1576: op = rv_op_vl4re64_v; break; 2515 case 3624: op = rv_op_vl8re64_v; break; 2516 } 2517 switch (((inst >> 26) & 0b111)) { 2518 case 0: 2519 switch (((inst >> 20) & 0b11111)) { 2520 case 0: op = rv_op_vle64_v; break; 2521 case 16: op = rv_op_vle64ff_v; break; 2522 } 2523 break; 2524 case 1: op = rv_op_vluxei64_v; break; 2525 case 2: op = rv_op_vlse64_v; break; 2526 case 3: op = rv_op_vloxei64_v; break; 2527 } 2528 break; 2529 } 2530 break; 2531 case 3: 2532 switch (((inst >> 12) & 0b111)) { 2533 case 0: op = rv_op_fence; break; 2534 case 1: op = rv_op_fence_i; break; 2535 case 2: op = rv_op_lq; break; 2536 } 2537 break; 2538 case 4: 2539 switch (((inst >> 12) & 0b111)) { 2540 case 0: op = rv_op_addi; break; 2541 case 1: 2542 switch (((inst >> 27) & 0b11111)) { 2543 case 0b00000: op = rv_op_slli; break; 2544 case 0b00001: 2545 switch (((inst >> 20) & 0b1111111)) { 2546 case 0b0001111: op = rv_op_zip; break; 2547 } 2548 break; 2549 case 0b00010: 2550 switch (((inst >> 20) & 0b1111111)) { 2551 case 0b0000000: op = rv_op_sha256sum0; break; 2552 case 0b0000001: op = rv_op_sha256sum1; break; 2553 case 0b0000010: op = rv_op_sha256sig0; break; 2554 case 0b0000011: op = rv_op_sha256sig1; break; 2555 case 0b0000100: op = rv_op_sha512sum0; break; 2556 case 0b0000101: op = rv_op_sha512sum1; break; 2557 case 0b0000110: op = rv_op_sha512sig0; break; 2558 case 0b0000111: op = rv_op_sha512sig1; break; 2559 case 0b0001000: op = rv_op_sm3p0; break; 2560 case 0b0001001: op = rv_op_sm3p1; break; 2561 } 2562 break; 2563 case 0b00101: op = rv_op_bseti; break; 2564 case 0b00110: 2565 switch (((inst >> 20) & 0b1111111)) { 2566 case 0b0000000: op = rv_op_aes64im; break; 2567 default: 2568 if (((inst >> 24) & 0b0111) == 0b001) { 2569 op = rv_op_aes64ks1i; 2570 } 2571 break; 2572 } 2573 break; 2574 case 0b01001: op = rv_op_bclri; break; 2575 case 0b01101: op = rv_op_binvi; break; 2576 case 0b01100: 2577 switch (((inst >> 20) & 0b1111111)) { 2578 case 0b0000000: op = rv_op_clz; break; 2579 case 0b0000001: op = rv_op_ctz; break; 2580 case 0b0000010: op = rv_op_cpop; break; 2581 /* 0b0000011 */ 2582 case 0b0000100: op = rv_op_sext_b; break; 2583 case 0b0000101: op = rv_op_sext_h; break; 2584 } 2585 break; 2586 } 2587 break; 2588 case 2: op = rv_op_slti; break; 2589 case 3: op = rv_op_sltiu; break; 2590 case 4: op = rv_op_xori; break; 2591 case 5: 2592 switch (((inst >> 27) & 0b11111)) { 2593 case 0b00000: op = rv_op_srli; break; 2594 case 0b00001: 2595 switch (((inst >> 20) & 0b1111111)) { 2596 case 0b0001111: op = rv_op_unzip; break; 2597 } 2598 break; 2599 case 0b00101: op = rv_op_orc_b; break; 2600 case 0b01000: op = rv_op_srai; break; 2601 case 0b01001: op = rv_op_bexti; break; 2602 case 0b01100: op = rv_op_rori; break; 2603 case 0b01101: 2604 switch ((inst >> 20) & 0b1111111) { 2605 case 0b0011000: op = rv_op_rev8; break; 2606 case 0b0111000: op = rv_op_rev8; break; 2607 case 0b0000111: op = rv_op_brev8; break; 2608 } 2609 break; 2610 } 2611 break; 2612 case 6: op = rv_op_ori; break; 2613 case 7: op = rv_op_andi; break; 2614 } 2615 break; 2616 case 5: op = rv_op_auipc; break; 2617 case 6: 2618 switch (((inst >> 12) & 0b111)) { 2619 case 0: op = rv_op_addiw; break; 2620 case 1: 2621 switch (((inst >> 26) & 0b111111)) { 2622 case 0: op = rv_op_slliw; break; 2623 case 2: op = rv_op_slli_uw; break; 2624 case 24: 2625 switch ((inst >> 20) & 0b11111) { 2626 case 0b00000: op = rv_op_clzw; break; 2627 case 0b00001: op = rv_op_ctzw; break; 2628 case 0b00010: op = rv_op_cpopw; break; 2629 } 2630 break; 2631 } 2632 break; 2633 case 5: 2634 switch (((inst >> 25) & 0b1111111)) { 2635 case 0: op = rv_op_srliw; break; 2636 case 32: op = rv_op_sraiw; break; 2637 case 48: op = rv_op_roriw; break; 2638 } 2639 break; 2640 } 2641 break; 2642 case 8: 2643 switch (((inst >> 12) & 0b111)) { 2644 case 0: op = rv_op_sb; break; 2645 case 1: op = rv_op_sh; break; 2646 case 2: op = rv_op_sw; break; 2647 case 3: op = rv_op_sd; break; 2648 case 4: op = rv_op_sq; break; 2649 } 2650 break; 2651 case 9: 2652 switch (((inst >> 12) & 0b111)) { 2653 case 0: 2654 switch (((inst >> 20) & 0b111111111111)) { 2655 case 40: op = rv_op_vs1r_v; break; 2656 case 552: op = rv_op_vs2r_v; break; 2657 case 1576: op = rv_op_vs4r_v; break; 2658 case 3624: op = rv_op_vs8r_v; break; 2659 } 2660 switch (((inst >> 26) & 0b111)) { 2661 case 0: 2662 switch (((inst >> 20) & 0b11111)) { 2663 case 0: op = rv_op_vse8_v; break; 2664 case 11: op = rv_op_vsm_v; break; 2665 } 2666 break; 2667 case 1: op = rv_op_vsuxei8_v; break; 2668 case 2: op = rv_op_vsse8_v; break; 2669 case 3: op = rv_op_vsoxei8_v; break; 2670 } 2671 break; 2672 case 2: op = rv_op_fsw; break; 2673 case 3: op = rv_op_fsd; break; 2674 case 4: op = rv_op_fsq; break; 2675 case 5: 2676 switch (((inst >> 26) & 0b111)) { 2677 case 0: 2678 switch (((inst >> 20) & 0b11111)) { 2679 case 0: op = rv_op_vse16_v; break; 2680 } 2681 break; 2682 case 1: op = rv_op_vsuxei16_v; break; 2683 case 2: op = rv_op_vsse16_v; break; 2684 case 3: op = rv_op_vsoxei16_v; break; 2685 } 2686 break; 2687 case 6: 2688 switch (((inst >> 26) & 0b111)) { 2689 case 0: 2690 switch (((inst >> 20) & 0b11111)) { 2691 case 0: op = rv_op_vse32_v; break; 2692 } 2693 break; 2694 case 1: op = rv_op_vsuxei32_v; break; 2695 case 2: op = rv_op_vsse32_v; break; 2696 case 3: op = rv_op_vsoxei32_v; break; 2697 } 2698 break; 2699 case 7: 2700 switch (((inst >> 26) & 0b111)) { 2701 case 0: 2702 switch (((inst >> 20) & 0b11111)) { 2703 case 0: op = rv_op_vse64_v; break; 2704 } 2705 break; 2706 case 1: op = rv_op_vsuxei64_v; break; 2707 case 2: op = rv_op_vsse64_v; break; 2708 case 3: op = rv_op_vsoxei64_v; break; 2709 } 2710 break; 2711 } 2712 break; 2713 case 11: 2714 switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 2715 case 2: op = rv_op_amoadd_w; break; 2716 case 3: op = rv_op_amoadd_d; break; 2717 case 4: op = rv_op_amoadd_q; break; 2718 case 10: op = rv_op_amoswap_w; break; 2719 case 11: op = rv_op_amoswap_d; break; 2720 case 12: op = rv_op_amoswap_q; break; 2721 case 18: 2722 switch (((inst >> 20) & 0b11111)) { 2723 case 0: op = rv_op_lr_w; break; 2724 } 2725 break; 2726 case 19: 2727 switch (((inst >> 20) & 0b11111)) { 2728 case 0: op = rv_op_lr_d; break; 2729 } 2730 break; 2731 case 20: 2732 switch (((inst >> 20) & 0b11111)) { 2733 case 0: op = rv_op_lr_q; break; 2734 } 2735 break; 2736 case 26: op = rv_op_sc_w; break; 2737 case 27: op = rv_op_sc_d; break; 2738 case 28: op = rv_op_sc_q; break; 2739 case 34: op = rv_op_amoxor_w; break; 2740 case 35: op = rv_op_amoxor_d; break; 2741 case 36: op = rv_op_amoxor_q; break; 2742 case 66: op = rv_op_amoor_w; break; 2743 case 67: op = rv_op_amoor_d; break; 2744 case 68: op = rv_op_amoor_q; break; 2745 case 98: op = rv_op_amoand_w; break; 2746 case 99: op = rv_op_amoand_d; break; 2747 case 100: op = rv_op_amoand_q; break; 2748 case 130: op = rv_op_amomin_w; break; 2749 case 131: op = rv_op_amomin_d; break; 2750 case 132: op = rv_op_amomin_q; break; 2751 case 162: op = rv_op_amomax_w; break; 2752 case 163: op = rv_op_amomax_d; break; 2753 case 164: op = rv_op_amomax_q; break; 2754 case 194: op = rv_op_amominu_w; break; 2755 case 195: op = rv_op_amominu_d; break; 2756 case 196: op = rv_op_amominu_q; break; 2757 case 226: op = rv_op_amomaxu_w; break; 2758 case 227: op = rv_op_amomaxu_d; break; 2759 case 228: op = rv_op_amomaxu_q; break; 2760 } 2761 break; 2762 case 12: 2763 switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { 2764 case 0: op = rv_op_add; break; 2765 case 1: op = rv_op_sll; break; 2766 case 2: op = rv_op_slt; break; 2767 case 3: op = rv_op_sltu; break; 2768 case 4: op = rv_op_xor; break; 2769 case 5: op = rv_op_srl; break; 2770 case 6: op = rv_op_or; break; 2771 case 7: op = rv_op_and; break; 2772 case 8: op = rv_op_mul; break; 2773 case 9: op = rv_op_mulh; break; 2774 case 10: op = rv_op_mulhsu; break; 2775 case 11: op = rv_op_mulhu; break; 2776 case 12: op = rv_op_div; break; 2777 case 13: op = rv_op_divu; break; 2778 case 14: op = rv_op_rem; break; 2779 case 15: op = rv_op_remu; break; 2780 case 36: 2781 switch ((inst >> 20) & 0b11111) { 2782 case 0: op = rv_op_zext_h; break; 2783 default: op = rv_op_pack; break; 2784 } 2785 break; 2786 case 39: op = rv_op_packh; break; 2787 2788 case 41: op = rv_op_clmul; break; 2789 case 42: op = rv_op_clmulr; break; 2790 case 43: op = rv_op_clmulh; break; 2791 case 44: op = rv_op_min; break; 2792 case 45: op = rv_op_minu; break; 2793 case 46: op = rv_op_max; break; 2794 case 47: op = rv_op_maxu; break; 2795 case 130: op = rv_op_sh1add; break; 2796 case 132: op = rv_op_sh2add; break; 2797 case 134: op = rv_op_sh3add; break; 2798 case 161: op = rv_op_bset; break; 2799 case 162: op = rv_op_xperm4; break; 2800 case 164: op = rv_op_xperm8; break; 2801 case 200: op = rv_op_aes64es; break; 2802 case 216: op = rv_op_aes64esm; break; 2803 case 232: op = rv_op_aes64ds; break; 2804 case 248: op = rv_op_aes64dsm; break; 2805 case 256: op = rv_op_sub; break; 2806 case 260: op = rv_op_xnor; break; 2807 case 261: op = rv_op_sra; break; 2808 case 262: op = rv_op_orn; break; 2809 case 263: op = rv_op_andn; break; 2810 case 289: op = rv_op_bclr; break; 2811 case 293: op = rv_op_bext; break; 2812 case 320: op = rv_op_sha512sum0r; break; 2813 case 328: op = rv_op_sha512sum1r; break; 2814 case 336: op = rv_op_sha512sig0l; break; 2815 case 344: op = rv_op_sha512sig1l; break; 2816 case 368: op = rv_op_sha512sig0h; break; 2817 case 376: op = rv_op_sha512sig1h; break; 2818 case 385: op = rv_op_rol; break; 2819 case 389: op = rv_op_ror; break; 2820 case 417: op = rv_op_binv; break; 2821 case 504: op = rv_op_aes64ks2; break; 2822 } 2823 switch ((inst >> 25) & 0b0011111) { 2824 case 17: op = rv_op_aes32esi; break; 2825 case 19: op = rv_op_aes32esmi; break; 2826 case 21: op = rv_op_aes32dsi; break; 2827 case 23: op = rv_op_aes32dsmi; break; 2828 case 24: op = rv_op_sm4ed; break; 2829 case 26: op = rv_op_sm4ks; break; 2830 } 2831 break; 2832 case 13: op = rv_op_lui; break; 2833 case 14: 2834 switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { 2835 case 0: op = rv_op_addw; break; 2836 case 1: op = rv_op_sllw; break; 2837 case 5: op = rv_op_srlw; break; 2838 case 8: op = rv_op_mulw; break; 2839 case 12: op = rv_op_divw; break; 2840 case 13: op = rv_op_divuw; break; 2841 case 14: op = rv_op_remw; break; 2842 case 15: op = rv_op_remuw; break; 2843 case 32: op = rv_op_add_uw; break; 2844 case 36: 2845 switch ((inst >> 20) & 0b11111) { 2846 case 0: op = rv_op_zext_h; break; 2847 default: op = rv_op_packw; break; 2848 } 2849 break; 2850 case 130: op = rv_op_sh1add_uw; break; 2851 case 132: op = rv_op_sh2add_uw; break; 2852 case 134: op = rv_op_sh3add_uw; break; 2853 case 256: op = rv_op_subw; break; 2854 case 261: op = rv_op_sraw; break; 2855 case 385: op = rv_op_rolw; break; 2856 case 389: op = rv_op_rorw; break; 2857 } 2858 break; 2859 case 16: 2860 switch (((inst >> 25) & 0b11)) { 2861 case 0: op = rv_op_fmadd_s; break; 2862 case 1: op = rv_op_fmadd_d; break; 2863 case 3: op = rv_op_fmadd_q; break; 2864 } 2865 break; 2866 case 17: 2867 switch (((inst >> 25) & 0b11)) { 2868 case 0: op = rv_op_fmsub_s; break; 2869 case 1: op = rv_op_fmsub_d; break; 2870 case 3: op = rv_op_fmsub_q; break; 2871 } 2872 break; 2873 case 18: 2874 switch (((inst >> 25) & 0b11)) { 2875 case 0: op = rv_op_fnmsub_s; break; 2876 case 1: op = rv_op_fnmsub_d; break; 2877 case 3: op = rv_op_fnmsub_q; break; 2878 } 2879 break; 2880 case 19: 2881 switch (((inst >> 25) & 0b11)) { 2882 case 0: op = rv_op_fnmadd_s; break; 2883 case 1: op = rv_op_fnmadd_d; break; 2884 case 3: op = rv_op_fnmadd_q; break; 2885 } 2886 break; 2887 case 20: 2888 switch (((inst >> 25) & 0b1111111)) { 2889 case 0: op = rv_op_fadd_s; break; 2890 case 1: op = rv_op_fadd_d; break; 2891 case 3: op = rv_op_fadd_q; break; 2892 case 4: op = rv_op_fsub_s; break; 2893 case 5: op = rv_op_fsub_d; break; 2894 case 7: op = rv_op_fsub_q; break; 2895 case 8: op = rv_op_fmul_s; break; 2896 case 9: op = rv_op_fmul_d; break; 2897 case 11: op = rv_op_fmul_q; break; 2898 case 12: op = rv_op_fdiv_s; break; 2899 case 13: op = rv_op_fdiv_d; break; 2900 case 15: op = rv_op_fdiv_q; break; 2901 case 16: 2902 switch (((inst >> 12) & 0b111)) { 2903 case 0: op = rv_op_fsgnj_s; break; 2904 case 1: op = rv_op_fsgnjn_s; break; 2905 case 2: op = rv_op_fsgnjx_s; break; 2906 } 2907 break; 2908 case 17: 2909 switch (((inst >> 12) & 0b111)) { 2910 case 0: op = rv_op_fsgnj_d; break; 2911 case 1: op = rv_op_fsgnjn_d; break; 2912 case 2: op = rv_op_fsgnjx_d; break; 2913 } 2914 break; 2915 case 19: 2916 switch (((inst >> 12) & 0b111)) { 2917 case 0: op = rv_op_fsgnj_q; break; 2918 case 1: op = rv_op_fsgnjn_q; break; 2919 case 2: op = rv_op_fsgnjx_q; break; 2920 } 2921 break; 2922 case 20: 2923 switch (((inst >> 12) & 0b111)) { 2924 case 0: op = rv_op_fmin_s; break; 2925 case 1: op = rv_op_fmax_s; break; 2926 } 2927 break; 2928 case 21: 2929 switch (((inst >> 12) & 0b111)) { 2930 case 0: op = rv_op_fmin_d; break; 2931 case 1: op = rv_op_fmax_d; break; 2932 } 2933 break; 2934 case 23: 2935 switch (((inst >> 12) & 0b111)) { 2936 case 0: op = rv_op_fmin_q; break; 2937 case 1: op = rv_op_fmax_q; break; 2938 } 2939 break; 2940 case 32: 2941 switch (((inst >> 20) & 0b11111)) { 2942 case 1: op = rv_op_fcvt_s_d; break; 2943 case 3: op = rv_op_fcvt_s_q; break; 2944 } 2945 break; 2946 case 33: 2947 switch (((inst >> 20) & 0b11111)) { 2948 case 0: op = rv_op_fcvt_d_s; break; 2949 case 3: op = rv_op_fcvt_d_q; break; 2950 } 2951 break; 2952 case 35: 2953 switch (((inst >> 20) & 0b11111)) { 2954 case 0: op = rv_op_fcvt_q_s; break; 2955 case 1: op = rv_op_fcvt_q_d; break; 2956 } 2957 break; 2958 case 44: 2959 switch (((inst >> 20) & 0b11111)) { 2960 case 0: op = rv_op_fsqrt_s; break; 2961 } 2962 break; 2963 case 45: 2964 switch (((inst >> 20) & 0b11111)) { 2965 case 0: op = rv_op_fsqrt_d; break; 2966 } 2967 break; 2968 case 47: 2969 switch (((inst >> 20) & 0b11111)) { 2970 case 0: op = rv_op_fsqrt_q; break; 2971 } 2972 break; 2973 case 80: 2974 switch (((inst >> 12) & 0b111)) { 2975 case 0: op = rv_op_fle_s; break; 2976 case 1: op = rv_op_flt_s; break; 2977 case 2: op = rv_op_feq_s; break; 2978 } 2979 break; 2980 case 81: 2981 switch (((inst >> 12) & 0b111)) { 2982 case 0: op = rv_op_fle_d; break; 2983 case 1: op = rv_op_flt_d; break; 2984 case 2: op = rv_op_feq_d; break; 2985 } 2986 break; 2987 case 83: 2988 switch (((inst >> 12) & 0b111)) { 2989 case 0: op = rv_op_fle_q; break; 2990 case 1: op = rv_op_flt_q; break; 2991 case 2: op = rv_op_feq_q; break; 2992 } 2993 break; 2994 case 96: 2995 switch (((inst >> 20) & 0b11111)) { 2996 case 0: op = rv_op_fcvt_w_s; break; 2997 case 1: op = rv_op_fcvt_wu_s; break; 2998 case 2: op = rv_op_fcvt_l_s; break; 2999 case 3: op = rv_op_fcvt_lu_s; break; 3000 } 3001 break; 3002 case 97: 3003 switch (((inst >> 20) & 0b11111)) { 3004 case 0: op = rv_op_fcvt_w_d; break; 3005 case 1: op = rv_op_fcvt_wu_d; break; 3006 case 2: op = rv_op_fcvt_l_d; break; 3007 case 3: op = rv_op_fcvt_lu_d; break; 3008 } 3009 break; 3010 case 99: 3011 switch (((inst >> 20) & 0b11111)) { 3012 case 0: op = rv_op_fcvt_w_q; break; 3013 case 1: op = rv_op_fcvt_wu_q; break; 3014 case 2: op = rv_op_fcvt_l_q; break; 3015 case 3: op = rv_op_fcvt_lu_q; break; 3016 } 3017 break; 3018 case 104: 3019 switch (((inst >> 20) & 0b11111)) { 3020 case 0: op = rv_op_fcvt_s_w; break; 3021 case 1: op = rv_op_fcvt_s_wu; break; 3022 case 2: op = rv_op_fcvt_s_l; break; 3023 case 3: op = rv_op_fcvt_s_lu; break; 3024 } 3025 break; 3026 case 105: 3027 switch (((inst >> 20) & 0b11111)) { 3028 case 0: op = rv_op_fcvt_d_w; break; 3029 case 1: op = rv_op_fcvt_d_wu; break; 3030 case 2: op = rv_op_fcvt_d_l; break; 3031 case 3: op = rv_op_fcvt_d_lu; break; 3032 } 3033 break; 3034 case 107: 3035 switch (((inst >> 20) & 0b11111)) { 3036 case 0: op = rv_op_fcvt_q_w; break; 3037 case 1: op = rv_op_fcvt_q_wu; break; 3038 case 2: op = rv_op_fcvt_q_l; break; 3039 case 3: op = rv_op_fcvt_q_lu; break; 3040 } 3041 break; 3042 case 112: 3043 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3044 case 0: op = rv_op_fmv_x_s; break; 3045 case 1: op = rv_op_fclass_s; break; 3046 } 3047 break; 3048 case 113: 3049 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3050 case 0: op = rv_op_fmv_x_d; break; 3051 case 1: op = rv_op_fclass_d; break; 3052 } 3053 break; 3054 case 115: 3055 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3056 case 0: op = rv_op_fmv_x_q; break; 3057 case 1: op = rv_op_fclass_q; break; 3058 } 3059 break; 3060 case 120: 3061 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3062 case 0: op = rv_op_fmv_s_x; break; 3063 } 3064 break; 3065 case 121: 3066 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3067 case 0: op = rv_op_fmv_d_x; break; 3068 } 3069 break; 3070 case 123: 3071 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) { 3072 case 0: op = rv_op_fmv_q_x; break; 3073 } 3074 break; 3075 } 3076 break; 3077 case 21: 3078 switch (((inst >> 12) & 0b111)) { 3079 case 0: 3080 switch (((inst >> 26) & 0b111111)) { 3081 case 0: op = rv_op_vadd_vv; break; 3082 case 2: op = rv_op_vsub_vv; break; 3083 case 4: op = rv_op_vminu_vv; break; 3084 case 5: op = rv_op_vmin_vv; break; 3085 case 6: op = rv_op_vmaxu_vv; break; 3086 case 7: op = rv_op_vmax_vv; break; 3087 case 9: op = rv_op_vand_vv; break; 3088 case 10: op = rv_op_vor_vv; break; 3089 case 11: op = rv_op_vxor_vv; break; 3090 case 12: op = rv_op_vrgather_vv; break; 3091 case 14: op = rv_op_vrgatherei16_vv; break; 3092 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break; 3093 case 17: op = rv_op_vmadc_vvm; break; 3094 case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break; 3095 case 19: op = rv_op_vmsbc_vvm; break; 3096 case 23: 3097 if (((inst >> 20) & 0b111111) == 32) 3098 op = rv_op_vmv_v_v; 3099 else if (((inst >> 25) & 1) == 0) 3100 op = rv_op_vmerge_vvm; 3101 break; 3102 case 24: op = rv_op_vmseq_vv; break; 3103 case 25: op = rv_op_vmsne_vv; break; 3104 case 26: op = rv_op_vmsltu_vv; break; 3105 case 27: op = rv_op_vmslt_vv; break; 3106 case 28: op = rv_op_vmsleu_vv; break; 3107 case 29: op = rv_op_vmsle_vv; break; 3108 case 32: op = rv_op_vsaddu_vv; break; 3109 case 33: op = rv_op_vsadd_vv; break; 3110 case 34: op = rv_op_vssubu_vv; break; 3111 case 35: op = rv_op_vssub_vv; break; 3112 case 37: op = rv_op_vsll_vv; break; 3113 case 39: op = rv_op_vsmul_vv; break; 3114 case 40: op = rv_op_vsrl_vv; break; 3115 case 41: op = rv_op_vsra_vv; break; 3116 case 42: op = rv_op_vssrl_vv; break; 3117 case 43: op = rv_op_vssra_vv; break; 3118 case 44: op = rv_op_vnsrl_wv; break; 3119 case 45: op = rv_op_vnsra_wv; break; 3120 case 46: op = rv_op_vnclipu_wv; break; 3121 case 47: op = rv_op_vnclip_wv; break; 3122 case 48: op = rv_op_vwredsumu_vs; break; 3123 case 49: op = rv_op_vwredsum_vs; break; 3124 } 3125 break; 3126 case 1: 3127 switch (((inst >> 26) & 0b111111)) { 3128 case 0: op = rv_op_vfadd_vv; break; 3129 case 1: op = rv_op_vfredusum_vs; break; 3130 case 2: op = rv_op_vfsub_vv; break; 3131 case 3: op = rv_op_vfredosum_vs; break; 3132 case 4: op = rv_op_vfmin_vv; break; 3133 case 5: op = rv_op_vfredmin_vs; break; 3134 case 6: op = rv_op_vfmax_vv; break; 3135 case 7: op = rv_op_vfredmax_vs; break; 3136 case 8: op = rv_op_vfsgnj_vv; break; 3137 case 9: op = rv_op_vfsgnjn_vv; break; 3138 case 10: op = rv_op_vfsgnjx_vv; break; 3139 case 16: 3140 switch (((inst >> 15) & 0b11111)) { 3141 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break; 3142 } 3143 break; 3144 case 18: 3145 switch (((inst >> 15) & 0b11111)) { 3146 case 0: op = rv_op_vfcvt_xu_f_v; break; 3147 case 1: op = rv_op_vfcvt_x_f_v; break; 3148 case 2: op = rv_op_vfcvt_f_xu_v; break; 3149 case 3: op = rv_op_vfcvt_f_x_v; break; 3150 case 6: op = rv_op_vfcvt_rtz_xu_f_v; break; 3151 case 7: op = rv_op_vfcvt_rtz_x_f_v; break; 3152 case 8: op = rv_op_vfwcvt_xu_f_v; break; 3153 case 9: op = rv_op_vfwcvt_x_f_v; break; 3154 case 10: op = rv_op_vfwcvt_f_xu_v; break; 3155 case 11: op = rv_op_vfwcvt_f_x_v; break; 3156 case 12: op = rv_op_vfwcvt_f_f_v; break; 3157 case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break; 3158 case 15: op = rv_op_vfwcvt_rtz_x_f_v; break; 3159 case 16: op = rv_op_vfncvt_xu_f_w; break; 3160 case 17: op = rv_op_vfncvt_x_f_w; break; 3161 case 18: op = rv_op_vfncvt_f_xu_w; break; 3162 case 19: op = rv_op_vfncvt_f_x_w; break; 3163 case 20: op = rv_op_vfncvt_f_f_w; break; 3164 case 21: op = rv_op_vfncvt_rod_f_f_w; break; 3165 case 22: op = rv_op_vfncvt_rtz_xu_f_w; break; 3166 case 23: op = rv_op_vfncvt_rtz_x_f_w; break; 3167 } 3168 break; 3169 case 19: 3170 switch (((inst >> 15) & 0b11111)) { 3171 case 0: op = rv_op_vfsqrt_v; break; 3172 case 4: op = rv_op_vfrsqrt7_v; break; 3173 case 5: op = rv_op_vfrec7_v; break; 3174 case 16: op = rv_op_vfclass_v; break; 3175 } 3176 break; 3177 case 24: op = rv_op_vmfeq_vv; break; 3178 case 25: op = rv_op_vmfle_vv; break; 3179 case 27: op = rv_op_vmflt_vv; break; 3180 case 28: op = rv_op_vmfne_vv; break; 3181 case 32: op = rv_op_vfdiv_vv; break; 3182 case 36: op = rv_op_vfmul_vv; break; 3183 case 40: op = rv_op_vfmadd_vv; break; 3184 case 41: op = rv_op_vfnmadd_vv; break; 3185 case 42: op = rv_op_vfmsub_vv; break; 3186 case 43: op = rv_op_vfnmsub_vv; break; 3187 case 44: op = rv_op_vfmacc_vv; break; 3188 case 45: op = rv_op_vfnmacc_vv; break; 3189 case 46: op = rv_op_vfmsac_vv; break; 3190 case 47: op = rv_op_vfnmsac_vv; break; 3191 case 48: op = rv_op_vfwadd_vv; break; 3192 case 49: op = rv_op_vfwredusum_vs; break; 3193 case 50: op = rv_op_vfwsub_vv; break; 3194 case 51: op = rv_op_vfwredosum_vs; break; 3195 case 52: op = rv_op_vfwadd_wv; break; 3196 case 54: op = rv_op_vfwsub_wv; break; 3197 case 56: op = rv_op_vfwmul_vv; break; 3198 case 60: op = rv_op_vfwmacc_vv; break; 3199 case 61: op = rv_op_vfwnmacc_vv; break; 3200 case 62: op = rv_op_vfwmsac_vv; break; 3201 case 63: op = rv_op_vfwnmsac_vv; break; 3202 } 3203 break; 3204 case 2: 3205 switch (((inst >> 26) & 0b111111)) { 3206 case 0: op = rv_op_vredsum_vs; break; 3207 case 1: op = rv_op_vredand_vs; break; 3208 case 2: op = rv_op_vredor_vs; break; 3209 case 3: op = rv_op_vredxor_vs; break; 3210 case 4: op = rv_op_vredminu_vs; break; 3211 case 5: op = rv_op_vredmin_vs; break; 3212 case 6: op = rv_op_vredmaxu_vs; break; 3213 case 7: op = rv_op_vredmax_vs; break; 3214 case 8: op = rv_op_vaaddu_vv; break; 3215 case 9: op = rv_op_vaadd_vv; break; 3216 case 10: op = rv_op_vasubu_vv; break; 3217 case 11: op = rv_op_vasub_vv; break; 3218 case 16: 3219 switch (((inst >> 15) & 0b11111)) { 3220 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break; 3221 case 16: op = rv_op_vcpop_m; break; 3222 case 17: op = rv_op_vfirst_m; break; 3223 } 3224 break; 3225 case 18: 3226 switch (((inst >> 15) & 0b11111)) { 3227 case 2: op = rv_op_vzext_vf8; break; 3228 case 3: op = rv_op_vsext_vf8; break; 3229 case 4: op = rv_op_vzext_vf4; break; 3230 case 5: op = rv_op_vsext_vf4; break; 3231 case 6: op = rv_op_vzext_vf2; break; 3232 case 7: op = rv_op_vsext_vf2; break; 3233 } 3234 break; 3235 case 20: 3236 switch (((inst >> 15) & 0b11111)) { 3237 case 1: op = rv_op_vmsbf_m; break; 3238 case 2: op = rv_op_vmsof_m; break; 3239 case 3: op = rv_op_vmsif_m; break; 3240 case 16: op = rv_op_viota_m; break; 3241 case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break; 3242 } 3243 break; 3244 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break; 3245 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break; 3246 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break; 3247 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break; 3248 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break; 3249 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break; 3250 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break; 3251 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break; 3252 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break; 3253 case 32: op = rv_op_vdivu_vv; break; 3254 case 33: op = rv_op_vdiv_vv; break; 3255 case 34: op = rv_op_vremu_vv; break; 3256 case 35: op = rv_op_vrem_vv; break; 3257 case 36: op = rv_op_vmulhu_vv; break; 3258 case 37: op = rv_op_vmul_vv; break; 3259 case 38: op = rv_op_vmulhsu_vv; break; 3260 case 39: op = rv_op_vmulh_vv; break; 3261 case 41: op = rv_op_vmadd_vv; break; 3262 case 43: op = rv_op_vnmsub_vv; break; 3263 case 45: op = rv_op_vmacc_vv; break; 3264 case 47: op = rv_op_vnmsac_vv; break; 3265 case 48: op = rv_op_vwaddu_vv; break; 3266 case 49: op = rv_op_vwadd_vv; break; 3267 case 50: op = rv_op_vwsubu_vv; break; 3268 case 51: op = rv_op_vwsub_vv; break; 3269 case 52: op = rv_op_vwaddu_wv; break; 3270 case 53: op = rv_op_vwadd_wv; break; 3271 case 54: op = rv_op_vwsubu_wv; break; 3272 case 55: op = rv_op_vwsub_wv; break; 3273 case 56: op = rv_op_vwmulu_vv; break; 3274 case 58: op = rv_op_vwmulsu_vv; break; 3275 case 59: op = rv_op_vwmul_vv; break; 3276 case 60: op = rv_op_vwmaccu_vv; break; 3277 case 61: op = rv_op_vwmacc_vv; break; 3278 case 63: op = rv_op_vwmaccsu_vv; break; 3279 } 3280 break; 3281 case 3: 3282 switch (((inst >> 26) & 0b111111)) { 3283 case 0: op = rv_op_vadd_vi; break; 3284 case 3: op = rv_op_vrsub_vi; break; 3285 case 9: op = rv_op_vand_vi; break; 3286 case 10: op = rv_op_vor_vi; break; 3287 case 11: op = rv_op_vxor_vi; break; 3288 case 12: op = rv_op_vrgather_vi; break; 3289 case 14: op = rv_op_vslideup_vi; break; 3290 case 15: op = rv_op_vslidedown_vi; break; 3291 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break; 3292 case 17: op = rv_op_vmadc_vim; break; 3293 case 23: 3294 if (((inst >> 20) & 0b111111) == 32) 3295 op = rv_op_vmv_v_i; 3296 else if (((inst >> 25) & 1) == 0) 3297 op = rv_op_vmerge_vim; 3298 break; 3299 case 24: op = rv_op_vmseq_vi; break; 3300 case 25: op = rv_op_vmsne_vi; break; 3301 case 28: op = rv_op_vmsleu_vi; break; 3302 case 29: op = rv_op_vmsle_vi; break; 3303 case 30: op = rv_op_vmsgtu_vi; break; 3304 case 31: op = rv_op_vmsgt_vi; break; 3305 case 32: op = rv_op_vsaddu_vi; break; 3306 case 33: op = rv_op_vsadd_vi; break; 3307 case 37: op = rv_op_vsll_vi; break; 3308 case 39: 3309 switch (((inst >> 15) & 0b11111)) { 3310 case 0: op = rv_op_vmv1r_v; break; 3311 case 1: op = rv_op_vmv2r_v; break; 3312 case 3: op = rv_op_vmv4r_v; break; 3313 case 7: op = rv_op_vmv8r_v; break; 3314 } 3315 break; 3316 case 40: op = rv_op_vsrl_vi; break; 3317 case 41: op = rv_op_vsra_vi; break; 3318 case 42: op = rv_op_vssrl_vi; break; 3319 case 43: op = rv_op_vssra_vi; break; 3320 case 44: op = rv_op_vnsrl_wi; break; 3321 case 45: op = rv_op_vnsra_wi; break; 3322 case 46: op = rv_op_vnclipu_wi; break; 3323 case 47: op = rv_op_vnclip_wi; break; 3324 } 3325 break; 3326 case 4: 3327 switch (((inst >> 26) & 0b111111)) { 3328 case 0: op = rv_op_vadd_vx; break; 3329 case 2: op = rv_op_vsub_vx; break; 3330 case 3: op = rv_op_vrsub_vx; break; 3331 case 4: op = rv_op_vminu_vx; break; 3332 case 5: op = rv_op_vmin_vx; break; 3333 case 6: op = rv_op_vmaxu_vx; break; 3334 case 7: op = rv_op_vmax_vx; break; 3335 case 9: op = rv_op_vand_vx; break; 3336 case 10: op = rv_op_vor_vx; break; 3337 case 11: op = rv_op_vxor_vx; break; 3338 case 12: op = rv_op_vrgather_vx; break; 3339 case 14: op = rv_op_vslideup_vx; break; 3340 case 15: op = rv_op_vslidedown_vx; break; 3341 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break; 3342 case 17: op = rv_op_vmadc_vxm; break; 3343 case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break; 3344 case 19: op = rv_op_vmsbc_vxm; break; 3345 case 23: 3346 if (((inst >> 20) & 0b111111) == 32) 3347 op = rv_op_vmv_v_x; 3348 else if (((inst >> 25) & 1) == 0) 3349 op = rv_op_vmerge_vxm; 3350 break; 3351 case 24: op = rv_op_vmseq_vx; break; 3352 case 25: op = rv_op_vmsne_vx; break; 3353 case 26: op = rv_op_vmsltu_vx; break; 3354 case 27: op = rv_op_vmslt_vx; break; 3355 case 28: op = rv_op_vmsleu_vx; break; 3356 case 29: op = rv_op_vmsle_vx; break; 3357 case 30: op = rv_op_vmsgtu_vx; break; 3358 case 31: op = rv_op_vmsgt_vx; break; 3359 case 32: op = rv_op_vsaddu_vx; break; 3360 case 33: op = rv_op_vsadd_vx; break; 3361 case 34: op = rv_op_vssubu_vx; break; 3362 case 35: op = rv_op_vssub_vx; break; 3363 case 37: op = rv_op_vsll_vx; break; 3364 case 39: op = rv_op_vsmul_vx; break; 3365 case 40: op = rv_op_vsrl_vx; break; 3366 case 41: op = rv_op_vsra_vx; break; 3367 case 42: op = rv_op_vssrl_vx; break; 3368 case 43: op = rv_op_vssra_vx; break; 3369 case 44: op = rv_op_vnsrl_wx; break; 3370 case 45: op = rv_op_vnsra_wx; break; 3371 case 46: op = rv_op_vnclipu_wx; break; 3372 case 47: op = rv_op_vnclip_wx; break; 3373 } 3374 break; 3375 case 5: 3376 switch (((inst >> 26) & 0b111111)) { 3377 case 0: op = rv_op_vfadd_vf; break; 3378 case 2: op = rv_op_vfsub_vf; break; 3379 case 4: op = rv_op_vfmin_vf; break; 3380 case 6: op = rv_op_vfmax_vf; break; 3381 case 8: op = rv_op_vfsgnj_vf; break; 3382 case 9: op = rv_op_vfsgnjn_vf; break; 3383 case 10: op = rv_op_vfsgnjx_vf; break; 3384 case 14: op = rv_op_vfslide1up_vf; break; 3385 case 15: op = rv_op_vfslide1down_vf; break; 3386 case 16: 3387 switch (((inst >> 20) & 0b11111)) { 3388 case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break; 3389 } 3390 break; 3391 case 23: 3392 if (((inst >> 25) & 1) == 0) 3393 op = rv_op_vfmerge_vfm; 3394 else if (((inst >> 20) & 0b111111) == 32) 3395 op = rv_op_vfmv_v_f; 3396 break; 3397 case 24: op = rv_op_vmfeq_vf; break; 3398 case 25: op = rv_op_vmfle_vf; break; 3399 case 27: op = rv_op_vmflt_vf; break; 3400 case 28: op = rv_op_vmfne_vf; break; 3401 case 29: op = rv_op_vmfgt_vf; break; 3402 case 31: op = rv_op_vmfge_vf; break; 3403 case 32: op = rv_op_vfdiv_vf; break; 3404 case 33: op = rv_op_vfrdiv_vf; break; 3405 case 36: op = rv_op_vfmul_vf; break; 3406 case 39: op = rv_op_vfrsub_vf; break; 3407 case 40: op = rv_op_vfmadd_vf; break; 3408 case 41: op = rv_op_vfnmadd_vf; break; 3409 case 42: op = rv_op_vfmsub_vf; break; 3410 case 43: op = rv_op_vfnmsub_vf; break; 3411 case 44: op = rv_op_vfmacc_vf; break; 3412 case 45: op = rv_op_vfnmacc_vf; break; 3413 case 46: op = rv_op_vfmsac_vf; break; 3414 case 47: op = rv_op_vfnmsac_vf; break; 3415 case 48: op = rv_op_vfwadd_vf; break; 3416 case 50: op = rv_op_vfwsub_vf; break; 3417 case 52: op = rv_op_vfwadd_wf; break; 3418 case 54: op = rv_op_vfwsub_wf; break; 3419 case 56: op = rv_op_vfwmul_vf; break; 3420 case 60: op = rv_op_vfwmacc_vf; break; 3421 case 61: op = rv_op_vfwnmacc_vf; break; 3422 case 62: op = rv_op_vfwmsac_vf; break; 3423 case 63: op = rv_op_vfwnmsac_vf; break; 3424 } 3425 break; 3426 case 6: 3427 switch (((inst >> 26) & 0b111111)) { 3428 case 8: op = rv_op_vaaddu_vx; break; 3429 case 9: op = rv_op_vaadd_vx; break; 3430 case 10: op = rv_op_vasubu_vx; break; 3431 case 11: op = rv_op_vasub_vx; break; 3432 case 14: op = rv_op_vslide1up_vx; break; 3433 case 15: op = rv_op_vslide1down_vx; break; 3434 case 16: 3435 switch (((inst >> 20) & 0b11111)) { 3436 case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break; 3437 } 3438 break; 3439 case 32: op = rv_op_vdivu_vx; break; 3440 case 33: op = rv_op_vdiv_vx; break; 3441 case 34: op = rv_op_vremu_vx; break; 3442 case 35: op = rv_op_vrem_vx; break; 3443 case 36: op = rv_op_vmulhu_vx; break; 3444 case 37: op = rv_op_vmul_vx; break; 3445 case 38: op = rv_op_vmulhsu_vx; break; 3446 case 39: op = rv_op_vmulh_vx; break; 3447 case 41: op = rv_op_vmadd_vx; break; 3448 case 43: op = rv_op_vnmsub_vx; break; 3449 case 45: op = rv_op_vmacc_vx; break; 3450 case 47: op = rv_op_vnmsac_vx; break; 3451 case 48: op = rv_op_vwaddu_vx; break; 3452 case 49: op = rv_op_vwadd_vx; break; 3453 case 50: op = rv_op_vwsubu_vx; break; 3454 case 51: op = rv_op_vwsub_vx; break; 3455 case 52: op = rv_op_vwaddu_wx; break; 3456 case 53: op = rv_op_vwadd_wx; break; 3457 case 54: op = rv_op_vwsubu_wx; break; 3458 case 55: op = rv_op_vwsub_wx; break; 3459 case 56: op = rv_op_vwmulu_vx; break; 3460 case 58: op = rv_op_vwmulsu_vx; break; 3461 case 59: op = rv_op_vwmul_vx; break; 3462 case 60: op = rv_op_vwmaccu_vx; break; 3463 case 61: op = rv_op_vwmacc_vx; break; 3464 case 62: op = rv_op_vwmaccus_vx; break; 3465 case 63: op = rv_op_vwmaccsu_vx; break; 3466 } 3467 break; 3468 case 7: 3469 if (((inst >> 31) & 1) == 0) { 3470 op = rv_op_vsetvli; 3471 } else if ((inst >> 30) & 1) { 3472 op = rv_op_vsetivli; 3473 } else if (((inst >> 25) & 0b11111) == 0) { 3474 op = rv_op_vsetvl; 3475 } 3476 break; 3477 } 3478 break; 3479 case 22: 3480 switch (((inst >> 12) & 0b111)) { 3481 case 0: op = rv_op_addid; break; 3482 case 1: 3483 switch (((inst >> 26) & 0b111111)) { 3484 case 0: op = rv_op_sllid; break; 3485 } 3486 break; 3487 case 5: 3488 switch (((inst >> 26) & 0b111111)) { 3489 case 0: op = rv_op_srlid; break; 3490 case 16: op = rv_op_sraid; break; 3491 } 3492 break; 3493 } 3494 break; 3495 case 24: 3496 switch (((inst >> 12) & 0b111)) { 3497 case 0: op = rv_op_beq; break; 3498 case 1: op = rv_op_bne; break; 3499 case 4: op = rv_op_blt; break; 3500 case 5: op = rv_op_bge; break; 3501 case 6: op = rv_op_bltu; break; 3502 case 7: op = rv_op_bgeu; break; 3503 } 3504 break; 3505 case 25: 3506 switch (((inst >> 12) & 0b111)) { 3507 case 0: op = rv_op_jalr; break; 3508 } 3509 break; 3510 case 27: op = rv_op_jal; break; 3511 case 28: 3512 switch (((inst >> 12) & 0b111)) { 3513 case 0: 3514 switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) { 3515 case 0: 3516 switch (((inst >> 15) & 0b1111111111)) { 3517 case 0: op = rv_op_ecall; break; 3518 case 32: op = rv_op_ebreak; break; 3519 case 64: op = rv_op_uret; break; 3520 } 3521 break; 3522 case 256: 3523 switch (((inst >> 20) & 0b11111)) { 3524 case 2: 3525 switch (((inst >> 15) & 0b11111)) { 3526 case 0: op = rv_op_sret; break; 3527 } 3528 break; 3529 case 4: op = rv_op_sfence_vm; break; 3530 case 5: 3531 switch (((inst >> 15) & 0b11111)) { 3532 case 0: op = rv_op_wfi; break; 3533 } 3534 break; 3535 } 3536 break; 3537 case 288: op = rv_op_sfence_vma; break; 3538 case 512: 3539 switch (((inst >> 15) & 0b1111111111)) { 3540 case 64: op = rv_op_hret; break; 3541 } 3542 break; 3543 case 768: 3544 switch (((inst >> 15) & 0b1111111111)) { 3545 case 64: op = rv_op_mret; break; 3546 } 3547 break; 3548 case 1952: 3549 switch (((inst >> 15) & 0b1111111111)) { 3550 case 576: op = rv_op_dret; break; 3551 } 3552 break; 3553 } 3554 break; 3555 case 1: op = rv_op_csrrw; break; 3556 case 2: op = rv_op_csrrs; break; 3557 case 3: op = rv_op_csrrc; break; 3558 case 5: op = rv_op_csrrwi; break; 3559 case 6: op = rv_op_csrrsi; break; 3560 case 7: op = rv_op_csrrci; break; 3561 } 3562 break; 3563 case 30: 3564 switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { 3565 case 0: op = rv_op_addd; break; 3566 case 1: op = rv_op_slld; break; 3567 case 5: op = rv_op_srld; break; 3568 case 8: op = rv_op_muld; break; 3569 case 12: op = rv_op_divd; break; 3570 case 13: op = rv_op_divud; break; 3571 case 14: op = rv_op_remd; break; 3572 case 15: op = rv_op_remud; break; 3573 case 256: op = rv_op_subd; break; 3574 case 261: op = rv_op_srad; break; 3575 } 3576 break; 3577 } 3578 break; 3579 } 3580 dec->op = op; 3581 } 3582 3583 /* operand extractors */ 3584 3585 static uint32_t operand_rd(rv_inst inst) 3586 { 3587 return (inst << 52) >> 59; 3588 } 3589 3590 static uint32_t operand_rs1(rv_inst inst) 3591 { 3592 return (inst << 44) >> 59; 3593 } 3594 3595 static uint32_t operand_rs2(rv_inst inst) 3596 { 3597 return (inst << 39) >> 59; 3598 } 3599 3600 static uint32_t operand_rs3(rv_inst inst) 3601 { 3602 return (inst << 32) >> 59; 3603 } 3604 3605 static uint32_t operand_aq(rv_inst inst) 3606 { 3607 return (inst << 37) >> 63; 3608 } 3609 3610 static uint32_t operand_rl(rv_inst inst) 3611 { 3612 return (inst << 38) >> 63; 3613 } 3614 3615 static uint32_t operand_pred(rv_inst inst) 3616 { 3617 return (inst << 36) >> 60; 3618 } 3619 3620 static uint32_t operand_succ(rv_inst inst) 3621 { 3622 return (inst << 40) >> 60; 3623 } 3624 3625 static uint32_t operand_rm(rv_inst inst) 3626 { 3627 return (inst << 49) >> 61; 3628 } 3629 3630 static uint32_t operand_shamt5(rv_inst inst) 3631 { 3632 return (inst << 39) >> 59; 3633 } 3634 3635 static uint32_t operand_shamt6(rv_inst inst) 3636 { 3637 return (inst << 38) >> 58; 3638 } 3639 3640 static uint32_t operand_shamt7(rv_inst inst) 3641 { 3642 return (inst << 37) >> 57; 3643 } 3644 3645 static uint32_t operand_crdq(rv_inst inst) 3646 { 3647 return (inst << 59) >> 61; 3648 } 3649 3650 static uint32_t operand_crs1q(rv_inst inst) 3651 { 3652 return (inst << 54) >> 61; 3653 } 3654 3655 static uint32_t operand_crs1rdq(rv_inst inst) 3656 { 3657 return (inst << 54) >> 61; 3658 } 3659 3660 static uint32_t operand_crs2q(rv_inst inst) 3661 { 3662 return (inst << 59) >> 61; 3663 } 3664 3665 static uint32_t operand_crd(rv_inst inst) 3666 { 3667 return (inst << 52) >> 59; 3668 } 3669 3670 static uint32_t operand_crs1(rv_inst inst) 3671 { 3672 return (inst << 52) >> 59; 3673 } 3674 3675 static uint32_t operand_crs1rd(rv_inst inst) 3676 { 3677 return (inst << 52) >> 59; 3678 } 3679 3680 static uint32_t operand_crs2(rv_inst inst) 3681 { 3682 return (inst << 57) >> 59; 3683 } 3684 3685 static uint32_t operand_cimmsh5(rv_inst inst) 3686 { 3687 return (inst << 57) >> 59; 3688 } 3689 3690 static uint32_t operand_csr12(rv_inst inst) 3691 { 3692 return (inst << 32) >> 52; 3693 } 3694 3695 static int32_t operand_imm12(rv_inst inst) 3696 { 3697 return ((int64_t)inst << 32) >> 52; 3698 } 3699 3700 static int32_t operand_imm20(rv_inst inst) 3701 { 3702 return (((int64_t)inst << 32) >> 44) << 12; 3703 } 3704 3705 static int32_t operand_jimm20(rv_inst inst) 3706 { 3707 return (((int64_t)inst << 32) >> 63) << 20 | 3708 ((inst << 33) >> 54) << 1 | 3709 ((inst << 43) >> 63) << 11 | 3710 ((inst << 44) >> 56) << 12; 3711 } 3712 3713 static int32_t operand_simm12(rv_inst inst) 3714 { 3715 return (((int64_t)inst << 32) >> 57) << 5 | 3716 (inst << 52) >> 59; 3717 } 3718 3719 static int32_t operand_sbimm12(rv_inst inst) 3720 { 3721 return (((int64_t)inst << 32) >> 63) << 12 | 3722 ((inst << 33) >> 58) << 5 | 3723 ((inst << 52) >> 60) << 1 | 3724 ((inst << 56) >> 63) << 11; 3725 } 3726 3727 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) 3728 { 3729 int imm = ((inst << 51) >> 63) << 5 | 3730 (inst << 57) >> 59; 3731 if (isa == rv128) { 3732 imm = imm ? imm : 64; 3733 } 3734 return imm; 3735 } 3736 3737 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) 3738 { 3739 int imm = ((inst << 51) >> 63) << 5 | 3740 (inst << 57) >> 59; 3741 if (isa == rv128) { 3742 imm = imm | (imm & 32) << 1; 3743 imm = imm ? imm : 64; 3744 } 3745 return imm; 3746 } 3747 3748 static int32_t operand_cimmi(rv_inst inst) 3749 { 3750 return (((int64_t)inst << 51) >> 63) << 5 | 3751 (inst << 57) >> 59; 3752 } 3753 3754 static int32_t operand_cimmui(rv_inst inst) 3755 { 3756 return (((int64_t)inst << 51) >> 63) << 17 | 3757 ((inst << 57) >> 59) << 12; 3758 } 3759 3760 static uint32_t operand_cimmlwsp(rv_inst inst) 3761 { 3762 return ((inst << 51) >> 63) << 5 | 3763 ((inst << 57) >> 61) << 2 | 3764 ((inst << 60) >> 62) << 6; 3765 } 3766 3767 static uint32_t operand_cimmldsp(rv_inst inst) 3768 { 3769 return ((inst << 51) >> 63) << 5 | 3770 ((inst << 57) >> 62) << 3 | 3771 ((inst << 59) >> 61) << 6; 3772 } 3773 3774 static uint32_t operand_cimmlqsp(rv_inst inst) 3775 { 3776 return ((inst << 51) >> 63) << 5 | 3777 ((inst << 57) >> 63) << 4 | 3778 ((inst << 58) >> 60) << 6; 3779 } 3780 3781 static int32_t operand_cimm16sp(rv_inst inst) 3782 { 3783 return (((int64_t)inst << 51) >> 63) << 9 | 3784 ((inst << 57) >> 63) << 4 | 3785 ((inst << 58) >> 63) << 6 | 3786 ((inst << 59) >> 62) << 7 | 3787 ((inst << 61) >> 63) << 5; 3788 } 3789 3790 static int32_t operand_cimmj(rv_inst inst) 3791 { 3792 return (((int64_t)inst << 51) >> 63) << 11 | 3793 ((inst << 52) >> 63) << 4 | 3794 ((inst << 53) >> 62) << 8 | 3795 ((inst << 55) >> 63) << 10 | 3796 ((inst << 56) >> 63) << 6 | 3797 ((inst << 57) >> 63) << 7 | 3798 ((inst << 58) >> 61) << 1 | 3799 ((inst << 61) >> 63) << 5; 3800 } 3801 3802 static int32_t operand_cimmb(rv_inst inst) 3803 { 3804 return (((int64_t)inst << 51) >> 63) << 8 | 3805 ((inst << 52) >> 62) << 3 | 3806 ((inst << 57) >> 62) << 6 | 3807 ((inst << 59) >> 62) << 1 | 3808 ((inst << 61) >> 63) << 5; 3809 } 3810 3811 static uint32_t operand_cimmswsp(rv_inst inst) 3812 { 3813 return ((inst << 51) >> 60) << 2 | 3814 ((inst << 55) >> 62) << 6; 3815 } 3816 3817 static uint32_t operand_cimmsdsp(rv_inst inst) 3818 { 3819 return ((inst << 51) >> 61) << 3 | 3820 ((inst << 54) >> 61) << 6; 3821 } 3822 3823 static uint32_t operand_cimmsqsp(rv_inst inst) 3824 { 3825 return ((inst << 51) >> 62) << 4 | 3826 ((inst << 53) >> 60) << 6; 3827 } 3828 3829 static uint32_t operand_cimm4spn(rv_inst inst) 3830 { 3831 return ((inst << 51) >> 62) << 4 | 3832 ((inst << 53) >> 60) << 6 | 3833 ((inst << 57) >> 63) << 2 | 3834 ((inst << 58) >> 63) << 3; 3835 } 3836 3837 static uint32_t operand_cimmw(rv_inst inst) 3838 { 3839 return ((inst << 51) >> 61) << 3 | 3840 ((inst << 57) >> 63) << 2 | 3841 ((inst << 58) >> 63) << 6; 3842 } 3843 3844 static uint32_t operand_cimmd(rv_inst inst) 3845 { 3846 return ((inst << 51) >> 61) << 3 | 3847 ((inst << 57) >> 62) << 6; 3848 } 3849 3850 static uint32_t operand_cimmq(rv_inst inst) 3851 { 3852 return ((inst << 51) >> 62) << 4 | 3853 ((inst << 53) >> 63) << 8 | 3854 ((inst << 57) >> 62) << 6; 3855 } 3856 3857 static uint32_t operand_vimm(rv_inst inst) 3858 { 3859 return (int64_t)(inst << 44) >> 59; 3860 } 3861 3862 static uint32_t operand_vzimm11(rv_inst inst) 3863 { 3864 return (inst << 33) >> 53; 3865 } 3866 3867 static uint32_t operand_vzimm10(rv_inst inst) 3868 { 3869 return (inst << 34) >> 54; 3870 } 3871 3872 static uint32_t operand_bs(rv_inst inst) 3873 { 3874 return (inst << 32) >> 62; 3875 } 3876 3877 static uint32_t operand_rnum(rv_inst inst) 3878 { 3879 return (inst << 40) >> 60; 3880 } 3881 3882 static uint32_t operand_vm(rv_inst inst) 3883 { 3884 return (inst << 38) >> 63; 3885 } 3886 3887 /* decode operands */ 3888 3889 static void decode_inst_operands(rv_decode *dec, rv_isa isa) 3890 { 3891 rv_inst inst = dec->inst; 3892 dec->codec = opcode_data[dec->op].codec; 3893 switch (dec->codec) { 3894 case rv_codec_none: 3895 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 3896 dec->imm = 0; 3897 break; 3898 case rv_codec_u: 3899 dec->rd = operand_rd(inst); 3900 dec->rs1 = dec->rs2 = rv_ireg_zero; 3901 dec->imm = operand_imm20(inst); 3902 break; 3903 case rv_codec_uj: 3904 dec->rd = operand_rd(inst); 3905 dec->rs1 = dec->rs2 = rv_ireg_zero; 3906 dec->imm = operand_jimm20(inst); 3907 break; 3908 case rv_codec_i: 3909 dec->rd = operand_rd(inst); 3910 dec->rs1 = operand_rs1(inst); 3911 dec->rs2 = rv_ireg_zero; 3912 dec->imm = operand_imm12(inst); 3913 break; 3914 case rv_codec_i_sh5: 3915 dec->rd = operand_rd(inst); 3916 dec->rs1 = operand_rs1(inst); 3917 dec->rs2 = rv_ireg_zero; 3918 dec->imm = operand_shamt5(inst); 3919 break; 3920 case rv_codec_i_sh6: 3921 dec->rd = operand_rd(inst); 3922 dec->rs1 = operand_rs1(inst); 3923 dec->rs2 = rv_ireg_zero; 3924 dec->imm = operand_shamt6(inst); 3925 break; 3926 case rv_codec_i_sh7: 3927 dec->rd = operand_rd(inst); 3928 dec->rs1 = operand_rs1(inst); 3929 dec->rs2 = rv_ireg_zero; 3930 dec->imm = operand_shamt7(inst); 3931 break; 3932 case rv_codec_i_csr: 3933 dec->rd = operand_rd(inst); 3934 dec->rs1 = operand_rs1(inst); 3935 dec->rs2 = rv_ireg_zero; 3936 dec->imm = operand_csr12(inst); 3937 break; 3938 case rv_codec_s: 3939 dec->rd = rv_ireg_zero; 3940 dec->rs1 = operand_rs1(inst); 3941 dec->rs2 = operand_rs2(inst); 3942 dec->imm = operand_simm12(inst); 3943 break; 3944 case rv_codec_sb: 3945 dec->rd = rv_ireg_zero; 3946 dec->rs1 = operand_rs1(inst); 3947 dec->rs2 = operand_rs2(inst); 3948 dec->imm = operand_sbimm12(inst); 3949 break; 3950 case rv_codec_r: 3951 dec->rd = operand_rd(inst); 3952 dec->rs1 = operand_rs1(inst); 3953 dec->rs2 = operand_rs2(inst); 3954 dec->imm = 0; 3955 break; 3956 case rv_codec_r_m: 3957 dec->rd = operand_rd(inst); 3958 dec->rs1 = operand_rs1(inst); 3959 dec->rs2 = operand_rs2(inst); 3960 dec->imm = 0; 3961 dec->rm = operand_rm(inst); 3962 break; 3963 case rv_codec_r4_m: 3964 dec->rd = operand_rd(inst); 3965 dec->rs1 = operand_rs1(inst); 3966 dec->rs2 = operand_rs2(inst); 3967 dec->rs3 = operand_rs3(inst); 3968 dec->imm = 0; 3969 dec->rm = operand_rm(inst); 3970 break; 3971 case rv_codec_r_a: 3972 dec->rd = operand_rd(inst); 3973 dec->rs1 = operand_rs1(inst); 3974 dec->rs2 = operand_rs2(inst); 3975 dec->imm = 0; 3976 dec->aq = operand_aq(inst); 3977 dec->rl = operand_rl(inst); 3978 break; 3979 case rv_codec_r_l: 3980 dec->rd = operand_rd(inst); 3981 dec->rs1 = operand_rs1(inst); 3982 dec->rs2 = rv_ireg_zero; 3983 dec->imm = 0; 3984 dec->aq = operand_aq(inst); 3985 dec->rl = operand_rl(inst); 3986 break; 3987 case rv_codec_r_f: 3988 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 3989 dec->pred = operand_pred(inst); 3990 dec->succ = operand_succ(inst); 3991 dec->imm = 0; 3992 break; 3993 case rv_codec_cb: 3994 dec->rd = rv_ireg_zero; 3995 dec->rs1 = operand_crs1q(inst) + 8; 3996 dec->rs2 = rv_ireg_zero; 3997 dec->imm = operand_cimmb(inst); 3998 break; 3999 case rv_codec_cb_imm: 4000 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4001 dec->rs2 = rv_ireg_zero; 4002 dec->imm = operand_cimmi(inst); 4003 break; 4004 case rv_codec_cb_sh5: 4005 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4006 dec->rs2 = rv_ireg_zero; 4007 dec->imm = operand_cimmsh5(inst); 4008 break; 4009 case rv_codec_cb_sh6: 4010 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4011 dec->rs2 = rv_ireg_zero; 4012 dec->imm = operand_cimmshr6(inst, isa); 4013 break; 4014 case rv_codec_ci: 4015 dec->rd = dec->rs1 = operand_crs1rd(inst); 4016 dec->rs2 = rv_ireg_zero; 4017 dec->imm = operand_cimmi(inst); 4018 break; 4019 case rv_codec_ci_sh5: 4020 dec->rd = dec->rs1 = operand_crs1rd(inst); 4021 dec->rs2 = rv_ireg_zero; 4022 dec->imm = operand_cimmsh5(inst); 4023 break; 4024 case rv_codec_ci_sh6: 4025 dec->rd = dec->rs1 = operand_crs1rd(inst); 4026 dec->rs2 = rv_ireg_zero; 4027 dec->imm = operand_cimmshl6(inst, isa); 4028 break; 4029 case rv_codec_ci_16sp: 4030 dec->rd = rv_ireg_sp; 4031 dec->rs1 = rv_ireg_sp; 4032 dec->rs2 = rv_ireg_zero; 4033 dec->imm = operand_cimm16sp(inst); 4034 break; 4035 case rv_codec_ci_lwsp: 4036 dec->rd = operand_crd(inst); 4037 dec->rs1 = rv_ireg_sp; 4038 dec->rs2 = rv_ireg_zero; 4039 dec->imm = operand_cimmlwsp(inst); 4040 break; 4041 case rv_codec_ci_ldsp: 4042 dec->rd = operand_crd(inst); 4043 dec->rs1 = rv_ireg_sp; 4044 dec->rs2 = rv_ireg_zero; 4045 dec->imm = operand_cimmldsp(inst); 4046 break; 4047 case rv_codec_ci_lqsp: 4048 dec->rd = operand_crd(inst); 4049 dec->rs1 = rv_ireg_sp; 4050 dec->rs2 = rv_ireg_zero; 4051 dec->imm = operand_cimmlqsp(inst); 4052 break; 4053 case rv_codec_ci_li: 4054 dec->rd = operand_crd(inst); 4055 dec->rs1 = rv_ireg_zero; 4056 dec->rs2 = rv_ireg_zero; 4057 dec->imm = operand_cimmi(inst); 4058 break; 4059 case rv_codec_ci_lui: 4060 dec->rd = operand_crd(inst); 4061 dec->rs1 = rv_ireg_zero; 4062 dec->rs2 = rv_ireg_zero; 4063 dec->imm = operand_cimmui(inst); 4064 break; 4065 case rv_codec_ci_none: 4066 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4067 dec->imm = 0; 4068 break; 4069 case rv_codec_ciw_4spn: 4070 dec->rd = operand_crdq(inst) + 8; 4071 dec->rs1 = rv_ireg_sp; 4072 dec->rs2 = rv_ireg_zero; 4073 dec->imm = operand_cimm4spn(inst); 4074 break; 4075 case rv_codec_cj: 4076 dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero; 4077 dec->imm = operand_cimmj(inst); 4078 break; 4079 case rv_codec_cj_jal: 4080 dec->rd = rv_ireg_ra; 4081 dec->rs1 = dec->rs2 = rv_ireg_zero; 4082 dec->imm = operand_cimmj(inst); 4083 break; 4084 case rv_codec_cl_lw: 4085 dec->rd = operand_crdq(inst) + 8; 4086 dec->rs1 = operand_crs1q(inst) + 8; 4087 dec->rs2 = rv_ireg_zero; 4088 dec->imm = operand_cimmw(inst); 4089 break; 4090 case rv_codec_cl_ld: 4091 dec->rd = operand_crdq(inst) + 8; 4092 dec->rs1 = operand_crs1q(inst) + 8; 4093 dec->rs2 = rv_ireg_zero; 4094 dec->imm = operand_cimmd(inst); 4095 break; 4096 case rv_codec_cl_lq: 4097 dec->rd = operand_crdq(inst) + 8; 4098 dec->rs1 = operand_crs1q(inst) + 8; 4099 dec->rs2 = rv_ireg_zero; 4100 dec->imm = operand_cimmq(inst); 4101 break; 4102 case rv_codec_cr: 4103 dec->rd = dec->rs1 = operand_crs1rd(inst); 4104 dec->rs2 = operand_crs2(inst); 4105 dec->imm = 0; 4106 break; 4107 case rv_codec_cr_mv: 4108 dec->rd = operand_crd(inst); 4109 dec->rs1 = operand_crs2(inst); 4110 dec->rs2 = rv_ireg_zero; 4111 dec->imm = 0; 4112 break; 4113 case rv_codec_cr_jalr: 4114 dec->rd = rv_ireg_ra; 4115 dec->rs1 = operand_crs1(inst); 4116 dec->rs2 = rv_ireg_zero; 4117 dec->imm = 0; 4118 break; 4119 case rv_codec_cr_jr: 4120 dec->rd = rv_ireg_zero; 4121 dec->rs1 = operand_crs1(inst); 4122 dec->rs2 = rv_ireg_zero; 4123 dec->imm = 0; 4124 break; 4125 case rv_codec_cs: 4126 dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8; 4127 dec->rs2 = operand_crs2q(inst) + 8; 4128 dec->imm = 0; 4129 break; 4130 case rv_codec_cs_sw: 4131 dec->rd = rv_ireg_zero; 4132 dec->rs1 = operand_crs1q(inst) + 8; 4133 dec->rs2 = operand_crs2q(inst) + 8; 4134 dec->imm = operand_cimmw(inst); 4135 break; 4136 case rv_codec_cs_sd: 4137 dec->rd = rv_ireg_zero; 4138 dec->rs1 = operand_crs1q(inst) + 8; 4139 dec->rs2 = operand_crs2q(inst) + 8; 4140 dec->imm = operand_cimmd(inst); 4141 break; 4142 case rv_codec_cs_sq: 4143 dec->rd = rv_ireg_zero; 4144 dec->rs1 = operand_crs1q(inst) + 8; 4145 dec->rs2 = operand_crs2q(inst) + 8; 4146 dec->imm = operand_cimmq(inst); 4147 break; 4148 case rv_codec_css_swsp: 4149 dec->rd = rv_ireg_zero; 4150 dec->rs1 = rv_ireg_sp; 4151 dec->rs2 = operand_crs2(inst); 4152 dec->imm = operand_cimmswsp(inst); 4153 break; 4154 case rv_codec_css_sdsp: 4155 dec->rd = rv_ireg_zero; 4156 dec->rs1 = rv_ireg_sp; 4157 dec->rs2 = operand_crs2(inst); 4158 dec->imm = operand_cimmsdsp(inst); 4159 break; 4160 case rv_codec_css_sqsp: 4161 dec->rd = rv_ireg_zero; 4162 dec->rs1 = rv_ireg_sp; 4163 dec->rs2 = operand_crs2(inst); 4164 dec->imm = operand_cimmsqsp(inst); 4165 break; 4166 case rv_codec_k_bs: 4167 dec->rs1 = operand_rs1(inst); 4168 dec->rs2 = operand_rs2(inst); 4169 dec->bs = operand_bs(inst); 4170 break; 4171 case rv_codec_k_rnum: 4172 dec->rd = operand_rd(inst); 4173 dec->rs1 = operand_rs1(inst); 4174 dec->rnum = operand_rnum(inst); 4175 break; 4176 case rv_codec_v_r: 4177 dec->rd = operand_rd(inst); 4178 dec->rs1 = operand_rs1(inst); 4179 dec->rs2 = operand_rs2(inst); 4180 dec->vm = operand_vm(inst); 4181 break; 4182 case rv_codec_v_ldst: 4183 dec->rd = operand_rd(inst); 4184 dec->rs1 = operand_rs1(inst); 4185 dec->vm = operand_vm(inst); 4186 break; 4187 case rv_codec_v_i: 4188 dec->rd = operand_rd(inst); 4189 dec->rs2 = operand_rs2(inst); 4190 dec->imm = operand_vimm(inst); 4191 dec->vm = operand_vm(inst); 4192 break; 4193 case rv_codec_vsetvli: 4194 dec->rd = operand_rd(inst); 4195 dec->rs1 = operand_rs1(inst); 4196 dec->vzimm = operand_vzimm11(inst); 4197 break; 4198 case rv_codec_vsetivli: 4199 dec->rd = operand_rd(inst); 4200 dec->imm = operand_vimm(inst); 4201 dec->vzimm = operand_vzimm10(inst); 4202 break; 4203 }; 4204 } 4205 4206 /* check constraint */ 4207 4208 static bool check_constraints(rv_decode *dec, const rvc_constraint *c) 4209 { 4210 int32_t imm = dec->imm; 4211 uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2; 4212 while (*c != rvc_end) { 4213 switch (*c) { 4214 case rvc_rd_eq_ra: 4215 if (!(rd == 1)) { 4216 return false; 4217 } 4218 break; 4219 case rvc_rd_eq_x0: 4220 if (!(rd == 0)) { 4221 return false; 4222 } 4223 break; 4224 case rvc_rs1_eq_x0: 4225 if (!(rs1 == 0)) { 4226 return false; 4227 } 4228 break; 4229 case rvc_rs2_eq_x0: 4230 if (!(rs2 == 0)) { 4231 return false; 4232 } 4233 break; 4234 case rvc_rs2_eq_rs1: 4235 if (!(rs2 == rs1)) { 4236 return false; 4237 } 4238 break; 4239 case rvc_rs1_eq_ra: 4240 if (!(rs1 == 1)) { 4241 return false; 4242 } 4243 break; 4244 case rvc_imm_eq_zero: 4245 if (!(imm == 0)) { 4246 return false; 4247 } 4248 break; 4249 case rvc_imm_eq_n1: 4250 if (!(imm == -1)) { 4251 return false; 4252 } 4253 break; 4254 case rvc_imm_eq_p1: 4255 if (!(imm == 1)) { 4256 return false; 4257 } 4258 break; 4259 case rvc_csr_eq_0x001: 4260 if (!(imm == 0x001)) { 4261 return false; 4262 } 4263 break; 4264 case rvc_csr_eq_0x002: 4265 if (!(imm == 0x002)) { 4266 return false; 4267 } 4268 break; 4269 case rvc_csr_eq_0x003: 4270 if (!(imm == 0x003)) { 4271 return false; 4272 } 4273 break; 4274 case rvc_csr_eq_0xc00: 4275 if (!(imm == 0xc00)) { 4276 return false; 4277 } 4278 break; 4279 case rvc_csr_eq_0xc01: 4280 if (!(imm == 0xc01)) { 4281 return false; 4282 } 4283 break; 4284 case rvc_csr_eq_0xc02: 4285 if (!(imm == 0xc02)) { 4286 return false; 4287 } 4288 break; 4289 case rvc_csr_eq_0xc80: 4290 if (!(imm == 0xc80)) { 4291 return false; 4292 } 4293 break; 4294 case rvc_csr_eq_0xc81: 4295 if (!(imm == 0xc81)) { 4296 return false; 4297 } 4298 break; 4299 case rvc_csr_eq_0xc82: 4300 if (!(imm == 0xc82)) { 4301 return false; 4302 } 4303 break; 4304 default: break; 4305 } 4306 c++; 4307 } 4308 return true; 4309 } 4310 4311 /* instruction length */ 4312 4313 static size_t inst_length(rv_inst inst) 4314 { 4315 /* NOTE: supports maximum instruction size of 64-bits */ 4316 4317 /* instruction length coding 4318 * 4319 * aa - 16 bit aa != 11 4320 * bbb11 - 32 bit bbb != 111 4321 * 011111 - 48 bit 4322 * 0111111 - 64 bit 4323 */ 4324 4325 return (inst & 0b11) != 0b11 ? 2 4326 : (inst & 0b11100) != 0b11100 ? 4 4327 : (inst & 0b111111) == 0b011111 ? 6 4328 : (inst & 0b1111111) == 0b0111111 ? 8 4329 : 0; 4330 } 4331 4332 /* format instruction */ 4333 4334 static void append(char *s1, const char *s2, size_t n) 4335 { 4336 size_t l1 = strlen(s1); 4337 if (n - l1 - 1 > 0) { 4338 strncat(s1, s2, n - l1); 4339 } 4340 } 4341 4342 static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) 4343 { 4344 char tmp[64]; 4345 const char *fmt; 4346 4347 fmt = opcode_data[dec->op].format; 4348 while (*fmt) { 4349 switch (*fmt) { 4350 case 'O': 4351 append(buf, opcode_data[dec->op].name, buflen); 4352 break; 4353 case '(': 4354 append(buf, "(", buflen); 4355 break; 4356 case ',': 4357 append(buf, ",", buflen); 4358 break; 4359 case ')': 4360 append(buf, ")", buflen); 4361 break; 4362 case 'b': 4363 snprintf(tmp, sizeof(tmp), "%d", dec->bs); 4364 append(buf, tmp, buflen); 4365 break; 4366 case 'n': 4367 snprintf(tmp, sizeof(tmp), "%d", dec->rnum); 4368 append(buf, tmp, buflen); 4369 break; 4370 case '0': 4371 append(buf, rv_ireg_name_sym[dec->rd], buflen); 4372 break; 4373 case '1': 4374 append(buf, rv_ireg_name_sym[dec->rs1], buflen); 4375 break; 4376 case '2': 4377 append(buf, rv_ireg_name_sym[dec->rs2], buflen); 4378 break; 4379 case '3': 4380 append(buf, rv_freg_name_sym[dec->rd], buflen); 4381 break; 4382 case '4': 4383 append(buf, rv_freg_name_sym[dec->rs1], buflen); 4384 break; 4385 case '5': 4386 append(buf, rv_freg_name_sym[dec->rs2], buflen); 4387 break; 4388 case '6': 4389 append(buf, rv_freg_name_sym[dec->rs3], buflen); 4390 break; 4391 case '7': 4392 snprintf(tmp, sizeof(tmp), "%d", dec->rs1); 4393 append(buf, tmp, buflen); 4394 break; 4395 case 'i': 4396 snprintf(tmp, sizeof(tmp), "%d", dec->imm); 4397 append(buf, tmp, buflen); 4398 break; 4399 case 'u': 4400 snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111)); 4401 append(buf, tmp, buflen); 4402 break; 4403 case 'o': 4404 snprintf(tmp, sizeof(tmp), "%d", dec->imm); 4405 append(buf, tmp, buflen); 4406 while (strlen(buf) < tab * 2) { 4407 append(buf, " ", buflen); 4408 } 4409 snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64, 4410 dec->pc + dec->imm); 4411 append(buf, tmp, buflen); 4412 break; 4413 case 'c': { 4414 const char *name = csr_name(dec->imm & 0xfff); 4415 if (name) { 4416 append(buf, name, buflen); 4417 } else { 4418 snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff); 4419 append(buf, tmp, buflen); 4420 } 4421 break; 4422 } 4423 case 'r': 4424 switch (dec->rm) { 4425 case rv_rm_rne: 4426 append(buf, "rne", buflen); 4427 break; 4428 case rv_rm_rtz: 4429 append(buf, "rtz", buflen); 4430 break; 4431 case rv_rm_rdn: 4432 append(buf, "rdn", buflen); 4433 break; 4434 case rv_rm_rup: 4435 append(buf, "rup", buflen); 4436 break; 4437 case rv_rm_rmm: 4438 append(buf, "rmm", buflen); 4439 break; 4440 case rv_rm_dyn: 4441 append(buf, "dyn", buflen); 4442 break; 4443 default: 4444 append(buf, "inv", buflen); 4445 break; 4446 } 4447 break; 4448 case 'p': 4449 if (dec->pred & rv_fence_i) { 4450 append(buf, "i", buflen); 4451 } 4452 if (dec->pred & rv_fence_o) { 4453 append(buf, "o", buflen); 4454 } 4455 if (dec->pred & rv_fence_r) { 4456 append(buf, "r", buflen); 4457 } 4458 if (dec->pred & rv_fence_w) { 4459 append(buf, "w", buflen); 4460 } 4461 break; 4462 case 's': 4463 if (dec->succ & rv_fence_i) { 4464 append(buf, "i", buflen); 4465 } 4466 if (dec->succ & rv_fence_o) { 4467 append(buf, "o", buflen); 4468 } 4469 if (dec->succ & rv_fence_r) { 4470 append(buf, "r", buflen); 4471 } 4472 if (dec->succ & rv_fence_w) { 4473 append(buf, "w", buflen); 4474 } 4475 break; 4476 case '\t': 4477 while (strlen(buf) < tab) { 4478 append(buf, " ", buflen); 4479 } 4480 break; 4481 case 'A': 4482 if (dec->aq) { 4483 append(buf, ".aq", buflen); 4484 } 4485 break; 4486 case 'R': 4487 if (dec->rl) { 4488 append(buf, ".rl", buflen); 4489 } 4490 break; 4491 case 'l': 4492 append(buf, ",v0", buflen); 4493 break; 4494 case 'm': 4495 if (dec->vm == 0) { 4496 append(buf, ",v0.t", buflen); 4497 } 4498 break; 4499 case 'D': 4500 append(buf, rv_vreg_name_sym[dec->rd], buflen); 4501 break; 4502 case 'E': 4503 append(buf, rv_vreg_name_sym[dec->rs1], buflen); 4504 break; 4505 case 'F': 4506 append(buf, rv_vreg_name_sym[dec->rs2], buflen); 4507 break; 4508 case 'G': 4509 append(buf, rv_vreg_name_sym[dec->rs3], buflen); 4510 break; 4511 case 'v': { 4512 char nbuf[32] = {0}; 4513 const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3); 4514 sprintf(nbuf, "%d", sew); 4515 const int lmul = dec->vzimm & 0b11; 4516 const int flmul = (dec->vzimm >> 2) & 1; 4517 const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu"; 4518 const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu"; 4519 append(buf, "e", buflen); 4520 append(buf, nbuf, buflen); 4521 append(buf, ",m", buflen); 4522 if (flmul) { 4523 switch (lmul) { 4524 case 3: 4525 sprintf(nbuf, "f2"); 4526 break; 4527 case 2: 4528 sprintf(nbuf, "f4"); 4529 break; 4530 case 1: 4531 sprintf(nbuf, "f8"); 4532 break; 4533 } 4534 append(buf, nbuf, buflen); 4535 } else { 4536 sprintf(nbuf, "%d", 1 << lmul); 4537 append(buf, nbuf, buflen); 4538 } 4539 append(buf, ",", buflen); 4540 append(buf, vta, buflen); 4541 append(buf, ",", buflen); 4542 append(buf, vma, buflen); 4543 break; 4544 } 4545 default: 4546 break; 4547 } 4548 fmt++; 4549 } 4550 } 4551 4552 /* lift instruction to pseudo-instruction */ 4553 4554 static void decode_inst_lift_pseudo(rv_decode *dec) 4555 { 4556 const rv_comp_data *comp_data = opcode_data[dec->op].pseudo; 4557 if (!comp_data) { 4558 return; 4559 } 4560 while (comp_data->constraints) { 4561 if (check_constraints(dec, comp_data->constraints)) { 4562 dec->op = comp_data->op; 4563 dec->codec = opcode_data[dec->op].codec; 4564 return; 4565 } 4566 comp_data++; 4567 } 4568 } 4569 4570 /* decompress instruction */ 4571 4572 static void decode_inst_decompress_rv32(rv_decode *dec) 4573 { 4574 int decomp_op = opcode_data[dec->op].decomp_rv32; 4575 if (decomp_op != rv_op_illegal) { 4576 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 4577 && dec->imm == 0) { 4578 dec->op = rv_op_illegal; 4579 } else { 4580 dec->op = decomp_op; 4581 dec->codec = opcode_data[decomp_op].codec; 4582 } 4583 } 4584 } 4585 4586 static void decode_inst_decompress_rv64(rv_decode *dec) 4587 { 4588 int decomp_op = opcode_data[dec->op].decomp_rv64; 4589 if (decomp_op != rv_op_illegal) { 4590 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 4591 && dec->imm == 0) { 4592 dec->op = rv_op_illegal; 4593 } else { 4594 dec->op = decomp_op; 4595 dec->codec = opcode_data[decomp_op].codec; 4596 } 4597 } 4598 } 4599 4600 static void decode_inst_decompress_rv128(rv_decode *dec) 4601 { 4602 int decomp_op = opcode_data[dec->op].decomp_rv128; 4603 if (decomp_op != rv_op_illegal) { 4604 if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) 4605 && dec->imm == 0) { 4606 dec->op = rv_op_illegal; 4607 } else { 4608 dec->op = decomp_op; 4609 dec->codec = opcode_data[decomp_op].codec; 4610 } 4611 } 4612 } 4613 4614 static void decode_inst_decompress(rv_decode *dec, rv_isa isa) 4615 { 4616 switch (isa) { 4617 case rv32: 4618 decode_inst_decompress_rv32(dec); 4619 break; 4620 case rv64: 4621 decode_inst_decompress_rv64(dec); 4622 break; 4623 case rv128: 4624 decode_inst_decompress_rv128(dec); 4625 break; 4626 } 4627 } 4628 4629 /* disassemble instruction */ 4630 4631 static void 4632 disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst) 4633 { 4634 rv_decode dec = { 0 }; 4635 dec.pc = pc; 4636 dec.inst = inst; 4637 decode_inst_opcode(&dec, isa); 4638 decode_inst_operands(&dec, isa); 4639 decode_inst_decompress(&dec, isa); 4640 decode_inst_lift_pseudo(&dec); 4641 format_inst(buf, buflen, 24, &dec); 4642 } 4643 4644 #define INST_FMT_2 "%04" PRIx64 " " 4645 #define INST_FMT_4 "%08" PRIx64 " " 4646 #define INST_FMT_6 "%012" PRIx64 " " 4647 #define INST_FMT_8 "%016" PRIx64 " " 4648 4649 static int 4650 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa) 4651 { 4652 char buf[128] = { 0 }; 4653 bfd_byte packet[2]; 4654 rv_inst inst = 0; 4655 size_t len = 2; 4656 bfd_vma n; 4657 int status; 4658 4659 /* Instructions are made of 2-byte packets in little-endian order */ 4660 for (n = 0; n < len; n += 2) { 4661 status = (*info->read_memory_func)(memaddr + n, packet, 2, info); 4662 if (status != 0) { 4663 /* Don't fail just because we fell off the end. */ 4664 if (n > 0) { 4665 break; 4666 } 4667 (*info->memory_error_func)(status, memaddr, info); 4668 return status; 4669 } 4670 inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n); 4671 if (n == 0) { 4672 len = inst_length(inst); 4673 } 4674 } 4675 4676 switch (len) { 4677 case 2: 4678 (*info->fprintf_func)(info->stream, INST_FMT_2, inst); 4679 break; 4680 case 4: 4681 (*info->fprintf_func)(info->stream, INST_FMT_4, inst); 4682 break; 4683 case 6: 4684 (*info->fprintf_func)(info->stream, INST_FMT_6, inst); 4685 break; 4686 default: 4687 (*info->fprintf_func)(info->stream, INST_FMT_8, inst); 4688 break; 4689 } 4690 4691 disasm_inst(buf, sizeof(buf), isa, memaddr, inst); 4692 (*info->fprintf_func)(info->stream, "%s", buf); 4693 4694 return len; 4695 } 4696 4697 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info) 4698 { 4699 return print_insn_riscv(memaddr, info, rv32); 4700 } 4701 4702 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info) 4703 { 4704 return print_insn_riscv(memaddr, info, rv64); 4705 } 4706 4707 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info) 4708 { 4709 return print_insn_riscv(memaddr, info, rv128); 4710 } 4711