xref: /openbmc/qemu/disas/riscv.c (revision 4d46d84e) 
1 /*
2  * QEMU RISC-V Disassembler
3  *
4  * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com>
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/bitops.h"
22 #include "disas/dis-asm.h"
23 #include "target/riscv/cpu_cfg.h"
24 #include "disas/riscv.h"
25 
26 /* Vendor extensions */
27 #include "disas/riscv-xthead.h"
28 #include "disas/riscv-xventana.h"
29 
30 typedef enum {
31     /* 0 is reserved for rv_op_illegal. */
32     rv_op_lui = 1,
33     rv_op_auipc = 2,
34     rv_op_jal = 3,
35     rv_op_jalr = 4,
36     rv_op_beq = 5,
37     rv_op_bne = 6,
38     rv_op_blt = 7,
39     rv_op_bge = 8,
40     rv_op_bltu = 9,
41     rv_op_bgeu = 10,
42     rv_op_lb = 11,
43     rv_op_lh = 12,
44     rv_op_lw = 13,
45     rv_op_lbu = 14,
46     rv_op_lhu = 15,
47     rv_op_sb = 16,
48     rv_op_sh = 17,
49     rv_op_sw = 18,
50     rv_op_addi = 19,
51     rv_op_slti = 20,
52     rv_op_sltiu = 21,
53     rv_op_xori = 22,
54     rv_op_ori = 23,
55     rv_op_andi = 24,
56     rv_op_slli = 25,
57     rv_op_srli = 26,
58     rv_op_srai = 27,
59     rv_op_add = 28,
60     rv_op_sub = 29,
61     rv_op_sll = 30,
62     rv_op_slt = 31,
63     rv_op_sltu = 32,
64     rv_op_xor = 33,
65     rv_op_srl = 34,
66     rv_op_sra = 35,
67     rv_op_or = 36,
68     rv_op_and = 37,
69     rv_op_fence = 38,
70     rv_op_fence_i = 39,
71     rv_op_lwu = 40,
72     rv_op_ld = 41,
73     rv_op_sd = 42,
74     rv_op_addiw = 43,
75     rv_op_slliw = 44,
76     rv_op_srliw = 45,
77     rv_op_sraiw = 46,
78     rv_op_addw = 47,
79     rv_op_subw = 48,
80     rv_op_sllw = 49,
81     rv_op_srlw = 50,
82     rv_op_sraw = 51,
83     rv_op_ldu = 52,
84     rv_op_lq = 53,
85     rv_op_sq = 54,
86     rv_op_addid = 55,
87     rv_op_sllid = 56,
88     rv_op_srlid = 57,
89     rv_op_sraid = 58,
90     rv_op_addd = 59,
91     rv_op_subd = 60,
92     rv_op_slld = 61,
93     rv_op_srld = 62,
94     rv_op_srad = 63,
95     rv_op_mul = 64,
96     rv_op_mulh = 65,
97     rv_op_mulhsu = 66,
98     rv_op_mulhu = 67,
99     rv_op_div = 68,
100     rv_op_divu = 69,
101     rv_op_rem = 70,
102     rv_op_remu = 71,
103     rv_op_mulw = 72,
104     rv_op_divw = 73,
105     rv_op_divuw = 74,
106     rv_op_remw = 75,
107     rv_op_remuw = 76,
108     rv_op_muld = 77,
109     rv_op_divd = 78,
110     rv_op_divud = 79,
111     rv_op_remd = 80,
112     rv_op_remud = 81,
113     rv_op_lr_w = 82,
114     rv_op_sc_w = 83,
115     rv_op_amoswap_w = 84,
116     rv_op_amoadd_w = 85,
117     rv_op_amoxor_w = 86,
118     rv_op_amoor_w = 87,
119     rv_op_amoand_w = 88,
120     rv_op_amomin_w = 89,
121     rv_op_amomax_w = 90,
122     rv_op_amominu_w = 91,
123     rv_op_amomaxu_w = 92,
124     rv_op_lr_d = 93,
125     rv_op_sc_d = 94,
126     rv_op_amoswap_d = 95,
127     rv_op_amoadd_d = 96,
128     rv_op_amoxor_d = 97,
129     rv_op_amoor_d = 98,
130     rv_op_amoand_d = 99,
131     rv_op_amomin_d = 100,
132     rv_op_amomax_d = 101,
133     rv_op_amominu_d = 102,
134     rv_op_amomaxu_d = 103,
135     rv_op_lr_q = 104,
136     rv_op_sc_q = 105,
137     rv_op_amoswap_q = 106,
138     rv_op_amoadd_q = 107,
139     rv_op_amoxor_q = 108,
140     rv_op_amoor_q = 109,
141     rv_op_amoand_q = 110,
142     rv_op_amomin_q = 111,
143     rv_op_amomax_q = 112,
144     rv_op_amominu_q = 113,
145     rv_op_amomaxu_q = 114,
146     rv_op_ecall = 115,
147     rv_op_ebreak = 116,
148     rv_op_uret = 117,
149     rv_op_sret = 118,
150     rv_op_hret = 119,
151     rv_op_mret = 120,
152     rv_op_dret = 121,
153     rv_op_sfence_vm = 122,
154     rv_op_sfence_vma = 123,
155     rv_op_wfi = 124,
156     rv_op_csrrw = 125,
157     rv_op_csrrs = 126,
158     rv_op_csrrc = 127,
159     rv_op_csrrwi = 128,
160     rv_op_csrrsi = 129,
161     rv_op_csrrci = 130,
162     rv_op_flw = 131,
163     rv_op_fsw = 132,
164     rv_op_fmadd_s = 133,
165     rv_op_fmsub_s = 134,
166     rv_op_fnmsub_s = 135,
167     rv_op_fnmadd_s = 136,
168     rv_op_fadd_s = 137,
169     rv_op_fsub_s = 138,
170     rv_op_fmul_s = 139,
171     rv_op_fdiv_s = 140,
172     rv_op_fsgnj_s = 141,
173     rv_op_fsgnjn_s = 142,
174     rv_op_fsgnjx_s = 143,
175     rv_op_fmin_s = 144,
176     rv_op_fmax_s = 145,
177     rv_op_fsqrt_s = 146,
178     rv_op_fle_s = 147,
179     rv_op_flt_s = 148,
180     rv_op_feq_s = 149,
181     rv_op_fcvt_w_s = 150,
182     rv_op_fcvt_wu_s = 151,
183     rv_op_fcvt_s_w = 152,
184     rv_op_fcvt_s_wu = 153,
185     rv_op_fmv_x_s = 154,
186     rv_op_fclass_s = 155,
187     rv_op_fmv_s_x = 156,
188     rv_op_fcvt_l_s = 157,
189     rv_op_fcvt_lu_s = 158,
190     rv_op_fcvt_s_l = 159,
191     rv_op_fcvt_s_lu = 160,
192     rv_op_fld = 161,
193     rv_op_fsd = 162,
194     rv_op_fmadd_d = 163,
195     rv_op_fmsub_d = 164,
196     rv_op_fnmsub_d = 165,
197     rv_op_fnmadd_d = 166,
198     rv_op_fadd_d = 167,
199     rv_op_fsub_d = 168,
200     rv_op_fmul_d = 169,
201     rv_op_fdiv_d = 170,
202     rv_op_fsgnj_d = 171,
203     rv_op_fsgnjn_d = 172,
204     rv_op_fsgnjx_d = 173,
205     rv_op_fmin_d = 174,
206     rv_op_fmax_d = 175,
207     rv_op_fcvt_s_d = 176,
208     rv_op_fcvt_d_s = 177,
209     rv_op_fsqrt_d = 178,
210     rv_op_fle_d = 179,
211     rv_op_flt_d = 180,
212     rv_op_feq_d = 181,
213     rv_op_fcvt_w_d = 182,
214     rv_op_fcvt_wu_d = 183,
215     rv_op_fcvt_d_w = 184,
216     rv_op_fcvt_d_wu = 185,
217     rv_op_fclass_d = 186,
218     rv_op_fcvt_l_d = 187,
219     rv_op_fcvt_lu_d = 188,
220     rv_op_fmv_x_d = 189,
221     rv_op_fcvt_d_l = 190,
222     rv_op_fcvt_d_lu = 191,
223     rv_op_fmv_d_x = 192,
224     rv_op_flq = 193,
225     rv_op_fsq = 194,
226     rv_op_fmadd_q = 195,
227     rv_op_fmsub_q = 196,
228     rv_op_fnmsub_q = 197,
229     rv_op_fnmadd_q = 198,
230     rv_op_fadd_q = 199,
231     rv_op_fsub_q = 200,
232     rv_op_fmul_q = 201,
233     rv_op_fdiv_q = 202,
234     rv_op_fsgnj_q = 203,
235     rv_op_fsgnjn_q = 204,
236     rv_op_fsgnjx_q = 205,
237     rv_op_fmin_q = 206,
238     rv_op_fmax_q = 207,
239     rv_op_fcvt_s_q = 208,
240     rv_op_fcvt_q_s = 209,
241     rv_op_fcvt_d_q = 210,
242     rv_op_fcvt_q_d = 211,
243     rv_op_fsqrt_q = 212,
244     rv_op_fle_q = 213,
245     rv_op_flt_q = 214,
246     rv_op_feq_q = 215,
247     rv_op_fcvt_w_q = 216,
248     rv_op_fcvt_wu_q = 217,
249     rv_op_fcvt_q_w = 218,
250     rv_op_fcvt_q_wu = 219,
251     rv_op_fclass_q = 220,
252     rv_op_fcvt_l_q = 221,
253     rv_op_fcvt_lu_q = 222,
254     rv_op_fcvt_q_l = 223,
255     rv_op_fcvt_q_lu = 224,
256     rv_op_fmv_x_q = 225,
257     rv_op_fmv_q_x = 226,
258     rv_op_c_addi4spn = 227,
259     rv_op_c_fld = 228,
260     rv_op_c_lw = 229,
261     rv_op_c_flw = 230,
262     rv_op_c_fsd = 231,
263     rv_op_c_sw = 232,
264     rv_op_c_fsw = 233,
265     rv_op_c_nop = 234,
266     rv_op_c_addi = 235,
267     rv_op_c_jal = 236,
268     rv_op_c_li = 237,
269     rv_op_c_addi16sp = 238,
270     rv_op_c_lui = 239,
271     rv_op_c_srli = 240,
272     rv_op_c_srai = 241,
273     rv_op_c_andi = 242,
274     rv_op_c_sub = 243,
275     rv_op_c_xor = 244,
276     rv_op_c_or = 245,
277     rv_op_c_and = 246,
278     rv_op_c_subw = 247,
279     rv_op_c_addw = 248,
280     rv_op_c_j = 249,
281     rv_op_c_beqz = 250,
282     rv_op_c_bnez = 251,
283     rv_op_c_slli = 252,
284     rv_op_c_fldsp = 253,
285     rv_op_c_lwsp = 254,
286     rv_op_c_flwsp = 255,
287     rv_op_c_jr = 256,
288     rv_op_c_mv = 257,
289     rv_op_c_ebreak = 258,
290     rv_op_c_jalr = 259,
291     rv_op_c_add = 260,
292     rv_op_c_fsdsp = 261,
293     rv_op_c_swsp = 262,
294     rv_op_c_fswsp = 263,
295     rv_op_c_ld = 264,
296     rv_op_c_sd = 265,
297     rv_op_c_addiw = 266,
298     rv_op_c_ldsp = 267,
299     rv_op_c_sdsp = 268,
300     rv_op_c_lq = 269,
301     rv_op_c_sq = 270,
302     rv_op_c_lqsp = 271,
303     rv_op_c_sqsp = 272,
304     rv_op_nop = 273,
305     rv_op_mv = 274,
306     rv_op_not = 275,
307     rv_op_neg = 276,
308     rv_op_negw = 277,
309     rv_op_sext_w = 278,
310     rv_op_seqz = 279,
311     rv_op_snez = 280,
312     rv_op_sltz = 281,
313     rv_op_sgtz = 282,
314     rv_op_fmv_s = 283,
315     rv_op_fabs_s = 284,
316     rv_op_fneg_s = 285,
317     rv_op_fmv_d = 286,
318     rv_op_fabs_d = 287,
319     rv_op_fneg_d = 288,
320     rv_op_fmv_q = 289,
321     rv_op_fabs_q = 290,
322     rv_op_fneg_q = 291,
323     rv_op_beqz = 292,
324     rv_op_bnez = 293,
325     rv_op_blez = 294,
326     rv_op_bgez = 295,
327     rv_op_bltz = 296,
328     rv_op_bgtz = 297,
329     rv_op_ble = 298,
330     rv_op_bleu = 299,
331     rv_op_bgt = 300,
332     rv_op_bgtu = 301,
333     rv_op_j = 302,
334     rv_op_ret = 303,
335     rv_op_jr = 304,
336     rv_op_rdcycle = 305,
337     rv_op_rdtime = 306,
338     rv_op_rdinstret = 307,
339     rv_op_rdcycleh = 308,
340     rv_op_rdtimeh = 309,
341     rv_op_rdinstreth = 310,
342     rv_op_frcsr = 311,
343     rv_op_frrm = 312,
344     rv_op_frflags = 313,
345     rv_op_fscsr = 314,
346     rv_op_fsrm = 315,
347     rv_op_fsflags = 316,
348     rv_op_fsrmi = 317,
349     rv_op_fsflagsi = 318,
350     rv_op_bseti = 319,
351     rv_op_bclri = 320,
352     rv_op_binvi = 321,
353     rv_op_bexti = 322,
354     rv_op_rori = 323,
355     rv_op_clz = 324,
356     rv_op_ctz = 325,
357     rv_op_cpop = 326,
358     rv_op_sext_h = 327,
359     rv_op_sext_b = 328,
360     rv_op_xnor = 329,
361     rv_op_orn = 330,
362     rv_op_andn = 331,
363     rv_op_rol = 332,
364     rv_op_ror = 333,
365     rv_op_sh1add = 334,
366     rv_op_sh2add = 335,
367     rv_op_sh3add = 336,
368     rv_op_sh1add_uw = 337,
369     rv_op_sh2add_uw = 338,
370     rv_op_sh3add_uw = 339,
371     rv_op_clmul = 340,
372     rv_op_clmulr = 341,
373     rv_op_clmulh = 342,
374     rv_op_min = 343,
375     rv_op_minu = 344,
376     rv_op_max = 345,
377     rv_op_maxu = 346,
378     rv_op_clzw = 347,
379     rv_op_ctzw = 348,
380     rv_op_cpopw = 349,
381     rv_op_slli_uw = 350,
382     rv_op_add_uw = 351,
383     rv_op_rolw = 352,
384     rv_op_rorw = 353,
385     rv_op_rev8 = 354,
386     rv_op_zext_h = 355,
387     rv_op_roriw = 356,
388     rv_op_orc_b = 357,
389     rv_op_bset = 358,
390     rv_op_bclr = 359,
391     rv_op_binv = 360,
392     rv_op_bext = 361,
393     rv_op_aes32esmi = 362,
394     rv_op_aes32esi = 363,
395     rv_op_aes32dsmi = 364,
396     rv_op_aes32dsi = 365,
397     rv_op_aes64ks1i = 366,
398     rv_op_aes64ks2 = 367,
399     rv_op_aes64im = 368,
400     rv_op_aes64esm = 369,
401     rv_op_aes64es = 370,
402     rv_op_aes64dsm = 371,
403     rv_op_aes64ds = 372,
404     rv_op_sha256sig0 = 373,
405     rv_op_sha256sig1 = 374,
406     rv_op_sha256sum0 = 375,
407     rv_op_sha256sum1 = 376,
408     rv_op_sha512sig0 = 377,
409     rv_op_sha512sig1 = 378,
410     rv_op_sha512sum0 = 379,
411     rv_op_sha512sum1 = 380,
412     rv_op_sha512sum0r = 381,
413     rv_op_sha512sum1r = 382,
414     rv_op_sha512sig0l = 383,
415     rv_op_sha512sig0h = 384,
416     rv_op_sha512sig1l = 385,
417     rv_op_sha512sig1h = 386,
418     rv_op_sm3p0 = 387,
419     rv_op_sm3p1 = 388,
420     rv_op_sm4ed = 389,
421     rv_op_sm4ks = 390,
422     rv_op_brev8 = 391,
423     rv_op_pack = 392,
424     rv_op_packh = 393,
425     rv_op_packw = 394,
426     rv_op_unzip = 395,
427     rv_op_zip = 396,
428     rv_op_xperm4 = 397,
429     rv_op_xperm8 = 398,
430     rv_op_vle8_v = 399,
431     rv_op_vle16_v = 400,
432     rv_op_vle32_v = 401,
433     rv_op_vle64_v = 402,
434     rv_op_vse8_v = 403,
435     rv_op_vse16_v = 404,
436     rv_op_vse32_v = 405,
437     rv_op_vse64_v = 406,
438     rv_op_vlm_v = 407,
439     rv_op_vsm_v = 408,
440     rv_op_vlse8_v = 409,
441     rv_op_vlse16_v = 410,
442     rv_op_vlse32_v = 411,
443     rv_op_vlse64_v = 412,
444     rv_op_vsse8_v = 413,
445     rv_op_vsse16_v = 414,
446     rv_op_vsse32_v = 415,
447     rv_op_vsse64_v = 416,
448     rv_op_vluxei8_v = 417,
449     rv_op_vluxei16_v = 418,
450     rv_op_vluxei32_v = 419,
451     rv_op_vluxei64_v = 420,
452     rv_op_vloxei8_v = 421,
453     rv_op_vloxei16_v = 422,
454     rv_op_vloxei32_v = 423,
455     rv_op_vloxei64_v = 424,
456     rv_op_vsuxei8_v = 425,
457     rv_op_vsuxei16_v = 426,
458     rv_op_vsuxei32_v = 427,
459     rv_op_vsuxei64_v = 428,
460     rv_op_vsoxei8_v = 429,
461     rv_op_vsoxei16_v = 430,
462     rv_op_vsoxei32_v = 431,
463     rv_op_vsoxei64_v = 432,
464     rv_op_vle8ff_v = 433,
465     rv_op_vle16ff_v = 434,
466     rv_op_vle32ff_v = 435,
467     rv_op_vle64ff_v = 436,
468     rv_op_vl1re8_v = 437,
469     rv_op_vl1re16_v = 438,
470     rv_op_vl1re32_v = 439,
471     rv_op_vl1re64_v = 440,
472     rv_op_vl2re8_v = 441,
473     rv_op_vl2re16_v = 442,
474     rv_op_vl2re32_v = 443,
475     rv_op_vl2re64_v = 444,
476     rv_op_vl4re8_v = 445,
477     rv_op_vl4re16_v = 446,
478     rv_op_vl4re32_v = 447,
479     rv_op_vl4re64_v = 448,
480     rv_op_vl8re8_v = 449,
481     rv_op_vl8re16_v = 450,
482     rv_op_vl8re32_v = 451,
483     rv_op_vl8re64_v = 452,
484     rv_op_vs1r_v = 453,
485     rv_op_vs2r_v = 454,
486     rv_op_vs4r_v = 455,
487     rv_op_vs8r_v = 456,
488     rv_op_vadd_vv = 457,
489     rv_op_vadd_vx = 458,
490     rv_op_vadd_vi = 459,
491     rv_op_vsub_vv = 460,
492     rv_op_vsub_vx = 461,
493     rv_op_vrsub_vx = 462,
494     rv_op_vrsub_vi = 463,
495     rv_op_vwaddu_vv = 464,
496     rv_op_vwaddu_vx = 465,
497     rv_op_vwadd_vv = 466,
498     rv_op_vwadd_vx = 467,
499     rv_op_vwsubu_vv = 468,
500     rv_op_vwsubu_vx = 469,
501     rv_op_vwsub_vv = 470,
502     rv_op_vwsub_vx = 471,
503     rv_op_vwaddu_wv = 472,
504     rv_op_vwaddu_wx = 473,
505     rv_op_vwadd_wv = 474,
506     rv_op_vwadd_wx = 475,
507     rv_op_vwsubu_wv = 476,
508     rv_op_vwsubu_wx = 477,
509     rv_op_vwsub_wv = 478,
510     rv_op_vwsub_wx = 479,
511     rv_op_vadc_vvm = 480,
512     rv_op_vadc_vxm = 481,
513     rv_op_vadc_vim = 482,
514     rv_op_vmadc_vvm = 483,
515     rv_op_vmadc_vxm = 484,
516     rv_op_vmadc_vim = 485,
517     rv_op_vsbc_vvm = 486,
518     rv_op_vsbc_vxm = 487,
519     rv_op_vmsbc_vvm = 488,
520     rv_op_vmsbc_vxm = 489,
521     rv_op_vand_vv = 490,
522     rv_op_vand_vx = 491,
523     rv_op_vand_vi = 492,
524     rv_op_vor_vv = 493,
525     rv_op_vor_vx = 494,
526     rv_op_vor_vi = 495,
527     rv_op_vxor_vv = 496,
528     rv_op_vxor_vx = 497,
529     rv_op_vxor_vi = 498,
530     rv_op_vsll_vv = 499,
531     rv_op_vsll_vx = 500,
532     rv_op_vsll_vi = 501,
533     rv_op_vsrl_vv = 502,
534     rv_op_vsrl_vx = 503,
535     rv_op_vsrl_vi = 504,
536     rv_op_vsra_vv = 505,
537     rv_op_vsra_vx = 506,
538     rv_op_vsra_vi = 507,
539     rv_op_vnsrl_wv = 508,
540     rv_op_vnsrl_wx = 509,
541     rv_op_vnsrl_wi = 510,
542     rv_op_vnsra_wv = 511,
543     rv_op_vnsra_wx = 512,
544     rv_op_vnsra_wi = 513,
545     rv_op_vmseq_vv = 514,
546     rv_op_vmseq_vx = 515,
547     rv_op_vmseq_vi = 516,
548     rv_op_vmsne_vv = 517,
549     rv_op_vmsne_vx = 518,
550     rv_op_vmsne_vi = 519,
551     rv_op_vmsltu_vv = 520,
552     rv_op_vmsltu_vx = 521,
553     rv_op_vmslt_vv = 522,
554     rv_op_vmslt_vx = 523,
555     rv_op_vmsleu_vv = 524,
556     rv_op_vmsleu_vx = 525,
557     rv_op_vmsleu_vi = 526,
558     rv_op_vmsle_vv = 527,
559     rv_op_vmsle_vx = 528,
560     rv_op_vmsle_vi = 529,
561     rv_op_vmsgtu_vx = 530,
562     rv_op_vmsgtu_vi = 531,
563     rv_op_vmsgt_vx = 532,
564     rv_op_vmsgt_vi = 533,
565     rv_op_vminu_vv = 534,
566     rv_op_vminu_vx = 535,
567     rv_op_vmin_vv = 536,
568     rv_op_vmin_vx = 537,
569     rv_op_vmaxu_vv = 538,
570     rv_op_vmaxu_vx = 539,
571     rv_op_vmax_vv = 540,
572     rv_op_vmax_vx = 541,
573     rv_op_vmul_vv = 542,
574     rv_op_vmul_vx = 543,
575     rv_op_vmulh_vv = 544,
576     rv_op_vmulh_vx = 545,
577     rv_op_vmulhu_vv = 546,
578     rv_op_vmulhu_vx = 547,
579     rv_op_vmulhsu_vv = 548,
580     rv_op_vmulhsu_vx = 549,
581     rv_op_vdivu_vv = 550,
582     rv_op_vdivu_vx = 551,
583     rv_op_vdiv_vv = 552,
584     rv_op_vdiv_vx = 553,
585     rv_op_vremu_vv = 554,
586     rv_op_vremu_vx = 555,
587     rv_op_vrem_vv = 556,
588     rv_op_vrem_vx = 557,
589     rv_op_vwmulu_vv = 558,
590     rv_op_vwmulu_vx = 559,
591     rv_op_vwmulsu_vv = 560,
592     rv_op_vwmulsu_vx = 561,
593     rv_op_vwmul_vv = 562,
594     rv_op_vwmul_vx = 563,
595     rv_op_vmacc_vv = 564,
596     rv_op_vmacc_vx = 565,
597     rv_op_vnmsac_vv = 566,
598     rv_op_vnmsac_vx = 567,
599     rv_op_vmadd_vv = 568,
600     rv_op_vmadd_vx = 569,
601     rv_op_vnmsub_vv = 570,
602     rv_op_vnmsub_vx = 571,
603     rv_op_vwmaccu_vv = 572,
604     rv_op_vwmaccu_vx = 573,
605     rv_op_vwmacc_vv = 574,
606     rv_op_vwmacc_vx = 575,
607     rv_op_vwmaccsu_vv = 576,
608     rv_op_vwmaccsu_vx = 577,
609     rv_op_vwmaccus_vx = 578,
610     rv_op_vmv_v_v = 579,
611     rv_op_vmv_v_x = 580,
612     rv_op_vmv_v_i = 581,
613     rv_op_vmerge_vvm = 582,
614     rv_op_vmerge_vxm = 583,
615     rv_op_vmerge_vim = 584,
616     rv_op_vsaddu_vv = 585,
617     rv_op_vsaddu_vx = 586,
618     rv_op_vsaddu_vi = 587,
619     rv_op_vsadd_vv = 588,
620     rv_op_vsadd_vx = 589,
621     rv_op_vsadd_vi = 590,
622     rv_op_vssubu_vv = 591,
623     rv_op_vssubu_vx = 592,
624     rv_op_vssub_vv = 593,
625     rv_op_vssub_vx = 594,
626     rv_op_vaadd_vv = 595,
627     rv_op_vaadd_vx = 596,
628     rv_op_vaaddu_vv = 597,
629     rv_op_vaaddu_vx = 598,
630     rv_op_vasub_vv = 599,
631     rv_op_vasub_vx = 600,
632     rv_op_vasubu_vv = 601,
633     rv_op_vasubu_vx = 602,
634     rv_op_vsmul_vv = 603,
635     rv_op_vsmul_vx = 604,
636     rv_op_vssrl_vv = 605,
637     rv_op_vssrl_vx = 606,
638     rv_op_vssrl_vi = 607,
639     rv_op_vssra_vv = 608,
640     rv_op_vssra_vx = 609,
641     rv_op_vssra_vi = 610,
642     rv_op_vnclipu_wv = 611,
643     rv_op_vnclipu_wx = 612,
644     rv_op_vnclipu_wi = 613,
645     rv_op_vnclip_wv = 614,
646     rv_op_vnclip_wx = 615,
647     rv_op_vnclip_wi = 616,
648     rv_op_vfadd_vv = 617,
649     rv_op_vfadd_vf = 618,
650     rv_op_vfsub_vv = 619,
651     rv_op_vfsub_vf = 620,
652     rv_op_vfrsub_vf = 621,
653     rv_op_vfwadd_vv = 622,
654     rv_op_vfwadd_vf = 623,
655     rv_op_vfwadd_wv = 624,
656     rv_op_vfwadd_wf = 625,
657     rv_op_vfwsub_vv = 626,
658     rv_op_vfwsub_vf = 627,
659     rv_op_vfwsub_wv = 628,
660     rv_op_vfwsub_wf = 629,
661     rv_op_vfmul_vv = 630,
662     rv_op_vfmul_vf = 631,
663     rv_op_vfdiv_vv = 632,
664     rv_op_vfdiv_vf = 633,
665     rv_op_vfrdiv_vf = 634,
666     rv_op_vfwmul_vv = 635,
667     rv_op_vfwmul_vf = 636,
668     rv_op_vfmacc_vv = 637,
669     rv_op_vfmacc_vf = 638,
670     rv_op_vfnmacc_vv = 639,
671     rv_op_vfnmacc_vf = 640,
672     rv_op_vfmsac_vv = 641,
673     rv_op_vfmsac_vf = 642,
674     rv_op_vfnmsac_vv = 643,
675     rv_op_vfnmsac_vf = 644,
676     rv_op_vfmadd_vv = 645,
677     rv_op_vfmadd_vf = 646,
678     rv_op_vfnmadd_vv = 647,
679     rv_op_vfnmadd_vf = 648,
680     rv_op_vfmsub_vv = 649,
681     rv_op_vfmsub_vf = 650,
682     rv_op_vfnmsub_vv = 651,
683     rv_op_vfnmsub_vf = 652,
684     rv_op_vfwmacc_vv = 653,
685     rv_op_vfwmacc_vf = 654,
686     rv_op_vfwnmacc_vv = 655,
687     rv_op_vfwnmacc_vf = 656,
688     rv_op_vfwmsac_vv = 657,
689     rv_op_vfwmsac_vf = 658,
690     rv_op_vfwnmsac_vv = 659,
691     rv_op_vfwnmsac_vf = 660,
692     rv_op_vfsqrt_v = 661,
693     rv_op_vfrsqrt7_v = 662,
694     rv_op_vfrec7_v = 663,
695     rv_op_vfmin_vv = 664,
696     rv_op_vfmin_vf = 665,
697     rv_op_vfmax_vv = 666,
698     rv_op_vfmax_vf = 667,
699     rv_op_vfsgnj_vv = 668,
700     rv_op_vfsgnj_vf = 669,
701     rv_op_vfsgnjn_vv = 670,
702     rv_op_vfsgnjn_vf = 671,
703     rv_op_vfsgnjx_vv = 672,
704     rv_op_vfsgnjx_vf = 673,
705     rv_op_vfslide1up_vf = 674,
706     rv_op_vfslide1down_vf = 675,
707     rv_op_vmfeq_vv = 676,
708     rv_op_vmfeq_vf = 677,
709     rv_op_vmfne_vv = 678,
710     rv_op_vmfne_vf = 679,
711     rv_op_vmflt_vv = 680,
712     rv_op_vmflt_vf = 681,
713     rv_op_vmfle_vv = 682,
714     rv_op_vmfle_vf = 683,
715     rv_op_vmfgt_vf = 684,
716     rv_op_vmfge_vf = 685,
717     rv_op_vfclass_v = 686,
718     rv_op_vfmerge_vfm = 687,
719     rv_op_vfmv_v_f = 688,
720     rv_op_vfcvt_xu_f_v = 689,
721     rv_op_vfcvt_x_f_v = 690,
722     rv_op_vfcvt_f_xu_v = 691,
723     rv_op_vfcvt_f_x_v = 692,
724     rv_op_vfcvt_rtz_xu_f_v = 693,
725     rv_op_vfcvt_rtz_x_f_v = 694,
726     rv_op_vfwcvt_xu_f_v = 695,
727     rv_op_vfwcvt_x_f_v = 696,
728     rv_op_vfwcvt_f_xu_v = 697,
729     rv_op_vfwcvt_f_x_v = 698,
730     rv_op_vfwcvt_f_f_v = 699,
731     rv_op_vfwcvt_rtz_xu_f_v = 700,
732     rv_op_vfwcvt_rtz_x_f_v = 701,
733     rv_op_vfncvt_xu_f_w = 702,
734     rv_op_vfncvt_x_f_w = 703,
735     rv_op_vfncvt_f_xu_w = 704,
736     rv_op_vfncvt_f_x_w = 705,
737     rv_op_vfncvt_f_f_w = 706,
738     rv_op_vfncvt_rod_f_f_w = 707,
739     rv_op_vfncvt_rtz_xu_f_w = 708,
740     rv_op_vfncvt_rtz_x_f_w = 709,
741     rv_op_vredsum_vs = 710,
742     rv_op_vredand_vs = 711,
743     rv_op_vredor_vs = 712,
744     rv_op_vredxor_vs = 713,
745     rv_op_vredminu_vs = 714,
746     rv_op_vredmin_vs = 715,
747     rv_op_vredmaxu_vs = 716,
748     rv_op_vredmax_vs = 717,
749     rv_op_vwredsumu_vs = 718,
750     rv_op_vwredsum_vs = 719,
751     rv_op_vfredusum_vs = 720,
752     rv_op_vfredosum_vs = 721,
753     rv_op_vfredmin_vs = 722,
754     rv_op_vfredmax_vs = 723,
755     rv_op_vfwredusum_vs = 724,
756     rv_op_vfwredosum_vs = 725,
757     rv_op_vmand_mm = 726,
758     rv_op_vmnand_mm = 727,
759     rv_op_vmandn_mm = 728,
760     rv_op_vmxor_mm = 729,
761     rv_op_vmor_mm = 730,
762     rv_op_vmnor_mm = 731,
763     rv_op_vmorn_mm = 732,
764     rv_op_vmxnor_mm = 733,
765     rv_op_vcpop_m = 734,
766     rv_op_vfirst_m = 735,
767     rv_op_vmsbf_m = 736,
768     rv_op_vmsif_m = 737,
769     rv_op_vmsof_m = 738,
770     rv_op_viota_m = 739,
771     rv_op_vid_v = 740,
772     rv_op_vmv_x_s = 741,
773     rv_op_vmv_s_x = 742,
774     rv_op_vfmv_f_s = 743,
775     rv_op_vfmv_s_f = 744,
776     rv_op_vslideup_vx = 745,
777     rv_op_vslideup_vi = 746,
778     rv_op_vslide1up_vx = 747,
779     rv_op_vslidedown_vx = 748,
780     rv_op_vslidedown_vi = 749,
781     rv_op_vslide1down_vx = 750,
782     rv_op_vrgather_vv = 751,
783     rv_op_vrgatherei16_vv = 752,
784     rv_op_vrgather_vx = 753,
785     rv_op_vrgather_vi = 754,
786     rv_op_vcompress_vm = 755,
787     rv_op_vmv1r_v = 756,
788     rv_op_vmv2r_v = 757,
789     rv_op_vmv4r_v = 758,
790     rv_op_vmv8r_v = 759,
791     rv_op_vzext_vf2 = 760,
792     rv_op_vzext_vf4 = 761,
793     rv_op_vzext_vf8 = 762,
794     rv_op_vsext_vf2 = 763,
795     rv_op_vsext_vf4 = 764,
796     rv_op_vsext_vf8 = 765,
797     rv_op_vsetvli = 766,
798     rv_op_vsetivli = 767,
799     rv_op_vsetvl = 768,
800     rv_op_c_zext_b = 769,
801     rv_op_c_sext_b = 770,
802     rv_op_c_zext_h = 771,
803     rv_op_c_sext_h = 772,
804     rv_op_c_zext_w = 773,
805     rv_op_c_not = 774,
806     rv_op_c_mul = 775,
807     rv_op_c_lbu = 776,
808     rv_op_c_lhu = 777,
809     rv_op_c_lh = 778,
810     rv_op_c_sb = 779,
811     rv_op_c_sh = 780,
812     rv_op_cm_push = 781,
813     rv_op_cm_pop = 782,
814     rv_op_cm_popret = 783,
815     rv_op_cm_popretz = 784,
816     rv_op_cm_mva01s = 785,
817     rv_op_cm_mvsa01 = 786,
818     rv_op_cm_jt = 787,
819     rv_op_cm_jalt = 788,
820     rv_op_czero_eqz = 789,
821     rv_op_czero_nez = 790,
822     rv_op_fcvt_bf16_s = 791,
823     rv_op_fcvt_s_bf16 = 792,
824     rv_op_vfncvtbf16_f_f_w = 793,
825     rv_op_vfwcvtbf16_f_f_v = 794,
826     rv_op_vfwmaccbf16_vv = 795,
827     rv_op_vfwmaccbf16_vf = 796,
828     rv_op_flh = 797,
829     rv_op_fsh = 798,
830     rv_op_fmv_h_x = 799,
831     rv_op_fmv_x_h = 800,
832     rv_op_fli_s = 801,
833     rv_op_fli_d = 802,
834     rv_op_fli_q = 803,
835     rv_op_fli_h = 804,
836     rv_op_fminm_s = 805,
837     rv_op_fmaxm_s = 806,
838     rv_op_fminm_d = 807,
839     rv_op_fmaxm_d = 808,
840     rv_op_fminm_q = 809,
841     rv_op_fmaxm_q = 810,
842     rv_op_fminm_h = 811,
843     rv_op_fmaxm_h = 812,
844     rv_op_fround_s = 813,
845     rv_op_froundnx_s = 814,
846     rv_op_fround_d = 815,
847     rv_op_froundnx_d = 816,
848     rv_op_fround_q = 817,
849     rv_op_froundnx_q = 818,
850     rv_op_fround_h = 819,
851     rv_op_froundnx_h = 820,
852     rv_op_fcvtmod_w_d = 821,
853     rv_op_fmvh_x_d = 822,
854     rv_op_fmvp_d_x = 823,
855     rv_op_fmvh_x_q = 824,
856     rv_op_fmvp_q_x = 825,
857     rv_op_fleq_s = 826,
858     rv_op_fltq_s = 827,
859     rv_op_fleq_d = 828,
860     rv_op_fltq_d = 829,
861     rv_op_fleq_q = 830,
862     rv_op_fltq_q = 831,
863     rv_op_fleq_h = 832,
864     rv_op_fltq_h = 833,
865     rv_op_vaesdf_vv = 834,
866     rv_op_vaesdf_vs = 835,
867     rv_op_vaesdm_vv = 836,
868     rv_op_vaesdm_vs = 837,
869     rv_op_vaesef_vv = 838,
870     rv_op_vaesef_vs = 839,
871     rv_op_vaesem_vv = 840,
872     rv_op_vaesem_vs = 841,
873     rv_op_vaeskf1_vi = 842,
874     rv_op_vaeskf2_vi = 843,
875     rv_op_vaesz_vs = 844,
876     rv_op_vandn_vv = 845,
877     rv_op_vandn_vx = 846,
878     rv_op_vbrev_v = 847,
879     rv_op_vbrev8_v = 848,
880     rv_op_vclmul_vv = 849,
881     rv_op_vclmul_vx = 850,
882     rv_op_vclmulh_vv = 851,
883     rv_op_vclmulh_vx = 852,
884     rv_op_vclz_v = 853,
885     rv_op_vcpop_v = 854,
886     rv_op_vctz_v = 855,
887     rv_op_vghsh_vv = 856,
888     rv_op_vgmul_vv = 857,
889     rv_op_vrev8_v = 858,
890     rv_op_vrol_vv = 859,
891     rv_op_vrol_vx = 860,
892     rv_op_vror_vv = 861,
893     rv_op_vror_vx = 862,
894     rv_op_vror_vi = 863,
895     rv_op_vsha2ch_vv = 864,
896     rv_op_vsha2cl_vv = 865,
897     rv_op_vsha2ms_vv = 866,
898     rv_op_vsm3c_vi = 867,
899     rv_op_vsm3me_vv = 868,
900     rv_op_vsm4k_vi = 869,
901     rv_op_vsm4r_vv = 870,
902     rv_op_vsm4r_vs = 871,
903     rv_op_vwsll_vv = 872,
904     rv_op_vwsll_vx = 873,
905     rv_op_vwsll_vi = 874,
906     rv_op_amocas_w = 875,
907     rv_op_amocas_d = 876,
908     rv_op_amocas_q = 877,
909     rv_mop_r_0     = 878,
910     rv_mop_r_1     = 879,
911     rv_mop_r_2     = 880,
912     rv_mop_r_3     = 881,
913     rv_mop_r_4     = 882,
914     rv_mop_r_5     = 883,
915     rv_mop_r_6     = 884,
916     rv_mop_r_7     = 885,
917     rv_mop_r_8     = 886,
918     rv_mop_r_9     = 887,
919     rv_mop_r_10    = 888,
920     rv_mop_r_11    = 889,
921     rv_mop_r_12    = 890,
922     rv_mop_r_13    = 891,
923     rv_mop_r_14    = 892,
924     rv_mop_r_15    = 893,
925     rv_mop_r_16    = 894,
926     rv_mop_r_17    = 895,
927     rv_mop_r_18    = 896,
928     rv_mop_r_19    = 897,
929     rv_mop_r_20    = 898,
930     rv_mop_r_21    = 899,
931     rv_mop_r_22    = 900,
932     rv_mop_r_23    = 901,
933     rv_mop_r_24    = 902,
934     rv_mop_r_25    = 903,
935     rv_mop_r_26    = 904,
936     rv_mop_r_27    = 905,
937     rv_mop_r_28    = 906,
938     rv_mop_r_29    = 907,
939     rv_mop_r_30    = 908,
940     rv_mop_r_31    = 909,
941     rv_mop_rr_0    = 910,
942     rv_mop_rr_1    = 911,
943     rv_mop_rr_2    = 912,
944     rv_mop_rr_3    = 913,
945     rv_mop_rr_4    = 914,
946     rv_mop_rr_5    = 915,
947     rv_mop_rr_6    = 916,
948     rv_mop_rr_7    = 917,
949     rv_c_mop_1     = 918,
950     rv_c_mop_3     = 919,
951     rv_c_mop_5     = 920,
952     rv_c_mop_7     = 921,
953     rv_c_mop_9     = 922,
954     rv_c_mop_11    = 923,
955     rv_c_mop_13    = 924,
956     rv_c_mop_15    = 925,
957     rv_op_amoswap_b = 926,
958     rv_op_amoadd_b  = 927,
959     rv_op_amoxor_b  = 928,
960     rv_op_amoor_b   = 929,
961     rv_op_amoand_b  = 930,
962     rv_op_amomin_b  = 931,
963     rv_op_amomax_b  = 932,
964     rv_op_amominu_b = 933,
965     rv_op_amomaxu_b = 934,
966     rv_op_amoswap_h = 935,
967     rv_op_amoadd_h  = 936,
968     rv_op_amoxor_h  = 937,
969     rv_op_amoor_h   = 938,
970     rv_op_amoand_h  = 939,
971     rv_op_amomin_h  = 940,
972     rv_op_amomax_h  = 941,
973     rv_op_amominu_h = 942,
974     rv_op_amomaxu_h = 943,
975     rv_op_amocas_b  = 944,
976     rv_op_amocas_h  = 945,
977     rv_op_wrs_sto = 946,
978     rv_op_wrs_nto = 947,
979 } rv_op;
980 
981 /* register names */
982 
983 static const char rv_ireg_name_sym[32][5] = {
984     "zero", "ra",   "sp",   "gp",   "tp",   "t0",   "t1",   "t2",
985     "s0",   "s1",   "a0",   "a1",   "a2",   "a3",   "a4",   "a5",
986     "a6",   "a7",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
987     "s8",   "s9",   "s10",  "s11",  "t3",   "t4",   "t5",   "t6",
988 };
989 
990 static const char rv_freg_name_sym[32][5] = {
991     "ft0",  "ft1",  "ft2",  "ft3",  "ft4",  "ft5",  "ft6",  "ft7",
992     "fs0",  "fs1",  "fa0",  "fa1",  "fa2",  "fa3",  "fa4",  "fa5",
993     "fa6",  "fa7",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7",
994     "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11",
995 };
996 
997 static const char rv_vreg_name_sym[32][4] = {
998     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
999     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
1000     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1001     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
1002 };
1003 
1004 /* The FLI.[HSDQ] numeric constants (0.0 for symbolic constants).
1005  * The constants use the hex floating-point literal representation
1006  * that is printed when using the printf %a format specifier,
1007  * which matches the output that is generated by the disassembler.
1008  */
1009 static const char rv_fli_name_const[32][9] =
1010 {
1011     "0x1p+0", "min", "0x1p-16", "0x1p-15",
1012     "0x1p-8", "0x1p-7", "0x1p-4", "0x1p-3",
1013     "0x1p-2", "0x1.4p-2", "0x1.8p-2", "0x1.cp-2",
1014     "0x1p-1", "0x1.4p-1", "0x1.8p-1", "0x1.cp-1",
1015     "0x1p+0", "0x1.4p+0", "0x1.8p+0", "0x1.cp+0",
1016     "0x1p+1", "0x1.4p+1", "0x1.8p+1", "0x1p+2",
1017     "0x1p+3", "0x1p+4", "0x1p+7", "0x1p+8",
1018     "0x1p+15", "0x1p+16", "inf", "nan"
1019 };
1020 
1021 /* pseudo-instruction constraints */
1022 
1023 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
1024 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero,
1025                                             rvc_end };
1026 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0,
1027                                            rvc_imm_eq_zero, rvc_end };
1028 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
1029 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
1030 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
1031 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
1032 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
1033 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
1034 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
1035 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
1036 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end };
1037 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end };
1038 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end };
1039 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end };
1040 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end };
1041 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end };
1042 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end };
1043 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end };
1044 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end };
1045 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end };
1046 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end };
1047 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end };
1048 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end };
1049 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end };
1050 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end };
1051 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end };
1052 static const rvc_constraint rvcc_ble[] = { rvc_end };
1053 static const rvc_constraint rvcc_bleu[] = { rvc_end };
1054 static const rvc_constraint rvcc_bgt[] = { rvc_end };
1055 static const rvc_constraint rvcc_bgtu[] = { rvc_end };
1056 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
1057 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
1058                                            rvc_end };
1059 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
1060                                           rvc_end };
1061 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00,
1062                                                rvc_end };
1063 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01,
1064                                               rvc_end };
1065 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
1066                                                  rvc_csr_eq_0xc02, rvc_end };
1067 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
1068                                                 rvc_csr_eq_0xc80, rvc_end };
1069 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81,
1070                                                rvc_end };
1071 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
1072                                                   rvc_csr_eq_0xc82, rvc_end };
1073 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003,
1074                                              rvc_end };
1075 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
1076                                             rvc_end };
1077 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001,
1078                                                rvc_end };
1079 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
1080 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
1081 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
1082 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
1083 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
1084 
1085 /* pseudo-instruction metadata */
1086 
1087 static const rv_comp_data rvcp_jal[] = {
1088     { rv_op_j, rvcc_j },
1089     { rv_op_jal, rvcc_jal },
1090     { rv_op_illegal, NULL }
1091 };
1092 
1093 static const rv_comp_data rvcp_jalr[] = {
1094     { rv_op_ret, rvcc_ret },
1095     { rv_op_jr, rvcc_jr },
1096     { rv_op_jalr, rvcc_jalr },
1097     { rv_op_illegal, NULL }
1098 };
1099 
1100 static const rv_comp_data rvcp_beq[] = {
1101     { rv_op_beqz, rvcc_beqz },
1102     { rv_op_illegal, NULL }
1103 };
1104 
1105 static const rv_comp_data rvcp_bne[] = {
1106     { rv_op_bnez, rvcc_bnez },
1107     { rv_op_illegal, NULL }
1108 };
1109 
1110 static const rv_comp_data rvcp_blt[] = {
1111     { rv_op_bltz, rvcc_bltz },
1112     { rv_op_bgtz, rvcc_bgtz },
1113     { rv_op_bgt, rvcc_bgt },
1114     { rv_op_illegal, NULL }
1115 };
1116 
1117 static const rv_comp_data rvcp_bge[] = {
1118     { rv_op_blez, rvcc_blez },
1119     { rv_op_bgez, rvcc_bgez },
1120     { rv_op_ble, rvcc_ble },
1121     { rv_op_illegal, NULL }
1122 };
1123 
1124 static const rv_comp_data rvcp_bltu[] = {
1125     { rv_op_bgtu, rvcc_bgtu },
1126     { rv_op_illegal, NULL }
1127 };
1128 
1129 static const rv_comp_data rvcp_bgeu[] = {
1130     { rv_op_bleu, rvcc_bleu },
1131     { rv_op_illegal, NULL }
1132 };
1133 
1134 static const rv_comp_data rvcp_addi[] = {
1135     { rv_op_nop, rvcc_nop },
1136     { rv_op_mv, rvcc_mv },
1137     { rv_op_illegal, NULL }
1138 };
1139 
1140 static const rv_comp_data rvcp_sltiu[] = {
1141     { rv_op_seqz, rvcc_seqz },
1142     { rv_op_illegal, NULL }
1143 };
1144 
1145 static const rv_comp_data rvcp_xori[] = {
1146     { rv_op_not, rvcc_not },
1147     { rv_op_illegal, NULL }
1148 };
1149 
1150 static const rv_comp_data rvcp_sub[] = {
1151     { rv_op_neg, rvcc_neg },
1152     { rv_op_illegal, NULL }
1153 };
1154 
1155 static const rv_comp_data rvcp_slt[] = {
1156     { rv_op_sltz, rvcc_sltz },
1157     { rv_op_sgtz, rvcc_sgtz },
1158     { rv_op_illegal, NULL }
1159 };
1160 
1161 static const rv_comp_data rvcp_sltu[] = {
1162     { rv_op_snez, rvcc_snez },
1163     { rv_op_illegal, NULL }
1164 };
1165 
1166 static const rv_comp_data rvcp_addiw[] = {
1167     { rv_op_sext_w, rvcc_sext_w },
1168     { rv_op_illegal, NULL }
1169 };
1170 
1171 static const rv_comp_data rvcp_subw[] = {
1172     { rv_op_negw, rvcc_negw },
1173     { rv_op_illegal, NULL }
1174 };
1175 
1176 static const rv_comp_data rvcp_csrrw[] = {
1177     { rv_op_fscsr, rvcc_fscsr },
1178     { rv_op_fsrm, rvcc_fsrm },
1179     { rv_op_fsflags, rvcc_fsflags },
1180     { rv_op_illegal, NULL }
1181 };
1182 
1183 
1184 static const rv_comp_data rvcp_csrrs[] = {
1185     { rv_op_rdcycle, rvcc_rdcycle },
1186     { rv_op_rdtime, rvcc_rdtime },
1187     { rv_op_rdinstret, rvcc_rdinstret },
1188     { rv_op_rdcycleh, rvcc_rdcycleh },
1189     { rv_op_rdtimeh, rvcc_rdtimeh },
1190     { rv_op_rdinstreth, rvcc_rdinstreth },
1191     { rv_op_frcsr, rvcc_frcsr },
1192     { rv_op_frrm, rvcc_frrm },
1193     { rv_op_frflags, rvcc_frflags },
1194     { rv_op_illegal, NULL }
1195 };
1196 
1197 static const rv_comp_data rvcp_csrrwi[] = {
1198     { rv_op_fsrmi, rvcc_fsrmi },
1199     { rv_op_fsflagsi, rvcc_fsflagsi },
1200     { rv_op_illegal, NULL }
1201 };
1202 
1203 static const rv_comp_data rvcp_fsgnj_s[] = {
1204     { rv_op_fmv_s, rvcc_fmv_s },
1205     { rv_op_illegal, NULL }
1206 };
1207 
1208 static const rv_comp_data rvcp_fsgnjn_s[] = {
1209     { rv_op_fneg_s, rvcc_fneg_s },
1210     { rv_op_illegal, NULL }
1211 };
1212 
1213 static const rv_comp_data rvcp_fsgnjx_s[] = {
1214     { rv_op_fabs_s, rvcc_fabs_s },
1215     { rv_op_illegal, NULL }
1216 };
1217 
1218 static const rv_comp_data rvcp_fsgnj_d[] = {
1219     { rv_op_fmv_d, rvcc_fmv_d },
1220     { rv_op_illegal, NULL }
1221 };
1222 
1223 static const rv_comp_data rvcp_fsgnjn_d[] = {
1224     { rv_op_fneg_d, rvcc_fneg_d },
1225     { rv_op_illegal, NULL }
1226 };
1227 
1228 static const rv_comp_data rvcp_fsgnjx_d[] = {
1229     { rv_op_fabs_d, rvcc_fabs_d },
1230     { rv_op_illegal, NULL }
1231 };
1232 
1233 static const rv_comp_data rvcp_fsgnj_q[] = {
1234     { rv_op_fmv_q, rvcc_fmv_q },
1235     { rv_op_illegal, NULL }
1236 };
1237 
1238 static const rv_comp_data rvcp_fsgnjn_q[] = {
1239     { rv_op_fneg_q, rvcc_fneg_q },
1240     { rv_op_illegal, NULL }
1241 };
1242 
1243 static const rv_comp_data rvcp_fsgnjx_q[] = {
1244     { rv_op_fabs_q, rvcc_fabs_q },
1245     { rv_op_illegal, NULL }
1246 };
1247 
1248 /* instruction metadata */
1249 
1250 const rv_opcode_data rvi_opcode_data[] = {
1251     { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
1252     { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 },
1253     { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 },
1254     { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },
1255     { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 },
1256     { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 },
1257     { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 },
1258     { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 },
1259     { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 },
1260     { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 },
1261     { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 },
1262     { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1263     { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1264     { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1265     { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1266     { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1267     { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1268     { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1269     { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1270     { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 },
1271     { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1272     { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 },
1273     { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 },
1274     { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1275     { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1276     { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1277     { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1278     { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1279     { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1280     { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 },
1281     { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1282     { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 },
1283     { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 },
1284     { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1285     { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1286     { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1287     { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1288     { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1289     { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 },
1290     { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1291     { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1292     { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1293     { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1294     { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 },
1295     { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1296     { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1297     { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1298     { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1299     { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 },
1300     { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1301     { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1302     { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1303     { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1304     { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1305     { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1306     { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1307     { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1308     { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1309     { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1310     { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1311     { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1312     { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1313     { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1314     { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1315     { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1316     { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1317     { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1318     { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1319     { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1320     { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1321     { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1322     { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1323     { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1324     { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1325     { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1326     { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1327     { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1328     { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1329     { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1330     { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1331     { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1332     { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1333     { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1334     { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1335     { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1336     { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1337     { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1338     { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1339     { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1340     { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1341     { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1342     { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1343     { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1344     { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1345     { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1346     { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1347     { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1348     { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1349     { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1350     { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1351     { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1352     { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1353     { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1354     { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1355     { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1356     { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1357     { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1358     { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1359     { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1360     { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1361     { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1362     { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1363     { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1364     { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1365     { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1366     { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1367     { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1368     { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1369     { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1370     { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1371     { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1372     { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1373     { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
1374     { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
1375     { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1376     { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 },
1377     { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 },
1378     { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 },
1379     { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 },
1380     { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1381     { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1382     { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1383     { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1384     { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1385     { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1386     { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1387     { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1388     { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1389     { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1390     { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1391     { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1392     { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 },
1393     { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 },
1394     { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 },
1395     { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1396     { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1397     { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1398     { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1399     { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1400     { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1401     { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1402     { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1403     { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1404     { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1405     { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1406     { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1407     { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1408     { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1409     { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1410     { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1411     { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1412     { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1413     { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1414     { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1415     { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1416     { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1417     { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1418     { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1419     { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1420     { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1421     { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1422     { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 },
1423     { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 },
1424     { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 },
1425     { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1426     { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1427     { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1428     { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1429     { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1430     { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1431     { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1432     { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1433     { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1434     { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1435     { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1436     { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1437     { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1438     { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1439     { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1440     { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1441     { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1442     { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1443     { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1444     { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1445     { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1446     { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1447     { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1448     { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1449     { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1450     { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1451     { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1452     { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1453     { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1454     { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 },
1455     { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 },
1456     { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 },
1457     { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1458     { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1459     { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1460     { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1461     { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1462     { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1463     { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1464     { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1465     { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1466     { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1467     { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1468     { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1469     { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1470     { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1471     { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1472     { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1473     { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1474     { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1475     { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1476     { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1477     { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1478     { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1479       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1480     { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
1481       rv_op_fld, 0 },
1482     { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw,
1483       rv_op_lw },
1484     { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
1485     { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
1486       rv_op_fsd, 0 },
1487     { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw,
1488       rv_op_sw },
1489     { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
1490     { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi,
1491       rv_op_addi },
1492     { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
1493       rv_op_addi, rvcd_imm_nz },
1494     { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
1495     { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
1496       rv_op_addi },
1497     { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1498       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1499     { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui,
1500       rv_op_lui, rvcd_imm_nz },
1501     { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
1502       rv_op_srli, rv_op_srli, rvcd_imm_nz },
1503     { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai,
1504       rv_op_srai, rv_op_srai, rvcd_imm_nz },
1505     { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
1506       rv_op_andi, rv_op_andi },
1507     { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub,
1508       rv_op_sub },
1509     { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor,
1510       rv_op_xor },
1511     { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or,
1512       rv_op_or },
1513     { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and,
1514       rv_op_and },
1515     { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw,
1516       rv_op_subw },
1517     { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw,
1518       rv_op_addw },
1519     { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal,
1520       rv_op_jal },
1521     { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq,
1522       rv_op_beq },
1523     { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne,
1524       rv_op_bne },
1525     { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
1526       rv_op_slli, rv_op_slli, rvcd_imm_nz },
1527     { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
1528       rv_op_fld, rv_op_fld },
1529     { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
1530       rv_op_lw, rv_op_lw },
1531     { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0,
1532       0 },
1533     { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
1534       rv_op_jalr, rv_op_jalr },
1535     { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi,
1536       rv_op_addi },
1537     { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
1538       rv_op_ebreak, rv_op_ebreak },
1539     { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
1540       rv_op_jalr, rv_op_jalr },
1541     { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add,
1542       rv_op_add },
1543     { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
1544       rv_op_fsd, rv_op_fsd },
1545     { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
1546       rv_op_sw, rv_op_sw },
1547     { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0,
1548       0 },
1549     { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
1550       rv_op_ld },
1551     { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
1552       rv_op_sd },
1553     { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw,
1554       rv_op_addiw },
1555     { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
1556       rv_op_ld },
1557     { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
1558       rv_op_sd },
1559     { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1560     { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
1561     { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1562     { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
1563       rv_op_sq },
1564     { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1565     { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1566     { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1567     { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1568     { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1569     { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1570     { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1571     { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1572     { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1573     { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1574     { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1575     { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1576     { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1577     { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1578     { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1579     { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1580     { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1581     { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1582     { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1583     { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1584     { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1585     { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1586     { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1587     { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1588     { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1589     { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1590     { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1591     { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1592     { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1593     { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 },
1594     { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1595     { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 },
1596     { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1597     { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1598     { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1599     { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1600     { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1601     { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1602     { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1603     { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1604     { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1605     { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1606     { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1607     { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1608     { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1609     { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1610     { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1611     { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1612     { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1613     { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1614     { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1615     { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1616     { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1617     { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1618     { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1619     { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1620     { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1621     { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1622     { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1623     { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1624     { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1625     { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1626     { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1627     { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1628     { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1629     { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1630     { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1631     { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1632     { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1633     { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1634     { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1635     { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1636     { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1637     { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1638     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1639     { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1640     { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1641     { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1642     { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1643     { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1644     { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1645     { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1646     { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1647     { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1648     { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1649     { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1650     { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1651     { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1652     { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1653     { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1654     { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1655     { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1656     { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1657     { "aes64ks1i", rv_codec_k_rnum,  rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
1658     { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1659     { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1660     { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1661     { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1662     { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1663     { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1664     { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1665     { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1666     { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1667     { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1668     { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1669     { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1670     { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1671     { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1672     { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1673     { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1674     { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1675     { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1676     { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1677     { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1678     { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1679     { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1680     { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1681     { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1682     { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1683     { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1684     { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1685     { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1686     { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1687     { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1688     { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1689     { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1690     { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1691     { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1692     { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1693     { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1694     { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1695     { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1696     { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1697     { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1698     { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1699     { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1700     { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1701     { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1702     { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1703     { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1704     { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1705     { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1706     { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1707     { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
1708     { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1709     { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1710     { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1711     { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1712     { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1713     { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1714     { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1715     { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1716     { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1717     { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1718     { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1719     { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1720     { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1721     { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1722     { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1723     { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1724     { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1725     { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1726     { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1727     { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1728     { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1729     { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1730     { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1731     { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1732     { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1733     { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1734     { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1735     { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1736     { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1737     { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1738     { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1739     { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1740     { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1741     { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1742     { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1743     { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1744     { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1745     { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1746     { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1747     { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
1748     { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1749     { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1750     { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1751     { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1752     { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1753     { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1754     { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1755     { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1756     { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1757     { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1758     { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1759     { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1760     { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1761     { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1762     { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1763     { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1764     { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1765     { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1766     { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1767     { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1768     { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1769     { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1770     { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1771     { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1772     { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1773     { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
1774     { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1775     { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1776     { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
1777     { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1778     { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1779     { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1780     { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1781     { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1782     { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1783     { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1784     { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1785     { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1786     { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1787     { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1788     { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1789     { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1790     { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1791     { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1792     { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1793     { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1794     { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1795     { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1796     { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1797     { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1798     { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1799     { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1800     { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1801     { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1802     { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1803     { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1804     { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1805     { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1806     { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1807     { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1808     { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1809     { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1810     { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1811     { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1812     { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1813     { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1814     { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1815     { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1816     { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1817     { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1818     { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1819     { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1820     { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1821     { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1822     { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1823     { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1824     { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1825     { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1826     { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1827     { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1828     { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1829     { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1830     { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1831     { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1832     { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1833     { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1834     { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1835     { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1836     { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1837     { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1838     { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1839     { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1840     { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1841     { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1842     { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1843     { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1844     { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1845     { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1846     { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1847     { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1848     { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1849     { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1850     { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1851     { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1852     { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1853     { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1854     { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1855     { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1856     { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1857     { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1858     { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1859     { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1860     { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1861     { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1862     { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1863     { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1864     { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1865     { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1866     { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1867     { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1868     { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1869     { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
1870     { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 },
1871     { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
1872     { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 },
1873     { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
1874     { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
1875     { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
1876     { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1877     { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1878     { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1879     { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1880     { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1881     { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
1882     { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1883     { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1884     { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1885     { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1886     { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1887     { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1888     { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1889     { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1890     { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1891     { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1892     { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1893     { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1894     { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1895     { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1896     { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1897     { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1898     { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1899     { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1900     { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1901     { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1902     { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1903     { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1904     { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1905     { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1906     { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
1907     { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
1908     { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1909     { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1910     { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1911     { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1912     { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1913     { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1914     { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1915     { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1916     { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1917     { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1918     { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1919     { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1920     { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1921     { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1922     { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1923     { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1924     { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1925     { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1926     { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1927     { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1928     { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1929     { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1930     { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1931     { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1932     { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1933     { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1934     { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1935     { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1936     { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1937     { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1938     { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1939     { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1940     { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1941     { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1942     { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1943     { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1944     { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1945     { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1946     { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1947     { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1948     { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1949     { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1950     { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
1951     { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
1952     { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1953     { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1954     { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
1955     { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1956     { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1957     { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1958     { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1959     { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1960     { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1961     { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1962     { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1963     { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1964     { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1965     { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1966     { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1967     { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1968     { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1969     { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1970     { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1971     { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1972     { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1973     { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
1974     { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1975     { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1976     { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
1977     { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1978     { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 },
1979     { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
1980     { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1981     { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1982     { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1983     { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1984     { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1985     { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1986     { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1987     { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1988     { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1989     { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1990     { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1991     { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1992     { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1993     { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1994     { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1995     { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1996     { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1997     { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1998     { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
1999     { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2000     { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2001     { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2002     { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2003     { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2004     { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2005     { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2006     { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2007     { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2008     { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2009     { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2010     { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2011     { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2012     { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2013     { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2014     { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2015     { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2016     { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2017     { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2018     { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2019     { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2020     { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2021     { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2022     { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2023     { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2024     { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2025     { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
2026     { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
2027     { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2028     { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2029     { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2030     { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2031     { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 },
2032     { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 },
2033     { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
2034     { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 },
2035     { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
2036     { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
2037     { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
2038     { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
2039     { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
2040     { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
2041     { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
2042     { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2043     { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2044     { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
2045     { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
2046     { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
2047     { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2048     { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2049     { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2050     { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2051     { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2052     { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2053     { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2054     { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2055     { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2056     { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2057     { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 },
2058     { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 },
2059     { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2060     { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2061     { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2062     { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2063     { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2064     { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2065     { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2066     { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 },
2067     { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2068     { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2069     { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2070     { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2071     { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2072     { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 },
2073     { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
2074     { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 },
2075     { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
2076     { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
2077     { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
2078     { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
2079     { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
2080     { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2081     { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2082     { "fcvt.bf16.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
2083     { "fcvt.s.bf16", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
2084     { "vfncvtbf16.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2085     { "vfwcvtbf16.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2086     { "vfwmaccbf16.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
2087     { "vfwmaccbf16.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
2088     { "flh", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
2089     { "fsh", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
2090     { "fmv.h.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
2091     { "fmv.x.h", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
2092     { "fli.s", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
2093     { "fli.d", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
2094     { "fli.q", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
2095     { "fli.h", rv_codec_fli, rv_fmt_fli, NULL, 0, 0, 0 },
2096     { "fminm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
2097     { "fmaxm.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
2098     { "fminm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
2099     { "fmaxm.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
2100     { "fminm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
2101     { "fmaxm.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
2102     { "fminm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
2103     { "fmaxm.h", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
2104     { "fround.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
2105     { "froundnx.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
2106     { "fround.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
2107     { "froundnx.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
2108     { "fround.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
2109     { "froundnx.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
2110     { "fround.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
2111     { "froundnx.h", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
2112     { "fcvtmod.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
2113     { "fmvh.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
2114     { "fmvp.d.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 },
2115     { "fmvh.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
2116     { "fmvp.q.x", rv_codec_r, rv_fmt_frd_rs1_rs2, NULL, 0, 0, 0 },
2117     { "fleq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
2118     { "fltq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
2119     { "fleq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
2120     { "fltq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
2121     { "fleq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
2122     { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
2123     { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
2124     { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
2125     { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2126     { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2127     { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2128     { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2129     { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2130     { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2131     { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2132     { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2133     { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
2134     { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
2135     { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2136     { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2137     { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
2138     { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2139     { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2140     { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2141     { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
2142     { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2143     { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
2144     { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2145     { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2146     { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2147     { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
2148     { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2149     { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
2150     { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2151     { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
2152     { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2153     { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
2154     { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
2155     { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
2156     { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
2157     { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
2158     { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
2159     { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
2160     { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
2161     { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2162     { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
2163     { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
2164     { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
2165     { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
2166     { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2167     { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2168     { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2169     { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2170     { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2171     { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2172     { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2173     { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2174     { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2175     { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2176     { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2177     { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2178     { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2179     { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2180     { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2181     { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2182     { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2183     { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2184     { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2185     { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2186     { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2187     { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2188     { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2189     { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2190     { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2191     { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2192     { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2193     { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2194     { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2195     { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2196     { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2197     { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2198     { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2199     { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2200     { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2201     { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2202     { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2203     { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2204     { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2205     { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2206     { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2207     { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2208     { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2209     { "c.mop.1",  rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2210     { "c.mop.3",  rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2211     { "c.mop.5",  rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2212     { "c.mop.7",  rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2213     { "c.mop.9",  rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2214     { "c.mop.11", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2215     { "c.mop.13", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2216     { "c.mop.15", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2217     { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2218     { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2219     { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2220     { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2221     { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2222     { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2223     { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2224     { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2225     { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2226     { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2227     { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2228     { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2229     { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2230     { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2231     { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2232     { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2233     { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2234     { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2235     { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2236     { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2237     { "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
2238     { "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
2239 };
2240 
2241 /* CSR names */
2242 
2243 static const char *csr_name(int csrno)
2244 {
2245     switch (csrno) {
2246     case 0x0000: return "ustatus";
2247     case 0x0001: return "fflags";
2248     case 0x0002: return "frm";
2249     case 0x0003: return "fcsr";
2250     case 0x0004: return "uie";
2251     case 0x0005: return "utvec";
2252     case 0x0008: return "vstart";
2253     case 0x0009: return "vxsat";
2254     case 0x000a: return "vxrm";
2255     case 0x000f: return "vcsr";
2256     case 0x0015: return "seed";
2257     case 0x0017: return "jvt";
2258     case 0x0040: return "uscratch";
2259     case 0x0041: return "uepc";
2260     case 0x0042: return "ucause";
2261     case 0x0043: return "utval";
2262     case 0x0044: return "uip";
2263     case 0x0100: return "sstatus";
2264     case 0x0104: return "sie";
2265     case 0x0105: return "stvec";
2266     case 0x0106: return "scounteren";
2267     case 0x0140: return "sscratch";
2268     case 0x0141: return "sepc";
2269     case 0x0142: return "scause";
2270     case 0x0143: return "stval";
2271     case 0x0144: return "sip";
2272     case 0x0180: return "satp";
2273     case 0x0200: return "hstatus";
2274     case 0x0202: return "hedeleg";
2275     case 0x0203: return "hideleg";
2276     case 0x0204: return "hie";
2277     case 0x0205: return "htvec";
2278     case 0x0240: return "hscratch";
2279     case 0x0241: return "hepc";
2280     case 0x0242: return "hcause";
2281     case 0x0243: return "hbadaddr";
2282     case 0x0244: return "hip";
2283     case 0x0300: return "mstatus";
2284     case 0x0301: return "misa";
2285     case 0x0302: return "medeleg";
2286     case 0x0303: return "mideleg";
2287     case 0x0304: return "mie";
2288     case 0x0305: return "mtvec";
2289     case 0x0306: return "mcounteren";
2290     case 0x0320: return "mucounteren";
2291     case 0x0321: return "mscounteren";
2292     case 0x0322: return "mhcounteren";
2293     case 0x0323: return "mhpmevent3";
2294     case 0x0324: return "mhpmevent4";
2295     case 0x0325: return "mhpmevent5";
2296     case 0x0326: return "mhpmevent6";
2297     case 0x0327: return "mhpmevent7";
2298     case 0x0328: return "mhpmevent8";
2299     case 0x0329: return "mhpmevent9";
2300     case 0x032a: return "mhpmevent10";
2301     case 0x032b: return "mhpmevent11";
2302     case 0x032c: return "mhpmevent12";
2303     case 0x032d: return "mhpmevent13";
2304     case 0x032e: return "mhpmevent14";
2305     case 0x032f: return "mhpmevent15";
2306     case 0x0330: return "mhpmevent16";
2307     case 0x0331: return "mhpmevent17";
2308     case 0x0332: return "mhpmevent18";
2309     case 0x0333: return "mhpmevent19";
2310     case 0x0334: return "mhpmevent20";
2311     case 0x0335: return "mhpmevent21";
2312     case 0x0336: return "mhpmevent22";
2313     case 0x0337: return "mhpmevent23";
2314     case 0x0338: return "mhpmevent24";
2315     case 0x0339: return "mhpmevent25";
2316     case 0x033a: return "mhpmevent26";
2317     case 0x033b: return "mhpmevent27";
2318     case 0x033c: return "mhpmevent28";
2319     case 0x033d: return "mhpmevent29";
2320     case 0x033e: return "mhpmevent30";
2321     case 0x033f: return "mhpmevent31";
2322     case 0x0340: return "mscratch";
2323     case 0x0341: return "mepc";
2324     case 0x0342: return "mcause";
2325     case 0x0343: return "mtval";
2326     case 0x0344: return "mip";
2327     case 0x0380: return "mbase";
2328     case 0x0381: return "mbound";
2329     case 0x0382: return "mibase";
2330     case 0x0383: return "mibound";
2331     case 0x0384: return "mdbase";
2332     case 0x0385: return "mdbound";
2333     case 0x03a0: return "pmpcfg0";
2334     case 0x03a1: return "pmpcfg1";
2335     case 0x03a2: return "pmpcfg2";
2336     case 0x03a3: return "pmpcfg3";
2337     case 0x03a4: return "pmpcfg4";
2338     case 0x03a5: return "pmpcfg5";
2339     case 0x03a6: return "pmpcfg6";
2340     case 0x03a7: return "pmpcfg7";
2341     case 0x03a8: return "pmpcfg8";
2342     case 0x03a9: return "pmpcfg9";
2343     case 0x03aa: return "pmpcfg10";
2344     case 0x03ab: return "pmpcfg11";
2345     case 0x03ac: return "pmpcfg12";
2346     case 0x03ad: return "pmpcfg13";
2347     case 0x03ae: return "pmpcfg14";
2348     case 0x03af: return "pmpcfg15";
2349     case 0x03b0: return "pmpaddr0";
2350     case 0x03b1: return "pmpaddr1";
2351     case 0x03b2: return "pmpaddr2";
2352     case 0x03b3: return "pmpaddr3";
2353     case 0x03b4: return "pmpaddr4";
2354     case 0x03b5: return "pmpaddr5";
2355     case 0x03b6: return "pmpaddr6";
2356     case 0x03b7: return "pmpaddr7";
2357     case 0x03b8: return "pmpaddr8";
2358     case 0x03b9: return "pmpaddr9";
2359     case 0x03ba: return "pmpaddr10";
2360     case 0x03bb: return "pmpaddr11";
2361     case 0x03bc: return "pmpaddr12";
2362     case 0x03bd: return "pmpaddr13";
2363     case 0x03be: return "pmpaddr14";
2364     case 0x03bf: return "pmpaddr15";
2365     case 0x03c0: return "pmpaddr16";
2366     case 0x03c1: return "pmpaddr17";
2367     case 0x03c2: return "pmpaddr18";
2368     case 0x03c3: return "pmpaddr19";
2369     case 0x03c4: return "pmpaddr20";
2370     case 0x03c5: return "pmpaddr21";
2371     case 0x03c6: return "pmpaddr22";
2372     case 0x03c7: return "pmpaddr23";
2373     case 0x03c8: return "pmpaddr24";
2374     case 0x03c9: return "pmpaddr25";
2375     case 0x03ca: return "pmpaddr26";
2376     case 0x03cb: return "pmpaddr27";
2377     case 0x03cc: return "pmpaddr28";
2378     case 0x03cd: return "pmpaddr29";
2379     case 0x03ce: return "pmpaddr30";
2380     case 0x03cf: return "pmpaddr31";
2381     case 0x03d0: return "pmpaddr32";
2382     case 0x03d1: return "pmpaddr33";
2383     case 0x03d2: return "pmpaddr34";
2384     case 0x03d3: return "pmpaddr35";
2385     case 0x03d4: return "pmpaddr36";
2386     case 0x03d5: return "pmpaddr37";
2387     case 0x03d6: return "pmpaddr38";
2388     case 0x03d7: return "pmpaddr39";
2389     case 0x03d8: return "pmpaddr40";
2390     case 0x03d9: return "pmpaddr41";
2391     case 0x03da: return "pmpaddr42";
2392     case 0x03db: return "pmpaddr43";
2393     case 0x03dc: return "pmpaddr44";
2394     case 0x03dd: return "pmpaddr45";
2395     case 0x03de: return "pmpaddr46";
2396     case 0x03df: return "pmpaddr47";
2397     case 0x03e0: return "pmpaddr48";
2398     case 0x03e1: return "pmpaddr49";
2399     case 0x03e2: return "pmpaddr50";
2400     case 0x03e3: return "pmpaddr51";
2401     case 0x03e4: return "pmpaddr52";
2402     case 0x03e5: return "pmpaddr53";
2403     case 0x03e6: return "pmpaddr54";
2404     case 0x03e7: return "pmpaddr55";
2405     case 0x03e8: return "pmpaddr56";
2406     case 0x03e9: return "pmpaddr57";
2407     case 0x03ea: return "pmpaddr58";
2408     case 0x03eb: return "pmpaddr59";
2409     case 0x03ec: return "pmpaddr60";
2410     case 0x03ed: return "pmpaddr61";
2411     case 0x03ee: return "pmpaddr62";
2412     case 0x03ef: return "pmpaddr63";
2413     case 0x0780: return "mtohost";
2414     case 0x0781: return "mfromhost";
2415     case 0x0782: return "mreset";
2416     case 0x0783: return "mipi";
2417     case 0x0784: return "miobase";
2418     case 0x07a0: return "tselect";
2419     case 0x07a1: return "tdata1";
2420     case 0x07a2: return "tdata2";
2421     case 0x07a3: return "tdata3";
2422     case 0x07b0: return "dcsr";
2423     case 0x07b1: return "dpc";
2424     case 0x07b2: return "dscratch";
2425     case 0x0b00: return "mcycle";
2426     case 0x0b01: return "mtime";
2427     case 0x0b02: return "minstret";
2428     case 0x0b03: return "mhpmcounter3";
2429     case 0x0b04: return "mhpmcounter4";
2430     case 0x0b05: return "mhpmcounter5";
2431     case 0x0b06: return "mhpmcounter6";
2432     case 0x0b07: return "mhpmcounter7";
2433     case 0x0b08: return "mhpmcounter8";
2434     case 0x0b09: return "mhpmcounter9";
2435     case 0x0b0a: return "mhpmcounter10";
2436     case 0x0b0b: return "mhpmcounter11";
2437     case 0x0b0c: return "mhpmcounter12";
2438     case 0x0b0d: return "mhpmcounter13";
2439     case 0x0b0e: return "mhpmcounter14";
2440     case 0x0b0f: return "mhpmcounter15";
2441     case 0x0b10: return "mhpmcounter16";
2442     case 0x0b11: return "mhpmcounter17";
2443     case 0x0b12: return "mhpmcounter18";
2444     case 0x0b13: return "mhpmcounter19";
2445     case 0x0b14: return "mhpmcounter20";
2446     case 0x0b15: return "mhpmcounter21";
2447     case 0x0b16: return "mhpmcounter22";
2448     case 0x0b17: return "mhpmcounter23";
2449     case 0x0b18: return "mhpmcounter24";
2450     case 0x0b19: return "mhpmcounter25";
2451     case 0x0b1a: return "mhpmcounter26";
2452     case 0x0b1b: return "mhpmcounter27";
2453     case 0x0b1c: return "mhpmcounter28";
2454     case 0x0b1d: return "mhpmcounter29";
2455     case 0x0b1e: return "mhpmcounter30";
2456     case 0x0b1f: return "mhpmcounter31";
2457     case 0x0b80: return "mcycleh";
2458     case 0x0b81: return "mtimeh";
2459     case 0x0b82: return "minstreth";
2460     case 0x0b83: return "mhpmcounter3h";
2461     case 0x0b84: return "mhpmcounter4h";
2462     case 0x0b85: return "mhpmcounter5h";
2463     case 0x0b86: return "mhpmcounter6h";
2464     case 0x0b87: return "mhpmcounter7h";
2465     case 0x0b88: return "mhpmcounter8h";
2466     case 0x0b89: return "mhpmcounter9h";
2467     case 0x0b8a: return "mhpmcounter10h";
2468     case 0x0b8b: return "mhpmcounter11h";
2469     case 0x0b8c: return "mhpmcounter12h";
2470     case 0x0b8d: return "mhpmcounter13h";
2471     case 0x0b8e: return "mhpmcounter14h";
2472     case 0x0b8f: return "mhpmcounter15h";
2473     case 0x0b90: return "mhpmcounter16h";
2474     case 0x0b91: return "mhpmcounter17h";
2475     case 0x0b92: return "mhpmcounter18h";
2476     case 0x0b93: return "mhpmcounter19h";
2477     case 0x0b94: return "mhpmcounter20h";
2478     case 0x0b95: return "mhpmcounter21h";
2479     case 0x0b96: return "mhpmcounter22h";
2480     case 0x0b97: return "mhpmcounter23h";
2481     case 0x0b98: return "mhpmcounter24h";
2482     case 0x0b99: return "mhpmcounter25h";
2483     case 0x0b9a: return "mhpmcounter26h";
2484     case 0x0b9b: return "mhpmcounter27h";
2485     case 0x0b9c: return "mhpmcounter28h";
2486     case 0x0b9d: return "mhpmcounter29h";
2487     case 0x0b9e: return "mhpmcounter30h";
2488     case 0x0b9f: return "mhpmcounter31h";
2489     case 0x0c00: return "cycle";
2490     case 0x0c01: return "time";
2491     case 0x0c02: return "instret";
2492     case 0x0c20: return "vl";
2493     case 0x0c21: return "vtype";
2494     case 0x0c22: return "vlenb";
2495     case 0x0c80: return "cycleh";
2496     case 0x0c81: return "timeh";
2497     case 0x0c82: return "instreth";
2498     case 0x0d00: return "scycle";
2499     case 0x0d01: return "stime";
2500     case 0x0d02: return "sinstret";
2501     case 0x0d80: return "scycleh";
2502     case 0x0d81: return "stimeh";
2503     case 0x0d82: return "sinstreth";
2504     case 0x0e00: return "hcycle";
2505     case 0x0e01: return "htime";
2506     case 0x0e02: return "hinstret";
2507     case 0x0e80: return "hcycleh";
2508     case 0x0e81: return "htimeh";
2509     case 0x0e82: return "hinstreth";
2510     case 0x0f11: return "mvendorid";
2511     case 0x0f12: return "marchid";
2512     case 0x0f13: return "mimpid";
2513     case 0x0f14: return "mhartid";
2514     default: return NULL;
2515     }
2516 }
2517 
2518 /* decode opcode */
2519 
2520 static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
2521 {
2522     rv_inst inst = dec->inst;
2523     rv_opcode op = rv_op_illegal;
2524     switch ((inst >> 0) & 0b11) {
2525     case 0:
2526         switch ((inst >> 13) & 0b111) {
2527         case 0: op = rv_op_c_addi4spn; break;
2528         case 1:
2529             if (isa == rv128) {
2530                 op = rv_op_c_lq;
2531             } else {
2532                 op = rv_op_c_fld;
2533             }
2534             break;
2535         case 2: op = rv_op_c_lw; break;
2536         case 3:
2537             if (isa == rv32) {
2538                 op = rv_op_c_flw;
2539             } else {
2540                 op = rv_op_c_ld;
2541             }
2542             break;
2543         case 4:
2544             switch ((inst >> 10) & 0b111) {
2545             case 0: op = rv_op_c_lbu; break;
2546             case 1:
2547                 if (((inst >> 6) & 1) == 0) {
2548                     op = rv_op_c_lhu;
2549                 } else {
2550                     op = rv_op_c_lh;
2551                 }
2552                 break;
2553             case 2: op = rv_op_c_sb; break;
2554             case 3:
2555                 if (((inst >> 6) & 1) == 0) {
2556                     op = rv_op_c_sh;
2557                 }
2558                 break;
2559             }
2560             break;
2561         case 5:
2562             if (isa == rv128) {
2563                 op = rv_op_c_sq;
2564             } else {
2565                 op = rv_op_c_fsd;
2566             }
2567             break;
2568         case 6: op = rv_op_c_sw; break;
2569         case 7:
2570             if (isa == rv32) {
2571                 op = rv_op_c_fsw;
2572             } else {
2573                 op = rv_op_c_sd;
2574             }
2575             break;
2576         }
2577         break;
2578     case 1:
2579         switch ((inst >> 13) & 0b111) {
2580         case 0:
2581             switch ((inst >> 2) & 0b11111111111) {
2582             case 0: op = rv_op_c_nop; break;
2583             default: op = rv_op_c_addi; break;
2584             }
2585             break;
2586         case 1:
2587             if (isa == rv32) {
2588                 op = rv_op_c_jal;
2589             } else {
2590                 op = rv_op_c_addiw;
2591             }
2592             break;
2593         case 2: op = rv_op_c_li; break;
2594         case 3:
2595             if (dec->cfg->ext_zcmop) {
2596                 if ((((inst >> 2) & 0b111111) == 0b100000) &&
2597                     (((inst >> 11) & 0b11) == 0b0)) {
2598                     op = rv_c_mop_1 + ((inst >> 8) & 0b111);
2599                     break;
2600                 }
2601             }
2602             switch ((inst >> 7) & 0b11111) {
2603             case 2: op = rv_op_c_addi16sp; break;
2604             default: op = rv_op_c_lui; break;
2605             }
2606             break;
2607         case 4:
2608             switch ((inst >> 10) & 0b11) {
2609             case 0:
2610                 op = rv_op_c_srli;
2611                 break;
2612             case 1:
2613                 op = rv_op_c_srai;
2614                 break;
2615             case 2: op = rv_op_c_andi; break;
2616             case 3:
2617                 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) {
2618                 case 0: op = rv_op_c_sub; break;
2619                 case 1: op = rv_op_c_xor; break;
2620                 case 2: op = rv_op_c_or; break;
2621                 case 3: op = rv_op_c_and; break;
2622                 case 4: op = rv_op_c_subw; break;
2623                 case 5: op = rv_op_c_addw; break;
2624                 case 6: op = rv_op_c_mul; break;
2625                 case 7:
2626                     switch ((inst >> 2) & 0b111) {
2627                     case 0: op = rv_op_c_zext_b; break;
2628                     case 1: op = rv_op_c_sext_b; break;
2629                     case 2: op = rv_op_c_zext_h; break;
2630                     case 3: op = rv_op_c_sext_h; break;
2631                     case 4: op = rv_op_c_zext_w; break;
2632                     case 5: op = rv_op_c_not; break;
2633                     }
2634                     break;
2635                 }
2636                 break;
2637             }
2638             break;
2639         case 5: op = rv_op_c_j; break;
2640         case 6: op = rv_op_c_beqz; break;
2641         case 7: op = rv_op_c_bnez; break;
2642         }
2643         break;
2644     case 2:
2645         switch ((inst >> 13) & 0b111) {
2646         case 0:
2647             op = rv_op_c_slli;
2648             break;
2649         case 1:
2650             if (isa == rv128) {
2651                 op = rv_op_c_lqsp;
2652             } else {
2653                 op = rv_op_c_fldsp;
2654             }
2655             break;
2656         case 2: op = rv_op_c_lwsp; break;
2657         case 3:
2658             if (isa == rv32) {
2659                 op = rv_op_c_flwsp;
2660             } else {
2661                 op = rv_op_c_ldsp;
2662             }
2663             break;
2664         case 4:
2665             switch ((inst >> 12) & 0b1) {
2666             case 0:
2667                 switch ((inst >> 2) & 0b11111) {
2668                 case 0: op = rv_op_c_jr; break;
2669                 default: op = rv_op_c_mv; break;
2670                 }
2671                 break;
2672             case 1:
2673                 switch ((inst >> 2) & 0b11111) {
2674                 case 0:
2675                     switch ((inst >> 7) & 0b11111) {
2676                     case 0: op = rv_op_c_ebreak; break;
2677                     default: op = rv_op_c_jalr; break;
2678                     }
2679                     break;
2680                 default: op = rv_op_c_add; break;
2681                 }
2682                 break;
2683             }
2684             break;
2685         case 5:
2686             if (isa == rv128) {
2687                 op = rv_op_c_sqsp;
2688             } else {
2689                 op = rv_op_c_fsdsp;
2690                 if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
2691                     switch ((inst >> 8) & 0b01111) {
2692                     case 8:
2693                         if (((inst >> 4) & 0b01111) >= 4) {
2694                             op = rv_op_cm_push;
2695                         }
2696                         break;
2697                     case 10:
2698                         if (((inst >> 4) & 0b01111) >= 4) {
2699                             op = rv_op_cm_pop;
2700                         }
2701                         break;
2702                     case 12:
2703                         if (((inst >> 4) & 0b01111) >= 4) {
2704                             op = rv_op_cm_popretz;
2705                         }
2706                         break;
2707                     case 14:
2708                         if (((inst >> 4) & 0b01111) >= 4) {
2709                             op = rv_op_cm_popret;
2710                         }
2711                         break;
2712                     }
2713                 } else {
2714                     switch ((inst >> 10) & 0b011) {
2715                     case 0:
2716                         if (!dec->cfg->ext_zcmt) {
2717                             break;
2718                         }
2719                         if (((inst >> 2) & 0xFF) >= 32) {
2720                             op = rv_op_cm_jalt;
2721                         } else {
2722                             op = rv_op_cm_jt;
2723                         }
2724                         break;
2725                     case 3:
2726                         if (!dec->cfg->ext_zcmp) {
2727                             break;
2728                         }
2729                         switch ((inst >> 5) & 0b011) {
2730                         case 1: op = rv_op_cm_mvsa01; break;
2731                         case 3: op = rv_op_cm_mva01s; break;
2732                         }
2733                         break;
2734                     }
2735                 }
2736             }
2737             break;
2738         case 6: op = rv_op_c_swsp; break;
2739         case 7:
2740             if (isa == rv32) {
2741                 op = rv_op_c_fswsp;
2742             } else {
2743                 op = rv_op_c_sdsp;
2744             }
2745             break;
2746         }
2747         break;
2748     case 3:
2749         switch ((inst >> 2) & 0b11111) {
2750         case 0:
2751             switch ((inst >> 12) & 0b111) {
2752             case 0: op = rv_op_lb; break;
2753             case 1: op = rv_op_lh; break;
2754             case 2: op = rv_op_lw; break;
2755             case 3: op = rv_op_ld; break;
2756             case 4: op = rv_op_lbu; break;
2757             case 5: op = rv_op_lhu; break;
2758             case 6: op = rv_op_lwu; break;
2759             case 7: op = rv_op_ldu; break;
2760             }
2761             break;
2762         case 1:
2763             switch ((inst >> 12) & 0b111) {
2764             case 0:
2765                 switch ((inst >> 20) & 0b111111111111) {
2766                 case 40: op = rv_op_vl1re8_v; break;
2767                 case 552: op = rv_op_vl2re8_v; break;
2768                 case 1576: op = rv_op_vl4re8_v; break;
2769                 case 3624: op = rv_op_vl8re8_v; break;
2770                 }
2771                 switch ((inst >> 26) & 0b111) {
2772                 case 0:
2773                     switch ((inst >> 20) & 0b11111) {
2774                     case 0: op = rv_op_vle8_v; break;
2775                     case 11: op = rv_op_vlm_v; break;
2776                     case 16: op = rv_op_vle8ff_v; break;
2777                     }
2778                     break;
2779                 case 1: op = rv_op_vluxei8_v; break;
2780                 case 2: op = rv_op_vlse8_v; break;
2781                 case 3: op = rv_op_vloxei8_v; break;
2782                 }
2783                 break;
2784             case 1: op = rv_op_flh; break;
2785             case 2: op = rv_op_flw; break;
2786             case 3: op = rv_op_fld; break;
2787             case 4: op = rv_op_flq; break;
2788             case 5:
2789                 switch ((inst >> 20) & 0b111111111111) {
2790                 case 40: op = rv_op_vl1re16_v; break;
2791                 case 552: op = rv_op_vl2re16_v; break;
2792                 case 1576: op = rv_op_vl4re16_v; break;
2793                 case 3624: op = rv_op_vl8re16_v; break;
2794                 }
2795                 switch ((inst >> 26) & 0b111) {
2796                 case 0:
2797                     switch ((inst >> 20) & 0b11111) {
2798                     case 0: op = rv_op_vle16_v; break;
2799                     case 16: op = rv_op_vle16ff_v; break;
2800                     }
2801                     break;
2802                 case 1: op = rv_op_vluxei16_v; break;
2803                 case 2: op = rv_op_vlse16_v; break;
2804                 case 3: op = rv_op_vloxei16_v; break;
2805                 }
2806                 break;
2807             case 6:
2808                 switch ((inst >> 20) & 0b111111111111) {
2809                 case 40: op = rv_op_vl1re32_v; break;
2810                 case 552: op = rv_op_vl2re32_v; break;
2811                 case 1576: op = rv_op_vl4re32_v; break;
2812                 case 3624: op = rv_op_vl8re32_v; break;
2813                 }
2814                 switch ((inst >> 26) & 0b111) {
2815                 case 0:
2816                     switch ((inst >> 20) & 0b11111) {
2817                     case 0: op = rv_op_vle32_v; break;
2818                     case 16: op = rv_op_vle32ff_v; break;
2819                     }
2820                     break;
2821                 case 1: op = rv_op_vluxei32_v; break;
2822                 case 2: op = rv_op_vlse32_v; break;
2823                 case 3: op = rv_op_vloxei32_v; break;
2824                 }
2825                 break;
2826             case 7:
2827                 switch ((inst >> 20) & 0b111111111111) {
2828                 case 40: op = rv_op_vl1re64_v; break;
2829                 case 552: op = rv_op_vl2re64_v; break;
2830                 case 1576: op = rv_op_vl4re64_v; break;
2831                 case 3624: op = rv_op_vl8re64_v; break;
2832                 }
2833                 switch ((inst >> 26) & 0b111) {
2834                 case 0:
2835                     switch ((inst >> 20) & 0b11111) {
2836                     case 0: op = rv_op_vle64_v; break;
2837                     case 16: op = rv_op_vle64ff_v; break;
2838                     }
2839                     break;
2840                 case 1: op = rv_op_vluxei64_v; break;
2841                 case 2: op = rv_op_vlse64_v; break;
2842                 case 3: op = rv_op_vloxei64_v; break;
2843                 }
2844                 break;
2845             }
2846             break;
2847         case 3:
2848             switch ((inst >> 12) & 0b111) {
2849             case 0: op = rv_op_fence; break;
2850             case 1: op = rv_op_fence_i; break;
2851             case 2: op = rv_op_lq; break;
2852             }
2853             break;
2854         case 4:
2855             switch ((inst >> 12) & 0b111) {
2856             case 0: op = rv_op_addi; break;
2857             case 1:
2858                 switch ((inst >> 27) & 0b11111) {
2859                 case 0b00000: op = rv_op_slli; break;
2860                 case 0b00001:
2861                     switch ((inst >> 20) & 0b1111111) {
2862                     case 0b0001111: op = rv_op_zip; break;
2863                     }
2864                     break;
2865                 case 0b00010:
2866                     switch ((inst >> 20) & 0b1111111) {
2867                     case 0b0000000: op = rv_op_sha256sum0; break;
2868                     case 0b0000001: op = rv_op_sha256sum1; break;
2869                     case 0b0000010: op = rv_op_sha256sig0; break;
2870                     case 0b0000011: op = rv_op_sha256sig1; break;
2871                     case 0b0000100: op = rv_op_sha512sum0; break;
2872                     case 0b0000101: op = rv_op_sha512sum1; break;
2873                     case 0b0000110: op = rv_op_sha512sig0; break;
2874                     case 0b0000111: op = rv_op_sha512sig1; break;
2875                     case 0b0001000: op = rv_op_sm3p0; break;
2876                     case 0b0001001: op = rv_op_sm3p1; break;
2877                     }
2878                     break;
2879                 case 0b00101: op = rv_op_bseti; break;
2880                 case 0b00110:
2881                     switch ((inst >> 20) & 0b1111111) {
2882                     case 0b0000000: op = rv_op_aes64im; break;
2883                     default:
2884                         if (((inst >> 24) & 0b0111) == 0b001) {
2885                             op = rv_op_aes64ks1i;
2886                         }
2887                         break;
2888                      }
2889                      break;
2890                 case 0b01001: op = rv_op_bclri; break;
2891                 case 0b01101: op = rv_op_binvi; break;
2892                 case 0b01100:
2893                     switch ((inst >> 20) & 0b1111111) {
2894                     case 0b0000000: op = rv_op_clz; break;
2895                     case 0b0000001: op = rv_op_ctz; break;
2896                     case 0b0000010: op = rv_op_cpop; break;
2897                       /* 0b0000011 */
2898                     case 0b0000100: op = rv_op_sext_b; break;
2899                     case 0b0000101: op = rv_op_sext_h; break;
2900                     }
2901                     break;
2902                 }
2903                 break;
2904             case 2: op = rv_op_slti; break;
2905             case 3: op = rv_op_sltiu; break;
2906             case 4: op = rv_op_xori; break;
2907             case 5:
2908                 switch ((inst >> 27) & 0b11111) {
2909                 case 0b00000: op = rv_op_srli; break;
2910                 case 0b00001:
2911                     switch ((inst >> 20) & 0b1111111) {
2912                     case 0b0001111: op = rv_op_unzip; break;
2913                     }
2914                     break;
2915                 case 0b00101: op = rv_op_orc_b; break;
2916                 case 0b01000: op = rv_op_srai; break;
2917                 case 0b01001: op = rv_op_bexti; break;
2918                 case 0b01100: op = rv_op_rori; break;
2919                 case 0b01101:
2920                     switch ((inst >> 20) & 0b1111111) {
2921                     case 0b0011000: op = rv_op_rev8; break;
2922                     case 0b0111000: op = rv_op_rev8; break;
2923                     case 0b0000111: op = rv_op_brev8; break;
2924                     }
2925                     break;
2926                 }
2927                 break;
2928             case 6: op = rv_op_ori; break;
2929             case 7: op = rv_op_andi; break;
2930             }
2931             break;
2932         case 5: op = rv_op_auipc; break;
2933         case 6:
2934             switch ((inst >> 12) & 0b111) {
2935             case 0: op = rv_op_addiw; break;
2936             case 1:
2937                 switch ((inst >> 26) & 0b111111) {
2938                 case 0: op = rv_op_slliw; break;
2939                 case 2: op = rv_op_slli_uw; break;
2940                 case 24:
2941                     switch ((inst >> 20) & 0b11111) {
2942                     case 0b00000: op = rv_op_clzw; break;
2943                     case 0b00001: op = rv_op_ctzw; break;
2944                     case 0b00010: op = rv_op_cpopw; break;
2945                     }
2946                     break;
2947                 }
2948                 break;
2949             case 5:
2950                 switch ((inst >> 25) & 0b1111111) {
2951                 case 0: op = rv_op_srliw; break;
2952                 case 32: op = rv_op_sraiw; break;
2953                 case 48: op = rv_op_roriw; break;
2954                 }
2955                 break;
2956             }
2957             break;
2958         case 8:
2959             switch ((inst >> 12) & 0b111) {
2960             case 0: op = rv_op_sb; break;
2961             case 1: op = rv_op_sh; break;
2962             case 2: op = rv_op_sw; break;
2963             case 3: op = rv_op_sd; break;
2964             case 4: op = rv_op_sq; break;
2965             }
2966             break;
2967         case 9:
2968             switch ((inst >> 12) & 0b111) {
2969             case 0:
2970                 switch ((inst >> 20) & 0b111111111111) {
2971                 case 40: op = rv_op_vs1r_v; break;
2972                 case 552: op = rv_op_vs2r_v; break;
2973                 case 1576: op = rv_op_vs4r_v; break;
2974                 case 3624: op = rv_op_vs8r_v; break;
2975                 }
2976                 switch ((inst >> 26) & 0b111) {
2977                 case 0:
2978                     switch ((inst >> 20) & 0b11111) {
2979                     case 0: op = rv_op_vse8_v; break;
2980                     case 11: op = rv_op_vsm_v; break;
2981                     }
2982                     break;
2983                 case 1: op = rv_op_vsuxei8_v; break;
2984                 case 2: op = rv_op_vsse8_v; break;
2985                 case 3: op = rv_op_vsoxei8_v; break;
2986                 }
2987                 break;
2988             case 1: op = rv_op_fsh; break;
2989             case 2: op = rv_op_fsw; break;
2990             case 3: op = rv_op_fsd; break;
2991             case 4: op = rv_op_fsq; break;
2992             case 5:
2993                 switch ((inst >> 26) & 0b111) {
2994                 case 0:
2995                     switch ((inst >> 20) & 0b11111) {
2996                     case 0: op = rv_op_vse16_v; break;
2997                     }
2998                     break;
2999                 case 1: op = rv_op_vsuxei16_v; break;
3000                 case 2: op = rv_op_vsse16_v; break;
3001                 case 3: op = rv_op_vsoxei16_v; break;
3002                 }
3003                 break;
3004             case 6:
3005                 switch ((inst >> 26) & 0b111) {
3006                 case 0:
3007                     switch ((inst >> 20) & 0b11111) {
3008                     case 0: op = rv_op_vse32_v; break;
3009                     }
3010                     break;
3011                 case 1: op = rv_op_vsuxei32_v; break;
3012                 case 2: op = rv_op_vsse32_v; break;
3013                 case 3: op = rv_op_vsoxei32_v; break;
3014                 }
3015                 break;
3016             case 7:
3017                 switch ((inst >> 26) & 0b111) {
3018                 case 0:
3019                     switch ((inst >> 20) & 0b11111) {
3020                     case 0: op = rv_op_vse64_v; break;
3021                     }
3022                     break;
3023                 case 1: op = rv_op_vsuxei64_v; break;
3024                 case 2: op = rv_op_vsse64_v; break;
3025                 case 3: op = rv_op_vsoxei64_v; break;
3026                 }
3027                 break;
3028             }
3029             break;
3030         case 11:
3031             switch (((inst >> 24) & 0b11111000) |
3032                     ((inst >> 12) & 0b00000111)) {
3033             case 0: op = rv_op_amoadd_b; break;
3034             case 1: op = rv_op_amoadd_h; break;
3035             case 2: op = rv_op_amoadd_w; break;
3036             case 3: op = rv_op_amoadd_d; break;
3037             case 4: op = rv_op_amoadd_q; break;
3038             case 8: op = rv_op_amoswap_b; break;
3039             case 9: op = rv_op_amoswap_h; break;
3040             case 10: op = rv_op_amoswap_w; break;
3041             case 11: op = rv_op_amoswap_d; break;
3042             case 12: op = rv_op_amoswap_q; break;
3043             case 18:
3044                 switch ((inst >> 20) & 0b11111) {
3045                 case 0: op = rv_op_lr_w; break;
3046                 }
3047                 break;
3048             case 19:
3049                 switch ((inst >> 20) & 0b11111) {
3050                 case 0: op = rv_op_lr_d; break;
3051                 }
3052                 break;
3053             case 20:
3054                 switch ((inst >> 20) & 0b11111) {
3055                 case 0: op = rv_op_lr_q; break;
3056                 }
3057                 break;
3058             case 26: op = rv_op_sc_w; break;
3059             case 27: op = rv_op_sc_d; break;
3060             case 28: op = rv_op_sc_q; break;
3061             case 32: op = rv_op_amoxor_b; break;
3062             case 33: op = rv_op_amoxor_h; break;
3063             case 34: op = rv_op_amoxor_w; break;
3064             case 35: op = rv_op_amoxor_d; break;
3065             case 36: op = rv_op_amoxor_q; break;
3066             case 40: op = rv_op_amocas_b; break;
3067             case 41: op = rv_op_amocas_h; break;
3068             case 42: op = rv_op_amocas_w; break;
3069             case 43: op = rv_op_amocas_d; break;
3070             case 44: op = rv_op_amocas_q; break;
3071             case 64: op = rv_op_amoor_b; break;
3072             case 65: op = rv_op_amoor_h; break;
3073             case 66: op = rv_op_amoor_w; break;
3074             case 67: op = rv_op_amoor_d; break;
3075             case 68: op = rv_op_amoor_q; break;
3076             case 96: op = rv_op_amoand_b; break;
3077             case 97: op = rv_op_amoand_h; break;
3078             case 98: op = rv_op_amoand_w; break;
3079             case 99: op = rv_op_amoand_d; break;
3080             case 100: op = rv_op_amoand_q; break;
3081             case 128: op = rv_op_amomin_b; break;
3082             case 129: op = rv_op_amomin_h; break;
3083             case 130: op = rv_op_amomin_w; break;
3084             case 131: op = rv_op_amomin_d; break;
3085             case 132: op = rv_op_amomin_q; break;
3086             case 160: op = rv_op_amomax_b; break;
3087             case 161: op = rv_op_amomax_h; break;
3088             case 162: op = rv_op_amomax_w; break;
3089             case 163: op = rv_op_amomax_d; break;
3090             case 164: op = rv_op_amomax_q; break;
3091             case 192: op = rv_op_amominu_b; break;
3092             case 193: op = rv_op_amominu_h; break;
3093             case 194: op = rv_op_amominu_w; break;
3094             case 195: op = rv_op_amominu_d; break;
3095             case 196: op = rv_op_amominu_q; break;
3096             case 224: op = rv_op_amomaxu_b; break;
3097             case 225: op = rv_op_amomaxu_h; break;
3098             case 226: op = rv_op_amomaxu_w; break;
3099             case 227: op = rv_op_amomaxu_d; break;
3100             case 228: op = rv_op_amomaxu_q; break;
3101             }
3102             break;
3103         case 12:
3104             switch (((inst >> 22) & 0b1111111000) |
3105                     ((inst >> 12) & 0b0000000111)) {
3106             case 0: op = rv_op_add; break;
3107             case 1: op = rv_op_sll; break;
3108             case 2: op = rv_op_slt; break;
3109             case 3: op = rv_op_sltu; break;
3110             case 4: op = rv_op_xor; break;
3111             case 5: op = rv_op_srl; break;
3112             case 6: op = rv_op_or; break;
3113             case 7: op = rv_op_and; break;
3114             case 8: op = rv_op_mul; break;
3115             case 9: op = rv_op_mulh; break;
3116             case 10: op = rv_op_mulhsu; break;
3117             case 11: op = rv_op_mulhu; break;
3118             case 12: op = rv_op_div; break;
3119             case 13: op = rv_op_divu; break;
3120             case 14: op = rv_op_rem; break;
3121             case 15: op = rv_op_remu; break;
3122             case 36:
3123                 switch ((inst >> 20) & 0b11111) {
3124                 case 0: op = rv_op_zext_h; break;
3125                 default: op = rv_op_pack; break;
3126                 }
3127                 break;
3128             case 39: op = rv_op_packh; break;
3129 
3130             case 41: op = rv_op_clmul; break;
3131             case 42: op = rv_op_clmulr; break;
3132             case 43: op = rv_op_clmulh; break;
3133             case 44: op = rv_op_min; break;
3134             case 45: op = rv_op_minu; break;
3135             case 46: op = rv_op_max; break;
3136             case 47: op = rv_op_maxu; break;
3137             case 075: op = rv_op_czero_eqz; break;
3138             case 077: op = rv_op_czero_nez; break;
3139             case 130: op = rv_op_sh1add; break;
3140             case 132: op = rv_op_sh2add; break;
3141             case 134: op = rv_op_sh3add; break;
3142             case 161: op = rv_op_bset; break;
3143             case 162: op = rv_op_xperm4; break;
3144             case 164: op = rv_op_xperm8; break;
3145             case 200: op = rv_op_aes64es; break;
3146             case 216: op = rv_op_aes64esm; break;
3147             case 232: op = rv_op_aes64ds; break;
3148             case 248: op = rv_op_aes64dsm; break;
3149             case 256: op = rv_op_sub; break;
3150             case 260: op = rv_op_xnor; break;
3151             case 261: op = rv_op_sra; break;
3152             case 262: op = rv_op_orn; break;
3153             case 263: op = rv_op_andn; break;
3154             case 289: op = rv_op_bclr; break;
3155             case 293: op = rv_op_bext; break;
3156             case 320: op = rv_op_sha512sum0r; break;
3157             case 328: op = rv_op_sha512sum1r; break;
3158             case 336: op = rv_op_sha512sig0l; break;
3159             case 344: op = rv_op_sha512sig1l; break;
3160             case 368: op = rv_op_sha512sig0h; break;
3161             case 376: op = rv_op_sha512sig1h; break;
3162             case 385: op = rv_op_rol; break;
3163             case 389: op = rv_op_ror; break;
3164             case 417: op = rv_op_binv; break;
3165             case 504: op = rv_op_aes64ks2; break;
3166             }
3167             switch ((inst >> 25) & 0b0011111) {
3168             case 17: op = rv_op_aes32esi; break;
3169             case 19: op = rv_op_aes32esmi; break;
3170             case 21: op = rv_op_aes32dsi; break;
3171             case 23: op = rv_op_aes32dsmi; break;
3172             case 24: op = rv_op_sm4ed; break;
3173             case 26: op = rv_op_sm4ks; break;
3174             }
3175             break;
3176         case 13: op = rv_op_lui; break;
3177         case 14:
3178             switch (((inst >> 22) & 0b1111111000) |
3179                     ((inst >> 12) & 0b0000000111)) {
3180             case 0: op = rv_op_addw; break;
3181             case 1: op = rv_op_sllw; break;
3182             case 5: op = rv_op_srlw; break;
3183             case 8: op = rv_op_mulw; break;
3184             case 12: op = rv_op_divw; break;
3185             case 13: op = rv_op_divuw; break;
3186             case 14: op = rv_op_remw; break;
3187             case 15: op = rv_op_remuw; break;
3188             case 32: op = rv_op_add_uw; break;
3189             case 36:
3190                 switch ((inst >> 20) & 0b11111) {
3191                 case 0: op = rv_op_zext_h; break;
3192                 default: op = rv_op_packw; break;
3193                 }
3194                 break;
3195             case 130: op = rv_op_sh1add_uw; break;
3196             case 132: op = rv_op_sh2add_uw; break;
3197             case 134: op = rv_op_sh3add_uw; break;
3198             case 256: op = rv_op_subw; break;
3199             case 261: op = rv_op_sraw; break;
3200             case 385: op = rv_op_rolw; break;
3201             case 389: op = rv_op_rorw; break;
3202             }
3203             break;
3204         case 16:
3205             switch ((inst >> 25) & 0b11) {
3206             case 0: op = rv_op_fmadd_s; break;
3207             case 1: op = rv_op_fmadd_d; break;
3208             case 3: op = rv_op_fmadd_q; break;
3209             }
3210             break;
3211         case 17:
3212             switch ((inst >> 25) & 0b11) {
3213             case 0: op = rv_op_fmsub_s; break;
3214             case 1: op = rv_op_fmsub_d; break;
3215             case 3: op = rv_op_fmsub_q; break;
3216             }
3217             break;
3218         case 18:
3219             switch ((inst >> 25) & 0b11) {
3220             case 0: op = rv_op_fnmsub_s; break;
3221             case 1: op = rv_op_fnmsub_d; break;
3222             case 3: op = rv_op_fnmsub_q; break;
3223             }
3224             break;
3225         case 19:
3226             switch ((inst >> 25) & 0b11) {
3227             case 0: op = rv_op_fnmadd_s; break;
3228             case 1: op = rv_op_fnmadd_d; break;
3229             case 3: op = rv_op_fnmadd_q; break;
3230             }
3231             break;
3232         case 20:
3233             switch ((inst >> 25) & 0b1111111) {
3234             case 0: op = rv_op_fadd_s; break;
3235             case 1: op = rv_op_fadd_d; break;
3236             case 3: op = rv_op_fadd_q; break;
3237             case 4: op = rv_op_fsub_s; break;
3238             case 5: op = rv_op_fsub_d; break;
3239             case 7: op = rv_op_fsub_q; break;
3240             case 8: op = rv_op_fmul_s; break;
3241             case 9: op = rv_op_fmul_d; break;
3242             case 11: op = rv_op_fmul_q; break;
3243             case 12: op = rv_op_fdiv_s; break;
3244             case 13: op = rv_op_fdiv_d; break;
3245             case 15: op = rv_op_fdiv_q; break;
3246             case 16:
3247                 switch ((inst >> 12) & 0b111) {
3248                 case 0: op = rv_op_fsgnj_s; break;
3249                 case 1: op = rv_op_fsgnjn_s; break;
3250                 case 2: op = rv_op_fsgnjx_s; break;
3251                 }
3252                 break;
3253             case 17:
3254                 switch ((inst >> 12) & 0b111) {
3255                 case 0: op = rv_op_fsgnj_d; break;
3256                 case 1: op = rv_op_fsgnjn_d; break;
3257                 case 2: op = rv_op_fsgnjx_d; break;
3258                 }
3259                 break;
3260             case 19:
3261                 switch ((inst >> 12) & 0b111) {
3262                 case 0: op = rv_op_fsgnj_q; break;
3263                 case 1: op = rv_op_fsgnjn_q; break;
3264                 case 2: op = rv_op_fsgnjx_q; break;
3265                 }
3266                 break;
3267             case 20:
3268                 switch ((inst >> 12) & 0b111) {
3269                 case 0: op = rv_op_fmin_s; break;
3270                 case 1: op = rv_op_fmax_s; break;
3271                 case 2: op = rv_op_fminm_s; break;
3272                 case 3: op = rv_op_fmaxm_s; break;
3273                 }
3274                 break;
3275             case 21:
3276                 switch ((inst >> 12) & 0b111) {
3277                 case 0: op = rv_op_fmin_d; break;
3278                 case 1: op = rv_op_fmax_d; break;
3279                 case 2: op = rv_op_fminm_d; break;
3280                 case 3: op = rv_op_fmaxm_d; break;
3281                 }
3282                 break;
3283             case 22:
3284                 switch (((inst >> 12) & 0b111)) {
3285                 case 2: op = rv_op_fminm_h; break;
3286                 case 3: op = rv_op_fmaxm_h; break;
3287                 }
3288                 break;
3289             case 23:
3290                 switch ((inst >> 12) & 0b111) {
3291                 case 0: op = rv_op_fmin_q; break;
3292                 case 1: op = rv_op_fmax_q; break;
3293                 case 2: op = rv_op_fminm_q; break;
3294                 case 3: op = rv_op_fmaxm_q; break;
3295                 }
3296                 break;
3297             case 32:
3298                 switch ((inst >> 20) & 0b11111) {
3299                 case 1: op = rv_op_fcvt_s_d; break;
3300                 case 3: op = rv_op_fcvt_s_q; break;
3301                 case 4: op = rv_op_fround_s; break;
3302                 case 5: op = rv_op_froundnx_s; break;
3303                 case 6: op = rv_op_fcvt_s_bf16; break;
3304                 }
3305                 break;
3306             case 33:
3307                 switch ((inst >> 20) & 0b11111) {
3308                 case 0: op = rv_op_fcvt_d_s; break;
3309                 case 3: op = rv_op_fcvt_d_q; break;
3310                 case 4: op = rv_op_fround_d; break;
3311                 case 5: op = rv_op_froundnx_d; break;
3312                 }
3313                 break;
3314             case 34:
3315                 switch (((inst >> 20) & 0b11111)) {
3316                 case 4: op = rv_op_fround_h; break;
3317                 case 5: op = rv_op_froundnx_h; break;
3318                 case 8: op = rv_op_fcvt_bf16_s; break;
3319                 }
3320                 break;
3321             case 35:
3322                 switch ((inst >> 20) & 0b11111) {
3323                 case 0: op = rv_op_fcvt_q_s; break;
3324                 case 1: op = rv_op_fcvt_q_d; break;
3325                 case 4: op = rv_op_fround_q; break;
3326                 case 5: op = rv_op_froundnx_q; break;
3327                 }
3328                 break;
3329             case 44:
3330                 switch ((inst >> 20) & 0b11111) {
3331                 case 0: op = rv_op_fsqrt_s; break;
3332                 }
3333                 break;
3334             case 45:
3335                 switch ((inst >> 20) & 0b11111) {
3336                 case 0: op = rv_op_fsqrt_d; break;
3337                 }
3338                 break;
3339             case 47:
3340                 switch ((inst >> 20) & 0b11111) {
3341                 case 0: op = rv_op_fsqrt_q; break;
3342                 }
3343                 break;
3344             case 80:
3345                 switch ((inst >> 12) & 0b111) {
3346                 case 0: op = rv_op_fle_s; break;
3347                 case 1: op = rv_op_flt_s; break;
3348                 case 2: op = rv_op_feq_s; break;
3349                 case 4: op = rv_op_fleq_s; break;
3350                 case 5: op = rv_op_fltq_s; break;
3351                 }
3352                 break;
3353             case 81:
3354                 switch ((inst >> 12) & 0b111) {
3355                 case 0: op = rv_op_fle_d; break;
3356                 case 1: op = rv_op_flt_d; break;
3357                 case 2: op = rv_op_feq_d; break;
3358                 case 4: op = rv_op_fleq_d; break;
3359                 case 5: op = rv_op_fltq_d; break;
3360                 }
3361                 break;
3362             case 82:
3363                 switch (((inst >> 12) & 0b111)) {
3364                 case 4: op = rv_op_fleq_h; break;
3365                 case 5: op = rv_op_fltq_h; break;
3366                 }
3367                 break;
3368             case 83:
3369                 switch ((inst >> 12) & 0b111) {
3370                 case 0: op = rv_op_fle_q; break;
3371                 case 1: op = rv_op_flt_q; break;
3372                 case 2: op = rv_op_feq_q; break;
3373                 case 4: op = rv_op_fleq_q; break;
3374                 case 5: op = rv_op_fltq_q; break;
3375                 }
3376                 break;
3377             case 89:
3378                 switch (((inst >> 12) & 0b111)) {
3379                 case 0: op = rv_op_fmvp_d_x; break;
3380                 }
3381                 break;
3382             case 91:
3383                 switch (((inst >> 12) & 0b111)) {
3384                 case 0: op = rv_op_fmvp_q_x; break;
3385                 }
3386                 break;
3387             case 96:
3388                 switch ((inst >> 20) & 0b11111) {
3389                 case 0: op = rv_op_fcvt_w_s; break;
3390                 case 1: op = rv_op_fcvt_wu_s; break;
3391                 case 2: op = rv_op_fcvt_l_s; break;
3392                 case 3: op = rv_op_fcvt_lu_s; break;
3393                 }
3394                 break;
3395             case 97:
3396                 switch ((inst >> 20) & 0b11111) {
3397                 case 0: op = rv_op_fcvt_w_d; break;
3398                 case 1: op = rv_op_fcvt_wu_d; break;
3399                 case 2: op = rv_op_fcvt_l_d; break;
3400                 case 3: op = rv_op_fcvt_lu_d; break;
3401                 case 8: op = rv_op_fcvtmod_w_d; break;
3402                 }
3403                 break;
3404             case 99:
3405                 switch ((inst >> 20) & 0b11111) {
3406                 case 0: op = rv_op_fcvt_w_q; break;
3407                 case 1: op = rv_op_fcvt_wu_q; break;
3408                 case 2: op = rv_op_fcvt_l_q; break;
3409                 case 3: op = rv_op_fcvt_lu_q; break;
3410                 }
3411                 break;
3412             case 104:
3413                 switch ((inst >> 20) & 0b11111) {
3414                 case 0: op = rv_op_fcvt_s_w; break;
3415                 case 1: op = rv_op_fcvt_s_wu; break;
3416                 case 2: op = rv_op_fcvt_s_l; break;
3417                 case 3: op = rv_op_fcvt_s_lu; break;
3418                 }
3419                 break;
3420             case 105:
3421                 switch ((inst >> 20) & 0b11111) {
3422                 case 0: op = rv_op_fcvt_d_w; break;
3423                 case 1: op = rv_op_fcvt_d_wu; break;
3424                 case 2: op = rv_op_fcvt_d_l; break;
3425                 case 3: op = rv_op_fcvt_d_lu; break;
3426                 }
3427                 break;
3428             case 107:
3429                 switch ((inst >> 20) & 0b11111) {
3430                 case 0: op = rv_op_fcvt_q_w; break;
3431                 case 1: op = rv_op_fcvt_q_wu; break;
3432                 case 2: op = rv_op_fcvt_q_l; break;
3433                 case 3: op = rv_op_fcvt_q_lu; break;
3434                 }
3435                 break;
3436             case 112:
3437                 switch (((inst >> 17) & 0b11111000) |
3438                         ((inst >> 12) & 0b00000111)) {
3439                 case 0: op = rv_op_fmv_x_s; break;
3440                 case 1: op = rv_op_fclass_s; break;
3441                 }
3442                 break;
3443             case 113:
3444                 switch (((inst >> 17) & 0b11111000) |
3445                         ((inst >> 12) & 0b00000111)) {
3446                 case 0: op = rv_op_fmv_x_d; break;
3447                 case 1: op = rv_op_fclass_d; break;
3448                 case 8: op = rv_op_fmvh_x_d; break;
3449                 }
3450                 break;
3451             case 114:
3452                 switch (((inst >> 17) & 0b11111000) |
3453                         ((inst >> 12) & 0b00000111)) {
3454                 case 0: op = rv_op_fmv_x_h; break;
3455                 }
3456                 break;
3457             case 115:
3458                 switch (((inst >> 17) & 0b11111000) |
3459                         ((inst >> 12) & 0b00000111)) {
3460                 case 0: op = rv_op_fmv_x_q; break;
3461                 case 1: op = rv_op_fclass_q; break;
3462                 case 8: op = rv_op_fmvh_x_q; break;
3463                 }
3464                 break;
3465             case 120:
3466                 switch (((inst >> 17) & 0b11111000) |
3467                         ((inst >> 12) & 0b00000111)) {
3468                 case 0: op = rv_op_fmv_s_x; break;
3469                 case 8: op = rv_op_fli_s; break;
3470                 }
3471                 break;
3472             case 121:
3473                 switch (((inst >> 17) & 0b11111000) |
3474                         ((inst >> 12) & 0b00000111)) {
3475                 case 0: op = rv_op_fmv_d_x; break;
3476                 case 8: op = rv_op_fli_d; break;
3477                 }
3478                 break;
3479             case 122:
3480                 switch (((inst >> 17) & 0b11111000) |
3481                         ((inst >> 12) & 0b00000111)) {
3482                 case 0: op = rv_op_fmv_h_x; break;
3483                 case 8: op = rv_op_fli_h; break;
3484                 }
3485                 break;
3486             case 123:
3487                 switch (((inst >> 17) & 0b11111000) |
3488                         ((inst >> 12) & 0b00000111)) {
3489                 case 0: op = rv_op_fmv_q_x; break;
3490                 case 8: op = rv_op_fli_q; break;
3491                 }
3492                 break;
3493             }
3494             break;
3495         case 21:
3496             switch ((inst >> 12) & 0b111) {
3497             case 0:
3498                 switch ((inst >> 26) & 0b111111) {
3499                 case 0: op = rv_op_vadd_vv; break;
3500                 case 1: op = rv_op_vandn_vv; break;
3501                 case 2: op = rv_op_vsub_vv; break;
3502                 case 4: op = rv_op_vminu_vv; break;
3503                 case 5: op = rv_op_vmin_vv; break;
3504                 case 6: op = rv_op_vmaxu_vv; break;
3505                 case 7: op = rv_op_vmax_vv; break;
3506                 case 9: op = rv_op_vand_vv; break;
3507                 case 10: op = rv_op_vor_vv; break;
3508                 case 11: op = rv_op_vxor_vv; break;
3509                 case 12: op = rv_op_vrgather_vv; break;
3510                 case 14: op = rv_op_vrgatherei16_vv; break;
3511                 case 16:
3512                     if (((inst >> 25) & 1) == 0) {
3513                         op = rv_op_vadc_vvm;
3514                     }
3515                     break;
3516                 case 17: op = rv_op_vmadc_vvm; break;
3517                 case 18:
3518                     if (((inst >> 25) & 1) == 0) {
3519                         op = rv_op_vsbc_vvm;
3520                     }
3521                     break;
3522                 case 19: op = rv_op_vmsbc_vvm; break;
3523                 case 20: op = rv_op_vror_vv; break;
3524                 case 21: op = rv_op_vrol_vv; break;
3525                 case 23:
3526                     if (((inst >> 20) & 0b111111) == 32)
3527                         op = rv_op_vmv_v_v;
3528                     else if (((inst >> 25) & 1) == 0)
3529                         op = rv_op_vmerge_vvm;
3530                     break;
3531                 case 24: op = rv_op_vmseq_vv; break;
3532                 case 25: op = rv_op_vmsne_vv; break;
3533                 case 26: op = rv_op_vmsltu_vv; break;
3534                 case 27: op = rv_op_vmslt_vv; break;
3535                 case 28: op = rv_op_vmsleu_vv; break;
3536                 case 29: op = rv_op_vmsle_vv; break;
3537                 case 32: op = rv_op_vsaddu_vv; break;
3538                 case 33: op = rv_op_vsadd_vv; break;
3539                 case 34: op = rv_op_vssubu_vv; break;
3540                 case 35: op = rv_op_vssub_vv; break;
3541                 case 37: op = rv_op_vsll_vv; break;
3542                 case 39: op = rv_op_vsmul_vv; break;
3543                 case 40: op = rv_op_vsrl_vv; break;
3544                 case 41: op = rv_op_vsra_vv; break;
3545                 case 42: op = rv_op_vssrl_vv; break;
3546                 case 43: op = rv_op_vssra_vv; break;
3547                 case 44: op = rv_op_vnsrl_wv; break;
3548                 case 45: op = rv_op_vnsra_wv; break;
3549                 case 46: op = rv_op_vnclipu_wv; break;
3550                 case 47: op = rv_op_vnclip_wv; break;
3551                 case 48: op = rv_op_vwredsumu_vs; break;
3552                 case 49: op = rv_op_vwredsum_vs; break;
3553                 case 53: op = rv_op_vwsll_vv; break;
3554                 }
3555                 break;
3556             case 1:
3557                 switch ((inst >> 26) & 0b111111) {
3558                 case 0: op = rv_op_vfadd_vv; break;
3559                 case 1: op = rv_op_vfredusum_vs; break;
3560                 case 2: op = rv_op_vfsub_vv; break;
3561                 case 3: op = rv_op_vfredosum_vs; break;
3562                 case 4: op = rv_op_vfmin_vv; break;
3563                 case 5: op = rv_op_vfredmin_vs; break;
3564                 case 6: op = rv_op_vfmax_vv; break;
3565                 case 7: op = rv_op_vfredmax_vs; break;
3566                 case 8: op = rv_op_vfsgnj_vv; break;
3567                 case 9: op = rv_op_vfsgnjn_vv; break;
3568                 case 10: op = rv_op_vfsgnjx_vv; break;
3569                 case 16:
3570                     switch ((inst >> 15) & 0b11111) {
3571                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
3572                     }
3573                     break;
3574                 case 18:
3575                     switch ((inst >> 15) & 0b11111) {
3576                     case 0: op = rv_op_vfcvt_xu_f_v; break;
3577                     case 1: op = rv_op_vfcvt_x_f_v; break;
3578                     case 2: op = rv_op_vfcvt_f_xu_v; break;
3579                     case 3: op = rv_op_vfcvt_f_x_v; break;
3580                     case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
3581                     case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
3582                     case 8: op = rv_op_vfwcvt_xu_f_v; break;
3583                     case 9: op = rv_op_vfwcvt_x_f_v; break;
3584                     case 10: op = rv_op_vfwcvt_f_xu_v; break;
3585                     case 11: op = rv_op_vfwcvt_f_x_v; break;
3586                     case 12: op = rv_op_vfwcvt_f_f_v; break;
3587                     case 13: op = rv_op_vfwcvtbf16_f_f_v; break;
3588                     case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
3589                     case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
3590                     case 16: op = rv_op_vfncvt_xu_f_w; break;
3591                     case 17: op = rv_op_vfncvt_x_f_w; break;
3592                     case 18: op = rv_op_vfncvt_f_xu_w; break;
3593                     case 19: op = rv_op_vfncvt_f_x_w; break;
3594                     case 20: op = rv_op_vfncvt_f_f_w; break;
3595                     case 21: op = rv_op_vfncvt_rod_f_f_w; break;
3596                     case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
3597                     case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
3598                     case 29: op = rv_op_vfncvtbf16_f_f_w; break;
3599                     }
3600                     break;
3601                 case 19:
3602                     switch ((inst >> 15) & 0b11111) {
3603                     case 0: op = rv_op_vfsqrt_v; break;
3604                     case 4: op = rv_op_vfrsqrt7_v; break;
3605                     case 5: op = rv_op_vfrec7_v; break;
3606                     case 16: op = rv_op_vfclass_v; break;
3607                     }
3608                     break;
3609                 case 24: op = rv_op_vmfeq_vv; break;
3610                 case 25: op = rv_op_vmfle_vv; break;
3611                 case 27: op = rv_op_vmflt_vv; break;
3612                 case 28: op = rv_op_vmfne_vv; break;
3613                 case 32: op = rv_op_vfdiv_vv; break;
3614                 case 36: op = rv_op_vfmul_vv; break;
3615                 case 40: op = rv_op_vfmadd_vv; break;
3616                 case 41: op = rv_op_vfnmadd_vv; break;
3617                 case 42: op = rv_op_vfmsub_vv; break;
3618                 case 43: op = rv_op_vfnmsub_vv; break;
3619                 case 44: op = rv_op_vfmacc_vv; break;
3620                 case 45: op = rv_op_vfnmacc_vv; break;
3621                 case 46: op = rv_op_vfmsac_vv; break;
3622                 case 47: op = rv_op_vfnmsac_vv; break;
3623                 case 48: op = rv_op_vfwadd_vv; break;
3624                 case 49: op = rv_op_vfwredusum_vs; break;
3625                 case 50: op = rv_op_vfwsub_vv; break;
3626                 case 51: op = rv_op_vfwredosum_vs; break;
3627                 case 52: op = rv_op_vfwadd_wv; break;
3628                 case 54: op = rv_op_vfwsub_wv; break;
3629                 case 56: op = rv_op_vfwmul_vv; break;
3630                 case 59: op = rv_op_vfwmaccbf16_vv; break;
3631                 case 60: op = rv_op_vfwmacc_vv; break;
3632                 case 61: op = rv_op_vfwnmacc_vv; break;
3633                 case 62: op = rv_op_vfwmsac_vv; break;
3634                 case 63: op = rv_op_vfwnmsac_vv; break;
3635                 }
3636                 break;
3637             case 2:
3638                 switch ((inst >> 26) & 0b111111) {
3639                 case 0: op = rv_op_vredsum_vs; break;
3640                 case 1: op = rv_op_vredand_vs; break;
3641                 case 2: op = rv_op_vredor_vs; break;
3642                 case 3: op = rv_op_vredxor_vs; break;
3643                 case 4: op = rv_op_vredminu_vs; break;
3644                 case 5: op = rv_op_vredmin_vs; break;
3645                 case 6: op = rv_op_vredmaxu_vs; break;
3646                 case 7: op = rv_op_vredmax_vs; break;
3647                 case 8: op = rv_op_vaaddu_vv; break;
3648                 case 9: op = rv_op_vaadd_vv; break;
3649                 case 10: op = rv_op_vasubu_vv; break;
3650                 case 11: op = rv_op_vasub_vv; break;
3651                 case 12: op = rv_op_vclmul_vv; break;
3652                 case 13: op = rv_op_vclmulh_vv; break;
3653                 case 16:
3654                     switch ((inst >> 15) & 0b11111) {
3655                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
3656                     case 16: op = rv_op_vcpop_m; break;
3657                     case 17: op = rv_op_vfirst_m; break;
3658                     }
3659                     break;
3660                 case 18:
3661                     switch ((inst >> 15) & 0b11111) {
3662                     case 2: op = rv_op_vzext_vf8; break;
3663                     case 3: op = rv_op_vsext_vf8; break;
3664                     case 4: op = rv_op_vzext_vf4; break;
3665                     case 5: op = rv_op_vsext_vf4; break;
3666                     case 6: op = rv_op_vzext_vf2; break;
3667                     case 7: op = rv_op_vsext_vf2; break;
3668                     case 8: op = rv_op_vbrev8_v; break;
3669                     case 9: op = rv_op_vrev8_v; break;
3670                     case 10: op = rv_op_vbrev_v; break;
3671                     case 12: op = rv_op_vclz_v; break;
3672                     case 13: op = rv_op_vctz_v; break;
3673                     case 14: op = rv_op_vcpop_v; break;
3674                     }
3675                     break;
3676                 case 20:
3677                     switch ((inst >> 15) & 0b11111) {
3678                     case 1: op = rv_op_vmsbf_m;  break;
3679                     case 2: op = rv_op_vmsof_m; break;
3680                     case 3: op = rv_op_vmsif_m; break;
3681                     case 16: op = rv_op_viota_m; break;
3682                     case 17:
3683                         if (((inst >> 20) & 0b11111) == 0) {
3684                             op = rv_op_vid_v;
3685                         }
3686                         break;
3687                     }
3688                     break;
3689                 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
3690                 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break;
3691                 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break;
3692                 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break;
3693                 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break;
3694                 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break;
3695                 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break;
3696                 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break;
3697                 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break;
3698                 case 32: op = rv_op_vdivu_vv; break;
3699                 case 33: op = rv_op_vdiv_vv; break;
3700                 case 34: op = rv_op_vremu_vv; break;
3701                 case 35: op = rv_op_vrem_vv; break;
3702                 case 36: op = rv_op_vmulhu_vv; break;
3703                 case 37: op = rv_op_vmul_vv; break;
3704                 case 38: op = rv_op_vmulhsu_vv; break;
3705                 case 39: op = rv_op_vmulh_vv; break;
3706                 case 41: op = rv_op_vmadd_vv; break;
3707                 case 43: op = rv_op_vnmsub_vv; break;
3708                 case 45: op = rv_op_vmacc_vv; break;
3709                 case 47: op = rv_op_vnmsac_vv; break;
3710                 case 48: op = rv_op_vwaddu_vv; break;
3711                 case 49: op = rv_op_vwadd_vv; break;
3712                 case 50: op = rv_op_vwsubu_vv; break;
3713                 case 51: op = rv_op_vwsub_vv; break;
3714                 case 52: op = rv_op_vwaddu_wv; break;
3715                 case 53: op = rv_op_vwadd_wv; break;
3716                 case 54: op = rv_op_vwsubu_wv; break;
3717                 case 55: op = rv_op_vwsub_wv; break;
3718                 case 56: op = rv_op_vwmulu_vv; break;
3719                 case 58: op = rv_op_vwmulsu_vv; break;
3720                 case 59: op = rv_op_vwmul_vv; break;
3721                 case 60: op = rv_op_vwmaccu_vv; break;
3722                 case 61: op = rv_op_vwmacc_vv; break;
3723                 case 63: op = rv_op_vwmaccsu_vv; break;
3724                 }
3725                 break;
3726             case 3:
3727                 switch ((inst >> 26) & 0b111111) {
3728                 case 0: op = rv_op_vadd_vi; break;
3729                 case 3: op = rv_op_vrsub_vi; break;
3730                 case 9: op = rv_op_vand_vi; break;
3731                 case 10: op = rv_op_vor_vi; break;
3732                 case 11: op = rv_op_vxor_vi; break;
3733                 case 12: op = rv_op_vrgather_vi; break;
3734                 case 14: op = rv_op_vslideup_vi; break;
3735                 case 15: op = rv_op_vslidedown_vi; break;
3736                 case 16:
3737                     if (((inst >> 25) & 1) == 0) {
3738                         op = rv_op_vadc_vim;
3739                     }
3740                     break;
3741                 case 17: op = rv_op_vmadc_vim; break;
3742                 case 20: case 21: op = rv_op_vror_vi; break;
3743                 case 23:
3744                     if (((inst >> 20) & 0b111111) == 32)
3745                         op = rv_op_vmv_v_i;
3746                     else if (((inst >> 25) & 1) == 0)
3747                         op = rv_op_vmerge_vim;
3748                     break;
3749                 case 24: op = rv_op_vmseq_vi; break;
3750                 case 25: op = rv_op_vmsne_vi; break;
3751                 case 28: op = rv_op_vmsleu_vi; break;
3752                 case 29: op = rv_op_vmsle_vi; break;
3753                 case 30: op = rv_op_vmsgtu_vi; break;
3754                 case 31: op = rv_op_vmsgt_vi; break;
3755                 case 32: op = rv_op_vsaddu_vi; break;
3756                 case 33: op = rv_op_vsadd_vi; break;
3757                 case 37: op = rv_op_vsll_vi; break;
3758                 case 39:
3759                     switch ((inst >> 15) & 0b11111) {
3760                     case 0: op = rv_op_vmv1r_v; break;
3761                     case 1: op = rv_op_vmv2r_v; break;
3762                     case 3: op = rv_op_vmv4r_v; break;
3763                     case 7: op = rv_op_vmv8r_v; break;
3764                     }
3765                     break;
3766                 case 40: op = rv_op_vsrl_vi; break;
3767                 case 41: op = rv_op_vsra_vi; break;
3768                 case 42: op = rv_op_vssrl_vi; break;
3769                 case 43: op = rv_op_vssra_vi; break;
3770                 case 44: op = rv_op_vnsrl_wi; break;
3771                 case 45: op = rv_op_vnsra_wi; break;
3772                 case 46: op = rv_op_vnclipu_wi; break;
3773                 case 47: op = rv_op_vnclip_wi; break;
3774                 case 53: op = rv_op_vwsll_vi; break;
3775                 }
3776                 break;
3777             case 4:
3778                 switch ((inst >> 26) & 0b111111) {
3779                 case 0: op = rv_op_vadd_vx; break;
3780                 case 1: op = rv_op_vandn_vx; break;
3781                 case 2: op = rv_op_vsub_vx; break;
3782                 case 3: op = rv_op_vrsub_vx; break;
3783                 case 4: op = rv_op_vminu_vx; break;
3784                 case 5: op = rv_op_vmin_vx; break;
3785                 case 6: op = rv_op_vmaxu_vx; break;
3786                 case 7: op = rv_op_vmax_vx; break;
3787                 case 9: op = rv_op_vand_vx; break;
3788                 case 10: op = rv_op_vor_vx; break;
3789                 case 11: op = rv_op_vxor_vx; break;
3790                 case 12: op = rv_op_vrgather_vx; break;
3791                 case 14: op = rv_op_vslideup_vx; break;
3792                 case 15: op = rv_op_vslidedown_vx; break;
3793                 case 16:
3794                     if (((inst >> 25) & 1) == 0) {
3795                         op = rv_op_vadc_vxm;
3796                     }
3797                     break;
3798                 case 17: op = rv_op_vmadc_vxm; break;
3799                 case 18:
3800                     if (((inst >> 25) & 1) == 0) {
3801                         op = rv_op_vsbc_vxm;
3802                     }
3803                     break;
3804                 case 19: op = rv_op_vmsbc_vxm; break;
3805                 case 20: op = rv_op_vror_vx; break;
3806                 case 21: op = rv_op_vrol_vx; break;
3807                 case 23:
3808                     if (((inst >> 20) & 0b111111) == 32)
3809                         op = rv_op_vmv_v_x;
3810                     else if (((inst >> 25) & 1) == 0)
3811                         op = rv_op_vmerge_vxm;
3812                     break;
3813                 case 24: op = rv_op_vmseq_vx; break;
3814                 case 25: op = rv_op_vmsne_vx; break;
3815                 case 26: op = rv_op_vmsltu_vx; break;
3816                 case 27: op = rv_op_vmslt_vx; break;
3817                 case 28: op = rv_op_vmsleu_vx; break;
3818                 case 29: op = rv_op_vmsle_vx; break;
3819                 case 30: op = rv_op_vmsgtu_vx; break;
3820                 case 31: op = rv_op_vmsgt_vx; break;
3821                 case 32: op = rv_op_vsaddu_vx; break;
3822                 case 33: op = rv_op_vsadd_vx; break;
3823                 case 34: op = rv_op_vssubu_vx; break;
3824                 case 35: op = rv_op_vssub_vx; break;
3825                 case 37: op = rv_op_vsll_vx; break;
3826                 case 39: op = rv_op_vsmul_vx; break;
3827                 case 40: op = rv_op_vsrl_vx; break;
3828                 case 41: op = rv_op_vsra_vx; break;
3829                 case 42: op = rv_op_vssrl_vx; break;
3830                 case 43: op = rv_op_vssra_vx; break;
3831                 case 44: op = rv_op_vnsrl_wx; break;
3832                 case 45: op = rv_op_vnsra_wx; break;
3833                 case 46: op = rv_op_vnclipu_wx; break;
3834                 case 47: op = rv_op_vnclip_wx; break;
3835                 case 53: op = rv_op_vwsll_vx; break;
3836                 }
3837                 break;
3838             case 5:
3839                 switch ((inst >> 26) & 0b111111) {
3840                 case 0: op = rv_op_vfadd_vf; break;
3841                 case 2: op = rv_op_vfsub_vf; break;
3842                 case 4: op = rv_op_vfmin_vf; break;
3843                 case 6: op = rv_op_vfmax_vf; break;
3844                 case 8: op = rv_op_vfsgnj_vf; break;
3845                 case 9: op = rv_op_vfsgnjn_vf; break;
3846                 case 10: op = rv_op_vfsgnjx_vf; break;
3847                 case 14: op = rv_op_vfslide1up_vf; break;
3848                 case 15: op = rv_op_vfslide1down_vf; break;
3849                 case 16:
3850                     switch ((inst >> 20) & 0b11111) {
3851                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
3852                     }
3853                     break;
3854                 case 23:
3855                     if (((inst >> 25) & 1) == 0)
3856                         op = rv_op_vfmerge_vfm;
3857                     else if (((inst >> 20) & 0b111111) == 32)
3858                         op = rv_op_vfmv_v_f;
3859                     break;
3860                 case 24: op = rv_op_vmfeq_vf; break;
3861                 case 25: op = rv_op_vmfle_vf; break;
3862                 case 27: op = rv_op_vmflt_vf; break;
3863                 case 28: op = rv_op_vmfne_vf; break;
3864                 case 29: op = rv_op_vmfgt_vf; break;
3865                 case 31: op = rv_op_vmfge_vf; break;
3866                 case 32: op = rv_op_vfdiv_vf; break;
3867                 case 33: op = rv_op_vfrdiv_vf; break;
3868                 case 36: op = rv_op_vfmul_vf; break;
3869                 case 39: op = rv_op_vfrsub_vf; break;
3870                 case 40: op = rv_op_vfmadd_vf; break;
3871                 case 41: op = rv_op_vfnmadd_vf; break;
3872                 case 42: op = rv_op_vfmsub_vf; break;
3873                 case 43: op = rv_op_vfnmsub_vf; break;
3874                 case 44: op = rv_op_vfmacc_vf; break;
3875                 case 45: op = rv_op_vfnmacc_vf; break;
3876                 case 46: op = rv_op_vfmsac_vf; break;
3877                 case 47: op = rv_op_vfnmsac_vf; break;
3878                 case 48: op = rv_op_vfwadd_vf; break;
3879                 case 50: op = rv_op_vfwsub_vf; break;
3880                 case 52: op = rv_op_vfwadd_wf; break;
3881                 case 54: op = rv_op_vfwsub_wf; break;
3882                 case 56: op = rv_op_vfwmul_vf; break;
3883                 case 59: op = rv_op_vfwmaccbf16_vf; break;
3884                 case 60: op = rv_op_vfwmacc_vf; break;
3885                 case 61: op = rv_op_vfwnmacc_vf; break;
3886                 case 62: op = rv_op_vfwmsac_vf; break;
3887                 case 63: op = rv_op_vfwnmsac_vf; break;
3888                 }
3889                 break;
3890             case 6:
3891                 switch ((inst >> 26) & 0b111111) {
3892                 case 8: op = rv_op_vaaddu_vx; break;
3893                 case 9: op = rv_op_vaadd_vx; break;
3894                 case 10: op = rv_op_vasubu_vx; break;
3895                 case 11: op = rv_op_vasub_vx; break;
3896                 case 12: op = rv_op_vclmul_vx; break;
3897                 case 13: op = rv_op_vclmulh_vx; break;
3898                 case 14: op = rv_op_vslide1up_vx; break;
3899                 case 15: op = rv_op_vslide1down_vx; break;
3900                 case 16:
3901                     switch ((inst >> 20) & 0b11111) {
3902                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
3903                     }
3904                     break;
3905                 case 32: op = rv_op_vdivu_vx; break;
3906                 case 33: op = rv_op_vdiv_vx; break;
3907                 case 34: op = rv_op_vremu_vx; break;
3908                 case 35: op = rv_op_vrem_vx; break;
3909                 case 36: op = rv_op_vmulhu_vx; break;
3910                 case 37: op = rv_op_vmul_vx; break;
3911                 case 38: op = rv_op_vmulhsu_vx; break;
3912                 case 39: op = rv_op_vmulh_vx; break;
3913                 case 41: op = rv_op_vmadd_vx; break;
3914                 case 43: op = rv_op_vnmsub_vx; break;
3915                 case 45: op = rv_op_vmacc_vx; break;
3916                 case 47: op = rv_op_vnmsac_vx; break;
3917                 case 48: op = rv_op_vwaddu_vx; break;
3918                 case 49: op = rv_op_vwadd_vx; break;
3919                 case 50: op = rv_op_vwsubu_vx; break;
3920                 case 51: op = rv_op_vwsub_vx; break;
3921                 case 52: op = rv_op_vwaddu_wx; break;
3922                 case 53: op = rv_op_vwadd_wx; break;
3923                 case 54: op = rv_op_vwsubu_wx; break;
3924                 case 55: op = rv_op_vwsub_wx; break;
3925                 case 56: op = rv_op_vwmulu_vx; break;
3926                 case 58: op = rv_op_vwmulsu_vx; break;
3927                 case 59: op = rv_op_vwmul_vx; break;
3928                 case 60: op = rv_op_vwmaccu_vx; break;
3929                 case 61: op = rv_op_vwmacc_vx; break;
3930                 case 62: op = rv_op_vwmaccus_vx; break;
3931                 case 63: op = rv_op_vwmaccsu_vx; break;
3932                 }
3933                 break;
3934             case 7:
3935                 if (((inst >> 31) & 1) == 0) {
3936                     op = rv_op_vsetvli;
3937                 } else if ((inst >> 30) & 1) {
3938                     op = rv_op_vsetivli;
3939                 } else if (((inst >> 25) & 0b11111) == 0) {
3940                     op = rv_op_vsetvl;
3941                 }
3942                 break;
3943             }
3944             break;
3945         case 22:
3946             switch ((inst >> 12) & 0b111) {
3947             case 0: op = rv_op_addid; break;
3948             case 1:
3949                 switch ((inst >> 26) & 0b111111) {
3950                 case 0: op = rv_op_sllid; break;
3951                 }
3952                 break;
3953             case 5:
3954                 switch ((inst >> 26) & 0b111111) {
3955                 case 0: op = rv_op_srlid; break;
3956                 case 16: op = rv_op_sraid; break;
3957                 }
3958                 break;
3959             }
3960             break;
3961         case 24:
3962             switch ((inst >> 12) & 0b111) {
3963             case 0: op = rv_op_beq; break;
3964             case 1: op = rv_op_bne; break;
3965             case 4: op = rv_op_blt; break;
3966             case 5: op = rv_op_bge; break;
3967             case 6: op = rv_op_bltu; break;
3968             case 7: op = rv_op_bgeu; break;
3969             }
3970             break;
3971         case 25:
3972             switch ((inst >> 12) & 0b111) {
3973             case 0: op = rv_op_jalr; break;
3974             }
3975             break;
3976         case 27: op = rv_op_jal; break;
3977         case 28:
3978             switch ((inst >> 12) & 0b111) {
3979             case 0:
3980                 switch (((inst >> 20) & 0b111111100000) |
3981                         ((inst >> 7) & 0b000000011111)) {
3982                 case 0:
3983                     switch ((inst >> 15) & 0b1111111111) {
3984                     case 0: op = rv_op_ecall; break;
3985                     case 32: op = rv_op_ebreak; break;
3986                     case 64: op = rv_op_uret; break;
3987                     case 416: op = rv_op_wrs_nto; break;
3988                     case 928: op = rv_op_wrs_sto; break;
3989                     }
3990                     break;
3991                 case 256:
3992                     switch ((inst >> 20) & 0b11111) {
3993                     case 2:
3994                         switch ((inst >> 15) & 0b11111) {
3995                         case 0: op = rv_op_sret; break;
3996                         }
3997                         break;
3998                     case 4: op = rv_op_sfence_vm; break;
3999                     case 5:
4000                         switch ((inst >> 15) & 0b11111) {
4001                         case 0: op = rv_op_wfi; break;
4002                         }
4003                         break;
4004                     }
4005                     break;
4006                 case 288: op = rv_op_sfence_vma; break;
4007                 case 512:
4008                     switch ((inst >> 15) & 0b1111111111) {
4009                     case 64: op = rv_op_hret; break;
4010                     }
4011                     break;
4012                 case 768:
4013                     switch ((inst >> 15) & 0b1111111111) {
4014                     case 64: op = rv_op_mret; break;
4015                     }
4016                     break;
4017                 case 1952:
4018                     switch ((inst >> 15) & 0b1111111111) {
4019                     case 576: op = rv_op_dret; break;
4020                     }
4021                     break;
4022                 }
4023                 break;
4024             case 1: op = rv_op_csrrw; break;
4025             case 2: op = rv_op_csrrs; break;
4026             case 3: op = rv_op_csrrc; break;
4027             case 4:
4028                 if (dec->cfg->ext_zimop) {
4029                     int imm_mop5, imm_mop3;
4030                     if ((extract32(inst, 22, 10) & 0b1011001111)
4031                         == 0b1000000111) {
4032                         imm_mop5 = deposit32(deposit32(extract32(inst, 20, 2),
4033                                                        2, 2,
4034                                                        extract32(inst, 26, 2)),
4035                                              4, 1, extract32(inst, 30, 1));
4036                         op = rv_mop_r_0 + imm_mop5;
4037                     } else if ((extract32(inst, 25, 7) & 0b1011001)
4038                                == 0b1000001) {
4039                         imm_mop3 = deposit32(extract32(inst, 26, 2),
4040                                              2, 1, extract32(inst, 30, 1));
4041                         op = rv_mop_rr_0 + imm_mop3;
4042                     }
4043                 }
4044                 break;
4045             case 5: op = rv_op_csrrwi; break;
4046             case 6: op = rv_op_csrrsi; break;
4047             case 7: op = rv_op_csrrci; break;
4048             }
4049             break;
4050         case 29:
4051             if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
4052                 switch ((inst >> 26) & 0b111111) {
4053                 case 32: op = rv_op_vsm3me_vv; break;
4054                 case 33: op = rv_op_vsm4k_vi; break;
4055                 case 34: op = rv_op_vaeskf1_vi; break;
4056                 case 40:
4057                     switch ((inst >> 15) & 0b11111) {
4058                     case 0: op = rv_op_vaesdm_vv; break;
4059                     case 1: op = rv_op_vaesdf_vv; break;
4060                     case 2: op = rv_op_vaesem_vv; break;
4061                     case 3: op = rv_op_vaesef_vv; break;
4062                     case 16: op = rv_op_vsm4r_vv; break;
4063                     case 17: op = rv_op_vgmul_vv; break;
4064                     }
4065                     break;
4066                 case 41:
4067                     switch ((inst >> 15) & 0b11111) {
4068                     case 0: op = rv_op_vaesdm_vs; break;
4069                     case 1: op = rv_op_vaesdf_vs; break;
4070                     case 2: op = rv_op_vaesem_vs; break;
4071                     case 3: op = rv_op_vaesef_vs; break;
4072                     case 7: op = rv_op_vaesz_vs; break;
4073                     case 16: op = rv_op_vsm4r_vs; break;
4074                     }
4075                     break;
4076                 case 42: op = rv_op_vaeskf2_vi; break;
4077                 case 43: op = rv_op_vsm3c_vi; break;
4078                 case 44: op = rv_op_vghsh_vv; break;
4079                 case 45: op = rv_op_vsha2ms_vv; break;
4080                 case 46: op = rv_op_vsha2ch_vv; break;
4081                 case 47: op = rv_op_vsha2cl_vv; break;
4082                 }
4083             }
4084             break;
4085         case 30:
4086             switch (((inst >> 22) & 0b1111111000) |
4087                     ((inst >> 12) & 0b0000000111)) {
4088             case 0: op = rv_op_addd; break;
4089             case 1: op = rv_op_slld; break;
4090             case 5: op = rv_op_srld; break;
4091             case 8: op = rv_op_muld; break;
4092             case 12: op = rv_op_divd; break;
4093             case 13: op = rv_op_divud; break;
4094             case 14: op = rv_op_remd; break;
4095             case 15: op = rv_op_remud; break;
4096             case 256: op = rv_op_subd; break;
4097             case 261: op = rv_op_srad; break;
4098             }
4099             break;
4100         }
4101         break;
4102     }
4103     dec->op = op;
4104 }
4105 
4106 /* operand extractors */
4107 
4108 static uint32_t operand_rd(rv_inst inst)
4109 {
4110     return (inst << 52) >> 59;
4111 }
4112 
4113 static uint32_t operand_rs1(rv_inst inst)
4114 {
4115     return (inst << 44) >> 59;
4116 }
4117 
4118 static uint32_t operand_rs2(rv_inst inst)
4119 {
4120     return (inst << 39) >> 59;
4121 }
4122 
4123 static uint32_t operand_rs3(rv_inst inst)
4124 {
4125     return (inst << 32) >> 59;
4126 }
4127 
4128 static uint32_t operand_aq(rv_inst inst)
4129 {
4130     return (inst << 37) >> 63;
4131 }
4132 
4133 static uint32_t operand_rl(rv_inst inst)
4134 {
4135     return (inst << 38) >> 63;
4136 }
4137 
4138 static uint32_t operand_pred(rv_inst inst)
4139 {
4140     return (inst << 36) >> 60;
4141 }
4142 
4143 static uint32_t operand_succ(rv_inst inst)
4144 {
4145     return (inst << 40) >> 60;
4146 }
4147 
4148 static uint32_t operand_rm(rv_inst inst)
4149 {
4150     return (inst << 49) >> 61;
4151 }
4152 
4153 static uint32_t operand_shamt5(rv_inst inst)
4154 {
4155     return (inst << 39) >> 59;
4156 }
4157 
4158 static uint32_t operand_shamt6(rv_inst inst)
4159 {
4160     return (inst << 38) >> 58;
4161 }
4162 
4163 static uint32_t operand_shamt7(rv_inst inst)
4164 {
4165     return (inst << 37) >> 57;
4166 }
4167 
4168 static uint32_t operand_crdq(rv_inst inst)
4169 {
4170     return (inst << 59) >> 61;
4171 }
4172 
4173 static uint32_t operand_crs1q(rv_inst inst)
4174 {
4175     return (inst << 54) >> 61;
4176 }
4177 
4178 static uint32_t operand_crs1rdq(rv_inst inst)
4179 {
4180     return (inst << 54) >> 61;
4181 }
4182 
4183 static uint32_t operand_crs2q(rv_inst inst)
4184 {
4185     return (inst << 59) >> 61;
4186 }
4187 
4188 static uint32_t calculate_xreg(uint32_t sreg)
4189 {
4190     return sreg < 2 ? sreg + 8 : sreg + 16;
4191 }
4192 
4193 static uint32_t operand_sreg1(rv_inst inst)
4194 {
4195     return calculate_xreg((inst << 54) >> 61);
4196 }
4197 
4198 static uint32_t operand_sreg2(rv_inst inst)
4199 {
4200     return calculate_xreg((inst << 59) >> 61);
4201 }
4202 
4203 static uint32_t operand_crd(rv_inst inst)
4204 {
4205     return (inst << 52) >> 59;
4206 }
4207 
4208 static uint32_t operand_crs1(rv_inst inst)
4209 {
4210     return (inst << 52) >> 59;
4211 }
4212 
4213 static uint32_t operand_crs1rd(rv_inst inst)
4214 {
4215     return (inst << 52) >> 59;
4216 }
4217 
4218 static uint32_t operand_crs2(rv_inst inst)
4219 {
4220     return (inst << 57) >> 59;
4221 }
4222 
4223 static uint32_t operand_cimmsh5(rv_inst inst)
4224 {
4225     return (inst << 57) >> 59;
4226 }
4227 
4228 static uint32_t operand_csr12(rv_inst inst)
4229 {
4230     return (inst << 32) >> 52;
4231 }
4232 
4233 static int32_t operand_imm12(rv_inst inst)
4234 {
4235     return ((int64_t)inst << 32) >> 52;
4236 }
4237 
4238 static int32_t operand_imm20(rv_inst inst)
4239 {
4240     return (((int64_t)inst << 32) >> 44) << 12;
4241 }
4242 
4243 static int32_t operand_jimm20(rv_inst inst)
4244 {
4245     return (((int64_t)inst << 32) >> 63) << 20 |
4246         ((inst << 33) >> 54) << 1 |
4247         ((inst << 43) >> 63) << 11 |
4248         ((inst << 44) >> 56) << 12;
4249 }
4250 
4251 static int32_t operand_simm12(rv_inst inst)
4252 {
4253     return (((int64_t)inst << 32) >> 57) << 5 |
4254         (inst << 52) >> 59;
4255 }
4256 
4257 static int32_t operand_sbimm12(rv_inst inst)
4258 {
4259     return (((int64_t)inst << 32) >> 63) << 12 |
4260         ((inst << 33) >> 58) << 5 |
4261         ((inst << 52) >> 60) << 1 |
4262         ((inst << 56) >> 63) << 11;
4263 }
4264 
4265 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
4266 {
4267     int imm = ((inst << 51) >> 63) << 5 |
4268         (inst << 57) >> 59;
4269     if (isa == rv128) {
4270         imm = imm ? imm : 64;
4271     }
4272     return imm;
4273 }
4274 
4275 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
4276 {
4277     int imm = ((inst << 51) >> 63) << 5 |
4278         (inst << 57) >> 59;
4279     if (isa == rv128) {
4280         imm = imm | (imm & 32) << 1;
4281         imm = imm ? imm : 64;
4282     }
4283     return imm;
4284 }
4285 
4286 static int32_t operand_cimmi(rv_inst inst)
4287 {
4288     return (((int64_t)inst << 51) >> 63) << 5 |
4289         (inst << 57) >> 59;
4290 }
4291 
4292 static int32_t operand_cimmui(rv_inst inst)
4293 {
4294     return (((int64_t)inst << 51) >> 63) << 17 |
4295         ((inst << 57) >> 59) << 12;
4296 }
4297 
4298 static uint32_t operand_cimmlwsp(rv_inst inst)
4299 {
4300     return ((inst << 51) >> 63) << 5 |
4301         ((inst << 57) >> 61) << 2 |
4302         ((inst << 60) >> 62) << 6;
4303 }
4304 
4305 static uint32_t operand_cimmldsp(rv_inst inst)
4306 {
4307     return ((inst << 51) >> 63) << 5 |
4308         ((inst << 57) >> 62) << 3 |
4309         ((inst << 59) >> 61) << 6;
4310 }
4311 
4312 static uint32_t operand_cimmlqsp(rv_inst inst)
4313 {
4314     return ((inst << 51) >> 63) << 5 |
4315         ((inst << 57) >> 63) << 4 |
4316         ((inst << 58) >> 60) << 6;
4317 }
4318 
4319 static int32_t operand_cimm16sp(rv_inst inst)
4320 {
4321     return (((int64_t)inst << 51) >> 63) << 9 |
4322         ((inst << 57) >> 63) << 4 |
4323         ((inst << 58) >> 63) << 6 |
4324         ((inst << 59) >> 62) << 7 |
4325         ((inst << 61) >> 63) << 5;
4326 }
4327 
4328 static int32_t operand_cimmj(rv_inst inst)
4329 {
4330     return (((int64_t)inst << 51) >> 63) << 11 |
4331         ((inst << 52) >> 63) << 4 |
4332         ((inst << 53) >> 62) << 8 |
4333         ((inst << 55) >> 63) << 10 |
4334         ((inst << 56) >> 63) << 6 |
4335         ((inst << 57) >> 63) << 7 |
4336         ((inst << 58) >> 61) << 1 |
4337         ((inst << 61) >> 63) << 5;
4338 }
4339 
4340 static int32_t operand_cimmb(rv_inst inst)
4341 {
4342     return (((int64_t)inst << 51) >> 63) << 8 |
4343         ((inst << 52) >> 62) << 3 |
4344         ((inst << 57) >> 62) << 6 |
4345         ((inst << 59) >> 62) << 1 |
4346         ((inst << 61) >> 63) << 5;
4347 }
4348 
4349 static uint32_t operand_cimmswsp(rv_inst inst)
4350 {
4351     return ((inst << 51) >> 60) << 2 |
4352         ((inst << 55) >> 62) << 6;
4353 }
4354 
4355 static uint32_t operand_cimmsdsp(rv_inst inst)
4356 {
4357     return ((inst << 51) >> 61) << 3 |
4358         ((inst << 54) >> 61) << 6;
4359 }
4360 
4361 static uint32_t operand_cimmsqsp(rv_inst inst)
4362 {
4363     return ((inst << 51) >> 62) << 4 |
4364         ((inst << 53) >> 60) << 6;
4365 }
4366 
4367 static uint32_t operand_cimm4spn(rv_inst inst)
4368 {
4369     return ((inst << 51) >> 62) << 4 |
4370         ((inst << 53) >> 60) << 6 |
4371         ((inst << 57) >> 63) << 2 |
4372         ((inst << 58) >> 63) << 3;
4373 }
4374 
4375 static uint32_t operand_cimmw(rv_inst inst)
4376 {
4377     return ((inst << 51) >> 61) << 3 |
4378         ((inst << 57) >> 63) << 2 |
4379         ((inst << 58) >> 63) << 6;
4380 }
4381 
4382 static uint32_t operand_cimmd(rv_inst inst)
4383 {
4384     return ((inst << 51) >> 61) << 3 |
4385         ((inst << 57) >> 62) << 6;
4386 }
4387 
4388 static uint32_t operand_cimmq(rv_inst inst)
4389 {
4390     return ((inst << 51) >> 62) << 4 |
4391         ((inst << 53) >> 63) << 8 |
4392         ((inst << 57) >> 62) << 6;
4393 }
4394 
4395 static uint32_t operand_vimm(rv_inst inst)
4396 {
4397     return (int64_t)(inst << 44) >> 59;
4398 }
4399 
4400 static uint32_t operand_vzimm11(rv_inst inst)
4401 {
4402     return (inst << 33) >> 53;
4403 }
4404 
4405 static uint32_t operand_vzimm10(rv_inst inst)
4406 {
4407     return (inst << 34) >> 54;
4408 }
4409 
4410 static uint32_t operand_vzimm6(rv_inst inst)
4411 {
4412     return ((inst << 37) >> 63) << 5 |
4413         ((inst << 44) >> 59);
4414 }
4415 
4416 static uint32_t operand_bs(rv_inst inst)
4417 {
4418     return (inst << 32) >> 62;
4419 }
4420 
4421 static uint32_t operand_rnum(rv_inst inst)
4422 {
4423     return (inst << 40) >> 60;
4424 }
4425 
4426 static uint32_t operand_vm(rv_inst inst)
4427 {
4428     return (inst << 38) >> 63;
4429 }
4430 
4431 static uint32_t operand_uimm_c_lb(rv_inst inst)
4432 {
4433     return (((inst << 58) >> 63) << 1) |
4434         ((inst << 57) >> 63);
4435 }
4436 
4437 static uint32_t operand_uimm_c_lh(rv_inst inst)
4438 {
4439     return (((inst << 58) >> 63) << 1);
4440 }
4441 
4442 static uint32_t operand_zcmp_spimm(rv_inst inst)
4443 {
4444     return ((inst << 60) >> 62) << 4;
4445 }
4446 
4447 static uint32_t operand_zcmp_rlist(rv_inst inst)
4448 {
4449     return ((inst << 56) >> 60);
4450 }
4451 
4452 static uint32_t operand_imm6(rv_inst inst)
4453 {
4454     return (inst << 38) >> 60;
4455 }
4456 
4457 static uint32_t operand_imm2(rv_inst inst)
4458 {
4459     return (inst << 37) >> 62;
4460 }
4461 
4462 static uint32_t operand_immh(rv_inst inst)
4463 {
4464     return (inst << 32) >> 58;
4465 }
4466 
4467 static uint32_t operand_imml(rv_inst inst)
4468 {
4469     return (inst << 38) >> 58;
4470 }
4471 
4472 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
4473 {
4474     int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
4475     int regs = rlist == 15 ? 13 : rlist - 3;
4476     uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
4477     return stack_adj_base + spimm;
4478 }
4479 
4480 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
4481 {
4482     return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
4483                                operand_zcmp_spimm(inst));
4484 }
4485 
4486 static uint32_t operand_tbl_index(rv_inst inst)
4487 {
4488     return ((inst << 54) >> 56);
4489 }
4490 
4491 /* decode operands */
4492 
4493 static void decode_inst_operands(rv_decode *dec, rv_isa isa)
4494 {
4495     const rv_opcode_data *opcode_data = dec->opcode_data;
4496     rv_inst inst = dec->inst;
4497     dec->codec = opcode_data[dec->op].codec;
4498     switch (dec->codec) {
4499     case rv_codec_none:
4500         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4501         dec->imm = 0;
4502         break;
4503     case rv_codec_u:
4504         dec->rd = operand_rd(inst);
4505         dec->rs1 = dec->rs2 = rv_ireg_zero;
4506         dec->imm = operand_imm20(inst);
4507         break;
4508     case rv_codec_uj:
4509         dec->rd = operand_rd(inst);
4510         dec->rs1 = dec->rs2 = rv_ireg_zero;
4511         dec->imm = operand_jimm20(inst);
4512         break;
4513     case rv_codec_i:
4514         dec->rd = operand_rd(inst);
4515         dec->rs1 = operand_rs1(inst);
4516         dec->rs2 = rv_ireg_zero;
4517         dec->imm = operand_imm12(inst);
4518         break;
4519     case rv_codec_i_sh5:
4520         dec->rd = operand_rd(inst);
4521         dec->rs1 = operand_rs1(inst);
4522         dec->rs2 = rv_ireg_zero;
4523         dec->imm = operand_shamt5(inst);
4524         break;
4525     case rv_codec_i_sh6:
4526         dec->rd = operand_rd(inst);
4527         dec->rs1 = operand_rs1(inst);
4528         dec->rs2 = rv_ireg_zero;
4529         dec->imm = operand_shamt6(inst);
4530         break;
4531     case rv_codec_i_sh7:
4532         dec->rd = operand_rd(inst);
4533         dec->rs1 = operand_rs1(inst);
4534         dec->rs2 = rv_ireg_zero;
4535         dec->imm = operand_shamt7(inst);
4536         break;
4537     case rv_codec_i_csr:
4538         dec->rd = operand_rd(inst);
4539         dec->rs1 = operand_rs1(inst);
4540         dec->rs2 = rv_ireg_zero;
4541         dec->imm = operand_csr12(inst);
4542         break;
4543     case rv_codec_s:
4544         dec->rd = rv_ireg_zero;
4545         dec->rs1 = operand_rs1(inst);
4546         dec->rs2 = operand_rs2(inst);
4547         dec->imm = operand_simm12(inst);
4548         break;
4549     case rv_codec_sb:
4550         dec->rd = rv_ireg_zero;
4551         dec->rs1 = operand_rs1(inst);
4552         dec->rs2 = operand_rs2(inst);
4553         dec->imm = operand_sbimm12(inst);
4554         break;
4555     case rv_codec_r:
4556         dec->rd = operand_rd(inst);
4557         dec->rs1 = operand_rs1(inst);
4558         dec->rs2 = operand_rs2(inst);
4559         dec->imm = 0;
4560         break;
4561     case rv_codec_r_m:
4562         dec->rd = operand_rd(inst);
4563         dec->rs1 = operand_rs1(inst);
4564         dec->rs2 = operand_rs2(inst);
4565         dec->imm = 0;
4566         dec->rm = operand_rm(inst);
4567         break;
4568     case rv_codec_r4_m:
4569         dec->rd = operand_rd(inst);
4570         dec->rs1 = operand_rs1(inst);
4571         dec->rs2 = operand_rs2(inst);
4572         dec->rs3 = operand_rs3(inst);
4573         dec->imm = 0;
4574         dec->rm = operand_rm(inst);
4575         break;
4576     case rv_codec_r_a:
4577         dec->rd = operand_rd(inst);
4578         dec->rs1 = operand_rs1(inst);
4579         dec->rs2 = operand_rs2(inst);
4580         dec->imm = 0;
4581         dec->aq = operand_aq(inst);
4582         dec->rl = operand_rl(inst);
4583         break;
4584     case rv_codec_r_l:
4585         dec->rd = operand_rd(inst);
4586         dec->rs1 = operand_rs1(inst);
4587         dec->rs2 = rv_ireg_zero;
4588         dec->imm = 0;
4589         dec->aq = operand_aq(inst);
4590         dec->rl = operand_rl(inst);
4591         break;
4592     case rv_codec_r_f:
4593         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4594         dec->pred = operand_pred(inst);
4595         dec->succ = operand_succ(inst);
4596         dec->imm = 0;
4597         break;
4598     case rv_codec_cb:
4599         dec->rd = rv_ireg_zero;
4600         dec->rs1 = operand_crs1q(inst) + 8;
4601         dec->rs2 = rv_ireg_zero;
4602         dec->imm = operand_cimmb(inst);
4603         break;
4604     case rv_codec_cb_imm:
4605         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4606         dec->rs2 = rv_ireg_zero;
4607         dec->imm = operand_cimmi(inst);
4608         break;
4609     case rv_codec_cb_sh5:
4610         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4611         dec->rs2 = rv_ireg_zero;
4612         dec->imm = operand_cimmsh5(inst);
4613         break;
4614     case rv_codec_cb_sh6:
4615         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4616         dec->rs2 = rv_ireg_zero;
4617         dec->imm = operand_cimmshr6(inst, isa);
4618         break;
4619     case rv_codec_ci:
4620         dec->rd = dec->rs1 = operand_crs1rd(inst);
4621         dec->rs2 = rv_ireg_zero;
4622         dec->imm = operand_cimmi(inst);
4623         break;
4624     case rv_codec_ci_sh5:
4625         dec->rd = dec->rs1 = operand_crs1rd(inst);
4626         dec->rs2 = rv_ireg_zero;
4627         dec->imm = operand_cimmsh5(inst);
4628         break;
4629     case rv_codec_ci_sh6:
4630         dec->rd = dec->rs1 = operand_crs1rd(inst);
4631         dec->rs2 = rv_ireg_zero;
4632         dec->imm = operand_cimmshl6(inst, isa);
4633         break;
4634     case rv_codec_ci_16sp:
4635         dec->rd = rv_ireg_sp;
4636         dec->rs1 = rv_ireg_sp;
4637         dec->rs2 = rv_ireg_zero;
4638         dec->imm = operand_cimm16sp(inst);
4639         break;
4640     case rv_codec_ci_lwsp:
4641         dec->rd = operand_crd(inst);
4642         dec->rs1 = rv_ireg_sp;
4643         dec->rs2 = rv_ireg_zero;
4644         dec->imm = operand_cimmlwsp(inst);
4645         break;
4646     case rv_codec_ci_ldsp:
4647         dec->rd = operand_crd(inst);
4648         dec->rs1 = rv_ireg_sp;
4649         dec->rs2 = rv_ireg_zero;
4650         dec->imm = operand_cimmldsp(inst);
4651         break;
4652     case rv_codec_ci_lqsp:
4653         dec->rd = operand_crd(inst);
4654         dec->rs1 = rv_ireg_sp;
4655         dec->rs2 = rv_ireg_zero;
4656         dec->imm = operand_cimmlqsp(inst);
4657         break;
4658     case rv_codec_ci_li:
4659         dec->rd = operand_crd(inst);
4660         dec->rs1 = rv_ireg_zero;
4661         dec->rs2 = rv_ireg_zero;
4662         dec->imm = operand_cimmi(inst);
4663         break;
4664     case rv_codec_ci_lui:
4665         dec->rd = operand_crd(inst);
4666         dec->rs1 = rv_ireg_zero;
4667         dec->rs2 = rv_ireg_zero;
4668         dec->imm = operand_cimmui(inst);
4669         break;
4670     case rv_codec_ci_none:
4671         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4672         dec->imm = 0;
4673         break;
4674     case rv_codec_ciw_4spn:
4675         dec->rd = operand_crdq(inst) + 8;
4676         dec->rs1 = rv_ireg_sp;
4677         dec->rs2 = rv_ireg_zero;
4678         dec->imm = operand_cimm4spn(inst);
4679         break;
4680     case rv_codec_cj:
4681         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4682         dec->imm = operand_cimmj(inst);
4683         break;
4684     case rv_codec_cj_jal:
4685         dec->rd = rv_ireg_ra;
4686         dec->rs1 = dec->rs2 = rv_ireg_zero;
4687         dec->imm = operand_cimmj(inst);
4688         break;
4689     case rv_codec_cl_lw:
4690         dec->rd = operand_crdq(inst) + 8;
4691         dec->rs1 = operand_crs1q(inst) + 8;
4692         dec->rs2 = rv_ireg_zero;
4693         dec->imm = operand_cimmw(inst);
4694         break;
4695     case rv_codec_cl_ld:
4696         dec->rd = operand_crdq(inst) + 8;
4697         dec->rs1 = operand_crs1q(inst) + 8;
4698         dec->rs2 = rv_ireg_zero;
4699         dec->imm = operand_cimmd(inst);
4700         break;
4701     case rv_codec_cl_lq:
4702         dec->rd = operand_crdq(inst) + 8;
4703         dec->rs1 = operand_crs1q(inst) + 8;
4704         dec->rs2 = rv_ireg_zero;
4705         dec->imm = operand_cimmq(inst);
4706         break;
4707     case rv_codec_cr:
4708         dec->rd = dec->rs1 = operand_crs1rd(inst);
4709         dec->rs2 = operand_crs2(inst);
4710         dec->imm = 0;
4711         break;
4712     case rv_codec_cr_mv:
4713         dec->rd = operand_crd(inst);
4714         dec->rs1 = operand_crs2(inst);
4715         dec->rs2 = rv_ireg_zero;
4716         dec->imm = 0;
4717         break;
4718     case rv_codec_cr_jalr:
4719         dec->rd = rv_ireg_ra;
4720         dec->rs1 = operand_crs1(inst);
4721         dec->rs2 = rv_ireg_zero;
4722         dec->imm = 0;
4723         break;
4724     case rv_codec_cr_jr:
4725         dec->rd = rv_ireg_zero;
4726         dec->rs1 = operand_crs1(inst);
4727         dec->rs2 = rv_ireg_zero;
4728         dec->imm = 0;
4729         break;
4730     case rv_codec_cs:
4731         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4732         dec->rs2 = operand_crs2q(inst) + 8;
4733         dec->imm = 0;
4734         break;
4735     case rv_codec_cs_sw:
4736         dec->rd = rv_ireg_zero;
4737         dec->rs1 = operand_crs1q(inst) + 8;
4738         dec->rs2 = operand_crs2q(inst) + 8;
4739         dec->imm = operand_cimmw(inst);
4740         break;
4741     case rv_codec_cs_sd:
4742         dec->rd = rv_ireg_zero;
4743         dec->rs1 = operand_crs1q(inst) + 8;
4744         dec->rs2 = operand_crs2q(inst) + 8;
4745         dec->imm = operand_cimmd(inst);
4746         break;
4747     case rv_codec_cs_sq:
4748         dec->rd = rv_ireg_zero;
4749         dec->rs1 = operand_crs1q(inst) + 8;
4750         dec->rs2 = operand_crs2q(inst) + 8;
4751         dec->imm = operand_cimmq(inst);
4752         break;
4753     case rv_codec_css_swsp:
4754         dec->rd = rv_ireg_zero;
4755         dec->rs1 = rv_ireg_sp;
4756         dec->rs2 = operand_crs2(inst);
4757         dec->imm = operand_cimmswsp(inst);
4758         break;
4759     case rv_codec_css_sdsp:
4760         dec->rd = rv_ireg_zero;
4761         dec->rs1 = rv_ireg_sp;
4762         dec->rs2 = operand_crs2(inst);
4763         dec->imm = operand_cimmsdsp(inst);
4764         break;
4765     case rv_codec_css_sqsp:
4766         dec->rd = rv_ireg_zero;
4767         dec->rs1 = rv_ireg_sp;
4768         dec->rs2 = operand_crs2(inst);
4769         dec->imm = operand_cimmsqsp(inst);
4770         break;
4771     case rv_codec_k_bs:
4772         dec->rs1 = operand_rs1(inst);
4773         dec->rs2 = operand_rs2(inst);
4774         dec->bs = operand_bs(inst);
4775         break;
4776     case rv_codec_k_rnum:
4777         dec->rd = operand_rd(inst);
4778         dec->rs1 = operand_rs1(inst);
4779         dec->rnum = operand_rnum(inst);
4780         break;
4781     case rv_codec_v_r:
4782         dec->rd = operand_rd(inst);
4783         dec->rs1 = operand_rs1(inst);
4784         dec->rs2 = operand_rs2(inst);
4785         dec->vm = operand_vm(inst);
4786         break;
4787     case rv_codec_v_ldst:
4788         dec->rd = operand_rd(inst);
4789         dec->rs1 = operand_rs1(inst);
4790         dec->vm = operand_vm(inst);
4791         break;
4792     case rv_codec_v_i:
4793         dec->rd = operand_rd(inst);
4794         dec->rs2 = operand_rs2(inst);
4795         dec->imm = operand_vimm(inst);
4796         dec->vm = operand_vm(inst);
4797         break;
4798     case rv_codec_vror_vi:
4799         dec->rd = operand_rd(inst);
4800         dec->rs2 = operand_rs2(inst);
4801         dec->imm = operand_vzimm6(inst);
4802         dec->vm = operand_vm(inst);
4803         break;
4804     case rv_codec_vsetvli:
4805         dec->rd = operand_rd(inst);
4806         dec->rs1 = operand_rs1(inst);
4807         dec->vzimm = operand_vzimm11(inst);
4808         break;
4809     case rv_codec_vsetivli:
4810         dec->rd = operand_rd(inst);
4811         dec->imm = operand_vimm(inst);
4812         dec->vzimm = operand_vzimm10(inst);
4813         break;
4814     case rv_codec_zcb_lb:
4815         dec->rs1 = operand_crs1q(inst) + 8;
4816         dec->rs2 = operand_crs2q(inst) + 8;
4817         dec->imm = operand_uimm_c_lb(inst);
4818         break;
4819     case rv_codec_zcb_lh:
4820         dec->rs1 = operand_crs1q(inst) + 8;
4821         dec->rs2 = operand_crs2q(inst) + 8;
4822         dec->imm = operand_uimm_c_lh(inst);
4823         break;
4824     case rv_codec_zcb_ext:
4825         dec->rd = operand_crs1q(inst) + 8;
4826         break;
4827     case rv_codec_zcb_mul:
4828         dec->rd = operand_crs1rdq(inst) + 8;
4829         dec->rs2 = operand_crs2q(inst) + 8;
4830         break;
4831     case rv_codec_zcmp_cm_pushpop:
4832         dec->imm = operand_zcmp_stack_adj(inst, isa);
4833         dec->rlist = operand_zcmp_rlist(inst);
4834         break;
4835     case rv_codec_zcmp_cm_mv:
4836         dec->rd = operand_sreg1(inst);
4837         dec->rs2 = operand_sreg2(inst);
4838         break;
4839     case rv_codec_zcmt_jt:
4840         dec->imm = operand_tbl_index(inst);
4841         break;
4842     case rv_codec_fli:
4843         dec->rd = operand_rd(inst);
4844         dec->imm = operand_rs1(inst);
4845         break;
4846     case rv_codec_r2_imm5:
4847         dec->rd = operand_rd(inst);
4848         dec->rs1 = operand_rs1(inst);
4849         dec->imm = operand_rs2(inst);
4850         break;
4851     case rv_codec_r2:
4852         dec->rd = operand_rd(inst);
4853         dec->rs1 = operand_rs1(inst);
4854         break;
4855     case rv_codec_r2_imm6:
4856         dec->rd = operand_rd(inst);
4857         dec->rs1 = operand_rs1(inst);
4858         dec->imm = operand_imm6(inst);
4859         break;
4860     case rv_codec_r_imm2:
4861         dec->rd = operand_rd(inst);
4862         dec->rs1 = operand_rs1(inst);
4863         dec->rs2 = operand_rs2(inst);
4864         dec->imm = operand_imm2(inst);
4865         break;
4866     case rv_codec_r2_immhl:
4867         dec->rd = operand_rd(inst);
4868         dec->rs1 = operand_rs1(inst);
4869         dec->imm = operand_immh(inst);
4870         dec->imm1 = operand_imml(inst);
4871         break;
4872     case rv_codec_r2_imm2_imm5:
4873         dec->rd = operand_rd(inst);
4874         dec->rs1 = operand_rs1(inst);
4875         dec->imm = sextract32(operand_rs2(inst), 0, 5);
4876         dec->imm1 = operand_imm2(inst);
4877         break;
4878     };
4879 }
4880 
4881 /* check constraint */
4882 
4883 static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
4884 {
4885     int32_t imm = dec->imm;
4886     uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2;
4887     while (*c != rvc_end) {
4888         switch (*c) {
4889         case rvc_rd_eq_ra:
4890             if (!(rd == 1)) {
4891                 return false;
4892             }
4893             break;
4894         case rvc_rd_eq_x0:
4895             if (!(rd == 0)) {
4896                 return false;
4897             }
4898             break;
4899         case rvc_rs1_eq_x0:
4900             if (!(rs1 == 0)) {
4901                 return false;
4902             }
4903             break;
4904         case rvc_rs2_eq_x0:
4905             if (!(rs2 == 0)) {
4906                 return false;
4907             }
4908             break;
4909         case rvc_rs2_eq_rs1:
4910             if (!(rs2 == rs1)) {
4911                 return false;
4912             }
4913             break;
4914         case rvc_rs1_eq_ra:
4915             if (!(rs1 == 1)) {
4916                 return false;
4917             }
4918             break;
4919         case rvc_imm_eq_zero:
4920             if (!(imm == 0)) {
4921                 return false;
4922             }
4923             break;
4924         case rvc_imm_eq_n1:
4925             if (!(imm == -1)) {
4926                 return false;
4927             }
4928             break;
4929         case rvc_imm_eq_p1:
4930             if (!(imm == 1)) {
4931                 return false;
4932             }
4933             break;
4934         case rvc_csr_eq_0x001:
4935             if (!(imm == 0x001)) {
4936                 return false;
4937             }
4938             break;
4939         case rvc_csr_eq_0x002:
4940             if (!(imm == 0x002)) {
4941                 return false;
4942             }
4943             break;
4944         case rvc_csr_eq_0x003:
4945             if (!(imm == 0x003)) {
4946                 return false;
4947             }
4948             break;
4949         case rvc_csr_eq_0xc00:
4950             if (!(imm == 0xc00)) {
4951                 return false;
4952             }
4953             break;
4954         case rvc_csr_eq_0xc01:
4955             if (!(imm == 0xc01)) {
4956                 return false;
4957             }
4958             break;
4959         case rvc_csr_eq_0xc02:
4960             if (!(imm == 0xc02)) {
4961                 return false;
4962             }
4963             break;
4964         case rvc_csr_eq_0xc80:
4965             if (!(imm == 0xc80)) {
4966                 return false;
4967             }
4968             break;
4969         case rvc_csr_eq_0xc81:
4970             if (!(imm == 0xc81)) {
4971                 return false;
4972             }
4973             break;
4974         case rvc_csr_eq_0xc82:
4975             if (!(imm == 0xc82)) {
4976                 return false;
4977             }
4978             break;
4979         default: break;
4980         }
4981         c++;
4982     }
4983     return true;
4984 }
4985 
4986 /* instruction length */
4987 
4988 static size_t inst_length(rv_inst inst)
4989 {
4990     /* NOTE: supports maximum instruction size of 64-bits */
4991 
4992     /*
4993      * instruction length coding
4994      *
4995      *      aa - 16 bit aa != 11
4996      *   bbb11 - 32 bit bbb != 111
4997      *  011111 - 48 bit
4998      * 0111111 - 64 bit
4999      */
5000 
5001     return (inst &      0b11) != 0b11      ? 2
5002          : (inst &   0b11100) != 0b11100   ? 4
5003          : (inst &  0b111111) == 0b011111  ? 6
5004          : (inst & 0b1111111) == 0b0111111 ? 8
5005          : 0;
5006 }
5007 
5008 /* format instruction */
5009 
5010 static GString *format_inst(size_t tab, rv_decode *dec)
5011 {
5012     const rv_opcode_data *opcode_data = dec->opcode_data;
5013     GString *buf = g_string_sized_new(64);
5014     const char *fmt;
5015 
5016     fmt = opcode_data[dec->op].format;
5017     while (*fmt) {
5018         switch (*fmt) {
5019         case 'O':
5020             g_string_append(buf, opcode_data[dec->op].name);
5021             break;
5022         case '(':
5023         case ',':
5024         case ')':
5025         case '-':
5026             g_string_append_c(buf, *fmt);
5027             break;
5028         case 'b':
5029             g_string_append_printf(buf, "%d", dec->bs);
5030             break;
5031         case 'n':
5032             g_string_append_printf(buf, "%d", dec->rnum);
5033             break;
5034         case '0':
5035             g_string_append(buf, rv_ireg_name_sym[dec->rd]);
5036             break;
5037         case '1':
5038             g_string_append(buf, rv_ireg_name_sym[dec->rs1]);
5039             break;
5040         case '2':
5041             g_string_append(buf, rv_ireg_name_sym[dec->rs2]);
5042             break;
5043         case '3':
5044             if (dec->cfg->ext_zfinx) {
5045                 g_string_append(buf, rv_ireg_name_sym[dec->rd]);
5046             } else {
5047                 g_string_append(buf, rv_freg_name_sym[dec->rd]);
5048             }
5049             break;
5050         case '4':
5051             if (dec->cfg->ext_zfinx) {
5052                 g_string_append(buf, rv_ireg_name_sym[dec->rs1]);
5053             } else {
5054                 g_string_append(buf, rv_freg_name_sym[dec->rs1]);
5055             }
5056             break;
5057         case '5':
5058             if (dec->cfg->ext_zfinx) {
5059                 g_string_append(buf, rv_ireg_name_sym[dec->rs2]);
5060             } else {
5061                 g_string_append(buf, rv_freg_name_sym[dec->rs2]);
5062             }
5063             break;
5064         case '6':
5065             if (dec->cfg->ext_zfinx) {
5066                 g_string_append(buf, rv_ireg_name_sym[dec->rs3]);
5067             } else {
5068                 g_string_append(buf, rv_freg_name_sym[dec->rs3]);
5069             }
5070             break;
5071         case '7':
5072             g_string_append_printf(buf, "%d", dec->rs1);
5073             break;
5074         case 'i':
5075             g_string_append_printf(buf, "%d", dec->imm);
5076             break;
5077         case 'u':
5078             g_string_append_printf(buf, "%u", ((uint32_t)dec->imm & 0b111111));
5079             break;
5080         case 'j':
5081             g_string_append_printf(buf, "%d", dec->imm1);
5082             break;
5083         case 'o':
5084             g_string_append_printf(buf, "%d", dec->imm);
5085             while (buf->len < tab * 2) {
5086                 g_string_append_c(buf, ' ');
5087             }
5088             g_string_append_printf(buf, "# 0x%" PRIx64, dec->pc + dec->imm);
5089             break;
5090         case 'U':
5091             fmt++;
5092             g_string_append_printf(buf, "%d", dec->imm >> 12);
5093             if (*fmt == 'o') {
5094                 while (buf->len < tab * 2) {
5095                     g_string_append_c(buf, ' ');
5096                 }
5097                 g_string_append_printf(buf, "# 0x%" PRIx64, dec->pc + dec->imm);
5098             }
5099             break;
5100         case 'c': {
5101             const char *name = csr_name(dec->imm & 0xfff);
5102             if (name) {
5103                 g_string_append(buf, name);
5104             } else {
5105                 g_string_append_printf(buf, "0x%03x", dec->imm & 0xfff);
5106             }
5107             break;
5108         }
5109         case 'r':
5110             switch (dec->rm) {
5111             case rv_rm_rne:
5112                 g_string_append(buf, "rne");
5113                 break;
5114             case rv_rm_rtz:
5115                 g_string_append(buf, "rtz");
5116                 break;
5117             case rv_rm_rdn:
5118                 g_string_append(buf, "rdn");
5119                 break;
5120             case rv_rm_rup:
5121                 g_string_append(buf, "rup");
5122                 break;
5123             case rv_rm_rmm:
5124                 g_string_append(buf, "rmm");
5125                 break;
5126             case rv_rm_dyn:
5127                 g_string_append(buf, "dyn");
5128                 break;
5129             default:
5130                 g_string_append(buf, "inv");
5131                 break;
5132             }
5133             break;
5134         case 'p':
5135             if (dec->pred & rv_fence_i) {
5136                 g_string_append_c(buf, 'i');
5137             }
5138             if (dec->pred & rv_fence_o) {
5139                 g_string_append_c(buf, 'o');
5140             }
5141             if (dec->pred & rv_fence_r) {
5142                 g_string_append_c(buf, 'r');
5143             }
5144             if (dec->pred & rv_fence_w) {
5145                 g_string_append_c(buf, 'w');
5146             }
5147             break;
5148         case 's':
5149             if (dec->succ & rv_fence_i) {
5150                 g_string_append_c(buf, 'i');
5151             }
5152             if (dec->succ & rv_fence_o) {
5153                 g_string_append_c(buf, 'o');
5154             }
5155             if (dec->succ & rv_fence_r) {
5156                 g_string_append_c(buf, 'r');
5157             }
5158             if (dec->succ & rv_fence_w) {
5159                 g_string_append_c(buf, 'w');
5160             }
5161             break;
5162         case '\t':
5163             while (buf->len < tab) {
5164                 g_string_append_c(buf, ' ');
5165             }
5166             break;
5167         case 'A':
5168             if (dec->aq) {
5169                 g_string_append(buf, ".aq");
5170             }
5171             break;
5172         case 'R':
5173             if (dec->rl) {
5174                 g_string_append(buf, ".rl");
5175             }
5176             break;
5177         case 'l':
5178             g_string_append(buf, ",v0");
5179             break;
5180         case 'm':
5181             if (dec->vm == 0) {
5182                 g_string_append(buf, ",v0.t");
5183             }
5184             break;
5185         case 'D':
5186             g_string_append(buf, rv_vreg_name_sym[dec->rd]);
5187             break;
5188         case 'E':
5189             g_string_append(buf, rv_vreg_name_sym[dec->rs1]);
5190             break;
5191         case 'F':
5192             g_string_append(buf, rv_vreg_name_sym[dec->rs2]);
5193             break;
5194         case 'G':
5195             g_string_append(buf, rv_vreg_name_sym[dec->rs3]);
5196             break;
5197         case 'v': {
5198             const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3);
5199             const int lmul = dec->vzimm & 0b11;
5200             const int flmul = (dec->vzimm >> 2) & 1;
5201             const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu";
5202             const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu";
5203 
5204             g_string_append_printf(buf, "e%d,m", sew);
5205             if (flmul) {
5206                 switch (lmul) {
5207                 case 3:
5208                     g_string_append(buf, "f2");
5209                     break;
5210                 case 2:
5211                     g_string_append(buf, "f4");
5212                     break;
5213                 case 1:
5214                     g_string_append(buf, "f8");
5215                     break;
5216                 }
5217             } else {
5218                 g_string_append_printf(buf, "%d", 1 << lmul);
5219             }
5220             g_string_append_c(buf, ',');
5221             g_string_append(buf, vta);
5222             g_string_append_c(buf, ',');
5223             g_string_append(buf, vma);
5224             break;
5225         }
5226         case 'x': {
5227             switch (dec->rlist) {
5228             case 4:
5229                 g_string_append(buf, "{ra}");
5230                 break;
5231             case 5:
5232                 g_string_append(buf, "{ra, s0}");
5233                 break;
5234             case 15:
5235                 g_string_append(buf, "{ra, s0-s11}");
5236                 break;
5237             default:
5238                 g_string_append_printf(buf, "{ra, s0-s%d}", dec->rlist - 5);
5239                 break;
5240             }
5241             break;
5242         }
5243         case 'h':
5244             g_string_append(buf, rv_fli_name_const[dec->imm]);
5245             break;
5246         default:
5247             break;
5248         }
5249         fmt++;
5250     }
5251 
5252     return buf;
5253 }
5254 
5255 /* lift instruction to pseudo-instruction */
5256 
5257 static void decode_inst_lift_pseudo(rv_decode *dec)
5258 {
5259     const rv_opcode_data *opcode_data = dec->opcode_data;
5260     const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;
5261     if (!comp_data) {
5262         return;
5263     }
5264     while (comp_data->constraints) {
5265         if (check_constraints(dec, comp_data->constraints)) {
5266             dec->op = comp_data->op;
5267             dec->codec = opcode_data[dec->op].codec;
5268             return;
5269         }
5270         comp_data++;
5271     }
5272 }
5273 
5274 /* decompress instruction */
5275 
5276 static void decode_inst_decompress_rv32(rv_decode *dec)
5277 {
5278     const rv_opcode_data *opcode_data = dec->opcode_data;
5279     int decomp_op = opcode_data[dec->op].decomp_rv32;
5280     if (decomp_op != rv_op_illegal) {
5281         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
5282             && dec->imm == 0) {
5283             dec->op = rv_op_illegal;
5284         } else {
5285             dec->op = decomp_op;
5286             dec->codec = opcode_data[decomp_op].codec;
5287         }
5288     }
5289 }
5290 
5291 static void decode_inst_decompress_rv64(rv_decode *dec)
5292 {
5293     const rv_opcode_data *opcode_data = dec->opcode_data;
5294     int decomp_op = opcode_data[dec->op].decomp_rv64;
5295     if (decomp_op != rv_op_illegal) {
5296         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
5297             && dec->imm == 0) {
5298             dec->op = rv_op_illegal;
5299         } else {
5300             dec->op = decomp_op;
5301             dec->codec = opcode_data[decomp_op].codec;
5302         }
5303     }
5304 }
5305 
5306 static void decode_inst_decompress_rv128(rv_decode *dec)
5307 {
5308     const rv_opcode_data *opcode_data = dec->opcode_data;
5309     int decomp_op = opcode_data[dec->op].decomp_rv128;
5310     if (decomp_op != rv_op_illegal) {
5311         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
5312             && dec->imm == 0) {
5313             dec->op = rv_op_illegal;
5314         } else {
5315             dec->op = decomp_op;
5316             dec->codec = opcode_data[decomp_op].codec;
5317         }
5318     }
5319 }
5320 
5321 static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
5322 {
5323     switch (isa) {
5324     case rv32:
5325         decode_inst_decompress_rv32(dec);
5326         break;
5327     case rv64:
5328         decode_inst_decompress_rv64(dec);
5329         break;
5330     case rv128:
5331         decode_inst_decompress_rv128(dec);
5332         break;
5333     }
5334 }
5335 
5336 /* disassemble instruction */
5337 
5338 static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,
5339                             RISCVCPUConfig *cfg)
5340 {
5341     rv_decode dec = { 0 };
5342     dec.pc = pc;
5343     dec.inst = inst;
5344     dec.cfg = cfg;
5345 
5346     static const struct {
5347         bool (*guard_func)(const RISCVCPUConfig *);
5348         const rv_opcode_data *opcode_data;
5349         void (*decode_func)(rv_decode *, rv_isa);
5350     } decoders[] = {
5351         { always_true_p, rvi_opcode_data, decode_inst_opcode },
5352         { has_xtheadba_p, xthead_opcode_data, decode_xtheadba },
5353         { has_xtheadbb_p, xthead_opcode_data, decode_xtheadbb },
5354         { has_xtheadbs_p, xthead_opcode_data, decode_xtheadbs },
5355         { has_xtheadcmo_p, xthead_opcode_data, decode_xtheadcmo },
5356         { has_xtheadcondmov_p, xthead_opcode_data, decode_xtheadcondmov },
5357         { has_xtheadfmemidx_p, xthead_opcode_data, decode_xtheadfmemidx },
5358         { has_xtheadfmv_p, xthead_opcode_data, decode_xtheadfmv },
5359         { has_xtheadmac_p, xthead_opcode_data, decode_xtheadmac },
5360         { has_xtheadmemidx_p, xthead_opcode_data, decode_xtheadmemidx },
5361         { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },
5362         { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },
5363         { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },
5364     };
5365 
5366     for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {
5367         bool (*guard_func)(const RISCVCPUConfig *) = decoders[i].guard_func;
5368         const rv_opcode_data *opcode_data = decoders[i].opcode_data;
5369         void (*decode_func)(rv_decode *, rv_isa) = decoders[i].decode_func;
5370 
5371         if (guard_func(cfg)) {
5372             dec.opcode_data = opcode_data;
5373             decode_func(&dec, isa);
5374             if (dec.op != rv_op_illegal)
5375                 break;
5376         }
5377     }
5378 
5379     if (dec.op == rv_op_illegal) {
5380         dec.opcode_data = rvi_opcode_data;
5381     }
5382 
5383     decode_inst_operands(&dec, isa);
5384     decode_inst_decompress(&dec, isa);
5385     decode_inst_lift_pseudo(&dec);
5386     return format_inst(24, &dec);
5387 }
5388 
5389 #define INST_FMT_2 "%04" PRIx64 "              "
5390 #define INST_FMT_4 "%08" PRIx64 "          "
5391 #define INST_FMT_6 "%012" PRIx64 "      "
5392 #define INST_FMT_8 "%016" PRIx64 "  "
5393 
5394 static int
5395 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
5396 {
5397     bfd_byte packet[2];
5398     rv_inst inst = 0;
5399     size_t len = 2;
5400     bfd_vma n;
5401     int status;
5402 
5403     /* Instructions are made of 2-byte packets in little-endian order */
5404     for (n = 0; n < len; n += 2) {
5405         status = (*info->read_memory_func)(memaddr + n, packet, 2, info);
5406         if (status != 0) {
5407             /* Don't fail just because we fell off the end.  */
5408             if (n > 0) {
5409                 break;
5410             }
5411             (*info->memory_error_func)(status, memaddr, info);
5412             return status;
5413         }
5414         inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n);
5415         if (n == 0) {
5416             len = inst_length(inst);
5417         }
5418     }
5419 
5420     if (info->show_opcodes) {
5421         switch (len) {
5422         case 2:
5423             (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
5424             break;
5425         case 4:
5426             (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
5427             break;
5428         case 6:
5429             (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
5430             break;
5431         default:
5432             (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
5433             break;
5434         }
5435     }
5436 
5437     g_autoptr(GString) str =
5438         disasm_inst(isa, memaddr, inst, (RISCVCPUConfig *)info->target_info);
5439     (*info->fprintf_func)(info->stream, "%s", str->str);
5440 
5441     return len;
5442 }
5443 
5444 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info)
5445 {
5446     return print_insn_riscv(memaddr, info, rv32);
5447 }
5448 
5449 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info)
5450 {
5451     return print_insn_riscv(memaddr, info, rv64);
5452 }
5453 
5454 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info)
5455 {
5456     return print_insn_riscv(memaddr, info, rv128);
5457 }
5458