xref: /openbmc/qemu/disas/nanomips.c (revision 75ac231c) 
1 /*
2  *  Source file for nanoMIPS disassembler component of QEMU
3  *
4  *  Copyright (C) 2018  Wave Computing, Inc.
5  *  Copyright (C) 2018  Matthew Fortune <matthew.fortune@mips.com>
6  *  Copyright (C) 2018  Aleksandar Markovic <amarkovic@wavecomp.com>
7  *
8  *  This program is free software: you can redistribute it and/or modify
9  *  it under the terms of the GNU General Public License as published by
10  *  the Free Software Foundation, either version 2 of the License, or
11  *  (at your option) any later version.
12  *
13  *  This program is distributed in the hope that it will be useful,
14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *  GNU General Public License for more details.
17  *
18  *  You should have received a copy of the GNU General Public License
19  *  along with this program.  If not, see <https://www.gnu.org/licenses/>.
20  *
21  */
22 
23 /*
24  *  Documentation used while implementing this component:
25  *
26  *  [1] "MIPS® Architecture Base: nanoMIPS32(tm) Instruction Set Technical
27  *      Reference Manual", Revision 01.01, April 27, 2018
28  */
29 
30 #include "qemu/osdep.h"
31 #include "disas/dis-asm.h"
32 
33 #include <string.h>
34 #include <stdio.h>
35 #include <stdarg.h>
36 
37 typedef int64_t int64;
38 typedef uint64_t uint64;
39 typedef uint32_t uint32;
40 typedef uint16_t uint16;
41 typedef uint64_t img_address;
42 
43 typedef enum  {
44     instruction,
45     call_instruction,
46     branch_instruction,
47     return_instruction,
48     reserved_block,
49     pool,
50 } TABLE_ENTRY_TYPE;
51 
52 typedef enum {
53     MIPS64_    = 0x00000001,
54     XNP_       = 0x00000002,
55     XMMS_      = 0x00000004,
56     EVA_       = 0x00000008,
57     DSP_       = 0x00000010,
58     MT_        = 0x00000020,
59     EJTAG_     = 0x00000040,
60     TLBINV_    = 0x00000080,
61     CP0_       = 0x00000100,
62     CP1_       = 0x00000200,
63     CP2_       = 0x00000400,
64     UDI_       = 0x00000800,
65     MCU_       = 0x00001000,
66     VZ_        = 0x00002000,
67     TLB_       = 0x00004000,
68     MVH_       = 0x00008000,
69     ALL_ATTRIBUTES = 0xffffffffull,
70 } TABLE_ATTRIBUTE_TYPE;
71 
72 typedef struct Dis_info {
73   img_address m_pc;
74   fprintf_function fprintf_func;
75   FILE *stream;
76   sigjmp_buf buf;
77 } Dis_info;
78 
79 typedef bool (*conditional_function)(uint64 instruction);
80 typedef char * (*disassembly_function)(uint64 instruction,
81                                             Dis_info *info);
82 
83 typedef struct Pool {
84     TABLE_ENTRY_TYPE     type;
85     const struct Pool    *next_table;
86     int                  next_table_size;
87     int                  instructions_size;
88     uint64               mask;
89     uint64               value;
90     disassembly_function disassembly;
91     conditional_function condition;
92     uint64               attributes;
93 } Pool;
94 
95 #define IMGASSERTONCE(test)
96 
97 
98 static char *img_format(const char *format, ...)
99 {
100     char *buffer;
101     va_list args;
102     va_start(args, format);
103     buffer = g_strdup_vprintf(format, args);
104     va_end(args);
105     return buffer;
106 }
107 
108 
109 static char *to_string(img_address a)
110 {
111     return g_strdup_printf("0x%" PRIx64, a);
112 }
113 
114 
115 static uint64 extract_bits(uint64 data, uint32 bit_offset, uint32 bit_size)
116 {
117     return (data << (64 - (bit_size + bit_offset))) >> (64 - bit_size);
118 }
119 
120 
121 static int64 sign_extend(int64 data, int msb)
122 {
123     uint64 shift = 63 - msb;
124     return (data << shift) >> shift;
125 }
126 
127 
128 static uint64 renumber_registers(uint64 index, uint64 *register_list,
129                                size_t register_list_size, Dis_info *info)
130 {
131     if (index < register_list_size) {
132         return register_list[index];
133     }
134 
135     info->fprintf_func(info->stream, "Invalid register mapping index %" PRIu64
136                        ", size of list = %zu", index, register_list_size);
137     siglongjmp(info->buf, 1);
138 }
139 
140 
141 /*
142  * decode_gpr_gpr4() - decoder for 'gpr4' gpr encoding type
143  *
144  *   Map a 4-bit code to the 5-bit register space according to this pattern:
145  *
146  *                              1                   0
147  *                    5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
148  *                    | | | | | | | | | | | | | | | |
149  *                    | | | | | | | | | | | | | | | |
150  *                    | | | | | | | | | | | └---------------┐
151  *                    | | | | | | | | | | └---------------┐ |
152  *                    | | | | | | | | | └---------------┐ | |
153  *                    | | | | | | | | └---------------┐ | | |
154  *                    | | | | | | | |         | | | | | | | |
155  *                    | | | | | | | |         | | | | | | | |
156  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
157  *      3                   2                   1                   0
158  *
159  *   Used in handling following instructions:
160  *
161  *     - ADDU[4X4]
162  *     - LW[4X4]
163  *     - MOVEP[REV]
164  *     - MUL[4X4]
165  *     - SW[4X4]
166  */
167 static uint64 decode_gpr_gpr4(uint64 d, Dis_info *info)
168 {
169     static uint64 register_list[] = {  8,  9, 10, 11,  4,  5,  6,  7,
170                                       16, 17, 18, 19, 20, 21, 22, 23 };
171     return renumber_registers(d, register_list,
172                sizeof(register_list) / sizeof(register_list[0]), info);
173 }
174 
175 
176 /*
177  * decode_gpr_gpr4_zero() - decoder for 'gpr4.zero' gpr encoding type
178  *
179  *   Map a 4-bit code to the 5-bit register space according to this pattern:
180  *
181  *                              1                   0
182  *                    5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
183  *                    | | | | | | | | | | | | | | | |
184  *                    | | | | | | | | | | | | └---------------------┐
185  *                    | | | | | | | | | | | └---------------┐       |
186  *                    | | | | | | | | | | └---------------┐ |       |
187  *                    | | | | | | | | | └---------------┐ | |       |
188  *                    | | | | | | | | └---------------┐ | | |       |
189  *                    | | | | | | | |           | | | | | | |       |
190  *                    | | | | | | | |           | | | | | | |       |
191  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
192  *      3                   2                   1                   0
193  *
194  *   This pattern is the same one used for 'gpr4' gpr encoding type, except for
195  * the input value 3, that is mapped to the output value 0 instead of 11.
196  *
197  *   Used in handling following instructions:
198  *
199  *     - MOVE.BALC
200  *     - MOVEP
201  *     - SW[4X4]
202  */
203 static uint64 decode_gpr_gpr4_zero(uint64 d, Dis_info *info)
204 {
205     static uint64 register_list[] = {  8,  9, 10,  0,  4,  5,  6,  7,
206                                       16, 17, 18, 19, 20, 21, 22, 23 };
207     return renumber_registers(d, register_list,
208                sizeof(register_list) / sizeof(register_list[0]), info);
209 }
210 
211 
212 /*
213  * decode_gpr_gpr3() - decoder for 'gpr3' gpr encoding type
214  *
215  *   Map a 3-bit code to the 5-bit register space according to this pattern:
216  *
217  *                            7 6 5 4 3 2 1 0
218  *                            | | | | | | | |
219  *                            | | | | | | | |
220  *                            | | | └-----------------------┐
221  *                            | | └-----------------------┐ |
222  *                            | └-----------------------┐ | |
223  *                            └-----------------------┐ | | |
224  *                                    | | | |         | | | |
225  *                            ┌-------┘ | | |         | | | |
226  *                            | ┌-------┘ | |         | | | |
227  *                            | | ┌-------┘ |         | | | |
228  *                            | | | ┌-------┘         | | | |
229  *                            | | | |                 | | | |
230  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
231  *      3                   2                   1                   0
232  *
233  *   Used in handling following instructions:
234  *
235  *     - ADDIU[R1.SP]
236  *     - ADDIU[R2]
237  *     - ADDU[16]
238  *     - AND[16]
239  *     - ANDI[16]
240  *     - BEQC[16]
241  *     - BEQZC[16]
242  *     - BNEC[16]
243  *     - BNEZC[16]
244  *     - LB[16]
245  *     - LBU[16]
246  *     - LH[16]
247  *     - LHU[16]
248  *     - LI[16]
249  *     - LW[16]
250  *     - LW[GP16]
251  *     - LWXS[16]
252  *     - NOT[16]
253  *     - OR[16]
254  *     - SB[16]
255  *     - SH[16]
256  *     - SLL[16]
257  *     - SRL[16]
258  *     - SUBU[16]
259  *     - SW[16]
260  *     - XOR[16]
261  */
262 static uint64 decode_gpr_gpr3(uint64 d, Dis_info *info)
263 {
264     static uint64 register_list[] = { 16, 17, 18, 19,  4,  5,  6,  7 };
265     return renumber_registers(d, register_list,
266                sizeof(register_list) / sizeof(register_list[0]), info);
267 }
268 
269 
270 /*
271  * decode_gpr_gpr3_src_store() - decoder for 'gpr3.src.store' gpr encoding
272  *     type
273  *
274  *   Map a 3-bit code to the 5-bit register space according to this pattern:
275  *
276  *                            7 6 5 4 3 2 1 0
277  *                            | | | | | | | |
278  *                            | | | | | | | └-----------------------┐
279  *                            | | | └-----------------------┐       |
280  *                            | | └-----------------------┐ |       |
281  *                            | └-----------------------┐ | |       |
282  *                            └-----------------------┐ | | |       |
283  *                                    | | |           | | | |       |
284  *                            ┌-------┘ | |           | | | |       |
285  *                            | ┌-------┘ |           | | | |       |
286  *                            | | ┌-------┘           | | | |       |
287  *                            | | |                   | | | |       |
288  *                            | | |                   | | | |       |
289  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
290  *      3                   2                   1                   0
291  *
292  *   This pattern is the same one used for 'gpr3' gpr encoding type, except for
293  * the input value 0, that is mapped to the output value 0 instead of 16.
294  *
295  *   Used in handling following instructions:
296  *
297  *     - SB[16]
298  *     - SH[16]
299  *     - SW[16]
300  *     - SW[GP16]
301  */
302 static uint64 decode_gpr_gpr3_src_store(uint64 d, Dis_info *info)
303 {
304     static uint64 register_list[] = {  0, 17, 18, 19,  4,  5,  6,  7 };
305     return renumber_registers(d, register_list,
306                sizeof(register_list) / sizeof(register_list[0]), info);
307 }
308 
309 
310 /*
311  * decode_gpr_gpr2_reg1() - decoder for 'gpr2.reg1' gpr encoding type
312  *
313  *   Map a 2-bit code to the 5-bit register space according to this pattern:
314  *
315  *                                3 2 1 0
316  *                                | | | |
317  *                                | | | |
318  *                                | | | └-------------------┐
319  *                                | | └-------------------┐ |
320  *                                | └-------------------┐ | |
321  *                                └-------------------┐ | | |
322  *                                                    | | | |
323  *                                                    | | | |
324  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
325  *      3                   2                   1                   0
326  *
327  *   Used in handling following instructions:
328  *
329  *     - MOVEP
330  *     - MOVEP[REV]
331  */
332 static uint64 decode_gpr_gpr2_reg1(uint64 d, Dis_info *info)
333 {
334     static uint64 register_list[] = {  4,  5,  6,  7 };
335     return renumber_registers(d, register_list,
336                sizeof(register_list) / sizeof(register_list[0]), info);
337 }
338 
339 
340 /*
341  * decode_gpr_gpr2_reg2() - decoder for 'gpr2.reg2' gpr encoding type
342  *
343  *   Map a 2-bit code to the 5-bit register space according to this pattern:
344  *
345  *                                3 2 1 0
346  *                                | | | |
347  *                                | | | |
348  *                                | | | └-----------------┐
349  *                                | | └-----------------┐ |
350  *                                | └-----------------┐ | |
351  *                                └-----------------┐ | | |
352  *                                                  | | | |
353  *                                                  | | | |
354  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
355  *      3                   2                   1                   0
356  *
357  *   Used in handling following instructions:
358  *
359  *     - MOVEP
360  *     - MOVEP[REV]
361  */
362 static uint64 decode_gpr_gpr2_reg2(uint64 d, Dis_info *info)
363 {
364     static uint64 register_list[] = {  5,  6,  7,  8 };
365     return renumber_registers(d, register_list,
366                sizeof(register_list) / sizeof(register_list[0]), info);
367 }
368 
369 
370 /*
371  * decode_gpr_gpr1() - decoder for 'gpr1' gpr encoding type
372  *
373  *   Map a 1-bit code to the 5-bit register space according to this pattern:
374  *
375  *                                  1 0
376  *                                  | |
377  *                                  | |
378  *                                  | └---------------------┐
379  *                                  └---------------------┐ |
380  *                                                        | |
381  *                                                        | |
382  *                                                        | |
383  *                                                        | |
384  *    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
385  *      3                   2                   1                   0
386  *
387  *   Used in handling following instruction:
388  *
389  *     - MOVE.BALC
390  */
391 static uint64 decode_gpr_gpr1(uint64 d, Dis_info *info)
392 {
393     static uint64 register_list[] = {  4,  5 };
394     return renumber_registers(d, register_list,
395                sizeof(register_list) / sizeof(register_list[0]), info);
396 }
397 
398 
399 static int64 neg_copy(uint64 d)
400 {
401     return 0ll - d;
402 }
403 
404 
405 static uint64 encode_count3_from_count(uint64 d)
406 {
407     IMGASSERTONCE(d < 8);
408     return d == 0ull ? 8ull : d;
409 }
410 
411 
412 static uint64 encode_shift3_from_shift(uint64 d)
413 {
414     IMGASSERTONCE(d < 8);
415     return d == 0ull ? 8ull : d;
416 }
417 
418 
419 /* special value for load literal */
420 static int64 encode_eu_from_s_li16(uint64 d)
421 {
422     IMGASSERTONCE(d < 128);
423     return d == 127 ? -1 : (int64)d;
424 }
425 
426 
427 static uint64 encode_msbd_from_size(uint64 d)
428 {
429     IMGASSERTONCE(d < 32);
430     return d + 1;
431 }
432 
433 
434 static uint64 encode_eu_from_u_andi16(uint64 d)
435 {
436     IMGASSERTONCE(d < 16);
437     if (d == 12) {
438         return 0x00ffull;
439     }
440     if (d == 13) {
441         return 0xffffull;
442     }
443     return d;
444 }
445 
446 
447 /* save16 / restore16   ???? */
448 static uint64 encode_rt1_from_rt(uint64 d)
449 {
450     return d ? 31 : 30;
451 }
452 
453 
454 static const char *GPR(uint64 reg, Dis_info *info)
455 {
456     static const char *gpr_reg[32] = {
457         "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
458         "a4",   "a5",   "a6",   "a7",   "r12",  "r13",  "r14",  "r15",
459         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
460         "r24",  "r25",  "k0",   "k1",   "gp",   "sp",   "fp",   "ra"
461     };
462 
463     if (reg < 32) {
464         return gpr_reg[reg];
465     }
466 
467     info->fprintf_func(info->stream, "Invalid GPR register index %" PRIu64,
468                        reg);
469     siglongjmp(info->buf, 1);
470 }
471 
472 
473 static char *save_restore_list(uint64 rt, uint64 count, uint64 gp,
474                                Dis_info *info)
475 {
476     char *reg_list[34];
477     reg_list[0] = (char *)"";
478 
479     assert(count <= 32);
480     for (uint64 counter = 0; counter != count; counter++) {
481         bool use_gp = gp && (counter == count - 1);
482         uint64 this_rt = use_gp ? 28 : ((rt & 0x10) | (rt + counter)) & 0x1f;
483         /* glib usage below requires casting away const */
484         reg_list[counter + 1] = (char *)GPR(this_rt, info);
485     }
486     reg_list[count + 1] = NULL;
487 
488     return g_strjoinv(",", reg_list);
489 }
490 
491 
492 static const char *FPR(uint64 reg, Dis_info *info)
493 {
494     static const char *fpr_reg[32] = {
495         "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
496         "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
497         "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
498         "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
499     };
500 
501     if (reg < 32) {
502         return fpr_reg[reg];
503     }
504 
505     info->fprintf_func(info->stream, "Invalid FPR register index %" PRIu64,
506                        reg);
507     siglongjmp(info->buf, 1);
508 }
509 
510 
511 static const char *AC(uint64 reg, Dis_info *info)
512 {
513     static const char *ac_reg[4] = {
514         "ac0",  "ac1",  "ac2",  "ac3"
515     };
516 
517     if (reg < 4) {
518         return ac_reg[reg];
519     }
520 
521     info->fprintf_func(info->stream, "Invalid AC register index %" PRIu64,
522                        reg);
523     siglongjmp(info->buf, 1);
524 }
525 
526 
527 static char *ADDRESS(uint64 value, int instruction_size, Dis_info *info)
528 {
529     /* token for string replace */
530     img_address address = info->m_pc + value + instruction_size;
531     /* symbol replacement */
532     return to_string(address);
533 }
534 
535 
536 static uint64 extract_op_code_value(const uint16 *data, int size)
537 {
538     switch (size) {
539     case 16:
540         return data[0];
541     case 32:
542         return ((uint64)data[0] << 16) | data[1];
543     case 48:
544         return ((uint64)data[0] << 32) | ((uint64)data[1] << 16) | data[2];
545     default:
546         return data[0];
547     }
548 }
549 
550 
551 /*
552  * Recurse through tables until the instruction is found then return
553  * the string and size
554  *
555  * inputs:
556  *      pointer to a word stream,
557  *      disassember table and size
558  * returns:
559  *      instruction size    - negative is error
560  *      disassembly string  - on error will constain error string
561  */
562 static int Disassemble(const uint16 *data, char **dis,
563                      TABLE_ENTRY_TYPE *type, const Pool *table,
564                      int table_size, Dis_info *info)
565 {
566     for (int i = 0; i < table_size; i++) {
567         uint64 op_code = extract_op_code_value(data,
568                              table[i].instructions_size);
569         if ((op_code & table[i].mask) == table[i].value) {
570             /* possible match */
571             conditional_function cond = table[i].condition;
572             if ((cond == NULL) || cond(op_code)) {
573                 if (table[i].type == pool) {
574                     return Disassemble(data, dis, type,
575                                        table[i].next_table,
576                                        table[i].next_table_size,
577                                        info);
578                 } else if ((table[i].type == instruction) ||
579                            (table[i].type == call_instruction) ||
580                            (table[i].type == branch_instruction) ||
581                            (table[i].type == return_instruction)) {
582                     disassembly_function dis_fn = table[i].disassembly;
583                     if (dis_fn == 0) {
584                         *dis = g_strdup(
585                             "disassembler failure - bad table entry");
586                         return -6;
587                     }
588                     *type = table[i].type;
589                     *dis = dis_fn(op_code, info);
590                     return table[i].instructions_size;
591                 } else {
592                     *dis = g_strdup("reserved instruction");
593                     return -2;
594                 }
595             }
596         }
597     }
598     *dis = g_strdup("failed to disassemble");
599     return -1;      /* failed to disassemble        */
600 }
601 
602 
603 static uint64 extract_code_18_to_0(uint64 instruction)
604 {
605     uint64 value = 0;
606     value |= extract_bits(instruction, 0, 19);
607     return value;
608 }
609 
610 
611 static uint64 extract_shift3_2_1_0(uint64 instruction)
612 {
613     uint64 value = 0;
614     value |= extract_bits(instruction, 0, 3);
615     return value;
616 }
617 
618 
619 static uint64 extract_u_11_10_9_8_7_6_5_4_3__s3(uint64 instruction)
620 {
621     uint64 value = 0;
622     value |= extract_bits(instruction, 3, 9) << 3;
623     return value;
624 }
625 
626 
627 static uint64 extract_count_3_2_1_0(uint64 instruction)
628 {
629     uint64 value = 0;
630     value |= extract_bits(instruction, 0, 4);
631     return value;
632 }
633 
634 
635 static uint64 extract_rtz3_9_8_7(uint64 instruction)
636 {
637     uint64 value = 0;
638     value |= extract_bits(instruction, 7, 3);
639     return value;
640 }
641 
642 
643 static uint64 extract_u_17_to_1__s1(uint64 instruction)
644 {
645     uint64 value = 0;
646     value |= extract_bits(instruction, 1, 17) << 1;
647     return value;
648 }
649 
650 
651 static int64 extract_s__se9_20_19_18_17_16_15_14_13_12_11(uint64 instruction)
652 {
653     int64 value = 0;
654     value |= extract_bits(instruction, 11, 10);
655     value = sign_extend(value, 9);
656     return value;
657 }
658 
659 
660 static int64 extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(uint64 instruction)
661 {
662     int64 value = 0;
663     value |= extract_bits(instruction, 0, 1) << 11;
664     value |= extract_bits(instruction, 1, 10) << 1;
665     value = sign_extend(value, 11);
666     return value;
667 }
668 
669 
670 static uint64 extract_u_10(uint64 instruction)
671 {
672     uint64 value = 0;
673     value |= extract_bits(instruction, 10, 1);
674     return value;
675 }
676 
677 
678 static uint64 extract_rtz4_27_26_25_23_22_21(uint64 instruction)
679 {
680     uint64 value = 0;
681     value |= extract_bits(instruction, 21, 3);
682     value |= extract_bits(instruction, 25, 1) << 3;
683     return value;
684 }
685 
686 
687 static uint64 extract_sa_15_14_13_12_11(uint64 instruction)
688 {
689     uint64 value = 0;
690     value |= extract_bits(instruction, 11, 5);
691     return value;
692 }
693 
694 
695 static uint64 extract_shift_4_3_2_1_0(uint64 instruction)
696 {
697     uint64 value = 0;
698     value |= extract_bits(instruction, 0, 5);
699     return value;
700 }
701 
702 
703 static uint64 extract_shiftx_10_9_8_7__s1(uint64 instruction)
704 {
705     uint64 value = 0;
706     value |= extract_bits(instruction, 7, 4) << 1;
707     return value;
708 }
709 
710 
711 static uint64 extract_hint_25_24_23_22_21(uint64 instruction)
712 {
713     uint64 value = 0;
714     value |= extract_bits(instruction, 21, 5);
715     return value;
716 }
717 
718 
719 static uint64 extract_count3_14_13_12(uint64 instruction)
720 {
721     uint64 value = 0;
722     value |= extract_bits(instruction, 12, 3);
723     return value;
724 }
725 
726 
727 static int64 extract_s__se31_0_11_to_2_20_to_12_s12(uint64 instruction)
728 {
729     int64 value = 0;
730     value |= extract_bits(instruction, 0, 1) << 31;
731     value |= extract_bits(instruction, 2, 10) << 21;
732     value |= extract_bits(instruction, 12, 9) << 12;
733     value = sign_extend(value, 31);
734     return value;
735 }
736 
737 
738 static int64 extract_s__se7_0_6_5_4_3_2_1_s1(uint64 instruction)
739 {
740     int64 value = 0;
741     value |= extract_bits(instruction, 0, 1) << 7;
742     value |= extract_bits(instruction, 1, 6) << 1;
743     value = sign_extend(value, 7);
744     return value;
745 }
746 
747 
748 static uint64 extract_u2_10_9(uint64 instruction)
749 {
750     uint64 value = 0;
751     value |= extract_bits(instruction, 9, 2);
752     return value;
753 }
754 
755 
756 static uint64 extract_code_25_24_23_22_21_20_19_18_17_16(uint64 instruction)
757 {
758     uint64 value = 0;
759     value |= extract_bits(instruction, 16, 10);
760     return value;
761 }
762 
763 
764 static uint64 extract_rs_20_19_18_17_16(uint64 instruction)
765 {
766     uint64 value = 0;
767     value |= extract_bits(instruction, 16, 5);
768     return value;
769 }
770 
771 
772 static uint64 extract_u_2_1__s1(uint64 instruction)
773 {
774     uint64 value = 0;
775     value |= extract_bits(instruction, 1, 2) << 1;
776     return value;
777 }
778 
779 
780 static uint64 extract_stripe_6(uint64 instruction)
781 {
782     uint64 value = 0;
783     value |= extract_bits(instruction, 6, 1);
784     return value;
785 }
786 
787 
788 static uint64 extract_ac_15_14(uint64 instruction)
789 {
790     uint64 value = 0;
791     value |= extract_bits(instruction, 14, 2);
792     return value;
793 }
794 
795 
796 static uint64 extract_shift_20_19_18_17_16(uint64 instruction)
797 {
798     uint64 value = 0;
799     value |= extract_bits(instruction, 16, 5);
800     return value;
801 }
802 
803 
804 static uint64 extract_rdl_25_24(uint64 instruction)
805 {
806     uint64 value = 0;
807     value |= extract_bits(instruction, 24, 1);
808     return value;
809 }
810 
811 
812 static int64 extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(uint64 instruction)
813 {
814     int64 value = 0;
815     value |= extract_bits(instruction, 0, 1) << 10;
816     value |= extract_bits(instruction, 1, 9) << 1;
817     value = sign_extend(value, 10);
818     return value;
819 }
820 
821 
822 static uint64 extract_eu_6_5_4_3_2_1_0(uint64 instruction)
823 {
824     uint64 value = 0;
825     value |= extract_bits(instruction, 0, 7);
826     return value;
827 }
828 
829 
830 static uint64 extract_shift_5_4_3_2_1_0(uint64 instruction)
831 {
832     uint64 value = 0;
833     value |= extract_bits(instruction, 0, 6);
834     return value;
835 }
836 
837 
838 static uint64 extract_count_19_18_17_16(uint64 instruction)
839 {
840     uint64 value = 0;
841     value |= extract_bits(instruction, 16, 4);
842     return value;
843 }
844 
845 
846 static uint64 extract_code_2_1_0(uint64 instruction)
847 {
848     uint64 value = 0;
849     value |= extract_bits(instruction, 0, 3);
850     return value;
851 }
852 
853 
854 static uint64 extract_u_11_10_9_8_7_6_5_4_3_2_1_0(uint64 instruction)
855 {
856     uint64 value = 0;
857     value |= extract_bits(instruction, 0, 12);
858     return value;
859 }
860 
861 
862 static uint64 extract_rs_4_3_2_1_0(uint64 instruction)
863 {
864     uint64 value = 0;
865     value |= extract_bits(instruction, 0, 5);
866     return value;
867 }
868 
869 
870 static uint64 extract_u_20_to_3__s3(uint64 instruction)
871 {
872     uint64 value = 0;
873     value |= extract_bits(instruction, 3, 18) << 3;
874     return value;
875 }
876 
877 
878 static uint64 extract_u_3_2_1_0__s2(uint64 instruction)
879 {
880     uint64 value = 0;
881     value |= extract_bits(instruction, 0, 4) << 2;
882     return value;
883 }
884 
885 
886 static uint64 extract_cofun_25_24_23(uint64 instruction)
887 {
888     uint64 value = 0;
889     value |= extract_bits(instruction, 3, 23);
890     return value;
891 }
892 
893 
894 static uint64 extract_u_2_1_0__s2(uint64 instruction)
895 {
896     uint64 value = 0;
897     value |= extract_bits(instruction, 0, 3) << 2;
898     return value;
899 }
900 
901 
902 static uint64 extract_rd3_3_2_1(uint64 instruction)
903 {
904     uint64 value = 0;
905     value |= extract_bits(instruction, 1, 3);
906     return value;
907 }
908 
909 
910 static uint64 extract_sa_15_14_13_12(uint64 instruction)
911 {
912     uint64 value = 0;
913     value |= extract_bits(instruction, 12, 4);
914     return value;
915 }
916 
917 
918 static uint64 extract_rt_25_24_23_22_21(uint64 instruction)
919 {
920     uint64 value = 0;
921     value |= extract_bits(instruction, 21, 5);
922     return value;
923 }
924 
925 
926 static uint64 extract_ru_7_6_5_4_3(uint64 instruction)
927 {
928     uint64 value = 0;
929     value |= extract_bits(instruction, 3, 5);
930     return value;
931 }
932 
933 
934 static uint64 extract_u_17_to_0(uint64 instruction)
935 {
936     uint64 value = 0;
937     value |= extract_bits(instruction, 0, 18);
938     return value;
939 }
940 
941 
942 static uint64 extract_rsz4_4_2_1_0(uint64 instruction)
943 {
944     uint64 value = 0;
945     value |= extract_bits(instruction, 0, 3);
946     value |= extract_bits(instruction, 4, 1) << 3;
947     return value;
948 }
949 
950 
951 static int64 extract_s__se21_0_20_to_1_s1(uint64 instruction)
952 {
953     int64 value = 0;
954     value |= extract_bits(instruction, 0, 1) << 21;
955     value |= extract_bits(instruction, 1, 20) << 1;
956     value = sign_extend(value, 21);
957     return value;
958 }
959 
960 
961 static uint64 extract_op_25_to_3(uint64 instruction)
962 {
963     uint64 value = 0;
964     value |= extract_bits(instruction, 3, 23);
965     return value;
966 }
967 
968 
969 static uint64 extract_rs4_4_2_1_0(uint64 instruction)
970 {
971     uint64 value = 0;
972     value |= extract_bits(instruction, 0, 3);
973     value |= extract_bits(instruction, 4, 1) << 3;
974     return value;
975 }
976 
977 
978 static uint64 extract_bit_23_22_21(uint64 instruction)
979 {
980     uint64 value = 0;
981     value |= extract_bits(instruction, 21, 3);
982     return value;
983 }
984 
985 
986 static uint64 extract_rt_41_40_39_38_37(uint64 instruction)
987 {
988     uint64 value = 0;
989     value |= extract_bits(instruction, 37, 5);
990     return value;
991 }
992 
993 
994 static int64 extract_shift__se5_21_20_19_18_17_16(uint64 instruction)
995 {
996     int64 value = 0;
997     value |= extract_bits(instruction, 16, 6);
998     value = sign_extend(value, 5);
999     return value;
1000 }
1001 
1002 
1003 static uint64 extract_rd2_3_8(uint64 instruction)
1004 {
1005     uint64 value = 0;
1006     value |= extract_bits(instruction, 3, 1) << 1;
1007     value |= extract_bits(instruction, 8, 1);
1008     return value;
1009 }
1010 
1011 
1012 static uint64 extract_code_17_to_0(uint64 instruction)
1013 {
1014     uint64 value = 0;
1015     value |= extract_bits(instruction, 0, 18);
1016     return value;
1017 }
1018 
1019 
1020 static uint64 extract_size_20_19_18_17_16(uint64 instruction)
1021 {
1022     uint64 value = 0;
1023     value |= extract_bits(instruction, 16, 5);
1024     return value;
1025 }
1026 
1027 
1028 static int64 extract_s__se8_15_7_6_5_4_3_2_s2(uint64 instruction)
1029 {
1030     int64 value = 0;
1031     value |= extract_bits(instruction, 2, 6) << 2;
1032     value |= extract_bits(instruction, 15, 1) << 8;
1033     value = sign_extend(value, 8);
1034     return value;
1035 }
1036 
1037 
1038 static uint64 extract_u_15_to_0(uint64 instruction)
1039 {
1040     uint64 value = 0;
1041     value |= extract_bits(instruction, 0, 16);
1042     return value;
1043 }
1044 
1045 
1046 static uint64 extract_fs_20_19_18_17_16(uint64 instruction)
1047 {
1048     uint64 value = 0;
1049     value |= extract_bits(instruction, 16, 5);
1050     return value;
1051 }
1052 
1053 
1054 static int64 extract_s__se8_15_7_6_5_4_3_2_1_0(uint64 instruction)
1055 {
1056     int64 value = 0;
1057     value |= extract_bits(instruction, 0, 8);
1058     value |= extract_bits(instruction, 15, 1) << 8;
1059     value = sign_extend(value, 8);
1060     return value;
1061 }
1062 
1063 
1064 static uint64 extract_stype_20_19_18_17_16(uint64 instruction)
1065 {
1066     uint64 value = 0;
1067     value |= extract_bits(instruction, 16, 5);
1068     return value;
1069 }
1070 
1071 
1072 static uint64 extract_rtl_11(uint64 instruction)
1073 {
1074     uint64 value = 0;
1075     value |= extract_bits(instruction, 9, 1);
1076     return value;
1077 }
1078 
1079 
1080 static uint64 extract_hs_20_19_18_17_16(uint64 instruction)
1081 {
1082     uint64 value = 0;
1083     value |= extract_bits(instruction, 16, 5);
1084     return value;
1085 }
1086 
1087 
1088 static uint64 extract_sel_13_12_11(uint64 instruction)
1089 {
1090     uint64 value = 0;
1091     value |= extract_bits(instruction, 11, 3);
1092     return value;
1093 }
1094 
1095 
1096 static uint64 extract_lsb_4_3_2_1_0(uint64 instruction)
1097 {
1098     uint64 value = 0;
1099     value |= extract_bits(instruction, 0, 5);
1100     return value;
1101 }
1102 
1103 
1104 static uint64 extract_gp_2(uint64 instruction)
1105 {
1106     uint64 value = 0;
1107     value |= extract_bits(instruction, 2, 1);
1108     return value;
1109 }
1110 
1111 
1112 static uint64 extract_rt3_9_8_7(uint64 instruction)
1113 {
1114     uint64 value = 0;
1115     value |= extract_bits(instruction, 7, 3);
1116     return value;
1117 }
1118 
1119 
1120 static uint64 extract_ft_25_24_23_22_21(uint64 instruction)
1121 {
1122     uint64 value = 0;
1123     value |= extract_bits(instruction, 21, 5);
1124     return value;
1125 }
1126 
1127 
1128 static uint64 extract_u_17_16_15_14_13_12_11(uint64 instruction)
1129 {
1130     uint64 value = 0;
1131     value |= extract_bits(instruction, 11, 7);
1132     return value;
1133 }
1134 
1135 
1136 static uint64 extract_cs_20_19_18_17_16(uint64 instruction)
1137 {
1138     uint64 value = 0;
1139     value |= extract_bits(instruction, 16, 5);
1140     return value;
1141 }
1142 
1143 
1144 static uint64 extract_rt4_9_7_6_5(uint64 instruction)
1145 {
1146     uint64 value = 0;
1147     value |= extract_bits(instruction, 5, 3);
1148     value |= extract_bits(instruction, 9, 1) << 3;
1149     return value;
1150 }
1151 
1152 
1153 static uint64 extract_msbt_10_9_8_7_6(uint64 instruction)
1154 {
1155     uint64 value = 0;
1156     value |= extract_bits(instruction, 6, 5);
1157     return value;
1158 }
1159 
1160 
1161 static uint64 extract_u_5_4_3_2_1_0__s2(uint64 instruction)
1162 {
1163     uint64 value = 0;
1164     value |= extract_bits(instruction, 0, 6) << 2;
1165     return value;
1166 }
1167 
1168 
1169 static uint64 extract_sa_15_14_13(uint64 instruction)
1170 {
1171     uint64 value = 0;
1172     value |= extract_bits(instruction, 13, 3);
1173     return value;
1174 }
1175 
1176 
1177 static int64 extract_s__se14_0_13_to_1_s1(uint64 instruction)
1178 {
1179     int64 value = 0;
1180     value |= extract_bits(instruction, 0, 1) << 14;
1181     value |= extract_bits(instruction, 1, 13) << 1;
1182     value = sign_extend(value, 14);
1183     return value;
1184 }
1185 
1186 
1187 static uint64 extract_rs3_6_5_4(uint64 instruction)
1188 {
1189     uint64 value = 0;
1190     value |= extract_bits(instruction, 4, 3);
1191     return value;
1192 }
1193 
1194 
1195 static uint64 extract_u_31_to_0__s32(uint64 instruction)
1196 {
1197     uint64 value = 0;
1198     value |= extract_bits(instruction, 0, 32) << 32;
1199     return value;
1200 }
1201 
1202 
1203 static uint64 extract_shift_10_9_8_7_6(uint64 instruction)
1204 {
1205     uint64 value = 0;
1206     value |= extract_bits(instruction, 6, 5);
1207     return value;
1208 }
1209 
1210 
1211 static uint64 extract_cs_25_24_23_22_21(uint64 instruction)
1212 {
1213     uint64 value = 0;
1214     value |= extract_bits(instruction, 21, 5);
1215     return value;
1216 }
1217 
1218 
1219 static uint64 extract_shiftx_11_10_9_8_7_6(uint64 instruction)
1220 {
1221     uint64 value = 0;
1222     value |= extract_bits(instruction, 6, 6);
1223     return value;
1224 }
1225 
1226 
1227 static uint64 extract_rt_9_8_7_6_5(uint64 instruction)
1228 {
1229     uint64 value = 0;
1230     value |= extract_bits(instruction, 5, 5);
1231     return value;
1232 }
1233 
1234 
1235 static uint64 extract_op_25_24_23_22_21(uint64 instruction)
1236 {
1237     uint64 value = 0;
1238     value |= extract_bits(instruction, 21, 5);
1239     return value;
1240 }
1241 
1242 
1243 static uint64 extract_u_6_5_4_3_2_1_0__s2(uint64 instruction)
1244 {
1245     uint64 value = 0;
1246     value |= extract_bits(instruction, 0, 7) << 2;
1247     return value;
1248 }
1249 
1250 
1251 static uint64 extract_bit_16_15_14_13_12_11(uint64 instruction)
1252 {
1253     uint64 value = 0;
1254     value |= extract_bits(instruction, 11, 6);
1255     return value;
1256 }
1257 
1258 
1259 static uint64 extract_mask_20_19_18_17_16_15_14(uint64 instruction)
1260 {
1261     uint64 value = 0;
1262     value |= extract_bits(instruction, 14, 7);
1263     return value;
1264 }
1265 
1266 
1267 static uint64 extract_eu_3_2_1_0(uint64 instruction)
1268 {
1269     uint64 value = 0;
1270     value |= extract_bits(instruction, 0, 4);
1271     return value;
1272 }
1273 
1274 
1275 static uint64 extract_u_7_6_5_4__s4(uint64 instruction)
1276 {
1277     uint64 value = 0;
1278     value |= extract_bits(instruction, 4, 4) << 4;
1279     return value;
1280 }
1281 
1282 
1283 static int64 extract_s__se8_15_7_6_5_4_3_s3(uint64 instruction)
1284 {
1285     int64 value = 0;
1286     value |= extract_bits(instruction, 3, 5) << 3;
1287     value |= extract_bits(instruction, 15, 1) << 8;
1288     value = sign_extend(value, 8);
1289     return value;
1290 }
1291 
1292 
1293 static uint64 extract_ft_15_14_13_12_11(uint64 instruction)
1294 {
1295     uint64 value = 0;
1296     value |= extract_bits(instruction, 11, 5);
1297     return value;
1298 }
1299 
1300 
1301 static int64 extract_s__se31_15_to_0_31_to_16(uint64 instruction)
1302 {
1303     int64 value = 0;
1304     value |= extract_bits(instruction, 0, 16) << 16;
1305     value |= extract_bits(instruction, 16, 16);
1306     value = sign_extend(value, 31);
1307     return value;
1308 }
1309 
1310 
1311 static uint64 extract_u_20_19_18_17_16_15_14_13(uint64 instruction)
1312 {
1313     uint64 value = 0;
1314     value |= extract_bits(instruction, 13, 8);
1315     return value;
1316 }
1317 
1318 
1319 static uint64 extract_u_17_to_2__s2(uint64 instruction)
1320 {
1321     uint64 value = 0;
1322     value |= extract_bits(instruction, 2, 16) << 2;
1323     return value;
1324 }
1325 
1326 
1327 static uint64 extract_rd_15_14_13_12_11(uint64 instruction)
1328 {
1329     uint64 value = 0;
1330     value |= extract_bits(instruction, 11, 5);
1331     return value;
1332 }
1333 
1334 
1335 static uint64 extract_c0s_20_19_18_17_16(uint64 instruction)
1336 {
1337     uint64 value = 0;
1338     value |= extract_bits(instruction, 16, 5);
1339     return value;
1340 }
1341 
1342 
1343 static uint64 extract_code_1_0(uint64 instruction)
1344 {
1345     uint64 value = 0;
1346     value |= extract_bits(instruction, 0, 2);
1347     return value;
1348 }
1349 
1350 
1351 static int64 extract_s__se25_0_24_to_1_s1(uint64 instruction)
1352 {
1353     int64 value = 0;
1354     value |= extract_bits(instruction, 0, 1) << 25;
1355     value |= extract_bits(instruction, 1, 24) << 1;
1356     value = sign_extend(value, 25);
1357     return value;
1358 }
1359 
1360 
1361 static uint64 extract_u_1_0(uint64 instruction)
1362 {
1363     uint64 value = 0;
1364     value |= extract_bits(instruction, 0, 2);
1365     return value;
1366 }
1367 
1368 
1369 static uint64 extract_u_3_8__s2(uint64 instruction)
1370 {
1371     uint64 value = 0;
1372     value |= extract_bits(instruction, 3, 1) << 3;
1373     value |= extract_bits(instruction, 8, 1) << 2;
1374     return value;
1375 }
1376 
1377 
1378 static uint64 extract_fd_15_14_13_12_11(uint64 instruction)
1379 {
1380     uint64 value = 0;
1381     value |= extract_bits(instruction, 11, 5);
1382     return value;
1383 }
1384 
1385 
1386 static uint64 extract_u_4_3_2_1_0__s2(uint64 instruction)
1387 {
1388     uint64 value = 0;
1389     value |= extract_bits(instruction, 0, 5) << 2;
1390     return value;
1391 }
1392 
1393 
1394 static uint64 extract_rtz4_9_7_6_5(uint64 instruction)
1395 {
1396     uint64 value = 0;
1397     value |= extract_bits(instruction, 5, 3);
1398     value |= extract_bits(instruction, 9, 1) << 3;
1399     return value;
1400 }
1401 
1402 
1403 static uint64 extract_sel_15_14_13_12_11(uint64 instruction)
1404 {
1405     uint64 value = 0;
1406     value |= extract_bits(instruction, 11, 5);
1407     return value;
1408 }
1409 
1410 
1411 static uint64 extract_ct_25_24_23_22_21(uint64 instruction)
1412 {
1413     uint64 value = 0;
1414     value |= extract_bits(instruction, 21, 5);
1415     return value;
1416 }
1417 
1418 
1419 static uint64 extract_u_20_to_2__s2(uint64 instruction)
1420 {
1421     uint64 value = 0;
1422     value |= extract_bits(instruction, 2, 19) << 2;
1423     return value;
1424 }
1425 
1426 
1427 static int64 extract_s__se3_4_2_1_0(uint64 instruction)
1428 {
1429     int64 value = 0;
1430     value |= extract_bits(instruction, 0, 3);
1431     value |= extract_bits(instruction, 4, 1) << 3;
1432     value = sign_extend(value, 3);
1433     return value;
1434 }
1435 
1436 
1437 static uint64 extract_u_3_2_1_0__s1(uint64 instruction)
1438 {
1439     uint64 value = 0;
1440     value |= extract_bits(instruction, 0, 4) << 1;
1441     return value;
1442 }
1443 
1444 
1445 
1446 static bool ADDIU_32__cond(uint64 instruction)
1447 {
1448     uint64 rt = extract_rt_25_24_23_22_21(instruction);
1449     return rt != 0;
1450 }
1451 
1452 
1453 static bool ADDIU_RS5__cond(uint64 instruction)
1454 {
1455     uint64 rt = extract_rt_9_8_7_6_5(instruction);
1456     return rt != 0;
1457 }
1458 
1459 
1460 static bool BALRSC_cond(uint64 instruction)
1461 {
1462     uint64 rt = extract_rt_25_24_23_22_21(instruction);
1463     return rt != 0;
1464 }
1465 
1466 
1467 static bool BEQC_16__cond(uint64 instruction)
1468 {
1469     uint64 rs3 = extract_rs3_6_5_4(instruction);
1470     uint64 rt3 = extract_rt3_9_8_7(instruction);
1471     uint64 u = extract_u_3_2_1_0__s1(instruction);
1472     return rs3 < rt3 && u != 0;
1473 }
1474 
1475 
1476 static bool BNEC_16__cond(uint64 instruction)
1477 {
1478     uint64 rs3 = extract_rs3_6_5_4(instruction);
1479     uint64 rt3 = extract_rt3_9_8_7(instruction);
1480     uint64 u = extract_u_3_2_1_0__s1(instruction);
1481     return rs3 >= rt3 && u != 0;
1482 }
1483 
1484 
1485 static bool MOVE_cond(uint64 instruction)
1486 {
1487     uint64 rt = extract_rt_9_8_7_6_5(instruction);
1488     return rt != 0;
1489 }
1490 
1491 
1492 static bool P16_BR1_cond(uint64 instruction)
1493 {
1494     uint64 u = extract_u_3_2_1_0__s1(instruction);
1495     return u != 0;
1496 }
1497 
1498 
1499 static bool PREF_S9__cond(uint64 instruction)
1500 {
1501     uint64 hint = extract_hint_25_24_23_22_21(instruction);
1502     return hint != 31;
1503 }
1504 
1505 
1506 static bool PREFE_cond(uint64 instruction)
1507 {
1508     uint64 hint = extract_hint_25_24_23_22_21(instruction);
1509     return hint != 31;
1510 }
1511 
1512 
1513 static bool SLTU_cond(uint64 instruction)
1514 {
1515     uint64 rd = extract_rd_15_14_13_12_11(instruction);
1516     return rd != 0;
1517 }
1518 
1519 
1520 
1521 /*
1522  * ABS.D fd, fs - Floating Point Absolute Value
1523  *
1524  *   3         2         1
1525  *  10987654321098765432109876543210
1526  *  010001     00000          000101
1527  *    fmt -----
1528  *               fs -----
1529  *                    fd -----
1530  */
1531 static char *ABS_D(uint64 instruction, Dis_info *info)
1532 {
1533     uint64 fd_value = extract_ft_25_24_23_22_21(instruction);
1534     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1535 
1536     const char *fs = FPR(fs_value, info);
1537     const char *fd = FPR(fd_value, info);
1538 
1539     return img_format("ABS.D %s, %s", fd, fs);
1540 }
1541 
1542 
1543 /*
1544  * ABS.S fd, fs - Floating Point Absolute Value
1545  *
1546  *   3         2         1
1547  *  10987654321098765432109876543210
1548  *  010001     00000          000101
1549  *    fmt -----
1550  *               fd -----
1551  *                    fs -----
1552  */
1553 static char *ABS_S(uint64 instruction, Dis_info *info)
1554 {
1555     uint64 fd_value = extract_ft_25_24_23_22_21(instruction);
1556     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1557 
1558     const char *fs = FPR(fs_value, info);
1559     const char *fd = FPR(fd_value, info);
1560 
1561     return img_format("ABS.S %s, %s", fd, fs);
1562 }
1563 
1564 
1565 /*
1566  * [DSP] ABSQ_S.PH rt, rs - Find absolute value of two fractional halfwords
1567  *         with 16-bit saturation
1568  *
1569  *   3         2         1
1570  *  10987654321098765432109876543210
1571  *  001000          0001000100111111
1572  *     rt -----
1573  *          rs -----
1574  */
1575 static char *ABSQ_S_PH(uint64 instruction, Dis_info *info)
1576 {
1577     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1578     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1579 
1580     const char *rt = GPR(rt_value, info);
1581     const char *rs = GPR(rs_value, info);
1582 
1583     return img_format("ABSQ_S.PH %s, %s", rt, rs);
1584 }
1585 
1586 
1587 /*
1588  * [DSP] ABSQ_S.QB rt, rs - Find absolute value of four fractional byte values
1589  *         with 8-bit saturation
1590  *
1591  *   3         2         1
1592  *  10987654321098765432109876543210
1593  *  001000          0000000100111111
1594  *     rt -----
1595  *          rs -----
1596  */
1597 static char *ABSQ_S_QB(uint64 instruction, Dis_info *info)
1598 {
1599     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1600     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1601 
1602     const char *rt = GPR(rt_value, info);
1603     const char *rs = GPR(rs_value, info);
1604 
1605     return img_format("ABSQ_S.QB %s, %s", rt, rs);
1606 }
1607 
1608 
1609 /*
1610  * [DSP] ABSQ_S.W rt, rs - Find absolute value of fractional word with 32-bit
1611  *         saturation
1612  *
1613  *   3         2         1
1614  *  10987654321098765432109876543210
1615  *  001000          0010000100111111
1616  *     rt -----
1617  *          rs -----
1618  */
1619 static char *ABSQ_S_W(uint64 instruction, Dis_info *info)
1620 {
1621     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1622     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1623 
1624     const char *rt = GPR(rt_value, info);
1625     const char *rs = GPR(rs_value, info);
1626 
1627     return img_format("ABSQ_S.W %s, %s", rt, rs);
1628 }
1629 
1630 
1631 /*
1632  *
1633  *
1634  *   3         2         1
1635  *  10987654321098765432109876543210
1636  *  001000          0010000100111111
1637  *     rt -----
1638  *          rs -----
1639  */
1640 static char *ACLR(uint64 instruction, Dis_info *info)
1641 {
1642     uint64 bit_value = extract_bit_23_22_21(instruction);
1643     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1644     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
1645 
1646     const char *rs = GPR(rs_value, info);
1647 
1648     return img_format("ACLR 0x%" PRIx64 ", %" PRId64 "(%s)",
1649                       bit_value, s_value, rs);
1650 }
1651 
1652 
1653 /*
1654  *
1655  *
1656  *   3         2         1
1657  *  10987654321098765432109876543210
1658  *  001000          0010000100111111
1659  *     rt -----
1660  *          rs -----
1661  */
1662 static char *ADD(uint64 instruction, Dis_info *info)
1663 {
1664     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1665     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1666     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
1667 
1668     const char *rd = GPR(rd_value, info);
1669     const char *rs = GPR(rs_value, info);
1670     const char *rt = GPR(rt_value, info);
1671 
1672     return img_format("ADD %s, %s, %s", rd, rs, rt);
1673 }
1674 
1675 
1676 /*
1677  * ADD.D fd, fs, ft - Floating Point Add
1678  *
1679  *   3         2         1
1680  *  10987654321098765432109876543210
1681  *  010001                    000101
1682  *    fmt -----
1683  *          ft -----
1684  *               fs -----
1685  *                    fd -----
1686  */
1687 static char *ADD_D(uint64 instruction, Dis_info *info)
1688 {
1689     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
1690     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1691     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
1692 
1693     const char *ft = FPR(ft_value, info);
1694     const char *fs = FPR(fs_value, info);
1695     const char *fd = FPR(fd_value, info);
1696 
1697     return img_format("ADD.D %s, %s, %s", fd, fs, ft);
1698 }
1699 
1700 
1701 /*
1702  * ADD.S fd, fs, ft - Floating Point Add
1703  *
1704  *   3         2         1
1705  *  10987654321098765432109876543210
1706  *  010001                    000101
1707  *    fmt -----
1708  *          ft -----
1709  *               fs -----
1710  *                    fd -----
1711  */
1712 static char *ADD_S(uint64 instruction, Dis_info *info)
1713 {
1714     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
1715     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
1716     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
1717 
1718     const char *ft = FPR(ft_value, info);
1719     const char *fs = FPR(fs_value, info);
1720     const char *fd = FPR(fd_value, info);
1721 
1722     return img_format("ADD.S %s, %s, %s", fd, fs, ft);
1723 }
1724 
1725 
1726 /*
1727  *
1728  *
1729  *   3         2         1
1730  *  10987654321098765432109876543210
1731  *  001000          0010000100111111
1732  *     rt -----
1733  *          rs -----
1734  */
1735 static char *ADDIU_32_(uint64 instruction, Dis_info *info)
1736 {
1737     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1738     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1739     uint64 u_value = extract_u_15_to_0(instruction);
1740 
1741     const char *rt = GPR(rt_value, info);
1742     const char *rs = GPR(rs_value, info);
1743 
1744     return img_format("ADDIU %s, %s, 0x%" PRIx64, rt, rs, u_value);
1745 }
1746 
1747 
1748 /*
1749  *
1750  *
1751  *   3         2         1
1752  *  10987654321098765432109876543210
1753  *  001000          0010000100111111
1754  *     rt -----
1755  *          rs -----
1756  */
1757 static char *ADDIU_48_(uint64 instruction, Dis_info *info)
1758 {
1759     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
1760     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
1761 
1762     const char *rt = GPR(rt_value, info);
1763 
1764     return img_format("ADDIU %s, %" PRId64, rt, s_value);
1765 }
1766 
1767 
1768 /*
1769  *
1770  *
1771  *   3         2         1
1772  *  10987654321098765432109876543210
1773  *  001000          0010000100111111
1774  *     rt -----
1775  *          rs -----
1776  */
1777 static char *ADDIU_GP48_(uint64 instruction, Dis_info *info)
1778 {
1779     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
1780     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
1781 
1782     const char *rt = GPR(rt_value, info);
1783 
1784     return img_format("ADDIU %s, $%d, %" PRId64, rt, 28, s_value);
1785 }
1786 
1787 
1788 /*
1789  *
1790  *
1791  *   3         2         1
1792  *  10987654321098765432109876543210
1793  *  001000          0010000100111111
1794  *     rt -----
1795  *          rs -----
1796  */
1797 static char *ADDIU_GP_B_(uint64 instruction, Dis_info *info)
1798 {
1799     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1800     uint64 u_value = extract_u_17_to_0(instruction);
1801 
1802     const char *rt = GPR(rt_value, info);
1803 
1804     return img_format("ADDIU %s, $%d, 0x%" PRIx64, rt, 28, u_value);
1805 }
1806 
1807 
1808 /*
1809  *
1810  *
1811  *   3         2         1
1812  *  10987654321098765432109876543210
1813  *  001000          0010000100111111
1814  *     rt -----
1815  *          rs -----
1816  */
1817 static char *ADDIU_GP_W_(uint64 instruction, Dis_info *info)
1818 {
1819     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1820     uint64 u_value = extract_u_20_to_2__s2(instruction);
1821 
1822     const char *rt = GPR(rt_value, info);
1823 
1824     return img_format("ADDIU %s, $%d, 0x%" PRIx64, rt, 28, u_value);
1825 }
1826 
1827 
1828 /*
1829  *
1830  *
1831  *   3         2         1
1832  *  10987654321098765432109876543210
1833  *  001000          0010000100111111
1834  *     rt -----
1835  *          rs -----
1836  */
1837 static char *ADDIU_NEG_(uint64 instruction, Dis_info *info)
1838 {
1839     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1840     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1841     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
1842 
1843     const char *rt = GPR(rt_value, info);
1844     const char *rs = GPR(rs_value, info);
1845     int64 u = neg_copy(u_value);
1846 
1847     return img_format("ADDIU %s, %s, %" PRId64, rt, rs, u);
1848 }
1849 
1850 
1851 /*
1852  *
1853  *
1854  *   3         2         1
1855  *  10987654321098765432109876543210
1856  *  001000          0010000100111111
1857  *     rt -----
1858  *          rs -----
1859  */
1860 static char *ADDIU_R1_SP_(uint64 instruction, Dis_info *info)
1861 {
1862     uint64 u_value = extract_u_5_4_3_2_1_0__s2(instruction);
1863     uint64 rt3_value = extract_rt3_9_8_7(instruction);
1864 
1865     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
1866 
1867     return img_format("ADDIU %s, $%d, 0x%" PRIx64, rt3, 29, u_value);
1868 }
1869 
1870 
1871 /*
1872  *
1873  *
1874  *   3         2         1
1875  *  10987654321098765432109876543210
1876  *  001000          0010000100111111
1877  *     rt -----
1878  *          rs -----
1879  */
1880 static char *ADDIU_R2_(uint64 instruction, Dis_info *info)
1881 {
1882     uint64 rt3_value = extract_rt3_9_8_7(instruction);
1883     uint64 rs3_value = extract_rs3_6_5_4(instruction);
1884     uint64 u_value = extract_u_2_1_0__s2(instruction);
1885 
1886     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
1887     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
1888 
1889     return img_format("ADDIU %s, %s, 0x%" PRIx64, rt3, rs3, u_value);
1890 }
1891 
1892 
1893 /*
1894  * ADDIU[RS5] rt, s5 - Add Signed Word and Set Carry Bit
1895  *
1896  *  5432109876543210
1897  *  100100      1
1898  *     rt -----
1899  *           s - ---
1900  */
1901 static char *ADDIU_RS5_(uint64 instruction, Dis_info *info)
1902 {
1903     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
1904     int64 s_value = extract_s__se3_4_2_1_0(instruction);
1905 
1906     const char *rt = GPR(rt_value, info);
1907 
1908     return img_format("ADDIU %s, %" PRId64, rt, s_value);
1909 }
1910 
1911 
1912 /*
1913  *
1914  *
1915  *   3         2         1
1916  *  10987654321098765432109876543210
1917  *  001000               x1110000101
1918  *     rt -----
1919  *          rs -----
1920  *               rd -----
1921  */
1922 static char *ADDIUPC_32_(uint64 instruction, Dis_info *info)
1923 {
1924     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1925     int64 s_value = extract_s__se21_0_20_to_1_s1(instruction);
1926 
1927     const char *rt = GPR(rt_value, info);
1928     g_autofree char *s = ADDRESS(s_value, 4, info);
1929 
1930     return img_format("ADDIUPC %s, %s", rt, s);
1931 }
1932 
1933 
1934 /*
1935  *
1936  *
1937  *   3         2         1
1938  *  10987654321098765432109876543210
1939  *  001000               x1110000101
1940  *     rt -----
1941  *          rs -----
1942  *               rd -----
1943  */
1944 static char *ADDIUPC_48_(uint64 instruction, Dis_info *info)
1945 {
1946     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
1947     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
1948 
1949     const char *rt = GPR(rt_value, info);
1950     g_autofree char *s = ADDRESS(s_value, 6, info);
1951 
1952     return img_format("ADDIUPC %s, %s", rt, s);
1953 }
1954 
1955 
1956 /*
1957  * [DSP] ADDQ.PH rd, rt, rs - Add fractional halfword vectors
1958  *
1959  *   3         2         1
1960  *  10987654321098765432109876543210
1961  *  001000               00000001101
1962  *     rt -----
1963  *          rs -----
1964  *               rd -----
1965  */
1966 static char *ADDQ_PH(uint64 instruction, Dis_info *info)
1967 {
1968     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1969     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1970     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
1971 
1972     const char *rd = GPR(rd_value, info);
1973     const char *rs = GPR(rs_value, info);
1974     const char *rt = GPR(rt_value, info);
1975 
1976     return img_format("ADDQ.PH %s, %s, %s", rd, rs, rt);
1977 }
1978 
1979 
1980 /*
1981  * [DSP] ADDQ_S.PH rd, rt, rs - Add fractional halfword vectors with 16-bit
1982  *         saturation
1983  *
1984  *   3         2         1
1985  *  10987654321098765432109876543210
1986  *  001000               10000001101
1987  *     rt -----
1988  *          rs -----
1989  *               rd -----
1990  */
1991 static char *ADDQ_S_PH(uint64 instruction, Dis_info *info)
1992 {
1993     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
1994     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
1995     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
1996 
1997     const char *rd = GPR(rd_value, info);
1998     const char *rs = GPR(rs_value, info);
1999     const char *rt = GPR(rt_value, info);
2000 
2001     return img_format("ADDQ_S.PH %s, %s, %s", rd, rs, rt);
2002 }
2003 
2004 
2005 /*
2006  * [DSP] ADDQ_S.W rd, rt, rs - Add fractional words with 32-bit saturation
2007  *
2008  *   3         2         1
2009  *  10987654321098765432109876543210
2010  *  001000               x1100000101
2011  *     rt -----
2012  *          rs -----
2013  *               rd -----
2014  */
2015 static char *ADDQ_S_W(uint64 instruction, Dis_info *info)
2016 {
2017     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2018     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2019     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2020 
2021     const char *rd = GPR(rd_value, info);
2022     const char *rs = GPR(rs_value, info);
2023     const char *rt = GPR(rt_value, info);
2024 
2025     return img_format("ADDQ_S.W %s, %s, %s", rd, rs, rt);
2026 }
2027 
2028 
2029 /*
2030  * [DSP] ADDQH.PH rd, rt, rs - Add fractional halfword vectors and shift
2031  *         right to halve results
2032  *
2033  *   3         2         1
2034  *  10987654321098765432109876543210
2035  *  001000               00001001101
2036  *     rt -----
2037  *          rs -----
2038  *               rd -----
2039  */
2040 static char *ADDQH_PH(uint64 instruction, Dis_info *info)
2041 {
2042     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2043     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2044     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2045 
2046     const char *rd = GPR(rd_value, info);
2047     const char *rs = GPR(rs_value, info);
2048     const char *rt = GPR(rt_value, info);
2049 
2050     return img_format("ADDQH.PH %s, %s, %s", rd, rs, rt);
2051 }
2052 
2053 
2054 /*
2055  * [DSP] ADDQH_R.PH rd, rt, rs - Add fractional halfword vectors and shift
2056  *         right to halve results with rounding
2057  *
2058  *   3         2         1
2059  *  10987654321098765432109876543210
2060  *  001000               10001001101
2061  *     rt -----
2062  *          rs -----
2063  *               rd -----
2064  */
2065 static char *ADDQH_R_PH(uint64 instruction, Dis_info *info)
2066 {
2067     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2068     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2069     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2070 
2071     const char *rd = GPR(rd_value, info);
2072     const char *rs = GPR(rs_value, info);
2073     const char *rt = GPR(rt_value, info);
2074 
2075     return img_format("ADDQH_R.PH %s, %s, %s", rd, rs, rt);
2076 }
2077 
2078 
2079 /*
2080  * [DSP] ADDQH_R.W rd, rt, rs - Add fractional words and shift right to halve
2081  *         results with rounding
2082  *
2083  *   3         2         1
2084  *  10987654321098765432109876543210
2085  *  001000               00010001101
2086  *     rt -----
2087  *          rs -----
2088  *               rd -----
2089  */
2090 static char *ADDQH_R_W(uint64 instruction, Dis_info *info)
2091 {
2092     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2093     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2094     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2095 
2096     const char *rd = GPR(rd_value, info);
2097     const char *rs = GPR(rs_value, info);
2098     const char *rt = GPR(rt_value, info);
2099 
2100     return img_format("ADDQH_R.W %s, %s, %s", rd, rs, rt);
2101 }
2102 
2103 
2104 /*
2105  * [DSP] ADDQH.W rd, rt, rs - Add fractional words and shift right to halve
2106  *         results
2107  *
2108  *   3         2         1
2109  *  10987654321098765432109876543210
2110  *  001000               10010001101
2111  *     rt -----
2112  *          rs -----
2113  *               rd -----
2114  */
2115 static char *ADDQH_W(uint64 instruction, Dis_info *info)
2116 {
2117     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2118     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2119     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2120 
2121     const char *rd = GPR(rd_value, info);
2122     const char *rs = GPR(rs_value, info);
2123     const char *rt = GPR(rt_value, info);
2124 
2125     return img_format("ADDQH.W %s, %s, %s", rd, rs, rt);
2126 }
2127 
2128 
2129 /*
2130  * [DSP] ADDSC rd, rt, rs - Add two signed words and set carry bit
2131  *
2132  *   3         2         1
2133  *  10987654321098765432109876543210
2134  *  001000               x1110000101
2135  *     rt -----
2136  *          rs -----
2137  *               rd -----
2138  */
2139 static char *ADDSC(uint64 instruction, Dis_info *info)
2140 {
2141     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2142     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2143     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2144 
2145     const char *rd = GPR(rd_value, info);
2146     const char *rs = GPR(rs_value, info);
2147     const char *rt = GPR(rt_value, info);
2148 
2149     return img_format("ADDSC %s, %s, %s", rd, rs, rt);
2150 }
2151 
2152 
2153 /*
2154  * ADDU[16] rd3, rs3, rt3 -
2155  *
2156  *  5432109876543210
2157  *  101100         0
2158  *    rt3 ---
2159  *       rs3 ---
2160  *          rd3 ---
2161  */
2162 static char *ADDU_16_(uint64 instruction, Dis_info *info)
2163 {
2164     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2165     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2166     uint64 rd3_value = extract_rd3_3_2_1(instruction);
2167 
2168     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
2169     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
2170     const char *rd3 = GPR(decode_gpr_gpr3(rd3_value, info), info);
2171 
2172     return img_format("ADDU %s, %s, %s", rd3, rs3, rt3);
2173 }
2174 
2175 
2176 /*
2177  *
2178  *
2179  *   3         2         1
2180  *  10987654321098765432109876543210
2181  *  001000               x1110000101
2182  *     rt -----
2183  *          rs -----
2184  *               rd -----
2185  */
2186 static char *ADDU_32_(uint64 instruction, Dis_info *info)
2187 {
2188     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2189     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2190     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2191 
2192     const char *rd = GPR(rd_value, info);
2193     const char *rs = GPR(rs_value, info);
2194     const char *rt = GPR(rt_value, info);
2195 
2196     return img_format("ADDU %s, %s, %s", rd, rs, rt);
2197 }
2198 
2199 
2200 /*
2201  *
2202  *
2203  *   3         2         1
2204  *  10987654321098765432109876543210
2205  *  001000               x1110000101
2206  *     rt -----
2207  *          rs -----
2208  *               rd -----
2209  */
2210 static char *ADDU_4X4_(uint64 instruction, Dis_info *info)
2211 {
2212     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
2213     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
2214 
2215     const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info);
2216     const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info);
2217 
2218     return img_format("ADDU %s, %s", rs4, rt4);
2219 }
2220 
2221 
2222 /*
2223  * [DSP] ADDU.PH rd, rt, rs - Add two pairs of unsigned halfwords
2224  *
2225  *   3         2         1
2226  *  10987654321098765432109876543210
2227  *  001000               00100001101
2228  *     rt -----
2229  *          rs -----
2230  *               rd -----
2231  */
2232 static char *ADDU_PH(uint64 instruction, Dis_info *info)
2233 {
2234     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2235     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2236     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2237 
2238     const char *rd = GPR(rd_value, info);
2239     const char *rs = GPR(rs_value, info);
2240     const char *rt = GPR(rt_value, info);
2241 
2242     return img_format("ADDU.PH %s, %s, %s", rd, rs, rt);
2243 }
2244 
2245 
2246 /*
2247  * ADDU.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2248  *
2249  *   3         2         1
2250  *  10987654321098765432109876543210
2251  *  001000               00011001101
2252  *     rt -----
2253  *          rs -----
2254  *               rd -----
2255  */
2256 static char *ADDU_QB(uint64 instruction, Dis_info *info)
2257 {
2258     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2259     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2260     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2261 
2262     const char *rd = GPR(rd_value, info);
2263     const char *rs = GPR(rs_value, info);
2264     const char *rt = GPR(rt_value, info);
2265 
2266     return img_format("ADDU.QB %s, %s, %s", rd, rs, rt);
2267 }
2268 
2269 
2270 /*
2271  * [DSP] ADDU_S.PH rd, rt, rs - Add two pairs of unsigned halfwords with 16-bit
2272  *         saturation
2273  *
2274  *   3         2         1
2275  *  10987654321098765432109876543210
2276  *  001000               10100001101
2277  *     rt -----
2278  *          rs -----
2279  *               rd -----
2280  */
2281 static char *ADDU_S_PH(uint64 instruction, Dis_info *info)
2282 {
2283     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2284     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2285     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2286 
2287     const char *rd = GPR(rd_value, info);
2288     const char *rs = GPR(rs_value, info);
2289     const char *rt = GPR(rt_value, info);
2290 
2291     return img_format("ADDU_S.PH %s, %s, %s", rd, rs, rt);
2292 }
2293 
2294 
2295 /*
2296  * ADDU_S.QB rd, rt, rs - Unsigned Add Quad Byte Vectors
2297  *
2298  *   3         2         1
2299  *  10987654321098765432109876543210
2300  *  001000               10011001101
2301  *     rt -----
2302  *          rs -----
2303  *               rd -----
2304  */
2305 static char *ADDU_S_QB(uint64 instruction, Dis_info *info)
2306 {
2307     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2308     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2309     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2310 
2311     const char *rd = GPR(rd_value, info);
2312     const char *rs = GPR(rs_value, info);
2313     const char *rt = GPR(rt_value, info);
2314 
2315     return img_format("ADDU_S.QB %s, %s, %s", rd, rs, rt);
2316 }
2317 
2318 
2319 /*
2320  * ADDUH.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2321  *                       to Halve Results
2322  *
2323  *   3         2         1
2324  *  10987654321098765432109876543210
2325  *  001000               00101001101
2326  *     rt -----
2327  *          rs -----
2328  *               rd -----
2329  */
2330 static char *ADDUH_QB(uint64 instruction, Dis_info *info)
2331 {
2332     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2333     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2334     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2335 
2336     const char *rd = GPR(rd_value, info);
2337     const char *rs = GPR(rs_value, info);
2338     const char *rt = GPR(rt_value, info);
2339 
2340     return img_format("ADDUH.QB %s, %s, %s", rd, rs, rt);
2341 }
2342 
2343 
2344 /*
2345  * ADDUH_R.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift
2346  *                         to Halve Results
2347  *
2348  *   3         2         1
2349  *  10987654321098765432109876543210
2350  *  001000               10101001101
2351  *     rt -----
2352  *          rs -----
2353  *               rd -----
2354  */
2355 static char *ADDUH_R_QB(uint64 instruction, Dis_info *info)
2356 {
2357     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2358     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2359     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2360 
2361     const char *rd = GPR(rd_value, info);
2362     const char *rs = GPR(rs_value, info);
2363     const char *rt = GPR(rt_value, info);
2364 
2365     return img_format("ADDUH_R.QB %s, %s, %s", rd, rs, rt);
2366 }
2367 
2368 /*
2369  * ADDWC rd, rt, rs - Add Word with Carry Bit
2370  *
2371  *   3         2         1
2372  *  10987654321098765432109876543210
2373  *  001000               x1111000101
2374  *     rt -----
2375  *          rs -----
2376  *               rd -----
2377  */
2378 static char *ADDWC(uint64 instruction, Dis_info *info)
2379 {
2380     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2381     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2382     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2383 
2384     const char *rd = GPR(rd_value, info);
2385     const char *rs = GPR(rs_value, info);
2386     const char *rt = GPR(rt_value, info);
2387 
2388     return img_format("ADDWC %s, %s, %s", rd, rs, rt);
2389 }
2390 
2391 
2392 /*
2393  *
2394  *
2395  *   3         2         1
2396  *  10987654321098765432109876543210
2397  *  001000               x1110000101
2398  *     rt -----
2399  *          rs -----
2400  *               rd -----
2401  */
2402 static char *ALUIPC(uint64 instruction, Dis_info *info)
2403 {
2404     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2405     int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction);
2406 
2407     const char *rt = GPR(rt_value, info);
2408     g_autofree char *s = ADDRESS(s_value, 4, info);
2409 
2410     return img_format("ALUIPC %s, %%pcrel_hi(%s)", rt, s);
2411 }
2412 
2413 
2414 /*
2415  * AND[16] rt3, rs3 -
2416  *
2417  *  5432109876543210
2418  *  101100
2419  *    rt3 ---
2420  *       rs3 ---
2421  *           eu ----
2422  */
2423 static char *AND_16_(uint64 instruction, Dis_info *info)
2424 {
2425     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2426     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2427 
2428     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
2429     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
2430 
2431     return img_format("AND %s, %s", rs3, rt3);
2432 }
2433 
2434 
2435 /*
2436  *
2437  *
2438  *   3         2         1
2439  *  10987654321098765432109876543210
2440  *  001000               x1110000101
2441  *     rt -----
2442  *          rs -----
2443  *               rd -----
2444  */
2445 static char *AND_32_(uint64 instruction, Dis_info *info)
2446 {
2447     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2448     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2449     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
2450 
2451     const char *rd = GPR(rd_value, info);
2452     const char *rs = GPR(rs_value, info);
2453     const char *rt = GPR(rt_value, info);
2454 
2455     return img_format("AND %s, %s, %s", rd, rs, rt);
2456 }
2457 
2458 
2459 /*
2460  * ANDI rt, rs, u -
2461  *
2462  *  5432109876543210
2463  *  101100
2464  *    rt3 ---
2465  *       rs3 ---
2466  *           eu ----
2467  */
2468 static char *ANDI_16_(uint64 instruction, Dis_info *info)
2469 {
2470     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2471     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2472     uint64 eu_value = extract_eu_3_2_1_0(instruction);
2473 
2474     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
2475     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
2476     uint64 eu = encode_eu_from_u_andi16(eu_value);
2477 
2478     return img_format("ANDI %s, %s, 0x%" PRIx64, rt3, rs3, eu);
2479 }
2480 
2481 
2482 /*
2483  *
2484  *
2485  *   3         2         1
2486  *  10987654321098765432109876543210
2487  *  001000               x1110000101
2488  *     rt -----
2489  *          rs -----
2490  *               rd -----
2491  */
2492 static char *ANDI_32_(uint64 instruction, Dis_info *info)
2493 {
2494     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2495     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2496     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
2497 
2498     const char *rt = GPR(rt_value, info);
2499     const char *rs = GPR(rs_value, info);
2500 
2501     return img_format("ANDI %s, %s, 0x%" PRIx64, rt, rs, u_value);
2502 }
2503 
2504 
2505 /*
2506  *
2507  *
2508  *   3         2         1
2509  *  10987654321098765432109876543210
2510  *  001000               x1110000101
2511  *     rt -----
2512  *          rs -----
2513  *               rd -----
2514  */
2515 static char *APPEND(uint64 instruction, Dis_info *info)
2516 {
2517     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2518     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2519     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
2520 
2521     const char *rt = GPR(rt_value, info);
2522     const char *rs = GPR(rs_value, info);
2523 
2524     return img_format("APPEND %s, %s, 0x%" PRIx64, rt, rs, sa_value);
2525 }
2526 
2527 
2528 /*
2529  *
2530  *
2531  *   3         2         1
2532  *  10987654321098765432109876543210
2533  *  001000               x1110000101
2534  *     rt -----
2535  *          rs -----
2536  *               rd -----
2537  */
2538 static char *ASET(uint64 instruction, Dis_info *info)
2539 {
2540     uint64 bit_value = extract_bit_23_22_21(instruction);
2541     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2542     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
2543 
2544     const char *rs = GPR(rs_value, info);
2545 
2546     return img_format("ASET 0x%" PRIx64 ", %" PRId64 "(%s)",
2547                       bit_value, s_value, rs);
2548 }
2549 
2550 
2551 /*
2552  *
2553  *
2554  *   3         2         1
2555  *  10987654321098765432109876543210
2556  *  001000               x1110000101
2557  *     rt -----
2558  *          rs -----
2559  *               rd -----
2560  */
2561 static char *BALC_16_(uint64 instruction, Dis_info *info)
2562 {
2563     int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction);
2564 
2565     g_autofree char *s = ADDRESS(s_value, 2, info);
2566 
2567     return img_format("BALC %s", s);
2568 }
2569 
2570 
2571 /*
2572  *
2573  *
2574  *   3         2         1
2575  *  10987654321098765432109876543210
2576  *  001000               x1110000101
2577  *     rt -----
2578  *          rs -----
2579  *               rd -----
2580  */
2581 static char *BALC_32_(uint64 instruction, Dis_info *info)
2582 {
2583     int64 s_value = extract_s__se25_0_24_to_1_s1(instruction);
2584 
2585     g_autofree char *s = ADDRESS(s_value, 4, info);
2586 
2587     return img_format("BALC %s", s);
2588 }
2589 
2590 
2591 /*
2592  *
2593  *
2594  *   3         2         1
2595  *  10987654321098765432109876543210
2596  *  001000               x1110000101
2597  *     rt -----
2598  *          rs -----
2599  *               rd -----
2600  */
2601 static char *BALRSC(uint64 instruction, Dis_info *info)
2602 {
2603     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2604     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2605 
2606     const char *rt = GPR(rt_value, info);
2607     const char *rs = GPR(rs_value, info);
2608 
2609     return img_format("BALRSC %s, %s", rt, rs);
2610 }
2611 
2612 
2613 /*
2614  *
2615  *
2616  *   3         2         1
2617  *  10987654321098765432109876543210
2618  *  001000               x1110000101
2619  *     rt -----
2620  *          rs -----
2621  *               rd -----
2622  */
2623 static char *BBEQZC(uint64 instruction, Dis_info *info)
2624 {
2625     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2626     uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction);
2627     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2628 
2629     const char *rt = GPR(rt_value, info);
2630     g_autofree char *s = ADDRESS(s_value, 4, info);
2631 
2632     return img_format("BBEQZC %s, 0x%" PRIx64 ", %s", rt, bit_value, s);
2633 }
2634 
2635 
2636 /*
2637  *
2638  *
2639  *   3         2         1
2640  *  10987654321098765432109876543210
2641  *  001000               x1110000101
2642  *     rt -----
2643  *          rs -----
2644  *               rd -----
2645  */
2646 static char *BBNEZC(uint64 instruction, Dis_info *info)
2647 {
2648     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2649     uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction);
2650     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2651 
2652     const char *rt = GPR(rt_value, info);
2653     g_autofree char *s = ADDRESS(s_value, 4, info);
2654 
2655     return img_format("BBNEZC %s, 0x%" PRIx64 ", %s", rt, bit_value, s);
2656 }
2657 
2658 
2659 /*
2660  *
2661  *
2662  *   3         2         1
2663  *  10987654321098765432109876543210
2664  *  001000               x1110000101
2665  *     rt -----
2666  *          rs -----
2667  *               rd -----
2668  */
2669 static char *BC_16_(uint64 instruction, Dis_info *info)
2670 {
2671     int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction);
2672 
2673     g_autofree char *s = ADDRESS(s_value, 2, info);
2674 
2675     return img_format("BC %s", s);
2676 }
2677 
2678 
2679 /*
2680  *
2681  *
2682  *   3         2         1
2683  *  10987654321098765432109876543210
2684  *  001000               x1110000101
2685  *     rt -----
2686  *          rs -----
2687  *               rd -----
2688  */
2689 static char *BC_32_(uint64 instruction, Dis_info *info)
2690 {
2691     int64 s_value = extract_s__se25_0_24_to_1_s1(instruction);
2692 
2693     g_autofree char *s = ADDRESS(s_value, 4, info);
2694 
2695     return img_format("BC %s", s);
2696 }
2697 
2698 
2699 /*
2700  *
2701  *
2702  *   3         2         1
2703  *  10987654321098765432109876543210
2704  *  001000               x1110000101
2705  *     rt -----
2706  *          rs -----
2707  *               rd -----
2708  */
2709 static char *BC1EQZC(uint64 instruction, Dis_info *info)
2710 {
2711     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
2712     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2713 
2714     const char *ft = FPR(ft_value, info);
2715     g_autofree char *s = ADDRESS(s_value, 4, info);
2716 
2717     return img_format("BC1EQZC %s, %s", ft, s);
2718 }
2719 
2720 
2721 /*
2722  *
2723  *
2724  *   3         2         1
2725  *  10987654321098765432109876543210
2726  *  001000               x1110000101
2727  *     rt -----
2728  *          rs -----
2729  *               rd -----
2730  */
2731 static char *BC1NEZC(uint64 instruction, Dis_info *info)
2732 {
2733     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
2734     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2735 
2736     const char *ft = FPR(ft_value, info);
2737     g_autofree char *s = ADDRESS(s_value, 4, info);
2738 
2739     return img_format("BC1NEZC %s, %s", ft, s);
2740 }
2741 
2742 
2743 /*
2744  *
2745  *
2746  *   3         2         1
2747  *  10987654321098765432109876543210
2748  *  001000               x1110000101
2749  *     rt -----
2750  *          rs -----
2751  *               rd -----
2752  */
2753 static char *BC2EQZC(uint64 instruction, Dis_info *info)
2754 {
2755     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
2756     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2757 
2758     g_autofree char *s = ADDRESS(s_value, 4, info);
2759 
2760     return img_format("BC2EQZC CP%" PRIu64 ", %s", ct_value, s);
2761 }
2762 
2763 
2764 /*
2765  *
2766  *
2767  *   3         2         1
2768  *  10987654321098765432109876543210
2769  *  001000               x1110000101
2770  *     rt -----
2771  *          rs -----
2772  *               rd -----
2773  */
2774 static char *BC2NEZC(uint64 instruction, Dis_info *info)
2775 {
2776     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
2777     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2778 
2779     g_autofree char *s = ADDRESS(s_value, 4, info);
2780 
2781     return img_format("BC2NEZC CP%" PRIu64 ", %s", ct_value, s);
2782 }
2783 
2784 
2785 /*
2786  *
2787  *
2788  *   3         2         1
2789  *  10987654321098765432109876543210
2790  *  001000               x1110000101
2791  *     rt -----
2792  *          rs -----
2793  *               rd -----
2794  */
2795 static char *BEQC_16_(uint64 instruction, Dis_info *info)
2796 {
2797     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2798     uint64 rs3_value = extract_rs3_6_5_4(instruction);
2799     uint64 u_value = extract_u_3_2_1_0__s1(instruction);
2800 
2801     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
2802     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
2803     g_autofree char *u = ADDRESS(u_value, 2, info);
2804 
2805     return img_format("BEQC %s, %s, %s", rs3, rt3, u);
2806 }
2807 
2808 
2809 /*
2810  *
2811  *
2812  *   3         2         1
2813  *  10987654321098765432109876543210
2814  *  001000               x1110000101
2815  *     rt -----
2816  *          rs -----
2817  *               rd -----
2818  */
2819 static char *BEQC_32_(uint64 instruction, Dis_info *info)
2820 {
2821     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2822     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2823     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2824 
2825     const char *rs = GPR(rs_value, info);
2826     const char *rt = GPR(rt_value, info);
2827     g_autofree char *s = ADDRESS(s_value, 4, info);
2828 
2829     return img_format("BEQC %s, %s, %s", rs, rt, s);
2830 }
2831 
2832 
2833 /*
2834  *
2835  *
2836  *   3         2         1
2837  *  10987654321098765432109876543210
2838  *  001000               x1110000101
2839  *     rt -----
2840  *          rs -----
2841  *               rd -----
2842  */
2843 static char *BEQIC(uint64 instruction, Dis_info *info)
2844 {
2845     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2846     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
2847     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2848 
2849     const char *rt = GPR(rt_value, info);
2850     g_autofree char *s = ADDRESS(s_value, 4, info);
2851 
2852     return img_format("BEQIC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
2853 }
2854 
2855 
2856 /*
2857  *
2858  *
2859  *   3         2         1
2860  *  10987654321098765432109876543210
2861  *  001000               x1110000101
2862  *     rt -----
2863  *          rs -----
2864  *               rd -----
2865  */
2866 static char *BEQZC_16_(uint64 instruction, Dis_info *info)
2867 {
2868     uint64 rt3_value = extract_rt3_9_8_7(instruction);
2869     int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction);
2870 
2871     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
2872     g_autofree char *s = ADDRESS(s_value, 2, info);
2873 
2874     return img_format("BEQZC %s, %s", rt3, s);
2875 }
2876 
2877 
2878 /*
2879  *
2880  *
2881  *   3         2         1
2882  *  10987654321098765432109876543210
2883  *  001000               x1110000101
2884  *     rt -----
2885  *          rs -----
2886  *               rd -----
2887  */
2888 static char *BGEC(uint64 instruction, Dis_info *info)
2889 {
2890     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2891     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2892     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2893 
2894     const char *rs = GPR(rs_value, info);
2895     const char *rt = GPR(rt_value, info);
2896     g_autofree char *s = ADDRESS(s_value, 4, info);
2897 
2898     return img_format("BGEC %s, %s, %s", rs, rt, s);
2899 }
2900 
2901 
2902 /*
2903  *
2904  *
2905  *   3         2         1
2906  *  10987654321098765432109876543210
2907  *  001000               x1110000101
2908  *     rt -----
2909  *          rs -----
2910  *               rd -----
2911  */
2912 static char *BGEIC(uint64 instruction, Dis_info *info)
2913 {
2914     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2915     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
2916     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2917 
2918     const char *rt = GPR(rt_value, info);
2919     g_autofree char *s = ADDRESS(s_value, 4, info);
2920 
2921     return img_format("BGEIC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
2922 }
2923 
2924 
2925 /*
2926  *
2927  *
2928  *   3         2         1
2929  *  10987654321098765432109876543210
2930  *  001000               x1110000101
2931  *     rt -----
2932  *          rs -----
2933  *               rd -----
2934  */
2935 static char *BGEIUC(uint64 instruction, Dis_info *info)
2936 {
2937     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2938     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
2939     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
2940 
2941     const char *rt = GPR(rt_value, info);
2942     g_autofree char *s = ADDRESS(s_value, 4, info);
2943 
2944     return img_format("BGEIUC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
2945 }
2946 
2947 
2948 /*
2949  *
2950  *
2951  *   3         2         1
2952  *  10987654321098765432109876543210
2953  *  001000               x1110000101
2954  *     rt -----
2955  *          rs -----
2956  *               rd -----
2957  */
2958 static char *BGEUC(uint64 instruction, Dis_info *info)
2959 {
2960     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2961     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2962     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2963 
2964     const char *rs = GPR(rs_value, info);
2965     const char *rt = GPR(rt_value, info);
2966     g_autofree char *s = ADDRESS(s_value, 4, info);
2967 
2968     return img_format("BGEUC %s, %s, %s", rs, rt, s);
2969 }
2970 
2971 
2972 /*
2973  *
2974  *
2975  *   3         2         1
2976  *  10987654321098765432109876543210
2977  *  001000               x1110000101
2978  *     rt -----
2979  *          rs -----
2980  *               rd -----
2981  */
2982 static char *BLTC(uint64 instruction, Dis_info *info)
2983 {
2984     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
2985     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
2986     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
2987 
2988     const char *rs = GPR(rs_value, info);
2989     const char *rt = GPR(rt_value, info);
2990     g_autofree char *s = ADDRESS(s_value, 4, info);
2991 
2992     return img_format("BLTC %s, %s, %s", rs, rt, s);
2993 }
2994 
2995 
2996 /*
2997  *
2998  *
2999  *   3         2         1
3000  *  10987654321098765432109876543210
3001  *  001000               x1110000101
3002  *     rt -----
3003  *          rs -----
3004  *               rd -----
3005  */
3006 static char *BLTIC(uint64 instruction, Dis_info *info)
3007 {
3008     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3009     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3010     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3011 
3012     const char *rt = GPR(rt_value, info);
3013     g_autofree char *s = ADDRESS(s_value, 4, info);
3014 
3015     return img_format("BLTIC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
3016 }
3017 
3018 
3019 /*
3020  *
3021  *
3022  *   3         2         1
3023  *  10987654321098765432109876543210
3024  *  001000               x1110000101
3025  *     rt -----
3026  *          rs -----
3027  *               rd -----
3028  */
3029 static char *BLTIUC(uint64 instruction, Dis_info *info)
3030 {
3031     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3032     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3033     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3034 
3035     const char *rt = GPR(rt_value, info);
3036     g_autofree char *s = ADDRESS(s_value, 4, info);
3037 
3038     return img_format("BLTIUC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
3039 }
3040 
3041 
3042 /*
3043  *
3044  *
3045  *   3         2         1
3046  *  10987654321098765432109876543210
3047  *  001000               x1110000101
3048  *     rt -----
3049  *          rs -----
3050  *               rd -----
3051  */
3052 static char *BLTUC(uint64 instruction, Dis_info *info)
3053 {
3054     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3055     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3056     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3057 
3058     const char *rs = GPR(rs_value, info);
3059     const char *rt = GPR(rt_value, info);
3060     g_autofree char *s = ADDRESS(s_value, 4, info);
3061 
3062     return img_format("BLTUC %s, %s, %s", rs, rt, s);
3063 }
3064 
3065 
3066 /*
3067  *
3068  *
3069  *   3         2         1
3070  *  10987654321098765432109876543210
3071  *  001000               x1110000101
3072  *     rt -----
3073  *          rs -----
3074  *               rd -----
3075  */
3076 static char *BNEC_16_(uint64 instruction, Dis_info *info)
3077 {
3078     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3079     uint64 rs3_value = extract_rs3_6_5_4(instruction);
3080     uint64 u_value = extract_u_3_2_1_0__s1(instruction);
3081 
3082     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
3083     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
3084     g_autofree char *u = ADDRESS(u_value, 2, info);
3085 
3086     return img_format("BNEC %s, %s, %s", rs3, rt3, u);
3087 }
3088 
3089 
3090 /*
3091  *
3092  *
3093  *   3         2         1
3094  *  10987654321098765432109876543210
3095  *  001000               x1110000101
3096  *     rt -----
3097  *          rs -----
3098  *               rd -----
3099  */
3100 static char *BNEC_32_(uint64 instruction, Dis_info *info)
3101 {
3102     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3103     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3104     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3105 
3106     const char *rs = GPR(rs_value, info);
3107     const char *rt = GPR(rt_value, info);
3108     g_autofree char *s = ADDRESS(s_value, 4, info);
3109 
3110     return img_format("BNEC %s, %s, %s", rs, rt, s);
3111 }
3112 
3113 
3114 /*
3115  *
3116  *
3117  *   3         2         1
3118  *  10987654321098765432109876543210
3119  *  001000               x1110000101
3120  *     rt -----
3121  *          rs -----
3122  *               rd -----
3123  */
3124 static char *BNEIC(uint64 instruction, Dis_info *info)
3125 {
3126     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3127     uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction);
3128     int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction);
3129 
3130     const char *rt = GPR(rt_value, info);
3131     g_autofree char *s = ADDRESS(s_value, 4, info);
3132 
3133     return img_format("BNEIC %s, 0x%" PRIx64 ", %s", rt, u_value, s);
3134 }
3135 
3136 
3137 /*
3138  *
3139  *
3140  *   3         2         1
3141  *  10987654321098765432109876543210
3142  *  001000               x1110000101
3143  *     rt -----
3144  *          rs -----
3145  *               rd -----
3146  */
3147 static char *BNEZC_16_(uint64 instruction, Dis_info *info)
3148 {
3149     uint64 rt3_value = extract_rt3_9_8_7(instruction);
3150     int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction);
3151 
3152     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
3153     g_autofree char *s = ADDRESS(s_value, 2, info);
3154 
3155     return img_format("BNEZC %s, %s", rt3, s);
3156 }
3157 
3158 
3159 /*
3160  * [DSP] BPOSGE32C offset - Branch on greater than or equal to value 32 in
3161  *   DSPControl Pos field
3162  *
3163  *   3         2         1
3164  *  10987654321098765432109876543210
3165  *  100010xxxxx0010001
3166  *            s[13:1] -------------
3167  *                           s[14] -
3168  */
3169 static char *BPOSGE32C(uint64 instruction, Dis_info *info)
3170 {
3171     int64 s_value = extract_s__se14_0_13_to_1_s1(instruction);
3172 
3173     g_autofree char *s = ADDRESS(s_value, 4, info);
3174 
3175     return img_format("BPOSGE32C %s", s);
3176 }
3177 
3178 
3179 /*
3180  *
3181  *
3182  *   3         2         1
3183  *  10987654321098765432109876543210
3184  *  001000               x1110000101
3185  *     rt -----
3186  *          rs -----
3187  *               rd -----
3188  */
3189 static char *BREAK_16_(uint64 instruction, Dis_info *info)
3190 {
3191     uint64 code_value = extract_code_2_1_0(instruction);
3192 
3193 
3194     return img_format("BREAK 0x%" PRIx64, code_value);
3195 }
3196 
3197 
3198 /*
3199  * BREAK code - Break. Cause a Breakpoint exception
3200  *
3201  *   3         2         1
3202  *  10987654321098765432109876543210
3203  *  001000               x1110000101
3204  *     rt -----
3205  *          rs -----
3206  *               rd -----
3207  */
3208 static char *BREAK_32_(uint64 instruction, Dis_info *info)
3209 {
3210     uint64 code_value = extract_code_18_to_0(instruction);
3211 
3212 
3213     return img_format("BREAK 0x%" PRIx64, code_value);
3214 }
3215 
3216 
3217 /*
3218  *
3219  *
3220  *   3         2         1
3221  *  10987654321098765432109876543210
3222  *  001000               x1110000101
3223  *     rt -----
3224  *          rs -----
3225  *               rd -----
3226  */
3227 static char *BRSC(uint64 instruction, Dis_info *info)
3228 {
3229     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3230 
3231     const char *rs = GPR(rs_value, info);
3232 
3233     return img_format("BRSC %s", rs);
3234 }
3235 
3236 
3237 /*
3238  *
3239  *
3240  *   3         2         1
3241  *  10987654321098765432109876543210
3242  *  001000               x1110000101
3243  *     rt -----
3244  *          rs -----
3245  *               rd -----
3246  */
3247 static char *CACHE(uint64 instruction, Dis_info *info)
3248 {
3249     uint64 op_value = extract_op_25_24_23_22_21(instruction);
3250     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3251     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
3252 
3253     const char *rs = GPR(rs_value, info);
3254 
3255     return img_format("CACHE 0x%" PRIx64 ", %s(%s)", op_value, s_value, rs);
3256 }
3257 
3258 
3259 /*
3260  *
3261  *
3262  *   3         2         1
3263  *  10987654321098765432109876543210
3264  *  001000               x1110000101
3265  *     rt -----
3266  *          rs -----
3267  *               rd -----
3268  */
3269 static char *CACHEE(uint64 instruction, Dis_info *info)
3270 {
3271     uint64 op_value = extract_op_25_24_23_22_21(instruction);
3272     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3273     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
3274 
3275     const char *rs = GPR(rs_value, info);
3276 
3277     return img_format("CACHEE 0x%" PRIx64 ", %s(%s)", op_value, s_value, rs);
3278 }
3279 
3280 
3281 /*
3282  *
3283  *
3284  *   3         2         1
3285  *  10987654321098765432109876543210
3286  *  001000               x1110000101
3287  *     rt -----
3288  *          rs -----
3289  *               rd -----
3290  */
3291 static char *CEIL_L_D(uint64 instruction, Dis_info *info)
3292 {
3293     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3294     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3295 
3296     const char *ft = FPR(ft_value, info);
3297     const char *fs = FPR(fs_value, info);
3298 
3299     return img_format("CEIL.L.D %s, %s", ft, fs);
3300 }
3301 
3302 
3303 /*
3304  *
3305  *
3306  *   3         2         1
3307  *  10987654321098765432109876543210
3308  *  001000               x1110000101
3309  *     rt -----
3310  *          rs -----
3311  *               rd -----
3312  */
3313 static char *CEIL_L_S(uint64 instruction, Dis_info *info)
3314 {
3315     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3316     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3317 
3318     const char *ft = FPR(ft_value, info);
3319     const char *fs = FPR(fs_value, info);
3320 
3321     return img_format("CEIL.L.S %s, %s", ft, fs);
3322 }
3323 
3324 
3325 /*
3326  *
3327  *
3328  *   3         2         1
3329  *  10987654321098765432109876543210
3330  *  001000               x1110000101
3331  *     rt -----
3332  *          rs -----
3333  *               rd -----
3334  */
3335 static char *CEIL_W_D(uint64 instruction, Dis_info *info)
3336 {
3337     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3338     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3339 
3340     const char *ft = FPR(ft_value, info);
3341     const char *fs = FPR(fs_value, info);
3342 
3343     return img_format("CEIL.W.D %s, %s", ft, fs);
3344 }
3345 
3346 
3347 /*
3348  *
3349  *
3350  *   3         2         1
3351  *  10987654321098765432109876543210
3352  *  001000               x1110000101
3353  *     rt -----
3354  *          rs -----
3355  *               rd -----
3356  */
3357 static char *CEIL_W_S(uint64 instruction, Dis_info *info)
3358 {
3359     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3360     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3361 
3362     const char *ft = FPR(ft_value, info);
3363     const char *fs = FPR(fs_value, info);
3364 
3365     return img_format("CEIL.W.S %s, %s", ft, fs);
3366 }
3367 
3368 
3369 /*
3370  *
3371  *
3372  *   3         2         1
3373  *  10987654321098765432109876543210
3374  *  001000               x1110000101
3375  *     rt -----
3376  *          rs -----
3377  *               rd -----
3378  */
3379 static char *CFC1(uint64 instruction, Dis_info *info)
3380 {
3381     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3382     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
3383 
3384     const char *rt = GPR(rt_value, info);
3385 
3386     return img_format("CFC1 %s, CP%" PRIu64, rt, cs_value);
3387 }
3388 
3389 
3390 /*
3391  *
3392  *
3393  *   3         2         1
3394  *  10987654321098765432109876543210
3395  *  001000               x1110000101
3396  *     rt -----
3397  *          rs -----
3398  *               rd -----
3399  */
3400 static char *CFC2(uint64 instruction, Dis_info *info)
3401 {
3402     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3403     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
3404 
3405     const char *rt = GPR(rt_value, info);
3406 
3407     return img_format("CFC2 %s, CP%" PRIu64, rt, cs_value);
3408 }
3409 
3410 
3411 /*
3412  *
3413  *
3414  *   3         2         1
3415  *  10987654321098765432109876543210
3416  *  001000               x1110000101
3417  *     rt -----
3418  *          rs -----
3419  *               rd -----
3420  */
3421 static char *CLASS_D(uint64 instruction, Dis_info *info)
3422 {
3423     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3424     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3425 
3426     const char *ft = FPR(ft_value, info);
3427     const char *fs = FPR(fs_value, info);
3428 
3429     return img_format("CLASS.D %s, %s", ft, fs);
3430 }
3431 
3432 
3433 /*
3434  *
3435  *
3436  *   3         2         1
3437  *  10987654321098765432109876543210
3438  *  001000               x1110000101
3439  *     rt -----
3440  *          rs -----
3441  *               rd -----
3442  */
3443 static char *CLASS_S(uint64 instruction, Dis_info *info)
3444 {
3445     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3446     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3447 
3448     const char *ft = FPR(ft_value, info);
3449     const char *fs = FPR(fs_value, info);
3450 
3451     return img_format("CLASS.S %s, %s", ft, fs);
3452 }
3453 
3454 
3455 /*
3456  *
3457  *
3458  *   3         2         1
3459  *  10987654321098765432109876543210
3460  *  001000               x1110000101
3461  *     rt -----
3462  *          rs -----
3463  *               rd -----
3464  */
3465 static char *CLO(uint64 instruction, Dis_info *info)
3466 {
3467     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3468     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3469 
3470     const char *rt = GPR(rt_value, info);
3471     const char *rs = GPR(rs_value, info);
3472 
3473     return img_format("CLO %s, %s", rt, rs);
3474 }
3475 
3476 
3477 /*
3478  *
3479  *
3480  *   3         2         1
3481  *  10987654321098765432109876543210
3482  *  001000               x1110000101
3483  *     rt -----
3484  *          rs -----
3485  *               rd -----
3486  */
3487 static char *CLZ(uint64 instruction, Dis_info *info)
3488 {
3489     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3490     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3491 
3492     const char *rt = GPR(rt_value, info);
3493     const char *rs = GPR(rs_value, info);
3494 
3495     return img_format("CLZ %s, %s", rt, rs);
3496 }
3497 
3498 
3499 /*
3500  *
3501  *
3502  *   3         2         1
3503  *  10987654321098765432109876543210
3504  *  001000               x1110000101
3505  *     rt -----
3506  *          rs -----
3507  *               rd -----
3508  */
3509 static char *CMP_AF_D(uint64 instruction, Dis_info *info)
3510 {
3511     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3512     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3513     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3514 
3515     const char *fd = FPR(fd_value, info);
3516     const char *fs = FPR(fs_value, info);
3517     const char *ft = FPR(ft_value, info);
3518 
3519     return img_format("CMP.AF.D %s, %s, %s", fd, fs, ft);
3520 }
3521 
3522 
3523 /*
3524  *
3525  *
3526  *   3         2         1
3527  *  10987654321098765432109876543210
3528  *  001000               x1110000101
3529  *     rt -----
3530  *          rs -----
3531  *               rd -----
3532  */
3533 static char *CMP_AF_S(uint64 instruction, Dis_info *info)
3534 {
3535     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3536     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3537     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3538 
3539     const char *fd = FPR(fd_value, info);
3540     const char *fs = FPR(fs_value, info);
3541     const char *ft = FPR(ft_value, info);
3542 
3543     return img_format("CMP.AF.S %s, %s, %s", fd, fs, ft);
3544 }
3545 
3546 
3547 /*
3548  *
3549  *
3550  *   3         2         1
3551  *  10987654321098765432109876543210
3552  *  001000               x1110000101
3553  *     rt -----
3554  *          rs -----
3555  *               rd -----
3556  */
3557 static char *CMP_EQ_D(uint64 instruction, Dis_info *info)
3558 {
3559     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3560     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3561     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3562 
3563     const char *fd = FPR(fd_value, info);
3564     const char *fs = FPR(fs_value, info);
3565     const char *ft = FPR(ft_value, info);
3566 
3567     return img_format("CMP.EQ.D %s, %s, %s", fd, fs, ft);
3568 }
3569 
3570 
3571 /*
3572  * [DSP] CMP.EQ.PH rs, rt - Compare vectors of signed integer halfword values
3573  *
3574  *   3         2         1
3575  *  10987654321098765432109876543210
3576  *  001000          xxxxxx0000000101
3577  *     rt -----
3578  *          rs -----
3579  */
3580 static char *CMP_EQ_PH(uint64 instruction, Dis_info *info)
3581 {
3582     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3583     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3584 
3585     const char *rs = GPR(rs_value, info);
3586     const char *rt = GPR(rt_value, info);
3587 
3588     return img_format("CMP.EQ.PH %s, %s", rs, rt);
3589 }
3590 
3591 
3592 /*
3593  *
3594  *
3595  *   3         2         1
3596  *  10987654321098765432109876543210
3597  *  001000               x1110000101
3598  *     rt -----
3599  *          rs -----
3600  *               rd -----
3601  */
3602 static char *CMP_EQ_S(uint64 instruction, Dis_info *info)
3603 {
3604     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3605     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3606     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3607 
3608     const char *fd = FPR(fd_value, info);
3609     const char *fs = FPR(fs_value, info);
3610     const char *ft = FPR(ft_value, info);
3611 
3612     return img_format("CMP.EQ.S %s, %s, %s", fd, fs, ft);
3613 }
3614 
3615 
3616 /*
3617  *
3618  *
3619  *   3         2         1
3620  *  10987654321098765432109876543210
3621  *  001000               x1110000101
3622  *     rt -----
3623  *          rs -----
3624  *               rd -----
3625  */
3626 static char *CMP_LE_D(uint64 instruction, Dis_info *info)
3627 {
3628     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3629     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3630     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3631 
3632     const char *fd = FPR(fd_value, info);
3633     const char *fs = FPR(fs_value, info);
3634     const char *ft = FPR(ft_value, info);
3635 
3636     return img_format("CMP.LE.D %s, %s, %s", fd, fs, ft);
3637 }
3638 
3639 
3640 /*
3641  * [DSP] CMP.LE.PH rs, rt - Compare vectors of signed integer halfword values
3642  *
3643  *   3         2         1
3644  *  10987654321098765432109876543210
3645  *  001000          xxxxxx0010000101
3646  *     rt -----
3647  *          rs -----
3648  */
3649 static char *CMP_LE_PH(uint64 instruction, Dis_info *info)
3650 {
3651     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3652     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3653 
3654     const char *rs = GPR(rs_value, info);
3655     const char *rt = GPR(rt_value, info);
3656 
3657     return img_format("CMP.LE.PH %s, %s", rs, rt);
3658 }
3659 
3660 
3661 /*
3662  *
3663  *
3664  *   3         2         1
3665  *  10987654321098765432109876543210
3666  *  001000               x1110000101
3667  *     rt -----
3668  *          rs -----
3669  *               rd -----
3670  */
3671 static char *CMP_LE_S(uint64 instruction, Dis_info *info)
3672 {
3673     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3674     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3675     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3676 
3677     const char *fd = FPR(fd_value, info);
3678     const char *fs = FPR(fs_value, info);
3679     const char *ft = FPR(ft_value, info);
3680 
3681     return img_format("CMP.LE.S %s, %s, %s", fd, fs, ft);
3682 }
3683 
3684 
3685 /*
3686  *
3687  *
3688  *   3         2         1
3689  *  10987654321098765432109876543210
3690  *  001000               x1110000101
3691  *     rt -----
3692  *          rs -----
3693  *               rd -----
3694  */
3695 static char *CMP_LT_D(uint64 instruction, Dis_info *info)
3696 {
3697     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3698     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3699     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3700 
3701     const char *fd = FPR(fd_value, info);
3702     const char *fs = FPR(fs_value, info);
3703     const char *ft = FPR(ft_value, info);
3704 
3705     return img_format("CMP.LT.D %s, %s, %s", fd, fs, ft);
3706 }
3707 
3708 
3709 /*
3710  * [DSP] CMP.LT.PH rs, rt - Compare vectors of signed integer halfword values
3711  *
3712  *   3         2         1
3713  *  10987654321098765432109876543210
3714  *  001000          xxxxxx0001000101
3715  *     rt -----
3716  *          rs -----
3717  */
3718 static char *CMP_LT_PH(uint64 instruction, Dis_info *info)
3719 {
3720     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
3721     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
3722 
3723     const char *rs = GPR(rs_value, info);
3724     const char *rt = GPR(rt_value, info);
3725 
3726     return img_format("CMP.LT.PH %s, %s", rs, rt);
3727 }
3728 
3729 
3730 /*
3731  *
3732  *
3733  *   3         2         1
3734  *  10987654321098765432109876543210
3735  *  001000               x1110000101
3736  *     rt -----
3737  *          rs -----
3738  *               rd -----
3739  */
3740 static char *CMP_LT_S(uint64 instruction, Dis_info *info)
3741 {
3742     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3743     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3744     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3745 
3746     const char *fd = FPR(fd_value, info);
3747     const char *fs = FPR(fs_value, info);
3748     const char *ft = FPR(ft_value, info);
3749 
3750     return img_format("CMP.LT.S %s, %s, %s", fd, fs, ft);
3751 }
3752 
3753 
3754 /*
3755  *
3756  *
3757  *   3         2         1
3758  *  10987654321098765432109876543210
3759  *  001000               x1110000101
3760  *     rt -----
3761  *          rs -----
3762  *               rd -----
3763  */
3764 static char *CMP_NE_D(uint64 instruction, Dis_info *info)
3765 {
3766     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3767     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3768     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3769 
3770     const char *fd = FPR(fd_value, info);
3771     const char *fs = FPR(fs_value, info);
3772     const char *ft = FPR(ft_value, info);
3773 
3774     return img_format("CMP.NE.D %s, %s, %s", fd, fs, ft);
3775 }
3776 
3777 
3778 /*
3779  *
3780  *
3781  *   3         2         1
3782  *  10987654321098765432109876543210
3783  *  001000               x1110000101
3784  *     rt -----
3785  *          rs -----
3786  *               rd -----
3787  */
3788 static char *CMP_NE_S(uint64 instruction, Dis_info *info)
3789 {
3790     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3791     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3792     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3793 
3794     const char *fd = FPR(fd_value, info);
3795     const char *fs = FPR(fs_value, info);
3796     const char *ft = FPR(ft_value, info);
3797 
3798     return img_format("CMP.NE.S %s, %s, %s", fd, fs, ft);
3799 }
3800 
3801 
3802 /*
3803  *
3804  *
3805  *   3         2         1
3806  *  10987654321098765432109876543210
3807  *  001000               x1110000101
3808  *     rt -----
3809  *          rs -----
3810  *               rd -----
3811  */
3812 static char *CMP_OR_D(uint64 instruction, Dis_info *info)
3813 {
3814     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3815     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3816     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3817 
3818     const char *fd = FPR(fd_value, info);
3819     const char *fs = FPR(fs_value, info);
3820     const char *ft = FPR(ft_value, info);
3821 
3822     return img_format("CMP.OR.D %s, %s, %s", fd, fs, ft);
3823 }
3824 
3825 
3826 /*
3827  *
3828  *
3829  *   3         2         1
3830  *  10987654321098765432109876543210
3831  *  001000               x1110000101
3832  *     rt -----
3833  *          rs -----
3834  *               rd -----
3835  */
3836 static char *CMP_OR_S(uint64 instruction, Dis_info *info)
3837 {
3838     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3839     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3840     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3841 
3842     const char *fd = FPR(fd_value, info);
3843     const char *fs = FPR(fs_value, info);
3844     const char *ft = FPR(ft_value, info);
3845 
3846     return img_format("CMP.OR.S %s, %s, %s", fd, fs, ft);
3847 }
3848 
3849 
3850 /*
3851  *
3852  *
3853  *   3         2         1
3854  *  10987654321098765432109876543210
3855  *  001000               x1110000101
3856  *     rt -----
3857  *          rs -----
3858  *               rd -----
3859  */
3860 static char *CMP_SAF_D(uint64 instruction, Dis_info *info)
3861 {
3862     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3863     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3864     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3865 
3866     const char *fd = FPR(fd_value, info);
3867     const char *fs = FPR(fs_value, info);
3868     const char *ft = FPR(ft_value, info);
3869 
3870     return img_format("CMP.SAF.D %s, %s, %s", fd, fs, ft);
3871 }
3872 
3873 
3874 /*
3875  *
3876  *
3877  *   3         2         1
3878  *  10987654321098765432109876543210
3879  *  001000               x1110000101
3880  *     rt -----
3881  *          rs -----
3882  *               rd -----
3883  */
3884 static char *CMP_SAF_S(uint64 instruction, Dis_info *info)
3885 {
3886     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3887     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3888     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3889 
3890     const char *fd = FPR(fd_value, info);
3891     const char *fs = FPR(fs_value, info);
3892     const char *ft = FPR(ft_value, info);
3893 
3894     return img_format("CMP.SAF.S %s, %s, %s", fd, fs, ft);
3895 }
3896 
3897 
3898 /*
3899  *
3900  *
3901  *   3         2         1
3902  *  10987654321098765432109876543210
3903  *  001000               x1110000101
3904  *     rt -----
3905  *          rs -----
3906  *               rd -----
3907  */
3908 static char *CMP_SEQ_D(uint64 instruction, Dis_info *info)
3909 {
3910     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3911     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3912     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3913 
3914     const char *fd = FPR(fd_value, info);
3915     const char *fs = FPR(fs_value, info);
3916     const char *ft = FPR(ft_value, info);
3917 
3918     return img_format("CMP.SEQ.D %s, %s, %s", fd, fs, ft);
3919 }
3920 
3921 
3922 /*
3923  *
3924  *
3925  *   3         2         1
3926  *  10987654321098765432109876543210
3927  *  001000               x1110000101
3928  *     rt -----
3929  *          rs -----
3930  *               rd -----
3931  */
3932 static char *CMP_SEQ_S(uint64 instruction, Dis_info *info)
3933 {
3934     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3935     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3936     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3937 
3938     const char *fd = FPR(fd_value, info);
3939     const char *fs = FPR(fs_value, info);
3940     const char *ft = FPR(ft_value, info);
3941 
3942     return img_format("CMP.SEQ.S %s, %s, %s", fd, fs, ft);
3943 }
3944 
3945 
3946 /*
3947  *
3948  *
3949  *   3         2         1
3950  *  10987654321098765432109876543210
3951  *  001000               x1110000101
3952  *     rt -----
3953  *          rs -----
3954  *               rd -----
3955  */
3956 static char *CMP_SLE_D(uint64 instruction, Dis_info *info)
3957 {
3958     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3959     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3960     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3961 
3962     const char *fd = FPR(fd_value, info);
3963     const char *fs = FPR(fs_value, info);
3964     const char *ft = FPR(ft_value, info);
3965 
3966     return img_format("CMP.SLE.D %s, %s, %s", fd, fs, ft);
3967 }
3968 
3969 
3970 /*
3971  *
3972  *
3973  *   3         2         1
3974  *  10987654321098765432109876543210
3975  *  001000               x1110000101
3976  *     rt -----
3977  *          rs -----
3978  *               rd -----
3979  */
3980 static char *CMP_SLE_S(uint64 instruction, Dis_info *info)
3981 {
3982     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
3983     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
3984     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
3985 
3986     const char *fd = FPR(fd_value, info);
3987     const char *fs = FPR(fs_value, info);
3988     const char *ft = FPR(ft_value, info);
3989 
3990     return img_format("CMP.SLE.S %s, %s, %s", fd, fs, ft);
3991 }
3992 
3993 
3994 /*
3995  *
3996  *
3997  *   3         2         1
3998  *  10987654321098765432109876543210
3999  *  001000               x1110000101
4000  *     rt -----
4001  *          rs -----
4002  *               rd -----
4003  */
4004 static char *CMP_SLT_D(uint64 instruction, Dis_info *info)
4005 {
4006     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4007     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4008     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4009 
4010     const char *fd = FPR(fd_value, info);
4011     const char *fs = FPR(fs_value, info);
4012     const char *ft = FPR(ft_value, info);
4013 
4014     return img_format("CMP.SLT.D %s, %s, %s", fd, fs, ft);
4015 }
4016 
4017 
4018 /*
4019  *
4020  *
4021  *   3         2         1
4022  *  10987654321098765432109876543210
4023  *  001000               x1110000101
4024  *     rt -----
4025  *          rs -----
4026  *               rd -----
4027  */
4028 static char *CMP_SLT_S(uint64 instruction, Dis_info *info)
4029 {
4030     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4031     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4032     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4033 
4034     const char *fd = FPR(fd_value, info);
4035     const char *fs = FPR(fs_value, info);
4036     const char *ft = FPR(ft_value, info);
4037 
4038     return img_format("CMP.SLT.S %s, %s, %s", fd, fs, ft);
4039 }
4040 
4041 
4042 /*
4043  *
4044  *
4045  *   3         2         1
4046  *  10987654321098765432109876543210
4047  *  001000               x1110000101
4048  *     rt -----
4049  *          rs -----
4050  *               rd -----
4051  */
4052 static char *CMP_SNE_D(uint64 instruction, Dis_info *info)
4053 {
4054     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4055     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4056     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4057 
4058     const char *fd = FPR(fd_value, info);
4059     const char *fs = FPR(fs_value, info);
4060     const char *ft = FPR(ft_value, info);
4061 
4062     return img_format("CMP.SNE.D %s, %s, %s", fd, fs, ft);
4063 }
4064 
4065 
4066 /*
4067  *
4068  *
4069  *   3         2         1
4070  *  10987654321098765432109876543210
4071  *  001000               x1110000101
4072  *     rt -----
4073  *          rs -----
4074  *               rd -----
4075  */
4076 static char *CMP_SNE_S(uint64 instruction, Dis_info *info)
4077 {
4078     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4079     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4080     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4081 
4082     const char *fd = FPR(fd_value, info);
4083     const char *fs = FPR(fs_value, info);
4084     const char *ft = FPR(ft_value, info);
4085 
4086     return img_format("CMP.SNE.S %s, %s, %s", fd, fs, ft);
4087 }
4088 
4089 
4090 /*
4091  *
4092  *
4093  *   3         2         1
4094  *  10987654321098765432109876543210
4095  *  001000               x1110000101
4096  *     rt -----
4097  *          rs -----
4098  *               rd -----
4099  */
4100 static char *CMP_SOR_D(uint64 instruction, Dis_info *info)
4101 {
4102     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4103     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4104     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4105 
4106     const char *fd = FPR(fd_value, info);
4107     const char *fs = FPR(fs_value, info);
4108     const char *ft = FPR(ft_value, info);
4109 
4110     return img_format("CMP.SOR.D %s, %s, %s", fd, fs, ft);
4111 }
4112 
4113 
4114 /*
4115  *
4116  *
4117  *   3         2         1
4118  *  10987654321098765432109876543210
4119  *  001000               x1110000101
4120  *     rt -----
4121  *          rs -----
4122  *               rd -----
4123  */
4124 static char *CMP_SOR_S(uint64 instruction, Dis_info *info)
4125 {
4126     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4127     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4128     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4129 
4130     const char *fd = FPR(fd_value, info);
4131     const char *fs = FPR(fs_value, info);
4132     const char *ft = FPR(ft_value, info);
4133 
4134     return img_format("CMP.SOR.S %s, %s, %s", fd, fs, ft);
4135 }
4136 
4137 
4138 /*
4139  *
4140  *
4141  *   3         2         1
4142  *  10987654321098765432109876543210
4143  *  001000               x1110000101
4144  *     rt -----
4145  *          rs -----
4146  *               rd -----
4147  */
4148 static char *CMP_SUEQ_D(uint64 instruction, Dis_info *info)
4149 {
4150     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4151     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4152     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4153 
4154     const char *fd = FPR(fd_value, info);
4155     const char *fs = FPR(fs_value, info);
4156     const char *ft = FPR(ft_value, info);
4157 
4158     return img_format("CMP.SUEQ.D %s, %s, %s", fd, fs, ft);
4159 }
4160 
4161 
4162 /*
4163  *
4164  *
4165  *   3         2         1
4166  *  10987654321098765432109876543210
4167  *  001000               x1110000101
4168  *     rt -----
4169  *          rs -----
4170  *               rd -----
4171  */
4172 static char *CMP_SUEQ_S(uint64 instruction, Dis_info *info)
4173 {
4174     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4175     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4176     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4177 
4178     const char *fd = FPR(fd_value, info);
4179     const char *fs = FPR(fs_value, info);
4180     const char *ft = FPR(ft_value, info);
4181 
4182     return img_format("CMP.SUEQ.S %s, %s, %s", fd, fs, ft);
4183 }
4184 
4185 
4186 /*
4187  *
4188  *
4189  *   3         2         1
4190  *  10987654321098765432109876543210
4191  *  001000               x1110000101
4192  *     rt -----
4193  *          rs -----
4194  *               rd -----
4195  */
4196 static char *CMP_SULE_D(uint64 instruction, Dis_info *info)
4197 {
4198     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4199     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4200     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4201 
4202     const char *fd = FPR(fd_value, info);
4203     const char *fs = FPR(fs_value, info);
4204     const char *ft = FPR(ft_value, info);
4205 
4206     return img_format("CMP.SULE.D %s, %s, %s", fd, fs, ft);
4207 }
4208 
4209 
4210 /*
4211  *
4212  *
4213  *   3         2         1
4214  *  10987654321098765432109876543210
4215  *  001000               x1110000101
4216  *     rt -----
4217  *          rs -----
4218  *               rd -----
4219  */
4220 static char *CMP_SULE_S(uint64 instruction, Dis_info *info)
4221 {
4222     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4223     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4224     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4225 
4226     const char *fd = FPR(fd_value, info);
4227     const char *fs = FPR(fs_value, info);
4228     const char *ft = FPR(ft_value, info);
4229 
4230     return img_format("CMP.SULE.S %s, %s, %s", fd, fs, ft);
4231 }
4232 
4233 
4234 /*
4235  *
4236  *
4237  *   3         2         1
4238  *  10987654321098765432109876543210
4239  *  001000               x1110000101
4240  *     rt -----
4241  *          rs -----
4242  *               rd -----
4243  */
4244 static char *CMP_SULT_D(uint64 instruction, Dis_info *info)
4245 {
4246     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4247     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4248     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4249 
4250     const char *fd = FPR(fd_value, info);
4251     const char *fs = FPR(fs_value, info);
4252     const char *ft = FPR(ft_value, info);
4253 
4254     return img_format("CMP.SULT.D %s, %s, %s", fd, fs, ft);
4255 }
4256 
4257 
4258 /*
4259  *
4260  *
4261  *   3         2         1
4262  *  10987654321098765432109876543210
4263  *  001000               x1110000101
4264  *     rt -----
4265  *          rs -----
4266  *               rd -----
4267  */
4268 static char *CMP_SULT_S(uint64 instruction, Dis_info *info)
4269 {
4270     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4271     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4272     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4273 
4274     const char *fd = FPR(fd_value, info);
4275     const char *fs = FPR(fs_value, info);
4276     const char *ft = FPR(ft_value, info);
4277 
4278     return img_format("CMP.SULT.S %s, %s, %s", fd, fs, ft);
4279 }
4280 
4281 
4282 /*
4283  *
4284  *
4285  *   3         2         1
4286  *  10987654321098765432109876543210
4287  *  001000               x1110000101
4288  *     rt -----
4289  *          rs -----
4290  *               rd -----
4291  */
4292 static char *CMP_SUN_D(uint64 instruction, Dis_info *info)
4293 {
4294     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4295     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4296     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4297 
4298     const char *fd = FPR(fd_value, info);
4299     const char *fs = FPR(fs_value, info);
4300     const char *ft = FPR(ft_value, info);
4301 
4302     return img_format("CMP.SUN.D %s, %s, %s", fd, fs, ft);
4303 }
4304 
4305 
4306 /*
4307  *
4308  *
4309  *   3         2         1
4310  *  10987654321098765432109876543210
4311  *  001000               x1110000101
4312  *     rt -----
4313  *          rs -----
4314  *               rd -----
4315  */
4316 static char *CMP_SUNE_D(uint64 instruction, Dis_info *info)
4317 {
4318     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4319     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4320     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4321 
4322     const char *fd = FPR(fd_value, info);
4323     const char *fs = FPR(fs_value, info);
4324     const char *ft = FPR(ft_value, info);
4325 
4326     return img_format("CMP.SUNE.D %s, %s, %s", fd, fs, ft);
4327 }
4328 
4329 
4330 /*
4331  *
4332  *
4333  *   3         2         1
4334  *  10987654321098765432109876543210
4335  *  001000               x1110000101
4336  *     rt -----
4337  *          rs -----
4338  *               rd -----
4339  */
4340 static char *CMP_SUNE_S(uint64 instruction, Dis_info *info)
4341 {
4342     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4343     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4344     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4345 
4346     const char *fd = FPR(fd_value, info);
4347     const char *fs = FPR(fs_value, info);
4348     const char *ft = FPR(ft_value, info);
4349 
4350     return img_format("CMP.SUNE.S %s, %s, %s", fd, fs, ft);
4351 }
4352 
4353 
4354 /*
4355  *
4356  *
4357  *   3         2         1
4358  *  10987654321098765432109876543210
4359  *  001000               x1110000101
4360  *     rt -----
4361  *          rs -----
4362  *               rd -----
4363  */
4364 static char *CMP_SUN_S(uint64 instruction, Dis_info *info)
4365 {
4366     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4367     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4368     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4369 
4370     const char *fd = FPR(fd_value, info);
4371     const char *fs = FPR(fs_value, info);
4372     const char *ft = FPR(ft_value, info);
4373 
4374     return img_format("CMP.SUN.S %s, %s, %s", fd, fs, ft);
4375 }
4376 
4377 
4378 /*
4379  *
4380  *
4381  *   3         2         1
4382  *  10987654321098765432109876543210
4383  *  001000               x1110000101
4384  *     rt -----
4385  *          rs -----
4386  *               rd -----
4387  */
4388 static char *CMP_UEQ_D(uint64 instruction, Dis_info *info)
4389 {
4390     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4391     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4392     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4393 
4394     const char *fd = FPR(fd_value, info);
4395     const char *fs = FPR(fs_value, info);
4396     const char *ft = FPR(ft_value, info);
4397 
4398     return img_format("CMP.UEQ.D %s, %s, %s", fd, fs, ft);
4399 }
4400 
4401 
4402 /*
4403  *
4404  *
4405  *   3         2         1
4406  *  10987654321098765432109876543210
4407  *  001000               x1110000101
4408  *     rt -----
4409  *          rs -----
4410  *               rd -----
4411  */
4412 static char *CMP_UEQ_S(uint64 instruction, Dis_info *info)
4413 {
4414     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4415     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4416     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4417 
4418     const char *fd = FPR(fd_value, info);
4419     const char *fs = FPR(fs_value, info);
4420     const char *ft = FPR(ft_value, info);
4421 
4422     return img_format("CMP.UEQ.S %s, %s, %s", fd, fs, ft);
4423 }
4424 
4425 
4426 /*
4427  *
4428  *
4429  *   3         2         1
4430  *  10987654321098765432109876543210
4431  *  001000               x1110000101
4432  *     rt -----
4433  *          rs -----
4434  *               rd -----
4435  */
4436 static char *CMP_ULE_D(uint64 instruction, Dis_info *info)
4437 {
4438     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4439     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4440     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4441 
4442     const char *fd = FPR(fd_value, info);
4443     const char *fs = FPR(fs_value, info);
4444     const char *ft = FPR(ft_value, info);
4445 
4446     return img_format("CMP.ULE.D %s, %s, %s", fd, fs, ft);
4447 }
4448 
4449 
4450 /*
4451  *
4452  *
4453  *   3         2         1
4454  *  10987654321098765432109876543210
4455  *  001000               x1110000101
4456  *     rt -----
4457  *          rs -----
4458  *               rd -----
4459  */
4460 static char *CMP_ULE_S(uint64 instruction, Dis_info *info)
4461 {
4462     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4463     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4464     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4465 
4466     const char *fd = FPR(fd_value, info);
4467     const char *fs = FPR(fs_value, info);
4468     const char *ft = FPR(ft_value, info);
4469 
4470     return img_format("CMP.ULE.S %s, %s, %s", fd, fs, ft);
4471 }
4472 
4473 
4474 /*
4475  *
4476  *
4477  *   3         2         1
4478  *  10987654321098765432109876543210
4479  *  001000               x1110000101
4480  *     rt -----
4481  *          rs -----
4482  *               rd -----
4483  */
4484 static char *CMP_ULT_D(uint64 instruction, Dis_info *info)
4485 {
4486     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4487     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4488     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4489 
4490     const char *fd = FPR(fd_value, info);
4491     const char *fs = FPR(fs_value, info);
4492     const char *ft = FPR(ft_value, info);
4493 
4494     return img_format("CMP.ULT.D %s, %s, %s", fd, fs, ft);
4495 }
4496 
4497 
4498 /*
4499  *
4500  *
4501  *   3         2         1
4502  *  10987654321098765432109876543210
4503  *  001000               x1110000101
4504  *     rt -----
4505  *          rs -----
4506  *               rd -----
4507  */
4508 static char *CMP_ULT_S(uint64 instruction, Dis_info *info)
4509 {
4510     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4511     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4512     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4513 
4514     const char *fd = FPR(fd_value, info);
4515     const char *fs = FPR(fs_value, info);
4516     const char *ft = FPR(ft_value, info);
4517 
4518     return img_format("CMP.ULT.S %s, %s, %s", fd, fs, ft);
4519 }
4520 
4521 
4522 /*
4523  *
4524  *
4525  *   3         2         1
4526  *  10987654321098765432109876543210
4527  *  001000               x1110000101
4528  *     rt -----
4529  *          rs -----
4530  *               rd -----
4531  */
4532 static char *CMP_UN_D(uint64 instruction, Dis_info *info)
4533 {
4534     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4535     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4536     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4537 
4538     const char *fd = FPR(fd_value, info);
4539     const char *fs = FPR(fs_value, info);
4540     const char *ft = FPR(ft_value, info);
4541 
4542     return img_format("CMP.UN.D %s, %s, %s", fd, fs, ft);
4543 }
4544 
4545 
4546 /*
4547  *
4548  *
4549  *   3         2         1
4550  *  10987654321098765432109876543210
4551  *  001000               x1110000101
4552  *     rt -----
4553  *          rs -----
4554  *               rd -----
4555  */
4556 static char *CMP_UNE_D(uint64 instruction, Dis_info *info)
4557 {
4558     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4559     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4560     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4561 
4562     const char *fd = FPR(fd_value, info);
4563     const char *fs = FPR(fs_value, info);
4564     const char *ft = FPR(ft_value, info);
4565 
4566     return img_format("CMP.UNE.D %s, %s, %s", fd, fs, ft);
4567 }
4568 
4569 
4570 /*
4571  *
4572  *
4573  *   3         2         1
4574  *  10987654321098765432109876543210
4575  *  001000               x1110000101
4576  *     rt -----
4577  *          rs -----
4578  *               rd -----
4579  */
4580 static char *CMP_UNE_S(uint64 instruction, Dis_info *info)
4581 {
4582     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4583     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4584     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4585 
4586     const char *fd = FPR(fd_value, info);
4587     const char *fs = FPR(fs_value, info);
4588     const char *ft = FPR(ft_value, info);
4589 
4590     return img_format("CMP.UNE.S %s, %s, %s", fd, fs, ft);
4591 }
4592 
4593 
4594 /*
4595  *
4596  *
4597  *   3         2         1
4598  *  10987654321098765432109876543210
4599  *  001000               x1110000101
4600  *     rt -----
4601  *          rs -----
4602  *               rd -----
4603  */
4604 static char *CMP_UN_S(uint64 instruction, Dis_info *info)
4605 {
4606     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4607     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4608     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
4609 
4610     const char *fd = FPR(fd_value, info);
4611     const char *fs = FPR(fs_value, info);
4612     const char *ft = FPR(ft_value, info);
4613 
4614     return img_format("CMP.UN.S %s, %s, %s", fd, fs, ft);
4615 }
4616 
4617 
4618 /*
4619  * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of
4620  *   four bytes and write result to GPR and DSPControl
4621  *
4622  *   3         2         1
4623  *  10987654321098765432109876543210
4624  *  001000               x0110000101
4625  *     rt -----
4626  *          rs -----
4627  *               rd -----
4628  */
4629 static char *CMPGDU_EQ_QB(uint64 instruction, Dis_info *info)
4630 {
4631     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4632     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4633     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4634 
4635     const char *rd = GPR(rd_value, info);
4636     const char *rs = GPR(rs_value, info);
4637     const char *rt = GPR(rt_value, info);
4638 
4639     return img_format("CMPGDU.EQ.QB %s, %s, %s", rd, rs, rt);
4640 }
4641 
4642 
4643 /*
4644  * [DSP] CMPGDU.LE.QB rd, rs, rt - Compare unsigned vector of
4645  *   four bytes and write result to GPR and DSPControl
4646  *
4647  *   3         2         1
4648  *  10987654321098765432109876543210
4649  *  001000               x1000000101
4650  *     rt -----
4651  *          rs -----
4652  *               rd -----
4653  */
4654 static char *CMPGDU_LE_QB(uint64 instruction, Dis_info *info)
4655 {
4656     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4657     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4658     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4659 
4660     const char *rd = GPR(rd_value, info);
4661     const char *rs = GPR(rs_value, info);
4662     const char *rt = GPR(rt_value, info);
4663 
4664     return img_format("CMPGDU.LE.QB %s, %s, %s", rd, rs, rt);
4665 }
4666 
4667 
4668 /*
4669  * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of
4670  *   four bytes and write result to GPR and DSPControl
4671  *
4672  *   3         2         1
4673  *  10987654321098765432109876543210
4674  *  001000               x0111000101
4675  *     rt -----
4676  *          rs -----
4677  *               rd -----
4678  */
4679 static char *CMPGDU_LT_QB(uint64 instruction, Dis_info *info)
4680 {
4681     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4682     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4683     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4684 
4685     const char *rd = GPR(rd_value, info);
4686     const char *rs = GPR(rs_value, info);
4687     const char *rt = GPR(rt_value, info);
4688 
4689     return img_format("CMPGDU.LT.QB %s, %s, %s", rd, rs, rt);
4690 }
4691 
4692 
4693 /*
4694  * [DSP] CMPGU.EQ.QB rd, rs, rt - Compare vectors of unsigned
4695  *   byte values and write result to a GPR
4696  *
4697  *   3         2         1
4698  *  10987654321098765432109876543210
4699  *  001000               x0011000101
4700  *     rt -----
4701  *          rs -----
4702  *               rd -----
4703  */
4704 static char *CMPGU_EQ_QB(uint64 instruction, Dis_info *info)
4705 {
4706     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4707     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4708     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4709 
4710     const char *rd = GPR(rd_value, info);
4711     const char *rs = GPR(rs_value, info);
4712     const char *rt = GPR(rt_value, info);
4713 
4714     return img_format("CMPGU.EQ.QB %s, %s, %s", rd, rs, rt);
4715 }
4716 
4717 
4718 /*
4719  * [DSP] CMPGU.LE.QB rd, rs, rt - Compare vectors of unsigned
4720  *   byte values and write result to a GPR
4721  *
4722  *   3         2         1
4723  *  10987654321098765432109876543210
4724  *  001000               x0101000101
4725  *     rt -----
4726  *          rs -----
4727  *               rd -----
4728  */
4729 static char *CMPGU_LE_QB(uint64 instruction, Dis_info *info)
4730 {
4731     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4732     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4733     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4734 
4735     const char *rd = GPR(rd_value, info);
4736     const char *rs = GPR(rs_value, info);
4737     const char *rt = GPR(rt_value, info);
4738 
4739     return img_format("CMPGU.LE.QB %s, %s, %s", rd, rs, rt);
4740 }
4741 
4742 
4743 /*
4744  * [DSP] CMPGU.LT.QB rd, rs, rt - Compare vectors of unsigned
4745  *   byte values and write result to a GPR
4746  *
4747  *   3         2         1
4748  *  10987654321098765432109876543210
4749  *  001000               x0100000101
4750  *     rt -----
4751  *          rs -----
4752  *               rd -----
4753  */
4754 static char *CMPGU_LT_QB(uint64 instruction, Dis_info *info)
4755 {
4756     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4757     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4758     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
4759 
4760     const char *rd = GPR(rd_value, info);
4761     const char *rs = GPR(rs_value, info);
4762     const char *rt = GPR(rt_value, info);
4763 
4764     return img_format("CMPGU.LT.QB %s, %s, %s", rd, rs, rt);
4765 }
4766 
4767 
4768 /*
4769  * [DSP] CMPU.EQ.QB rd, rs, rt - Compare vectors of unsigned
4770  *   byte values
4771  *
4772  *   3         2         1
4773  *  10987654321098765432109876543210
4774  *  001000          xxxxxx1001000101
4775  *     rt -----
4776  *          rs -----
4777  */
4778 static char *CMPU_EQ_QB(uint64 instruction, Dis_info *info)
4779 {
4780     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4781     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4782 
4783     const char *rs = GPR(rs_value, info);
4784     const char *rt = GPR(rt_value, info);
4785 
4786     return img_format("CMPU.EQ.QB %s, %s", rs, rt);
4787 }
4788 
4789 
4790 /*
4791  * [DSP] CMPU.LE.QB rd, rs, rt - Compare vectors of unsigned
4792  *   byte values
4793  *
4794  *   3         2         1
4795  *  10987654321098765432109876543210
4796  *  001000          xxxxxx1011000101
4797  *     rt -----
4798  *          rs -----
4799  */
4800 static char *CMPU_LE_QB(uint64 instruction, Dis_info *info)
4801 {
4802     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4803     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4804 
4805     const char *rs = GPR(rs_value, info);
4806     const char *rt = GPR(rt_value, info);
4807 
4808     return img_format("CMPU.LE.QB %s, %s", rs, rt);
4809 }
4810 
4811 
4812 /*
4813  * [DSP] CMPU.LT.QB rd, rs, rt - Compare vectors of unsigned
4814  *   byte values
4815  *
4816  *   3         2         1
4817  *  10987654321098765432109876543210
4818  *  001000          xxxxxx1010000101
4819  *     rt -----
4820  *          rs -----
4821  */
4822 static char *CMPU_LT_QB(uint64 instruction, Dis_info *info)
4823 {
4824     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4825     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
4826 
4827     const char *rs = GPR(rs_value, info);
4828     const char *rt = GPR(rt_value, info);
4829 
4830     return img_format("CMPU.LT.QB %s, %s", rs, rt);
4831 }
4832 
4833 
4834 /*
4835  *
4836  *
4837  *   3         2         1
4838  *  10987654321098765432109876543210
4839  *  001000               x1110000101
4840  *     rt -----
4841  *          rs -----
4842  *               rd -----
4843  */
4844 static char *COP2_1(uint64 instruction, Dis_info *info)
4845 {
4846     uint64 cofun_value = extract_cofun_25_24_23(instruction);
4847 
4848 
4849     return img_format("COP2_1 0x%" PRIx64, cofun_value);
4850 }
4851 
4852 
4853 /*
4854  *
4855  *
4856  *   3         2         1
4857  *  10987654321098765432109876543210
4858  *  001000               x1110000101
4859  *     rt -----
4860  *          rs -----
4861  *               rd -----
4862  */
4863 static char *CTC1(uint64 instruction, Dis_info *info)
4864 {
4865     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4866     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
4867 
4868     const char *rt = GPR(rt_value, info);
4869 
4870     return img_format("CTC1 %s, CP%" PRIu64, rt, cs_value);
4871 }
4872 
4873 
4874 /*
4875  *
4876  *
4877  *   3         2         1
4878  *  10987654321098765432109876543210
4879  *  001000               x1110000101
4880  *     rt -----
4881  *          rs -----
4882  *               rd -----
4883  */
4884 static char *CTC2(uint64 instruction, Dis_info *info)
4885 {
4886     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
4887     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
4888 
4889     const char *rt = GPR(rt_value, info);
4890 
4891     return img_format("CTC2 %s, CP%" PRIu64, rt, cs_value);
4892 }
4893 
4894 
4895 /*
4896  *
4897  *
4898  *   3         2         1
4899  *  10987654321098765432109876543210
4900  *  001000               x1110000101
4901  *     rt -----
4902  *          rs -----
4903  *               rd -----
4904  */
4905 static char *CVT_D_L(uint64 instruction, Dis_info *info)
4906 {
4907     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4908     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4909 
4910     const char *ft = FPR(ft_value, info);
4911     const char *fs = FPR(fs_value, info);
4912 
4913     return img_format("CVT.D.L %s, %s", ft, fs);
4914 }
4915 
4916 
4917 /*
4918  *
4919  *
4920  *   3         2         1
4921  *  10987654321098765432109876543210
4922  *  001000               x1110000101
4923  *     rt -----
4924  *          rs -----
4925  *               rd -----
4926  */
4927 static char *CVT_D_S(uint64 instruction, Dis_info *info)
4928 {
4929     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4930     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4931 
4932     const char *ft = FPR(ft_value, info);
4933     const char *fs = FPR(fs_value, info);
4934 
4935     return img_format("CVT.D.S %s, %s", ft, fs);
4936 }
4937 
4938 
4939 /*
4940  *
4941  *
4942  *   3         2         1
4943  *  10987654321098765432109876543210
4944  *  001000               x1110000101
4945  *     rt -----
4946  *          rs -----
4947  *               rd -----
4948  */
4949 static char *CVT_D_W(uint64 instruction, Dis_info *info)
4950 {
4951     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4952     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4953 
4954     const char *ft = FPR(ft_value, info);
4955     const char *fs = FPR(fs_value, info);
4956 
4957     return img_format("CVT.D.W %s, %s", ft, fs);
4958 }
4959 
4960 
4961 /*
4962  *
4963  *
4964  *   3         2         1
4965  *  10987654321098765432109876543210
4966  *  001000               x1110000101
4967  *     rt -----
4968  *          rs -----
4969  *               rd -----
4970  */
4971 static char *CVT_L_D(uint64 instruction, Dis_info *info)
4972 {
4973     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4974     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4975 
4976     const char *ft = FPR(ft_value, info);
4977     const char *fs = FPR(fs_value, info);
4978 
4979     return img_format("CVT.L.D %s, %s", ft, fs);
4980 }
4981 
4982 
4983 /*
4984  *
4985  *
4986  *   3         2         1
4987  *  10987654321098765432109876543210
4988  *  001000               x1110000101
4989  *     rt -----
4990  *          rs -----
4991  *               rd -----
4992  */
4993 static char *CVT_L_S(uint64 instruction, Dis_info *info)
4994 {
4995     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
4996     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
4997 
4998     const char *ft = FPR(ft_value, info);
4999     const char *fs = FPR(fs_value, info);
5000 
5001     return img_format("CVT.L.S %s, %s", ft, fs);
5002 }
5003 
5004 
5005 /*
5006  *
5007  *
5008  *   3         2         1
5009  *  10987654321098765432109876543210
5010  *  001000               x1110000101
5011  *     rt -----
5012  *          rs -----
5013  *               rd -----
5014  */
5015 static char *CVT_S_D(uint64 instruction, Dis_info *info)
5016 {
5017     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5018     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5019 
5020     const char *ft = FPR(ft_value, info);
5021     const char *fs = FPR(fs_value, info);
5022 
5023     return img_format("CVT.S.D %s, %s", ft, fs);
5024 }
5025 
5026 
5027 /*
5028  *
5029  *
5030  *   3         2         1
5031  *  10987654321098765432109876543210
5032  *  001000               x1110000101
5033  *     rt -----
5034  *          rs -----
5035  *               rd -----
5036  */
5037 static char *CVT_S_L(uint64 instruction, Dis_info *info)
5038 {
5039     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5040     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5041 
5042     const char *ft = FPR(ft_value, info);
5043     const char *fs = FPR(fs_value, info);
5044 
5045     return img_format("CVT.S.L %s, %s", ft, fs);
5046 }
5047 
5048 
5049 /*
5050  *
5051  *
5052  *   3         2         1
5053  *  10987654321098765432109876543210
5054  *  001000               x1110000101
5055  *     rt -----
5056  *          rs -----
5057  *               rd -----
5058  */
5059 static char *CVT_S_PL(uint64 instruction, Dis_info *info)
5060 {
5061     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5062     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5063 
5064     const char *ft = FPR(ft_value, info);
5065     const char *fs = FPR(fs_value, info);
5066 
5067     return img_format("CVT.S.PL %s, %s", ft, fs);
5068 }
5069 
5070 
5071 /*
5072  *
5073  *
5074  *   3         2         1
5075  *  10987654321098765432109876543210
5076  *  001000               x1110000101
5077  *     rt -----
5078  *          rs -----
5079  *               rd -----
5080  */
5081 static char *CVT_S_PU(uint64 instruction, Dis_info *info)
5082 {
5083     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5084     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5085 
5086     const char *ft = FPR(ft_value, info);
5087     const char *fs = FPR(fs_value, info);
5088 
5089     return img_format("CVT.S.PU %s, %s", ft, fs);
5090 }
5091 
5092 
5093 /*
5094  *
5095  *
5096  *   3         2         1
5097  *  10987654321098765432109876543210
5098  *  001000               x1110000101
5099  *     rt -----
5100  *          rs -----
5101  *               rd -----
5102  */
5103 static char *CVT_S_W(uint64 instruction, Dis_info *info)
5104 {
5105     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5106     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5107 
5108     const char *ft = FPR(ft_value, info);
5109     const char *fs = FPR(fs_value, info);
5110 
5111     return img_format("CVT.S.W %s, %s", ft, fs);
5112 }
5113 
5114 
5115 /*
5116  *
5117  *
5118  *   3         2         1
5119  *  10987654321098765432109876543210
5120  *  001000               x1110000101
5121  *     rt -----
5122  *          rs -----
5123  *               rd -----
5124  */
5125 static char *CVT_W_D(uint64 instruction, Dis_info *info)
5126 {
5127     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5128     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5129 
5130     const char *ft = FPR(ft_value, info);
5131     const char *fs = FPR(fs_value, info);
5132 
5133     return img_format("CVT.W.D %s, %s", ft, fs);
5134 }
5135 
5136 
5137 /*
5138  *
5139  *
5140  *   3         2         1
5141  *  10987654321098765432109876543210
5142  *  001000               x1110000101
5143  *     rt -----
5144  *          rs -----
5145  *               rd -----
5146  */
5147 static char *CVT_W_S(uint64 instruction, Dis_info *info)
5148 {
5149     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5150     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5151 
5152     const char *ft = FPR(ft_value, info);
5153     const char *fs = FPR(fs_value, info);
5154 
5155     return img_format("CVT.W.S %s, %s", ft, fs);
5156 }
5157 
5158 
5159 /*
5160  *
5161  *
5162  *   3         2         1
5163  *  10987654321098765432109876543210
5164  *  001000               x1110000101
5165  *     rt -----
5166  *          rs -----
5167  *               rd -----
5168  */
5169 static char *DADDIU_48_(uint64 instruction, Dis_info *info)
5170 {
5171     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
5172     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
5173 
5174     const char *rt = GPR(rt_value, info);
5175 
5176     return img_format("DADDIU %s, %s", rt, s_value);
5177 }
5178 
5179 
5180 /*
5181  *
5182  *
5183  *   3         2         1
5184  *  10987654321098765432109876543210
5185  *  001000               x1110000101
5186  *     rt -----
5187  *          rs -----
5188  *               rd -----
5189  */
5190 static char *DADDIU_NEG_(uint64 instruction, Dis_info *info)
5191 {
5192     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5193     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5194     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
5195 
5196     const char *rt = GPR(rt_value, info);
5197     const char *rs = GPR(rs_value, info);
5198     int64 u = neg_copy(u_value);
5199 
5200     return img_format("DADDIU %s, %s, %" PRId64, rt, rs, u);
5201 }
5202 
5203 
5204 /*
5205  *
5206  *
5207  *   3         2         1
5208  *  10987654321098765432109876543210
5209  *  001000               x1110000101
5210  *     rt -----
5211  *          rs -----
5212  *               rd -----
5213  */
5214 static char *DADDIU_U12_(uint64 instruction, Dis_info *info)
5215 {
5216     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5217     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5218     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
5219 
5220     const char *rt = GPR(rt_value, info);
5221     const char *rs = GPR(rs_value, info);
5222 
5223     return img_format("DADDIU %s, %s, 0x%" PRIx64, rt, rs, u_value);
5224 }
5225 
5226 
5227 /*
5228  *
5229  *
5230  *   3         2         1
5231  *  10987654321098765432109876543210
5232  *  001000               x1110000101
5233  *     rt -----
5234  *          rs -----
5235  *               rd -----
5236  */
5237 static char *DADD(uint64 instruction, Dis_info *info)
5238 {
5239     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5240     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5241     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5242 
5243     const char *rd = GPR(rd_value, info);
5244     const char *rs = GPR(rs_value, info);
5245     const char *rt = GPR(rt_value, info);
5246 
5247     return img_format("DADD %s, %s, %s", rd, rs, rt);
5248 }
5249 
5250 
5251 /*
5252  *
5253  *
5254  *   3         2         1
5255  *  10987654321098765432109876543210
5256  *  001000               x1110000101
5257  *     rt -----
5258  *          rs -----
5259  *               rd -----
5260  */
5261 static char *DADDU(uint64 instruction, Dis_info *info)
5262 {
5263     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5264     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5265     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5266 
5267     const char *rd = GPR(rd_value, info);
5268     const char *rs = GPR(rs_value, info);
5269     const char *rt = GPR(rt_value, info);
5270 
5271     return img_format("DADDU %s, %s, %s", rd, rs, rt);
5272 }
5273 
5274 
5275 /*
5276  *
5277  *
5278  *   3         2         1
5279  *  10987654321098765432109876543210
5280  *  001000               x1110000101
5281  *     rt -----
5282  *          rs -----
5283  *               rd -----
5284  */
5285 static char *DCLO(uint64 instruction, Dis_info *info)
5286 {
5287     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5288     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5289 
5290     const char *rt = GPR(rt_value, info);
5291     const char *rs = GPR(rs_value, info);
5292 
5293     return img_format("DCLO %s, %s", rt, rs);
5294 }
5295 
5296 
5297 /*
5298  *
5299  *
5300  *   3         2         1
5301  *  10987654321098765432109876543210
5302  *  001000               x1110000101
5303  *     rt -----
5304  *          rs -----
5305  *               rd -----
5306  */
5307 static char *DCLZ(uint64 instruction, Dis_info *info)
5308 {
5309     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5310     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5311 
5312     const char *rt = GPR(rt_value, info);
5313     const char *rs = GPR(rs_value, info);
5314 
5315     return img_format("DCLZ %s, %s", rt, rs);
5316 }
5317 
5318 
5319 /*
5320  *
5321  *
5322  *   3         2         1
5323  *  10987654321098765432109876543210
5324  *  001000               x1110000101
5325  *     rt -----
5326  *          rs -----
5327  *               rd -----
5328  */
5329 static char *DDIV(uint64 instruction, Dis_info *info)
5330 {
5331     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5332     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5333     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5334 
5335     const char *rd = GPR(rd_value, info);
5336     const char *rs = GPR(rs_value, info);
5337     const char *rt = GPR(rt_value, info);
5338 
5339     return img_format("DDIV %s, %s, %s", rd, rs, rt);
5340 }
5341 
5342 
5343 /*
5344  *
5345  *
5346  *   3         2         1
5347  *  10987654321098765432109876543210
5348  *  001000               x1110000101
5349  *     rt -----
5350  *          rs -----
5351  *               rd -----
5352  */
5353 static char *DDIVU(uint64 instruction, Dis_info *info)
5354 {
5355     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5356     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5357     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5358 
5359     const char *rd = GPR(rd_value, info);
5360     const char *rs = GPR(rs_value, info);
5361     const char *rt = GPR(rt_value, info);
5362 
5363     return img_format("DDIVU %s, %s, %s", rd, rs, rt);
5364 }
5365 
5366 
5367 /*
5368  *
5369  *
5370  *   3         2         1
5371  *  10987654321098765432109876543210
5372  *  001000               x1110000101
5373  *     rt -----
5374  *          rs -----
5375  *               rd -----
5376  */
5377 static char *DERET(uint64 instruction, Dis_info *info)
5378 {
5379     (void)instruction;
5380 
5381     return g_strdup("DERET ");
5382 }
5383 
5384 
5385 /*
5386  *
5387  *
5388  *   3         2         1
5389  *  10987654321098765432109876543210
5390  *  001000               x1110000101
5391  *     rt -----
5392  *          rs -----
5393  *               rd -----
5394  */
5395 static char *DEXTM(uint64 instruction, Dis_info *info)
5396 {
5397     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5398     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5399     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5400     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5401 
5402     const char *rt = GPR(rt_value, info);
5403     const char *rs = GPR(rs_value, info);
5404     uint64 msbd = encode_msbd_from_size(msbd_value);
5405 
5406     return img_format("DEXTM %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5407                       rt, rs, lsb_value, msbd);
5408 }
5409 
5410 
5411 /*
5412  *
5413  *
5414  *   3         2         1
5415  *  10987654321098765432109876543210
5416  *  001000               x1110000101
5417  *     rt -----
5418  *          rs -----
5419  *               rd -----
5420  */
5421 static char *DEXT(uint64 instruction, Dis_info *info)
5422 {
5423     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5424     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5425     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5426     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5427 
5428     const char *rt = GPR(rt_value, info);
5429     const char *rs = GPR(rs_value, info);
5430     uint64 msbd = encode_msbd_from_size(msbd_value);
5431 
5432     return img_format("DEXT %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5433                       rt, rs, lsb_value, msbd);
5434 }
5435 
5436 
5437 /*
5438  *
5439  *
5440  *   3         2         1
5441  *  10987654321098765432109876543210
5442  *  001000               x1110000101
5443  *     rt -----
5444  *          rs -----
5445  *               rd -----
5446  */
5447 static char *DEXTU(uint64 instruction, Dis_info *info)
5448 {
5449     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5450     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5451     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5452     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5453 
5454     const char *rt = GPR(rt_value, info);
5455     const char *rs = GPR(rs_value, info);
5456     uint64 msbd = encode_msbd_from_size(msbd_value);
5457 
5458     return img_format("DEXTU %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5459                       rt, rs, lsb_value, msbd);
5460 }
5461 
5462 
5463 /*
5464  *
5465  *
5466  *   3         2         1
5467  *  10987654321098765432109876543210
5468  *  001000               x1110000101
5469  *     rt -----
5470  *          rs -----
5471  *               rd -----
5472  */
5473 static char *DINSM(uint64 instruction, Dis_info *info)
5474 {
5475     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5476     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5477     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5478     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5479 
5480     const char *rt = GPR(rt_value, info);
5481     const char *rs = GPR(rs_value, info);
5482     /* !!!!!!!!!! - no conversion function */
5483 
5484     return img_format("DINSM %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5485                       rt, rs, lsb_value, msbd_value);
5486     /* hand edited */
5487 }
5488 
5489 
5490 /*
5491  *
5492  *
5493  *   3         2         1
5494  *  10987654321098765432109876543210
5495  *  001000               x1110000101
5496  *     rt -----
5497  *          rs -----
5498  *               rd -----
5499  */
5500 static char *DINS(uint64 instruction, Dis_info *info)
5501 {
5502     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5503     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5504     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5505     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5506 
5507     const char *rt = GPR(rt_value, info);
5508     const char *rs = GPR(rs_value, info);
5509     /* !!!!!!!!!! - no conversion function */
5510 
5511     return img_format("DINS %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5512                       rt, rs, lsb_value, msbd_value);
5513     /* hand edited */
5514 }
5515 
5516 
5517 /*
5518  *
5519  *
5520  *   3         2         1
5521  *  10987654321098765432109876543210
5522  *  001000               x1110000101
5523  *     rt -----
5524  *          rs -----
5525  *               rd -----
5526  */
5527 static char *DINSU(uint64 instruction, Dis_info *info)
5528 {
5529     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5530     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5531     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
5532     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
5533 
5534     const char *rt = GPR(rt_value, info);
5535     const char *rs = GPR(rs_value, info);
5536     /* !!!!!!!!!! - no conversion function */
5537 
5538     return img_format("DINSU %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
5539                       rt, rs, lsb_value, msbd_value);
5540     /* hand edited */
5541 }
5542 
5543 
5544 /*
5545  *
5546  *
5547  *   3         2         1
5548  *  10987654321098765432109876543210
5549  *  001000               x1110000101
5550  *     rt -----
5551  *          rs -----
5552  *               rd -----
5553  */
5554 static char *DI(uint64 instruction, Dis_info *info)
5555 {
5556     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5557 
5558     const char *rt = GPR(rt_value, info);
5559 
5560     return img_format("DI %s", rt);
5561 }
5562 
5563 
5564 /*
5565  *
5566  *
5567  *   3         2         1
5568  *  10987654321098765432109876543210
5569  *  001000               x1110000101
5570  *     rt -----
5571  *          rs -----
5572  *               rd -----
5573  */
5574 static char *DIV(uint64 instruction, Dis_info *info)
5575 {
5576     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5577     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5578     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5579 
5580     const char *rd = GPR(rd_value, info);
5581     const char *rs = GPR(rs_value, info);
5582     const char *rt = GPR(rt_value, info);
5583 
5584     return img_format("DIV %s, %s, %s", rd, rs, rt);
5585 }
5586 
5587 
5588 /*
5589  *
5590  *
5591  *   3         2         1
5592  *  10987654321098765432109876543210
5593  *  001000               x1110000101
5594  *     rt -----
5595  *          rs -----
5596  *               rd -----
5597  */
5598 static char *DIV_D(uint64 instruction, Dis_info *info)
5599 {
5600     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5601     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5602     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
5603 
5604     const char *fd = FPR(fd_value, info);
5605     const char *fs = FPR(fs_value, info);
5606     const char *ft = FPR(ft_value, info);
5607 
5608     return img_format("DIV.D %s, %s, %s", fd, fs, ft);
5609 }
5610 
5611 
5612 /*
5613  *
5614  *
5615  *   3         2         1
5616  *  10987654321098765432109876543210
5617  *  001000               x1110000101
5618  *     rt -----
5619  *          rs -----
5620  *               rd -----
5621  */
5622 static char *DIV_S(uint64 instruction, Dis_info *info)
5623 {
5624     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
5625     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5626     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
5627 
5628     const char *fd = FPR(fd_value, info);
5629     const char *fs = FPR(fs_value, info);
5630     const char *ft = FPR(ft_value, info);
5631 
5632     return img_format("DIV.S %s, %s, %s", fd, fs, ft);
5633 }
5634 
5635 
5636 /*
5637  *
5638  *
5639  *   3         2         1
5640  *  10987654321098765432109876543210
5641  *  001000               x1110000101
5642  *     rt -----
5643  *          rs -----
5644  *               rd -----
5645  */
5646 static char *DIVU(uint64 instruction, Dis_info *info)
5647 {
5648     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5649     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5650     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5651 
5652     const char *rd = GPR(rd_value, info);
5653     const char *rs = GPR(rs_value, info);
5654     const char *rt = GPR(rt_value, info);
5655 
5656     return img_format("DIVU %s, %s, %s", rd, rs, rt);
5657 }
5658 
5659 
5660 /*
5661  *
5662  *
5663  *   3         2         1
5664  *  10987654321098765432109876543210
5665  *  001000               x1110000101
5666  *     rt -----
5667  *          rs -----
5668  *               rd -----
5669  */
5670 static char *DLSA(uint64 instruction, Dis_info *info)
5671 {
5672     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5673     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5674     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5675     uint64 u2_value = extract_u2_10_9(instruction);
5676 
5677     const char *rd = GPR(rd_value, info);
5678     const char *rs = GPR(rs_value, info);
5679     const char *rt = GPR(rt_value, info);
5680 
5681     return img_format("DLSA %s, %s, %s, 0x%" PRIx64, rd, rs, rt, u2_value);
5682 }
5683 
5684 
5685 /*
5686  *
5687  *
5688  *   3         2         1
5689  *  10987654321098765432109876543210
5690  *  001000               x1110000101
5691  *     rt -----
5692  *          rs -----
5693  *               rd -----
5694  */
5695 static char *DLUI_48_(uint64 instruction, Dis_info *info)
5696 {
5697     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
5698     uint64 u_value = extract_u_31_to_0__s32(instruction);
5699 
5700     const char *rt = GPR(rt_value, info);
5701 
5702     return img_format("DLUI %s, 0x%" PRIx64, rt, u_value);
5703 }
5704 
5705 
5706 /*
5707  *
5708  *
5709  *   3         2         1
5710  *  10987654321098765432109876543210
5711  *  001000               x1110000101
5712  *     rt -----
5713  *          rs -----
5714  *               rd -----
5715  */
5716 static char *DMFC0(uint64 instruction, Dis_info *info)
5717 {
5718     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5719     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
5720     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
5721 
5722     const char *rt = GPR(rt_value, info);
5723 
5724     return img_format("DMFC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
5725                       rt, c0s_value, sel_value);
5726 }
5727 
5728 
5729 /*
5730  *
5731  *
5732  *   3         2         1
5733  *  10987654321098765432109876543210
5734  *  001000               x1110000101
5735  *     rt -----
5736  *          rs -----
5737  *               rd -----
5738  */
5739 static char *DMFC1(uint64 instruction, Dis_info *info)
5740 {
5741     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5742     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5743 
5744     const char *rt = GPR(rt_value, info);
5745     const char *fs = FPR(fs_value, info);
5746 
5747     return img_format("DMFC1 %s, %s", rt, fs);
5748 }
5749 
5750 
5751 /*
5752  *
5753  *
5754  *   3         2         1
5755  *  10987654321098765432109876543210
5756  *  001000               x1110000101
5757  *     rt -----
5758  *          rs -----
5759  *               rd -----
5760  */
5761 static char *DMFC2(uint64 instruction, Dis_info *info)
5762 {
5763     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5764     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
5765 
5766     const char *rt = GPR(rt_value, info);
5767 
5768     return img_format("DMFC2 %s, CP%" PRIu64, rt, cs_value);
5769 }
5770 
5771 
5772 /*
5773  *
5774  *
5775  *   3         2         1
5776  *  10987654321098765432109876543210
5777  *  001000               x1110000101
5778  *     rt -----
5779  *          rs -----
5780  *               rd -----
5781  */
5782 static char *DMFGC0(uint64 instruction, Dis_info *info)
5783 {
5784     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5785     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
5786     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
5787 
5788     const char *rt = GPR(rt_value, info);
5789 
5790     return img_format("DMFGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
5791                       rt, c0s_value, sel_value);
5792 }
5793 
5794 
5795 /*
5796  *
5797  *
5798  *   3         2         1
5799  *  10987654321098765432109876543210
5800  *  001000               x1110000101
5801  *     rt -----
5802  *          rs -----
5803  *               rd -----
5804  */
5805 static char *DMOD(uint64 instruction, Dis_info *info)
5806 {
5807     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5808     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5809     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5810 
5811     const char *rd = GPR(rd_value, info);
5812     const char *rs = GPR(rs_value, info);
5813     const char *rt = GPR(rt_value, info);
5814 
5815     return img_format("DMOD %s, %s, %s", rd, rs, rt);
5816 }
5817 
5818 
5819 /*
5820  *
5821  *
5822  *   3         2         1
5823  *  10987654321098765432109876543210
5824  *  001000               x1110000101
5825  *     rt -----
5826  *          rs -----
5827  *               rd -----
5828  */
5829 static char *DMODU(uint64 instruction, Dis_info *info)
5830 {
5831     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5832     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5833     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5834 
5835     const char *rd = GPR(rd_value, info);
5836     const char *rs = GPR(rs_value, info);
5837     const char *rt = GPR(rt_value, info);
5838 
5839     return img_format("DMODU %s, %s, %s", rd, rs, rt);
5840 }
5841 
5842 
5843 /*
5844  *
5845  *
5846  *   3         2         1
5847  *  10987654321098765432109876543210
5848  *  001000               x1110000101
5849  *     rt -----
5850  *          rs -----
5851  *               rd -----
5852  */
5853 static char *DMTC0(uint64 instruction, Dis_info *info)
5854 {
5855     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5856     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
5857     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
5858 
5859     const char *rt = GPR(rt_value, info);
5860 
5861     return img_format("DMTC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
5862                       rt, c0s_value, sel_value);
5863 }
5864 
5865 
5866 /*
5867  *
5868  *
5869  *   3         2         1
5870  *  10987654321098765432109876543210
5871  *  001000               x1110000101
5872  *     rt -----
5873  *          rs -----
5874  *               rd -----
5875  */
5876 static char *DMTC1(uint64 instruction, Dis_info *info)
5877 {
5878     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5879     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
5880 
5881     const char *rt = GPR(rt_value, info);
5882     const char *fs = FPR(fs_value, info);
5883 
5884     return img_format("DMTC1 %s, %s", rt, fs);
5885 }
5886 
5887 
5888 /*
5889  *
5890  *
5891  *   3         2         1
5892  *  10987654321098765432109876543210
5893  *  001000               x1110000101
5894  *     rt -----
5895  *          rs -----
5896  *               rd -----
5897  */
5898 static char *DMTC2(uint64 instruction, Dis_info *info)
5899 {
5900     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5901     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
5902 
5903     const char *rt = GPR(rt_value, info);
5904 
5905     return img_format("DMTC2 %s, CP%" PRIu64, rt, cs_value);
5906 }
5907 
5908 
5909 /*
5910  *
5911  *
5912  *   3         2         1
5913  *  10987654321098765432109876543210
5914  *  001000               x1110000101
5915  *     rt -----
5916  *          rs -----
5917  *               rd -----
5918  */
5919 static char *DMTGC0(uint64 instruction, Dis_info *info)
5920 {
5921     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5922     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
5923     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
5924 
5925     const char *rt = GPR(rt_value, info);
5926 
5927     return img_format("DMTGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
5928                       rt, c0s_value, sel_value);
5929 }
5930 
5931 
5932 /*
5933  *
5934  *
5935  *   3         2         1
5936  *  10987654321098765432109876543210
5937  *  001000               x1110000101
5938  *     rt -----
5939  *          rs -----
5940  *               rd -----
5941  */
5942 static char *DMT(uint64 instruction, Dis_info *info)
5943 {
5944     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5945 
5946     const char *rt = GPR(rt_value, info);
5947 
5948     return img_format("DMT %s", rt);
5949 }
5950 
5951 
5952 /*
5953  *
5954  *
5955  *   3         2         1
5956  *  10987654321098765432109876543210
5957  *  001000               x1110000101
5958  *     rt -----
5959  *          rs -----
5960  *               rd -----
5961  */
5962 static char *DMUH(uint64 instruction, Dis_info *info)
5963 {
5964     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5965     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5966     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5967 
5968     const char *rd = GPR(rd_value, info);
5969     const char *rs = GPR(rs_value, info);
5970     const char *rt = GPR(rt_value, info);
5971 
5972     return img_format("DMUH %s, %s, %s", rd, rs, rt);
5973 }
5974 
5975 
5976 /*
5977  *
5978  *
5979  *   3         2         1
5980  *  10987654321098765432109876543210
5981  *  001000               x1110000101
5982  *     rt -----
5983  *          rs -----
5984  *               rd -----
5985  */
5986 static char *DMUHU(uint64 instruction, Dis_info *info)
5987 {
5988     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
5989     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
5990     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
5991 
5992     const char *rd = GPR(rd_value, info);
5993     const char *rs = GPR(rs_value, info);
5994     const char *rt = GPR(rt_value, info);
5995 
5996     return img_format("DMUHU %s, %s, %s", rd, rs, rt);
5997 }
5998 
5999 
6000 /*
6001  *
6002  *
6003  *   3         2         1
6004  *  10987654321098765432109876543210
6005  *  001000               x1110000101
6006  *     rt -----
6007  *          rs -----
6008  *               rd -----
6009  */
6010 static char *DMUL(uint64 instruction, Dis_info *info)
6011 {
6012     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6013     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6014     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6015 
6016     const char *rd = GPR(rd_value, info);
6017     const char *rs = GPR(rs_value, info);
6018     const char *rt = GPR(rt_value, info);
6019 
6020     return img_format("DMUL %s, %s, %s", rd, rs, rt);
6021 }
6022 
6023 
6024 /*
6025  *
6026  *
6027  *   3         2         1
6028  *  10987654321098765432109876543210
6029  *  001000               x1110000101
6030  *     rt -----
6031  *          rs -----
6032  *               rd -----
6033  */
6034 static char *DMULU(uint64 instruction, Dis_info *info)
6035 {
6036     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6037     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6038     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6039 
6040     const char *rd = GPR(rd_value, info);
6041     const char *rs = GPR(rs_value, info);
6042     const char *rt = GPR(rt_value, info);
6043 
6044     return img_format("DMULU %s, %s, %s", rd, rs, rt);
6045 }
6046 
6047 
6048 /*
6049  * [DSP] DPA.W.PH ac, rs, rt - Dot product with accumulate on
6050  *   vector integer halfword elements
6051  *
6052  *   3         2         1
6053  *  10987654321098765432109876543210
6054  *  001000            00000010111111
6055  *     rt -----
6056  *          rs -----
6057  *               ac --
6058  */
6059 static char *DPA_W_PH(uint64 instruction, Dis_info *info)
6060 {
6061     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6062     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6063     uint64 ac_value = extract_ac_15_14(instruction);
6064 
6065     const char *ac = AC(ac_value, info);
6066     const char *rs = GPR(rs_value, info);
6067     const char *rt = GPR(rt_value, info);
6068 
6069     return img_format("DPA.W.PH %s, %s, %s", ac, rs, rt);
6070 }
6071 
6072 
6073 /*
6074  *
6075  *
6076  *   3         2         1
6077  *  10987654321098765432109876543210
6078  *  001000               x1110000101
6079  *     rt -----
6080  *          rs -----
6081  *               rd -----
6082  */
6083 static char *DPAQ_SA_L_W(uint64 instruction, Dis_info *info)
6084 {
6085     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6086     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6087     uint64 ac_value = extract_ac_15_14(instruction);
6088 
6089     const char *ac = AC(ac_value, info);
6090     const char *rs = GPR(rs_value, info);
6091     const char *rt = GPR(rt_value, info);
6092 
6093     return img_format("DPAQ_SA.L.W %s, %s, %s", ac, rs, rt);
6094 }
6095 
6096 
6097 /*
6098  *
6099  *
6100  *   3         2         1
6101  *  10987654321098765432109876543210
6102  *  001000               x1110000101
6103  *     rt -----
6104  *          rs -----
6105  *               rd -----
6106  */
6107 static char *DPAQ_S_W_PH(uint64 instruction, Dis_info *info)
6108 {
6109     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6110     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6111     uint64 ac_value = extract_ac_15_14(instruction);
6112 
6113     const char *ac = AC(ac_value, info);
6114     const char *rs = GPR(rs_value, info);
6115     const char *rt = GPR(rt_value, info);
6116 
6117     return img_format("DPAQ_S.W.PH %s, %s, %s", ac, rs, rt);
6118 }
6119 
6120 
6121 /*
6122  *
6123  *
6124  *   3         2         1
6125  *  10987654321098765432109876543210
6126  *  001000               x1110000101
6127  *     rt -----
6128  *          rs -----
6129  *               rd -----
6130  */
6131 static char *DPAQX_SA_W_PH(uint64 instruction, Dis_info *info)
6132 {
6133     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6134     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6135     uint64 ac_value = extract_ac_15_14(instruction);
6136 
6137     const char *ac = AC(ac_value, info);
6138     const char *rs = GPR(rs_value, info);
6139     const char *rt = GPR(rt_value, info);
6140 
6141     return img_format("DPAQX_SA.W.PH %s, %s, %s", ac, rs, rt);
6142 }
6143 
6144 
6145 /*
6146  *
6147  *
6148  *   3         2         1
6149  *  10987654321098765432109876543210
6150  *  001000               x1110000101
6151  *     rt -----
6152  *          rs -----
6153  *               rd -----
6154  */
6155 static char *DPAQX_S_W_PH(uint64 instruction, Dis_info *info)
6156 {
6157     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6158     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6159     uint64 ac_value = extract_ac_15_14(instruction);
6160 
6161     const char *ac = AC(ac_value, info);
6162     const char *rs = GPR(rs_value, info);
6163     const char *rt = GPR(rt_value, info);
6164 
6165     return img_format("DPAQX_S.W.PH %s, %s, %s", ac, rs, rt);
6166 }
6167 
6168 
6169 /*
6170  *
6171  *
6172  *   3         2         1
6173  *  10987654321098765432109876543210
6174  *  001000               x1110000101
6175  *     rt -----
6176  *          rs -----
6177  *               rd -----
6178  */
6179 static char *DPAU_H_QBL(uint64 instruction, Dis_info *info)
6180 {
6181     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6182     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6183     uint64 ac_value = extract_ac_15_14(instruction);
6184 
6185     const char *ac = AC(ac_value, info);
6186     const char *rs = GPR(rs_value, info);
6187     const char *rt = GPR(rt_value, info);
6188 
6189     return img_format("DPAU.H.QBL %s, %s, %s", ac, rs, rt);
6190 }
6191 
6192 
6193 /*
6194  *
6195  *
6196  *   3         2         1
6197  *  10987654321098765432109876543210
6198  *  001000               x1110000101
6199  *     rt -----
6200  *          rs -----
6201  *               rd -----
6202  */
6203 static char *DPAU_H_QBR(uint64 instruction, Dis_info *info)
6204 {
6205     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6206     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6207     uint64 ac_value = extract_ac_15_14(instruction);
6208 
6209     const char *ac = AC(ac_value, info);
6210     const char *rs = GPR(rs_value, info);
6211     const char *rt = GPR(rt_value, info);
6212 
6213     return img_format("DPAU.H.QBR %s, %s, %s", ac, rs, rt);
6214 }
6215 
6216 
6217 /*
6218  *
6219  *
6220  *   3         2         1
6221  *  10987654321098765432109876543210
6222  *  001000               x1110000101
6223  *     rt -----
6224  *          rs -----
6225  *               rd -----
6226  */
6227 static char *DPAX_W_PH(uint64 instruction, Dis_info *info)
6228 {
6229     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6230     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6231     uint64 ac_value = extract_ac_15_14(instruction);
6232 
6233     const char *ac = AC(ac_value, info);
6234     const char *rs = GPR(rs_value, info);
6235     const char *rt = GPR(rt_value, info);
6236 
6237     return img_format("DPAX.W.PH %s, %s, %s", ac, rs, rt);
6238 }
6239 
6240 
6241 /*
6242  *
6243  *
6244  *   3         2         1
6245  *  10987654321098765432109876543210
6246  *  001000               x1110000101
6247  *     rt -----
6248  *          rs -----
6249  *               rd -----
6250  */
6251 static char *DPS_W_PH(uint64 instruction, Dis_info *info)
6252 {
6253     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6254     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6255     uint64 ac_value = extract_ac_15_14(instruction);
6256 
6257     const char *ac = AC(ac_value, info);
6258     const char *rs = GPR(rs_value, info);
6259     const char *rt = GPR(rt_value, info);
6260 
6261     return img_format("DPS.W.PH %s, %s, %s", ac, rs, rt);
6262 }
6263 
6264 
6265 /*
6266  *
6267  *
6268  *   3         2         1
6269  *  10987654321098765432109876543210
6270  *  001000               x1110000101
6271  *     rt -----
6272  *          rs -----
6273  *               rd -----
6274  */
6275 static char *DPSQ_SA_L_W(uint64 instruction, Dis_info *info)
6276 {
6277     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6278     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6279     uint64 ac_value = extract_ac_15_14(instruction);
6280 
6281     const char *ac = AC(ac_value, info);
6282     const char *rs = GPR(rs_value, info);
6283     const char *rt = GPR(rt_value, info);
6284 
6285     return img_format("DPSQ_SA.L.W %s, %s, %s", ac, rs, rt);
6286 }
6287 
6288 
6289 /*
6290  *
6291  *
6292  *   3         2         1
6293  *  10987654321098765432109876543210
6294  *  001000               x1110000101
6295  *     rt -----
6296  *          rs -----
6297  *               rd -----
6298  */
6299 static char *DPSQ_S_W_PH(uint64 instruction, Dis_info *info)
6300 {
6301     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6302     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6303     uint64 ac_value = extract_ac_15_14(instruction);
6304 
6305     const char *ac = AC(ac_value, info);
6306     const char *rs = GPR(rs_value, info);
6307     const char *rt = GPR(rt_value, info);
6308 
6309     return img_format("DPSQ_S.W.PH %s, %s, %s", ac, rs, rt);
6310 }
6311 
6312 
6313 /*
6314  *
6315  *
6316  *   3         2         1
6317  *  10987654321098765432109876543210
6318  *  001000               x1110000101
6319  *     rt -----
6320  *          rs -----
6321  *               rd -----
6322  */
6323 static char *DPSQX_SA_W_PH(uint64 instruction, Dis_info *info)
6324 {
6325     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6326     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6327     uint64 ac_value = extract_ac_15_14(instruction);
6328 
6329     const char *ac = AC(ac_value, info);
6330     const char *rs = GPR(rs_value, info);
6331     const char *rt = GPR(rt_value, info);
6332 
6333     return img_format("DPSQX_SA.W.PH %s, %s, %s", ac, rs, rt);
6334 }
6335 
6336 
6337 /*
6338  *
6339  *
6340  *   3         2         1
6341  *  10987654321098765432109876543210
6342  *  001000               x1110000101
6343  *     rt -----
6344  *          rs -----
6345  *               rd -----
6346  */
6347 static char *DPSQX_S_W_PH(uint64 instruction, Dis_info *info)
6348 {
6349     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6350     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6351     uint64 ac_value = extract_ac_15_14(instruction);
6352 
6353     const char *ac = AC(ac_value, info);
6354     const char *rs = GPR(rs_value, info);
6355     const char *rt = GPR(rt_value, info);
6356 
6357     return img_format("DPSQX_S.W.PH %s, %s, %s", ac, rs, rt);
6358 }
6359 
6360 
6361 /*
6362  *
6363  *
6364  *   3         2         1
6365  *  10987654321098765432109876543210
6366  *  001000               x1110000101
6367  *     rt -----
6368  *          rs -----
6369  *               rd -----
6370  */
6371 static char *DPSU_H_QBL(uint64 instruction, Dis_info *info)
6372 {
6373     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6374     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6375     uint64 ac_value = extract_ac_15_14(instruction);
6376 
6377     const char *ac = AC(ac_value, info);
6378     const char *rs = GPR(rs_value, info);
6379     const char *rt = GPR(rt_value, info);
6380 
6381     return img_format("DPSU.H.QBL %s, %s, %s", ac, rs, rt);
6382 }
6383 
6384 
6385 /*
6386  *
6387  *
6388  *   3         2         1
6389  *  10987654321098765432109876543210
6390  *  001000               x1110000101
6391  *     rt -----
6392  *          rs -----
6393  *               rd -----
6394  */
6395 static char *DPSU_H_QBR(uint64 instruction, Dis_info *info)
6396 {
6397     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6398     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6399     uint64 ac_value = extract_ac_15_14(instruction);
6400 
6401     const char *ac = AC(ac_value, info);
6402     const char *rs = GPR(rs_value, info);
6403     const char *rt = GPR(rt_value, info);
6404 
6405     return img_format("DPSU.H.QBR %s, %s, %s", ac, rs, rt);
6406 }
6407 
6408 
6409 /*
6410  *
6411  *
6412  *   3         2         1
6413  *  10987654321098765432109876543210
6414  *  001000               x1110000101
6415  *     rt -----
6416  *          rs -----
6417  *               rd -----
6418  */
6419 static char *DPSX_W_PH(uint64 instruction, Dis_info *info)
6420 {
6421     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6422     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6423     uint64 ac_value = extract_ac_15_14(instruction);
6424 
6425     const char *ac = AC(ac_value, info);
6426     const char *rs = GPR(rs_value, info);
6427     const char *rt = GPR(rt_value, info);
6428 
6429     return img_format("DPSX.W.PH %s, %s, %s", ac, rs, rt);
6430 }
6431 
6432 
6433 /*
6434  * DROTR -
6435  *
6436  *   3         2         1
6437  *  10987654321098765432109876543210
6438  *  001000               x1110000101
6439  *     rt -----
6440  *          rs -----
6441  *               rd -----
6442  */
6443 static char *DROTR(uint64 instruction, Dis_info *info)
6444 {
6445     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6446     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6447     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6448 
6449     const char *rt = GPR(rt_value, info);
6450     const char *rs = GPR(rs_value, info);
6451 
6452     return img_format("DROTR %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6453 }
6454 
6455 
6456 /*
6457  * DROTR[32] -
6458  *
6459  *   3         2         1
6460  *  10987654321098765432109876543210
6461  *  10o000          1100xxx0110
6462  *     rt -----
6463  *          rs -----
6464  *                       shift -----
6465  */
6466 static char *DROTR32(uint64 instruction, Dis_info *info)
6467 {
6468     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6469     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6470     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6471 
6472     const char *rt = GPR(rt_value, info);
6473     const char *rs = GPR(rs_value, info);
6474 
6475     return img_format("DROTR32 %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6476 }
6477 
6478 
6479 /*
6480  *
6481  *
6482  *   3         2         1
6483  *  10987654321098765432109876543210
6484  *  001000               x1110000101
6485  *     rt -----
6486  *          rs -----
6487  *               rd -----
6488  */
6489 static char *DROTRV(uint64 instruction, Dis_info *info)
6490 {
6491     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6492     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6493     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6494 
6495     const char *rd = GPR(rd_value, info);
6496     const char *rs = GPR(rs_value, info);
6497     const char *rt = GPR(rt_value, info);
6498 
6499     return img_format("DROTRV %s, %s, %s", rd, rs, rt);
6500 }
6501 
6502 
6503 /*
6504  *
6505  *
6506  *   3         2         1
6507  *  10987654321098765432109876543210
6508  *  001000               x1110000101
6509  *     rt -----
6510  *          rs -----
6511  *               rd -----
6512  */
6513 static char *DROTX(uint64 instruction, Dis_info *info)
6514 {
6515     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6516     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6517     uint64 shiftx_value = extract_shiftx_11_10_9_8_7_6(instruction);
6518     uint64 shift_value = extract_shift_5_4_3_2_1_0(instruction);
6519 
6520     const char *rt = GPR(rt_value, info);
6521     const char *rs = GPR(rs_value, info);
6522 
6523     return img_format("DROTX %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
6524                       rt, rs, shift_value, shiftx_value);
6525 }
6526 
6527 
6528 /*
6529  * DSLL -
6530  *
6531  *   3         2         1
6532  *  10987654321098765432109876543210
6533  *  10o000          1100xxx0000
6534  *     rt -----
6535  *          rs -----
6536  *                       shift -----
6537  */
6538 static char *DSLL(uint64 instruction, Dis_info *info)
6539 {
6540     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6541     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6542     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6543 
6544     const char *rt = GPR(rt_value, info);
6545     const char *rs = GPR(rs_value, info);
6546 
6547     return img_format("DSLL %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6548 }
6549 
6550 
6551 /*
6552  * DSLL[32] -
6553  *
6554  *   3         2         1
6555  *  10987654321098765432109876543210
6556  *  10o000          1100xxx0000
6557  *     rt -----
6558  *          rs -----
6559  *                       shift -----
6560  */
6561 static char *DSLL32(uint64 instruction, Dis_info *info)
6562 {
6563     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6564     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6565     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6566 
6567     const char *rt = GPR(rt_value, info);
6568     const char *rs = GPR(rs_value, info);
6569 
6570     return img_format("DSLL32 %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6571 }
6572 
6573 
6574 /*
6575  *
6576  *
6577  *   3         2         1
6578  *  10987654321098765432109876543210
6579  *  001000               x1110000101
6580  *     rt -----
6581  *          rs -----
6582  *               rd -----
6583  */
6584 static char *DSLLV(uint64 instruction, Dis_info *info)
6585 {
6586     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6587     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6588     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6589 
6590     const char *rd = GPR(rd_value, info);
6591     const char *rs = GPR(rs_value, info);
6592     const char *rt = GPR(rt_value, info);
6593 
6594     return img_format("DSLLV %s, %s, %s", rd, rs, rt);
6595 }
6596 
6597 
6598 /*
6599  * DSRA -
6600  *
6601  *   3         2         1
6602  *  10987654321098765432109876543210
6603  *  10o000          1100xxx0100
6604  *     rt -----
6605  *          rs -----
6606  *                       shift -----
6607  */
6608 static char *DSRA(uint64 instruction, Dis_info *info)
6609 {
6610     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6611     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6612     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6613 
6614     const char *rt = GPR(rt_value, info);
6615     const char *rs = GPR(rs_value, info);
6616 
6617     return img_format("DSRA %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6618 }
6619 
6620 
6621 /*
6622  * DSRA[32] -
6623  *
6624  *   3         2         1
6625  *  10987654321098765432109876543210
6626  *  10o000          1100xxx0100
6627  *     rt -----
6628  *          rs -----
6629  *                       shift -----
6630  */
6631 static char *DSRA32(uint64 instruction, Dis_info *info)
6632 {
6633     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6634     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6635     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6636 
6637     const char *rt = GPR(rt_value, info);
6638     const char *rs = GPR(rs_value, info);
6639 
6640     return img_format("DSRA32 %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6641 }
6642 
6643 
6644 /*
6645  *
6646  *
6647  *   3         2         1
6648  *  10987654321098765432109876543210
6649  *  001000               x1110000101
6650  *     rt -----
6651  *          rs -----
6652  *               rd -----
6653  */
6654 static char *DSRAV(uint64 instruction, Dis_info *info)
6655 {
6656     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6657     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6658     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6659 
6660     const char *rd = GPR(rd_value, info);
6661     const char *rs = GPR(rs_value, info);
6662     const char *rt = GPR(rt_value, info);
6663 
6664     return img_format("DSRAV %s, %s, %s", rd, rs, rt);
6665 }
6666 
6667 
6668 /*
6669  * DSRL -
6670  *
6671  *   3         2         1
6672  *  10987654321098765432109876543210
6673  *  10o000          1100xxx0100
6674  *     rt -----
6675  *          rs -----
6676  *                       shift -----
6677  */
6678 static char *DSRL(uint64 instruction, Dis_info *info)
6679 {
6680     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6681     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6682     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6683 
6684     const char *rt = GPR(rt_value, info);
6685     const char *rs = GPR(rs_value, info);
6686 
6687     return img_format("DSRL %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6688 }
6689 
6690 
6691 /*
6692  * DSRL[32] -
6693  *
6694  *   3         2         1
6695  *  10987654321098765432109876543210
6696  *  10o000          1100xxx0010
6697  *     rt -----
6698  *          rs -----
6699  *                       shift -----
6700  */
6701 static char *DSRL32(uint64 instruction, Dis_info *info)
6702 {
6703     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6704     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6705     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
6706 
6707     const char *rt = GPR(rt_value, info);
6708     const char *rs = GPR(rs_value, info);
6709 
6710     return img_format("DSRL32 %s, %s, 0x%" PRIx64, rt, rs, shift_value);
6711 }
6712 
6713 
6714 /*
6715  *
6716  *
6717  *   3         2         1
6718  *  10987654321098765432109876543210
6719  *  001000               x1110000101
6720  *     rt -----
6721  *          rs -----
6722  *               rd -----
6723  */
6724 static char *DSRLV(uint64 instruction, Dis_info *info)
6725 {
6726     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6727     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6728     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6729 
6730     const char *rd = GPR(rd_value, info);
6731     const char *rs = GPR(rs_value, info);
6732     const char *rt = GPR(rt_value, info);
6733 
6734     return img_format("DSRLV %s, %s, %s", rd, rs, rt);
6735 }
6736 
6737 
6738 /*
6739  *
6740  *
6741  *   3         2         1
6742  *  10987654321098765432109876543210
6743  *  001000               x1110000101
6744  *     rt -----
6745  *          rs -----
6746  *               rd -----
6747  */
6748 static char *DSUB(uint64 instruction, Dis_info *info)
6749 {
6750     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6751     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6752     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6753 
6754     const char *rd = GPR(rd_value, info);
6755     const char *rs = GPR(rs_value, info);
6756     const char *rt = GPR(rt_value, info);
6757 
6758     return img_format("DSUB %s, %s, %s", rd, rs, rt);
6759 }
6760 
6761 
6762 /*
6763  *
6764  *
6765  *   3         2         1
6766  *  10987654321098765432109876543210
6767  *  001000               x1110000101
6768  *     rt -----
6769  *          rs -----
6770  *               rd -----
6771  */
6772 static char *DSUBU(uint64 instruction, Dis_info *info)
6773 {
6774     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6775     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6776     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
6777 
6778     const char *rd = GPR(rd_value, info);
6779     const char *rs = GPR(rs_value, info);
6780     const char *rt = GPR(rt_value, info);
6781 
6782     return img_format("DSUBU %s, %s, %s", rd, rs, rt);
6783 }
6784 
6785 
6786 /*
6787  *
6788  *
6789  *   3         2         1
6790  *  10987654321098765432109876543210
6791  *  001000               x1110000101
6792  *     rt -----
6793  *          rs -----
6794  *               rd -----
6795  */
6796 static char *DVPE(uint64 instruction, Dis_info *info)
6797 {
6798     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6799 
6800     const char *rt = GPR(rt_value, info);
6801 
6802     return img_format("DVPE %s", rt);
6803 }
6804 
6805 
6806 /*
6807  *
6808  *
6809  *   3         2         1
6810  *  10987654321098765432109876543210
6811  *  001000               x1110000101
6812  *     rt -----
6813  *          rs -----
6814  *               rd -----
6815  */
6816 static char *DVP(uint64 instruction, Dis_info *info)
6817 {
6818     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6819 
6820     const char *rt = GPR(rt_value, info);
6821 
6822     return img_format("DVP %s", rt);
6823 }
6824 
6825 
6826 /*
6827  *
6828  *
6829  *   3         2         1
6830  *  10987654321098765432109876543210
6831  *  001000               x1110000101
6832  *     rt -----
6833  *          rs -----
6834  *               rd -----
6835  */
6836 static char *EHB(uint64 instruction, Dis_info *info)
6837 {
6838     (void)instruction;
6839 
6840     return g_strdup("EHB ");
6841 }
6842 
6843 
6844 /*
6845  *
6846  *
6847  *   3         2         1
6848  *  10987654321098765432109876543210
6849  *  001000               x1110000101
6850  *     rt -----
6851  *          rs -----
6852  *               rd -----
6853  */
6854 static char *EI(uint64 instruction, Dis_info *info)
6855 {
6856     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6857 
6858     const char *rt = GPR(rt_value, info);
6859 
6860     return img_format("EI %s", rt);
6861 }
6862 
6863 
6864 /*
6865  *
6866  *
6867  *   3         2         1
6868  *  10987654321098765432109876543210
6869  *  001000               x1110000101
6870  *     rt -----
6871  *          rs -----
6872  *               rd -----
6873  */
6874 static char *EMT(uint64 instruction, Dis_info *info)
6875 {
6876     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6877 
6878     const char *rt = GPR(rt_value, info);
6879 
6880     return img_format("EMT %s", rt);
6881 }
6882 
6883 
6884 /*
6885  *
6886  *
6887  *   3         2         1
6888  *  10987654321098765432109876543210
6889  *  001000               x1110000101
6890  *     rt -----
6891  *          rs -----
6892  *               rd -----
6893  */
6894 static char *ERET(uint64 instruction, Dis_info *info)
6895 {
6896     (void)instruction;
6897 
6898     return g_strdup("ERET ");
6899 }
6900 
6901 
6902 /*
6903  *
6904  *
6905  *   3         2         1
6906  *  10987654321098765432109876543210
6907  *  001000               x1110000101
6908  *     rt -----
6909  *          rs -----
6910  *               rd -----
6911  */
6912 static char *ERETNC(uint64 instruction, Dis_info *info)
6913 {
6914     (void)instruction;
6915 
6916     return g_strdup("ERETNC ");
6917 }
6918 
6919 
6920 /*
6921  *
6922  *
6923  *   3         2         1
6924  *  10987654321098765432109876543210
6925  *  001000               x1110000101
6926  *     rt -----
6927  *          rs -----
6928  *               rd -----
6929  */
6930 static char *EVP(uint64 instruction, Dis_info *info)
6931 {
6932     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6933 
6934     const char *rt = GPR(rt_value, info);
6935 
6936     return img_format("EVP %s", rt);
6937 }
6938 
6939 
6940 /*
6941  *
6942  *
6943  *   3         2         1
6944  *  10987654321098765432109876543210
6945  *  001000               x1110000101
6946  *     rt -----
6947  *          rs -----
6948  *               rd -----
6949  */
6950 static char *EVPE(uint64 instruction, Dis_info *info)
6951 {
6952     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6953 
6954     const char *rt = GPR(rt_value, info);
6955 
6956     return img_format("EVPE %s", rt);
6957 }
6958 
6959 
6960 /*
6961  *
6962  *
6963  *   3         2         1
6964  *  10987654321098765432109876543210
6965  *  001000               x1110000101
6966  *     rt -----
6967  *          rs -----
6968  *               rd -----
6969  */
6970 static char *EXT(uint64 instruction, Dis_info *info)
6971 {
6972     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6973     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
6974     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
6975     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
6976 
6977     const char *rt = GPR(rt_value, info);
6978     const char *rs = GPR(rs_value, info);
6979     uint64 msbd = encode_msbd_from_size(msbd_value);
6980 
6981     return img_format("EXT %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
6982                       rt, rs, lsb_value, msbd);
6983 }
6984 
6985 
6986 /*
6987  *
6988  *
6989  *   3         2         1
6990  *  10987654321098765432109876543210
6991  *  001000               x1110000101
6992  *     rt -----
6993  *          rs -----
6994  *               rd -----
6995  */
6996 static char *EXTD(uint64 instruction, Dis_info *info)
6997 {
6998     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
6999     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7000     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7001     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7002 
7003     const char *rd = GPR(rd_value, info);
7004     const char *rs = GPR(rs_value, info);
7005     const char *rt = GPR(rt_value, info);
7006 
7007     return img_format("EXTD %s, %s, %s, 0x%" PRIx64, rd, rs, rt, shift_value);
7008 }
7009 
7010 
7011 /*
7012  *
7013  *
7014  *   3         2         1
7015  *  10987654321098765432109876543210
7016  *  001000               x1110000101
7017  *     rt -----
7018  *          rs -----
7019  *               rd -----
7020  */
7021 static char *EXTD32(uint64 instruction, Dis_info *info)
7022 {
7023     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7024     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7025     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7026     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7027 
7028     const char *rd = GPR(rd_value, info);
7029     const char *rs = GPR(rs_value, info);
7030     const char *rt = GPR(rt_value, info);
7031 
7032     return img_format("EXTD32 %s, %s, %s, 0x%" PRIx64, rd, rs, rt, shift_value);
7033 }
7034 
7035 
7036 /*
7037  *
7038  *
7039  *   3         2         1
7040  *  10987654321098765432109876543210
7041  *  001000               x1110000101
7042  *     rt -----
7043  *          rs -----
7044  *               rd -----
7045  */
7046 static char *EXTPDP(uint64 instruction, Dis_info *info)
7047 {
7048     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7049     uint64 size_value = extract_size_20_19_18_17_16(instruction);
7050     uint64 ac_value = extract_ac_15_14(instruction);
7051 
7052     const char *rt = GPR(rt_value, info);
7053     const char *ac = AC(ac_value, info);
7054 
7055     return img_format("EXTPDP %s, %s, 0x%" PRIx64, rt, ac, size_value);
7056 }
7057 
7058 
7059 /*
7060  *
7061  *
7062  *   3         2         1
7063  *  10987654321098765432109876543210
7064  *  001000               x1110000101
7065  *     rt -----
7066  *          rs -----
7067  *               rd -----
7068  */
7069 static char *EXTPDPV(uint64 instruction, Dis_info *info)
7070 {
7071     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7072     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7073     uint64 ac_value = extract_ac_15_14(instruction);
7074 
7075     const char *rt = GPR(rt_value, info);
7076     const char *ac = AC(ac_value, info);
7077     const char *rs = GPR(rs_value, info);
7078 
7079     return img_format("EXTPDPV %s, %s, %s", rt, ac, rs);
7080 }
7081 
7082 
7083 /*
7084  *
7085  *
7086  *   3         2         1
7087  *  10987654321098765432109876543210
7088  *  001000               x1110000101
7089  *     rt -----
7090  *          rs -----
7091  *               rd -----
7092  */
7093 static char *EXTP(uint64 instruction, Dis_info *info)
7094 {
7095     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7096     uint64 size_value = extract_size_20_19_18_17_16(instruction);
7097     uint64 ac_value = extract_ac_15_14(instruction);
7098 
7099     const char *rt = GPR(rt_value, info);
7100     const char *ac = AC(ac_value, info);
7101 
7102     return img_format("EXTP %s, %s, 0x%" PRIx64, rt, ac, size_value);
7103 }
7104 
7105 
7106 /*
7107  *
7108  *
7109  *   3         2         1
7110  *  10987654321098765432109876543210
7111  *  001000               x1110000101
7112  *     rt -----
7113  *          rs -----
7114  *               rd -----
7115  */
7116 static char *EXTPV(uint64 instruction, Dis_info *info)
7117 {
7118     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7119     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7120     uint64 ac_value = extract_ac_15_14(instruction);
7121 
7122     const char *rt = GPR(rt_value, info);
7123     const char *ac = AC(ac_value, info);
7124     const char *rs = GPR(rs_value, info);
7125 
7126     return img_format("EXTPV %s, %s, %s", rt, ac, rs);
7127 }
7128 
7129 
7130 /*
7131  * [DSP] EXTR_RS.W rt, ac, shift - Extract word value from accumulator to GPR
7132  *   with right shift
7133  *
7134  *   3         2         1
7135  *  10987654321098765432109876543210
7136  *  001000            10111001111111
7137  *     rt -----
7138  *       shift -----
7139  *               ac --
7140  */
7141 static char *EXTR_RS_W(uint64 instruction, Dis_info *info)
7142 {
7143     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7144     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7145     uint64 ac_value = extract_ac_15_14(instruction);
7146 
7147     const char *rt = GPR(rt_value, info);
7148     const char *ac = AC(ac_value, info);
7149 
7150     return img_format("EXTR_RS.W %s, %s, 0x%" PRIx64, rt, ac, shift_value);
7151 }
7152 
7153 
7154 /*
7155  * [DSP] EXTR_R.W rt, ac, shift - Extract word value from accumulator to GPR
7156  *   with right shift
7157  *
7158  *   3         2         1
7159  *  10987654321098765432109876543210
7160  *  001000            01111001111111
7161  *     rt -----
7162  *       shift -----
7163  *               ac --
7164  */
7165 static char *EXTR_R_W(uint64 instruction, Dis_info *info)
7166 {
7167     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7168     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7169     uint64 ac_value = extract_ac_15_14(instruction);
7170 
7171     const char *rt = GPR(rt_value, info);
7172     const char *ac = AC(ac_value, info);
7173 
7174     return img_format("EXTR_R.W %s, %s, 0x%" PRIx64, rt, ac, shift_value);
7175 }
7176 
7177 
7178 /*
7179  * [DSP] EXTR_S.H rt, ac, shift - Extract halfword value from accumulator
7180  *   to GPR with right shift and saturate
7181  *
7182  *   3         2         1
7183  *  10987654321098765432109876543210
7184  *  001000            11111001111111
7185  *     rt -----
7186  *       shift -----
7187  *               ac --
7188  */
7189 static char *EXTR_S_H(uint64 instruction, Dis_info *info)
7190 {
7191     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7192     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7193     uint64 ac_value = extract_ac_15_14(instruction);
7194 
7195     const char *rt = GPR(rt_value, info);
7196     const char *ac = AC(ac_value, info);
7197 
7198     return img_format("EXTR_S.H %s, %s, 0x%" PRIx64, rt, ac, shift_value);
7199 }
7200 
7201 
7202 /*
7203  * [DSP] EXTR.W rt, ac, shift - Extract word value from accumulator to GPR
7204  *   with right shift
7205  *
7206  *   3         2         1
7207  *  10987654321098765432109876543210
7208  *  001000            00111001111111
7209  *     rt -----
7210  *       shift -----
7211  *               ac --
7212  */
7213 static char *EXTR_W(uint64 instruction, Dis_info *info)
7214 {
7215     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7216     uint64 shift_value = extract_shift_20_19_18_17_16(instruction);
7217     uint64 ac_value = extract_ac_15_14(instruction);
7218 
7219     const char *rt = GPR(rt_value, info);
7220     const char *ac = AC(ac_value, info);
7221 
7222     return img_format("EXTR.W %s, %s, 0x%" PRIx64, rt, ac, shift_value);
7223 }
7224 
7225 
7226 /*
7227  * [DSP] EXTRV_RS.W rt, ac, rs - Extract word value with variable
7228  *   right shift from accumulator to GPR
7229  *
7230  *   3         2         1
7231  *  10987654321098765432109876543210
7232  *  001000            10111010111111
7233  *     rt -----
7234  *          rs -----
7235  *               ac --
7236  */
7237 static char *EXTRV_RS_W(uint64 instruction, Dis_info *info)
7238 {
7239     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7240     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7241     uint64 ac_value = extract_ac_15_14(instruction);
7242 
7243     const char *rt = GPR(rt_value, info);
7244     const char *ac = AC(ac_value, info);
7245     const char *rs = GPR(rs_value, info);
7246 
7247     return img_format("EXTRV_RS.W %s, %s, %s", rt, ac, rs);
7248 }
7249 
7250 
7251 /*
7252  * [DSP] EXTRV_R.W rt, ac, rs - Extract word value with variable
7253  *   right shift from accumulator to GPR
7254  *
7255  *   3         2         1
7256  *  10987654321098765432109876543210
7257  *  001000            01111010111111
7258  *     rt -----
7259  *          rs -----
7260  *               ac --
7261  */
7262 static char *EXTRV_R_W(uint64 instruction, Dis_info *info)
7263 {
7264     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7265     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7266     uint64 ac_value = extract_ac_15_14(instruction);
7267 
7268     const char *rt = GPR(rt_value, info);
7269     const char *ac = AC(ac_value, info);
7270     const char *rs = GPR(rs_value, info);
7271 
7272     return img_format("EXTRV_R.W %s, %s, %s", rt, ac, rs);
7273 }
7274 
7275 
7276 /*
7277  * [DSP] EXTRV_S.H rt, ac, rs - Extract halfword value variable from
7278  *   accumulator to GPR with right shift and saturate
7279  *
7280  *   3         2         1
7281  *  10987654321098765432109876543210
7282  *  001000            11111010111111
7283  *     rt -----
7284  *          rs -----
7285  *               ac --
7286  */
7287 static char *EXTRV_S_H(uint64 instruction, Dis_info *info)
7288 {
7289     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7290     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7291     uint64 ac_value = extract_ac_15_14(instruction);
7292 
7293     const char *rt = GPR(rt_value, info);
7294     const char *ac = AC(ac_value, info);
7295     const char *rs = GPR(rs_value, info);
7296 
7297     return img_format("EXTRV_S.H %s, %s, %s", rt, ac, rs);
7298 }
7299 
7300 
7301 /*
7302  * [DSP] EXTRV.W rt, ac, rs - Extract word value with variable
7303  *   right shift from accumulator to GPR
7304  *
7305  *   3         2         1
7306  *  10987654321098765432109876543210
7307  *  001000            00111010111111
7308  *     rt -----
7309  *          rs -----
7310  *               ac --
7311  */
7312 static char *EXTRV_W(uint64 instruction, Dis_info *info)
7313 {
7314     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7315     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7316     uint64 ac_value = extract_ac_15_14(instruction);
7317 
7318     const char *rt = GPR(rt_value, info);
7319     const char *ac = AC(ac_value, info);
7320     const char *rs = GPR(rs_value, info);
7321 
7322     return img_format("EXTRV.W %s, %s, %s", rt, ac, rs);
7323 }
7324 
7325 
7326 /*
7327  * EXTW - Extract Word
7328  *
7329  *   3         2         1
7330  *  10987654321098765432109876543210
7331  *  001000                    011111
7332  *     rt -----
7333  *          rs -----
7334  *               rd -----
7335  *                 shift -----
7336  */
7337 static char *EXTW(uint64 instruction, Dis_info *info)
7338 {
7339     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7340     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7341     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7342     uint64 shift_value = extract_shift_10_9_8_7_6(instruction);
7343 
7344     const char *rd = GPR(rd_value, info);
7345     const char *rs = GPR(rs_value, info);
7346     const char *rt = GPR(rt_value, info);
7347 
7348     return img_format("EXTW %s, %s, %s, 0x%" PRIx64, rd, rs, rt, shift_value);
7349 }
7350 
7351 
7352 /*
7353  *
7354  *
7355  *   3         2         1
7356  *  10987654321098765432109876543210
7357  *  001000               x1110000101
7358  *     rt -----
7359  *          rs -----
7360  *               rd -----
7361  */
7362 static char *FLOOR_L_D(uint64 instruction, Dis_info *info)
7363 {
7364     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7365     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7366 
7367     const char *ft = FPR(ft_value, info);
7368     const char *fs = FPR(fs_value, info);
7369 
7370     return img_format("FLOOR.L.D %s, %s", ft, fs);
7371 }
7372 
7373 
7374 /*
7375  *
7376  *
7377  *   3         2         1
7378  *  10987654321098765432109876543210
7379  *  001000               x1110000101
7380  *     rt -----
7381  *          rs -----
7382  *               rd -----
7383  */
7384 static char *FLOOR_L_S(uint64 instruction, Dis_info *info)
7385 {
7386     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7387     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7388 
7389     const char *ft = FPR(ft_value, info);
7390     const char *fs = FPR(fs_value, info);
7391 
7392     return img_format("FLOOR.L.S %s, %s", ft, fs);
7393 }
7394 
7395 
7396 /*
7397  *
7398  *
7399  *   3         2         1
7400  *  10987654321098765432109876543210
7401  *  001000               x1110000101
7402  *     rt -----
7403  *          rs -----
7404  *               rd -----
7405  */
7406 static char *FLOOR_W_D(uint64 instruction, Dis_info *info)
7407 {
7408     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7409     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7410 
7411     const char *ft = FPR(ft_value, info);
7412     const char *fs = FPR(fs_value, info);
7413 
7414     return img_format("FLOOR.W.D %s, %s", ft, fs);
7415 }
7416 
7417 
7418 /*
7419  *
7420  *
7421  *   3         2         1
7422  *  10987654321098765432109876543210
7423  *  001000               x1110000101
7424  *     rt -----
7425  *          rs -----
7426  *               rd -----
7427  */
7428 static char *FLOOR_W_S(uint64 instruction, Dis_info *info)
7429 {
7430     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
7431     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
7432 
7433     const char *ft = FPR(ft_value, info);
7434     const char *fs = FPR(fs_value, info);
7435 
7436     return img_format("FLOOR.W.S %s, %s", ft, fs);
7437 }
7438 
7439 
7440 /*
7441  *
7442  *
7443  *   3         2         1
7444  *  10987654321098765432109876543210
7445  *  001000               x1110000101
7446  *     rt -----
7447  *          rs -----
7448  *               rd -----
7449  */
7450 static char *FORK(uint64 instruction, Dis_info *info)
7451 {
7452     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7453     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7454     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7455 
7456     const char *rd = GPR(rd_value, info);
7457     const char *rs = GPR(rs_value, info);
7458     const char *rt = GPR(rt_value, info);
7459 
7460     return img_format("FORK %s, %s, %s", rd, rs, rt);
7461 }
7462 
7463 
7464 /*
7465  *
7466  *
7467  *   3         2         1
7468  *  10987654321098765432109876543210
7469  *  001000               x1110000101
7470  *     rt -----
7471  *          rs -----
7472  *               rd -----
7473  */
7474 static char *HYPCALL(uint64 instruction, Dis_info *info)
7475 {
7476     uint64 code_value = extract_code_17_to_0(instruction);
7477 
7478 
7479     return img_format("HYPCALL 0x%" PRIx64, code_value);
7480 }
7481 
7482 
7483 /*
7484  *
7485  *
7486  *   3         2         1
7487  *  10987654321098765432109876543210
7488  *  001000               x1110000101
7489  *     rt -----
7490  *          rs -----
7491  *               rd -----
7492  */
7493 static char *HYPCALL_16_(uint64 instruction, Dis_info *info)
7494 {
7495     uint64 code_value = extract_code_1_0(instruction);
7496 
7497 
7498     return img_format("HYPCALL 0x%" PRIx64, code_value);
7499 }
7500 
7501 
7502 /*
7503  *
7504  *
7505  *   3         2         1
7506  *  10987654321098765432109876543210
7507  *  001000               x1110000101
7508  *     rt -----
7509  *          rs -----
7510  *               rd -----
7511  */
7512 static char *INS(uint64 instruction, Dis_info *info)
7513 {
7514     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7515     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7516     uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction);
7517     uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction);
7518 
7519     const char *rt = GPR(rt_value, info);
7520     const char *rs = GPR(rs_value, info);
7521     /* !!!!!!!!!! - no conversion function */
7522 
7523     return img_format("INS %s, %s, 0x%" PRIx64 ", 0x%" PRIx64,
7524                       rt, rs, lsb_value, msbd_value);
7525     /* hand edited */
7526 }
7527 
7528 
7529 /*
7530  * [DSP] INSV rt, rs - Insert bit field variable
7531  *
7532  *   3         2         1
7533  *  10987654321098765432109876543210
7534  *  001000          0100000100111111
7535  *     rt -----
7536  *          rs -----
7537  */
7538 static char *INSV(uint64 instruction, Dis_info *info)
7539 {
7540     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7541     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7542 
7543     const char *rt = GPR(rt_value, info);
7544     const char *rs = GPR(rs_value, info);
7545 
7546     return img_format("INSV %s, %s", rt, rs);
7547 }
7548 
7549 
7550 /*
7551  *
7552  *
7553  *   3         2         1
7554  *  10987654321098765432109876543210
7555  *  001000               x1110000101
7556  *     rt -----
7557  *          rs -----
7558  *               rd -----
7559  */
7560 static char *IRET(uint64 instruction, Dis_info *info)
7561 {
7562     (void)instruction;
7563 
7564     return g_strdup("IRET ");
7565 }
7566 
7567 
7568 /*
7569  *
7570  *
7571  *   3         2         1
7572  *  10987654321098765432109876543210
7573  *  001000               x1110000101
7574  *     rt -----
7575  *          rs -----
7576  *               rd -----
7577  */
7578 static char *JALRC_16_(uint64 instruction, Dis_info *info)
7579 {
7580     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
7581 
7582     const char *rt = GPR(rt_value, info);
7583 
7584     return img_format("JALRC $%d, %s", 31, rt);
7585 }
7586 
7587 
7588 /*
7589  *
7590  *
7591  *   3         2         1
7592  *  10987654321098765432109876543210
7593  *  001000               x1110000101
7594  *     rt -----
7595  *          rs -----
7596  *               rd -----
7597  */
7598 static char *JALRC_32_(uint64 instruction, Dis_info *info)
7599 {
7600     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7601     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7602 
7603     const char *rt = GPR(rt_value, info);
7604     const char *rs = GPR(rs_value, info);
7605 
7606     return img_format("JALRC %s, %s", rt, rs);
7607 }
7608 
7609 
7610 /*
7611  *
7612  *
7613  *   3         2         1
7614  *  10987654321098765432109876543210
7615  *  001000               x1110000101
7616  *     rt -----
7617  *          rs -----
7618  *               rd -----
7619  */
7620 static char *JALRC_HB(uint64 instruction, Dis_info *info)
7621 {
7622     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7623     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7624 
7625     const char *rt = GPR(rt_value, info);
7626     const char *rs = GPR(rs_value, info);
7627 
7628     return img_format("JALRC.HB %s, %s", rt, rs);
7629 }
7630 
7631 
7632 /*
7633  *
7634  *
7635  *   3         2         1
7636  *  10987654321098765432109876543210
7637  *  001000               x1110000101
7638  *     rt -----
7639  *          rs -----
7640  *               rd -----
7641  */
7642 static char *JRC(uint64 instruction, Dis_info *info)
7643 {
7644     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
7645 
7646     const char *rt = GPR(rt_value, info);
7647 
7648     return img_format("JRC %s", rt);
7649 }
7650 
7651 
7652 /*
7653  *
7654  *
7655  *   3         2         1
7656  *  10987654321098765432109876543210
7657  *  001000               x1110000101
7658  *     rt -----
7659  *          rs -----
7660  *               rd -----
7661  */
7662 static char *LB_16_(uint64 instruction, Dis_info *info)
7663 {
7664     uint64 rt3_value = extract_rt3_9_8_7(instruction);
7665     uint64 rs3_value = extract_rs3_6_5_4(instruction);
7666     uint64 u_value = extract_u_1_0(instruction);
7667 
7668     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
7669     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
7670 
7671     return img_format("LB %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3);
7672 }
7673 
7674 
7675 /*
7676  *
7677  *
7678  *   3         2         1
7679  *  10987654321098765432109876543210
7680  *  001000               x1110000101
7681  *     rt -----
7682  *          rs -----
7683  *               rd -----
7684  */
7685 static char *LB_GP_(uint64 instruction, Dis_info *info)
7686 {
7687     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7688     uint64 u_value = extract_u_17_to_0(instruction);
7689 
7690     const char *rt = GPR(rt_value, info);
7691 
7692     return img_format("LB %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
7693 }
7694 
7695 
7696 /*
7697  *
7698  *
7699  *   3         2         1
7700  *  10987654321098765432109876543210
7701  *  001000               x1110000101
7702  *     rt -----
7703  *          rs -----
7704  *               rd -----
7705  */
7706 static char *LB_S9_(uint64 instruction, Dis_info *info)
7707 {
7708     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7709     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7710     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
7711 
7712     const char *rt = GPR(rt_value, info);
7713     const char *rs = GPR(rs_value, info);
7714 
7715     return img_format("LB %s, %" PRId64 "(%s)", rt, s_value, rs);
7716 }
7717 
7718 
7719 /*
7720  *
7721  *
7722  *   3         2         1
7723  *  10987654321098765432109876543210
7724  *  001000               x1110000101
7725  *     rt -----
7726  *          rs -----
7727  *               rd -----
7728  */
7729 static char *LB_U12_(uint64 instruction, Dis_info *info)
7730 {
7731     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7732     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7733     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
7734 
7735     const char *rt = GPR(rt_value, info);
7736     const char *rs = GPR(rs_value, info);
7737 
7738     return img_format("LB %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
7739 }
7740 
7741 
7742 /*
7743  *
7744  *
7745  *   3         2         1
7746  *  10987654321098765432109876543210
7747  *  001000               x1110000101
7748  *     rt -----
7749  *          rs -----
7750  *               rd -----
7751  */
7752 static char *LBE(uint64 instruction, Dis_info *info)
7753 {
7754     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7755     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7756     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
7757 
7758     const char *rt = GPR(rt_value, info);
7759     const char *rs = GPR(rs_value, info);
7760 
7761     return img_format("LBE %s, %" PRId64 "(%s)", rt, s_value, rs);
7762 }
7763 
7764 
7765 /*
7766  *
7767  *
7768  *   3         2         1
7769  *  10987654321098765432109876543210
7770  *  001000               x1110000101
7771  *     rt -----
7772  *          rs -----
7773  *               rd -----
7774  */
7775 static char *LBU_16_(uint64 instruction, Dis_info *info)
7776 {
7777     uint64 rt3_value = extract_rt3_9_8_7(instruction);
7778     uint64 rs3_value = extract_rs3_6_5_4(instruction);
7779     uint64 u_value = extract_u_1_0(instruction);
7780 
7781     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
7782     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
7783 
7784     return img_format("LBU %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3);
7785 }
7786 
7787 
7788 /*
7789  *
7790  *
7791  *   3         2         1
7792  *  10987654321098765432109876543210
7793  *  001000               x1110000101
7794  *     rt -----
7795  *          rs -----
7796  *               rd -----
7797  */
7798 static char *LBU_GP_(uint64 instruction, Dis_info *info)
7799 {
7800     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7801     uint64 u_value = extract_u_17_to_0(instruction);
7802 
7803     const char *rt = GPR(rt_value, info);
7804 
7805     return img_format("LBU %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
7806 }
7807 
7808 
7809 /*
7810  *
7811  *
7812  *   3         2         1
7813  *  10987654321098765432109876543210
7814  *  001000               x1110000101
7815  *     rt -----
7816  *          rs -----
7817  *               rd -----
7818  */
7819 static char *LBU_S9_(uint64 instruction, Dis_info *info)
7820 {
7821     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7822     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7823     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
7824 
7825     const char *rt = GPR(rt_value, info);
7826     const char *rs = GPR(rs_value, info);
7827 
7828     return img_format("LBU %s, %" PRId64 "(%s)", rt, s_value, rs);
7829 }
7830 
7831 
7832 /*
7833  *
7834  *
7835  *   3         2         1
7836  *  10987654321098765432109876543210
7837  *  001000               x1110000101
7838  *     rt -----
7839  *          rs -----
7840  *               rd -----
7841  */
7842 static char *LBU_U12_(uint64 instruction, Dis_info *info)
7843 {
7844     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7845     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7846     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
7847 
7848     const char *rt = GPR(rt_value, info);
7849     const char *rs = GPR(rs_value, info);
7850 
7851     return img_format("LBU %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
7852 }
7853 
7854 
7855 /*
7856  *
7857  *
7858  *   3         2         1
7859  *  10987654321098765432109876543210
7860  *  001000               x1110000101
7861  *     rt -----
7862  *          rs -----
7863  *               rd -----
7864  */
7865 static char *LBUE(uint64 instruction, Dis_info *info)
7866 {
7867     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7868     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7869     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
7870 
7871     const char *rt = GPR(rt_value, info);
7872     const char *rs = GPR(rs_value, info);
7873 
7874     return img_format("LBUE %s, %" PRId64 "(%s)", rt, s_value, rs);
7875 }
7876 
7877 
7878 /*
7879  *
7880  *
7881  *   3         2         1
7882  *  10987654321098765432109876543210
7883  *  001000               x1110000101
7884  *     rt -----
7885  *          rs -----
7886  *               rd -----
7887  */
7888 static char *LBUX(uint64 instruction, Dis_info *info)
7889 {
7890     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7891     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7892     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7893 
7894     const char *rd = GPR(rd_value, info);
7895     const char *rs = GPR(rs_value, info);
7896     const char *rt = GPR(rt_value, info);
7897 
7898     return img_format("LBUX %s, %s(%s)", rd, rs, rt);
7899 }
7900 
7901 
7902 /*
7903  *
7904  *
7905  *   3         2         1
7906  *  10987654321098765432109876543210
7907  *  001000               x1110000101
7908  *     rt -----
7909  *          rs -----
7910  *               rd -----
7911  */
7912 static char *LBX(uint64 instruction, Dis_info *info)
7913 {
7914     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7915     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7916     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
7917 
7918     const char *rd = GPR(rd_value, info);
7919     const char *rs = GPR(rs_value, info);
7920     const char *rt = GPR(rt_value, info);
7921 
7922     return img_format("LBX %s, %s(%s)", rd, rs, rt);
7923 }
7924 
7925 
7926 /*
7927  *
7928  *
7929  *   3         2         1
7930  *  10987654321098765432109876543210
7931  *  001000               x1110000101
7932  *     rt -----
7933  *          rs -----
7934  *               rd -----
7935  */
7936 static char *LD_GP_(uint64 instruction, Dis_info *info)
7937 {
7938     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7939     uint64 u_value = extract_u_20_to_3__s3(instruction);
7940 
7941     const char *rt = GPR(rt_value, info);
7942 
7943     return img_format("LD %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
7944 }
7945 
7946 
7947 /*
7948  *
7949  *
7950  *   3         2         1
7951  *  10987654321098765432109876543210
7952  *  001000               x1110000101
7953  *     rt -----
7954  *          rs -----
7955  *               rd -----
7956  */
7957 static char *LD_S9_(uint64 instruction, Dis_info *info)
7958 {
7959     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7960     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7961     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
7962 
7963     const char *rt = GPR(rt_value, info);
7964     const char *rs = GPR(rs_value, info);
7965 
7966     return img_format("LD %s, %" PRId64 "(%s)", rt, s_value, rs);
7967 }
7968 
7969 
7970 /*
7971  *
7972  *
7973  *   3         2         1
7974  *  10987654321098765432109876543210
7975  *  001000               x1110000101
7976  *     rt -----
7977  *          rs -----
7978  *               rd -----
7979  */
7980 static char *LD_U12_(uint64 instruction, Dis_info *info)
7981 {
7982     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
7983     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
7984     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
7985 
7986     const char *rt = GPR(rt_value, info);
7987     const char *rs = GPR(rs_value, info);
7988 
7989     return img_format("LD %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
7990 }
7991 
7992 
7993 /*
7994  *
7995  *
7996  *   3         2         1
7997  *  10987654321098765432109876543210
7998  *  001000               x1110000101
7999  *     rt -----
8000  *          rs -----
8001  *               rd -----
8002  */
8003 static char *LDC1_GP_(uint64 instruction, Dis_info *info)
8004 {
8005     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8006     uint64 u_value = extract_u_17_to_2__s2(instruction);
8007 
8008     const char *ft = FPR(ft_value, info);
8009 
8010     return img_format("LDC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28);
8011 }
8012 
8013 
8014 /*
8015  *
8016  *
8017  *   3         2         1
8018  *  10987654321098765432109876543210
8019  *  001000               x1110000101
8020  *     rt -----
8021  *          rs -----
8022  *               rd -----
8023  */
8024 static char *LDC1_S9_(uint64 instruction, Dis_info *info)
8025 {
8026     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8027     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8028     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8029 
8030     const char *ft = FPR(ft_value, info);
8031     const char *rs = GPR(rs_value, info);
8032 
8033     return img_format("LDC1 %s, %" PRId64 "(%s)", ft, s_value, rs);
8034 }
8035 
8036 
8037 /*
8038  *
8039  *
8040  *   3         2         1
8041  *  10987654321098765432109876543210
8042  *  001000               x1110000101
8043  *     rt -----
8044  *          rs -----
8045  *               rd -----
8046  */
8047 static char *LDC1_U12_(uint64 instruction, Dis_info *info)
8048 {
8049     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8050     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8051     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8052 
8053     const char *ft = FPR(ft_value, info);
8054     const char *rs = GPR(rs_value, info);
8055 
8056     return img_format("LDC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs);
8057 }
8058 
8059 
8060 /*
8061  *
8062  *
8063  *   3         2         1
8064  *  10987654321098765432109876543210
8065  *  001000               x1110000101
8066  *     rt -----
8067  *          rs -----
8068  *               rd -----
8069  */
8070 static char *LDC1XS(uint64 instruction, Dis_info *info)
8071 {
8072     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8073     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8074     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
8075 
8076     const char *ft = FPR(ft_value, info);
8077     const char *rs = GPR(rs_value, info);
8078     const char *rt = GPR(rt_value, info);
8079 
8080     return img_format("LDC1XS %s, %s(%s)", ft, rs, rt);
8081 }
8082 
8083 
8084 /*
8085  *
8086  *
8087  *   3         2         1
8088  *  10987654321098765432109876543210
8089  *  001000               x1110000101
8090  *     rt -----
8091  *          rs -----
8092  *               rd -----
8093  */
8094 static char *LDC1X(uint64 instruction, Dis_info *info)
8095 {
8096     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8097     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8098     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
8099 
8100     const char *ft = FPR(ft_value, info);
8101     const char *rs = GPR(rs_value, info);
8102     const char *rt = GPR(rt_value, info);
8103 
8104     return img_format("LDC1X %s, %s(%s)", ft, rs, rt);
8105 }
8106 
8107 
8108 /*
8109  *
8110  *
8111  *   3         2         1
8112  *  10987654321098765432109876543210
8113  *  001000               x1110000101
8114  *     rt -----
8115  *          rs -----
8116  *               rd -----
8117  */
8118 static char *LDC2(uint64 instruction, Dis_info *info)
8119 {
8120     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
8121     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8122     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8123 
8124     const char *rs = GPR(rs_value, info);
8125 
8126     return img_format("LDC2 CP%" PRIu64 ", %" PRId64 "(%s)",
8127                       ct_value, s_value, rs);
8128 }
8129 
8130 
8131 /*
8132  *
8133  *
8134  *   3         2         1
8135  *  10987654321098765432109876543210
8136  *  001000               x1110000101
8137  *     rt -----
8138  *          rs -----
8139  *               rd -----
8140  */
8141 static char *LDM(uint64 instruction, Dis_info *info)
8142 {
8143     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8144     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8145     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8146     uint64 count3_value = extract_count3_14_13_12(instruction);
8147 
8148     const char *rt = GPR(rt_value, info);
8149     const char *rs = GPR(rs_value, info);
8150     uint64 count3 = encode_count3_from_count(count3_value);
8151 
8152     return img_format("LDM %s, %" PRId64 "(%s), 0x%" PRIx64,
8153                       rt, s_value, rs, count3);
8154 }
8155 
8156 
8157 /*
8158  *
8159  *
8160  *   3         2         1
8161  *  10987654321098765432109876543210
8162  *  001000               x1110000101
8163  *     rt -----
8164  *          rs -----
8165  *               rd -----
8166  */
8167 static char *LDPC_48_(uint64 instruction, Dis_info *info)
8168 {
8169     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
8170     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
8171 
8172     const char *rt = GPR(rt_value, info);
8173     g_autofree char *s = ADDRESS(s_value, 6, info);
8174 
8175     return img_format("LDPC %s, %s", rt, s);
8176 }
8177 
8178 
8179 /*
8180  *
8181  *
8182  *   3         2         1
8183  *  10987654321098765432109876543210
8184  *  001000               x1110000101
8185  *     rt -----
8186  *          rs -----
8187  *               rd -----
8188  */
8189 static char *LDX(uint64 instruction, Dis_info *info)
8190 {
8191     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8192     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8193     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8194 
8195     const char *rd = GPR(rd_value, info);
8196     const char *rs = GPR(rs_value, info);
8197     const char *rt = GPR(rt_value, info);
8198 
8199     return img_format("LDX %s, %s(%s)", rd, rs, rt);
8200 }
8201 
8202 
8203 /*
8204  *
8205  *
8206  *   3         2         1
8207  *  10987654321098765432109876543210
8208  *  001000               x1110000101
8209  *     rt -----
8210  *          rs -----
8211  *               rd -----
8212  */
8213 static char *LDXS(uint64 instruction, Dis_info *info)
8214 {
8215     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8216     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8217     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8218 
8219     const char *rd = GPR(rd_value, info);
8220     const char *rs = GPR(rs_value, info);
8221     const char *rt = GPR(rt_value, info);
8222 
8223     return img_format("LDXS %s, %s(%s)", rd, rs, rt);
8224 }
8225 
8226 
8227 /*
8228  *
8229  *
8230  *   3         2         1
8231  *  10987654321098765432109876543210
8232  *  001000               x1110000101
8233  *     rt -----
8234  *          rs -----
8235  *               rd -----
8236  */
8237 static char *LH_16_(uint64 instruction, Dis_info *info)
8238 {
8239     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8240     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8241     uint64 u_value = extract_u_2_1__s1(instruction);
8242 
8243     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
8244     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
8245 
8246     return img_format("LH %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3);
8247 }
8248 
8249 
8250 /*
8251  *
8252  *
8253  *   3         2         1
8254  *  10987654321098765432109876543210
8255  *  001000               x1110000101
8256  *     rt -----
8257  *          rs -----
8258  *               rd -----
8259  */
8260 static char *LH_GP_(uint64 instruction, Dis_info *info)
8261 {
8262     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8263     uint64 u_value = extract_u_17_to_1__s1(instruction);
8264 
8265     const char *rt = GPR(rt_value, info);
8266 
8267     return img_format("LH %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
8268 }
8269 
8270 
8271 /*
8272  *
8273  *
8274  *   3         2         1
8275  *  10987654321098765432109876543210
8276  *  001000               x1110000101
8277  *     rt -----
8278  *          rs -----
8279  *               rd -----
8280  */
8281 static char *LH_S9_(uint64 instruction, Dis_info *info)
8282 {
8283     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8284     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8285     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8286 
8287     const char *rt = GPR(rt_value, info);
8288     const char *rs = GPR(rs_value, info);
8289 
8290     return img_format("LH %s, %" PRId64 "(%s)", rt, s_value, rs);
8291 }
8292 
8293 
8294 /*
8295  *
8296  *
8297  *   3         2         1
8298  *  10987654321098765432109876543210
8299  *  001000               x1110000101
8300  *     rt -----
8301  *          rs -----
8302  *               rd -----
8303  */
8304 static char *LH_U12_(uint64 instruction, Dis_info *info)
8305 {
8306     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8307     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8308     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8309 
8310     const char *rt = GPR(rt_value, info);
8311     const char *rs = GPR(rs_value, info);
8312 
8313     return img_format("LH %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
8314 }
8315 
8316 
8317 /*
8318  *
8319  *
8320  *   3         2         1
8321  *  10987654321098765432109876543210
8322  *  001000               x1110000101
8323  *     rt -----
8324  *          rs -----
8325  *               rd -----
8326  */
8327 static char *LHE(uint64 instruction, Dis_info *info)
8328 {
8329     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8330     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8331     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8332 
8333     const char *rt = GPR(rt_value, info);
8334     const char *rs = GPR(rs_value, info);
8335 
8336     return img_format("LHE %s, %" PRId64 "(%s)", rt, s_value, rs);
8337 }
8338 
8339 
8340 /*
8341  *
8342  *
8343  *   3         2         1
8344  *  10987654321098765432109876543210
8345  *  001000               x1110000101
8346  *     rt -----
8347  *          rs -----
8348  *               rd -----
8349  */
8350 static char *LHU_16_(uint64 instruction, Dis_info *info)
8351 {
8352     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8353     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8354     uint64 u_value = extract_u_2_1__s1(instruction);
8355 
8356     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
8357     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
8358 
8359     return img_format("LHU %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3);
8360 }
8361 
8362 
8363 /*
8364  *
8365  *
8366  *   3         2         1
8367  *  10987654321098765432109876543210
8368  *  001000               x1110000101
8369  *     rt -----
8370  *          rs -----
8371  *               rd -----
8372  */
8373 static char *LHU_GP_(uint64 instruction, Dis_info *info)
8374 {
8375     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8376     uint64 u_value = extract_u_17_to_1__s1(instruction);
8377 
8378     const char *rt = GPR(rt_value, info);
8379 
8380     return img_format("LHU %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
8381 }
8382 
8383 
8384 /*
8385  *
8386  *
8387  *   3         2         1
8388  *  10987654321098765432109876543210
8389  *  001000               x1110000101
8390  *     rt -----
8391  *          rs -----
8392  *               rd -----
8393  */
8394 static char *LHU_S9_(uint64 instruction, Dis_info *info)
8395 {
8396     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8397     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8398     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8399 
8400     const char *rt = GPR(rt_value, info);
8401     const char *rs = GPR(rs_value, info);
8402 
8403     return img_format("LHU %s, %" PRId64 "(%s)", rt, s_value, rs);
8404 }
8405 
8406 
8407 /*
8408  *
8409  *
8410  *   3         2         1
8411  *  10987654321098765432109876543210
8412  *  001000               x1110000101
8413  *     rt -----
8414  *          rs -----
8415  *               rd -----
8416  */
8417 static char *LHU_U12_(uint64 instruction, Dis_info *info)
8418 {
8419     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8420     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8421     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8422 
8423     const char *rt = GPR(rt_value, info);
8424     const char *rs = GPR(rs_value, info);
8425 
8426     return img_format("LHU %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
8427 }
8428 
8429 
8430 /*
8431  *
8432  *
8433  *   3         2         1
8434  *  10987654321098765432109876543210
8435  *  001000               x1110000101
8436  *     rt -----
8437  *          rs -----
8438  *               rd -----
8439  */
8440 static char *LHUE(uint64 instruction, Dis_info *info)
8441 {
8442     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8443     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8444     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8445 
8446     const char *rt = GPR(rt_value, info);
8447     const char *rs = GPR(rs_value, info);
8448 
8449     return img_format("LHUE %s, %" PRId64 "(%s)", rt, s_value, rs);
8450 }
8451 
8452 
8453 /*
8454  *
8455  *
8456  *   3         2         1
8457  *  10987654321098765432109876543210
8458  *  001000               x1110000101
8459  *     rt -----
8460  *          rs -----
8461  *               rd -----
8462  */
8463 static char *LHUX(uint64 instruction, Dis_info *info)
8464 {
8465     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8466     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8467     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8468 
8469     const char *rd = GPR(rd_value, info);
8470     const char *rs = GPR(rs_value, info);
8471     const char *rt = GPR(rt_value, info);
8472 
8473     return img_format("LHUX %s, %s(%s)", rd, rs, rt);
8474 }
8475 
8476 
8477 /*
8478  *
8479  *
8480  *   3         2         1
8481  *  10987654321098765432109876543210
8482  *  001000               x1110000101
8483  *     rt -----
8484  *          rs -----
8485  *               rd -----
8486  */
8487 static char *LHUXS(uint64 instruction, Dis_info *info)
8488 {
8489     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8490     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8491     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8492 
8493     const char *rd = GPR(rd_value, info);
8494     const char *rs = GPR(rs_value, info);
8495     const char *rt = GPR(rt_value, info);
8496 
8497     return img_format("LHUXS %s, %s(%s)", rd, rs, rt);
8498 }
8499 
8500 
8501 /*
8502  *
8503  *
8504  *   3         2         1
8505  *  10987654321098765432109876543210
8506  *  001000               x1110000101
8507  *     rt -----
8508  *          rs -----
8509  *               rd -----
8510  */
8511 static char *LHXS(uint64 instruction, Dis_info *info)
8512 {
8513     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8514     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8515     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8516 
8517     const char *rd = GPR(rd_value, info);
8518     const char *rs = GPR(rs_value, info);
8519     const char *rt = GPR(rt_value, info);
8520 
8521     return img_format("LHXS %s, %s(%s)", rd, rs, rt);
8522 }
8523 
8524 
8525 /*
8526  *
8527  *
8528  *   3         2         1
8529  *  10987654321098765432109876543210
8530  *  001000               x1110000101
8531  *     rt -----
8532  *          rs -----
8533  *               rd -----
8534  */
8535 static char *LHX(uint64 instruction, Dis_info *info)
8536 {
8537     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8538     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8539     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8540 
8541     const char *rd = GPR(rd_value, info);
8542     const char *rs = GPR(rs_value, info);
8543     const char *rt = GPR(rt_value, info);
8544 
8545     return img_format("LHX %s, %s(%s)", rd, rs, rt);
8546 }
8547 
8548 
8549 /*
8550  *
8551  *
8552  *   3         2         1
8553  *  10987654321098765432109876543210
8554  *  001000               x1110000101
8555  *     rt -----
8556  *          rs -----
8557  *               rd -----
8558  */
8559 static char *LI_16_(uint64 instruction, Dis_info *info)
8560 {
8561     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8562     uint64 eu_value = extract_eu_6_5_4_3_2_1_0(instruction);
8563 
8564     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
8565     int64 eu = encode_eu_from_s_li16(eu_value);
8566 
8567     return img_format("LI %s, %" PRId64, rt3, eu);
8568 }
8569 
8570 
8571 /*
8572  *
8573  *
8574  *   3         2         1
8575  *  10987654321098765432109876543210
8576  *  001000               x1110000101
8577  *     rt -----
8578  *          rs -----
8579  *               rd -----
8580  */
8581 static char *LI_48_(uint64 instruction, Dis_info *info)
8582 {
8583     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
8584     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
8585 
8586     const char *rt = GPR(rt_value, info);
8587 
8588     return img_format("LI %s, %" PRId64, rt, s_value);
8589 }
8590 
8591 
8592 /*
8593  *
8594  *
8595  *   3         2         1
8596  *  10987654321098765432109876543210
8597  *  001000               x1110000101
8598  *     rt -----
8599  *          rs -----
8600  *               rd -----
8601  */
8602 static char *LL(uint64 instruction, Dis_info *info)
8603 {
8604     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8605     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8606     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
8607 
8608     const char *rt = GPR(rt_value, info);
8609     const char *rs = GPR(rs_value, info);
8610 
8611     return img_format("LL %s, %" PRId64 "(%s)", rt, s_value, rs);
8612 }
8613 
8614 
8615 /*
8616  *
8617  *
8618  *   3         2         1
8619  *  10987654321098765432109876543210
8620  *  001000               x1110000101
8621  *     rt -----
8622  *          rs -----
8623  *               rd -----
8624  */
8625 static char *LLD(uint64 instruction, Dis_info *info)
8626 {
8627     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8628     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8629     int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction);
8630 
8631     const char *rt = GPR(rt_value, info);
8632     const char *rs = GPR(rs_value, info);
8633 
8634     return img_format("LLD %s, %" PRId64 "(%s)", rt, s_value, rs);
8635 }
8636 
8637 
8638 /*
8639  *
8640  *
8641  *   3         2         1
8642  *  10987654321098765432109876543210
8643  *  001000               x1110000101
8644  *     rt -----
8645  *          rs -----
8646  *               rd -----
8647  */
8648 static char *LLDP(uint64 instruction, Dis_info *info)
8649 {
8650     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8651     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8652     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
8653 
8654     const char *rt = GPR(rt_value, info);
8655     const char *ru = GPR(ru_value, info);
8656     const char *rs = GPR(rs_value, info);
8657 
8658     return img_format("LLDP %s, %s, (%s)", rt, ru, rs);
8659 }
8660 
8661 
8662 /*
8663  *
8664  *
8665  *   3         2         1
8666  *  10987654321098765432109876543210
8667  *  001000               x1110000101
8668  *     rt -----
8669  *          rs -----
8670  *               rd -----
8671  */
8672 static char *LLE(uint64 instruction, Dis_info *info)
8673 {
8674     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8675     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8676     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
8677 
8678     const char *rt = GPR(rt_value, info);
8679     const char *rs = GPR(rs_value, info);
8680 
8681     return img_format("LLE %s, %" PRId64 "(%s)", rt, s_value, rs);
8682 }
8683 
8684 
8685 /*
8686  *
8687  *
8688  *   3         2         1
8689  *  10987654321098765432109876543210
8690  *  001000               x1110000101
8691  *     rt -----
8692  *          rs -----
8693  *               rd -----
8694  */
8695 static char *LLWP(uint64 instruction, Dis_info *info)
8696 {
8697     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8698     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8699     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
8700 
8701     const char *rt = GPR(rt_value, info);
8702     const char *ru = GPR(ru_value, info);
8703     const char *rs = GPR(rs_value, info);
8704 
8705     return img_format("LLWP %s, %s, (%s)", rt, ru, rs);
8706 }
8707 
8708 
8709 /*
8710  *
8711  *
8712  *   3         2         1
8713  *  10987654321098765432109876543210
8714  *  001000               x1110000101
8715  *     rt -----
8716  *          rs -----
8717  *               rd -----
8718  */
8719 static char *LLWPE(uint64 instruction, Dis_info *info)
8720 {
8721     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8722     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8723     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
8724 
8725     const char *rt = GPR(rt_value, info);
8726     const char *ru = GPR(ru_value, info);
8727     const char *rs = GPR(rs_value, info);
8728 
8729     return img_format("LLWPE %s, %s, (%s)", rt, ru, rs);
8730 }
8731 
8732 
8733 /*
8734  *
8735  *
8736  *   3         2         1
8737  *  10987654321098765432109876543210
8738  *  001000               x1110000101
8739  *     rt -----
8740  *          rs -----
8741  *               rd -----
8742  */
8743 static char *LSA(uint64 instruction, Dis_info *info)
8744 {
8745     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8746     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8747     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
8748     uint64 u2_value = extract_u2_10_9(instruction);
8749 
8750     const char *rd = GPR(rd_value, info);
8751     const char *rs = GPR(rs_value, info);
8752     const char *rt = GPR(rt_value, info);
8753 
8754     return img_format("LSA %s, %s, %s, 0x%" PRIx64, rd, rs, rt, u2_value);
8755 }
8756 
8757 
8758 /*
8759  *
8760  *
8761  *   3         2         1
8762  *  10987654321098765432109876543210
8763  *  001000               x1110000101
8764  *     rt -----
8765  *          rs -----
8766  *               rd -----
8767  */
8768 static char *LUI(uint64 instruction, Dis_info *info)
8769 {
8770     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8771     int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction);
8772 
8773     const char *rt = GPR(rt_value, info);
8774 
8775     return img_format("LUI %s, %%hi(%" PRId64 ")", rt, s_value);
8776 }
8777 
8778 
8779 /*
8780  *
8781  *
8782  *   3         2         1
8783  *  10987654321098765432109876543210
8784  *  001000               x1110000101
8785  *     rt -----
8786  *          rs -----
8787  *               rd -----
8788  */
8789 static char *LW_16_(uint64 instruction, Dis_info *info)
8790 {
8791     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8792     uint64 rs3_value = extract_rs3_6_5_4(instruction);
8793     uint64 u_value = extract_u_3_2_1_0__s2(instruction);
8794 
8795     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
8796     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
8797 
8798     return img_format("LW %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3);
8799 }
8800 
8801 
8802 /*
8803  *
8804  *
8805  *   3         2         1
8806  *  10987654321098765432109876543210
8807  *  001000               x1110000101
8808  *     rt -----
8809  *          rs -----
8810  *               rd -----
8811  */
8812 static char *LW_4X4_(uint64 instruction, Dis_info *info)
8813 {
8814     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
8815     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
8816     uint64 u_value = extract_u_3_8__s2(instruction);
8817 
8818     const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info);
8819     const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info);
8820 
8821     return img_format("LW %s, 0x%" PRIx64 "(%s)", rt4, u_value, rs4);
8822 }
8823 
8824 
8825 /*
8826  *
8827  *
8828  *   3         2         1
8829  *  10987654321098765432109876543210
8830  *  001000               x1110000101
8831  *     rt -----
8832  *          rs -----
8833  *               rd -----
8834  */
8835 static char *LW_GP_(uint64 instruction, Dis_info *info)
8836 {
8837     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8838     uint64 u_value = extract_u_20_to_2__s2(instruction);
8839 
8840     const char *rt = GPR(rt_value, info);
8841 
8842     return img_format("LW %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
8843 }
8844 
8845 
8846 /*
8847  *
8848  *
8849  *   3         2         1
8850  *  10987654321098765432109876543210
8851  *  001000               x1110000101
8852  *     rt -----
8853  *          rs -----
8854  *               rd -----
8855  */
8856 static char *LW_GP16_(uint64 instruction, Dis_info *info)
8857 {
8858     uint64 rt3_value = extract_rt3_9_8_7(instruction);
8859     uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction);
8860 
8861     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
8862 
8863     return img_format("LW %s, 0x%" PRIx64 "($%d)", rt3, u_value, 28);
8864 }
8865 
8866 
8867 /*
8868  *
8869  *
8870  *   3         2         1
8871  *  10987654321098765432109876543210
8872  *  001000               x1110000101
8873  *     rt -----
8874  *          rs -----
8875  *               rd -----
8876  */
8877 static char *LW_S9_(uint64 instruction, Dis_info *info)
8878 {
8879     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8880     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8881     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8882 
8883     const char *rt = GPR(rt_value, info);
8884     const char *rs = GPR(rs_value, info);
8885 
8886     return img_format("LW %s, %" PRId64 "(%s)", rt, s_value, rs);
8887 }
8888 
8889 
8890 /*
8891  *
8892  *
8893  *   3         2         1
8894  *  10987654321098765432109876543210
8895  *  001000               x1110000101
8896  *     rt -----
8897  *          rs -----
8898  *               rd -----
8899  */
8900 static char *LW_SP_(uint64 instruction, Dis_info *info)
8901 {
8902     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
8903     uint64 u_value = extract_u_4_3_2_1_0__s2(instruction);
8904 
8905     const char *rt = GPR(rt_value, info);
8906 
8907     return img_format("LW %s, 0x%" PRIx64 "($%d)", rt, u_value, 29);
8908 }
8909 
8910 
8911 /*
8912  *
8913  *
8914  *   3         2         1
8915  *  10987654321098765432109876543210
8916  *  001000               x1110000101
8917  *     rt -----
8918  *          rs -----
8919  *               rd -----
8920  */
8921 static char *LW_U12_(uint64 instruction, Dis_info *info)
8922 {
8923     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
8924     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8925     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8926 
8927     const char *rt = GPR(rt_value, info);
8928     const char *rs = GPR(rs_value, info);
8929 
8930     return img_format("LW %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
8931 }
8932 
8933 
8934 /*
8935  *
8936  *
8937  *   3         2         1
8938  *  10987654321098765432109876543210
8939  *  001000               x1110000101
8940  *     rt -----
8941  *          rs -----
8942  *               rd -----
8943  */
8944 static char *LWC1_GP_(uint64 instruction, Dis_info *info)
8945 {
8946     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8947     uint64 u_value = extract_u_17_to_2__s2(instruction);
8948 
8949     const char *ft = FPR(ft_value, info);
8950 
8951     return img_format("LWC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28);
8952 }
8953 
8954 
8955 /*
8956  *
8957  *
8958  *   3         2         1
8959  *  10987654321098765432109876543210
8960  *  001000               x1110000101
8961  *     rt -----
8962  *          rs -----
8963  *               rd -----
8964  */
8965 static char *LWC1_S9_(uint64 instruction, Dis_info *info)
8966 {
8967     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8968     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8969     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
8970 
8971     const char *ft = FPR(ft_value, info);
8972     const char *rs = GPR(rs_value, info);
8973 
8974     return img_format("LWC1 %s, %" PRId64 "(%s)", ft, s_value, rs);
8975 }
8976 
8977 
8978 /*
8979  *
8980  *
8981  *   3         2         1
8982  *  10987654321098765432109876543210
8983  *  001000               x1110000101
8984  *     rt -----
8985  *          rs -----
8986  *               rd -----
8987  */
8988 static char *LWC1_U12_(uint64 instruction, Dis_info *info)
8989 {
8990     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
8991     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
8992     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
8993 
8994     const char *ft = FPR(ft_value, info);
8995     const char *rs = GPR(rs_value, info);
8996 
8997     return img_format("LWC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs);
8998 }
8999 
9000 
9001 /*
9002  *
9003  *
9004  *   3         2         1
9005  *  10987654321098765432109876543210
9006  *  001000               x1110000101
9007  *     rt -----
9008  *          rs -----
9009  *               rd -----
9010  */
9011 static char *LWC1X(uint64 instruction, Dis_info *info)
9012 {
9013     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9014     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9015     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
9016 
9017     const char *ft = FPR(ft_value, info);
9018     const char *rs = GPR(rs_value, info);
9019     const char *rt = GPR(rt_value, info);
9020 
9021     return img_format("LWC1X %s, %s(%s)", ft, rs, rt);
9022 }
9023 
9024 
9025 /*
9026  *
9027  *
9028  *   3         2         1
9029  *  10987654321098765432109876543210
9030  *  001000               x1110000101
9031  *     rt -----
9032  *          rs -----
9033  *               rd -----
9034  */
9035 static char *LWC1XS(uint64 instruction, Dis_info *info)
9036 {
9037     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9038     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9039     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
9040 
9041     const char *ft = FPR(ft_value, info);
9042     const char *rs = GPR(rs_value, info);
9043     const char *rt = GPR(rt_value, info);
9044 
9045     return img_format("LWC1XS %s, %s(%s)", ft, rs, rt);
9046 }
9047 
9048 
9049 /*
9050  *
9051  *
9052  *   3         2         1
9053  *  10987654321098765432109876543210
9054  *  001000               x1110000101
9055  *     rt -----
9056  *          rs -----
9057  *               rd -----
9058  */
9059 static char *LWC2(uint64 instruction, Dis_info *info)
9060 {
9061     uint64 ct_value = extract_ct_25_24_23_22_21(instruction);
9062     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9063     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9064 
9065     const char *rs = GPR(rs_value, info);
9066 
9067     return img_format("LWC2 CP%" PRIu64 ", %" PRId64 "(%s)",
9068                       ct_value, s_value, rs);
9069 }
9070 
9071 
9072 /*
9073  *
9074  *
9075  *   3         2         1
9076  *  10987654321098765432109876543210
9077  *  001000               x1110000101
9078  *     rt -----
9079  *          rs -----
9080  *               rd -----
9081  */
9082 static char *LWE(uint64 instruction, Dis_info *info)
9083 {
9084     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9085     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9086     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9087 
9088     const char *rt = GPR(rt_value, info);
9089     const char *rs = GPR(rs_value, info);
9090 
9091     return img_format("LWE %s, %" PRId64 "(%s)", rt, s_value, rs);
9092 }
9093 
9094 
9095 /*
9096  *
9097  *
9098  *   3         2         1
9099  *  10987654321098765432109876543210
9100  *  001000               x1110000101
9101  *     rt -----
9102  *          rs -----
9103  *               rd -----
9104  */
9105 static char *LWM(uint64 instruction, Dis_info *info)
9106 {
9107     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9108     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9109     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9110     uint64 count3_value = extract_count3_14_13_12(instruction);
9111 
9112     const char *rt = GPR(rt_value, info);
9113     const char *rs = GPR(rs_value, info);
9114     uint64 count3 = encode_count3_from_count(count3_value);
9115 
9116     return img_format("LWM %s, %" PRId64 "(%s), 0x%" PRIx64,
9117                       rt, s_value, rs, count3);
9118 }
9119 
9120 
9121 /*
9122  *
9123  *
9124  *   3         2         1
9125  *  10987654321098765432109876543210
9126  *  001000               x1110000101
9127  *     rt -----
9128  *          rs -----
9129  *               rd -----
9130  */
9131 static char *LWPC_48_(uint64 instruction, Dis_info *info)
9132 {
9133     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
9134     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
9135 
9136     const char *rt = GPR(rt_value, info);
9137     g_autofree char *s = ADDRESS(s_value, 6, info);
9138 
9139     return img_format("LWPC %s, %s", rt, s);
9140 }
9141 
9142 
9143 /*
9144  *
9145  *
9146  *   3         2         1
9147  *  10987654321098765432109876543210
9148  *  001000               x1110000101
9149  *     rt -----
9150  *          rs -----
9151  *               rd -----
9152  */
9153 static char *LWU_GP_(uint64 instruction, Dis_info *info)
9154 {
9155     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9156     uint64 u_value = extract_u_17_to_2__s2(instruction);
9157 
9158     const char *rt = GPR(rt_value, info);
9159 
9160     return img_format("LWU %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
9161 }
9162 
9163 
9164 /*
9165  *
9166  *
9167  *   3         2         1
9168  *  10987654321098765432109876543210
9169  *  001000               x1110000101
9170  *     rt -----
9171  *          rs -----
9172  *               rd -----
9173  */
9174 static char *LWU_S9_(uint64 instruction, Dis_info *info)
9175 {
9176     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9177     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9178     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
9179 
9180     const char *rt = GPR(rt_value, info);
9181     const char *rs = GPR(rs_value, info);
9182 
9183     return img_format("LWU %s, %" PRId64 "(%s)", rt, s_value, rs);
9184 }
9185 
9186 
9187 /*
9188  *
9189  *
9190  *   3         2         1
9191  *  10987654321098765432109876543210
9192  *  001000               x1110000101
9193  *     rt -----
9194  *          rs -----
9195  *               rd -----
9196  */
9197 static char *LWU_U12_(uint64 instruction, Dis_info *info)
9198 {
9199     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9200     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9201     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
9202 
9203     const char *rt = GPR(rt_value, info);
9204     const char *rs = GPR(rs_value, info);
9205 
9206     return img_format("LWU %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
9207 }
9208 
9209 
9210 /*
9211  *
9212  *
9213  *   3         2         1
9214  *  10987654321098765432109876543210
9215  *  001000               x1110000101
9216  *     rt -----
9217  *          rs -----
9218  *               rd -----
9219  */
9220 static char *LWUX(uint64 instruction, Dis_info *info)
9221 {
9222     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9223     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9224     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9225 
9226     const char *rd = GPR(rd_value, info);
9227     const char *rs = GPR(rs_value, info);
9228     const char *rt = GPR(rt_value, info);
9229 
9230     return img_format("LWUX %s, %s(%s)", rd, rs, rt);
9231 }
9232 
9233 
9234 /*
9235  *
9236  *
9237  *   3         2         1
9238  *  10987654321098765432109876543210
9239  *  001000               x1110000101
9240  *     rt -----
9241  *          rs -----
9242  *               rd -----
9243  */
9244 static char *LWUXS(uint64 instruction, Dis_info *info)
9245 {
9246     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9247     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9248     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9249 
9250     const char *rd = GPR(rd_value, info);
9251     const char *rs = GPR(rs_value, info);
9252     const char *rt = GPR(rt_value, info);
9253 
9254     return img_format("LWUXS %s, %s(%s)", rd, rs, rt);
9255 }
9256 
9257 
9258 /*
9259  *
9260  *
9261  *   3         2         1
9262  *  10987654321098765432109876543210
9263  *  001000               x1110000101
9264  *     rt -----
9265  *          rs -----
9266  *               rd -----
9267  */
9268 static char *LWX(uint64 instruction, Dis_info *info)
9269 {
9270     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9271     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9272     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9273 
9274     const char *rd = GPR(rd_value, info);
9275     const char *rs = GPR(rs_value, info);
9276     const char *rt = GPR(rt_value, info);
9277 
9278     return img_format("LWX %s, %s(%s)", rd, rs, rt);
9279 }
9280 
9281 
9282 /*
9283  *
9284  *
9285  *   3         2         1
9286  *  10987654321098765432109876543210
9287  *  001000               x1110000101
9288  *     rt -----
9289  *          rs -----
9290  *               rd -----
9291  */
9292 static char *LWXS_16_(uint64 instruction, Dis_info *info)
9293 {
9294     uint64 rt3_value = extract_rt3_9_8_7(instruction);
9295     uint64 rs3_value = extract_rs3_6_5_4(instruction);
9296     uint64 rd3_value = extract_rd3_3_2_1(instruction);
9297 
9298     const char *rd3 = GPR(decode_gpr_gpr3(rd3_value, info), info);
9299     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
9300     uint64 rt3 = decode_gpr_gpr3(rt3_value, info);
9301 
9302     return img_format("LWXS %s, %s(0x%" PRIx64 ")", rd3, rs3, rt3);
9303 }
9304 
9305 
9306 /*
9307  *
9308  *
9309  *   3         2         1
9310  *  10987654321098765432109876543210
9311  *  001000               x1110000101
9312  *     rt -----
9313  *          rs -----
9314  *               rd -----
9315  */
9316 static char *LWXS_32_(uint64 instruction, Dis_info *info)
9317 {
9318     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9319     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9320     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
9321 
9322     const char *rd = GPR(rd_value, info);
9323     const char *rs = GPR(rs_value, info);
9324     const char *rt = GPR(rt_value, info);
9325 
9326     return img_format("LWXS %s, %s(%s)", rd, rs, rt);
9327 }
9328 
9329 
9330 /*
9331  * [DSP] MADD ac, rs, rt - Multiply two words and add to the specified
9332  *         accumulator
9333  *
9334  *   3         2         1
9335  *  10987654321098765432109876543210
9336  *  001000               x1110000101
9337  *     rt -----
9338  *          rs -----
9339  *               rd -----
9340  */
9341 static char *MADD_DSP_(uint64 instruction, Dis_info *info)
9342 {
9343     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9344     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9345     uint64 ac_value = extract_ac_15_14(instruction);
9346 
9347     const char *ac = AC(ac_value, info);
9348     const char *rs = GPR(rs_value, info);
9349     const char *rt = GPR(rt_value, info);
9350 
9351     return img_format("MADD %s, %s, %s", ac, rs, rt);
9352 }
9353 
9354 
9355 /*
9356  *
9357  *
9358  *   3         2         1
9359  *  10987654321098765432109876543210
9360  *  001000               x1110000101
9361  *     rt -----
9362  *          rs -----
9363  *               rd -----
9364  */
9365 static char *MADDF_D(uint64 instruction, Dis_info *info)
9366 {
9367     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9368     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9369     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9370 
9371     const char *fd = FPR(fd_value, info);
9372     const char *fs = FPR(fs_value, info);
9373     const char *ft = FPR(ft_value, info);
9374 
9375     return img_format("MADDF.D %s, %s, %s", fd, fs, ft);
9376 }
9377 
9378 
9379 /*
9380  *
9381  *
9382  *   3         2         1
9383  *  10987654321098765432109876543210
9384  *  001000               x1110000101
9385  *     rt -----
9386  *          rs -----
9387  *               rd -----
9388  */
9389 static char *MADDF_S(uint64 instruction, Dis_info *info)
9390 {
9391     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9392     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9393     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9394 
9395     const char *fd = FPR(fd_value, info);
9396     const char *fs = FPR(fs_value, info);
9397     const char *ft = FPR(ft_value, info);
9398 
9399     return img_format("MADDF.S %s, %s, %s", fd, fs, ft);
9400 }
9401 
9402 
9403 /*
9404  * [DSP] MADDU ac, rs, rt - Multiply two unsigned words and add to the
9405  *         specified accumulator
9406  *
9407  *   3         2         1
9408  *  10987654321098765432109876543210
9409  *  001000               x1110000101
9410  *     rt -----
9411  *          rs -----
9412  *               rd -----
9413  */
9414 static char *MADDU_DSP_(uint64 instruction, Dis_info *info)
9415 {
9416     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9417     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9418     uint64 ac_value = extract_ac_15_14(instruction);
9419 
9420     const char *ac = AC(ac_value, info);
9421     const char *rs = GPR(rs_value, info);
9422     const char *rt = GPR(rt_value, info);
9423 
9424     return img_format("MADDU %s, %s, %s", ac, rs, rt);
9425 }
9426 
9427 
9428 /*
9429  * [DSP] MAQ_S.W.PHL ac, rs, rt - Multiply the left-most single vector
9430  *         fractional halfword elements with accumulation
9431  *
9432  *   3         2         1
9433  *  10987654321098765432109876543210
9434  *  001000               x1110000101
9435  *     rt -----
9436  *          rs -----
9437  *               rd -----
9438  */
9439 static char *MAQ_S_W_PHL(uint64 instruction, Dis_info *info)
9440 {
9441     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9442     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9443     uint64 ac_value = extract_ac_15_14(instruction);
9444 
9445     const char *ac = AC(ac_value, info);
9446     const char *rs = GPR(rs_value, info);
9447     const char *rt = GPR(rt_value, info);
9448 
9449     return img_format("MAQ_S.W.PHL %s, %s, %s", ac, rs, rt);
9450 }
9451 
9452 
9453 /*
9454  * [DSP] MAQ_S.W.PHR ac, rs, rt - Multiply the right-most single vector
9455  *         fractional halfword elements with accumulation
9456  *
9457  *   3         2         1
9458  *  10987654321098765432109876543210
9459  *  001000               x1110000101
9460  *     rt -----
9461  *          rs -----
9462  *               rd -----
9463  */
9464 static char *MAQ_S_W_PHR(uint64 instruction, Dis_info *info)
9465 {
9466     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9467     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9468     uint64 ac_value = extract_ac_15_14(instruction);
9469 
9470     const char *ac = AC(ac_value, info);
9471     const char *rs = GPR(rs_value, info);
9472     const char *rt = GPR(rt_value, info);
9473 
9474     return img_format("MAQ_S.W.PHR %s, %s, %s", ac, rs, rt);
9475 }
9476 
9477 
9478 /*
9479  * [DSP] MAQ_SA.W.PHL ac, rs, rt - Multiply the left-most single vector
9480  *         fractional halfword elements with saturating accumulation
9481  *
9482  *   3         2         1
9483  *  10987654321098765432109876543210
9484  *  001000               x1110000101
9485  *     rt -----
9486  *          rs -----
9487  *               rd -----
9488  */
9489 static char *MAQ_SA_W_PHL(uint64 instruction, Dis_info *info)
9490 {
9491     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9492     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9493     uint64 ac_value = extract_ac_15_14(instruction);
9494 
9495     const char *ac = AC(ac_value, info);
9496     const char *rs = GPR(rs_value, info);
9497     const char *rt = GPR(rt_value, info);
9498 
9499     return img_format("MAQ_SA.W.PHL %s, %s, %s", ac, rs, rt);
9500 }
9501 
9502 
9503 /*
9504  * [DSP] MAQ_SA.W.PHR ac, rs, rt - Multiply the right-most single vector
9505  *         fractional halfword elements with saturating accumulation
9506  *
9507  *   3         2         1
9508  *  10987654321098765432109876543210
9509  *  001000               x1110000101
9510  *     rt -----
9511  *          rs -----
9512  *               rd -----
9513  */
9514 static char *MAQ_SA_W_PHR(uint64 instruction, Dis_info *info)
9515 {
9516     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9517     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
9518     uint64 ac_value = extract_ac_15_14(instruction);
9519 
9520     const char *ac = AC(ac_value, info);
9521     const char *rs = GPR(rs_value, info);
9522     const char *rt = GPR(rt_value, info);
9523 
9524     return img_format("MAQ_SA.W.PHR %s, %s, %s", ac, rs, rt);
9525 }
9526 
9527 
9528 /*
9529  *
9530  *
9531  *   3         2         1
9532  *  10987654321098765432109876543210
9533  *  001000               x1110000101
9534  *     rt -----
9535  *          rs -----
9536  *               rd -----
9537  */
9538 static char *MAX_D(uint64 instruction, Dis_info *info)
9539 {
9540     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9541     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9542     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9543 
9544     const char *fd = FPR(fd_value, info);
9545     const char *fs = FPR(fs_value, info);
9546     const char *ft = FPR(ft_value, info);
9547 
9548     return img_format("MAX.D %s, %s, %s", fd, fs, ft);
9549 }
9550 
9551 
9552 /*
9553  *
9554  *
9555  *   3         2         1
9556  *  10987654321098765432109876543210
9557  *  001000               x1110000101
9558  *     rt -----
9559  *          rs -----
9560  *               rd -----
9561  */
9562 static char *MAX_S(uint64 instruction, Dis_info *info)
9563 {
9564     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9565     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9566     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9567 
9568     const char *fd = FPR(fd_value, info);
9569     const char *fs = FPR(fs_value, info);
9570     const char *ft = FPR(ft_value, info);
9571 
9572     return img_format("MAX.S %s, %s, %s", fd, fs, ft);
9573 }
9574 
9575 
9576 /*
9577  *
9578  *
9579  *   3         2         1
9580  *  10987654321098765432109876543210
9581  *  001000               x1110000101
9582  *     rt -----
9583  *          rs -----
9584  *               rd -----
9585  */
9586 static char *MAXA_D(uint64 instruction, Dis_info *info)
9587 {
9588     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9589     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9590     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9591 
9592     const char *fd = FPR(fd_value, info);
9593     const char *fs = FPR(fs_value, info);
9594     const char *ft = FPR(ft_value, info);
9595 
9596     return img_format("MAXA.D %s, %s, %s", fd, fs, ft);
9597 }
9598 
9599 
9600 /*
9601  *
9602  *
9603  *   3         2         1
9604  *  10987654321098765432109876543210
9605  *  001000               x1110000101
9606  *     rt -----
9607  *          rs -----
9608  *               rd -----
9609  */
9610 static char *MAXA_S(uint64 instruction, Dis_info *info)
9611 {
9612     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9613     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9614     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9615 
9616     const char *fd = FPR(fd_value, info);
9617     const char *fs = FPR(fs_value, info);
9618     const char *ft = FPR(ft_value, info);
9619 
9620     return img_format("MAXA.S %s, %s, %s", fd, fs, ft);
9621 }
9622 
9623 
9624 /*
9625  *
9626  *
9627  *   3         2         1
9628  *  10987654321098765432109876543210
9629  *  001000               x1110000101
9630  *     rt -----
9631  *          rs -----
9632  *               rd -----
9633  */
9634 static char *MFC0(uint64 instruction, Dis_info *info)
9635 {
9636     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9637     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9638     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9639 
9640     const char *rt = GPR(rt_value, info);
9641 
9642     return img_format("MFC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
9643                       rt, c0s_value, sel_value);
9644 }
9645 
9646 
9647 /*
9648  *
9649  *
9650  *   3         2         1
9651  *  10987654321098765432109876543210
9652  *  001000               x1110000101
9653  *     rt -----
9654  *          rs -----
9655  *               rd -----
9656  */
9657 static char *MFC1(uint64 instruction, Dis_info *info)
9658 {
9659     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9660     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9661 
9662     const char *rt = GPR(rt_value, info);
9663     const char *fs = FPR(fs_value, info);
9664 
9665     return img_format("MFC1 %s, %s", rt, fs);
9666 }
9667 
9668 
9669 /*
9670  *
9671  *
9672  *   3         2         1
9673  *  10987654321098765432109876543210
9674  *  001000               x1110000101
9675  *     rt -----
9676  *          rs -----
9677  *               rd -----
9678  */
9679 static char *MFC2(uint64 instruction, Dis_info *info)
9680 {
9681     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9682     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
9683 
9684     const char *rt = GPR(rt_value, info);
9685 
9686     return img_format("MFC2 %s, CP%" PRIu64, rt, cs_value);
9687 }
9688 
9689 
9690 /*
9691  *
9692  *
9693  *   3         2         1
9694  *  10987654321098765432109876543210
9695  *  001000               x1110000101
9696  *     rt -----
9697  *          rs -----
9698  *               rd -----
9699  */
9700 static char *MFGC0(uint64 instruction, Dis_info *info)
9701 {
9702     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9703     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9704     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9705 
9706     const char *rt = GPR(rt_value, info);
9707 
9708     return img_format("MFGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
9709                       rt, c0s_value, sel_value);
9710 }
9711 
9712 
9713 /*
9714  *
9715  *
9716  *   3         2         1
9717  *  10987654321098765432109876543210
9718  *  001000               x1110000101
9719  *     rt -----
9720  *          rs -----
9721  *               rd -----
9722  */
9723 static char *MFHC0(uint64 instruction, Dis_info *info)
9724 {
9725     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9726     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9727     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9728 
9729     const char *rt = GPR(rt_value, info);
9730 
9731     return img_format("MFHC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
9732                       rt, c0s_value, sel_value);
9733 }
9734 
9735 
9736 /*
9737  *
9738  *
9739  *   3         2         1
9740  *  10987654321098765432109876543210
9741  *  001000               x1110000101
9742  *     rt -----
9743  *          rs -----
9744  *               rd -----
9745  */
9746 static char *MFHC1(uint64 instruction, Dis_info *info)
9747 {
9748     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9749     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9750 
9751     const char *rt = GPR(rt_value, info);
9752     const char *fs = FPR(fs_value, info);
9753 
9754     return img_format("MFHC1 %s, %s", rt, fs);
9755 }
9756 
9757 
9758 /*
9759  *
9760  *
9761  *   3         2         1
9762  *  10987654321098765432109876543210
9763  *  001000               x1110000101
9764  *     rt -----
9765  *          rs -----
9766  *               rd -----
9767  */
9768 static char *MFHC2(uint64 instruction, Dis_info *info)
9769 {
9770     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9771     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
9772 
9773     const char *rt = GPR(rt_value, info);
9774 
9775     return img_format("MFHC2 %s, CP%" PRIu64, rt, cs_value);
9776 }
9777 
9778 
9779 /*
9780  *
9781  *
9782  *   3         2         1
9783  *  10987654321098765432109876543210
9784  *  001000               x1110000101
9785  *     rt -----
9786  *          rs -----
9787  *               rd -----
9788  */
9789 static char *MFHGC0(uint64 instruction, Dis_info *info)
9790 {
9791     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9792     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9793     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9794 
9795     const char *rt = GPR(rt_value, info);
9796 
9797     return img_format("MFHGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
9798                       rt, c0s_value, sel_value);
9799 }
9800 
9801 
9802 /*
9803  * [DSP] MFHI rs, ac - Move from HI register
9804  *
9805  *   3         2         1
9806  *  10987654321098765432109876543210
9807  *  001000     xxxxx  00000001111111
9808  *     rt -----
9809  *               ac --
9810  */
9811 static char *MFHI_DSP_(uint64 instruction, Dis_info *info)
9812 {
9813     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9814     uint64 ac_value = extract_ac_15_14(instruction);
9815 
9816     const char *rt = GPR(rt_value, info);
9817     const char *ac = AC(ac_value, info);
9818 
9819     return img_format("MFHI %s, %s", rt, ac);
9820 }
9821 
9822 
9823 /*
9824  *
9825  *
9826  *   3         2         1
9827  *  10987654321098765432109876543210
9828  *  001000               x1110000101
9829  *     rt -----
9830  *          rs -----
9831  *               rd -----
9832  */
9833 static char *MFHTR(uint64 instruction, Dis_info *info)
9834 {
9835     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9836     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9837     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9838     uint64 u_value = extract_u_10(instruction);
9839 
9840     const char *rt = GPR(rt_value, info);
9841 
9842     return img_format("MFHTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64,
9843                       rt, c0s_value, u_value, sel_value);
9844 }
9845 
9846 
9847 /*
9848  * [DSP] MFLO rs, ac - Move from HI register
9849  *
9850  *   3         2         1
9851  *  10987654321098765432109876543210
9852  *  001000     xxxxx  01000001111111
9853  *     rt -----
9854  *               ac --
9855  */
9856 static char *MFLO_DSP_(uint64 instruction, Dis_info *info)
9857 {
9858     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9859     uint64 ac_value = extract_ac_15_14(instruction);
9860 
9861     const char *rt = GPR(rt_value, info);
9862     const char *ac = AC(ac_value, info);
9863 
9864     return img_format("MFLO %s, %s", rt, ac);
9865 }
9866 
9867 
9868 /*
9869  *
9870  *
9871  *   3         2         1
9872  *  10987654321098765432109876543210
9873  *  001000               x1110000101
9874  *     rt -----
9875  *          rs -----
9876  *               rd -----
9877  */
9878 static char *MFTR(uint64 instruction, Dis_info *info)
9879 {
9880     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
9881     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
9882     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
9883     uint64 u_value = extract_u_10(instruction);
9884 
9885     const char *rt = GPR(rt_value, info);
9886 
9887     return img_format("MFTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64,
9888                       rt, c0s_value, u_value, sel_value);
9889 }
9890 
9891 
9892 /*
9893  *
9894  *
9895  *   3         2         1
9896  *  10987654321098765432109876543210
9897  *  001000               x1110000101
9898  *     rt -----
9899  *          rs -----
9900  *               rd -----
9901  */
9902 static char *MIN_D(uint64 instruction, Dis_info *info)
9903 {
9904     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9905     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9906     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9907 
9908     const char *fd = FPR(fd_value, info);
9909     const char *fs = FPR(fs_value, info);
9910     const char *ft = FPR(ft_value, info);
9911 
9912     return img_format("MIN.D %s, %s, %s", fd, fs, ft);
9913 }
9914 
9915 
9916 /*
9917  *
9918  *
9919  *   3         2         1
9920  *  10987654321098765432109876543210
9921  *  001000               x1110000101
9922  *     rt -----
9923  *          rs -----
9924  *               rd -----
9925  */
9926 static char *MIN_S(uint64 instruction, Dis_info *info)
9927 {
9928     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9929     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9930     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9931 
9932     const char *fd = FPR(fd_value, info);
9933     const char *fs = FPR(fs_value, info);
9934     const char *ft = FPR(ft_value, info);
9935 
9936     return img_format("MIN.S %s, %s, %s", fd, fs, ft);
9937 }
9938 
9939 
9940 /*
9941  *
9942  *
9943  *   3         2         1
9944  *  10987654321098765432109876543210
9945  *  001000               x1110000101
9946  *     rt -----
9947  *          rs -----
9948  *               rd -----
9949  */
9950 static char *MINA_D(uint64 instruction, Dis_info *info)
9951 {
9952     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9953     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9954     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9955 
9956     const char *fd = FPR(fd_value, info);
9957     const char *fs = FPR(fs_value, info);
9958     const char *ft = FPR(ft_value, info);
9959 
9960     return img_format("MINA.D %s, %s, %s", fd, fs, ft);
9961 }
9962 
9963 
9964 /*
9965  *
9966  *
9967  *   3         2         1
9968  *  10987654321098765432109876543210
9969  *  001000               x1110000101
9970  *     rt -----
9971  *          rs -----
9972  *               rd -----
9973  */
9974 static char *MINA_S(uint64 instruction, Dis_info *info)
9975 {
9976     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
9977     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
9978     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
9979 
9980     const char *fd = FPR(fd_value, info);
9981     const char *fs = FPR(fs_value, info);
9982     const char *ft = FPR(ft_value, info);
9983 
9984     return img_format("MINA.S %s, %s, %s", fd, fs, ft);
9985 }
9986 
9987 
9988 /*
9989  *
9990  *
9991  *   3         2         1
9992  *  10987654321098765432109876543210
9993  *  001000               x1110000101
9994  *     rt -----
9995  *          rs -----
9996  *               rd -----
9997  */
9998 static char *MOD(uint64 instruction, Dis_info *info)
9999 {
10000     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10001     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10002     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10003 
10004     const char *rd = GPR(rd_value, info);
10005     const char *rs = GPR(rs_value, info);
10006     const char *rt = GPR(rt_value, info);
10007 
10008     return img_format("MOD %s, %s, %s", rd, rs, rt);
10009 }
10010 
10011 
10012 /*
10013  * [DSP] MODSUB rd, rs, rt - Modular subtraction on an index value
10014  *
10015  *   3         2         1
10016  *  10987654321098765432109876543210
10017  *  001000               x1110000101
10018  *     rt -----
10019  *          rs -----
10020  *               rd -----
10021  */
10022 static char *MODSUB(uint64 instruction, Dis_info *info)
10023 {
10024     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10025     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10026     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10027 
10028     const char *rd = GPR(rd_value, info);
10029     const char *rs = GPR(rs_value, info);
10030     const char *rt = GPR(rt_value, info);
10031 
10032     return img_format("MODSUB %s, %s, %s", rd, rs, rt);
10033 }
10034 
10035 
10036 /*
10037  *
10038  *
10039  *   3         2         1
10040  *  10987654321098765432109876543210
10041  *  001000               x1010010101
10042  *     rt -----
10043  *          rs -----
10044  *               rd -----
10045  */
10046 static char *MODU(uint64 instruction, Dis_info *info)
10047 {
10048     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10049     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10050     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10051 
10052     const char *rd = GPR(rd_value, info);
10053     const char *rs = GPR(rs_value, info);
10054     const char *rt = GPR(rt_value, info);
10055 
10056     return img_format("MODU %s, %s, %s", rd, rs, rt);
10057 }
10058 
10059 
10060 /*
10061  *
10062  *
10063  *   3         2         1
10064  *  10987654321098765432109876543210
10065  *  001000               x1110000101
10066  *     rt -----
10067  *          rs -----
10068  *               rd -----
10069  */
10070 static char *MOV_D(uint64 instruction, Dis_info *info)
10071 {
10072     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10073     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10074 
10075     const char *ft = FPR(ft_value, info);
10076     const char *fs = FPR(fs_value, info);
10077 
10078     return img_format("MOV.D %s, %s", ft, fs);
10079 }
10080 
10081 
10082 /*
10083  *
10084  *
10085  *   3         2         1
10086  *  10987654321098765432109876543210
10087  *  001000               x1110000101
10088  *     rt -----
10089  *          rs -----
10090  *               rd -----
10091  */
10092 static char *MOV_S(uint64 instruction, Dis_info *info)
10093 {
10094     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10095     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10096 
10097     const char *ft = FPR(ft_value, info);
10098     const char *fs = FPR(fs_value, info);
10099 
10100     return img_format("MOV.S %s, %s", ft, fs);
10101 }
10102 
10103 
10104 /*
10105  *
10106  *
10107  *   3         2         1
10108  *  10987654321098765432109876543210
10109  *  001000               x1110000101
10110  *     rt -----
10111  *          rs -----
10112  *               rd -----
10113  */
10114 static char *MOVE_BALC(uint64 instruction, Dis_info *info)
10115 {
10116     uint64 rtz4_value = extract_rtz4_27_26_25_23_22_21(instruction);
10117     uint64 rd1_value = extract_rdl_25_24(instruction);
10118     int64 s_value = extract_s__se21_0_20_to_1_s1(instruction);
10119 
10120     const char *rd1 = GPR(decode_gpr_gpr1(rd1_value, info), info);
10121     const char *rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value, info), info);
10122     g_autofree char *s = ADDRESS(s_value, 4, info);
10123 
10124     return img_format("MOVE.BALC %s, %s, %s", rd1, rtz4, s);
10125 }
10126 
10127 
10128 /*
10129  *
10130  *
10131  *   3         2         1
10132  *  10987654321098765432109876543210
10133  *  001000               x1110000101
10134  *     rt -----
10135  *          rs -----
10136  *               rd -----
10137  */
10138 static char *MOVEP(uint64 instruction, Dis_info *info)
10139 {
10140     uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction);
10141     uint64 rd2_value = extract_rd2_3_8(instruction);
10142     uint64 rsz4_value = extract_rsz4_4_2_1_0(instruction);
10143 
10144     const char *rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value, info), info);
10145     const char *re2 = GPR(decode_gpr_gpr2_reg2(rd2_value, info), info);
10146     /* !!!!!!!!!! - no conversion function */
10147     const char *rsz4 = GPR(decode_gpr_gpr4_zero(rsz4_value, info), info);
10148     const char *rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value, info), info);
10149 
10150     return img_format("MOVEP %s, %s, %s, %s", rd2, re2, rsz4, rtz4);
10151     /* hand edited */
10152 }
10153 
10154 
10155 /*
10156  *
10157  *
10158  *   3         2         1
10159  *  10987654321098765432109876543210
10160  *  001000               x1110000101
10161  *     rt -----
10162  *          rs -----
10163  *               rd -----
10164  */
10165 static char *MOVEP_REV_(uint64 instruction, Dis_info *info)
10166 {
10167     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
10168     uint64 rd2_value = extract_rd2_3_8(instruction);
10169     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
10170 
10171     const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info);
10172     const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info);
10173     const char *rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value, info), info);
10174     const char *rs2 = GPR(decode_gpr_gpr2_reg2(rd2_value, info), info);
10175     /* !!!!!!!!!! - no conversion function */
10176 
10177     return img_format("MOVEP %s, %s, %s, %s", rs4, rt4, rd2, rs2);
10178     /* hand edited */
10179 }
10180 
10181 
10182 /*
10183  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10184  *
10185  *   3         2         1
10186  *  10987654321098765432109876543210
10187  *  001000               00010001101
10188  *     rt -----
10189  *          rs -----
10190  *               rd -----
10191  */
10192 static char *MOVE(uint64 instruction, Dis_info *info)
10193 {
10194     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
10195     uint64 rs_value = extract_rs_4_3_2_1_0(instruction);
10196 
10197     const char *rt = GPR(rt_value, info);
10198     const char *rs = GPR(rs_value, info);
10199 
10200     return img_format("MOVE %s, %s", rt, rs);
10201 }
10202 
10203 
10204 /*
10205  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10206  *
10207  *   3         2         1
10208  *  10987654321098765432109876543210
10209  *  001000               00010001101
10210  *     rt -----
10211  *          rs -----
10212  *               rd -----
10213  */
10214 static char *MOVN(uint64 instruction, Dis_info *info)
10215 {
10216     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10217     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10218     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10219 
10220     const char *rd = GPR(rd_value, info);
10221     const char *rs = GPR(rs_value, info);
10222     const char *rt = GPR(rt_value, info);
10223 
10224     return img_format("MOVN %s, %s, %s", rd, rs, rt);
10225 }
10226 
10227 
10228 /*
10229  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10230  *
10231  *   3         2         1
10232  *  10987654321098765432109876543210
10233  *  001000               00010001101
10234  *     rt -----
10235  *          rs -----
10236  *               rd -----
10237  */
10238 static char *MOVZ(uint64 instruction, Dis_info *info)
10239 {
10240     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10241     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10242     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10243 
10244     const char *rd = GPR(rd_value, info);
10245     const char *rs = GPR(rs_value, info);
10246     const char *rt = GPR(rt_value, info);
10247 
10248     return img_format("MOVZ %s, %s, %s", rd, rs, rt);
10249 }
10250 
10251 
10252 /*
10253  * [DSP] MSUB ac, rs, rt - Multiply word and subtract from accumulator
10254  *
10255  *   3         2         1
10256  *  10987654321098765432109876543210
10257  *  001000            10101010111111
10258  *     rt -----
10259  *          rs -----
10260  *               ac --
10261  */
10262 static char *MSUB_DSP_(uint64 instruction, Dis_info *info)
10263 {
10264     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10265     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10266     uint64 ac_value = extract_ac_15_14(instruction);
10267 
10268     const char *ac = AC(ac_value, info);
10269     const char *rs = GPR(rs_value, info);
10270     const char *rt = GPR(rt_value, info);
10271 
10272     return img_format("MSUB %s, %s, %s", ac, rs, rt);
10273 }
10274 
10275 
10276 /*
10277  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10278  *
10279  *   3         2         1
10280  *  10987654321098765432109876543210
10281  *  001000               00010001101
10282  *     rt -----
10283  *          rs -----
10284  *               rd -----
10285  */
10286 static char *MSUBF_D(uint64 instruction, Dis_info *info)
10287 {
10288     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10289     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10290     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10291 
10292     const char *fd = FPR(fd_value, info);
10293     const char *fs = FPR(fs_value, info);
10294     const char *ft = FPR(ft_value, info);
10295 
10296     return img_format("MSUBF.D %s, %s, %s", fd, fs, ft);
10297 }
10298 
10299 
10300 /*
10301  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10302  *
10303  *   3         2         1
10304  *  10987654321098765432109876543210
10305  *  001000               00010001101
10306  *     rt -----
10307  *          rs -----
10308  *               rd -----
10309  */
10310 static char *MSUBF_S(uint64 instruction, Dis_info *info)
10311 {
10312     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10313     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10314     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10315 
10316     const char *fd = FPR(fd_value, info);
10317     const char *fs = FPR(fs_value, info);
10318     const char *ft = FPR(ft_value, info);
10319 
10320     return img_format("MSUBF.S %s, %s, %s", fd, fs, ft);
10321 }
10322 
10323 
10324 /*
10325  * [DSP] MSUBU ac, rs, rt - Multiply word and add to accumulator
10326  *
10327  *   3         2         1
10328  *  10987654321098765432109876543210
10329  *  001000            11101010111111
10330  *     rt -----
10331  *          rs -----
10332  *               ac --
10333  */
10334 static char *MSUBU_DSP_(uint64 instruction, Dis_info *info)
10335 {
10336     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10337     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10338     uint64 ac_value = extract_ac_15_14(instruction);
10339 
10340     const char *ac = AC(ac_value, info);
10341     const char *rs = GPR(rs_value, info);
10342     const char *rt = GPR(rt_value, info);
10343 
10344     return img_format("MSUBU %s, %s, %s", ac, rs, rt);
10345 }
10346 
10347 
10348 /*
10349  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10350  *
10351  *   3         2         1
10352  *  10987654321098765432109876543210
10353  *  001000               00010001101
10354  *     rt -----
10355  *          rs -----
10356  *               rd -----
10357  */
10358 static char *MTC0(uint64 instruction, Dis_info *info)
10359 {
10360     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10361     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10362     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10363 
10364     const char *rt = GPR(rt_value, info);
10365 
10366     return img_format("MTC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
10367                       rt, c0s_value, sel_value);
10368 }
10369 
10370 
10371 /*
10372  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10373  *
10374  *   3         2         1
10375  *  10987654321098765432109876543210
10376  *  001000               00010001101
10377  *     rt -----
10378  *          rs -----
10379  *               rd -----
10380  */
10381 static char *MTC1(uint64 instruction, Dis_info *info)
10382 {
10383     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10384     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10385 
10386     const char *rt = GPR(rt_value, info);
10387     const char *fs = FPR(fs_value, info);
10388 
10389     return img_format("MTC1 %s, %s", rt, fs);
10390 }
10391 
10392 
10393 /*
10394  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10395  *
10396  *   3         2         1
10397  *  10987654321098765432109876543210
10398  *  001000               00010001101
10399  *     rt -----
10400  *          rs -----
10401  *               rd -----
10402  */
10403 static char *MTC2(uint64 instruction, Dis_info *info)
10404 {
10405     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10406     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10407 
10408     const char *rt = GPR(rt_value, info);
10409 
10410     return img_format("MTC2 %s, CP%" PRIu64, rt, cs_value);
10411 }
10412 
10413 
10414 /*
10415  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10416  *
10417  *   3         2         1
10418  *  10987654321098765432109876543210
10419  *  001000               00010001101
10420  *     rt -----
10421  *          rs -----
10422  *               rd -----
10423  */
10424 static char *MTGC0(uint64 instruction, Dis_info *info)
10425 {
10426     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10427     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10428     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10429 
10430     const char *rt = GPR(rt_value, info);
10431 
10432     return img_format("MTGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
10433                       rt, c0s_value, sel_value);
10434 }
10435 
10436 
10437 /*
10438  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10439  *
10440  *   3         2         1
10441  *  10987654321098765432109876543210
10442  *  001000               00010001101
10443  *     rt -----
10444  *          rs -----
10445  *               rd -----
10446  */
10447 static char *MTHC0(uint64 instruction, Dis_info *info)
10448 {
10449     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10450     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10451     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10452 
10453     const char *rt = GPR(rt_value, info);
10454 
10455     return img_format("MTHC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
10456                       rt, c0s_value, sel_value);
10457 }
10458 
10459 
10460 /*
10461  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10462  *
10463  *   3         2         1
10464  *  10987654321098765432109876543210
10465  *  001000               00010001101
10466  *     rt -----
10467  *          rs -----
10468  *               rd -----
10469  */
10470 static char *MTHC1(uint64 instruction, Dis_info *info)
10471 {
10472     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10473     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10474 
10475     const char *rt = GPR(rt_value, info);
10476     const char *fs = FPR(fs_value, info);
10477 
10478     return img_format("MTHC1 %s, %s", rt, fs);
10479 }
10480 
10481 
10482 /*
10483  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10484  *
10485  *   3         2         1
10486  *  10987654321098765432109876543210
10487  *  001000               00010001101
10488  *     rt -----
10489  *          rs -----
10490  *               rd -----
10491  */
10492 static char *MTHC2(uint64 instruction, Dis_info *info)
10493 {
10494     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10495     uint64 cs_value = extract_cs_20_19_18_17_16(instruction);
10496 
10497     const char *rt = GPR(rt_value, info);
10498 
10499     return img_format("MTHC2 %s, CP%" PRIu64, rt, cs_value);
10500 }
10501 
10502 
10503 /*
10504  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10505  *
10506  *   3         2         1
10507  *  10987654321098765432109876543210
10508  *  001000               00010001101
10509  *     rt -----
10510  *          rs -----
10511  *               rd -----
10512  */
10513 static char *MTHGC0(uint64 instruction, Dis_info *info)
10514 {
10515     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10516     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10517     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10518 
10519     const char *rt = GPR(rt_value, info);
10520 
10521     return img_format("MTHGC0 %s, CP%" PRIu64 ", 0x%" PRIx64,
10522                       rt, c0s_value, sel_value);
10523 }
10524 
10525 
10526 /*
10527  * [DSP] MTHI rs, ac - Move to HI register
10528  *
10529  *   3         2         1
10530  *  10987654321098765432109876543210
10531  *  001000xxxxx       10000001111111
10532  *          rs -----
10533  *               ac --
10534  */
10535 static char *MTHI_DSP_(uint64 instruction, Dis_info *info)
10536 {
10537     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10538     uint64 ac_value = extract_ac_15_14(instruction);
10539 
10540     const char *rs = GPR(rs_value, info);
10541     const char *ac = AC(ac_value, info);
10542 
10543     return img_format("MTHI %s, %s", rs, ac);
10544 }
10545 
10546 
10547 /*
10548  * [DSP] MTHLIP rs, ac - Copy LO to HI and a GPR to LO and increment pos by 32
10549  *
10550  *   3         2         1
10551  *  10987654321098765432109876543210
10552  *  001000xxxxx       00001001111111
10553  *          rs -----
10554  *               ac --
10555  */
10556 static char *MTHLIP(uint64 instruction, Dis_info *info)
10557 {
10558     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10559     uint64 ac_value = extract_ac_15_14(instruction);
10560 
10561     const char *rs = GPR(rs_value, info);
10562     const char *ac = AC(ac_value, info);
10563 
10564     return img_format("MTHLIP %s, %s", rs, ac);
10565 }
10566 
10567 
10568 /*
10569  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10570  *
10571  *   3         2         1
10572  *  10987654321098765432109876543210
10573  *  001000               00010001101
10574  *     rt -----
10575  *          rs -----
10576  *               rd -----
10577  */
10578 static char *MTHTR(uint64 instruction, Dis_info *info)
10579 {
10580     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10581     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10582     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10583     uint64 u_value = extract_u_10(instruction);
10584 
10585     const char *rt = GPR(rt_value, info);
10586 
10587     return img_format("MTHTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64,
10588                       rt, c0s_value, u_value, sel_value);
10589 }
10590 
10591 
10592 /*
10593  * [DSP] MTLO rs, ac - Move to LO register
10594  *
10595  *   3         2         1
10596  *  10987654321098765432109876543210
10597  *  001000xxxxx       11000001111111
10598  *          rs -----
10599  *               ac --
10600  */
10601 static char *MTLO_DSP_(uint64 instruction, Dis_info *info)
10602 {
10603     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10604     uint64 ac_value = extract_ac_15_14(instruction);
10605 
10606     const char *rs = GPR(rs_value, info);
10607     const char *ac = AC(ac_value, info);
10608 
10609     return img_format("MTLO %s, %s", rs, ac);
10610 }
10611 
10612 
10613 /*
10614  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10615  *
10616  *   3         2         1
10617  *  10987654321098765432109876543210
10618  *  001000               00010001101
10619  *     rt -----
10620  *          rs -----
10621  *               rd -----
10622  */
10623 static char *MTTR(uint64 instruction, Dis_info *info)
10624 {
10625     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10626     uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction);
10627     uint64 sel_value = extract_sel_15_14_13_12_11(instruction);
10628     uint64 u_value = extract_u_10(instruction);
10629 
10630     const char *rt = GPR(rt_value, info);
10631 
10632     return img_format("MTTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64,
10633                       rt, c0s_value, u_value, sel_value);
10634 }
10635 
10636 
10637 /*
10638  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10639  *
10640  *   3         2         1
10641  *  10987654321098765432109876543210
10642  *  001000               00010001101
10643  *     rt -----
10644  *          rs -----
10645  *               rd -----
10646  */
10647 static char *MUH(uint64 instruction, Dis_info *info)
10648 {
10649     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10650     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10651     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10652 
10653     const char *rd = GPR(rd_value, info);
10654     const char *rs = GPR(rs_value, info);
10655     const char *rt = GPR(rt_value, info);
10656 
10657     return img_format("MUH %s, %s, %s", rd, rs, rt);
10658 }
10659 
10660 
10661 /*
10662  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10663  *
10664  *   3         2         1
10665  *  10987654321098765432109876543210
10666  *  001000               00010001101
10667  *     rt -----
10668  *          rs -----
10669  *               rd -----
10670  */
10671 static char *MUHU(uint64 instruction, Dis_info *info)
10672 {
10673     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10674     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10675     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10676 
10677     const char *rd = GPR(rd_value, info);
10678     const char *rs = GPR(rs_value, info);
10679     const char *rt = GPR(rt_value, info);
10680 
10681     return img_format("MUHU %s, %s, %s", rd, rs, rt);
10682 }
10683 
10684 
10685 /*
10686  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10687  *
10688  *   3         2         1
10689  *  10987654321098765432109876543210
10690  *  001000               00010001101
10691  *     rt -----
10692  *          rs -----
10693  *               rd -----
10694  */
10695 static char *MUL_32_(uint64 instruction, Dis_info *info)
10696 {
10697     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10698     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10699     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10700 
10701     const char *rd = GPR(rd_value, info);
10702     const char *rs = GPR(rs_value, info);
10703     const char *rt = GPR(rt_value, info);
10704 
10705     return img_format("MUL %s, %s, %s", rd, rs, rt);
10706 }
10707 
10708 
10709 /*
10710  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10711  *
10712  *   3         2         1
10713  *  10987654321098765432109876543210
10714  *  001000               00010001101
10715  *     rt -----
10716  *          rs -----
10717  *               rd -----
10718  */
10719 static char *MUL_4X4_(uint64 instruction, Dis_info *info)
10720 {
10721     uint64 rt4_value = extract_rt4_9_7_6_5(instruction);
10722     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
10723 
10724     const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info);
10725     const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info);
10726 
10727     return img_format("MUL %s, %s", rs4, rt4);
10728 }
10729 
10730 
10731 /*
10732  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10733  *
10734  *   3         2         1
10735  *  10987654321098765432109876543210
10736  *  001000               00010001101
10737  *     rt -----
10738  *          rs -----
10739  *               rd -----
10740  */
10741 static char *MUL_D(uint64 instruction, Dis_info *info)
10742 {
10743     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10744     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10745     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10746 
10747     const char *fd = FPR(fd_value, info);
10748     const char *fs = FPR(fs_value, info);
10749     const char *ft = FPR(ft_value, info);
10750 
10751     return img_format("MUL.D %s, %s, %s", fd, fs, ft);
10752 }
10753 
10754 
10755 /*
10756  * [DSP] MUL.PH rd, rs, rt - Multiply vector integer half words to same size
10757  *   products
10758  *
10759  *   3         2         1
10760  *  10987654321098765432109876543210
10761  *  001000               00000101101
10762  *     rt -----
10763  *          rs -----
10764  *               rd -----
10765  */
10766 static char *MUL_PH(uint64 instruction, Dis_info *info)
10767 {
10768     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10769     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10770     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10771 
10772     const char *rd = GPR(rd_value, info);
10773     const char *rs = GPR(rs_value, info);
10774     const char *rt = GPR(rt_value, info);
10775 
10776     return img_format("MUL.PH %s, %s, %s", rd, rs, rt);
10777 }
10778 
10779 
10780 /*
10781  * [DSP] MUL_S.PH rd, rs, rt - Multiply vector integer half words to same size
10782  *   products (saturated)
10783  *
10784  *   3         2         1
10785  *  10987654321098765432109876543210
10786  *  001000               10000101101
10787  *     rt -----
10788  *          rs -----
10789  *               rd -----
10790  */
10791 static char *MUL_S_PH(uint64 instruction, Dis_info *info)
10792 {
10793     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10794     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10795     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10796 
10797     const char *rd = GPR(rd_value, info);
10798     const char *rs = GPR(rs_value, info);
10799     const char *rt = GPR(rt_value, info);
10800 
10801     return img_format("MUL_S.PH %s, %s, %s", rd, rs, rt);
10802 }
10803 
10804 
10805 /*
10806  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
10807  *
10808  *   3         2         1
10809  *  10987654321098765432109876543210
10810  *  001000               00010001101
10811  *     rt -----
10812  *          rs -----
10813  *               rd -----
10814  */
10815 static char *MUL_S(uint64 instruction, Dis_info *info)
10816 {
10817     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
10818     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
10819     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
10820 
10821     const char *fd = FPR(fd_value, info);
10822     const char *fs = FPR(fs_value, info);
10823     const char *ft = FPR(ft_value, info);
10824 
10825     return img_format("MUL.S %s, %s, %s", fd, fs, ft);
10826 }
10827 
10828 
10829 /*
10830  * [DSP] MULEQ_S.W.PHL rd, rs, rt - Multiply vector fractional left halfwords
10831  *   to expanded width products
10832  *
10833  *   3         2         1
10834  *  10987654321098765432109876543210
10835  *  001000               x0000100101
10836  *     rt -----
10837  *          rs -----
10838  *               rd -----
10839  */
10840 static char *MULEQ_S_W_PHL(uint64 instruction, Dis_info *info)
10841 {
10842     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10843     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10844     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10845 
10846     const char *rd = GPR(rd_value, info);
10847     const char *rs = GPR(rs_value, info);
10848     const char *rt = GPR(rt_value, info);
10849 
10850     return img_format("MULEQ_S.W.PHL %s, %s, %s", rd, rs, rt);
10851 }
10852 
10853 
10854 /*
10855  * [DSP] MULEQ_S.W.PHR rd, rs, rt - Multiply vector fractional right halfwords
10856  *   to expanded width products
10857  *
10858  *   3         2         1
10859  *  10987654321098765432109876543210
10860  *  001000               x0001100101
10861  *     rt -----
10862  *          rs -----
10863  *               rd -----
10864  */
10865 static char *MULEQ_S_W_PHR(uint64 instruction, Dis_info *info)
10866 {
10867     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10868     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10869     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10870 
10871     const char *rd = GPR(rd_value, info);
10872     const char *rs = GPR(rs_value, info);
10873     const char *rt = GPR(rt_value, info);
10874 
10875     return img_format("MULEQ_S.W.PHR %s, %s, %s", rd, rs, rt);
10876 }
10877 
10878 
10879 /*
10880  * [DSP] MULEU_S.PH.QBL rd, rs, rt - Multiply vector fractional left bytes
10881  *   by halfwords to halfword products
10882  *
10883  *   3         2         1
10884  *  10987654321098765432109876543210
10885  *  001000               x0010010101
10886  *     rt -----
10887  *          rs -----
10888  *               rd -----
10889  */
10890 static char *MULEU_S_PH_QBL(uint64 instruction, Dis_info *info)
10891 {
10892     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10893     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10894     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10895 
10896     const char *rd = GPR(rd_value, info);
10897     const char *rs = GPR(rs_value, info);
10898     const char *rt = GPR(rt_value, info);
10899 
10900     return img_format("MULEU_S.PH.QBL %s, %s, %s", rd, rs, rt);
10901 }
10902 
10903 
10904 /*
10905  * [DSP] MULEU_S.PH.QBR rd, rs, rt - Multiply vector fractional right bytes
10906  *   by halfwords to halfword products
10907  *
10908  *   3         2         1
10909  *  10987654321098765432109876543210
10910  *  001000               x0011010101
10911  *     rt -----
10912  *          rs -----
10913  *               rd -----
10914  */
10915 static char *MULEU_S_PH_QBR(uint64 instruction, Dis_info *info)
10916 {
10917     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10918     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10919     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10920 
10921     const char *rd = GPR(rd_value, info);
10922     const char *rs = GPR(rs_value, info);
10923     const char *rt = GPR(rt_value, info);
10924 
10925     return img_format("MULEU_S.PH.QBR %s, %s, %s", rd, rs, rt);
10926 }
10927 
10928 
10929 /*
10930  * [DSP] MULQ_RS.PH rd, rs, rt - Multiply vector fractional halfwords
10931  *   to fractional halfword products
10932  *
10933  *   3         2         1
10934  *  10987654321098765432109876543210
10935  *  001000               x0100010101
10936  *     rt -----
10937  *          rs -----
10938  *               rd -----
10939  */
10940 static char *MULQ_RS_PH(uint64 instruction, Dis_info *info)
10941 {
10942     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10943     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10944     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10945 
10946     const char *rd = GPR(rd_value, info);
10947     const char *rs = GPR(rs_value, info);
10948     const char *rt = GPR(rt_value, info);
10949 
10950     return img_format("MULQ_RS.PH %s, %s, %s", rd, rs, rt);
10951 }
10952 
10953 
10954 /*
10955  * [DSP] MULQ_RS.W rd, rs, rt - Multiply fractional words to same size
10956  *   product with saturation and rounding
10957  *
10958  *   3         2         1
10959  *  10987654321098765432109876543210
10960  *  001000               x0110010101
10961  *     rt -----
10962  *          rs -----
10963  *               rd -----
10964  */
10965 static char *MULQ_RS_W(uint64 instruction, Dis_info *info)
10966 {
10967     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10968     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10969     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10970 
10971     const char *rd = GPR(rd_value, info);
10972     const char *rs = GPR(rs_value, info);
10973     const char *rt = GPR(rt_value, info);
10974 
10975     return img_format("MULQ_RS.W %s, %s, %s", rd, rs, rt);
10976 }
10977 
10978 
10979 /*
10980  * [DSP] MULQ_S.PH rd, rs, rt - Multiply fractional halfwords to same size
10981  *   products
10982  *
10983  *   3         2         1
10984  *  10987654321098765432109876543210
10985  *  001000               x0101010101
10986  *     rt -----
10987  *          rs -----
10988  *               rd -----
10989  */
10990 static char *MULQ_S_PH(uint64 instruction, Dis_info *info)
10991 {
10992     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
10993     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
10994     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
10995 
10996     const char *rd = GPR(rd_value, info);
10997     const char *rs = GPR(rs_value, info);
10998     const char *rt = GPR(rt_value, info);
10999 
11000     return img_format("MULQ_S.PH %s, %s, %s", rd, rs, rt);
11001 }
11002 
11003 
11004 /*
11005  * [DSP] MULQ_S.W rd, rs, rt - Multiply fractional words to same size product
11006  *   with saturation
11007  *
11008  *   3         2         1
11009  *  10987654321098765432109876543210
11010  *  001000               x0111010101
11011  *     rt -----
11012  *          rs -----
11013  *               rd -----
11014  */
11015 static char *MULQ_S_W(uint64 instruction, Dis_info *info)
11016 {
11017     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11018     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11019     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11020 
11021     const char *rd = GPR(rd_value, info);
11022     const char *rs = GPR(rs_value, info);
11023     const char *rt = GPR(rt_value, info);
11024 
11025     return img_format("MULQ_S.W %s, %s, %s", rd, rs, rt);
11026 }
11027 
11028 
11029 /*
11030  * [DSP] MULSA.W.PH ac, rs, rt - Multiply and subtract vector integer halfword
11031  *   elements and accumulate
11032  *
11033  *   3         2         1
11034  *  10987654321098765432109876543210
11035  *  001000            10110010111111
11036  *     rt -----
11037  *          rs -----
11038  *               ac --
11039  */
11040 static char *MULSA_W_PH(uint64 instruction, Dis_info *info)
11041 {
11042     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11043     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11044     uint64 ac_value = extract_ac_15_14(instruction);
11045 
11046     const char *ac = AC(ac_value, info);
11047     const char *rs = GPR(rs_value, info);
11048     const char *rt = GPR(rt_value, info);
11049 
11050     return img_format("MULSA.W.PH %s, %s, %s", ac, rs, rt);
11051 }
11052 
11053 
11054 /*
11055  * [DSP] MULSAQ_S.W.PH ac, rs, rt - Multiply and subtract vector fractional
11056  *   halfwords and accumulate
11057  *
11058  *   3         2         1
11059  *  10987654321098765432109876543210
11060  *  001000            11110010111111
11061  *     rt -----
11062  *          rs -----
11063  *               ac --
11064  */
11065 static char *MULSAQ_S_W_PH(uint64 instruction, Dis_info *info)
11066 {
11067     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11068     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11069     uint64 ac_value = extract_ac_15_14(instruction);
11070 
11071     const char *ac = AC(ac_value, info);
11072     const char *rs = GPR(rs_value, info);
11073     const char *rt = GPR(rt_value, info);
11074 
11075     return img_format("MULSAQ_S.W.PH %s, %s, %s", ac, rs, rt);
11076 }
11077 
11078 
11079 /*
11080  * [DSP] MULT ac, rs, rt - Multiply word
11081  *
11082  *   3         2         1
11083  *  10987654321098765432109876543210
11084  *  001000            00110010111111
11085  *     rt -----
11086  *          rs -----
11087  *               ac --
11088  */
11089 static char *MULT_DSP_(uint64 instruction, Dis_info *info)
11090 {
11091     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11092     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11093     uint64 ac_value = extract_ac_15_14(instruction);
11094 
11095     const char *ac = AC(ac_value, info);
11096     const char *rs = GPR(rs_value, info);
11097     const char *rt = GPR(rt_value, info);
11098 
11099     return img_format("MULT %s, %s, %s", ac, rs, rt);
11100 }
11101 
11102 
11103 /*
11104  * [DSP] MULTU ac, rs, rt - Multiply unsigned word
11105  *
11106  *   3         2         1
11107  *  10987654321098765432109876543210
11108  *  001000            01110010111111
11109  *     rt -----
11110  *          rs -----
11111  *               ac --
11112  */
11113 static char *MULTU_DSP_(uint64 instruction, Dis_info *info)
11114 {
11115     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11116     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11117     uint64 ac_value = extract_ac_15_14(instruction);
11118 
11119     const char *ac = AC(ac_value, info);
11120     const char *rs = GPR(rs_value, info);
11121     const char *rt = GPR(rt_value, info);
11122 
11123     return img_format("MULTU %s, %s, %s", ac, rs, rt);
11124 }
11125 
11126 
11127 /*
11128  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11129  *
11130  *   3         2         1
11131  *  10987654321098765432109876543210
11132  *  001000               00010001101
11133  *     rt -----
11134  *          rs -----
11135  *               rd -----
11136  */
11137 static char *MULU(uint64 instruction, Dis_info *info)
11138 {
11139     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11140     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11141     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11142 
11143     const char *rd = GPR(rd_value, info);
11144     const char *rs = GPR(rs_value, info);
11145     const char *rt = GPR(rt_value, info);
11146 
11147     return img_format("MULU %s, %s, %s", rd, rs, rt);
11148 }
11149 
11150 
11151 /*
11152  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11153  *
11154  *   3         2         1
11155  *  10987654321098765432109876543210
11156  *  001000               00010001101
11157  *     rt -----
11158  *          rs -----
11159  *               rd -----
11160  */
11161 static char *NEG_D(uint64 instruction, Dis_info *info)
11162 {
11163     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11164     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11165 
11166     const char *ft = FPR(ft_value, info);
11167     const char *fs = FPR(fs_value, info);
11168 
11169     return img_format("NEG.D %s, %s", ft, fs);
11170 }
11171 
11172 
11173 /*
11174  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11175  *
11176  *   3         2         1
11177  *  10987654321098765432109876543210
11178  *  001000               00010001101
11179  *     rt -----
11180  *          rs -----
11181  *               rd -----
11182  */
11183 static char *NEG_S(uint64 instruction, Dis_info *info)
11184 {
11185     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
11186     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
11187 
11188     const char *ft = FPR(ft_value, info);
11189     const char *fs = FPR(fs_value, info);
11190 
11191     return img_format("NEG.S %s, %s", ft, fs);
11192 }
11193 
11194 
11195 /*
11196  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11197  *
11198  *   3         2         1
11199  *  10987654321098765432109876543210
11200  *  001000               00010001101
11201  *     rt -----
11202  *          rs -----
11203  *               rd -----
11204  */
11205 static char *NOP_16_(uint64 instruction, Dis_info *info)
11206 {
11207     (void)instruction;
11208 
11209     return g_strdup("NOP ");
11210 }
11211 
11212 
11213 /*
11214  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11215  *
11216  *   3         2         1
11217  *  10987654321098765432109876543210
11218  *  001000               00010001101
11219  *     rt -----
11220  *          rs -----
11221  *               rd -----
11222  */
11223 static char *NOP_32_(uint64 instruction, Dis_info *info)
11224 {
11225     (void)instruction;
11226 
11227     return g_strdup("NOP ");
11228 }
11229 
11230 
11231 /*
11232  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11233  *
11234  *   3         2         1
11235  *  10987654321098765432109876543210
11236  *  001000               00010001101
11237  *     rt -----
11238  *          rs -----
11239  *               rd -----
11240  */
11241 static char *NOR(uint64 instruction, Dis_info *info)
11242 {
11243     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11244     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11245     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11246 
11247     const char *rd = GPR(rd_value, info);
11248     const char *rs = GPR(rs_value, info);
11249     const char *rt = GPR(rt_value, info);
11250 
11251     return img_format("NOR %s, %s, %s", rd, rs, rt);
11252 }
11253 
11254 
11255 /*
11256  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11257  *
11258  *   3         2         1
11259  *  10987654321098765432109876543210
11260  *  001000               00010001101
11261  *     rt -----
11262  *          rs -----
11263  *               rd -----
11264  */
11265 static char *NOT_16_(uint64 instruction, Dis_info *info)
11266 {
11267     uint64 rt3_value = extract_rt3_9_8_7(instruction);
11268     uint64 rs3_value = extract_rs3_6_5_4(instruction);
11269 
11270     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
11271     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
11272 
11273     return img_format("NOT %s, %s", rt3, rs3);
11274 }
11275 
11276 
11277 /*
11278  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11279  *
11280  *   3         2         1
11281  *  10987654321098765432109876543210
11282  *  001000               00010001101
11283  *     rt -----
11284  *          rs -----
11285  *               rd -----
11286  */
11287 static char *OR_16_(uint64 instruction, Dis_info *info)
11288 {
11289     uint64 rt3_value = extract_rt3_9_8_7(instruction);
11290     uint64 rs3_value = extract_rs3_6_5_4(instruction);
11291 
11292     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
11293     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
11294 
11295     return img_format("OR %s, %s", rs3, rt3);
11296 }
11297 
11298 
11299 /*
11300  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11301  *
11302  *   3         2         1
11303  *  10987654321098765432109876543210
11304  *  001000               00010001101
11305  *     rt -----
11306  *          rs -----
11307  *               rd -----
11308  */
11309 static char *OR_32_(uint64 instruction, Dis_info *info)
11310 {
11311     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11312     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11313     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11314 
11315     const char *rd = GPR(rd_value, info);
11316     const char *rs = GPR(rs_value, info);
11317     const char *rt = GPR(rt_value, info);
11318 
11319     return img_format("OR %s, %s, %s", rd, rs, rt);
11320 }
11321 
11322 
11323 /*
11324  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11325  *
11326  *   3         2         1
11327  *  10987654321098765432109876543210
11328  *  001000               00010001101
11329  *     rt -----
11330  *          rs -----
11331  *               rd -----
11332  */
11333 static char *ORI(uint64 instruction, Dis_info *info)
11334 {
11335     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11336     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11337     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
11338 
11339     const char *rt = GPR(rt_value, info);
11340     const char *rs = GPR(rs_value, info);
11341 
11342     return img_format("ORI %s, %s, 0x%" PRIx64, rt, rs, u_value);
11343 }
11344 
11345 
11346 /*
11347  * [DSP] PACKRL.PH rd, rs, rt - Pack a word using the right halfword from one
11348  *         source register and left halfword from another source register
11349  *
11350  *   3         2         1
11351  *  10987654321098765432109876543210
11352  *  001000               00010001101
11353  *     rt -----
11354  *          rs -----
11355  *               rd -----
11356  */
11357 static char *PACKRL_PH(uint64 instruction, Dis_info *info)
11358 {
11359     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11360     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11361     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11362 
11363     const char *rd = GPR(rd_value, info);
11364     const char *rs = GPR(rs_value, info);
11365     const char *rt = GPR(rt_value, info);
11366 
11367     return img_format("PACKRL.PH %s, %s, %s", rd, rs, rt);
11368 }
11369 
11370 
11371 /*
11372  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
11373  *
11374  *   3         2         1
11375  *  10987654321098765432109876543210
11376  *  001000               00010001101
11377  *     rt -----
11378  *          rs -----
11379  *               rd -----
11380  */
11381 static char *PAUSE(uint64 instruction, Dis_info *info)
11382 {
11383     (void)instruction;
11384 
11385     return g_strdup("PAUSE ");
11386 }
11387 
11388 
11389 /*
11390  * [DSP] PICK.PH rd, rs, rt - Pick a vector of halfwords based on condition
11391  *         code bits
11392  *
11393  *   3         2         1
11394  *  10987654321098765432109876543210
11395  *  001000               00010001101
11396  *     rt -----
11397  *          rs -----
11398  *               rd -----
11399  */
11400 static char *PICK_PH(uint64 instruction, Dis_info *info)
11401 {
11402     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11403     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11404     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11405 
11406     const char *rd = GPR(rd_value, info);
11407     const char *rs = GPR(rs_value, info);
11408     const char *rt = GPR(rt_value, info);
11409 
11410     return img_format("PICK.PH %s, %s, %s", rd, rs, rt);
11411 }
11412 
11413 
11414 /*
11415  * [DSP] PICK.QB rd, rs, rt - Pick a vector of byte values based on condition
11416  *         code bits
11417  *
11418  *   3         2         1
11419  *  10987654321098765432109876543210
11420  *  001000               00010001101
11421  *     rt -----
11422  *          rs -----
11423  *               rd -----
11424  */
11425 static char *PICK_QB(uint64 instruction, Dis_info *info)
11426 {
11427     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11428     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11429     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11430 
11431     const char *rd = GPR(rd_value, info);
11432     const char *rs = GPR(rs_value, info);
11433     const char *rt = GPR(rt_value, info);
11434 
11435     return img_format("PICK.QB %s, %s, %s", rd, rs, rt);
11436 }
11437 
11438 
11439 /*
11440  * [DSP] PRECEQ.W.PHL rt, rs - Expand the precision of the left-most element
11441  *         of a paired halfword
11442  *
11443  *   3         2         1
11444  *  10987654321098765432109876543210
11445  *  001000               00010001101
11446  *     rt -----
11447  *          rs -----
11448  *               rd -----
11449  */
11450 static char *PRECEQ_W_PHL(uint64 instruction, Dis_info *info)
11451 {
11452     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11453     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11454 
11455     const char *rt = GPR(rt_value, info);
11456     const char *rs = GPR(rs_value, info);
11457 
11458     return img_format("PRECEQ.W.PHL %s, %s", rt, rs);
11459 }
11460 
11461 
11462 /*
11463  * [DSP] PRECEQ.W.PHR rt, rs - Expand the precision of the right-most element
11464  *         of a paired halfword
11465  *
11466  *   3         2         1
11467  *  10987654321098765432109876543210
11468  *  001000               00010001101
11469  *     rt -----
11470  *          rs -----
11471  *               rd -----
11472  */
11473 static char *PRECEQ_W_PHR(uint64 instruction, Dis_info *info)
11474 {
11475     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11476     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11477 
11478     const char *rt = GPR(rt_value, info);
11479     const char *rs = GPR(rs_value, info);
11480 
11481     return img_format("PRECEQ.W.PHR %s, %s", rt, rs);
11482 }
11483 
11484 
11485 /*
11486  * [DSP] PRECEQU.PH.QBLA rt, rs - Expand the precision of the two
11487  *         left-alternate elements of a quad byte vector
11488  *
11489  *   3         2         1
11490  *  10987654321098765432109876543210
11491  *  001000               00010001101
11492  *     rt -----
11493  *          rs -----
11494  *               rd -----
11495  */
11496 static char *PRECEQU_PH_QBLA(uint64 instruction, Dis_info *info)
11497 {
11498     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11499     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11500 
11501     const char *rt = GPR(rt_value, info);
11502     const char *rs = GPR(rs_value, info);
11503 
11504     return img_format("PRECEQU.PH.QBLA %s, %s", rt, rs);
11505 }
11506 
11507 
11508 /*
11509  * [DSP] PRECEQU.PH.QBL rt, rs - Expand the precision of the two left-most
11510  *         elements of a quad byte vector
11511  *
11512  *   3         2         1
11513  *  10987654321098765432109876543210
11514  *  001000               00010001101
11515  *     rt -----
11516  *          rs -----
11517  *               rd -----
11518  */
11519 static char *PRECEQU_PH_QBL(uint64 instruction, Dis_info *info)
11520 {
11521     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11522     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11523 
11524     const char *rt = GPR(rt_value, info);
11525     const char *rs = GPR(rs_value, info);
11526 
11527     return img_format("PRECEQU.PH.QBL %s, %s", rt, rs);
11528 }
11529 
11530 
11531 /*
11532  * [DSP] PRECEQU.PH.QBRA rt, rs - Expand the precision of the two
11533  *         right-alternate elements of a quad byte vector
11534  *
11535  *   3         2         1
11536  *  10987654321098765432109876543210
11537  *  001000               00010001101
11538  *     rt -----
11539  *          rs -----
11540  *               rd -----
11541  */
11542 static char *PRECEQU_PH_QBRA(uint64 instruction, Dis_info *info)
11543 {
11544     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11545     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11546 
11547     const char *rt = GPR(rt_value, info);
11548     const char *rs = GPR(rs_value, info);
11549 
11550     return img_format("PRECEQU.PH.QBRA %s, %s", rt, rs);
11551 }
11552 
11553 
11554 /*
11555  * [DSP] PRECEQU.PH.QBR rt, rs - Expand the precision of the two right-most
11556  *         elements of a quad byte vector
11557  *
11558  *   3         2         1
11559  *  10987654321098765432109876543210
11560  *  001000               00010001101
11561  *     rt -----
11562  *          rs -----
11563  *               rd -----
11564  */
11565 static char *PRECEQU_PH_QBR(uint64 instruction, Dis_info *info)
11566 {
11567     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11568     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11569 
11570     const char *rt = GPR(rt_value, info);
11571     const char *rs = GPR(rs_value, info);
11572 
11573     return img_format("PRECEQU.PH.QBR %s, %s", rt, rs);
11574 }
11575 
11576 
11577 /*
11578  * [DSP] PRECEU.PH.QBLA rt, rs - Expand the precision of the two
11579  *         left-alternate elements of a quad byte vector to four unsigned
11580  *         halfwords
11581  *
11582  *   3         2         1
11583  *  10987654321098765432109876543210
11584  *  001000               00010001101
11585  *     rt -----
11586  *          rs -----
11587  *               rd -----
11588  */
11589 static char *PRECEU_PH_QBLA(uint64 instruction, Dis_info *info)
11590 {
11591     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11592     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11593 
11594     const char *rt = GPR(rt_value, info);
11595     const char *rs = GPR(rs_value, info);
11596 
11597     return img_format("PRECEU.PH.QBLA %s, %s", rt, rs);
11598 }
11599 
11600 
11601 /*
11602  * [DSP] PRECEU.PH.QBL rt, rs - Expand the precision of the two left-most
11603  *         elements of a quad byte vector to form unsigned halfwords
11604  *
11605  *   3         2         1
11606  *  10987654321098765432109876543210
11607  *  001000               00010001101
11608  *     rt -----
11609  *          rs -----
11610  *               rd -----
11611  */
11612 static char *PRECEU_PH_QBL(uint64 instruction, Dis_info *info)
11613 {
11614     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11615     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11616 
11617     const char *rt = GPR(rt_value, info);
11618     const char *rs = GPR(rs_value, info);
11619 
11620     return img_format("PRECEU.PH.QBL %s, %s", rt, rs);
11621 }
11622 
11623 
11624 /*
11625  * [DSP] PRECEU.PH.QBRA rt, rs - Expand the precision of the two
11626  *         right-alternate elements of a quad byte vector to form four
11627  *         unsigned halfwords
11628  *
11629  *   3         2         1
11630  *  10987654321098765432109876543210
11631  *  001000               00010001101
11632  *     rt -----
11633  *          rs -----
11634  *               rd -----
11635  */
11636 static char *PRECEU_PH_QBRA(uint64 instruction, Dis_info *info)
11637 {
11638     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11639     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11640 
11641     const char *rt = GPR(rt_value, info);
11642     const char *rs = GPR(rs_value, info);
11643 
11644     return img_format("PRECEU.PH.QBRA %s, %s", rt, rs);
11645 }
11646 
11647 
11648 /*
11649  * [DSP] PRECEU.PH.QBR rt, rs - Expand the precision of the two right-most
11650  *         elements of a quad byte vector to form unsigned halfwords
11651  *
11652  *   3         2         1
11653  *  10987654321098765432109876543210
11654  *  001000               00010001101
11655  *     rt -----
11656  *          rs -----
11657  *               rd -----
11658  */
11659 static char *PRECEU_PH_QBR(uint64 instruction, Dis_info *info)
11660 {
11661     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11662     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11663 
11664     const char *rt = GPR(rt_value, info);
11665     const char *rs = GPR(rs_value, info);
11666 
11667     return img_format("PRECEU.PH.QBR %s, %s", rt, rs);
11668 }
11669 
11670 
11671 /*
11672  * [DSP] PRECR.QB.PH rd, rs, rt - Reduce the precision of four integer
11673  *   halfwords to four bytes
11674  *
11675  *   3         2         1
11676  *  10987654321098765432109876543210
11677  *  001000               x0001101101
11678  *     rt -----
11679  *          rs -----
11680  *               rd -----
11681  */
11682 static char *PRECR_QB_PH(uint64 instruction, Dis_info *info)
11683 {
11684     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11685     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11686     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11687 
11688     const char *rd = GPR(rd_value, info);
11689     const char *rs = GPR(rs_value, info);
11690     const char *rt = GPR(rt_value, info);
11691 
11692     return img_format("PRECR.QB.PH %s, %s, %s", rd, rs, rt);
11693 }
11694 
11695 
11696 /*
11697  * [DSP] PRECR_SRA.PH.W rt, rs, sa - Reduce the precision of two integer
11698  *   words to halfwords after a right shift
11699  *
11700  *   3         2         1
11701  *  10987654321098765432109876543210
11702  *  001000               x1110000101
11703  *     rt -----
11704  *          rs -----
11705  *               rd -----
11706  */
11707 static char *PRECR_SRA_PH_W(uint64 instruction, Dis_info *info)
11708 {
11709     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11710     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11711     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
11712 
11713     const char *rt = GPR(rt_value, info);
11714     const char *rs = GPR(rs_value, info);
11715 
11716     return img_format("PRECR_SRA.PH.W %s, %s, 0x%" PRIx64, rt, rs, sa_value);
11717 }
11718 
11719 
11720 /*
11721  * [DSP] PRECR_SRA_R.PH.W rt, rs, sa - Reduce the precision of two integer
11722  *   words to halfwords after a right shift with rounding
11723  *
11724  *   3         2         1
11725  *  10987654321098765432109876543210
11726  *  001000               x1110000101
11727  *     rt -----
11728  *          rs -----
11729  *               rd -----
11730  */
11731 static char *PRECR_SRA_R_PH_W(uint64 instruction, Dis_info *info)
11732 {
11733     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11734     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11735     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
11736 
11737     const char *rt = GPR(rt_value, info);
11738     const char *rs = GPR(rs_value, info);
11739 
11740     return img_format("PRECR_SRA_R.PH.W %s, %s, 0x%" PRIx64, rt, rs, sa_value);
11741 }
11742 
11743 
11744 /*
11745  * [DSP] PRECRQ.PH.W rd, rs, rt - Reduce the precision of fractional
11746  *   words to fractional halfwords
11747  *
11748  *   3         2         1
11749  *  10987654321098765432109876543210
11750  *  001000               x1110000101
11751  *     rt -----
11752  *          rs -----
11753  *               rd -----
11754  */
11755 static char *PRECRQ_PH_W(uint64 instruction, Dis_info *info)
11756 {
11757     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11758     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11759     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11760 
11761     const char *rd = GPR(rd_value, info);
11762     const char *rs = GPR(rs_value, info);
11763     const char *rt = GPR(rt_value, info);
11764 
11765     return img_format("PRECRQ.PH.W %s, %s, %s", rd, rs, rt);
11766 }
11767 
11768 
11769 /*
11770  * [DSP] PRECRQ.QB.PH rd, rs, rt - Reduce the precision of four fractional
11771  *   halfwords to four bytes
11772  *
11773  *   3         2         1
11774  *  10987654321098765432109876543210
11775  *  001000               x0010101101
11776  *     rt -----
11777  *          rs -----
11778  *               rd -----
11779  */
11780 static char *PRECRQ_QB_PH(uint64 instruction, Dis_info *info)
11781 {
11782     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11783     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11784     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11785 
11786     const char *rd = GPR(rd_value, info);
11787     const char *rs = GPR(rs_value, info);
11788     const char *rt = GPR(rt_value, info);
11789 
11790     return img_format("PRECRQ.QB.PH %s, %s, %s", rd, rs, rt);
11791 }
11792 
11793 
11794 /*
11795  * [DSP] PRECRQ_RS.PH.W rd, rs, rt - Reduce the precision of fractional
11796  *   words to halfwords with rounding and saturation
11797  *
11798  *   3         2         1
11799  *  10987654321098765432109876543210
11800  *  001000               x1110000101
11801  *     rt -----
11802  *          rs -----
11803  *               rd -----
11804  */
11805 static char *PRECRQ_RS_PH_W(uint64 instruction, Dis_info *info)
11806 {
11807     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11808     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11809     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11810 
11811     const char *rd = GPR(rd_value, info);
11812     const char *rs = GPR(rs_value, info);
11813     const char *rt = GPR(rt_value, info);
11814 
11815     return img_format("PRECRQ_RS.PH.W %s, %s, %s", rd, rs, rt);
11816 }
11817 
11818 
11819 /*
11820  * [DSP] PRECRQU_S.QB.PH rd, rs, rt - Reduce the precision of fractional
11821  *   halfwords to unsigned bytes with saturation
11822  *
11823  *   3         2         1
11824  *  10987654321098765432109876543210
11825  *  001000               x1110000101
11826  *     rt -----
11827  *          rs -----
11828  *               rd -----
11829  */
11830 static char *PRECRQU_S_QB_PH(uint64 instruction, Dis_info *info)
11831 {
11832     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11833     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11834     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
11835 
11836     const char *rd = GPR(rd_value, info);
11837     const char *rs = GPR(rs_value, info);
11838     const char *rt = GPR(rt_value, info);
11839 
11840     return img_format("PRECRQU_S.QB.PH %s, %s, %s", rd, rs, rt);
11841 }
11842 
11843 
11844 /*
11845  *
11846  *
11847  *   3         2         1
11848  *  10987654321098765432109876543210
11849  *  001000               x1110000101
11850  *     rt -----
11851  *          rs -----
11852  *               rd -----
11853  */
11854 static char *PREF_S9_(uint64 instruction, Dis_info *info)
11855 {
11856     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
11857     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11858     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
11859 
11860     const char *rs = GPR(rs_value, info);
11861 
11862     return img_format("PREF 0x%" PRIx64 ", %s(%s)",
11863                       hint_value, s_value, rs);
11864 }
11865 
11866 
11867 /*
11868  *
11869  *
11870  *   3         2         1
11871  *  10987654321098765432109876543210
11872  *  001000               x1110000101
11873  *     rt -----
11874  *          rs -----
11875  *               rd -----
11876  */
11877 static char *PREF_U12_(uint64 instruction, Dis_info *info)
11878 {
11879     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
11880     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11881     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
11882 
11883     const char *rs = GPR(rs_value, info);
11884 
11885     return img_format("PREF 0x%" PRIx64 ", 0x%" PRIx64 "(%s)",
11886                       hint_value, u_value, rs);
11887 }
11888 
11889 
11890 /*
11891  *
11892  *
11893  *   3         2         1
11894  *  10987654321098765432109876543210
11895  *  001000               x1110000101
11896  *     rt -----
11897  *          rs -----
11898  *               rd -----
11899  */
11900 static char *PREFE(uint64 instruction, Dis_info *info)
11901 {
11902     uint64 hint_value = extract_hint_25_24_23_22_21(instruction);
11903     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11904     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
11905 
11906     const char *rs = GPR(rs_value, info);
11907 
11908     return img_format("PREFE 0x%" PRIx64 ", %s(%s)", hint_value, s_value, rs);
11909 }
11910 
11911 
11912 /*
11913  * [DSP] PREPEND rt, rs, sa - Right shift and prepend bits to the MSB
11914  *
11915  *   3         2         1
11916  *  10987654321098765432109876543210
11917  *  001000               x1110000101
11918  *     rt -----
11919  *          rs -----
11920  *               rd -----
11921  */
11922 static char *PREPEND(uint64 instruction, Dis_info *info)
11923 {
11924     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11925     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11926     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
11927 
11928     const char *rt = GPR(rt_value, info);
11929     const char *rs = GPR(rs_value, info);
11930 
11931     return img_format("PREPEND %s, %s, 0x%" PRIx64, rt, rs, sa_value);
11932 }
11933 
11934 
11935 /*
11936  * [DSP] RADDU.W.QB rt, rs - Unsigned reduction add of vector quad bytes
11937  *
11938  *   3         2         1
11939  *  10987654321098765432109876543210
11940  *  001000          1111000100111111
11941  *     rt -----
11942  *          rs -----
11943  */
11944 static char *RADDU_W_QB(uint64 instruction, Dis_info *info)
11945 {
11946     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11947     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
11948 
11949     const char *rt = GPR(rt_value, info);
11950     const char *rs = GPR(rs_value, info);
11951 
11952     return img_format("RADDU.W.QB %s, %s", rt, rs);
11953 }
11954 
11955 
11956 /*
11957  * [DSP] RDDSP rt, mask - Read DSPControl register fields to a GPR
11958  *
11959  *   3         2         1
11960  *  10987654321098765432109876543210
11961  *  001000            00011001111111
11962  *     rt -----
11963  *        mask -------
11964  */
11965 static char *RDDSP(uint64 instruction, Dis_info *info)
11966 {
11967     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11968     uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction);
11969 
11970     const char *rt = GPR(rt_value, info);
11971 
11972     return img_format("RDDSP %s, 0x%" PRIx64, rt, mask_value);
11973 }
11974 
11975 
11976 /*
11977  *
11978  *
11979  *   3         2         1
11980  *  10987654321098765432109876543210
11981  *  001000               x1110000101
11982  *     rt -----
11983  *          rs -----
11984  *               rd -----
11985  */
11986 static char *RDHWR(uint64 instruction, Dis_info *info)
11987 {
11988     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
11989     uint64 hs_value = extract_hs_20_19_18_17_16(instruction);
11990     uint64 sel_value = extract_sel_13_12_11(instruction);
11991 
11992     const char *rt = GPR(rt_value, info);
11993 
11994     return img_format("RDHWR %s, CP%" PRIu64 ", 0x%" PRIx64,
11995                       rt, hs_value, sel_value);
11996 }
11997 
11998 
11999 /*
12000  *
12001  *
12002  *   3         2         1
12003  *  10987654321098765432109876543210
12004  *  001000               x1110000101
12005  *     rt -----
12006  *          rs -----
12007  *               rd -----
12008  */
12009 static char *RDPGPR(uint64 instruction, Dis_info *info)
12010 {
12011     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12012     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12013 
12014     const char *rt = GPR(rt_value, info);
12015     const char *rs = GPR(rs_value, info);
12016 
12017     return img_format("RDPGPR %s, %s", rt, rs);
12018 }
12019 
12020 
12021 /*
12022  *
12023  *
12024  *   3         2         1
12025  *  10987654321098765432109876543210
12026  *  001000               x1110000101
12027  *     rt -----
12028  *          rs -----
12029  *               rd -----
12030  */
12031 static char *RECIP_D(uint64 instruction, Dis_info *info)
12032 {
12033     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12034     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12035 
12036     const char *ft = FPR(ft_value, info);
12037     const char *fs = FPR(fs_value, info);
12038 
12039     return img_format("RECIP.D %s, %s", ft, fs);
12040 }
12041 
12042 
12043 /*
12044  *
12045  *
12046  *   3         2         1
12047  *  10987654321098765432109876543210
12048  *  001000               x1110000101
12049  *     rt -----
12050  *          rs -----
12051  *               rd -----
12052  */
12053 static char *RECIP_S(uint64 instruction, Dis_info *info)
12054 {
12055     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12056     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12057 
12058     const char *ft = FPR(ft_value, info);
12059     const char *fs = FPR(fs_value, info);
12060 
12061     return img_format("RECIP.S %s, %s", ft, fs);
12062 }
12063 
12064 
12065 /*
12066  * [DSP] REPL.PH rd, s - Replicate immediate integer into all vector element
12067  *   positions
12068  *
12069  *   3         2         1
12070  *  10987654321098765432109876543210
12071  *  001000               x0000111101
12072  *     rt -----
12073  *           s ----------
12074  */
12075 static char *REPL_PH(uint64 instruction, Dis_info *info)
12076 {
12077     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12078     int64 s_value = extract_s__se9_20_19_18_17_16_15_14_13_12_11(instruction);
12079 
12080     const char *rt = GPR(rt_value, info);
12081 
12082     return img_format("REPL.PH %s, %s", rt, s_value);
12083 }
12084 
12085 
12086 /*
12087  * [DSP] REPL.QB rd, u - Replicate immediate integer into all vector element
12088  *   positions
12089  *
12090  *   3         2         1
12091  *  10987654321098765432109876543210
12092  *  001000             x010111111111
12093  *     rt -----
12094  *           u --------
12095  */
12096 static char *REPL_QB(uint64 instruction, Dis_info *info)
12097 {
12098     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12099     uint64 u_value = extract_u_20_19_18_17_16_15_14_13(instruction);
12100 
12101     const char *rt = GPR(rt_value, info);
12102 
12103     return img_format("REPL.QB %s, 0x%" PRIx64, rt, u_value);
12104 }
12105 
12106 
12107 /*
12108  * [DSP] REPLV.PH rt, rs - Replicate a halfword into all vector element
12109  *   positions
12110  *
12111  *   3         2         1
12112  *  10987654321098765432109876543210
12113  *  001000          0000001100111111
12114  *     rt -----
12115  *          rs -----
12116  */
12117 static char *REPLV_PH(uint64 instruction, Dis_info *info)
12118 {
12119     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12120     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12121 
12122     const char *rt = GPR(rt_value, info);
12123     const char *rs = GPR(rs_value, info);
12124 
12125     return img_format("REPLV.PH %s, %s", rt, rs);
12126 }
12127 
12128 
12129 /*
12130  * [DSP] REPLV.QB rt, rs - Replicate byte into all vector element positions
12131  *
12132  *   3         2         1
12133  *  10987654321098765432109876543210
12134  *  001000          0001001100111111
12135  *     rt -----
12136  *          rs -----
12137  */
12138 static char *REPLV_QB(uint64 instruction, Dis_info *info)
12139 {
12140     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12141     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12142 
12143     const char *rt = GPR(rt_value, info);
12144     const char *rs = GPR(rs_value, info);
12145 
12146     return img_format("REPLV.QB %s, %s", rt, rs);
12147 }
12148 
12149 
12150 /*
12151  *
12152  *
12153  *   3         2         1
12154  *  10987654321098765432109876543210
12155  *  001000               x1110000101
12156  *     rt -----
12157  *          rs -----
12158  *               rd -----
12159  */
12160 static char *RESTORE_32_(uint64 instruction, Dis_info *info)
12161 {
12162     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12163     uint64 count_value = extract_count_19_18_17_16(instruction);
12164     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12165     uint64 gp_value = extract_gp_2(instruction);
12166 
12167     g_autofree char *save_restore_str = save_restore_list(
12168         rt_value, count_value, gp_value, info);
12169     return img_format("RESTORE 0x%" PRIx64 "%s", u_value, save_restore_str);
12170 }
12171 
12172 
12173 /*
12174  *
12175  *
12176  *   3         2         1
12177  *  10987654321098765432109876543210
12178  *  001000               x1110000101
12179  *     rt -----
12180  *          rs -----
12181  *               rd -----
12182  */
12183 static char *RESTORE_JRC_16_(uint64 instruction, Dis_info *info)
12184 {
12185     uint64 rt1_value = extract_rtl_11(instruction);
12186     uint64 u_value = extract_u_7_6_5_4__s4(instruction);
12187     uint64 count_value = extract_count_3_2_1_0(instruction);
12188 
12189     g_autofree char *save_restore_str = save_restore_list(
12190         encode_rt1_from_rt(rt1_value), count_value, 0, info);
12191     return img_format("RESTORE.JRC 0x%" PRIx64 "%s", u_value, save_restore_str);
12192 }
12193 
12194 
12195 /*
12196  *
12197  *
12198  *   3         2         1
12199  *  10987654321098765432109876543210
12200  *  001000               x1110000101
12201  *     rt -----
12202  *          rs -----
12203  *               rd -----
12204  */
12205 static char *RESTORE_JRC_32_(uint64 instruction, Dis_info *info)
12206 {
12207     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12208     uint64 count_value = extract_count_19_18_17_16(instruction);
12209     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12210     uint64 gp_value = extract_gp_2(instruction);
12211 
12212     g_autofree char *save_restore_str = save_restore_list(
12213         rt_value, count_value, gp_value, info);
12214     return img_format("RESTORE.JRC 0x%" PRIx64 "%s", u_value,
12215                       save_restore_str);
12216 }
12217 
12218 
12219 /*
12220  *
12221  *
12222  *   3         2         1
12223  *  10987654321098765432109876543210
12224  *  001000               x1110000101
12225  *     rt -----
12226  *          rs -----
12227  *               rd -----
12228  */
12229 static char *RESTOREF(uint64 instruction, Dis_info *info)
12230 {
12231     uint64 count_value = extract_count_19_18_17_16(instruction);
12232     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12233 
12234 
12235     return img_format("RESTOREF 0x%" PRIx64 ", %s", u_value, count_value);
12236 }
12237 
12238 
12239 /*
12240  *
12241  *
12242  *   3         2         1
12243  *  10987654321098765432109876543210
12244  *  001000               x1110000101
12245  *     rt -----
12246  *          rs -----
12247  *               rd -----
12248  */
12249 static char *RINT_D(uint64 instruction, Dis_info *info)
12250 {
12251     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12252     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12253 
12254     const char *ft = FPR(ft_value, info);
12255     const char *fs = FPR(fs_value, info);
12256 
12257     return img_format("RINT.D %s, %s", ft, fs);
12258 }
12259 
12260 
12261 /*
12262  *
12263  *
12264  *   3         2         1
12265  *  10987654321098765432109876543210
12266  *  001000               x1110000101
12267  *     rt -----
12268  *          rs -----
12269  *               rd -----
12270  */
12271 static char *RINT_S(uint64 instruction, Dis_info *info)
12272 {
12273     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12274     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12275 
12276     const char *ft = FPR(ft_value, info);
12277     const char *fs = FPR(fs_value, info);
12278 
12279     return img_format("RINT.S %s, %s", ft, fs);
12280 }
12281 
12282 
12283 /*
12284  *
12285  *
12286  *   3         2         1
12287  *  10987654321098765432109876543210
12288  *  001000               x1110000101
12289  *     rt -----
12290  *          rs -----
12291  *               rd -----
12292  */
12293 static char *ROTR(uint64 instruction, Dis_info *info)
12294 {
12295     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12296     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12297     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
12298 
12299     const char *rt = GPR(rt_value, info);
12300     const char *rs = GPR(rs_value, info);
12301 
12302     return img_format("ROTR %s, %s, 0x%" PRIx64, rt, rs, shift_value);
12303 }
12304 
12305 
12306 /*
12307  *
12308  *
12309  *   3         2         1
12310  *  10987654321098765432109876543210
12311  *  001000               x1110000101
12312  *     rt -----
12313  *          rs -----
12314  *               rd -----
12315  */
12316 static char *ROTRV(uint64 instruction, Dis_info *info)
12317 {
12318     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12319     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12320     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12321 
12322     const char *rd = GPR(rd_value, info);
12323     const char *rs = GPR(rs_value, info);
12324     const char *rt = GPR(rt_value, info);
12325 
12326     return img_format("ROTRV %s, %s, %s", rd, rs, rt);
12327 }
12328 
12329 
12330 /*
12331  *
12332  *
12333  *   3         2         1
12334  *  10987654321098765432109876543210
12335  *  001000               x1110000101
12336  *     rt -----
12337  *          rs -----
12338  *               rd -----
12339  */
12340 static char *ROTX(uint64 instruction, Dis_info *info)
12341 {
12342     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12343     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12344     uint64 shiftx_value = extract_shiftx_10_9_8_7__s1(instruction);
12345     uint64 stripe_value = extract_stripe_6(instruction);
12346     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
12347 
12348     const char *rt = GPR(rt_value, info);
12349     const char *rs = GPR(rs_value, info);
12350 
12351     return img_format("ROTX %s, %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64,
12352                        rt, rs, shift_value, shiftx_value, stripe_value);
12353 }
12354 
12355 
12356 /*
12357  *
12358  *
12359  *   3         2         1
12360  *  10987654321098765432109876543210
12361  *  001000               x1110000101
12362  *     rt -----
12363  *          rs -----
12364  *               rd -----
12365  */
12366 static char *ROUND_L_D(uint64 instruction, Dis_info *info)
12367 {
12368     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12369     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12370 
12371     const char *ft = FPR(ft_value, info);
12372     const char *fs = FPR(fs_value, info);
12373 
12374     return img_format("ROUND.L.D %s, %s", ft, fs);
12375 }
12376 
12377 
12378 /*
12379  *
12380  *
12381  *   3         2         1
12382  *  10987654321098765432109876543210
12383  *  001000               x1110000101
12384  *     rt -----
12385  *          rs -----
12386  *               rd -----
12387  */
12388 static char *ROUND_L_S(uint64 instruction, Dis_info *info)
12389 {
12390     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12391     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12392 
12393     const char *ft = FPR(ft_value, info);
12394     const char *fs = FPR(fs_value, info);
12395 
12396     return img_format("ROUND.L.S %s, %s", ft, fs);
12397 }
12398 
12399 
12400 /*
12401  *
12402  *
12403  *   3         2         1
12404  *  10987654321098765432109876543210
12405  *  001000               x1110000101
12406  *     rt -----
12407  *          rs -----
12408  *               rd -----
12409  */
12410 static char *ROUND_W_D(uint64 instruction, Dis_info *info)
12411 {
12412     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12413     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12414 
12415     const char *ft = FPR(ft_value, info);
12416     const char *fs = FPR(fs_value, info);
12417 
12418     return img_format("ROUND.W.D %s, %s", ft, fs);
12419 }
12420 
12421 
12422 /*
12423  *
12424  *
12425  *   3         2         1
12426  *  10987654321098765432109876543210
12427  *  001000               x1110000101
12428  *     rt -----
12429  *          rs -----
12430  *               rd -----
12431  */
12432 static char *ROUND_W_S(uint64 instruction, Dis_info *info)
12433 {
12434     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12435     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12436 
12437     const char *ft = FPR(ft_value, info);
12438     const char *fs = FPR(fs_value, info);
12439 
12440     return img_format("ROUND.W.S %s, %s", ft, fs);
12441 }
12442 
12443 
12444 /*
12445  *
12446  *
12447  *   3         2         1
12448  *  10987654321098765432109876543210
12449  *  001000               x1110000101
12450  *     rt -----
12451  *          rs -----
12452  *               rd -----
12453  */
12454 static char *RSQRT_D(uint64 instruction, Dis_info *info)
12455 {
12456     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12457     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12458 
12459     const char *ft = FPR(ft_value, info);
12460     const char *fs = FPR(fs_value, info);
12461 
12462     return img_format("RSQRT.D %s, %s", ft, fs);
12463 }
12464 
12465 
12466 /*
12467  *
12468  *
12469  *   3         2         1
12470  *  10987654321098765432109876543210
12471  *  001000               x1110000101
12472  *     rt -----
12473  *          rs -----
12474  *               rd -----
12475  */
12476 static char *RSQRT_S(uint64 instruction, Dis_info *info)
12477 {
12478     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12479     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
12480 
12481     const char *ft = FPR(ft_value, info);
12482     const char *fs = FPR(fs_value, info);
12483 
12484     return img_format("RSQRT.S %s, %s", ft, fs);
12485 }
12486 
12487 
12488 /*
12489  *
12490  *
12491  *   3         2         1
12492  *  10987654321098765432109876543210
12493  *  001000               01001001101
12494  *     rt -----
12495  *          rs -----
12496  *               rd -----
12497  */
12498 static char *SAVE_16_(uint64 instruction, Dis_info *info)
12499 {
12500     uint64 rt1_value = extract_rtl_11(instruction);
12501     uint64 u_value = extract_u_7_6_5_4__s4(instruction);
12502     uint64 count_value = extract_count_3_2_1_0(instruction);
12503 
12504     g_autofree char *save_restore_str = save_restore_list(
12505         encode_rt1_from_rt(rt1_value), count_value, 0, info);
12506     return img_format("SAVE 0x%" PRIx64 "%s", u_value, save_restore_str);
12507 }
12508 
12509 
12510 /*
12511  *
12512  *
12513  *   3         2         1
12514  *  10987654321098765432109876543210
12515  *  001000               01001001101
12516  *     rt -----
12517  *          rs -----
12518  *               rd -----
12519  */
12520 static char *SAVE_32_(uint64 instruction, Dis_info *info)
12521 {
12522     uint64 count_value = extract_count_19_18_17_16(instruction);
12523     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12524     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12525     uint64 gp_value = extract_gp_2(instruction);
12526 
12527     g_autofree char *save_restore_str = save_restore_list(
12528         rt_value, count_value, gp_value, info);
12529     return img_format("SAVE 0x%" PRIx64 "%s", u_value, save_restore_str);
12530 }
12531 
12532 
12533 /*
12534  *
12535  *
12536  *   3         2         1
12537  *  10987654321098765432109876543210
12538  *  001000               01001001101
12539  *     rt -----
12540  *          rs -----
12541  *               rd -----
12542  */
12543 static char *SAVEF(uint64 instruction, Dis_info *info)
12544 {
12545     uint64 count_value = extract_count_19_18_17_16(instruction);
12546     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction);
12547 
12548 
12549     return img_format("SAVEF 0x%" PRIx64 ", 0x%" PRIx64, u_value, count_value);
12550 }
12551 
12552 
12553 /*
12554  *
12555  *
12556  *   3         2         1
12557  *  10987654321098765432109876543210
12558  *  001000               01001001101
12559  *     rt -----
12560  *          rs -----
12561  *               rd -----
12562  */
12563 static char *SB_16_(uint64 instruction, Dis_info *info)
12564 {
12565     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
12566     uint64 rs3_value = extract_rs3_6_5_4(instruction);
12567     uint64 u_value = extract_u_1_0(instruction);
12568 
12569     const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info);
12570     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
12571 
12572     return img_format("SB %s, 0x%" PRIx64 "(%s)", rtz3, u_value, rs3);
12573 }
12574 
12575 
12576 /*
12577  *
12578  *
12579  *   3         2         1
12580  *  10987654321098765432109876543210
12581  *  001000               01001001101
12582  *     rt -----
12583  *          rs -----
12584  *               rd -----
12585  */
12586 static char *SB_GP_(uint64 instruction, Dis_info *info)
12587 {
12588     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12589     uint64 u_value = extract_u_17_to_0(instruction);
12590 
12591     const char *rt = GPR(rt_value, info);
12592 
12593     return img_format("SB %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
12594 }
12595 
12596 
12597 /*
12598  *
12599  *
12600  *   3         2         1
12601  *  10987654321098765432109876543210
12602  *  001000               01001001101
12603  *     rt -----
12604  *          rs -----
12605  *               rd -----
12606  */
12607 static char *SB_S9_(uint64 instruction, Dis_info *info)
12608 {
12609     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12610     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12611     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12612 
12613     const char *rt = GPR(rt_value, info);
12614     const char *rs = GPR(rs_value, info);
12615 
12616     return img_format("SB %s, %s(%s)", rt, s_value, rs);
12617 }
12618 
12619 
12620 /*
12621  *
12622  *
12623  *   3         2         1
12624  *  10987654321098765432109876543210
12625  *  001000               01001001101
12626  *     rt -----
12627  *          rs -----
12628  *               rd -----
12629  */
12630 static char *SB_U12_(uint64 instruction, Dis_info *info)
12631 {
12632     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12633     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12634     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
12635 
12636     const char *rt = GPR(rt_value, info);
12637     const char *rs = GPR(rs_value, info);
12638 
12639     return img_format("SB %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
12640 }
12641 
12642 
12643 /*
12644  *
12645  *
12646  *   3         2         1
12647  *  10987654321098765432109876543210
12648  *  001000               01001001101
12649  *     rt -----
12650  *          rs -----
12651  *               rd -----
12652  */
12653 static char *SBE(uint64 instruction, Dis_info *info)
12654 {
12655     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12656     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12657     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12658 
12659     const char *rt = GPR(rt_value, info);
12660     const char *rs = GPR(rs_value, info);
12661 
12662     return img_format("SBE %s, %s(%s)", rt, s_value, rs);
12663 }
12664 
12665 
12666 /*
12667  *
12668  *
12669  *   3         2         1
12670  *  10987654321098765432109876543210
12671  *  001000               01001001101
12672  *     rt -----
12673  *          rs -----
12674  *               rd -----
12675  */
12676 static char *SBX(uint64 instruction, Dis_info *info)
12677 {
12678     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12679     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12680     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
12681 
12682     const char *rd = GPR(rd_value, info);
12683     const char *rs = GPR(rs_value, info);
12684     const char *rt = GPR(rt_value, info);
12685 
12686     return img_format("SBX %s, %s(%s)", rd, rs, rt);
12687 }
12688 
12689 
12690 /*
12691  *
12692  *
12693  *   3         2         1
12694  *  10987654321098765432109876543210
12695  *  001000               01001001101
12696  *     rt -----
12697  *          rs -----
12698  *               rd -----
12699  */
12700 static char *SC(uint64 instruction, Dis_info *info)
12701 {
12702     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12703     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12704     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
12705 
12706     const char *rt = GPR(rt_value, info);
12707     const char *rs = GPR(rs_value, info);
12708 
12709     return img_format("SC %s, %s(%s)", rt, s_value, rs);
12710 }
12711 
12712 
12713 /*
12714  *
12715  *
12716  *   3         2         1
12717  *  10987654321098765432109876543210
12718  *  001000               01001001101
12719  *     rt -----
12720  *          rs -----
12721  *               rd -----
12722  */
12723 static char *SCD(uint64 instruction, Dis_info *info)
12724 {
12725     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12726     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12727     int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction);
12728 
12729     const char *rt = GPR(rt_value, info);
12730     const char *rs = GPR(rs_value, info);
12731 
12732     return img_format("SCD %s, %s(%s)", rt, s_value, rs);
12733 }
12734 
12735 
12736 /*
12737  *
12738  *
12739  *   3         2         1
12740  *  10987654321098765432109876543210
12741  *  001000               01001001101
12742  *     rt -----
12743  *          rs -----
12744  *               rd -----
12745  */
12746 static char *SCDP(uint64 instruction, Dis_info *info)
12747 {
12748     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12749     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12750     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
12751 
12752     const char *rt = GPR(rt_value, info);
12753     const char *ru = GPR(ru_value, info);
12754     const char *rs = GPR(rs_value, info);
12755 
12756     return img_format("SCDP %s, %s, (%s)", rt, ru, rs);
12757 }
12758 
12759 
12760 /*
12761  *
12762  *
12763  *   3         2         1
12764  *  10987654321098765432109876543210
12765  *  001000               01001001101
12766  *     rt -----
12767  *          rs -----
12768  *               rd -----
12769  */
12770 static char *SCE(uint64 instruction, Dis_info *info)
12771 {
12772     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12773     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12774     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction);
12775 
12776     const char *rt = GPR(rt_value, info);
12777     const char *rs = GPR(rs_value, info);
12778 
12779     return img_format("SCE %s, %s(%s)", rt, s_value, rs);
12780 }
12781 
12782 
12783 /*
12784  *
12785  *
12786  *   3         2         1
12787  *  10987654321098765432109876543210
12788  *  001000               01001001101
12789  *     rt -----
12790  *          rs -----
12791  *               rd -----
12792  */
12793 static char *SCWP(uint64 instruction, Dis_info *info)
12794 {
12795     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12796     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12797     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
12798 
12799     const char *rt = GPR(rt_value, info);
12800     const char *ru = GPR(ru_value, info);
12801     const char *rs = GPR(rs_value, info);
12802 
12803     return img_format("SCWP %s, %s, (%s)", rt, ru, rs);
12804 }
12805 
12806 
12807 /*
12808  *
12809  *
12810  *   3         2         1
12811  *  10987654321098765432109876543210
12812  *  001000               01001001101
12813  *     rt -----
12814  *          rs -----
12815  *               rd -----
12816  */
12817 static char *SCWPE(uint64 instruction, Dis_info *info)
12818 {
12819     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12820     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12821     uint64 ru_value = extract_ru_7_6_5_4_3(instruction);
12822 
12823     const char *rt = GPR(rt_value, info);
12824     const char *ru = GPR(ru_value, info);
12825     const char *rs = GPR(rs_value, info);
12826 
12827     return img_format("SCWPE %s, %s, (%s)", rt, ru, rs);
12828 }
12829 
12830 
12831 /*
12832  *
12833  *
12834  *   3         2         1
12835  *  10987654321098765432109876543210
12836  *  001000               01001001101
12837  *     rt -----
12838  *          rs -----
12839  *               rd -----
12840  */
12841 static char *SD_GP_(uint64 instruction, Dis_info *info)
12842 {
12843     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12844     uint64 u_value = extract_u_20_to_3__s3(instruction);
12845 
12846     const char *rt = GPR(rt_value, info);
12847 
12848     return img_format("SD %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
12849 }
12850 
12851 
12852 /*
12853  *
12854  *
12855  *   3         2         1
12856  *  10987654321098765432109876543210
12857  *  001000               01001001101
12858  *     rt -----
12859  *          rs -----
12860  *               rd -----
12861  */
12862 static char *SD_S9_(uint64 instruction, Dis_info *info)
12863 {
12864     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12865     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12866     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12867 
12868     const char *rt = GPR(rt_value, info);
12869     const char *rs = GPR(rs_value, info);
12870 
12871     return img_format("SD %s, %s(%s)", rt, s_value, rs);
12872 }
12873 
12874 
12875 /*
12876  *
12877  *
12878  *   3         2         1
12879  *  10987654321098765432109876543210
12880  *  001000               01001001101
12881  *     rt -----
12882  *          rs -----
12883  *               rd -----
12884  */
12885 static char *SD_U12_(uint64 instruction, Dis_info *info)
12886 {
12887     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
12888     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12889     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
12890 
12891     const char *rt = GPR(rt_value, info);
12892     const char *rs = GPR(rs_value, info);
12893 
12894     return img_format("SD %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
12895 }
12896 
12897 
12898 /*
12899  *
12900  *
12901  *   3         2         1
12902  *  10987654321098765432109876543210
12903  *  001000               01001001101
12904  *     rt -----
12905  *          rs -----
12906  *               rd -----
12907  */
12908 static char *SDBBP_16_(uint64 instruction, Dis_info *info)
12909 {
12910     uint64 code_value = extract_code_2_1_0(instruction);
12911 
12912 
12913     return img_format("SDBBP 0x%" PRIx64, code_value);
12914 }
12915 
12916 
12917 /*
12918  *
12919  *
12920  *   3         2         1
12921  *  10987654321098765432109876543210
12922  *  001000               01001001101
12923  *     rt -----
12924  *          rs -----
12925  *               rd -----
12926  */
12927 static char *SDBBP_32_(uint64 instruction, Dis_info *info)
12928 {
12929     uint64 code_value = extract_code_18_to_0(instruction);
12930 
12931 
12932     return img_format("SDBBP 0x%" PRIx64, code_value);
12933 }
12934 
12935 
12936 /*
12937  *
12938  *
12939  *   3         2         1
12940  *  10987654321098765432109876543210
12941  *  001000               01001001101
12942  *     rt -----
12943  *          rs -----
12944  *               rd -----
12945  */
12946 static char *SDC1_GP_(uint64 instruction, Dis_info *info)
12947 {
12948     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12949     uint64 u_value = extract_u_17_to_2__s2(instruction);
12950 
12951     const char *ft = FPR(ft_value, info);
12952 
12953     return img_format("SDC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28);
12954 }
12955 
12956 
12957 /*
12958  *
12959  *
12960  *   3         2         1
12961  *  10987654321098765432109876543210
12962  *  001000               01001001101
12963  *     rt -----
12964  *          rs -----
12965  *               rd -----
12966  */
12967 static char *SDC1_S9_(uint64 instruction, Dis_info *info)
12968 {
12969     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12970     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12971     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
12972 
12973     const char *ft = FPR(ft_value, info);
12974     const char *rs = GPR(rs_value, info);
12975 
12976     return img_format("SDC1 %s, %s(%s)", ft, s_value, rs);
12977 }
12978 
12979 
12980 /*
12981  *
12982  *
12983  *   3         2         1
12984  *  10987654321098765432109876543210
12985  *  001000               01001001101
12986  *     rt -----
12987  *          rs -----
12988  *               rd -----
12989  */
12990 static char *SDC1_U12_(uint64 instruction, Dis_info *info)
12991 {
12992     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
12993     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
12994     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
12995 
12996     const char *ft = FPR(ft_value, info);
12997     const char *rs = GPR(rs_value, info);
12998 
12999     return img_format("SDC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs);
13000 }
13001 
13002 
13003 /*
13004  *
13005  *
13006  *   3         2         1
13007  *  10987654321098765432109876543210
13008  *  001000               01001001101
13009  *     rt -----
13010  *          rs -----
13011  *               rd -----
13012  */
13013 static char *SDC1X(uint64 instruction, Dis_info *info)
13014 {
13015     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13016     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13017     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
13018 
13019     const char *ft = FPR(ft_value, info);
13020     const char *rs = GPR(rs_value, info);
13021     const char *rt = GPR(rt_value, info);
13022 
13023     return img_format("SDC1X %s, %s(%s)", ft, rs, rt);
13024 }
13025 
13026 
13027 /*
13028  *
13029  *
13030  *   3         2         1
13031  *  10987654321098765432109876543210
13032  *  001000               01001001101
13033  *     rt -----
13034  *          rs -----
13035  *               rd -----
13036  */
13037 static char *SDC1XS(uint64 instruction, Dis_info *info)
13038 {
13039     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13040     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13041     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
13042 
13043     const char *ft = FPR(ft_value, info);
13044     const char *rs = GPR(rs_value, info);
13045     const char *rt = GPR(rt_value, info);
13046 
13047     return img_format("SDC1XS %s, %s(%s)", ft, rs, rt);
13048 }
13049 
13050 
13051 /*
13052  *
13053  *
13054  *   3         2         1
13055  *  10987654321098765432109876543210
13056  *  001000               01001001101
13057  *     rt -----
13058  *          rs -----
13059  *               rd -----
13060  */
13061 static char *SDC2(uint64 instruction, Dis_info *info)
13062 {
13063     uint64 cs_value = extract_cs_25_24_23_22_21(instruction);
13064     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13065     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13066 
13067     const char *rs = GPR(rs_value, info);
13068 
13069     return img_format("SDC2 CP%" PRIu64 ", %s(%s)", cs_value, s_value, rs);
13070 }
13071 
13072 
13073 /*
13074  *
13075  *
13076  *   3         2         1
13077  *  10987654321098765432109876543210
13078  *  001000               01001001101
13079  *     rt -----
13080  *          rs -----
13081  *               rd -----
13082  */
13083 static char *SDM(uint64 instruction, Dis_info *info)
13084 {
13085     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13086     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13087     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13088     uint64 count3_value = extract_count3_14_13_12(instruction);
13089 
13090     const char *rt = GPR(rt_value, info);
13091     const char *rs = GPR(rs_value, info);
13092     uint64 count3 = encode_count3_from_count(count3_value);
13093 
13094     return img_format("SDM %s, %s(%s), 0x%" PRIx64, rt, s_value, rs, count3);
13095 }
13096 
13097 
13098 /*
13099  *
13100  *
13101  *   3         2         1
13102  *  10987654321098765432109876543210
13103  *  001000               01001001101
13104  *     rt -----
13105  *          rs -----
13106  *               rd -----
13107  */
13108 static char *SDPC_48_(uint64 instruction, Dis_info *info)
13109 {
13110     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
13111     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
13112 
13113     const char *rt = GPR(rt_value, info);
13114     g_autofree char *s = ADDRESS(s_value, 6, info);
13115 
13116     return img_format("SDPC %s, %s", rt, s);
13117 }
13118 
13119 
13120 /*
13121  *
13122  *
13123  *   3         2         1
13124  *  10987654321098765432109876543210
13125  *  001000               01001001101
13126  *     rt -----
13127  *          rs -----
13128  *               rd -----
13129  */
13130 static char *SDXS(uint64 instruction, Dis_info *info)
13131 {
13132     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13133     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13134     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13135 
13136     const char *rd = GPR(rd_value, info);
13137     const char *rs = GPR(rs_value, info);
13138     const char *rt = GPR(rt_value, info);
13139 
13140     return img_format("SDXS %s, %s(%s)", rd, rs, rt);
13141 }
13142 
13143 
13144 /*
13145  *
13146  *
13147  *   3         2         1
13148  *  10987654321098765432109876543210
13149  *  001000               01001001101
13150  *     rt -----
13151  *          rs -----
13152  *               rd -----
13153  */
13154 static char *SDX(uint64 instruction, Dis_info *info)
13155 {
13156     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13157     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13158     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13159 
13160     const char *rd = GPR(rd_value, info);
13161     const char *rs = GPR(rs_value, info);
13162     const char *rt = GPR(rt_value, info);
13163 
13164     return img_format("SDX %s, %s(%s)", rd, rs, rt);
13165 }
13166 
13167 
13168 /*
13169  *
13170  *
13171  *   3         2         1
13172  *  10987654321098765432109876543210
13173  *  001000               01001001101
13174  *     rt -----
13175  *          rs -----
13176  *               rd -----
13177  */
13178 static char *SEB(uint64 instruction, Dis_info *info)
13179 {
13180     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13181     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13182 
13183     const char *rt = GPR(rt_value, info);
13184     const char *rs = GPR(rs_value, info);
13185 
13186     return img_format("SEB %s, %s", rt, rs);
13187 }
13188 
13189 
13190 /*
13191  *
13192  *
13193  *   3         2         1
13194  *  10987654321098765432109876543210
13195  *  001000               01001001101
13196  *     rt -----
13197  *          rs -----
13198  *               rd -----
13199  */
13200 static char *SEH(uint64 instruction, Dis_info *info)
13201 {
13202     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13203     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13204 
13205     const char *rt = GPR(rt_value, info);
13206     const char *rs = GPR(rs_value, info);
13207 
13208     return img_format("SEH %s, %s", rt, rs);
13209 }
13210 
13211 
13212 /*
13213  *
13214  *
13215  *   3         2         1
13216  *  10987654321098765432109876543210
13217  *  001000               01001001101
13218  *     rt -----
13219  *          rs -----
13220  *               rd -----
13221  */
13222 static char *SEL_D(uint64 instruction, Dis_info *info)
13223 {
13224     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13225     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13226     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13227 
13228     const char *fd = FPR(fd_value, info);
13229     const char *fs = FPR(fs_value, info);
13230     const char *ft = FPR(ft_value, info);
13231 
13232     return img_format("SEL.D %s, %s, %s", fd, fs, ft);
13233 }
13234 
13235 
13236 /*
13237  *
13238  *
13239  *   3         2         1
13240  *  10987654321098765432109876543210
13241  *  001000               01001001101
13242  *     rt -----
13243  *          rs -----
13244  *               rd -----
13245  */
13246 static char *SEL_S(uint64 instruction, Dis_info *info)
13247 {
13248     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13249     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13250     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13251 
13252     const char *fd = FPR(fd_value, info);
13253     const char *fs = FPR(fs_value, info);
13254     const char *ft = FPR(ft_value, info);
13255 
13256     return img_format("SEL.S %s, %s, %s", fd, fs, ft);
13257 }
13258 
13259 
13260 /*
13261  *
13262  *
13263  *   3         2         1
13264  *  10987654321098765432109876543210
13265  *  001000               01001001101
13266  *     rt -----
13267  *          rs -----
13268  *               rd -----
13269  */
13270 static char *SELEQZ_D(uint64 instruction, Dis_info *info)
13271 {
13272     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13273     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13274     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13275 
13276     const char *fd = FPR(fd_value, info);
13277     const char *fs = FPR(fs_value, info);
13278     const char *ft = FPR(ft_value, info);
13279 
13280     return img_format("SELEQZ.D %s, %s, %s", fd, fs, ft);
13281 }
13282 
13283 
13284 /*
13285  *
13286  *
13287  *   3         2         1
13288  *  10987654321098765432109876543210
13289  *  001000               01001001101
13290  *     rt -----
13291  *          rs -----
13292  *               rd -----
13293  */
13294 static char *SELEQZ_S(uint64 instruction, Dis_info *info)
13295 {
13296     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13297     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13298     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13299 
13300     const char *fd = FPR(fd_value, info);
13301     const char *fs = FPR(fs_value, info);
13302     const char *ft = FPR(ft_value, info);
13303 
13304     return img_format("SELEQZ.S %s, %s, %s", fd, fs, ft);
13305 }
13306 
13307 
13308 /*
13309  *
13310  *
13311  *   3         2         1
13312  *  10987654321098765432109876543210
13313  *  001000               01001001101
13314  *     rt -----
13315  *          rs -----
13316  *               rd -----
13317  */
13318 static char *SELNEZ_D(uint64 instruction, Dis_info *info)
13319 {
13320     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13321     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13322     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13323 
13324     const char *fd = FPR(fd_value, info);
13325     const char *fs = FPR(fs_value, info);
13326     const char *ft = FPR(ft_value, info);
13327 
13328     return img_format("SELNEZ.D %s, %s, %s", fd, fs, ft);
13329 }
13330 
13331 
13332 /*
13333  *
13334  *
13335  *   3         2         1
13336  *  10987654321098765432109876543210
13337  *  001000               01001001101
13338  *     rt -----
13339  *          rs -----
13340  *               rd -----
13341  */
13342 static char *SELNEZ_S(uint64 instruction, Dis_info *info)
13343 {
13344     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
13345     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
13346     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
13347 
13348     const char *fd = FPR(fd_value, info);
13349     const char *fs = FPR(fs_value, info);
13350     const char *ft = FPR(ft_value, info);
13351 
13352     return img_format("SELNEZ.S %s, %s, %s", fd, fs, ft);
13353 }
13354 
13355 
13356 /*
13357  *
13358  *
13359  *   3         2         1
13360  *  10987654321098765432109876543210
13361  *  001000               01001001101
13362  *     rt -----
13363  *          rs -----
13364  *               rd -----
13365  */
13366 static char *SEQI(uint64 instruction, Dis_info *info)
13367 {
13368     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13369     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13370     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13371 
13372     const char *rt = GPR(rt_value, info);
13373     const char *rs = GPR(rs_value, info);
13374 
13375     return img_format("SEQI %s, %s, 0x%" PRIx64, rt, rs, u_value);
13376 }
13377 
13378 
13379 /*
13380  *
13381  *
13382  *   3         2         1
13383  *  10987654321098765432109876543210
13384  *  001000               01001001101
13385  *     rt -----
13386  *          rs -----
13387  *               rd -----
13388  */
13389 static char *SH_16_(uint64 instruction, Dis_info *info)
13390 {
13391     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
13392     uint64 rs3_value = extract_rs3_6_5_4(instruction);
13393     uint64 u_value = extract_u_2_1__s1(instruction);
13394 
13395     const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info);
13396     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
13397 
13398     return img_format("SH %s, 0x%" PRIx64 "(%s)", rtz3, u_value, rs3);
13399 }
13400 
13401 
13402 /*
13403  *
13404  *
13405  *   3         2         1
13406  *  10987654321098765432109876543210
13407  *  001000               01001001101
13408  *     rt -----
13409  *          rs -----
13410  *               rd -----
13411  */
13412 static char *SH_GP_(uint64 instruction, Dis_info *info)
13413 {
13414     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13415     uint64 u_value = extract_u_17_to_1__s1(instruction);
13416 
13417     const char *rt = GPR(rt_value, info);
13418 
13419     return img_format("SH %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
13420 }
13421 
13422 
13423 /*
13424  *
13425  *
13426  *   3         2         1
13427  *  10987654321098765432109876543210
13428  *  001000               01001001101
13429  *     rt -----
13430  *          rs -----
13431  *               rd -----
13432  */
13433 static char *SH_S9_(uint64 instruction, Dis_info *info)
13434 {
13435     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13436     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13437     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13438 
13439     const char *rt = GPR(rt_value, info);
13440     const char *rs = GPR(rs_value, info);
13441 
13442     return img_format("SH %s, %" PRId64 "(%s)", rt, s_value, rs);
13443 }
13444 
13445 
13446 /*
13447  *
13448  *
13449  *   3         2         1
13450  *  10987654321098765432109876543210
13451  *  001000               01001001101
13452  *     rt -----
13453  *          rs -----
13454  *               rd -----
13455  */
13456 static char *SH_U12_(uint64 instruction, Dis_info *info)
13457 {
13458     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13459     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13460     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
13461 
13462     const char *rt = GPR(rt_value, info);
13463     const char *rs = GPR(rs_value, info);
13464 
13465     return img_format("SH %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
13466 }
13467 
13468 
13469 /*
13470  *
13471  *
13472  *   3         2         1
13473  *  10987654321098765432109876543210
13474  *  001000               01001001101
13475  *     rt -----
13476  *          rs -----
13477  *               rd -----
13478  */
13479 static char *SHE(uint64 instruction, Dis_info *info)
13480 {
13481     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13482     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13483     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
13484 
13485     const char *rt = GPR(rt_value, info);
13486     const char *rs = GPR(rs_value, info);
13487 
13488     return img_format("SHE %s, %" PRId64 "(%s)", rt, s_value, rs);
13489 }
13490 
13491 
13492 /*
13493  * [DSP] SHILO ac, shift - Shift an accumulator value leaving the result in
13494  *   the same accumulator
13495  *
13496  *   3         2         1
13497  *  10987654321098765432109876543210
13498  *  001000xxxx        xxxx0000011101
13499  *      shift ------
13500  *               ac --
13501  */
13502 static char *SHILO(uint64 instruction, Dis_info *info)
13503 {
13504     int64 shift_value = extract_shift__se5_21_20_19_18_17_16(instruction);
13505     uint64 ac_value = extract_ac_15_14(instruction);
13506 
13507     const char *ac = AC(ac_value, info);
13508 
13509     return img_format("SHILO %s, 0x%" PRIx64, ac, shift_value);
13510 }
13511 
13512 
13513 /*
13514  * [DSP] SHILOV ac, rs - Variable shift of accumulator value leaving the result
13515  *   in the same accumulator
13516  *
13517  *   3         2         1
13518  *  10987654321098765432109876543210
13519  *  001000xxxxx       01001001111111
13520  *          rs -----
13521  *               ac --
13522  */
13523 static char *SHILOV(uint64 instruction, Dis_info *info)
13524 {
13525     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13526     uint64 ac_value = extract_ac_15_14(instruction);
13527 
13528     const char *rs = GPR(rs_value, info);
13529     const char *ac = AC(ac_value, info);
13530 
13531     return img_format("SHILOV %s, %s", ac, rs);
13532 }
13533 
13534 
13535 /*
13536  * [DSP] SHLL.PH rt, rs, sa - Shift left logical vector pair halfwords
13537  *
13538  *   3         2         1
13539  *  10987654321098765432109876543210
13540  *  001000              001110110101
13541  *     rt -----
13542  *          rs -----
13543  *               sa ----
13544  */
13545 static char *SHLL_PH(uint64 instruction, Dis_info *info)
13546 {
13547     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13548     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13549     uint64 sa_value = extract_sa_15_14_13_12(instruction);
13550 
13551     const char *rt = GPR(rt_value, info);
13552     const char *rs = GPR(rs_value, info);
13553 
13554     return img_format("SHLL.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13555 }
13556 
13557 
13558 /*
13559  * [DSP] SHLL.QB rt, rs, sa - Shift left logical vector quad bytes
13560  *
13561  *   3         2         1
13562  *  10987654321098765432109876543210
13563  *  001000             0100001111111
13564  *     rt -----
13565  *          rs -----
13566  *               sa ---
13567  */
13568 static char *SHLL_QB(uint64 instruction, Dis_info *info)
13569 {
13570     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13571     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13572     uint64 sa_value = extract_sa_15_14_13(instruction);
13573 
13574     const char *rt = GPR(rt_value, info);
13575     const char *rs = GPR(rs_value, info);
13576 
13577     return img_format("SHLL.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13578 }
13579 
13580 
13581 /*
13582  * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical vector pair halfwords
13583  *   with saturation
13584  *
13585  *   3         2         1
13586  *  10987654321098765432109876543210
13587  *  001000              001110110101
13588  *     rt -----
13589  *          rs -----
13590  *               sa ----
13591  */
13592 static char *SHLL_S_PH(uint64 instruction, Dis_info *info)
13593 {
13594     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13595     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13596     uint64 sa_value = extract_sa_15_14_13_12(instruction);
13597 
13598     const char *rt = GPR(rt_value, info);
13599     const char *rs = GPR(rs_value, info);
13600 
13601     return img_format("SHLL_S.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13602 }
13603 
13604 
13605 /*
13606  * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical word with saturation
13607  *
13608  *   3         2         1
13609  *  10987654321098765432109876543210
13610  *  001000               x1111110101
13611  *     rt -----
13612  *          rs -----
13613  *               sa -----
13614  */
13615 static char *SHLL_S_W(uint64 instruction, Dis_info *info)
13616 {
13617     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13618     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13619     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
13620 
13621     const char *rt = GPR(rt_value, info);
13622     const char *rs = GPR(rs_value, info);
13623 
13624     return img_format("SHLL_S.W %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13625 }
13626 
13627 
13628 /*
13629  * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair
13630  *   halfwords
13631  *
13632  *   3         2         1
13633  *  10987654321098765432109876543210
13634  *  001000               01110001101
13635  *     rt -----
13636  *          rs -----
13637  *               rd -----
13638  */
13639 static char *SHLLV_PH(uint64 instruction, Dis_info *info)
13640 {
13641     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13642     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13643     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13644 
13645     const char *rd = GPR(rd_value, info);
13646     const char *rt = GPR(rt_value, info);
13647     const char *rs = GPR(rs_value, info);
13648 
13649     return img_format("SHLLV.PH %s, %s, %s", rd, rt, rs);
13650 }
13651 
13652 
13653 /*
13654  * [DSP] SHLLV_S.QB rd, rt, rs - Shift left logical variable vector quad bytes
13655  *
13656  *   3         2         1
13657  *  10987654321098765432109876543210
13658  *  001000               x1110010101
13659  *     rt -----
13660  *          rs -----
13661  *               rd -----
13662  */
13663 static char *SHLLV_QB(uint64 instruction, Dis_info *info)
13664 {
13665     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13666     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13667     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13668 
13669     const char *rd = GPR(rd_value, info);
13670     const char *rt = GPR(rt_value, info);
13671     const char *rs = GPR(rs_value, info);
13672 
13673     return img_format("SHLLV.QB %s, %s, %s", rd, rt, rs);
13674 }
13675 
13676 
13677 /*
13678  * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair
13679  *   halfwords with saturation
13680  *
13681  *   3         2         1
13682  *  10987654321098765432109876543210
13683  *  001000               11110001101
13684  *     rt -----
13685  *          rs -----
13686  *               rd -----
13687  */
13688 static char *SHLLV_S_PH(uint64 instruction, Dis_info *info)
13689 {
13690     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13691     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13692     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13693 
13694     const char *rd = GPR(rd_value, info);
13695     const char *rt = GPR(rt_value, info);
13696     const char *rs = GPR(rs_value, info);
13697 
13698     return img_format("SHLLV_S.PH %s, %s, %s", rd, rt, rs);
13699 }
13700 
13701 
13702 /*
13703  * [DSP] SHLLV_S.W rd, rt, rs - Shift left logical variable vector word
13704  *
13705  *   3         2         1
13706  *  10987654321098765432109876543210
13707  *  001000               x1111010101
13708  *     rt -----
13709  *          rs -----
13710  *               rd -----
13711  */
13712 static char *SHLLV_S_W(uint64 instruction, Dis_info *info)
13713 {
13714     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13715     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13716     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13717 
13718     const char *rd = GPR(rd_value, info);
13719     const char *rt = GPR(rt_value, info);
13720     const char *rs = GPR(rs_value, info);
13721 
13722     return img_format("SHLLV_S.W %s, %s, %s", rd, rt, rs);
13723 }
13724 
13725 
13726 /*
13727  *
13728  *
13729  *   3         2         1
13730  *  10987654321098765432109876543210
13731  *  001000               01001001101
13732  *     rt -----
13733  *          rs -----
13734  *               rd -----
13735  */
13736 static char *SHRA_PH(uint64 instruction, Dis_info *info)
13737 {
13738     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13739     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13740     uint64 sa_value = extract_sa_15_14_13_12(instruction);
13741 
13742     const char *rt = GPR(rt_value, info);
13743     const char *rs = GPR(rs_value, info);
13744 
13745     return img_format("SHRA.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13746 }
13747 
13748 
13749 /*
13750  *
13751  *
13752  *   3         2         1
13753  *  10987654321098765432109876543210
13754  *  001000               01001001101
13755  *     rt -----
13756  *          rs -----
13757  *               rd -----
13758  */
13759 static char *SHRA_QB(uint64 instruction, Dis_info *info)
13760 {
13761     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13762     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13763     uint64 sa_value = extract_sa_15_14_13(instruction);
13764 
13765     const char *rt = GPR(rt_value, info);
13766     const char *rs = GPR(rs_value, info);
13767 
13768     return img_format("SHRA.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13769 }
13770 
13771 
13772 /*
13773  *
13774  *
13775  *   3         2         1
13776  *  10987654321098765432109876543210
13777  *  001000               01001001101
13778  *     rt -----
13779  *          rs -----
13780  *               rd -----
13781  */
13782 static char *SHRA_R_PH(uint64 instruction, Dis_info *info)
13783 {
13784     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13785     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13786     uint64 sa_value = extract_sa_15_14_13_12(instruction);
13787 
13788     const char *rt = GPR(rt_value, info);
13789     const char *rs = GPR(rs_value, info);
13790 
13791     return img_format("SHRA_R.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13792 }
13793 
13794 
13795 /*
13796  *
13797  *
13798  *   3         2         1
13799  *  10987654321098765432109876543210
13800  *  001000               01001001101
13801  *     rt -----
13802  *          rs -----
13803  *               rd -----
13804  */
13805 static char *SHRA_R_QB(uint64 instruction, Dis_info *info)
13806 {
13807     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13808     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13809     uint64 sa_value = extract_sa_15_14_13(instruction);
13810 
13811     const char *rt = GPR(rt_value, info);
13812     const char *rs = GPR(rs_value, info);
13813 
13814     return img_format("SHRA_R.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13815 }
13816 
13817 
13818 /*
13819  *
13820  *
13821  *   3         2         1
13822  *  10987654321098765432109876543210
13823  *  001000               01001001101
13824  *     rt -----
13825  *          rs -----
13826  *               rd -----
13827  */
13828 static char *SHRA_R_W(uint64 instruction, Dis_info *info)
13829 {
13830     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13831     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13832     uint64 sa_value = extract_sa_15_14_13_12_11(instruction);
13833 
13834     const char *rt = GPR(rt_value, info);
13835     const char *rs = GPR(rs_value, info);
13836 
13837     return img_format("SHRA_R.W %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13838 }
13839 
13840 
13841 /*
13842  *
13843  *
13844  *   3         2         1
13845  *  10987654321098765432109876543210
13846  *  001000               01001001101
13847  *     rt -----
13848  *          rs -----
13849  *               rd -----
13850  */
13851 static char *SHRAV_PH(uint64 instruction, Dis_info *info)
13852 {
13853     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13854     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13855     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13856 
13857     const char *rd = GPR(rd_value, info);
13858     const char *rt = GPR(rt_value, info);
13859     const char *rs = GPR(rs_value, info);
13860 
13861     return img_format("SHRAV.PH %s, %s, %s", rd, rt, rs);
13862 }
13863 
13864 
13865 /*
13866  *
13867  *
13868  *   3         2         1
13869  *  10987654321098765432109876543210
13870  *  001000               01001001101
13871  *     rt -----
13872  *          rs -----
13873  *               rd -----
13874  */
13875 static char *SHRAV_QB(uint64 instruction, Dis_info *info)
13876 {
13877     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13878     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13879     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13880 
13881     const char *rd = GPR(rd_value, info);
13882     const char *rt = GPR(rt_value, info);
13883     const char *rs = GPR(rs_value, info);
13884 
13885     return img_format("SHRAV.QB %s, %s, %s", rd, rt, rs);
13886 }
13887 
13888 
13889 /*
13890  *
13891  *
13892  *   3         2         1
13893  *  10987654321098765432109876543210
13894  *  001000               01001001101
13895  *     rt -----
13896  *          rs -----
13897  *               rd -----
13898  */
13899 static char *SHRAV_R_PH(uint64 instruction, Dis_info *info)
13900 {
13901     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13902     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13903     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13904 
13905     const char *rd = GPR(rd_value, info);
13906     const char *rt = GPR(rt_value, info);
13907     const char *rs = GPR(rs_value, info);
13908 
13909     return img_format("SHRAV_R.PH %s, %s, %s", rd, rt, rs);
13910 }
13911 
13912 
13913 /*
13914  *
13915  *
13916  *   3         2         1
13917  *  10987654321098765432109876543210
13918  *  001000               01001001101
13919  *     rt -----
13920  *          rs -----
13921  *               rd -----
13922  */
13923 static char *SHRAV_R_QB(uint64 instruction, Dis_info *info)
13924 {
13925     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13926     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13927     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13928 
13929     const char *rd = GPR(rd_value, info);
13930     const char *rt = GPR(rt_value, info);
13931     const char *rs = GPR(rs_value, info);
13932 
13933     return img_format("SHRAV_R.QB %s, %s, %s", rd, rt, rs);
13934 }
13935 
13936 
13937 /*
13938  *
13939  *
13940  *   3         2         1
13941  *  10987654321098765432109876543210
13942  *  001000               01001001101
13943  *     rt -----
13944  *          rs -----
13945  *               rd -----
13946  */
13947 static char *SHRAV_R_W(uint64 instruction, Dis_info *info)
13948 {
13949     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13950     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13951     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
13952 
13953     const char *rd = GPR(rd_value, info);
13954     const char *rt = GPR(rt_value, info);
13955     const char *rs = GPR(rs_value, info);
13956 
13957     return img_format("SHRAV_R.W %s, %s, %s", rd, rt, rs);
13958 }
13959 
13960 
13961 /*
13962  * [DSP] SHRL.PH rt, rs, sa - Shift right logical two halfwords
13963  *
13964  *   3         2         1
13965  *  10987654321098765432109876543210
13966  *  001000              001111111111
13967  *     rt -----
13968  *          rs -----
13969  *               sa ----
13970  */
13971 static char *SHRL_PH(uint64 instruction, Dis_info *info)
13972 {
13973     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13974     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13975     uint64 sa_value = extract_sa_15_14_13_12(instruction);
13976 
13977     const char *rt = GPR(rt_value, info);
13978     const char *rs = GPR(rs_value, info);
13979 
13980     return img_format("SHRL.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value);
13981 }
13982 
13983 
13984 /*
13985  * [DSP] SHRL.QB rt, rs, sa - Shift right logical vector quad bytes
13986  *
13987  *   3         2         1
13988  *  10987654321098765432109876543210
13989  *  001000             1100001111111
13990  *     rt -----
13991  *          rs -----
13992  *               sa ---
13993  */
13994 static char *SHRL_QB(uint64 instruction, Dis_info *info)
13995 {
13996     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
13997     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
13998     uint64 sa_value = extract_sa_15_14_13(instruction);
13999 
14000     const char *rt = GPR(rt_value, info);
14001     const char *rs = GPR(rs_value, info);
14002 
14003     return img_format("SHRL.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value);
14004 }
14005 
14006 
14007 /*
14008  * [DSP] SHLLV.PH rd, rt, rs - Shift right logical variable vector pair of
14009  *   halfwords
14010  *
14011  *   3         2         1
14012  *  10987654321098765432109876543210
14013  *  001000               x1100010101
14014  *     rt -----
14015  *          rs -----
14016  *               rd -----
14017  */
14018 static char *SHRLV_PH(uint64 instruction, Dis_info *info)
14019 {
14020     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14021     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14022     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14023 
14024     const char *rd = GPR(rd_value, info);
14025     const char *rt = GPR(rt_value, info);
14026     const char *rs = GPR(rs_value, info);
14027 
14028     return img_format("SHRLV.PH %s, %s, %s", rd, rt, rs);
14029 }
14030 
14031 
14032 /*
14033  * [DSP] SHLLV.QB rd, rt, rs - Shift right logical variable vector quad bytes
14034  *
14035  *   3         2         1
14036  *  10987654321098765432109876543210
14037  *  001000               x1101010101
14038  *     rt -----
14039  *          rs -----
14040  *               rd -----
14041  */
14042 static char *SHRLV_QB(uint64 instruction, Dis_info *info)
14043 {
14044     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14045     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14046     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14047 
14048     const char *rd = GPR(rd_value, info);
14049     const char *rt = GPR(rt_value, info);
14050     const char *rs = GPR(rs_value, info);
14051 
14052     return img_format("SHRLV.QB %s, %s, %s", rd, rt, rs);
14053 }
14054 
14055 
14056 /*
14057  *
14058  *
14059  *   3         2         1
14060  *  10987654321098765432109876543210
14061  *  001000               01001001101
14062  *     rt -----
14063  *          rs -----
14064  *               rd -----
14065  */
14066 static char *SHX(uint64 instruction, Dis_info *info)
14067 {
14068     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14069     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14070     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14071 
14072     const char *rd = GPR(rd_value, info);
14073     const char *rs = GPR(rs_value, info);
14074     const char *rt = GPR(rt_value, info);
14075 
14076     return img_format("SHX %s, %s(%s)", rd, rs, rt);
14077 }
14078 
14079 
14080 /*
14081  *
14082  *
14083  *   3         2         1
14084  *  10987654321098765432109876543210
14085  *  001000               01001001101
14086  *     rt -----
14087  *          rs -----
14088  *               rd -----
14089  */
14090 static char *SHXS(uint64 instruction, Dis_info *info)
14091 {
14092     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14093     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14094     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14095 
14096     const char *rd = GPR(rd_value, info);
14097     const char *rs = GPR(rs_value, info);
14098     const char *rt = GPR(rt_value, info);
14099 
14100     return img_format("SHXS %s, %s(%s)", rd, rs, rt);
14101 }
14102 
14103 
14104 /*
14105  *
14106  *
14107  *   3         2         1
14108  *  10987654321098765432109876543210
14109  *  001000               01001001101
14110  *     rt -----
14111  *          rs -----
14112  *               rd -----
14113  */
14114 static char *SIGRIE(uint64 instruction, Dis_info *info)
14115 {
14116     uint64 code_value = extract_code_18_to_0(instruction);
14117 
14118 
14119     return img_format("SIGRIE 0x%" PRIx64, code_value);
14120 }
14121 
14122 
14123 /*
14124  *
14125  *
14126  *   3         2         1
14127  *  10987654321098765432109876543210
14128  *  001000               01001001101
14129  *     rt -----
14130  *          rs -----
14131  *               rd -----
14132  */
14133 static char *SLL_16_(uint64 instruction, Dis_info *info)
14134 {
14135     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14136     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14137     uint64 shift3_value = extract_shift3_2_1_0(instruction);
14138 
14139     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
14140     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
14141     uint64 shift3 = encode_shift3_from_shift(shift3_value);
14142 
14143     return img_format("SLL %s, %s, 0x%" PRIx64, rt3, rs3, shift3);
14144 }
14145 
14146 
14147 /*
14148  *
14149  *
14150  *   3         2         1
14151  *  10987654321098765432109876543210
14152  *  001000               01001001101
14153  *     rt -----
14154  *          rs -----
14155  *               rd -----
14156  */
14157 static char *SLL_32_(uint64 instruction, Dis_info *info)
14158 {
14159     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14160     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14161     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14162 
14163     const char *rt = GPR(rt_value, info);
14164     const char *rs = GPR(rs_value, info);
14165 
14166     return img_format("SLL %s, %s, 0x%" PRIx64, rt, rs, shift_value);
14167 }
14168 
14169 
14170 /*
14171  *
14172  *
14173  *   3         2         1
14174  *  10987654321098765432109876543210
14175  *  001000               01001001101
14176  *     rt -----
14177  *          rs -----
14178  *               rd -----
14179  */
14180 static char *SLLV(uint64 instruction, Dis_info *info)
14181 {
14182     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14183     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14184     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14185 
14186     const char *rd = GPR(rd_value, info);
14187     const char *rs = GPR(rs_value, info);
14188     const char *rt = GPR(rt_value, info);
14189 
14190     return img_format("SLLV %s, %s, %s", rd, rs, rt);
14191 }
14192 
14193 
14194 /*
14195  *
14196  *
14197  *   3         2         1
14198  *  10987654321098765432109876543210
14199  *  001000               01001001101
14200  *     rt -----
14201  *          rs -----
14202  *               rd -----
14203  */
14204 static char *SLT(uint64 instruction, Dis_info *info)
14205 {
14206     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14207     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14208     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14209 
14210     const char *rd = GPR(rd_value, info);
14211     const char *rs = GPR(rs_value, info);
14212     const char *rt = GPR(rt_value, info);
14213 
14214     return img_format("SLT %s, %s, %s", rd, rs, rt);
14215 }
14216 
14217 
14218 /*
14219  *
14220  *
14221  *   3         2         1
14222  *  10987654321098765432109876543210
14223  *  001000               01001001101
14224  *     rt -----
14225  *          rs -----
14226  *               rd -----
14227  */
14228 static char *SLTI(uint64 instruction, Dis_info *info)
14229 {
14230     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14231     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14232     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
14233 
14234     const char *rt = GPR(rt_value, info);
14235     const char *rs = GPR(rs_value, info);
14236 
14237     return img_format("SLTI %s, %s, 0x%" PRIx64, rt, rs, u_value);
14238 }
14239 
14240 
14241 /*
14242  *
14243  *
14244  *   3         2         1
14245  *  10987654321098765432109876543210
14246  *  001000               01001001101
14247  *     rt -----
14248  *          rs -----
14249  *               rd -----
14250  */
14251 static char *SLTIU(uint64 instruction, Dis_info *info)
14252 {
14253     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14254     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14255     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
14256 
14257     const char *rt = GPR(rt_value, info);
14258     const char *rs = GPR(rs_value, info);
14259 
14260     return img_format("SLTIU %s, %s, 0x%" PRIx64, rt, rs, u_value);
14261 }
14262 
14263 
14264 /*
14265  *
14266  *
14267  *   3         2         1
14268  *  10987654321098765432109876543210
14269  *  001000               01001001101
14270  *     rt -----
14271  *          rs -----
14272  *               rd -----
14273  */
14274 static char *SLTU(uint64 instruction, Dis_info *info)
14275 {
14276     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14277     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14278     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14279 
14280     const char *rd = GPR(rd_value, info);
14281     const char *rs = GPR(rs_value, info);
14282     const char *rt = GPR(rt_value, info);
14283 
14284     return img_format("SLTU %s, %s, %s", rd, rs, rt);
14285 }
14286 
14287 
14288 /*
14289  *
14290  *
14291  *   3         2         1
14292  *  10987654321098765432109876543210
14293  *  001000               01001001101
14294  *     rt -----
14295  *          rs -----
14296  *               rd -----
14297  */
14298 static char *SOV(uint64 instruction, Dis_info *info)
14299 {
14300     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14301     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14302     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14303 
14304     const char *rd = GPR(rd_value, info);
14305     const char *rs = GPR(rs_value, info);
14306     const char *rt = GPR(rt_value, info);
14307 
14308     return img_format("SOV %s, %s, %s", rd, rs, rt);
14309 }
14310 
14311 
14312 /*
14313  *
14314  *
14315  *   3         2         1
14316  *  10987654321098765432109876543210
14317  *  001000               01001001101
14318  *     rt -----
14319  *          rs -----
14320  *               rd -----
14321  */
14322 static char *SPECIAL2(uint64 instruction, Dis_info *info)
14323 {
14324     uint64 op_value = extract_op_25_to_3(instruction);
14325 
14326 
14327     return img_format("SPECIAL2 0x%" PRIx64, op_value);
14328 }
14329 
14330 
14331 /*
14332  *
14333  *
14334  *   3         2         1
14335  *  10987654321098765432109876543210
14336  *  001000               01001001101
14337  *     rt -----
14338  *          rs -----
14339  *               rd -----
14340  */
14341 static char *SQRT_D(uint64 instruction, Dis_info *info)
14342 {
14343     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14344     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14345 
14346     const char *ft = FPR(ft_value, info);
14347     const char *fs = FPR(fs_value, info);
14348 
14349     return img_format("SQRT.D %s, %s", ft, fs);
14350 }
14351 
14352 
14353 /*
14354  *
14355  *
14356  *   3         2         1
14357  *  10987654321098765432109876543210
14358  *  001000               01001001101
14359  *     rt -----
14360  *          rs -----
14361  *               rd -----
14362  */
14363 static char *SQRT_S(uint64 instruction, Dis_info *info)
14364 {
14365     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14366     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14367 
14368     const char *ft = FPR(ft_value, info);
14369     const char *fs = FPR(fs_value, info);
14370 
14371     return img_format("SQRT.S %s, %s", ft, fs);
14372 }
14373 
14374 
14375 /*
14376  * SRA rd, rt, sa - Shift Word Right Arithmetic
14377  *
14378  *   3         2         1
14379  *  10987654321098765432109876543210
14380  *  00000000000               000011
14381  *          rt -----
14382  *               rd -----
14383  *                    sa -----
14384  */
14385 static char *SRA(uint64 instruction, Dis_info *info)
14386 {
14387     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14388     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14389     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14390 
14391     const char *rt = GPR(rt_value, info);
14392     const char *rs = GPR(rs_value, info);
14393 
14394     return img_format("SRA %s, %s, 0x%" PRIx64, rt, rs, shift_value);
14395 }
14396 
14397 
14398 /*
14399  * SRAV rd, rt, rs - Shift Word Right Arithmetic Variable
14400  *
14401  *   3         2         1
14402  *  10987654321098765432109876543210
14403  *  001000               00000000111
14404  *     rs -----
14405  *          rt -----
14406  *               rd -----
14407  */
14408 static char *SRAV(uint64 instruction, Dis_info *info)
14409 {
14410     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14411     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14412     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14413 
14414     const char *rd = GPR(rd_value, info);
14415     const char *rs = GPR(rs_value, info);
14416     const char *rt = GPR(rt_value, info);
14417 
14418     return img_format("SRAV %s, %s, %s", rd, rs, rt);
14419 }
14420 
14421 
14422 /*
14423  *
14424  *
14425  *   3         2         1
14426  *  10987654321098765432109876543210
14427  *  001000               00000000111
14428  *     rs -----
14429  *          rt -----
14430  *               rd -----
14431  */
14432 static char *SRL_16_(uint64 instruction, Dis_info *info)
14433 {
14434     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14435     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14436     uint64 shift3_value = extract_shift3_2_1_0(instruction);
14437 
14438     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
14439     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
14440     uint64 shift3 = encode_shift3_from_shift(shift3_value);
14441 
14442     return img_format("SRL %s, %s, 0x%" PRIx64, rt3, rs3, shift3);
14443 }
14444 
14445 
14446 /*
14447  *
14448  *
14449  *   3         2         1
14450  *  10987654321098765432109876543210
14451  *  001000               01001001101
14452  *     rt -----
14453  *          rs -----
14454  *               rd -----
14455  */
14456 static char *SRL_32_(uint64 instruction, Dis_info *info)
14457 {
14458     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14459     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14460     uint64 shift_value = extract_shift_4_3_2_1_0(instruction);
14461 
14462     const char *rt = GPR(rt_value, info);
14463     const char *rs = GPR(rs_value, info);
14464 
14465     return img_format("SRL %s, %s, 0x%" PRIx64, rt, rs, shift_value);
14466 }
14467 
14468 
14469 /*
14470  *
14471  *
14472  *   3         2         1
14473  *  10987654321098765432109876543210
14474  *  001000               01001001101
14475  *     rt -----
14476  *          rs -----
14477  *               rd -----
14478  */
14479 static char *SRLV(uint64 instruction, Dis_info *info)
14480 {
14481     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14482     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14483     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14484 
14485     const char *rd = GPR(rd_value, info);
14486     const char *rs = GPR(rs_value, info);
14487     const char *rt = GPR(rt_value, info);
14488 
14489     return img_format("SRLV %s, %s, %s", rd, rs, rt);
14490 }
14491 
14492 
14493 /*
14494  *
14495  *
14496  *   3         2         1
14497  *  10987654321098765432109876543210
14498  *  001000               01001001101
14499  *     rt -----
14500  *          rs -----
14501  *               rd -----
14502  */
14503 static char *SUB(uint64 instruction, Dis_info *info)
14504 {
14505     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14506     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14507     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14508 
14509     const char *rd = GPR(rd_value, info);
14510     const char *rs = GPR(rs_value, info);
14511     const char *rt = GPR(rt_value, info);
14512 
14513     return img_format("SUB %s, %s, %s", rd, rs, rt);
14514 }
14515 
14516 
14517 /*
14518  *
14519  *
14520  *   3         2         1
14521  *  10987654321098765432109876543210
14522  *  001000               01001001101
14523  *     rt -----
14524  *          rs -----
14525  *               rd -----
14526  */
14527 static char *SUB_D(uint64 instruction, Dis_info *info)
14528 {
14529     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14530     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14531     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
14532 
14533     const char *fd = FPR(fd_value, info);
14534     const char *fs = FPR(fs_value, info);
14535     const char *ft = FPR(ft_value, info);
14536 
14537     return img_format("SUB.D %s, %s, %s", fd, fs, ft);
14538 }
14539 
14540 
14541 /*
14542  *
14543  *
14544  *   3         2         1
14545  *  10987654321098765432109876543210
14546  *  001000               01001001101
14547  *     rt -----
14548  *          rs -----
14549  *               rd -----
14550  */
14551 static char *SUB_S(uint64 instruction, Dis_info *info)
14552 {
14553     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
14554     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
14555     uint64 fd_value = extract_fd_15_14_13_12_11(instruction);
14556 
14557     const char *fd = FPR(fd_value, info);
14558     const char *fs = FPR(fs_value, info);
14559     const char *ft = FPR(ft_value, info);
14560 
14561     return img_format("SUB.S %s, %s, %s", fd, fs, ft);
14562 }
14563 
14564 
14565 /*
14566  *
14567  *
14568  *   3         2         1
14569  *  10987654321098765432109876543210
14570  *  001000               01001001101
14571  *     rt -----
14572  *          rs -----
14573  *               rd -----
14574  */
14575 static char *SUBQ_PH(uint64 instruction, Dis_info *info)
14576 {
14577     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14578     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14579     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14580 
14581     const char *rd = GPR(rd_value, info);
14582     const char *rs = GPR(rs_value, info);
14583     const char *rt = GPR(rt_value, info);
14584 
14585     return img_format("SUBQ.PH %s, %s, %s", rd, rs, rt);
14586 }
14587 
14588 
14589 /*
14590  * [DSP] SUBQ.S.PH rd, rt, rs - Subtract fractional halfword vectors and shift
14591  *   right to halve results
14592  *
14593  *   3         2         1
14594  *  10987654321098765432109876543210
14595  *  001000               01001001101
14596  *     rt -----
14597  *          rs -----
14598  *               rd -----
14599  */
14600 static char *SUBQ_S_PH(uint64 instruction, Dis_info *info)
14601 {
14602     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14603     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14604     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14605 
14606     const char *rd = GPR(rd_value, info);
14607     const char *rs = GPR(rs_value, info);
14608     const char *rt = GPR(rt_value, info);
14609 
14610     return img_format("SUBQ_S.PH %s, %s, %s", rd, rs, rt);
14611 }
14612 
14613 
14614 /*
14615  * [DSP] SUBQ.S.W rd, rt, rs - Subtract fractional halfword vectors and shift
14616  *   right to halve results
14617  *
14618  *   3         2         1
14619  *  10987654321098765432109876543210
14620  *  001000               01001001101
14621  *     rt -----
14622  *          rs -----
14623  *               rd -----
14624  */
14625 static char *SUBQ_S_W(uint64 instruction, Dis_info *info)
14626 {
14627     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14628     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14629     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14630 
14631     const char *rd = GPR(rd_value, info);
14632     const char *rs = GPR(rs_value, info);
14633     const char *rt = GPR(rt_value, info);
14634 
14635     return img_format("SUBQ_S.W %s, %s, %s", rd, rs, rt);
14636 }
14637 
14638 
14639 /*
14640  * [DSP] SUBQH.PH rd, rt, rs - Subtract fractional halfword vectors and shift
14641  *   right to halve results
14642  *
14643  *   3         2         1
14644  *  10987654321098765432109876543210
14645  *  001000               01001001101
14646  *     rt -----
14647  *          rs -----
14648  *               rd -----
14649  */
14650 static char *SUBQH_PH(uint64 instruction, Dis_info *info)
14651 {
14652     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14653     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14654     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14655 
14656     const char *rd = GPR(rd_value, info);
14657     const char *rs = GPR(rs_value, info);
14658     const char *rt = GPR(rt_value, info);
14659 
14660     return img_format("SUBQH.PH %s, %s, %s", rd, rs, rt);
14661 }
14662 
14663 
14664 /*
14665  * [DSP] SUBQH_R.PH rd, rt, rs - Subtract fractional halfword vectors and shift
14666  *   right to halve results
14667  *
14668  *   3         2         1
14669  *  10987654321098765432109876543210
14670  *  001000               01001001101
14671  *     rt -----
14672  *          rs -----
14673  *               rd -----
14674  */
14675 static char *SUBQH_R_PH(uint64 instruction, Dis_info *info)
14676 {
14677     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14678     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14679     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14680 
14681     const char *rd = GPR(rd_value, info);
14682     const char *rs = GPR(rs_value, info);
14683     const char *rt = GPR(rt_value, info);
14684 
14685     return img_format("SUBQH_R.PH %s, %s, %s", rd, rs, rt);
14686 }
14687 
14688 
14689 /*
14690  * [DSP] SUBQH_R.W rd, rt, rs - Subtract fractional halfword vectors and shift
14691  *   right to halve results with rounding
14692  *
14693  *   3         2         1
14694  *  10987654321098765432109876543210
14695  *  001000               11001001101
14696  *     rt -----
14697  *          rs -----
14698  *               rd -----
14699  */
14700 static char *SUBQH_R_W(uint64 instruction, Dis_info *info)
14701 {
14702     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14703     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14704     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14705 
14706     const char *rd = GPR(rd_value, info);
14707     const char *rs = GPR(rs_value, info);
14708     const char *rt = GPR(rt_value, info);
14709 
14710     return img_format("SUBQH_R.W %s, %s, %s", rd, rs, rt);
14711 }
14712 
14713 
14714 /*
14715  * [DSP] SUBQH.W rd, rs, rt - Subtract fractional words and shift right to
14716  *   halve results
14717  *
14718  *   3         2         1
14719  *  10987654321098765432109876543210
14720  *  001000               01010001101
14721  *     rt -----
14722  *          rs -----
14723  *               rd -----
14724  */
14725 static char *SUBQH_W(uint64 instruction, Dis_info *info)
14726 {
14727     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14728     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14729     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14730 
14731     const char *rd = GPR(rd_value, info);
14732     const char *rs = GPR(rs_value, info);
14733     const char *rt = GPR(rt_value, info);
14734 
14735     return img_format("SUBQH.W %s, %s, %s", rd, rs, rt);
14736 }
14737 
14738 
14739 /*
14740  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14741  *
14742  *   3         2         1
14743  *  10987654321098765432109876543210
14744  *  001000               00010001101
14745  *     rt -----
14746  *          rs -----
14747  *               rd -----
14748  */
14749 static char *SUBU_16_(uint64 instruction, Dis_info *info)
14750 {
14751     uint64 rt3_value = extract_rt3_9_8_7(instruction);
14752     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14753     uint64 rd3_value = extract_rd3_3_2_1(instruction);
14754 
14755     const char *rd3 = GPR(decode_gpr_gpr3(rd3_value, info), info);
14756     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
14757     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
14758 
14759     return img_format("SUBU %s, %s, %s", rd3, rs3, rt3);
14760 }
14761 
14762 
14763 /*
14764  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14765  *
14766  *   3         2         1
14767  *  10987654321098765432109876543210
14768  *  001000               00010001101
14769  *     rt -----
14770  *          rs -----
14771  *               rd -----
14772  */
14773 static char *SUBU_32_(uint64 instruction, Dis_info *info)
14774 {
14775     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14776     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14777     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14778 
14779     const char *rd = GPR(rd_value, info);
14780     const char *rs = GPR(rs_value, info);
14781     const char *rt = GPR(rt_value, info);
14782 
14783     return img_format("SUBU %s, %s, %s", rd, rs, rt);
14784 }
14785 
14786 
14787 /*
14788  * [DSP] SUBU.PH rd, rs, rt - Subtract unsigned unsigned halfwords
14789  *
14790  *   3         2         1
14791  *  10987654321098765432109876543210
14792  *  001000               01100001101
14793  *     rt -----
14794  *          rs -----
14795  *               rd -----
14796  */
14797 static char *SUBU_PH(uint64 instruction, Dis_info *info)
14798 {
14799     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14800     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14801     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14802 
14803     const char *rd = GPR(rd_value, info);
14804     const char *rs = GPR(rs_value, info);
14805     const char *rt = GPR(rt_value, info);
14806 
14807     return img_format("SUBU.PH %s, %s, %s", rd, rs, rt);
14808 }
14809 
14810 
14811 /*
14812  * [DSP] SUBU.QB rd, rs, rt - Subtract unsigned quad byte vectors
14813  *
14814  *   3         2         1
14815  *  10987654321098765432109876543210
14816  *  001000               01011001101
14817  *     rt -----
14818  *          rs -----
14819  *               rd -----
14820  */
14821 static char *SUBU_QB(uint64 instruction, Dis_info *info)
14822 {
14823     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14824     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14825     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14826 
14827     const char *rd = GPR(rd_value, info);
14828     const char *rs = GPR(rs_value, info);
14829     const char *rt = GPR(rt_value, info);
14830 
14831     return img_format("SUBU.QB %s, %s, %s", rd, rs, rt);
14832 }
14833 
14834 
14835 /*
14836  * [DSP] SUBU_S.PH rd, rs, rt - Subtract unsigned unsigned halfwords with
14837  *   8-bit saturation
14838  *
14839  *   3         2         1
14840  *  10987654321098765432109876543210
14841  *  001000               11100001101
14842  *     rt -----
14843  *          rs -----
14844  *               rd -----
14845  */
14846 static char *SUBU_S_PH(uint64 instruction, Dis_info *info)
14847 {
14848     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14849     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14850     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14851 
14852     const char *rd = GPR(rd_value, info);
14853     const char *rs = GPR(rs_value, info);
14854     const char *rt = GPR(rt_value, info);
14855 
14856     return img_format("SUBU_S.PH %s, %s, %s", rd, rs, rt);
14857 }
14858 
14859 
14860 /*
14861  * [DSP] SUBU_S.QB rd, rs, rt - Subtract unsigned quad byte vectors with
14862  *   8-bit saturation
14863  *
14864  *   3         2         1
14865  *  10987654321098765432109876543210
14866  *  001000               11011001101
14867  *     rt -----
14868  *          rs -----
14869  *               rd -----
14870  */
14871 static char *SUBU_S_QB(uint64 instruction, Dis_info *info)
14872 {
14873     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14874     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14875     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14876 
14877     const char *rd = GPR(rd_value, info);
14878     const char *rs = GPR(rs_value, info);
14879     const char *rt = GPR(rt_value, info);
14880 
14881     return img_format("SUBU_S.QB %s, %s, %s", rd, rs, rt);
14882 }
14883 
14884 
14885 /*
14886  * [DSP] SUBUH.QB rd, rs, rt - Subtract unsigned bytes and right shift
14887  *   to halve results
14888  *
14889  *   3         2         1
14890  *  10987654321098765432109876543210
14891  *  001000               01101001101
14892  *     rt -----
14893  *          rs -----
14894  *               rd -----
14895  */
14896 static char *SUBUH_QB(uint64 instruction, Dis_info *info)
14897 {
14898     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14899     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14900     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14901 
14902     const char *rd = GPR(rd_value, info);
14903     const char *rs = GPR(rs_value, info);
14904     const char *rt = GPR(rt_value, info);
14905 
14906     return img_format("SUBUH.QB %s, %s, %s", rd, rs, rt);
14907 }
14908 
14909 
14910 /*
14911  * [DSP] SUBUH_R.QB rd, rs, rt - Subtract unsigned bytes and right shift
14912  *   to halve results with rounding
14913  *
14914  *   3         2         1
14915  *  10987654321098765432109876543210
14916  *  001000               11101001101
14917  *     rt -----
14918  *          rs -----
14919  *               rd -----
14920  */
14921 static char *SUBUH_R_QB(uint64 instruction, Dis_info *info)
14922 {
14923     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
14924     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
14925     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
14926 
14927     const char *rd = GPR(rd_value, info);
14928     const char *rs = GPR(rs_value, info);
14929     const char *rt = GPR(rt_value, info);
14930 
14931     return img_format("SUBUH_R.QB %s, %s, %s", rd, rs, rt);
14932 }
14933 
14934 
14935 /*
14936  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14937  *
14938  *   3         2         1
14939  *  10987654321098765432109876543210
14940  *  001000               00010001101
14941  *     rt -----
14942  *          rs -----
14943  *               rd -----
14944  */
14945 static char *SW_16_(uint64 instruction, Dis_info *info)
14946 {
14947     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
14948     uint64 rs3_value = extract_rs3_6_5_4(instruction);
14949     uint64 u_value = extract_u_3_2_1_0__s2(instruction);
14950 
14951     const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info);
14952     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
14953 
14954     return img_format("SW %s, 0x%" PRIx64 "(%s)", rtz3, u_value, rs3);
14955 }
14956 
14957 
14958 /*
14959  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14960  *
14961  *   3         2         1
14962  *  10987654321098765432109876543210
14963  *  001000               00010001101
14964  *     rt -----
14965  *          rs -----
14966  *               rd -----
14967  */
14968 static char *SW_4X4_(uint64 instruction, Dis_info *info)
14969 {
14970     uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction);
14971     uint64 rs4_value = extract_rs4_4_2_1_0(instruction);
14972     uint64 u_value = extract_u_3_8__s2(instruction);
14973 
14974     const char *rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value, info), info);
14975     const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info);
14976 
14977     return img_format("SW %s, 0x%" PRIx64 "(%s)", rtz4, u_value, rs4);
14978 }
14979 
14980 
14981 /*
14982  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
14983  *
14984  *   3         2         1
14985  *  10987654321098765432109876543210
14986  *  001000               00010001101
14987  *     rt -----
14988  *          rs -----
14989  *               rd -----
14990  */
14991 static char *SW_GP16_(uint64 instruction, Dis_info *info)
14992 {
14993     uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction);
14994     uint64 rtz3_value = extract_rtz3_9_8_7(instruction);
14995 
14996     const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info);
14997 
14998     return img_format("SW %s, 0x%" PRIx64 "($%d)", rtz3, u_value, 28);
14999 }
15000 
15001 
15002 /*
15003  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15004  *
15005  *   3         2         1
15006  *  10987654321098765432109876543210
15007  *  001000               00010001101
15008  *     rt -----
15009  *          rs -----
15010  *               rd -----
15011  */
15012 static char *SW_GP_(uint64 instruction, Dis_info *info)
15013 {
15014     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15015     uint64 u_value = extract_u_20_to_2__s2(instruction);
15016 
15017     const char *rt = GPR(rt_value, info);
15018 
15019     return img_format("SW %s, 0x%" PRIx64 "($%d)", rt, u_value, 28);
15020 }
15021 
15022 
15023 /*
15024  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15025  *
15026  *   3         2         1
15027  *  10987654321098765432109876543210
15028  *  001000               00010001101
15029  *     rt -----
15030  *          rs -----
15031  *               rd -----
15032  */
15033 static char *SW_S9_(uint64 instruction, Dis_info *info)
15034 {
15035     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15036     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15037     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15038 
15039     const char *rt = GPR(rt_value, info);
15040     const char *rs = GPR(rs_value, info);
15041 
15042     return img_format("SW %s, %" PRId64 "(%s)", rt, s_value, rs);
15043 }
15044 
15045 
15046 /*
15047  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15048  *
15049  *   3         2         1
15050  *  10987654321098765432109876543210
15051  *  001000               00010001101
15052  *     rt -----
15053  *          rs -----
15054  *               rd -----
15055  */
15056 static char *SW_SP_(uint64 instruction, Dis_info *info)
15057 {
15058     uint64 rt_value = extract_rt_9_8_7_6_5(instruction);
15059     uint64 u_value = extract_u_4_3_2_1_0__s2(instruction);
15060 
15061     const char *rt = GPR(rt_value, info);
15062 
15063     return img_format("SW %s, 0x%" PRIx64 "($%d)", rt, u_value, 29);
15064 }
15065 
15066 
15067 /*
15068  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15069  *
15070  *   3         2         1
15071  *  10987654321098765432109876543210
15072  *  001000               00010001101
15073  *     rt -----
15074  *          rs -----
15075  *               rd -----
15076  */
15077 static char *SW_U12_(uint64 instruction, Dis_info *info)
15078 {
15079     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15080     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15081     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
15082 
15083     const char *rt = GPR(rt_value, info);
15084     const char *rs = GPR(rs_value, info);
15085 
15086     return img_format("SW %s, 0x%" PRIx64 "(%s)", rt, u_value, rs);
15087 }
15088 
15089 
15090 /*
15091  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15092  *
15093  *   3         2         1
15094  *  10987654321098765432109876543210
15095  *  001000               00010001101
15096  *     rt -----
15097  *          rs -----
15098  *               rd -----
15099  */
15100 static char *SWC1_GP_(uint64 instruction, Dis_info *info)
15101 {
15102     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15103     uint64 u_value = extract_u_17_to_2__s2(instruction);
15104 
15105     const char *ft = FPR(ft_value, info);
15106 
15107     return img_format("SWC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28);
15108 }
15109 
15110 
15111 /*
15112  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15113  *
15114  *   3         2         1
15115  *  10987654321098765432109876543210
15116  *  001000               00010001101
15117  *     rt -----
15118  *          rs -----
15119  *               rd -----
15120  */
15121 static char *SWC1_S9_(uint64 instruction, Dis_info *info)
15122 {
15123     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15124     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15125     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15126 
15127     const char *ft = FPR(ft_value, info);
15128     const char *rs = GPR(rs_value, info);
15129 
15130     return img_format("SWC1 %s, %" PRId64 "(%s)", ft, s_value, rs);
15131 }
15132 
15133 
15134 /*
15135  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15136  *
15137  *   3         2         1
15138  *  10987654321098765432109876543210
15139  *  001000               00010001101
15140  *     rt -----
15141  *          rs -----
15142  *               rd -----
15143  */
15144 static char *SWC1_U12_(uint64 instruction, Dis_info *info)
15145 {
15146     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15147     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15148     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
15149 
15150     const char *ft = FPR(ft_value, info);
15151     const char *rs = GPR(rs_value, info);
15152 
15153     return img_format("SWC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs);
15154 }
15155 
15156 
15157 /*
15158  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15159  *
15160  *   3         2         1
15161  *  10987654321098765432109876543210
15162  *  001000               00010001101
15163  *     rt -----
15164  *          rs -----
15165  *               rd -----
15166  */
15167 static char *SWC1X(uint64 instruction, Dis_info *info)
15168 {
15169     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15170     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15171     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
15172 
15173     const char *ft = FPR(ft_value, info);
15174     const char *rs = GPR(rs_value, info);
15175     const char *rt = GPR(rt_value, info);
15176 
15177     return img_format("SWC1X %s, %s(%s)", ft, rs, rt);
15178 }
15179 
15180 
15181 /*
15182  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15183  *
15184  *   3         2         1
15185  *  10987654321098765432109876543210
15186  *  001000               00010001101
15187  *     rt -----
15188  *          rs -----
15189  *               rd -----
15190  */
15191 static char *SWC1XS(uint64 instruction, Dis_info *info)
15192 {
15193     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15194     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15195     uint64 ft_value = extract_ft_15_14_13_12_11(instruction);
15196 
15197     const char *ft = FPR(ft_value, info);
15198     const char *rs = GPR(rs_value, info);
15199     const char *rt = GPR(rt_value, info);
15200 
15201     return img_format("SWC1XS %s, %s(%s)", ft, rs, rt);
15202 }
15203 
15204 
15205 /*
15206  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15207  *
15208  *   3         2         1
15209  *  10987654321098765432109876543210
15210  *  001000               00010001101
15211  *     rt -----
15212  *          rs -----
15213  *               rd -----
15214  */
15215 static char *SWC2(uint64 instruction, Dis_info *info)
15216 {
15217     uint64 cs_value = extract_cs_25_24_23_22_21(instruction);
15218     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15219     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15220 
15221     const char *rs = GPR(rs_value, info);
15222 
15223     return img_format("SWC2 CP%" PRIu64 ", %" PRId64 "(%s)",
15224                       cs_value, s_value, rs);
15225 }
15226 
15227 
15228 /*
15229  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15230  *
15231  *   3         2         1
15232  *  10987654321098765432109876543210
15233  *  001000               00010001101
15234  *     rt -----
15235  *          rs -----
15236  *               rd -----
15237  */
15238 static char *SWE(uint64 instruction, Dis_info *info)
15239 {
15240     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15241     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15242     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15243 
15244     const char *rt = GPR(rt_value, info);
15245     const char *rs = GPR(rs_value, info);
15246 
15247     return img_format("SWE %s, %" PRId64 "(%s)", rt, s_value, rs);
15248 }
15249 
15250 
15251 /*
15252  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15253  *
15254  *   3         2         1
15255  *  10987654321098765432109876543210
15256  *  001000               00010001101
15257  *     rt -----
15258  *          rs -----
15259  *               rd -----
15260  */
15261 static char *SWM(uint64 instruction, Dis_info *info)
15262 {
15263     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15264     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15265     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15266     uint64 count3_value = extract_count3_14_13_12(instruction);
15267 
15268     const char *rt = GPR(rt_value, info);
15269     const char *rs = GPR(rs_value, info);
15270     uint64 count3 = encode_count3_from_count(count3_value);
15271 
15272     return img_format("SWM %s, %" PRId64 "(%s), 0x%" PRIx64,
15273                       rt, s_value, rs, count3);
15274 }
15275 
15276 
15277 /*
15278  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15279  *
15280  *   3         2         1
15281  *  10987654321098765432109876543210
15282  *  001000               00010001101
15283  *     rt -----
15284  *          rs -----
15285  *               rd -----
15286  */
15287 static char *SWPC_48_(uint64 instruction, Dis_info *info)
15288 {
15289     uint64 rt_value = extract_rt_41_40_39_38_37(instruction);
15290     int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction);
15291 
15292     const char *rt = GPR(rt_value, info);
15293     g_autofree char *s = ADDRESS(s_value, 6, info);
15294 
15295     return img_format("SWPC %s, %s", rt, s);
15296 }
15297 
15298 
15299 /*
15300  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15301  *
15302  *   3         2         1
15303  *  10987654321098765432109876543210
15304  *  001000               00010001101
15305  *     rt -----
15306  *          rs -----
15307  *               rd -----
15308  */
15309 static char *SWX(uint64 instruction, Dis_info *info)
15310 {
15311     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15312     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15313     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15314 
15315     const char *rd = GPR(rd_value, info);
15316     const char *rs = GPR(rs_value, info);
15317     const char *rt = GPR(rt_value, info);
15318 
15319     return img_format("SWX %s, %s(%s)", rd, rs, rt);
15320 }
15321 
15322 
15323 /*
15324  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15325  *
15326  *   3         2         1
15327  *  10987654321098765432109876543210
15328  *  001000               00010001101
15329  *     rt -----
15330  *          rs -----
15331  *               rd -----
15332  */
15333 static char *SWXS(uint64 instruction, Dis_info *info)
15334 {
15335     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15336     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15337     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
15338 
15339     const char *rd = GPR(rd_value, info);
15340     const char *rs = GPR(rs_value, info);
15341     const char *rt = GPR(rt_value, info);
15342 
15343     return img_format("SWXS %s, %s(%s)", rd, rs, rt);
15344 }
15345 
15346 
15347 /*
15348  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15349  *
15350  *   3         2         1
15351  *  10987654321098765432109876543210
15352  *  001000               00010001101
15353  *     rt -----
15354  *          rs -----
15355  *               rd -----
15356  */
15357 static char *SYNC(uint64 instruction, Dis_info *info)
15358 {
15359     uint64 stype_value = extract_stype_20_19_18_17_16(instruction);
15360 
15361 
15362     return img_format("SYNC 0x%" PRIx64, stype_value);
15363 }
15364 
15365 
15366 /*
15367  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15368  *
15369  *   3         2         1
15370  *  10987654321098765432109876543210
15371  *  001000               00010001101
15372  *     rt -----
15373  *          rs -----
15374  *               rd -----
15375  */
15376 static char *SYNCI(uint64 instruction, Dis_info *info)
15377 {
15378     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15379     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15380 
15381     const char *rs = GPR(rs_value, info);
15382 
15383     return img_format("SYNCI %" PRId64 "(%s)", s_value, rs);
15384 }
15385 
15386 
15387 /*
15388  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15389  *
15390  *   3         2         1
15391  *  10987654321098765432109876543210
15392  *  001000               00010001101
15393  *     rt -----
15394  *          rs -----
15395  *               rd -----
15396  */
15397 static char *SYNCIE(uint64 instruction, Dis_info *info)
15398 {
15399     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15400     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15401 
15402     const char *rs = GPR(rs_value, info);
15403 
15404     return img_format("SYNCIE %" PRId64 "(%s)", s_value, rs);
15405 }
15406 
15407 
15408 /*
15409  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15410  *
15411  *   3         2         1
15412  *  10987654321098765432109876543210
15413  *  001000               00010001101
15414  *     rt -----
15415  *          rs -----
15416  *               rd -----
15417  */
15418 static char *SYSCALL_16_(uint64 instruction, Dis_info *info)
15419 {
15420     uint64 code_value = extract_code_1_0(instruction);
15421 
15422 
15423     return img_format("SYSCALL 0x%" PRIx64, code_value);
15424 }
15425 
15426 
15427 /*
15428  * SYSCALL code - System Call. Cause a System Call Exception
15429  *
15430  *   3         2         1
15431  *  10987654321098765432109876543210
15432  *  00000000000010
15433  *           code ------------------
15434  */
15435 static char *SYSCALL_32_(uint64 instruction, Dis_info *info)
15436 {
15437     uint64 code_value = extract_code_17_to_0(instruction);
15438 
15439 
15440     return img_format("SYSCALL 0x%" PRIx64, code_value);
15441 }
15442 
15443 
15444 /*
15445  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15446  *
15447  *   3         2         1
15448  *  10987654321098765432109876543210
15449  *  001000               00010001101
15450  *     rt -----
15451  *          rs -----
15452  *               rd -----
15453  */
15454 static char *TEQ(uint64 instruction, Dis_info *info)
15455 {
15456     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15457     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15458 
15459     const char *rs = GPR(rs_value, info);
15460     const char *rt = GPR(rt_value, info);
15461 
15462     return img_format("TEQ %s, %s", rs, rt);
15463 }
15464 
15465 
15466 /*
15467  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15468  *
15469  *   3         2         1
15470  *  10987654321098765432109876543210
15471  *  001000               00010001101
15472  *     rt -----
15473  *          rs -----
15474  *               rd -----
15475  */
15476 static char *TLBGINV(uint64 instruction, Dis_info *info)
15477 {
15478     (void)instruction;
15479 
15480     return g_strdup("TLBGINV ");
15481 }
15482 
15483 
15484 /*
15485  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15486  *
15487  *   3         2         1
15488  *  10987654321098765432109876543210
15489  *  001000               00010001101
15490  *     rt -----
15491  *          rs -----
15492  *               rd -----
15493  */
15494 static char *TLBGINVF(uint64 instruction, Dis_info *info)
15495 {
15496     (void)instruction;
15497 
15498     return g_strdup("TLBGINVF ");
15499 }
15500 
15501 
15502 /*
15503  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15504  *
15505  *   3         2         1
15506  *  10987654321098765432109876543210
15507  *  001000               00010001101
15508  *     rt -----
15509  *          rs -----
15510  *               rd -----
15511  */
15512 static char *TLBGP(uint64 instruction, Dis_info *info)
15513 {
15514     (void)instruction;
15515 
15516     return g_strdup("TLBGP ");
15517 }
15518 
15519 
15520 /*
15521  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15522  *
15523  *   3         2         1
15524  *  10987654321098765432109876543210
15525  *  001000               00010001101
15526  *     rt -----
15527  *          rs -----
15528  *               rd -----
15529  */
15530 static char *TLBGR(uint64 instruction, Dis_info *info)
15531 {
15532     (void)instruction;
15533 
15534     return g_strdup("TLBGR ");
15535 }
15536 
15537 
15538 /*
15539  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15540  *
15541  *   3         2         1
15542  *  10987654321098765432109876543210
15543  *  001000               00010001101
15544  *     rt -----
15545  *          rs -----
15546  *               rd -----
15547  */
15548 static char *TLBGWI(uint64 instruction, Dis_info *info)
15549 {
15550     (void)instruction;
15551 
15552     return g_strdup("TLBGWI ");
15553 }
15554 
15555 
15556 /*
15557  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15558  *
15559  *   3         2         1
15560  *  10987654321098765432109876543210
15561  *  001000               00010001101
15562  *     rt -----
15563  *          rs -----
15564  *               rd -----
15565  */
15566 static char *TLBGWR(uint64 instruction, Dis_info *info)
15567 {
15568     (void)instruction;
15569 
15570     return g_strdup("TLBGWR ");
15571 }
15572 
15573 
15574 /*
15575  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15576  *
15577  *   3         2         1
15578  *  10987654321098765432109876543210
15579  *  001000               00010001101
15580  *     rt -----
15581  *          rs -----
15582  *               rd -----
15583  */
15584 static char *TLBINV(uint64 instruction, Dis_info *info)
15585 {
15586     (void)instruction;
15587 
15588     return g_strdup("TLBINV ");
15589 }
15590 
15591 
15592 /*
15593  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15594  *
15595  *   3         2         1
15596  *  10987654321098765432109876543210
15597  *  001000               00010001101
15598  *     rt -----
15599  *          rs -----
15600  *               rd -----
15601  */
15602 static char *TLBINVF(uint64 instruction, Dis_info *info)
15603 {
15604     (void)instruction;
15605 
15606     return g_strdup("TLBINVF ");
15607 }
15608 
15609 
15610 /*
15611  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15612  *
15613  *   3         2         1
15614  *  10987654321098765432109876543210
15615  *  001000               00010001101
15616  *     rt -----
15617  *          rs -----
15618  *               rd -----
15619  */
15620 static char *TLBP(uint64 instruction, Dis_info *info)
15621 {
15622     (void)instruction;
15623 
15624     return g_strdup("TLBP ");
15625 }
15626 
15627 
15628 /*
15629  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15630  *
15631  *   3         2         1
15632  *  10987654321098765432109876543210
15633  *  001000               00010001101
15634  *     rt -----
15635  *          rs -----
15636  *               rd -----
15637  */
15638 static char *TLBR(uint64 instruction, Dis_info *info)
15639 {
15640     (void)instruction;
15641 
15642     return g_strdup("TLBR ");
15643 }
15644 
15645 
15646 /*
15647  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15648  *
15649  *   3         2         1
15650  *  10987654321098765432109876543210
15651  *  001000               00010001101
15652  *     rt -----
15653  *          rs -----
15654  *               rd -----
15655  */
15656 static char *TLBWI(uint64 instruction, Dis_info *info)
15657 {
15658     (void)instruction;
15659 
15660     return g_strdup("TLBWI ");
15661 }
15662 
15663 
15664 /*
15665  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15666  *
15667  *   3         2         1
15668  *  10987654321098765432109876543210
15669  *  001000               00010001101
15670  *     rt -----
15671  *          rs -----
15672  *               rd -----
15673  */
15674 static char *TLBWR(uint64 instruction, Dis_info *info)
15675 {
15676     (void)instruction;
15677 
15678     return g_strdup("TLBWR ");
15679 }
15680 
15681 
15682 /*
15683  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15684  *
15685  *   3         2         1
15686  *  10987654321098765432109876543210
15687  *  001000               00010001101
15688  *     rt -----
15689  *          rs -----
15690  *               rd -----
15691  */
15692 static char *TNE(uint64 instruction, Dis_info *info)
15693 {
15694     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15695     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15696 
15697     const char *rs = GPR(rs_value, info);
15698     const char *rt = GPR(rt_value, info);
15699 
15700     return img_format("TNE %s, %s", rs, rt);
15701 }
15702 
15703 
15704 /*
15705  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15706  *
15707  *   3         2         1
15708  *  10987654321098765432109876543210
15709  *  001000               00010001101
15710  *     rt -----
15711  *          rs -----
15712  *               rd -----
15713  */
15714 static char *TRUNC_L_D(uint64 instruction, Dis_info *info)
15715 {
15716     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15717     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15718 
15719     const char *ft = FPR(ft_value, info);
15720     const char *fs = FPR(fs_value, info);
15721 
15722     return img_format("TRUNC.L.D %s, %s", ft, fs);
15723 }
15724 
15725 
15726 /*
15727  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15728  *
15729  *   3         2         1
15730  *  10987654321098765432109876543210
15731  *  001000               00010001101
15732  *     rt -----
15733  *          rs -----
15734  *               rd -----
15735  */
15736 static char *TRUNC_L_S(uint64 instruction, Dis_info *info)
15737 {
15738     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15739     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15740 
15741     const char *ft = FPR(ft_value, info);
15742     const char *fs = FPR(fs_value, info);
15743 
15744     return img_format("TRUNC.L.S %s, %s", ft, fs);
15745 }
15746 
15747 
15748 /*
15749  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15750  *
15751  *   3         2         1
15752  *  10987654321098765432109876543210
15753  *  001000               00010001101
15754  *     rt -----
15755  *          rs -----
15756  *               rd -----
15757  */
15758 static char *TRUNC_W_D(uint64 instruction, Dis_info *info)
15759 {
15760     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15761     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15762 
15763     const char *ft = FPR(ft_value, info);
15764     const char *fs = FPR(fs_value, info);
15765 
15766     return img_format("TRUNC.W.D %s, %s", ft, fs);
15767 }
15768 
15769 
15770 /*
15771  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15772  *
15773  *   3         2         1
15774  *  10987654321098765432109876543210
15775  *  001000               00010001101
15776  *     rt -----
15777  *          rs -----
15778  *               rd -----
15779  */
15780 static char *TRUNC_W_S(uint64 instruction, Dis_info *info)
15781 {
15782     uint64 ft_value = extract_ft_25_24_23_22_21(instruction);
15783     uint64 fs_value = extract_fs_20_19_18_17_16(instruction);
15784 
15785     const char *ft = FPR(ft_value, info);
15786     const char *fs = FPR(fs_value, info);
15787 
15788     return img_format("TRUNC.W.S %s, %s", ft, fs);
15789 }
15790 
15791 
15792 /*
15793  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15794  *
15795  *   3         2         1
15796  *  10987654321098765432109876543210
15797  *  001000               00010001101
15798  *     rt -----
15799  *          rs -----
15800  *               rd -----
15801  */
15802 static char *UALDM(uint64 instruction, Dis_info *info)
15803 {
15804     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15805     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15806     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15807     uint64 count3_value = extract_count3_14_13_12(instruction);
15808 
15809     const char *rt = GPR(rt_value, info);
15810     const char *rs = GPR(rs_value, info);
15811     uint64 count3 = encode_count3_from_count(count3_value);
15812 
15813     return img_format("UALDM %s, %" PRId64 "(%s), 0x%" PRIx64,
15814                       rt, s_value, rs, count3);
15815 }
15816 
15817 
15818 /*
15819  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15820  *
15821  *   3         2         1
15822  *  10987654321098765432109876543210
15823  *  001000               00010001101
15824  *     rt -----
15825  *          rs -----
15826  *               rd -----
15827  */
15828 static char *UALH(uint64 instruction, Dis_info *info)
15829 {
15830     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15831     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15832     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15833 
15834     const char *rt = GPR(rt_value, info);
15835     const char *rs = GPR(rs_value, info);
15836 
15837     return img_format("UALH %s, %" PRId64 "(%s)", rt, s_value, rs);
15838 }
15839 
15840 
15841 /*
15842  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15843  *
15844  *   3         2         1
15845  *  10987654321098765432109876543210
15846  *  001000               00010001101
15847  *     rt -----
15848  *          rs -----
15849  *               rd -----
15850  */
15851 static char *UALWM(uint64 instruction, Dis_info *info)
15852 {
15853     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15854     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15855     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15856     uint64 count3_value = extract_count3_14_13_12(instruction);
15857 
15858     const char *rt = GPR(rt_value, info);
15859     const char *rs = GPR(rs_value, info);
15860     uint64 count3 = encode_count3_from_count(count3_value);
15861 
15862     return img_format("UALWM %s, %" PRId64 "(%s), 0x%" PRIx64,
15863                       rt, s_value, rs, count3);
15864 }
15865 
15866 
15867 /*
15868  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15869  *
15870  *   3         2         1
15871  *  10987654321098765432109876543210
15872  *  001000               00010001101
15873  *     rt -----
15874  *          rs -----
15875  *               rd -----
15876  */
15877 static char *UASDM(uint64 instruction, Dis_info *info)
15878 {
15879     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15880     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15881     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15882     uint64 count3_value = extract_count3_14_13_12(instruction);
15883 
15884     const char *rt = GPR(rt_value, info);
15885     const char *rs = GPR(rs_value, info);
15886     uint64 count3 = encode_count3_from_count(count3_value);
15887 
15888     return img_format("UASDM %s, %" PRId64 "(%s), 0x%" PRIx64,
15889                       rt, s_value, rs, count3);
15890 }
15891 
15892 
15893 /*
15894  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15895  *
15896  *   3         2         1
15897  *  10987654321098765432109876543210
15898  *  001000               00010001101
15899  *     rt -----
15900  *          rs -----
15901  *               rd -----
15902  */
15903 static char *UASH(uint64 instruction, Dis_info *info)
15904 {
15905     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15906     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15907     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15908 
15909     const char *rt = GPR(rt_value, info);
15910     const char *rs = GPR(rs_value, info);
15911 
15912     return img_format("UASH %s, %" PRId64 "(%s)", rt, s_value, rs);
15913 }
15914 
15915 
15916 /*
15917  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15918  *
15919  *   3         2         1
15920  *  10987654321098765432109876543210
15921  *  001000               00010001101
15922  *     rt -----
15923  *          rs -----
15924  *               rd -----
15925  */
15926 static char *UASWM(uint64 instruction, Dis_info *info)
15927 {
15928     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15929     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
15930     int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction);
15931     uint64 count3_value = extract_count3_14_13_12(instruction);
15932 
15933     const char *rt = GPR(rt_value, info);
15934     const char *rs = GPR(rs_value, info);
15935     uint64 count3 = encode_count3_from_count(count3_value);
15936 
15937     return img_format("UASWM %s, %" PRId64 "(%s), 0x%" PRIx64,
15938                       rt, s_value, rs, count3);
15939 }
15940 
15941 
15942 /*
15943  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
15944  *
15945  *   3         2         1
15946  *  10987654321098765432109876543210
15947  *  001000               00010001101
15948  *     rt -----
15949  *          rs -----
15950  *               rd -----
15951  */
15952 static char *UDI(uint64 instruction, Dis_info *info)
15953 {
15954     uint64 op_value = extract_op_25_to_3(instruction);
15955 
15956 
15957     return img_format("UDI 0x%" PRIx64, op_value);
15958 }
15959 
15960 
15961 /*
15962  * WAIT code - Enter Wait State
15963  *
15964  *   3         2         1
15965  *  10987654321098765432109876543210
15966  *  001000          1100001101111111
15967  *   code ----------
15968  */
15969 static char *WAIT(uint64 instruction, Dis_info *info)
15970 {
15971     uint64 code_value = extract_code_25_24_23_22_21_20_19_18_17_16(instruction);
15972 
15973 
15974     return img_format("WAIT 0x%" PRIx64, code_value);
15975 }
15976 
15977 
15978 /*
15979  * [DSP] WRDSP rt, mask - Write selected fields from a GPR to the DSPControl
15980  *         register
15981  *
15982  *   3         2         1
15983  *  10987654321098765432109876543210
15984  *  001000            01011001111111
15985  *     rt -----
15986  *        mask -------
15987  */
15988 static char *WRDSP(uint64 instruction, Dis_info *info)
15989 {
15990     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
15991     uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction);
15992 
15993     const char *rt = GPR(rt_value, info);
15994 
15995     return img_format("WRDSP %s, 0x%" PRIx64, rt, mask_value);
15996 }
15997 
15998 
15999 /*
16000  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16001  *
16002  *   3         2         1
16003  *  10987654321098765432109876543210
16004  *  001000               00010001101
16005  *     rt -----
16006  *          rs -----
16007  *               rd -----
16008  */
16009 static char *WRPGPR(uint64 instruction, Dis_info *info)
16010 {
16011     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16012     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16013 
16014     const char *rt = GPR(rt_value, info);
16015     const char *rs = GPR(rs_value, info);
16016 
16017     return img_format("WRPGPR %s, %s", rt, rs);
16018 }
16019 
16020 
16021 /*
16022  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16023  *
16024  *   3         2         1
16025  *  10987654321098765432109876543210
16026  *  001000               00010001101
16027  *     rt -----
16028  *          rs -----
16029  *               rd -----
16030  */
16031 static char *XOR_16_(uint64 instruction, Dis_info *info)
16032 {
16033     uint64 rt3_value = extract_rt3_9_8_7(instruction);
16034     uint64 rs3_value = extract_rs3_6_5_4(instruction);
16035 
16036     const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info);
16037     const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info);
16038 
16039     return img_format("XOR %s, %s", rs3, rt3);
16040 }
16041 
16042 
16043 /*
16044  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16045  *
16046  *   3         2         1
16047  *  10987654321098765432109876543210
16048  *  001000               00010001101
16049  *     rt -----
16050  *          rs -----
16051  *               rd -----
16052  */
16053 static char *XOR_32_(uint64 instruction, Dis_info *info)
16054 {
16055     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16056     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16057     uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
16058 
16059     const char *rd = GPR(rd_value, info);
16060     const char *rs = GPR(rs_value, info);
16061     const char *rt = GPR(rt_value, info);
16062 
16063     return img_format("XOR %s, %s, %s", rd, rs, rt);
16064 }
16065 
16066 
16067 /*
16068  * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results
16069  *
16070  *   3         2         1
16071  *  10987654321098765432109876543210
16072  *  001000               00010001101
16073  *     rt -----
16074  *          rs -----
16075  *               rd -----
16076  */
16077 static char *XORI(uint64 instruction, Dis_info *info)
16078 {
16079     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16080     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16081     uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction);
16082 
16083     const char *rt = GPR(rt_value, info);
16084     const char *rs = GPR(rs_value, info);
16085 
16086     return img_format("XORI %s, %s, 0x%" PRIx64, rt, rs, u_value);
16087 }
16088 
16089 
16090 /*
16091  * YIELD rt, rs -
16092  *
16093  *   3         2         1
16094  *  10987654321098765432109876543210
16095  *  001000               00010001101
16096  *     rt -----
16097  *          rs -----
16098  */
16099 static char *YIELD(uint64 instruction, Dis_info *info)
16100 {
16101     uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
16102     uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
16103 
16104     const char *rt = GPR(rt_value, info);
16105     const char *rs = GPR(rs_value, info);
16106 
16107     return img_format("YIELD %s, %s", rt, rs);
16108 }
16109 
16110 
16111 
16112 /*
16113  *                nanoMIPS instruction pool organization
16114  *                ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
16115  *
16116  *
16117  *                 ┌─ P.ADDIU ─── P.RI ─── P.SYSCALL
16118  *                 │
16119  *                 │                                      ┌─ P.TRAP
16120  *                 │                                      │
16121  *                 │                      ┌─ _POOL32A0_0 ─┼─ P.CMOVE
16122  *                 │                      │               │
16123  *                 │                      │               └─ P.SLTU
16124  *                 │        ┌─ _POOL32A0 ─┤
16125  *                 │        │             │
16126  *                 │        │             │
16127  *                 │        │             └─ _POOL32A0_1 ─── CRC32
16128  *                 │        │
16129  *                 ├─ P32A ─┤
16130  *                 │        │                           ┌─ PP.LSX
16131  *                 │        │             ┌─ P.LSX ─────┤
16132  *                 │        │             │             └─ PP.LSXS
16133  *                 │        └─ _POOL32A7 ─┤
16134  *                 │                      │             ┌─ POOL32Axf_4
16135  *                 │                      └─ POOL32Axf ─┤
16136  *                 │                                    └─ POOL32Axf_5
16137  *                 │
16138  *                 ├─ PBAL
16139  *                 │
16140  *                 ├─ P.GP.W   ┌─ PP.LSX
16141  *         ┌─ P32 ─┤           │
16142  *         │       ├─ P.GP.BH ─┴─ PP.LSXS
16143  *         │       │
16144  *         │       ├─ P.J ─────── PP.BALRSC
16145  *         │       │
16146  *         │       ├─ P48I
16147  *         │       │           ┌─ P.SR
16148  *         │       │           │
16149  *         │       │           ├─ P.SHIFT
16150  *         │       │           │
16151  *         │       ├─ P.U12 ───┼─ P.ROTX
16152  *         │       │           │
16153  *         │       │           ├─ P.INS
16154  *         │       │           │
16155  *         │       │           └─ P.EXT
16156  *         │       │
16157  *         │       ├─ P.LS.U12 ── P.PREF.U12
16158  *         │       │
16159  *         │       ├─ P.BR1 ───── P.BR3A
16160  *         │       │
16161  *         │       │           ┌─ P.LS.S0 ─── P16.SYSCALL
16162  *         │       │           │
16163  *         │       │           │           ┌─ P.LL
16164  *         │       │           ├─ P.LS.S1 ─┤
16165  *         │       │           │           └─ P.SC
16166  *         │       │           │
16167  *         │       │           │           ┌─ P.PREFE
16168  *  MAJOR ─┤       ├─ P.LS.S9 ─┤           │
16169  *         │       │           ├─ P.LS.E0 ─┼─ P.LLE
16170  *         │       │           │           │
16171  *         │       │           │           └─ P.SCE
16172  *         │       │           │
16173  *         │       │           ├─ P.LS.WM
16174  *         │       │           │
16175  *         │       │           └─ P.LS.UAWM
16176  *         │       │
16177  *         │       │
16178  *         │       ├─ P.BR2
16179  *         │       │
16180  *         │       ├─ P.BRI
16181  *         │       │
16182  *         │       └─ P.LUI
16183  *         │
16184  *         │
16185  *         │       ┌─ P16.MV ──── P16.RI ─── P16.SYSCALL
16186  *         │       │
16187  *         │       ├─ P16.SR
16188  *         │       │
16189  *         │       ├─ P16.SHIFT
16190  *         │       │
16191  *         │       ├─ P16.4x4
16192  *         │       │
16193  *         │       ├─ P16C ────── POOL16C_0 ── POOL16C_00
16194  *         │       │
16195  *         └─ P16 ─┼─ P16.LB
16196  *                 │
16197  *                 ├─ P16.A1
16198  *                 │
16199  *                 ├─ P16.LH
16200  *                 │
16201  *                 ├─ P16.A2 ──── P.ADDIU[RS5]
16202  *                 │
16203  *                 ├─ P16.ADDU
16204  *                 │
16205  *                 └─ P16.BR ──┬─ P16.JRC
16206  *                             │
16207  *                             └─ P16.BR1
16208  *
16209  *
16210  *  (FP, DPS, and some minor instruction pools are omitted from the diagram)
16211  *
16212  */
16213 
16214 static const Pool P_SYSCALL[2] = {
16215     { instruction         , 0                   , 0   , 32,
16216        0xfffc0000, 0x00080000, &SYSCALL_32_      , 0,
16217        0x0                 },        /* SYSCALL[32] */
16218     { instruction         , 0                   , 0   , 32,
16219        0xfffc0000, 0x000c0000, &HYPCALL          , 0,
16220        CP0_ | VZ_          },        /* HYPCALL */
16221 };
16222 
16223 
16224 static const Pool P_RI[4] = {
16225     { instruction         , 0                   , 0   , 32,
16226        0xfff80000, 0x00000000, &SIGRIE           , 0,
16227        0x0                 },        /* SIGRIE */
16228     { pool                , P_SYSCALL           , 2   , 32,
16229        0xfff80000, 0x00080000, 0                      , 0,
16230        0x0                 },        /* P.SYSCALL */
16231     { instruction         , 0                   , 0   , 32,
16232        0xfff80000, 0x00100000, &BREAK_32_        , 0,
16233        0x0                 },        /* BREAK[32] */
16234     { instruction         , 0                   , 0   , 32,
16235        0xfff80000, 0x00180000, &SDBBP_32_        , 0,
16236        EJTAG_              },        /* SDBBP[32] */
16237 };
16238 
16239 
16240 static const Pool P_ADDIU[2] = {
16241     { pool                , P_RI                , 4   , 32,
16242        0xffe00000, 0x00000000, 0                      , 0,
16243        0x0                 },        /* P.RI */
16244     { instruction         , 0                   , 0   , 32,
16245        0xfc000000, 0x00000000, &ADDIU_32_        , &ADDIU_32__cond   ,
16246        0x0                 },        /* ADDIU[32] */
16247 };
16248 
16249 
16250 static const Pool P_TRAP[2] = {
16251     { instruction         , 0                   , 0   , 32,
16252        0xfc0007ff, 0x20000000, &TEQ              , 0,
16253        XMMS_               },        /* TEQ */
16254     { instruction         , 0                   , 0   , 32,
16255        0xfc0007ff, 0x20000400, &TNE              , 0,
16256        XMMS_               },        /* TNE */
16257 };
16258 
16259 
16260 static const Pool P_CMOVE[2] = {
16261     { instruction         , 0                   , 0   , 32,
16262        0xfc0007ff, 0x20000210, &MOVZ             , 0,
16263        0x0                 },        /* MOVZ */
16264     { instruction         , 0                   , 0   , 32,
16265        0xfc0007ff, 0x20000610, &MOVN             , 0,
16266        0x0                 },        /* MOVN */
16267 };
16268 
16269 
16270 static const Pool P_D_MT_VPE[2] = {
16271     { instruction         , 0                   , 0   , 32,
16272        0xfc1f3fff, 0x20010ab0, &DMT              , 0,
16273        MT_                 },        /* DMT */
16274     { instruction         , 0                   , 0   , 32,
16275        0xfc1f3fff, 0x20000ab0, &DVPE             , 0,
16276        MT_                 },        /* DVPE */
16277 };
16278 
16279 
16280 static const Pool P_E_MT_VPE[2] = {
16281     { instruction         , 0                   , 0   , 32,
16282        0xfc1f3fff, 0x20010eb0, &EMT              , 0,
16283        MT_                 },        /* EMT */
16284     { instruction         , 0                   , 0   , 32,
16285        0xfc1f3fff, 0x20000eb0, &EVPE             , 0,
16286        MT_                 },        /* EVPE */
16287 };
16288 
16289 
16290 static const Pool _P_MT_VPE[2] = {
16291     { pool                , P_D_MT_VPE          , 2   , 32,
16292        0xfc003fff, 0x20000ab0, 0                      , 0,
16293        0x0                 },        /* P.D_MT_VPE */
16294     { pool                , P_E_MT_VPE          , 2   , 32,
16295        0xfc003fff, 0x20000eb0, 0                      , 0,
16296        0x0                 },        /* P.E_MT_VPE */
16297 };
16298 
16299 
16300 static const Pool P_MT_VPE[8] = {
16301     { reserved_block      , 0                   , 0   , 32,
16302        0xfc003bff, 0x200002b0, 0                      , 0,
16303        0x0                 },        /* P.MT_VPE~*(0) */
16304     { pool                , _P_MT_VPE           , 2   , 32,
16305        0xfc003bff, 0x20000ab0, 0                      , 0,
16306        0x0                 },        /* _P.MT_VPE */
16307     { reserved_block      , 0                   , 0   , 32,
16308        0xfc003bff, 0x200012b0, 0                      , 0,
16309        0x0                 },        /* P.MT_VPE~*(2) */
16310     { reserved_block      , 0                   , 0   , 32,
16311        0xfc003bff, 0x20001ab0, 0                      , 0,
16312        0x0                 },        /* P.MT_VPE~*(3) */
16313     { reserved_block      , 0                   , 0   , 32,
16314        0xfc003bff, 0x200022b0, 0                      , 0,
16315        0x0                 },        /* P.MT_VPE~*(4) */
16316     { reserved_block      , 0                   , 0   , 32,
16317        0xfc003bff, 0x20002ab0, 0                      , 0,
16318        0x0                 },        /* P.MT_VPE~*(5) */
16319     { reserved_block      , 0                   , 0   , 32,
16320        0xfc003bff, 0x200032b0, 0                      , 0,
16321        0x0                 },        /* P.MT_VPE~*(6) */
16322     { reserved_block      , 0                   , 0   , 32,
16323        0xfc003bff, 0x20003ab0, 0                      , 0,
16324        0x0                 },        /* P.MT_VPE~*(7) */
16325 };
16326 
16327 
16328 static const Pool P_DVP[2] = {
16329     { instruction         , 0                   , 0   , 32,
16330        0xfc00ffff, 0x20000390, &DVP              , 0,
16331        0x0                 },        /* DVP */
16332     { instruction         , 0                   , 0   , 32,
16333        0xfc00ffff, 0x20000790, &EVP              , 0,
16334        0x0                 },        /* EVP */
16335 };
16336 
16337 
16338 static const Pool P_SLTU[2] = {
16339     { pool                , P_DVP               , 2   , 32,
16340        0xfc00fbff, 0x20000390, 0                      , 0,
16341        0x0                 },        /* P.DVP */
16342     { instruction         , 0                   , 0   , 32,
16343        0xfc0003ff, 0x20000390, &SLTU             , &SLTU_cond        ,
16344        0x0                 },        /* SLTU */
16345 };
16346 
16347 
16348 static const Pool _POOL32A0[128] = {
16349     { pool                , P_TRAP              , 2   , 32,
16350        0xfc0003ff, 0x20000000, 0                      , 0,
16351        0x0                 },        /* P.TRAP */
16352     { instruction         , 0                   , 0   , 32,
16353        0xfc0003ff, 0x20000008, &SEB              , 0,
16354        XMMS_               },        /* SEB */
16355     { instruction         , 0                   , 0   , 32,
16356        0xfc0003ff, 0x20000010, &SLLV             , 0,
16357        0x0                 },        /* SLLV */
16358     { instruction         , 0                   , 0   , 32,
16359        0xfc0003ff, 0x20000018, &MUL_32_          , 0,
16360        0x0                 },        /* MUL[32] */
16361     { reserved_block      , 0                   , 0   , 32,
16362        0xfc0003ff, 0x20000020, 0                      , 0,
16363        0x0                 },        /* _POOL32A0~*(4) */
16364     { reserved_block      , 0                   , 0   , 32,
16365        0xfc0003ff, 0x20000028, 0                      , 0,
16366        0x0                 },        /* _POOL32A0~*(5) */
16367     { instruction         , 0                   , 0   , 32,
16368        0xfc0003ff, 0x20000030, &MFC0             , 0,
16369        0x0                 },        /* MFC0 */
16370     { instruction         , 0                   , 0   , 32,
16371        0xfc0003ff, 0x20000038, &MFHC0            , 0,
16372        CP0_ | MVH_         },        /* MFHC0 */
16373     { reserved_block      , 0                   , 0   , 32,
16374        0xfc0003ff, 0x20000040, 0                      , 0,
16375        0x0                 },        /* _POOL32A0~*(8) */
16376     { instruction         , 0                   , 0   , 32,
16377        0xfc0003ff, 0x20000048, &SEH              , 0,
16378        0x0                 },        /* SEH */
16379     { instruction         , 0                   , 0   , 32,
16380        0xfc0003ff, 0x20000050, &SRLV             , 0,
16381        0x0                 },        /* SRLV */
16382     { instruction         , 0                   , 0   , 32,
16383        0xfc0003ff, 0x20000058, &MUH              , 0,
16384        0x0                 },        /* MUH */
16385     { reserved_block      , 0                   , 0   , 32,
16386        0xfc0003ff, 0x20000060, 0                      , 0,
16387        0x0                 },        /* _POOL32A0~*(12) */
16388     { reserved_block      , 0                   , 0   , 32,
16389        0xfc0003ff, 0x20000068, 0                      , 0,
16390        0x0                 },        /* _POOL32A0~*(13) */
16391     { instruction         , 0                   , 0   , 32,
16392        0xfc0003ff, 0x20000070, &MTC0             , 0,
16393        CP0_                },        /* MTC0 */
16394     { instruction         , 0                   , 0   , 32,
16395        0xfc0003ff, 0x20000078, &MTHC0            , 0,
16396        CP0_ | MVH_         },        /* MTHC0 */
16397     { reserved_block      , 0                   , 0   , 32,
16398        0xfc0003ff, 0x20000080, 0                      , 0,
16399        0x0                 },        /* _POOL32A0~*(16) */
16400     { reserved_block      , 0                   , 0   , 32,
16401        0xfc0003ff, 0x20000088, 0                      , 0,
16402        0x0                 },        /* _POOL32A0~*(17) */
16403     { instruction         , 0                   , 0   , 32,
16404        0xfc0003ff, 0x20000090, &SRAV             , 0,
16405        0x0                 },        /* SRAV */
16406     { instruction         , 0                   , 0   , 32,
16407        0xfc0003ff, 0x20000098, &MULU             , 0,
16408        0x0                 },        /* MULU */
16409     { reserved_block      , 0                   , 0   , 32,
16410        0xfc0003ff, 0x200000a0, 0                      , 0,
16411        0x0                 },        /* _POOL32A0~*(20) */
16412     { reserved_block      , 0                   , 0   , 32,
16413        0xfc0003ff, 0x200000a8, 0                      , 0,
16414        0x0                 },        /* _POOL32A0~*(21) */
16415     { instruction         , 0                   , 0   , 32,
16416        0xfc0003ff, 0x200000b0, &MFGC0            , 0,
16417        CP0_ | VZ_          },        /* MFGC0 */
16418     { instruction         , 0                   , 0   , 32,
16419        0xfc0003ff, 0x200000b8, &MFHGC0           , 0,
16420        CP0_ | VZ_ | MVH_   },        /* MFHGC0 */
16421     { reserved_block      , 0                   , 0   , 32,
16422        0xfc0003ff, 0x200000c0, 0                      , 0,
16423        0x0                 },        /* _POOL32A0~*(24) */
16424     { reserved_block      , 0                   , 0   , 32,
16425        0xfc0003ff, 0x200000c8, 0                      , 0,
16426        0x0                 },        /* _POOL32A0~*(25) */
16427     { instruction         , 0                   , 0   , 32,
16428        0xfc0003ff, 0x200000d0, &ROTRV            , 0,
16429        0x0                 },        /* ROTRV */
16430     { instruction         , 0                   , 0   , 32,
16431        0xfc0003ff, 0x200000d8, &MUHU             , 0,
16432        0x0                 },        /* MUHU */
16433     { reserved_block      , 0                   , 0   , 32,
16434        0xfc0003ff, 0x200000e0, 0                      , 0,
16435        0x0                 },        /* _POOL32A0~*(28) */
16436     { reserved_block      , 0                   , 0   , 32,
16437        0xfc0003ff, 0x200000e8, 0                      , 0,
16438        0x0                 },        /* _POOL32A0~*(29) */
16439     { instruction         , 0                   , 0   , 32,
16440        0xfc0003ff, 0x200000f0, &MTGC0            , 0,
16441        CP0_ | VZ_          },        /* MTGC0 */
16442     { instruction         , 0                   , 0   , 32,
16443        0xfc0003ff, 0x200000f8, &MTHGC0           , 0,
16444        CP0_ | VZ_ | MVH_   },        /* MTHGC0 */
16445     { reserved_block      , 0                   , 0   , 32,
16446        0xfc0003ff, 0x20000100, 0                      , 0,
16447        0x0                 },        /* _POOL32A0~*(32) */
16448     { reserved_block      , 0                   , 0   , 32,
16449        0xfc0003ff, 0x20000108, 0                      , 0,
16450        0x0                 },        /* _POOL32A0~*(33) */
16451     { instruction         , 0                   , 0   , 32,
16452        0xfc0003ff, 0x20000110, &ADD              , 0,
16453        XMMS_               },        /* ADD */
16454     { instruction         , 0                   , 0   , 32,
16455        0xfc0003ff, 0x20000118, &DIV              , 0,
16456        0x0                 },        /* DIV */
16457     { reserved_block      , 0                   , 0   , 32,
16458        0xfc0003ff, 0x20000120, 0                      , 0,
16459        0x0                 },        /* _POOL32A0~*(36) */
16460     { reserved_block      , 0                   , 0   , 32,
16461        0xfc0003ff, 0x20000128, 0                      , 0,
16462        0x0                 },        /* _POOL32A0~*(37) */
16463     { instruction         , 0                   , 0   , 32,
16464        0xfc0003ff, 0x20000130, &DMFC0            , 0,
16465        CP0_ | MIPS64_      },        /* DMFC0 */
16466     { reserved_block      , 0                   , 0   , 32,
16467        0xfc0003ff, 0x20000138, 0                      , 0,
16468        0x0                 },        /* _POOL32A0~*(39) */
16469     { reserved_block      , 0                   , 0   , 32,
16470        0xfc0003ff, 0x20000140, 0                      , 0,
16471        0x0                 },        /* _POOL32A0~*(40) */
16472     { reserved_block      , 0                   , 0   , 32,
16473        0xfc0003ff, 0x20000148, 0                      , 0,
16474        0x0                 },        /* _POOL32A0~*(41) */
16475     { instruction         , 0                   , 0   , 32,
16476        0xfc0003ff, 0x20000150, &ADDU_32_         , 0,
16477        0x0                 },        /* ADDU[32] */
16478     { instruction         , 0                   , 0   , 32,
16479        0xfc0003ff, 0x20000158, &MOD              , 0,
16480        0x0                 },        /* MOD */
16481     { reserved_block      , 0                   , 0   , 32,
16482        0xfc0003ff, 0x20000160, 0                      , 0,
16483        0x0                 },        /* _POOL32A0~*(44) */
16484     { reserved_block      , 0                   , 0   , 32,
16485        0xfc0003ff, 0x20000168, 0                      , 0,
16486        0x0                 },        /* _POOL32A0~*(45) */
16487     { instruction         , 0                   , 0   , 32,
16488        0xfc0003ff, 0x20000170, &DMTC0            , 0,
16489        CP0_ | MIPS64_      },        /* DMTC0 */
16490     { reserved_block      , 0                   , 0   , 32,
16491        0xfc0003ff, 0x20000178, 0                      , 0,
16492        0x0                 },        /* _POOL32A0~*(47) */
16493     { reserved_block      , 0                   , 0   , 32,
16494        0xfc0003ff, 0x20000180, 0                      , 0,
16495        0x0                 },        /* _POOL32A0~*(48) */
16496     { reserved_block      , 0                   , 0   , 32,
16497        0xfc0003ff, 0x20000188, 0                      , 0,
16498        0x0                 },        /* _POOL32A0~*(49) */
16499     { instruction         , 0                   , 0   , 32,
16500        0xfc0003ff, 0x20000190, &SUB              , 0,
16501        XMMS_               },        /* SUB */
16502     { instruction         , 0                   , 0   , 32,
16503        0xfc0003ff, 0x20000198, &DIVU             , 0,
16504        0x0                 },        /* DIVU */
16505     { reserved_block      , 0                   , 0   , 32,
16506        0xfc0003ff, 0x200001a0, 0                      , 0,
16507        0x0                 },        /* _POOL32A0~*(52) */
16508     { reserved_block      , 0                   , 0   , 32,
16509        0xfc0003ff, 0x200001a8, 0                      , 0,
16510        0x0                 },        /* _POOL32A0~*(53) */
16511     { instruction         , 0                   , 0   , 32,
16512        0xfc0003ff, 0x200001b0, &DMFGC0           , 0,
16513        CP0_ | MIPS64_ | VZ_},        /* DMFGC0 */
16514     { reserved_block      , 0                   , 0   , 32,
16515        0xfc0003ff, 0x200001b8, 0                      , 0,
16516        0x0                 },        /* _POOL32A0~*(55) */
16517     { instruction         , 0                   , 0   , 32,
16518        0xfc0003ff, 0x200001c0, &RDHWR            , 0,
16519        XMMS_               },        /* RDHWR */
16520     { reserved_block      , 0                   , 0   , 32,
16521        0xfc0003ff, 0x200001c8, 0                      , 0,
16522        0x0                 },        /* _POOL32A0~*(57) */
16523     { instruction         , 0                   , 0   , 32,
16524        0xfc0003ff, 0x200001d0, &SUBU_32_         , 0,
16525        0x0                 },        /* SUBU[32] */
16526     { instruction         , 0                   , 0   , 32,
16527        0xfc0003ff, 0x200001d8, &MODU             , 0,
16528        0x0                 },        /* MODU */
16529     { reserved_block      , 0                   , 0   , 32,
16530        0xfc0003ff, 0x200001e0, 0                      , 0,
16531        0x0                 },        /* _POOL32A0~*(60) */
16532     { reserved_block      , 0                   , 0   , 32,
16533        0xfc0003ff, 0x200001e8, 0                      , 0,
16534        0x0                 },        /* _POOL32A0~*(61) */
16535     { instruction         , 0                   , 0   , 32,
16536        0xfc0003ff, 0x200001f0, &DMTGC0           , 0,
16537        CP0_ | MIPS64_ | VZ_},        /* DMTGC0 */
16538     { reserved_block      , 0                   , 0   , 32,
16539        0xfc0003ff, 0x200001f8, 0                      , 0,
16540        0x0                 },        /* _POOL32A0~*(63) */
16541     { reserved_block      , 0                   , 0   , 32,
16542        0xfc0003ff, 0x20000200, 0                      , 0,
16543        0x0                 },        /* _POOL32A0~*(64) */
16544     { reserved_block      , 0                   , 0   , 32,
16545        0xfc0003ff, 0x20000208, 0                      , 0,
16546        0x0                 },        /* _POOL32A0~*(65) */
16547     { pool                , P_CMOVE             , 2   , 32,
16548        0xfc0003ff, 0x20000210, 0                      , 0,
16549        0x0                 },        /* P.CMOVE */
16550     { reserved_block      , 0                   , 0   , 32,
16551        0xfc0003ff, 0x20000218, 0                      , 0,
16552        0x0                 },        /* _POOL32A0~*(67) */
16553     { reserved_block      , 0                   , 0   , 32,
16554        0xfc0003ff, 0x20000220, 0                      , 0,
16555        0x0                 },        /* _POOL32A0~*(68) */
16556     { instruction         , 0                   , 0   , 32,
16557        0xfc0003ff, 0x20000228, &FORK             , 0,
16558        MT_                 },        /* FORK */
16559     { instruction         , 0                   , 0   , 32,
16560        0xfc0003ff, 0x20000230, &MFTR             , 0,
16561        MT_                 },        /* MFTR */
16562     { instruction         , 0                   , 0   , 32,
16563        0xfc0003ff, 0x20000238, &MFHTR            , 0,
16564        MT_                 },        /* MFHTR */
16565     { reserved_block      , 0                   , 0   , 32,
16566        0xfc0003ff, 0x20000240, 0                      , 0,
16567        0x0                 },        /* _POOL32A0~*(72) */
16568     { reserved_block      , 0                   , 0   , 32,
16569        0xfc0003ff, 0x20000248, 0                      , 0,
16570        0x0                 },        /* _POOL32A0~*(73) */
16571     { instruction         , 0                   , 0   , 32,
16572        0xfc0003ff, 0x20000250, &AND_32_          , 0,
16573        0x0                 },        /* AND[32] */
16574     { reserved_block      , 0                   , 0   , 32,
16575        0xfc0003ff, 0x20000258, 0                      , 0,
16576        0x0                 },        /* _POOL32A0~*(75) */
16577     { reserved_block      , 0                   , 0   , 32,
16578        0xfc0003ff, 0x20000260, 0                      , 0,
16579        0x0                 },        /* _POOL32A0~*(76) */
16580     { instruction         , 0                   , 0   , 32,
16581        0xfc0003ff, 0x20000268, &YIELD            , 0,
16582        MT_                 },        /* YIELD */
16583     { instruction         , 0                   , 0   , 32,
16584        0xfc0003ff, 0x20000270, &MTTR             , 0,
16585        MT_                 },        /* MTTR */
16586     { instruction         , 0                   , 0   , 32,
16587        0xfc0003ff, 0x20000278, &MTHTR            , 0,
16588        MT_                 },        /* MTHTR */
16589     { reserved_block      , 0                   , 0   , 32,
16590        0xfc0003ff, 0x20000280, 0                      , 0,
16591        0x0                 },        /* _POOL32A0~*(80) */
16592     { reserved_block      , 0                   , 0   , 32,
16593        0xfc0003ff, 0x20000288, 0                      , 0,
16594        0x0                 },        /* _POOL32A0~*(81) */
16595     { instruction         , 0                   , 0   , 32,
16596        0xfc0003ff, 0x20000290, &OR_32_           , 0,
16597        0x0                 },        /* OR[32] */
16598     { reserved_block      , 0                   , 0   , 32,
16599        0xfc0003ff, 0x20000298, 0                      , 0,
16600        0x0                 },        /* _POOL32A0~*(83) */
16601     { reserved_block      , 0                   , 0   , 32,
16602        0xfc0003ff, 0x200002a0, 0                      , 0,
16603        0x0                 },        /* _POOL32A0~*(84) */
16604     { reserved_block      , 0                   , 0   , 32,
16605        0xfc0003ff, 0x200002a8, 0                      , 0,
16606        0x0                 },        /* _POOL32A0~*(85) */
16607     { pool                , P_MT_VPE            , 8   , 32,
16608        0xfc0003ff, 0x200002b0, 0                      , 0,
16609        0x0                 },        /* P.MT_VPE */
16610     { reserved_block      , 0                   , 0   , 32,
16611        0xfc0003ff, 0x200002b8, 0                      , 0,
16612        0x0                 },        /* _POOL32A0~*(87) */
16613     { reserved_block      , 0                   , 0   , 32,
16614        0xfc0003ff, 0x200002c0, 0                      , 0,
16615        0x0                 },        /* _POOL32A0~*(88) */
16616     { reserved_block      , 0                   , 0   , 32,
16617        0xfc0003ff, 0x200002c8, 0                      , 0,
16618        0x0                 },        /* _POOL32A0~*(89) */
16619     { instruction         , 0                   , 0   , 32,
16620        0xfc0003ff, 0x200002d0, &NOR              , 0,
16621        0x0                 },        /* NOR */
16622     { reserved_block      , 0                   , 0   , 32,
16623        0xfc0003ff, 0x200002d8, 0                      , 0,
16624        0x0                 },        /* _POOL32A0~*(91) */
16625     { reserved_block      , 0                   , 0   , 32,
16626        0xfc0003ff, 0x200002e0, 0                      , 0,
16627        0x0                 },        /* _POOL32A0~*(92) */
16628     { reserved_block      , 0                   , 0   , 32,
16629        0xfc0003ff, 0x200002e8, 0                      , 0,
16630        0x0                 },        /* _POOL32A0~*(93) */
16631     { reserved_block      , 0                   , 0   , 32,
16632        0xfc0003ff, 0x200002f0, 0                      , 0,
16633        0x0                 },        /* _POOL32A0~*(94) */
16634     { reserved_block      , 0                   , 0   , 32,
16635        0xfc0003ff, 0x200002f8, 0                      , 0,
16636        0x0                 },        /* _POOL32A0~*(95) */
16637     { reserved_block      , 0                   , 0   , 32,
16638        0xfc0003ff, 0x20000300, 0                      , 0,
16639        0x0                 },        /* _POOL32A0~*(96) */
16640     { reserved_block      , 0                   , 0   , 32,
16641        0xfc0003ff, 0x20000308, 0                      , 0,
16642        0x0                 },        /* _POOL32A0~*(97) */
16643     { instruction         , 0                   , 0   , 32,
16644        0xfc0003ff, 0x20000310, &XOR_32_          , 0,
16645        0x0                 },        /* XOR[32] */
16646     { reserved_block      , 0                   , 0   , 32,
16647        0xfc0003ff, 0x20000318, 0                      , 0,
16648        0x0                 },        /* _POOL32A0~*(99) */
16649     { reserved_block      , 0                   , 0   , 32,
16650        0xfc0003ff, 0x20000320, 0                      , 0,
16651        0x0                 },        /* _POOL32A0~*(100) */
16652     { reserved_block      , 0                   , 0   , 32,
16653        0xfc0003ff, 0x20000328, 0                      , 0,
16654        0x0                 },        /* _POOL32A0~*(101) */
16655     { reserved_block      , 0                   , 0   , 32,
16656        0xfc0003ff, 0x20000330, 0                      , 0,
16657        0x0                 },        /* _POOL32A0~*(102) */
16658     { reserved_block      , 0                   , 0   , 32,
16659        0xfc0003ff, 0x20000338, 0                      , 0,
16660        0x0                 },        /* _POOL32A0~*(103) */
16661     { reserved_block      , 0                   , 0   , 32,
16662        0xfc0003ff, 0x20000340, 0                      , 0,
16663        0x0                 },        /* _POOL32A0~*(104) */
16664     { reserved_block      , 0                   , 0   , 32,
16665        0xfc0003ff, 0x20000348, 0                      , 0,
16666        0x0                 },        /* _POOL32A0~*(105) */
16667     { instruction         , 0                   , 0   , 32,
16668        0xfc0003ff, 0x20000350, &SLT              , 0,
16669        0x0                 },        /* SLT */
16670     { reserved_block      , 0                   , 0   , 32,
16671        0xfc0003ff, 0x20000358, 0                      , 0,
16672        0x0                 },        /* _POOL32A0~*(107) */
16673     { reserved_block      , 0                   , 0   , 32,
16674        0xfc0003ff, 0x20000360, 0                      , 0,
16675        0x0                 },        /* _POOL32A0~*(108) */
16676     { reserved_block      , 0                   , 0   , 32,
16677        0xfc0003ff, 0x20000368, 0                      , 0,
16678        0x0                 },        /* _POOL32A0~*(109) */
16679     { reserved_block      , 0                   , 0   , 32,
16680        0xfc0003ff, 0x20000370, 0                      , 0,
16681        0x0                 },        /* _POOL32A0~*(110) */
16682     { reserved_block      , 0                   , 0   , 32,
16683        0xfc0003ff, 0x20000378, 0                      , 0,
16684        0x0                 },        /* _POOL32A0~*(111) */
16685     { reserved_block      , 0                   , 0   , 32,
16686        0xfc0003ff, 0x20000380, 0                      , 0,
16687        0x0                 },        /* _POOL32A0~*(112) */
16688     { reserved_block      , 0                   , 0   , 32,
16689        0xfc0003ff, 0x20000388, 0                      , 0,
16690        0x0                 },        /* _POOL32A0~*(113) */
16691     { pool                , P_SLTU              , 2   , 32,
16692        0xfc0003ff, 0x20000390, 0                      , 0,
16693        0x0                 },        /* P.SLTU */
16694     { reserved_block      , 0                   , 0   , 32,
16695        0xfc0003ff, 0x20000398, 0                      , 0,
16696        0x0                 },        /* _POOL32A0~*(115) */
16697     { reserved_block      , 0                   , 0   , 32,
16698        0xfc0003ff, 0x200003a0, 0                      , 0,
16699        0x0                 },        /* _POOL32A0~*(116) */
16700     { reserved_block      , 0                   , 0   , 32,
16701        0xfc0003ff, 0x200003a8, 0                      , 0,
16702        0x0                 },        /* _POOL32A0~*(117) */
16703     { reserved_block      , 0                   , 0   , 32,
16704        0xfc0003ff, 0x200003b0, 0                      , 0,
16705        0x0                 },        /* _POOL32A0~*(118) */
16706     { reserved_block      , 0                   , 0   , 32,
16707        0xfc0003ff, 0x200003b8, 0                      , 0,
16708        0x0                 },        /* _POOL32A0~*(119) */
16709     { reserved_block      , 0                   , 0   , 32,
16710        0xfc0003ff, 0x200003c0, 0                      , 0,
16711        0x0                 },        /* _POOL32A0~*(120) */
16712     { reserved_block      , 0                   , 0   , 32,
16713        0xfc0003ff, 0x200003c8, 0                      , 0,
16714        0x0                 },        /* _POOL32A0~*(121) */
16715     { instruction         , 0                   , 0   , 32,
16716        0xfc0003ff, 0x200003d0, &SOV              , 0,
16717        0x0                 },        /* SOV */
16718     { reserved_block      , 0                   , 0   , 32,
16719        0xfc0003ff, 0x200003d8, 0                      , 0,
16720        0x0                 },        /* _POOL32A0~*(123) */
16721     { reserved_block      , 0                   , 0   , 32,
16722        0xfc0003ff, 0x200003e0, 0                      , 0,
16723        0x0                 },        /* _POOL32A0~*(124) */
16724     { reserved_block      , 0                   , 0   , 32,
16725        0xfc0003ff, 0x200003e8, 0                      , 0,
16726        0x0                 },        /* _POOL32A0~*(125) */
16727     { reserved_block      , 0                   , 0   , 32,
16728        0xfc0003ff, 0x200003f0, 0                      , 0,
16729        0x0                 },        /* _POOL32A0~*(126) */
16730     { reserved_block      , 0                   , 0   , 32,
16731        0xfc0003ff, 0x200003f8, 0                      , 0,
16732        0x0                 },        /* _POOL32A0~*(127) */
16733 };
16734 
16735 
16736 static const Pool ADDQ__S__PH[2] = {
16737     { instruction         , 0                   , 0   , 32,
16738        0xfc0007ff, 0x2000000d, &ADDQ_PH          , 0,
16739        DSP_                },        /* ADDQ.PH */
16740     { instruction         , 0                   , 0   , 32,
16741        0xfc0007ff, 0x2000040d, &ADDQ_S_PH        , 0,
16742        DSP_                },        /* ADDQ_S.PH */
16743 };
16744 
16745 
16746 static const Pool MUL__S__PH[2] = {
16747     { instruction         , 0                   , 0   , 32,
16748        0xfc0007ff, 0x2000002d, &MUL_PH           , 0,
16749        DSP_                },        /* MUL.PH */
16750     { instruction         , 0                   , 0   , 32,
16751        0xfc0007ff, 0x2000042d, &MUL_S_PH         , 0,
16752        DSP_                },        /* MUL_S.PH */
16753 };
16754 
16755 
16756 static const Pool ADDQH__R__PH[2] = {
16757     { instruction         , 0                   , 0   , 32,
16758        0xfc0007ff, 0x2000004d, &ADDQH_PH         , 0,
16759        DSP_                },        /* ADDQH.PH */
16760     { instruction         , 0                   , 0   , 32,
16761        0xfc0007ff, 0x2000044d, &ADDQH_R_PH       , 0,
16762        DSP_                },        /* ADDQH_R.PH */
16763 };
16764 
16765 
16766 static const Pool ADDQH__R__W[2] = {
16767     { instruction         , 0                   , 0   , 32,
16768        0xfc0007ff, 0x2000008d, &ADDQH_W          , 0,
16769        DSP_                },        /* ADDQH.W */
16770     { instruction         , 0                   , 0   , 32,
16771        0xfc0007ff, 0x2000048d, &ADDQH_R_W        , 0,
16772        DSP_                },        /* ADDQH_R.W */
16773 };
16774 
16775 
16776 static const Pool ADDU__S__QB[2] = {
16777     { instruction         , 0                   , 0   , 32,
16778        0xfc0007ff, 0x200000cd, &ADDU_QB          , 0,
16779        DSP_                },        /* ADDU.QB */
16780     { instruction         , 0                   , 0   , 32,
16781        0xfc0007ff, 0x200004cd, &ADDU_S_QB        , 0,
16782        DSP_                },        /* ADDU_S.QB */
16783 };
16784 
16785 
16786 static const Pool ADDU__S__PH[2] = {
16787     { instruction         , 0                   , 0   , 32,
16788        0xfc0007ff, 0x2000010d, &ADDU_PH          , 0,
16789        DSP_                },        /* ADDU.PH */
16790     { instruction         , 0                   , 0   , 32,
16791        0xfc0007ff, 0x2000050d, &ADDU_S_PH        , 0,
16792        DSP_                },        /* ADDU_S.PH */
16793 };
16794 
16795 
16796 static const Pool ADDUH__R__QB[2] = {
16797     { instruction         , 0                   , 0   , 32,
16798        0xfc0007ff, 0x2000014d, &ADDUH_QB         , 0,
16799        DSP_                },        /* ADDUH.QB */
16800     { instruction         , 0                   , 0   , 32,
16801        0xfc0007ff, 0x2000054d, &ADDUH_R_QB       , 0,
16802        DSP_                },        /* ADDUH_R.QB */
16803 };
16804 
16805 
16806 static const Pool SHRAV__R__PH[2] = {
16807     { instruction         , 0                   , 0   , 32,
16808        0xfc0007ff, 0x2000018d, &SHRAV_PH         , 0,
16809        DSP_                },        /* SHRAV.PH */
16810     { instruction         , 0                   , 0   , 32,
16811        0xfc0007ff, 0x2000058d, &SHRAV_R_PH       , 0,
16812        DSP_                },        /* SHRAV_R.PH */
16813 };
16814 
16815 
16816 static const Pool SHRAV__R__QB[2] = {
16817     { instruction         , 0                   , 0   , 32,
16818        0xfc0007ff, 0x200001cd, &SHRAV_QB         , 0,
16819        DSP_                },        /* SHRAV.QB */
16820     { instruction         , 0                   , 0   , 32,
16821        0xfc0007ff, 0x200005cd, &SHRAV_R_QB       , 0,
16822        DSP_                },        /* SHRAV_R.QB */
16823 };
16824 
16825 
16826 static const Pool SUBQ__S__PH[2] = {
16827     { instruction         , 0                   , 0   , 32,
16828        0xfc0007ff, 0x2000020d, &SUBQ_PH          , 0,
16829        DSP_                },        /* SUBQ.PH */
16830     { instruction         , 0                   , 0   , 32,
16831        0xfc0007ff, 0x2000060d, &SUBQ_S_PH        , 0,
16832        DSP_                },        /* SUBQ_S.PH */
16833 };
16834 
16835 
16836 static const Pool SUBQH__R__PH[2] = {
16837     { instruction         , 0                   , 0   , 32,
16838        0xfc0007ff, 0x2000024d, &SUBQH_PH         , 0,
16839        DSP_                },        /* SUBQH.PH */
16840     { instruction         , 0                   , 0   , 32,
16841        0xfc0007ff, 0x2000064d, &SUBQH_R_PH       , 0,
16842        DSP_                },        /* SUBQH_R.PH */
16843 };
16844 
16845 
16846 static const Pool SUBQH__R__W[2] = {
16847     { instruction         , 0                   , 0   , 32,
16848        0xfc0007ff, 0x2000028d, &SUBQH_W          , 0,
16849        DSP_                },        /* SUBQH.W */
16850     { instruction         , 0                   , 0   , 32,
16851        0xfc0007ff, 0x2000068d, &SUBQH_R_W        , 0,
16852        DSP_                },        /* SUBQH_R.W */
16853 };
16854 
16855 
16856 static const Pool SUBU__S__QB[2] = {
16857     { instruction         , 0                   , 0   , 32,
16858        0xfc0007ff, 0x200002cd, &SUBU_QB          , 0,
16859        DSP_                },        /* SUBU.QB */
16860     { instruction         , 0                   , 0   , 32,
16861        0xfc0007ff, 0x200006cd, &SUBU_S_QB        , 0,
16862        DSP_                },        /* SUBU_S.QB */
16863 };
16864 
16865 
16866 static const Pool SUBU__S__PH[2] = {
16867     { instruction         , 0                   , 0   , 32,
16868        0xfc0007ff, 0x2000030d, &SUBU_PH          , 0,
16869        DSP_                },        /* SUBU.PH */
16870     { instruction         , 0                   , 0   , 32,
16871        0xfc0007ff, 0x2000070d, &SUBU_S_PH        , 0,
16872        DSP_                },        /* SUBU_S.PH */
16873 };
16874 
16875 
16876 static const Pool SHRA__R__PH[2] = {
16877     { instruction         , 0                   , 0   , 32,
16878        0xfc0007ff, 0x20000335, &SHRA_PH          , 0,
16879        DSP_                },        /* SHRA.PH */
16880     { instruction         , 0                   , 0   , 32,
16881        0xfc0007ff, 0x20000735, &SHRA_R_PH        , 0,
16882        DSP_                },        /* SHRA_R.PH */
16883 };
16884 
16885 
16886 static const Pool SUBUH__R__QB[2] = {
16887     { instruction         , 0                   , 0   , 32,
16888        0xfc0007ff, 0x2000034d, &SUBUH_QB         , 0,
16889        DSP_                },        /* SUBUH.QB */
16890     { instruction         , 0                   , 0   , 32,
16891        0xfc0007ff, 0x2000074d, &SUBUH_R_QB       , 0,
16892        DSP_                },        /* SUBUH_R.QB */
16893 };
16894 
16895 
16896 static const Pool SHLLV__S__PH[2] = {
16897     { instruction         , 0                   , 0   , 32,
16898        0xfc0007ff, 0x2000038d, &SHLLV_PH         , 0,
16899        DSP_                },        /* SHLLV.PH */
16900     { instruction         , 0                   , 0   , 32,
16901        0xfc0007ff, 0x2000078d, &SHLLV_S_PH       , 0,
16902        DSP_                },        /* SHLLV_S.PH */
16903 };
16904 
16905 
16906 static const Pool SHLL__S__PH[4] = {
16907     { instruction         , 0                   , 0   , 32,
16908        0xfc000fff, 0x200003b5, &SHLL_PH          , 0,
16909        DSP_                },        /* SHLL.PH */
16910     { reserved_block      , 0                   , 0   , 32,
16911        0xfc000fff, 0x200007b5, 0                      , 0,
16912        0x0                 },        /* SHLL[_S].PH~*(1) */
16913     { instruction         , 0                   , 0   , 32,
16914        0xfc000fff, 0x20000bb5, &SHLL_S_PH        , 0,
16915        DSP_                },        /* SHLL_S.PH */
16916     { reserved_block      , 0                   , 0   , 32,
16917        0xfc000fff, 0x20000fb5, 0                      , 0,
16918        0x0                 },        /* SHLL[_S].PH~*(3) */
16919 };
16920 
16921 
16922 static const Pool PRECR_SRA__R__PH_W[2] = {
16923     { instruction         , 0                   , 0   , 32,
16924        0xfc0007ff, 0x200003cd, &PRECR_SRA_PH_W   , 0,
16925        DSP_                },        /* PRECR_SRA.PH.W */
16926     { instruction         , 0                   , 0   , 32,
16927        0xfc0007ff, 0x200007cd, &PRECR_SRA_R_PH_W , 0,
16928        DSP_                },        /* PRECR_SRA_R.PH.W */
16929 };
16930 
16931 
16932 static const Pool _POOL32A5[128] = {
16933     { instruction         , 0                   , 0   , 32,
16934        0xfc0003ff, 0x20000005, &CMP_EQ_PH        , 0,
16935        DSP_                },        /* CMP.EQ.PH */
16936     { pool                , ADDQ__S__PH         , 2   , 32,
16937        0xfc0003ff, 0x2000000d, 0                      , 0,
16938        0x0                 },        /* ADDQ[_S].PH */
16939     { reserved_block      , 0                   , 0   , 32,
16940        0xfc0003ff, 0x20000015, 0                      , 0,
16941        0x0                 },        /* _POOL32A5~*(2) */
16942     { instruction         , 0                   , 0   , 32,
16943        0xfc0003ff, 0x2000001d, &SHILO            , 0,
16944        DSP_                },        /* SHILO */
16945     { instruction         , 0                   , 0   , 32,
16946        0xfc0003ff, 0x20000025, &MULEQ_S_W_PHL    , 0,
16947        DSP_                },        /* MULEQ_S.W.PHL */
16948     { pool                , MUL__S__PH          , 2   , 32,
16949        0xfc0003ff, 0x2000002d, 0                      , 0,
16950        0x0                 },        /* MUL[_S].PH */
16951     { reserved_block      , 0                   , 0   , 32,
16952        0xfc0003ff, 0x20000035, 0                      , 0,
16953        0x0                 },        /* _POOL32A5~*(6) */
16954     { instruction         , 0                   , 0   , 32,
16955        0xfc0003ff, 0x2000003d, &REPL_PH          , 0,
16956        DSP_                },        /* REPL.PH */
16957     { instruction         , 0                   , 0   , 32,
16958        0xfc0003ff, 0x20000045, &CMP_LT_PH        , 0,
16959        DSP_                },        /* CMP.LT.PH */
16960     { pool                , ADDQH__R__PH        , 2   , 32,
16961        0xfc0003ff, 0x2000004d, 0                      , 0,
16962        0x0                 },        /* ADDQH[_R].PH */
16963     { reserved_block      , 0                   , 0   , 32,
16964        0xfc0003ff, 0x20000055, 0                      , 0,
16965        0x0                 },        /* _POOL32A5~*(10) */
16966     { reserved_block      , 0                   , 0   , 32,
16967        0xfc0003ff, 0x2000005d, 0                      , 0,
16968        0x0                 },        /* _POOL32A5~*(11) */
16969     { instruction         , 0                   , 0   , 32,
16970        0xfc0003ff, 0x20000065, &MULEQ_S_W_PHR    , 0,
16971        DSP_                },        /* MULEQ_S.W.PHR */
16972     { instruction         , 0                   , 0   , 32,
16973        0xfc0003ff, 0x2000006d, &PRECR_QB_PH      , 0,
16974        DSP_                },        /* PRECR.QB.PH */
16975     { reserved_block      , 0                   , 0   , 32,
16976        0xfc0003ff, 0x20000075, 0                      , 0,
16977        0x0                 },        /* _POOL32A5~*(14) */
16978     { reserved_block      , 0                   , 0   , 32,
16979        0xfc0003ff, 0x2000007d, 0                      , 0,
16980        0x0                 },        /* _POOL32A5~*(15) */
16981     { instruction         , 0                   , 0   , 32,
16982        0xfc0003ff, 0x20000085, &CMP_LE_PH        , 0,
16983        DSP_                },        /* CMP.LE.PH */
16984     { pool                , ADDQH__R__W         , 2   , 32,
16985        0xfc0003ff, 0x2000008d, 0                      , 0,
16986        0x0                 },        /* ADDQH[_R].W */
16987     { instruction         , 0                   , 0   , 32,
16988        0xfc0003ff, 0x20000095, &MULEU_S_PH_QBL   , 0,
16989        DSP_                },        /* MULEU_S.PH.QBL */
16990     { reserved_block      , 0                   , 0   , 32,
16991        0xfc0003ff, 0x2000009d, 0                      , 0,
16992        0x0                 },        /* _POOL32A5~*(19) */
16993     { reserved_block      , 0                   , 0   , 32,
16994        0xfc0003ff, 0x200000a5, 0                      , 0,
16995        0x0                 },        /* _POOL32A5~*(20) */
16996     { instruction         , 0                   , 0   , 32,
16997        0xfc0003ff, 0x200000ad, &PRECRQ_QB_PH     , 0,
16998        DSP_                },        /* PRECRQ.QB.PH */
16999     { reserved_block      , 0                   , 0   , 32,
17000        0xfc0003ff, 0x200000b5, 0                      , 0,
17001        0x0                 },        /* _POOL32A5~*(22) */
17002     { reserved_block      , 0                   , 0   , 32,
17003        0xfc0003ff, 0x200000bd, 0                      , 0,
17004        0x0                 },        /* _POOL32A5~*(23) */
17005     { instruction         , 0                   , 0   , 32,
17006        0xfc0003ff, 0x200000c5, &CMPGU_EQ_QB      , 0,
17007        DSP_                },        /* CMPGU.EQ.QB */
17008     { pool                , ADDU__S__QB         , 2   , 32,
17009        0xfc0003ff, 0x200000cd, 0                      , 0,
17010        0x0                 },        /* ADDU[_S].QB */
17011     { instruction         , 0                   , 0   , 32,
17012        0xfc0003ff, 0x200000d5, &MULEU_S_PH_QBR   , 0,
17013        DSP_                },        /* MULEU_S.PH.QBR */
17014     { reserved_block      , 0                   , 0   , 32,
17015        0xfc0003ff, 0x200000dd, 0                      , 0,
17016        0x0                 },        /* _POOL32A5~*(27) */
17017     { reserved_block      , 0                   , 0   , 32,
17018        0xfc0003ff, 0x200000e5, 0                      , 0,
17019        0x0                 },        /* _POOL32A5~*(28) */
17020     { instruction         , 0                   , 0   , 32,
17021        0xfc0003ff, 0x200000ed, &PRECRQ_PH_W      , 0,
17022        DSP_                },        /* PRECRQ.PH.W */
17023     { reserved_block      , 0                   , 0   , 32,
17024        0xfc0003ff, 0x200000f5, 0                      , 0,
17025        0x0                 },        /* _POOL32A5~*(30) */
17026     { reserved_block      , 0                   , 0   , 32,
17027        0xfc0003ff, 0x200000fd, 0                      , 0,
17028        0x0                 },        /* _POOL32A5~*(31) */
17029     { instruction         , 0                   , 0   , 32,
17030        0xfc0003ff, 0x20000105, &CMPGU_LT_QB      , 0,
17031        DSP_                },        /* CMPGU.LT.QB */
17032     { pool                , ADDU__S__PH         , 2   , 32,
17033        0xfc0003ff, 0x2000010d, 0                      , 0,
17034        0x0                 },        /* ADDU[_S].PH */
17035     { instruction         , 0                   , 0   , 32,
17036        0xfc0003ff, 0x20000115, &MULQ_RS_PH       , 0,
17037        DSP_                },        /* MULQ_RS.PH */
17038     { reserved_block      , 0                   , 0   , 32,
17039        0xfc0003ff, 0x2000011d, 0                      , 0,
17040        0x0                 },        /* _POOL32A5~*(35) */
17041     { reserved_block      , 0                   , 0   , 32,
17042        0xfc0003ff, 0x20000125, 0                      , 0,
17043        0x0                 },        /* _POOL32A5~*(36) */
17044     { instruction         , 0                   , 0   , 32,
17045        0xfc0003ff, 0x2000012d, &PRECRQ_RS_PH_W   , 0,
17046        DSP_                },        /* PRECRQ_RS.PH.W */
17047     { reserved_block      , 0                   , 0   , 32,
17048        0xfc0003ff, 0x20000135, 0                      , 0,
17049        0x0                 },        /* _POOL32A5~*(38) */
17050     { reserved_block      , 0                   , 0   , 32,
17051        0xfc0003ff, 0x2000013d, 0                      , 0,
17052        0x0                 },        /* _POOL32A5~*(39) */
17053     { instruction         , 0                   , 0   , 32,
17054        0xfc0003ff, 0x20000145, &CMPGU_LE_QB      , 0,
17055        DSP_                },        /* CMPGU.LE.QB */
17056     { pool                , ADDUH__R__QB        , 2   , 32,
17057        0xfc0003ff, 0x2000014d, 0                      , 0,
17058        0x0                 },        /* ADDUH[_R].QB */
17059     { instruction         , 0                   , 0   , 32,
17060        0xfc0003ff, 0x20000155, &MULQ_S_PH        , 0,
17061        DSP_                },        /* MULQ_S.PH */
17062     { reserved_block      , 0                   , 0   , 32,
17063        0xfc0003ff, 0x2000015d, 0                      , 0,
17064        0x0                 },        /* _POOL32A5~*(43) */
17065     { reserved_block      , 0                   , 0   , 32,
17066        0xfc0003ff, 0x20000165, 0                      , 0,
17067        0x0                 },        /* _POOL32A5~*(44) */
17068     { instruction         , 0                   , 0   , 32,
17069        0xfc0003ff, 0x2000016d, &PRECRQU_S_QB_PH  , 0,
17070        DSP_                },        /* PRECRQU_S.QB.PH */
17071     { reserved_block      , 0                   , 0   , 32,
17072        0xfc0003ff, 0x20000175, 0                      , 0,
17073        0x0                 },        /* _POOL32A5~*(46) */
17074     { reserved_block      , 0                   , 0   , 32,
17075        0xfc0003ff, 0x2000017d, 0                      , 0,
17076        0x0                 },        /* _POOL32A5~*(47) */
17077     { instruction         , 0                   , 0   , 32,
17078        0xfc0003ff, 0x20000185, &CMPGDU_EQ_QB     , 0,
17079        DSP_                },        /* CMPGDU.EQ.QB */
17080     { pool                , SHRAV__R__PH        , 2   , 32,
17081        0xfc0003ff, 0x2000018d, 0                      , 0,
17082        0x0                 },        /* SHRAV[_R].PH */
17083     { instruction         , 0                   , 0   , 32,
17084        0xfc0003ff, 0x20000195, &MULQ_RS_W        , 0,
17085        DSP_                },        /* MULQ_RS.W */
17086     { reserved_block      , 0                   , 0   , 32,
17087        0xfc0003ff, 0x2000019d, 0                      , 0,
17088        0x0                 },        /* _POOL32A5~*(51) */
17089     { reserved_block      , 0                   , 0   , 32,
17090        0xfc0003ff, 0x200001a5, 0                      , 0,
17091        0x0                 },        /* _POOL32A5~*(52) */
17092     { instruction         , 0                   , 0   , 32,
17093        0xfc0003ff, 0x200001ad, &PACKRL_PH        , 0,
17094        DSP_                },        /* PACKRL.PH */
17095     { reserved_block      , 0                   , 0   , 32,
17096        0xfc0003ff, 0x200001b5, 0                      , 0,
17097        0x0                 },        /* _POOL32A5~*(54) */
17098     { reserved_block      , 0                   , 0   , 32,
17099        0xfc0003ff, 0x200001bd, 0                      , 0,
17100        0x0                 },        /* _POOL32A5~*(55) */
17101     { instruction         , 0                   , 0   , 32,
17102        0xfc0003ff, 0x200001c5, &CMPGDU_LT_QB     , 0,
17103        DSP_                },        /* CMPGDU.LT.QB */
17104     { pool                , SHRAV__R__QB        , 2   , 32,
17105        0xfc0003ff, 0x200001cd, 0                      , 0,
17106        0x0                 },        /* SHRAV[_R].QB */
17107     { instruction         , 0                   , 0   , 32,
17108        0xfc0003ff, 0x200001d5, &MULQ_S_W         , 0,
17109        DSP_                },        /* MULQ_S.W */
17110     { reserved_block      , 0                   , 0   , 32,
17111        0xfc0003ff, 0x200001dd, 0                      , 0,
17112        0x0                 },        /* _POOL32A5~*(59) */
17113     { reserved_block      , 0                   , 0   , 32,
17114        0xfc0003ff, 0x200001e5, 0                      , 0,
17115        0x0                 },        /* _POOL32A5~*(60) */
17116     { instruction         , 0                   , 0   , 32,
17117        0xfc0003ff, 0x200001ed, &PICK_QB          , 0,
17118        DSP_                },        /* PICK.QB */
17119     { reserved_block      , 0                   , 0   , 32,
17120        0xfc0003ff, 0x200001f5, 0                      , 0,
17121        0x0                 },        /* _POOL32A5~*(62) */
17122     { reserved_block      , 0                   , 0   , 32,
17123        0xfc0003ff, 0x200001fd, 0                      , 0,
17124        0x0                 },        /* _POOL32A5~*(63) */
17125     { instruction         , 0                   , 0   , 32,
17126        0xfc0003ff, 0x20000205, &CMPGDU_LE_QB     , 0,
17127        DSP_                },        /* CMPGDU.LE.QB */
17128     { pool                , SUBQ__S__PH         , 2   , 32,
17129        0xfc0003ff, 0x2000020d, 0                      , 0,
17130        0x0                 },        /* SUBQ[_S].PH */
17131     { instruction         , 0                   , 0   , 32,
17132        0xfc0003ff, 0x20000215, &APPEND           , 0,
17133        DSP_                },        /* APPEND */
17134     { reserved_block      , 0                   , 0   , 32,
17135        0xfc0003ff, 0x2000021d, 0                      , 0,
17136        0x0                 },        /* _POOL32A5~*(67) */
17137     { reserved_block      , 0                   , 0   , 32,
17138        0xfc0003ff, 0x20000225, 0                      , 0,
17139        0x0                 },        /* _POOL32A5~*(68) */
17140     { instruction         , 0                   , 0   , 32,
17141        0xfc0003ff, 0x2000022d, &PICK_PH          , 0,
17142        DSP_                },        /* PICK.PH */
17143     { reserved_block      , 0                   , 0   , 32,
17144        0xfc0003ff, 0x20000235, 0                      , 0,
17145        0x0                 },        /* _POOL32A5~*(70) */
17146     { reserved_block      , 0                   , 0   , 32,
17147        0xfc0003ff, 0x2000023d, 0                      , 0,
17148        0x0                 },        /* _POOL32A5~*(71) */
17149     { instruction         , 0                   , 0   , 32,
17150        0xfc0003ff, 0x20000245, &CMPU_EQ_QB       , 0,
17151        DSP_                },        /* CMPU.EQ.QB */
17152     { pool                , SUBQH__R__PH        , 2   , 32,
17153        0xfc0003ff, 0x2000024d, 0                      , 0,
17154        0x0                 },        /* SUBQH[_R].PH */
17155     { instruction         , 0                   , 0   , 32,
17156        0xfc0003ff, 0x20000255, &PREPEND          , 0,
17157        DSP_                },        /* PREPEND */
17158     { reserved_block      , 0                   , 0   , 32,
17159        0xfc0003ff, 0x2000025d, 0                      , 0,
17160        0x0                 },        /* _POOL32A5~*(75) */
17161     { reserved_block      , 0                   , 0   , 32,
17162        0xfc0003ff, 0x20000265, 0                      , 0,
17163        0x0                 },        /* _POOL32A5~*(76) */
17164     { reserved_block      , 0                   , 0   , 32,
17165        0xfc0003ff, 0x2000026d, 0                      , 0,
17166        0x0                 },        /* _POOL32A5~*(77) */
17167     { reserved_block      , 0                   , 0   , 32,
17168        0xfc0003ff, 0x20000275, 0                      , 0,
17169        0x0                 },        /* _POOL32A5~*(78) */
17170     { reserved_block      , 0                   , 0   , 32,
17171        0xfc0003ff, 0x2000027d, 0                      , 0,
17172        0x0                 },        /* _POOL32A5~*(79) */
17173     { instruction         , 0                   , 0   , 32,
17174        0xfc0003ff, 0x20000285, &CMPU_LT_QB       , 0,
17175        DSP_                },        /* CMPU.LT.QB */
17176     { pool                , SUBQH__R__W         , 2   , 32,
17177        0xfc0003ff, 0x2000028d, 0                      , 0,
17178        0x0                 },        /* SUBQH[_R].W */
17179     { instruction         , 0                   , 0   , 32,
17180        0xfc0003ff, 0x20000295, &MODSUB           , 0,
17181        DSP_                },        /* MODSUB */
17182     { reserved_block      , 0                   , 0   , 32,
17183        0xfc0003ff, 0x2000029d, 0                      , 0,
17184        0x0                 },        /* _POOL32A5~*(83) */
17185     { reserved_block      , 0                   , 0   , 32,
17186        0xfc0003ff, 0x200002a5, 0                      , 0,
17187        0x0                 },        /* _POOL32A5~*(84) */
17188     { reserved_block      , 0                   , 0   , 32,
17189        0xfc0003ff, 0x200002ad, 0                      , 0,
17190        0x0                 },        /* _POOL32A5~*(85) */
17191     { reserved_block      , 0                   , 0   , 32,
17192        0xfc0003ff, 0x200002b5, 0                      , 0,
17193        0x0                 },        /* _POOL32A5~*(86) */
17194     { reserved_block      , 0                   , 0   , 32,
17195        0xfc0003ff, 0x200002bd, 0                      , 0,
17196        0x0                 },        /* _POOL32A5~*(87) */
17197     { instruction         , 0                   , 0   , 32,
17198        0xfc0003ff, 0x200002c5, &CMPU_LE_QB       , 0,
17199        DSP_                },        /* CMPU.LE.QB */
17200     { pool                , SUBU__S__QB         , 2   , 32,
17201        0xfc0003ff, 0x200002cd, 0                      , 0,
17202        0x0                 },        /* SUBU[_S].QB */
17203     { instruction         , 0                   , 0   , 32,
17204        0xfc0003ff, 0x200002d5, &SHRAV_R_W        , 0,
17205        DSP_                },        /* SHRAV_R.W */
17206     { reserved_block      , 0                   , 0   , 32,
17207        0xfc0003ff, 0x200002dd, 0                      , 0,
17208        0x0                 },        /* _POOL32A5~*(91) */
17209     { reserved_block      , 0                   , 0   , 32,
17210        0xfc0003ff, 0x200002e5, 0                      , 0,
17211        0x0                 },        /* _POOL32A5~*(92) */
17212     { reserved_block      , 0                   , 0   , 32,
17213        0xfc0003ff, 0x200002ed, 0                      , 0,
17214        0x0                 },        /* _POOL32A5~*(93) */
17215     { instruction         , 0                   , 0   , 32,
17216        0xfc0003ff, 0x200002f5, &SHRA_R_W         , 0,
17217        DSP_                },        /* SHRA_R.W */
17218     { reserved_block      , 0                   , 0   , 32,
17219        0xfc0003ff, 0x200002fd, 0                      , 0,
17220        0x0                 },        /* _POOL32A5~*(95) */
17221     { instruction         , 0                   , 0   , 32,
17222        0xfc0003ff, 0x20000305, &ADDQ_S_W         , 0,
17223        DSP_                },        /* ADDQ_S.W */
17224     { pool                , SUBU__S__PH         , 2   , 32,
17225        0xfc0003ff, 0x2000030d, 0                      , 0,
17226        0x0                 },        /* SUBU[_S].PH */
17227     { instruction         , 0                   , 0   , 32,
17228        0xfc0003ff, 0x20000315, &SHRLV_PH         , 0,
17229        DSP_                },        /* SHRLV.PH */
17230     { reserved_block      , 0                   , 0   , 32,
17231        0xfc0003ff, 0x2000031d, 0                      , 0,
17232        0x0                 },        /* _POOL32A5~*(99) */
17233     { reserved_block      , 0                   , 0   , 32,
17234        0xfc0003ff, 0x20000325, 0                      , 0,
17235        0x0                 },        /* _POOL32A5~*(100) */
17236     { reserved_block      , 0                   , 0   , 32,
17237        0xfc0003ff, 0x2000032d, 0                      , 0,
17238        0x0                 },        /* _POOL32A5~*(101) */
17239     { pool                , SHRA__R__PH         , 2   , 32,
17240        0xfc0003ff, 0x20000335, 0                      , 0,
17241        0x0                 },        /* SHRA[_R].PH */
17242     { reserved_block      , 0                   , 0   , 32,
17243        0xfc0003ff, 0x2000033d, 0                      , 0,
17244        0x0                 },        /* _POOL32A5~*(103) */
17245     { instruction         , 0                   , 0   , 32,
17246        0xfc0003ff, 0x20000345, &SUBQ_S_W         , 0,
17247        DSP_                },        /* SUBQ_S.W */
17248     { pool                , SUBUH__R__QB        , 2   , 32,
17249        0xfc0003ff, 0x2000034d, 0                      , 0,
17250        0x0                 },        /* SUBUH[_R].QB */
17251     { instruction         , 0                   , 0   , 32,
17252        0xfc0003ff, 0x20000355, &SHRLV_QB         , 0,
17253        DSP_                },        /* SHRLV.QB */
17254     { reserved_block      , 0                   , 0   , 32,
17255        0xfc0003ff, 0x2000035d, 0                      , 0,
17256        0x0                 },        /* _POOL32A5~*(107) */
17257     { reserved_block      , 0                   , 0   , 32,
17258        0xfc0003ff, 0x20000365, 0                      , 0,
17259        0x0                 },        /* _POOL32A5~*(108) */
17260     { reserved_block      , 0                   , 0   , 32,
17261        0xfc0003ff, 0x2000036d, 0                      , 0,
17262        0x0                 },        /* _POOL32A5~*(109) */
17263     { reserved_block      , 0                   , 0   , 32,
17264        0xfc0003ff, 0x20000375, 0                      , 0,
17265        0x0                 },        /* _POOL32A5~*(110) */
17266     { reserved_block      , 0                   , 0   , 32,
17267        0xfc0003ff, 0x2000037d, 0                      , 0,
17268        0x0                 },        /* _POOL32A5~*(111) */
17269     { instruction         , 0                   , 0   , 32,
17270        0xfc0003ff, 0x20000385, &ADDSC            , 0,
17271        DSP_                },        /* ADDSC */
17272     { pool                , SHLLV__S__PH        , 2   , 32,
17273        0xfc0003ff, 0x2000038d, 0                      , 0,
17274        0x0                 },        /* SHLLV[_S].PH */
17275     { instruction         , 0                   , 0   , 32,
17276        0xfc0003ff, 0x20000395, &SHLLV_QB         , 0,
17277        DSP_                },        /* SHLLV.QB */
17278     { reserved_block      , 0                   , 0   , 32,
17279        0xfc0003ff, 0x2000039d, 0                      , 0,
17280        0x0                 },        /* _POOL32A5~*(115) */
17281     { reserved_block      , 0                   , 0   , 32,
17282        0xfc0003ff, 0x200003a5, 0                      , 0,
17283        0x0                 },        /* _POOL32A5~*(116) */
17284     { reserved_block      , 0                   , 0   , 32,
17285        0xfc0003ff, 0x200003ad, 0                      , 0,
17286        0x0                 },        /* _POOL32A5~*(117) */
17287     { pool                , SHLL__S__PH         , 4   , 32,
17288        0xfc0003ff, 0x200003b5, 0                      , 0,
17289        0x0                 },        /* SHLL[_S].PH */
17290     { reserved_block      , 0                   , 0   , 32,
17291        0xfc0003ff, 0x200003bd, 0                      , 0,
17292        0x0                 },        /* _POOL32A5~*(119) */
17293     { instruction         , 0                   , 0   , 32,
17294        0xfc0003ff, 0x200003c5, &ADDWC            , 0,
17295        DSP_                },        /* ADDWC */
17296     { pool                , PRECR_SRA__R__PH_W  , 2   , 32,
17297        0xfc0003ff, 0x200003cd, 0                      , 0,
17298        0x0                 },        /* PRECR_SRA[_R].PH.W */
17299     { instruction         , 0                   , 0   , 32,
17300        0xfc0003ff, 0x200003d5, &SHLLV_S_W        , 0,
17301        DSP_                },        /* SHLLV_S.W */
17302     { reserved_block      , 0                   , 0   , 32,
17303        0xfc0003ff, 0x200003dd, 0                      , 0,
17304        0x0                 },        /* _POOL32A5~*(123) */
17305     { reserved_block      , 0                   , 0   , 32,
17306        0xfc0003ff, 0x200003e5, 0                      , 0,
17307        0x0                 },        /* _POOL32A5~*(124) */
17308     { reserved_block      , 0                   , 0   , 32,
17309        0xfc0003ff, 0x200003ed, 0                      , 0,
17310        0x0                 },        /* _POOL32A5~*(125) */
17311     { instruction         , 0                   , 0   , 32,
17312        0xfc0003ff, 0x200003f5, &SHLL_S_W         , 0,
17313        DSP_                },        /* SHLL_S.W */
17314     { reserved_block      , 0                   , 0   , 32,
17315        0xfc0003ff, 0x200003fd, 0                      , 0,
17316        0x0                 },        /* _POOL32A5~*(127) */
17317 };
17318 
17319 
17320 static const Pool PP_LSX[16] = {
17321     { instruction         , 0                   , 0   , 32,
17322        0xfc0007ff, 0x20000007, &LBX              , 0,
17323        0x0                 },        /* LBX */
17324     { instruction         , 0                   , 0   , 32,
17325        0xfc0007ff, 0x20000087, &SBX              , 0,
17326        XMMS_               },        /* SBX */
17327     { instruction         , 0                   , 0   , 32,
17328        0xfc0007ff, 0x20000107, &LBUX             , 0,
17329        0x0                 },        /* LBUX */
17330     { reserved_block      , 0                   , 0   , 32,
17331        0xfc0007ff, 0x20000187, 0                      , 0,
17332        0x0                 },        /* PP.LSX~*(3) */
17333     { instruction         , 0                   , 0   , 32,
17334        0xfc0007ff, 0x20000207, &LHX              , 0,
17335        0x0                 },        /* LHX */
17336     { instruction         , 0                   , 0   , 32,
17337        0xfc0007ff, 0x20000287, &SHX              , 0,
17338        XMMS_               },        /* SHX */
17339     { instruction         , 0                   , 0   , 32,
17340        0xfc0007ff, 0x20000307, &LHUX             , 0,
17341        0x0                 },        /* LHUX */
17342     { instruction         , 0                   , 0   , 32,
17343        0xfc0007ff, 0x20000387, &LWUX             , 0,
17344        MIPS64_             },        /* LWUX */
17345     { instruction         , 0                   , 0   , 32,
17346        0xfc0007ff, 0x20000407, &LWX              , 0,
17347        0x0                 },        /* LWX */
17348     { instruction         , 0                   , 0   , 32,
17349        0xfc0007ff, 0x20000487, &SWX              , 0,
17350        XMMS_               },        /* SWX */
17351     { instruction         , 0                   , 0   , 32,
17352        0xfc0007ff, 0x20000507, &LWC1X            , 0,
17353        CP1_                },        /* LWC1X */
17354     { instruction         , 0                   , 0   , 32,
17355        0xfc0007ff, 0x20000587, &SWC1X            , 0,
17356        CP1_                },        /* SWC1X */
17357     { instruction         , 0                   , 0   , 32,
17358        0xfc0007ff, 0x20000607, &LDX              , 0,
17359        MIPS64_             },        /* LDX */
17360     { instruction         , 0                   , 0   , 32,
17361        0xfc0007ff, 0x20000687, &SDX              , 0,
17362        MIPS64_             },        /* SDX */
17363     { instruction         , 0                   , 0   , 32,
17364        0xfc0007ff, 0x20000707, &LDC1X            , 0,
17365        CP1_                },        /* LDC1X */
17366     { instruction         , 0                   , 0   , 32,
17367        0xfc0007ff, 0x20000787, &SDC1X            , 0,
17368        CP1_                },        /* SDC1X */
17369 };
17370 
17371 
17372 static const Pool PP_LSXS[16] = {
17373     { reserved_block      , 0                   , 0   , 32,
17374        0xfc0007ff, 0x20000047, 0                      , 0,
17375        0x0                 },        /* PP.LSXS~*(0) */
17376     { reserved_block      , 0                   , 0   , 32,
17377        0xfc0007ff, 0x200000c7, 0                      , 0,
17378        0x0                 },        /* PP.LSXS~*(1) */
17379     { reserved_block      , 0                   , 0   , 32,
17380        0xfc0007ff, 0x20000147, 0                      , 0,
17381        0x0                 },        /* PP.LSXS~*(2) */
17382     { reserved_block      , 0                   , 0   , 32,
17383        0xfc0007ff, 0x200001c7, 0                      , 0,
17384        0x0                 },        /* PP.LSXS~*(3) */
17385     { instruction         , 0                   , 0   , 32,
17386        0xfc0007ff, 0x20000247, &LHXS             , 0,
17387        0x0                 },        /* LHXS */
17388     { instruction         , 0                   , 0   , 32,
17389        0xfc0007ff, 0x200002c7, &SHXS             , 0,
17390        XMMS_               },        /* SHXS */
17391     { instruction         , 0                   , 0   , 32,
17392        0xfc0007ff, 0x20000347, &LHUXS            , 0,
17393        0x0                 },        /* LHUXS */
17394     { instruction         , 0                   , 0   , 32,
17395        0xfc0007ff, 0x200003c7, &LWUXS            , 0,
17396        MIPS64_             },        /* LWUXS */
17397     { instruction         , 0                   , 0   , 32,
17398        0xfc0007ff, 0x20000447, &LWXS_32_         , 0,
17399        0x0                 },        /* LWXS[32] */
17400     { instruction         , 0                   , 0   , 32,
17401        0xfc0007ff, 0x200004c7, &SWXS             , 0,
17402        XMMS_               },        /* SWXS */
17403     { instruction         , 0                   , 0   , 32,
17404        0xfc0007ff, 0x20000547, &LWC1XS           , 0,
17405        CP1_                },        /* LWC1XS */
17406     { instruction         , 0                   , 0   , 32,
17407        0xfc0007ff, 0x200005c7, &SWC1XS           , 0,
17408        CP1_                },        /* SWC1XS */
17409     { instruction         , 0                   , 0   , 32,
17410        0xfc0007ff, 0x20000647, &LDXS             , 0,
17411        MIPS64_             },        /* LDXS */
17412     { instruction         , 0                   , 0   , 32,
17413        0xfc0007ff, 0x200006c7, &SDXS             , 0,
17414        MIPS64_             },        /* SDXS */
17415     { instruction         , 0                   , 0   , 32,
17416        0xfc0007ff, 0x20000747, &LDC1XS           , 0,
17417        CP1_                },        /* LDC1XS */
17418     { instruction         , 0                   , 0   , 32,
17419        0xfc0007ff, 0x200007c7, &SDC1XS           , 0,
17420        CP1_                },        /* SDC1XS */
17421 };
17422 
17423 
17424 static const Pool P_LSX[2] = {
17425     { pool                , PP_LSX              , 16  , 32,
17426        0xfc00007f, 0x20000007, 0                      , 0,
17427        0x0                 },        /* PP.LSX */
17428     { pool                , PP_LSXS             , 16  , 32,
17429        0xfc00007f, 0x20000047, 0                      , 0,
17430        0x0                 },        /* PP.LSXS */
17431 };
17432 
17433 
17434 static const Pool POOL32Axf_1_0[4] = {
17435     { instruction         , 0                   , 0   , 32,
17436        0xfc003fff, 0x2000007f, &MFHI_DSP_        , 0,
17437        DSP_                },        /* MFHI[DSP] */
17438     { instruction         , 0                   , 0   , 32,
17439        0xfc003fff, 0x2000107f, &MFLO_DSP_        , 0,
17440        DSP_                },        /* MFLO[DSP] */
17441     { instruction         , 0                   , 0   , 32,
17442        0xfc003fff, 0x2000207f, &MTHI_DSP_        , 0,
17443        DSP_                },        /* MTHI[DSP] */
17444     { instruction         , 0                   , 0   , 32,
17445        0xfc003fff, 0x2000307f, &MTLO_DSP_        , 0,
17446        DSP_                },        /* MTLO[DSP] */
17447 };
17448 
17449 
17450 static const Pool POOL32Axf_1_1[4] = {
17451     { instruction         , 0                   , 0   , 32,
17452        0xfc003fff, 0x2000027f, &MTHLIP           , 0,
17453        DSP_                },        /* MTHLIP */
17454     { instruction         , 0                   , 0   , 32,
17455        0xfc003fff, 0x2000127f, &SHILOV           , 0,
17456        DSP_                },        /* SHILOV */
17457     { reserved_block      , 0                   , 0   , 32,
17458        0xfc003fff, 0x2000227f, 0                      , 0,
17459        0x0                 },        /* POOL32Axf_1_1~*(2) */
17460     { reserved_block      , 0                   , 0   , 32,
17461        0xfc003fff, 0x2000327f, 0                      , 0,
17462        0x0                 },        /* POOL32Axf_1_1~*(3) */
17463 };
17464 
17465 
17466 static const Pool POOL32Axf_1_3[4] = {
17467     { instruction         , 0                   , 0   , 32,
17468        0xfc003fff, 0x2000067f, &RDDSP            , 0,
17469        DSP_                },        /* RDDSP */
17470     { instruction         , 0                   , 0   , 32,
17471        0xfc003fff, 0x2000167f, &WRDSP            , 0,
17472        DSP_                },        /* WRDSP */
17473     { instruction         , 0                   , 0   , 32,
17474        0xfc003fff, 0x2000267f, &EXTP             , 0,
17475        DSP_                },        /* EXTP */
17476     { instruction         , 0                   , 0   , 32,
17477        0xfc003fff, 0x2000367f, &EXTPDP           , 0,
17478        DSP_                },        /* EXTPDP */
17479 };
17480 
17481 
17482 static const Pool POOL32Axf_1_4[2] = {
17483     { instruction         , 0                   , 0   , 32,
17484        0xfc001fff, 0x2000087f, &SHLL_QB          , 0,
17485        DSP_                },        /* SHLL.QB */
17486     { instruction         , 0                   , 0   , 32,
17487        0xfc001fff, 0x2000187f, &SHRL_QB          , 0,
17488        DSP_                },        /* SHRL.QB */
17489 };
17490 
17491 
17492 static const Pool MAQ_S_A__W_PHR[2] = {
17493     { instruction         , 0                   , 0   , 32,
17494        0xfc003fff, 0x20000a7f, &MAQ_S_W_PHR      , 0,
17495        DSP_                },        /* MAQ_S.W.PHR */
17496     { instruction         , 0                   , 0   , 32,
17497        0xfc003fff, 0x20002a7f, &MAQ_SA_W_PHR     , 0,
17498        DSP_                },        /* MAQ_SA.W.PHR */
17499 };
17500 
17501 
17502 static const Pool MAQ_S_A__W_PHL[2] = {
17503     { instruction         , 0                   , 0   , 32,
17504        0xfc003fff, 0x20001a7f, &MAQ_S_W_PHL      , 0,
17505        DSP_                },        /* MAQ_S.W.PHL */
17506     { instruction         , 0                   , 0   , 32,
17507        0xfc003fff, 0x20003a7f, &MAQ_SA_W_PHL     , 0,
17508        DSP_                },        /* MAQ_SA.W.PHL */
17509 };
17510 
17511 
17512 static const Pool POOL32Axf_1_5[2] = {
17513     { pool                , MAQ_S_A__W_PHR      , 2   , 32,
17514        0xfc001fff, 0x20000a7f, 0                      , 0,
17515        0x0                 },        /* MAQ_S[A].W.PHR */
17516     { pool                , MAQ_S_A__W_PHL      , 2   , 32,
17517        0xfc001fff, 0x20001a7f, 0                      , 0,
17518        0x0                 },        /* MAQ_S[A].W.PHL */
17519 };
17520 
17521 
17522 static const Pool POOL32Axf_1_7[4] = {
17523     { instruction         , 0                   , 0   , 32,
17524        0xfc003fff, 0x20000e7f, &EXTR_W           , 0,
17525        DSP_                },        /* EXTR.W */
17526     { instruction         , 0                   , 0   , 32,
17527        0xfc003fff, 0x20001e7f, &EXTR_R_W         , 0,
17528        DSP_                },        /* EXTR_R.W */
17529     { instruction         , 0                   , 0   , 32,
17530        0xfc003fff, 0x20002e7f, &EXTR_RS_W        , 0,
17531        DSP_                },        /* EXTR_RS.W */
17532     { instruction         , 0                   , 0   , 32,
17533        0xfc003fff, 0x20003e7f, &EXTR_S_H         , 0,
17534        DSP_                },        /* EXTR_S.H */
17535 };
17536 
17537 
17538 static const Pool POOL32Axf_1[8] = {
17539     { pool                , POOL32Axf_1_0       , 4   , 32,
17540        0xfc000fff, 0x2000007f, 0                      , 0,
17541        0x0                 },        /* POOL32Axf_1_0 */
17542     { pool                , POOL32Axf_1_1       , 4   , 32,
17543        0xfc000fff, 0x2000027f, 0                      , 0,
17544        0x0                 },        /* POOL32Axf_1_1 */
17545     { reserved_block      , 0                   , 0   , 32,
17546        0xfc000fff, 0x2000047f, 0                      , 0,
17547        0x0                 },        /* POOL32Axf_1~*(2) */
17548     { pool                , POOL32Axf_1_3       , 4   , 32,
17549        0xfc000fff, 0x2000067f, 0                      , 0,
17550        0x0                 },        /* POOL32Axf_1_3 */
17551     { pool                , POOL32Axf_1_4       , 2   , 32,
17552        0xfc000fff, 0x2000087f, 0                      , 0,
17553        0x0                 },        /* POOL32Axf_1_4 */
17554     { pool                , POOL32Axf_1_5       , 2   , 32,
17555        0xfc000fff, 0x20000a7f, 0                      , 0,
17556        0x0                 },        /* POOL32Axf_1_5 */
17557     { reserved_block      , 0                   , 0   , 32,
17558        0xfc000fff, 0x20000c7f, 0                      , 0,
17559        0x0                 },        /* POOL32Axf_1~*(6) */
17560     { pool                , POOL32Axf_1_7       , 4   , 32,
17561        0xfc000fff, 0x20000e7f, 0                      , 0,
17562        0x0                 },        /* POOL32Axf_1_7 */
17563 };
17564 
17565 
17566 static const Pool POOL32Axf_2_DSP__0_7[8] = {
17567     { instruction         , 0                   , 0   , 32,
17568        0xfc003fff, 0x200000bf, &DPA_W_PH         , 0,
17569        DSP_                },        /* DPA.W.PH */
17570     { instruction         , 0                   , 0   , 32,
17571        0xfc003fff, 0x200002bf, &DPAQ_S_W_PH      , 0,
17572        DSP_                },        /* DPAQ_S.W.PH */
17573     { instruction         , 0                   , 0   , 32,
17574        0xfc003fff, 0x200004bf, &DPS_W_PH         , 0,
17575        DSP_                },        /* DPS.W.PH */
17576     { instruction         , 0                   , 0   , 32,
17577        0xfc003fff, 0x200006bf, &DPSQ_S_W_PH      , 0,
17578        DSP_                },        /* DPSQ_S.W.PH */
17579     { reserved_block      , 0                   , 0   , 32,
17580        0xfc003fff, 0x200008bf, 0                      , 0,
17581        0x0                 },        /* POOL32Axf_2(DSP)_0_7~*(4) */
17582     { instruction         , 0                   , 0   , 32,
17583        0xfc003fff, 0x20000abf, &MADD_DSP_        , 0,
17584        DSP_                },        /* MADD[DSP] */
17585     { instruction         , 0                   , 0   , 32,
17586        0xfc003fff, 0x20000cbf, &MULT_DSP_        , 0,
17587        DSP_                },        /* MULT[DSP] */
17588     { instruction         , 0                   , 0   , 32,
17589        0xfc003fff, 0x20000ebf, &EXTRV_W          , 0,
17590        DSP_                },        /* EXTRV.W */
17591 };
17592 
17593 
17594 static const Pool POOL32Axf_2_DSP__8_15[8] = {
17595     { instruction         , 0                   , 0   , 32,
17596        0xfc003fff, 0x200010bf, &DPAX_W_PH        , 0,
17597        DSP_                },        /* DPAX.W.PH */
17598     { instruction         , 0                   , 0   , 32,
17599        0xfc003fff, 0x200012bf, &DPAQ_SA_L_W      , 0,
17600        DSP_                },        /* DPAQ_SA.L.W */
17601     { instruction         , 0                   , 0   , 32,
17602        0xfc003fff, 0x200014bf, &DPSX_W_PH        , 0,
17603        DSP_                },        /* DPSX.W.PH */
17604     { instruction         , 0                   , 0   , 32,
17605        0xfc003fff, 0x200016bf, &DPSQ_SA_L_W      , 0,
17606        DSP_                },        /* DPSQ_SA.L.W */
17607     { reserved_block      , 0                   , 0   , 32,
17608        0xfc003fff, 0x200018bf, 0                      , 0,
17609        0x0                 },        /* POOL32Axf_2(DSP)_8_15~*(4) */
17610     { instruction         , 0                   , 0   , 32,
17611        0xfc003fff, 0x20001abf, &MADDU_DSP_       , 0,
17612        DSP_                },        /* MADDU[DSP] */
17613     { instruction         , 0                   , 0   , 32,
17614        0xfc003fff, 0x20001cbf, &MULTU_DSP_       , 0,
17615        DSP_                },        /* MULTU[DSP] */
17616     { instruction         , 0                   , 0   , 32,
17617        0xfc003fff, 0x20001ebf, &EXTRV_R_W        , 0,
17618        DSP_                },        /* EXTRV_R.W */
17619 };
17620 
17621 
17622 static const Pool POOL32Axf_2_DSP__16_23[8] = {
17623     { instruction         , 0                   , 0   , 32,
17624        0xfc003fff, 0x200020bf, &DPAU_H_QBL       , 0,
17625        DSP_                },        /* DPAU.H.QBL */
17626     { instruction         , 0                   , 0   , 32,
17627        0xfc003fff, 0x200022bf, &DPAQX_S_W_PH     , 0,
17628        DSP_                },        /* DPAQX_S.W.PH */
17629     { instruction         , 0                   , 0   , 32,
17630        0xfc003fff, 0x200024bf, &DPSU_H_QBL       , 0,
17631        DSP_                },        /* DPSU.H.QBL */
17632     { instruction         , 0                   , 0   , 32,
17633        0xfc003fff, 0x200026bf, &DPSQX_S_W_PH     , 0,
17634        DSP_                },        /* DPSQX_S.W.PH */
17635     { instruction         , 0                   , 0   , 32,
17636        0xfc003fff, 0x200028bf, &EXTPV            , 0,
17637        DSP_                },        /* EXTPV */
17638     { instruction         , 0                   , 0   , 32,
17639        0xfc003fff, 0x20002abf, &MSUB_DSP_        , 0,
17640        DSP_                },        /* MSUB[DSP] */
17641     { instruction         , 0                   , 0   , 32,
17642        0xfc003fff, 0x20002cbf, &MULSA_W_PH       , 0,
17643        DSP_                },        /* MULSA.W.PH */
17644     { instruction         , 0                   , 0   , 32,
17645        0xfc003fff, 0x20002ebf, &EXTRV_RS_W       , 0,
17646        DSP_                },        /* EXTRV_RS.W */
17647 };
17648 
17649 
17650 static const Pool POOL32Axf_2_DSP__24_31[8] = {
17651     { instruction         , 0                   , 0   , 32,
17652        0xfc003fff, 0x200030bf, &DPAU_H_QBR       , 0,
17653        DSP_                },        /* DPAU.H.QBR */
17654     { instruction         , 0                   , 0   , 32,
17655        0xfc003fff, 0x200032bf, &DPAQX_SA_W_PH    , 0,
17656        DSP_                },        /* DPAQX_SA.W.PH */
17657     { instruction         , 0                   , 0   , 32,
17658        0xfc003fff, 0x200034bf, &DPSU_H_QBR       , 0,
17659        DSP_                },        /* DPSU.H.QBR */
17660     { instruction         , 0                   , 0   , 32,
17661        0xfc003fff, 0x200036bf, &DPSQX_SA_W_PH    , 0,
17662        DSP_                },        /* DPSQX_SA.W.PH */
17663     { instruction         , 0                   , 0   , 32,
17664        0xfc003fff, 0x200038bf, &EXTPDPV          , 0,
17665        DSP_                },        /* EXTPDPV */
17666     { instruction         , 0                   , 0   , 32,
17667        0xfc003fff, 0x20003abf, &MSUBU_DSP_       , 0,
17668        DSP_                },        /* MSUBU[DSP] */
17669     { instruction         , 0                   , 0   , 32,
17670        0xfc003fff, 0x20003cbf, &MULSAQ_S_W_PH    , 0,
17671        DSP_                },        /* MULSAQ_S.W.PH */
17672     { instruction         , 0                   , 0   , 32,
17673        0xfc003fff, 0x20003ebf, &EXTRV_S_H        , 0,
17674        DSP_                },        /* EXTRV_S.H */
17675 };
17676 
17677 
17678 static const Pool POOL32Axf_2[4] = {
17679     { pool                , POOL32Axf_2_DSP__0_7, 8   , 32,
17680        0xfc0031ff, 0x200000bf, 0                      , 0,
17681        0x0                 },        /* POOL32Axf_2(DSP)_0_7 */
17682     { pool                , POOL32Axf_2_DSP__8_15, 8   , 32,
17683        0xfc0031ff, 0x200010bf, 0                      , 0,
17684        0x0                 },        /* POOL32Axf_2(DSP)_8_15 */
17685     { pool                , POOL32Axf_2_DSP__16_23, 8   , 32,
17686        0xfc0031ff, 0x200020bf, 0                      , 0,
17687        0x0                 },        /* POOL32Axf_2(DSP)_16_23 */
17688     { pool                , POOL32Axf_2_DSP__24_31, 8   , 32,
17689        0xfc0031ff, 0x200030bf, 0                      , 0,
17690        0x0                 },        /* POOL32Axf_2(DSP)_24_31 */
17691 };
17692 
17693 
17694 static const Pool POOL32Axf_4[128] = {
17695     { instruction         , 0                   , 0   , 32,
17696        0xfc00ffff, 0x2000013f, &ABSQ_S_QB        , 0,
17697        DSP_                },        /* ABSQ_S.QB */
17698     { instruction         , 0                   , 0   , 32,
17699        0xfc00ffff, 0x2000033f, &REPLV_PH         , 0,
17700        DSP_                },        /* REPLV.PH */
17701     { reserved_block      , 0                   , 0   , 32,
17702        0xfc00ffff, 0x2000053f, 0                      , 0,
17703        0x0                 },        /* POOL32Axf_4~*(2) */
17704     { reserved_block      , 0                   , 0   , 32,
17705        0xfc00ffff, 0x2000073f, 0                      , 0,
17706        0x0                 },        /* POOL32Axf_4~*(3) */
17707     { reserved_block      , 0                   , 0   , 32,
17708        0xfc00ffff, 0x2000093f, 0                      , 0,
17709        0x0                 },        /* POOL32Axf_4~*(4) */
17710     { reserved_block      , 0                   , 0   , 32,
17711        0xfc00ffff, 0x20000b3f, 0                      , 0,
17712        0x0                 },        /* POOL32Axf_4~*(5) */
17713     { reserved_block      , 0                   , 0   , 32,
17714        0xfc00ffff, 0x20000d3f, 0                      , 0,
17715        0x0                 },        /* POOL32Axf_4~*(6) */
17716     { reserved_block      , 0                   , 0   , 32,
17717        0xfc00ffff, 0x20000f3f, 0                      , 0,
17718        0x0                 },        /* POOL32Axf_4~*(7) */
17719     { instruction         , 0                   , 0   , 32,
17720        0xfc00ffff, 0x2000113f, &ABSQ_S_PH        , 0,
17721        DSP_                },        /* ABSQ_S.PH */
17722     { instruction         , 0                   , 0   , 32,
17723        0xfc00ffff, 0x2000133f, &REPLV_QB         , 0,
17724        DSP_                },        /* REPLV.QB */
17725     { reserved_block      , 0                   , 0   , 32,
17726        0xfc00ffff, 0x2000153f, 0                      , 0,
17727        0x0                 },        /* POOL32Axf_4~*(10) */
17728     { reserved_block      , 0                   , 0   , 32,
17729        0xfc00ffff, 0x2000173f, 0                      , 0,
17730        0x0                 },        /* POOL32Axf_4~*(11) */
17731     { reserved_block      , 0                   , 0   , 32,
17732        0xfc00ffff, 0x2000193f, 0                      , 0,
17733        0x0                 },        /* POOL32Axf_4~*(12) */
17734     { reserved_block      , 0                   , 0   , 32,
17735        0xfc00ffff, 0x20001b3f, 0                      , 0,
17736        0x0                 },        /* POOL32Axf_4~*(13) */
17737     { reserved_block      , 0                   , 0   , 32,
17738        0xfc00ffff, 0x20001d3f, 0                      , 0,
17739        0x0                 },        /* POOL32Axf_4~*(14) */
17740     { reserved_block      , 0                   , 0   , 32,
17741        0xfc00ffff, 0x20001f3f, 0                      , 0,
17742        0x0                 },        /* POOL32Axf_4~*(15) */
17743     { instruction         , 0                   , 0   , 32,
17744        0xfc00ffff, 0x2000213f, &ABSQ_S_W         , 0,
17745        DSP_                },        /* ABSQ_S.W */
17746     { reserved_block      , 0                   , 0   , 32,
17747        0xfc00ffff, 0x2000233f, 0                      , 0,
17748        0x0                 },        /* POOL32Axf_4~*(17) */
17749     { reserved_block      , 0                   , 0   , 32,
17750        0xfc00ffff, 0x2000253f, 0                      , 0,
17751        0x0                 },        /* POOL32Axf_4~*(18) */
17752     { reserved_block      , 0                   , 0   , 32,
17753        0xfc00ffff, 0x2000273f, 0                      , 0,
17754        0x0                 },        /* POOL32Axf_4~*(19) */
17755     { reserved_block      , 0                   , 0   , 32,
17756        0xfc00ffff, 0x2000293f, 0                      , 0,
17757        0x0                 },        /* POOL32Axf_4~*(20) */
17758     { reserved_block      , 0                   , 0   , 32,
17759        0xfc00ffff, 0x20002b3f, 0                      , 0,
17760        0x0                 },        /* POOL32Axf_4~*(21) */
17761     { reserved_block      , 0                   , 0   , 32,
17762        0xfc00ffff, 0x20002d3f, 0                      , 0,
17763        0x0                 },        /* POOL32Axf_4~*(22) */
17764     { reserved_block      , 0                   , 0   , 32,
17765        0xfc00ffff, 0x20002f3f, 0                      , 0,
17766        0x0                 },        /* POOL32Axf_4~*(23) */
17767     { reserved_block      , 0                   , 0   , 32,
17768        0xfc00ffff, 0x2000313f, 0                      , 0,
17769        0x0                 },        /* POOL32Axf_4~*(24) */
17770     { reserved_block      , 0                   , 0   , 32,
17771        0xfc00ffff, 0x2000333f, 0                      , 0,
17772        0x0                 },        /* POOL32Axf_4~*(25) */
17773     { reserved_block      , 0                   , 0   , 32,
17774        0xfc00ffff, 0x2000353f, 0                      , 0,
17775        0x0                 },        /* POOL32Axf_4~*(26) */
17776     { reserved_block      , 0                   , 0   , 32,
17777        0xfc00ffff, 0x2000373f, 0                      , 0,
17778        0x0                 },        /* POOL32Axf_4~*(27) */
17779     { reserved_block      , 0                   , 0   , 32,
17780        0xfc00ffff, 0x2000393f, 0                      , 0,
17781        0x0                 },        /* POOL32Axf_4~*(28) */
17782     { reserved_block      , 0                   , 0   , 32,
17783        0xfc00ffff, 0x20003b3f, 0                      , 0,
17784        0x0                 },        /* POOL32Axf_4~*(29) */
17785     { reserved_block      , 0                   , 0   , 32,
17786        0xfc00ffff, 0x20003d3f, 0                      , 0,
17787        0x0                 },        /* POOL32Axf_4~*(30) */
17788     { reserved_block      , 0                   , 0   , 32,
17789        0xfc00ffff, 0x20003f3f, 0                      , 0,
17790        0x0                 },        /* POOL32Axf_4~*(31) */
17791     { instruction         , 0                   , 0   , 32,
17792        0xfc00ffff, 0x2000413f, &INSV             , 0,
17793        DSP_                },        /* INSV */
17794     { reserved_block      , 0                   , 0   , 32,
17795        0xfc00ffff, 0x2000433f, 0                      , 0,
17796        0x0                 },        /* POOL32Axf_4~*(33) */
17797     { reserved_block      , 0                   , 0   , 32,
17798        0xfc00ffff, 0x2000453f, 0                      , 0,
17799        0x0                 },        /* POOL32Axf_4~*(34) */
17800     { reserved_block      , 0                   , 0   , 32,
17801        0xfc00ffff, 0x2000473f, 0                      , 0,
17802        0x0                 },        /* POOL32Axf_4~*(35) */
17803     { reserved_block      , 0                   , 0   , 32,
17804        0xfc00ffff, 0x2000493f, 0                      , 0,
17805        0x0                 },        /* POOL32Axf_4~*(36) */
17806     { instruction         , 0                   , 0   , 32,
17807        0xfc00ffff, 0x20004b3f, &CLO              , 0,
17808        XMMS_               },        /* CLO */
17809     { instruction         , 0                   , 0   , 32,
17810        0xfc00ffff, 0x20004d3f, &MFC2             , 0,
17811        CP2_                },        /* MFC2 */
17812     { reserved_block      , 0                   , 0   , 32,
17813        0xfc00ffff, 0x20004f3f, 0                      , 0,
17814        0x0                 },        /* POOL32Axf_4~*(39) */
17815     { instruction         , 0                   , 0   , 32,
17816        0xfc00ffff, 0x2000513f, &PRECEQ_W_PHL     , 0,
17817        DSP_                },        /* PRECEQ.W.PHL */
17818     { reserved_block      , 0                   , 0   , 32,
17819        0xfc00ffff, 0x2000533f, 0                      , 0,
17820        0x0                 },        /* POOL32Axf_4~*(41) */
17821     { reserved_block      , 0                   , 0   , 32,
17822        0xfc00ffff, 0x2000553f, 0                      , 0,
17823        0x0                 },        /* POOL32Axf_4~*(42) */
17824     { reserved_block      , 0                   , 0   , 32,
17825        0xfc00ffff, 0x2000573f, 0                      , 0,
17826        0x0                 },        /* POOL32Axf_4~*(43) */
17827     { reserved_block      , 0                   , 0   , 32,
17828        0xfc00ffff, 0x2000593f, 0                      , 0,
17829        0x0                 },        /* POOL32Axf_4~*(44) */
17830     { instruction         , 0                   , 0   , 32,
17831        0xfc00ffff, 0x20005b3f, &CLZ              , 0,
17832        XMMS_               },        /* CLZ */
17833     { instruction         , 0                   , 0   , 32,
17834        0xfc00ffff, 0x20005d3f, &MTC2             , 0,
17835        CP2_                },        /* MTC2 */
17836     { reserved_block      , 0                   , 0   , 32,
17837        0xfc00ffff, 0x20005f3f, 0                      , 0,
17838        0x0                 },        /* POOL32Axf_4~*(47) */
17839     { instruction         , 0                   , 0   , 32,
17840        0xfc00ffff, 0x2000613f, &PRECEQ_W_PHR     , 0,
17841        DSP_                },        /* PRECEQ.W.PHR */
17842     { reserved_block      , 0                   , 0   , 32,
17843        0xfc00ffff, 0x2000633f, 0                      , 0,
17844        0x0                 },        /* POOL32Axf_4~*(49) */
17845     { reserved_block      , 0                   , 0   , 32,
17846        0xfc00ffff, 0x2000653f, 0                      , 0,
17847        0x0                 },        /* POOL32Axf_4~*(50) */
17848     { reserved_block      , 0                   , 0   , 32,
17849        0xfc00ffff, 0x2000673f, 0                      , 0,
17850        0x0                 },        /* POOL32Axf_4~*(51) */
17851     { reserved_block      , 0                   , 0   , 32,
17852        0xfc00ffff, 0x2000693f, 0                      , 0,
17853        0x0                 },        /* POOL32Axf_4~*(52) */
17854     { reserved_block      , 0                   , 0   , 32,
17855        0xfc00ffff, 0x20006b3f, 0                      , 0,
17856        0x0                 },        /* POOL32Axf_4~*(53) */
17857     { instruction         , 0                   , 0   , 32,
17858        0xfc00ffff, 0x20006d3f, &DMFC2            , 0,
17859        CP2_                },        /* DMFC2 */
17860     { reserved_block      , 0                   , 0   , 32,
17861        0xfc00ffff, 0x20006f3f, 0                      , 0,
17862        0x0                 },        /* POOL32Axf_4~*(55) */
17863     { instruction         , 0                   , 0   , 32,
17864        0xfc00ffff, 0x2000713f, &PRECEQU_PH_QBL   , 0,
17865        DSP_                },        /* PRECEQU.PH.QBL */
17866     { instruction         , 0                   , 0   , 32,
17867        0xfc00ffff, 0x2000733f, &PRECEQU_PH_QBLA  , 0,
17868        DSP_                },        /* PRECEQU.PH.QBLA */
17869     { reserved_block      , 0                   , 0   , 32,
17870        0xfc00ffff, 0x2000753f, 0                      , 0,
17871        0x0                 },        /* POOL32Axf_4~*(58) */
17872     { reserved_block      , 0                   , 0   , 32,
17873        0xfc00ffff, 0x2000773f, 0                      , 0,
17874        0x0                 },        /* POOL32Axf_4~*(59) */
17875     { reserved_block      , 0                   , 0   , 32,
17876        0xfc00ffff, 0x2000793f, 0                      , 0,
17877        0x0                 },        /* POOL32Axf_4~*(60) */
17878     { reserved_block      , 0                   , 0   , 32,
17879        0xfc00ffff, 0x20007b3f, 0                      , 0,
17880        0x0                 },        /* POOL32Axf_4~*(61) */
17881     { instruction         , 0                   , 0   , 32,
17882        0xfc00ffff, 0x20007d3f, &DMTC2            , 0,
17883        CP2_                },        /* DMTC2 */
17884     { reserved_block      , 0                   , 0   , 32,
17885        0xfc00ffff, 0x20007f3f, 0                      , 0,
17886        0x0                 },        /* POOL32Axf_4~*(63) */
17887     { reserved_block      , 0                   , 0   , 32,
17888        0xfc00ffff, 0x2000813f, 0                      , 0,
17889        0x0                 },        /* POOL32Axf_4~*(64) */
17890     { reserved_block      , 0                   , 0   , 32,
17891        0xfc00ffff, 0x2000833f, 0                      , 0,
17892        0x0                 },        /* POOL32Axf_4~*(65) */
17893     { reserved_block      , 0                   , 0   , 32,
17894        0xfc00ffff, 0x2000853f, 0                      , 0,
17895        0x0                 },        /* POOL32Axf_4~*(66) */
17896     { reserved_block      , 0                   , 0   , 32,
17897        0xfc00ffff, 0x2000873f, 0                      , 0,
17898        0x0                 },        /* POOL32Axf_4~*(67) */
17899     { reserved_block      , 0                   , 0   , 32,
17900        0xfc00ffff, 0x2000893f, 0                      , 0,
17901        0x0                 },        /* POOL32Axf_4~*(68) */
17902     { reserved_block      , 0                   , 0   , 32,
17903        0xfc00ffff, 0x20008b3f, 0                      , 0,
17904        0x0                 },        /* POOL32Axf_4~*(69) */
17905     { instruction         , 0                   , 0   , 32,
17906        0xfc00ffff, 0x20008d3f, &MFHC2            , 0,
17907        CP2_                },        /* MFHC2 */
17908     { reserved_block      , 0                   , 0   , 32,
17909        0xfc00ffff, 0x20008f3f, 0                      , 0,
17910        0x0                 },        /* POOL32Axf_4~*(71) */
17911     { instruction         , 0                   , 0   , 32,
17912        0xfc00ffff, 0x2000913f, &PRECEQU_PH_QBR   , 0,
17913        DSP_                },        /* PRECEQU.PH.QBR */
17914     { instruction         , 0                   , 0   , 32,
17915        0xfc00ffff, 0x2000933f, &PRECEQU_PH_QBRA  , 0,
17916        DSP_                },        /* PRECEQU.PH.QBRA */
17917     { reserved_block      , 0                   , 0   , 32,
17918        0xfc00ffff, 0x2000953f, 0                      , 0,
17919        0x0                 },        /* POOL32Axf_4~*(74) */
17920     { reserved_block      , 0                   , 0   , 32,
17921        0xfc00ffff, 0x2000973f, 0                      , 0,
17922        0x0                 },        /* POOL32Axf_4~*(75) */
17923     { reserved_block      , 0                   , 0   , 32,
17924        0xfc00ffff, 0x2000993f, 0                      , 0,
17925        0x0                 },        /* POOL32Axf_4~*(76) */
17926     { reserved_block      , 0                   , 0   , 32,
17927        0xfc00ffff, 0x20009b3f, 0                      , 0,
17928        0x0                 },        /* POOL32Axf_4~*(77) */
17929     { instruction         , 0                   , 0   , 32,
17930        0xfc00ffff, 0x20009d3f, &MTHC2            , 0,
17931        CP2_                },        /* MTHC2 */
17932     { reserved_block      , 0                   , 0   , 32,
17933        0xfc00ffff, 0x20009f3f, 0                      , 0,
17934        0x0                 },        /* POOL32Axf_4~*(79) */
17935     { reserved_block      , 0                   , 0   , 32,
17936        0xfc00ffff, 0x2000a13f, 0                      , 0,
17937        0x0                 },        /* POOL32Axf_4~*(80) */
17938     { reserved_block      , 0                   , 0   , 32,
17939        0xfc00ffff, 0x2000a33f, 0                      , 0,
17940        0x0                 },        /* POOL32Axf_4~*(81) */
17941     { reserved_block      , 0                   , 0   , 32,
17942        0xfc00ffff, 0x2000a53f, 0                      , 0,
17943        0x0                 },        /* POOL32Axf_4~*(82) */
17944     { reserved_block      , 0                   , 0   , 32,
17945        0xfc00ffff, 0x2000a73f, 0                      , 0,
17946        0x0                 },        /* POOL32Axf_4~*(83) */
17947     { reserved_block      , 0                   , 0   , 32,
17948        0xfc00ffff, 0x2000a93f, 0                      , 0,
17949        0x0                 },        /* POOL32Axf_4~*(84) */
17950     { reserved_block      , 0                   , 0   , 32,
17951        0xfc00ffff, 0x2000ab3f, 0                      , 0,
17952        0x0                 },        /* POOL32Axf_4~*(85) */
17953     { reserved_block      , 0                   , 0   , 32,
17954        0xfc00ffff, 0x2000ad3f, 0                      , 0,
17955        0x0                 },        /* POOL32Axf_4~*(86) */
17956     { reserved_block      , 0                   , 0   , 32,
17957        0xfc00ffff, 0x2000af3f, 0                      , 0,
17958        0x0                 },        /* POOL32Axf_4~*(87) */
17959     { instruction         , 0                   , 0   , 32,
17960        0xfc00ffff, 0x2000b13f, &PRECEU_PH_QBL    , 0,
17961        DSP_                },        /* PRECEU.PH.QBL */
17962     { instruction         , 0                   , 0   , 32,
17963        0xfc00ffff, 0x2000b33f, &PRECEU_PH_QBLA   , 0,
17964        DSP_                },        /* PRECEU.PH.QBLA */
17965     { reserved_block      , 0                   , 0   , 32,
17966        0xfc00ffff, 0x2000b53f, 0                      , 0,
17967        0x0                 },        /* POOL32Axf_4~*(90) */
17968     { reserved_block      , 0                   , 0   , 32,
17969        0xfc00ffff, 0x2000b73f, 0                      , 0,
17970        0x0                 },        /* POOL32Axf_4~*(91) */
17971     { reserved_block      , 0                   , 0   , 32,
17972        0xfc00ffff, 0x2000b93f, 0                      , 0,
17973        0x0                 },        /* POOL32Axf_4~*(92) */
17974     { reserved_block      , 0                   , 0   , 32,
17975        0xfc00ffff, 0x2000bb3f, 0                      , 0,
17976        0x0                 },        /* POOL32Axf_4~*(93) */
17977     { reserved_block      , 0                   , 0   , 32,
17978        0xfc00ffff, 0x2000bd3f, 0                      , 0,
17979        0x0                 },        /* POOL32Axf_4~*(94) */
17980     { reserved_block      , 0                   , 0   , 32,
17981        0xfc00ffff, 0x2000bf3f, 0                      , 0,
17982        0x0                 },        /* POOL32Axf_4~*(95) */
17983     { reserved_block      , 0                   , 0   , 32,
17984        0xfc00ffff, 0x2000c13f, 0                      , 0,
17985        0x0                 },        /* POOL32Axf_4~*(96) */
17986     { reserved_block      , 0                   , 0   , 32,
17987        0xfc00ffff, 0x2000c33f, 0                      , 0,
17988        0x0                 },        /* POOL32Axf_4~*(97) */
17989     { reserved_block      , 0                   , 0   , 32,
17990        0xfc00ffff, 0x2000c53f, 0                      , 0,
17991        0x0                 },        /* POOL32Axf_4~*(98) */
17992     { reserved_block      , 0                   , 0   , 32,
17993        0xfc00ffff, 0x2000c73f, 0                      , 0,
17994        0x0                 },        /* POOL32Axf_4~*(99) */
17995     { reserved_block      , 0                   , 0   , 32,
17996        0xfc00ffff, 0x2000c93f, 0                      , 0,
17997        0x0                 },        /* POOL32Axf_4~*(100) */
17998     { reserved_block      , 0                   , 0   , 32,
17999        0xfc00ffff, 0x2000cb3f, 0                      , 0,
18000        0x0                 },        /* POOL32Axf_4~*(101) */
18001     { instruction         , 0                   , 0   , 32,
18002        0xfc00ffff, 0x2000cd3f, &CFC2             , 0,
18003        CP2_                },        /* CFC2 */
18004     { reserved_block      , 0                   , 0   , 32,
18005        0xfc00ffff, 0x2000cf3f, 0                      , 0,
18006        0x0                 },        /* POOL32Axf_4~*(103) */
18007     { instruction         , 0                   , 0   , 32,
18008        0xfc00ffff, 0x2000d13f, &PRECEU_PH_QBR    , 0,
18009        DSP_                },        /* PRECEU.PH.QBR */
18010     { instruction         , 0                   , 0   , 32,
18011        0xfc00ffff, 0x2000d33f, &PRECEU_PH_QBRA   , 0,
18012        DSP_                },        /* PRECEU.PH.QBRA */
18013     { reserved_block      , 0                   , 0   , 32,
18014        0xfc00ffff, 0x2000d53f, 0                      , 0,
18015        0x0                 },        /* POOL32Axf_4~*(106) */
18016     { reserved_block      , 0                   , 0   , 32,
18017        0xfc00ffff, 0x2000d73f, 0                      , 0,
18018        0x0                 },        /* POOL32Axf_4~*(107) */
18019     { reserved_block      , 0                   , 0   , 32,
18020        0xfc00ffff, 0x2000d93f, 0                      , 0,
18021        0x0                 },        /* POOL32Axf_4~*(108) */
18022     { reserved_block      , 0                   , 0   , 32,
18023        0xfc00ffff, 0x2000db3f, 0                      , 0,
18024        0x0                 },        /* POOL32Axf_4~*(109) */
18025     { instruction         , 0                   , 0   , 32,
18026        0xfc00ffff, 0x2000dd3f, &CTC2             , 0,
18027        CP2_                },        /* CTC2 */
18028     { reserved_block      , 0                   , 0   , 32,
18029        0xfc00ffff, 0x2000df3f, 0                      , 0,
18030        0x0                 },        /* POOL32Axf_4~*(111) */
18031     { reserved_block      , 0                   , 0   , 32,
18032        0xfc00ffff, 0x2000e13f, 0                      , 0,
18033        0x0                 },        /* POOL32Axf_4~*(112) */
18034     { reserved_block      , 0                   , 0   , 32,
18035        0xfc00ffff, 0x2000e33f, 0                      , 0,
18036        0x0                 },        /* POOL32Axf_4~*(113) */
18037     { reserved_block      , 0                   , 0   , 32,
18038        0xfc00ffff, 0x2000e53f, 0                      , 0,
18039        0x0                 },        /* POOL32Axf_4~*(114) */
18040     { reserved_block      , 0                   , 0   , 32,
18041        0xfc00ffff, 0x2000e73f, 0                      , 0,
18042        0x0                 },        /* POOL32Axf_4~*(115) */
18043     { reserved_block      , 0                   , 0   , 32,
18044        0xfc00ffff, 0x2000e93f, 0                      , 0,
18045        0x0                 },        /* POOL32Axf_4~*(116) */
18046     { reserved_block      , 0                   , 0   , 32,
18047        0xfc00ffff, 0x2000eb3f, 0                      , 0,
18048        0x0                 },        /* POOL32Axf_4~*(117) */
18049     { reserved_block      , 0                   , 0   , 32,
18050        0xfc00ffff, 0x2000ed3f, 0                      , 0,
18051        0x0                 },        /* POOL32Axf_4~*(118) */
18052     { reserved_block      , 0                   , 0   , 32,
18053        0xfc00ffff, 0x2000ef3f, 0                      , 0,
18054        0x0                 },        /* POOL32Axf_4~*(119) */
18055     { instruction         , 0                   , 0   , 32,
18056        0xfc00ffff, 0x2000f13f, &RADDU_W_QB       , 0,
18057        DSP_                },        /* RADDU.W.QB */
18058     { reserved_block      , 0                   , 0   , 32,
18059        0xfc00ffff, 0x2000f33f, 0                      , 0,
18060        0x0                 },        /* POOL32Axf_4~*(121) */
18061     { reserved_block      , 0                   , 0   , 32,
18062        0xfc00ffff, 0x2000f53f, 0                      , 0,
18063        0x0                 },        /* POOL32Axf_4~*(122) */
18064     { reserved_block      , 0                   , 0   , 32,
18065        0xfc00ffff, 0x2000f73f, 0                      , 0,
18066        0x0                 },        /* POOL32Axf_4~*(123) */
18067     { reserved_block      , 0                   , 0   , 32,
18068        0xfc00ffff, 0x2000f93f, 0                      , 0,
18069        0x0                 },        /* POOL32Axf_4~*(124) */
18070     { reserved_block      , 0                   , 0   , 32,
18071        0xfc00ffff, 0x2000fb3f, 0                      , 0,
18072        0x0                 },        /* POOL32Axf_4~*(125) */
18073     { reserved_block      , 0                   , 0   , 32,
18074        0xfc00ffff, 0x2000fd3f, 0                      , 0,
18075        0x0                 },        /* POOL32Axf_4~*(126) */
18076     { reserved_block      , 0                   , 0   , 32,
18077        0xfc00ffff, 0x2000ff3f, 0                      , 0,
18078        0x0                 },        /* POOL32Axf_4~*(127) */
18079 };
18080 
18081 
18082 static const Pool POOL32Axf_5_group0[32] = {
18083     { instruction         , 0                   , 0   , 32,
18084        0xfc00ffff, 0x2000017f, &TLBGP            , 0,
18085        CP0_ | VZ_ | TLB_   },        /* TLBGP */
18086     { instruction         , 0                   , 0   , 32,
18087        0xfc00ffff, 0x2000037f, &TLBP             , 0,
18088        CP0_ | TLB_         },        /* TLBP */
18089     { instruction         , 0                   , 0   , 32,
18090        0xfc00ffff, 0x2000057f, &TLBGINV          , 0,
18091        CP0_ | VZ_ | TLB_ | TLBINV_},        /* TLBGINV */
18092     { instruction         , 0                   , 0   , 32,
18093        0xfc00ffff, 0x2000077f, &TLBINV           , 0,
18094        CP0_ | TLB_ | TLBINV_},        /* TLBINV */
18095     { reserved_block      , 0                   , 0   , 32,
18096        0xfc00ffff, 0x2000097f, 0                      , 0,
18097        0x0                 },        /* POOL32Axf_5_group0~*(4) */
18098     { reserved_block      , 0                   , 0   , 32,
18099        0xfc00ffff, 0x20000b7f, 0                      , 0,
18100        0x0                 },        /* POOL32Axf_5_group0~*(5) */
18101     { reserved_block      , 0                   , 0   , 32,
18102        0xfc00ffff, 0x20000d7f, 0                      , 0,
18103        0x0                 },        /* POOL32Axf_5_group0~*(6) */
18104     { reserved_block      , 0                   , 0   , 32,
18105        0xfc00ffff, 0x20000f7f, 0                      , 0,
18106        0x0                 },        /* POOL32Axf_5_group0~*(7) */
18107     { instruction         , 0                   , 0   , 32,
18108        0xfc00ffff, 0x2000117f, &TLBGR            , 0,
18109        CP0_ | VZ_ | TLB_   },        /* TLBGR */
18110     { instruction         , 0                   , 0   , 32,
18111        0xfc00ffff, 0x2000137f, &TLBR             , 0,
18112        CP0_ | TLB_         },        /* TLBR */
18113     { instruction         , 0                   , 0   , 32,
18114        0xfc00ffff, 0x2000157f, &TLBGINVF         , 0,
18115        CP0_ | VZ_ | TLB_ | TLBINV_},        /* TLBGINVF */
18116     { instruction         , 0                   , 0   , 32,
18117        0xfc00ffff, 0x2000177f, &TLBINVF          , 0,
18118        CP0_ | TLB_ | TLBINV_},        /* TLBINVF */
18119     { reserved_block      , 0                   , 0   , 32,
18120        0xfc00ffff, 0x2000197f, 0                      , 0,
18121        0x0                 },        /* POOL32Axf_5_group0~*(12) */
18122     { reserved_block      , 0                   , 0   , 32,
18123        0xfc00ffff, 0x20001b7f, 0                      , 0,
18124        0x0                 },        /* POOL32Axf_5_group0~*(13) */
18125     { reserved_block      , 0                   , 0   , 32,
18126        0xfc00ffff, 0x20001d7f, 0                      , 0,
18127        0x0                 },        /* POOL32Axf_5_group0~*(14) */
18128     { reserved_block      , 0                   , 0   , 32,
18129        0xfc00ffff, 0x20001f7f, 0                      , 0,
18130        0x0                 },        /* POOL32Axf_5_group0~*(15) */
18131     { instruction         , 0                   , 0   , 32,
18132        0xfc00ffff, 0x2000217f, &TLBGWI           , 0,
18133        CP0_ | VZ_ | TLB_   },        /* TLBGWI */
18134     { instruction         , 0                   , 0   , 32,
18135        0xfc00ffff, 0x2000237f, &TLBWI            , 0,
18136        CP0_ | TLB_         },        /* TLBWI */
18137     { reserved_block      , 0                   , 0   , 32,
18138        0xfc00ffff, 0x2000257f, 0                      , 0,
18139        0x0                 },        /* POOL32Axf_5_group0~*(18) */
18140     { reserved_block      , 0                   , 0   , 32,
18141        0xfc00ffff, 0x2000277f, 0                      , 0,
18142        0x0                 },        /* POOL32Axf_5_group0~*(19) */
18143     { reserved_block      , 0                   , 0   , 32,
18144        0xfc00ffff, 0x2000297f, 0                      , 0,
18145        0x0                 },        /* POOL32Axf_5_group0~*(20) */
18146     { reserved_block      , 0                   , 0   , 32,
18147        0xfc00ffff, 0x20002b7f, 0                      , 0,
18148        0x0                 },        /* POOL32Axf_5_group0~*(21) */
18149     { reserved_block      , 0                   , 0   , 32,
18150        0xfc00ffff, 0x20002d7f, 0                      , 0,
18151        0x0                 },        /* POOL32Axf_5_group0~*(22) */
18152     { reserved_block      , 0                   , 0   , 32,
18153        0xfc00ffff, 0x20002f7f, 0                      , 0,
18154        0x0                 },        /* POOL32Axf_5_group0~*(23) */
18155     { instruction         , 0                   , 0   , 32,
18156        0xfc00ffff, 0x2000317f, &TLBGWR           , 0,
18157        CP0_ | VZ_ | TLB_   },        /* TLBGWR */
18158     { instruction         , 0                   , 0   , 32,
18159        0xfc00ffff, 0x2000337f, &TLBWR            , 0,
18160        CP0_ | TLB_         },        /* TLBWR */
18161     { reserved_block      , 0                   , 0   , 32,
18162        0xfc00ffff, 0x2000357f, 0                      , 0,
18163        0x0                 },        /* POOL32Axf_5_group0~*(26) */
18164     { reserved_block      , 0                   , 0   , 32,
18165        0xfc00ffff, 0x2000377f, 0                      , 0,
18166        0x0                 },        /* POOL32Axf_5_group0~*(27) */
18167     { reserved_block      , 0                   , 0   , 32,
18168        0xfc00ffff, 0x2000397f, 0                      , 0,
18169        0x0                 },        /* POOL32Axf_5_group0~*(28) */
18170     { reserved_block      , 0                   , 0   , 32,
18171        0xfc00ffff, 0x20003b7f, 0                      , 0,
18172        0x0                 },        /* POOL32Axf_5_group0~*(29) */
18173     { reserved_block      , 0                   , 0   , 32,
18174        0xfc00ffff, 0x20003d7f, 0                      , 0,
18175        0x0                 },        /* POOL32Axf_5_group0~*(30) */
18176     { reserved_block      , 0                   , 0   , 32,
18177        0xfc00ffff, 0x20003f7f, 0                      , 0,
18178        0x0                 },        /* POOL32Axf_5_group0~*(31) */
18179 };
18180 
18181 
18182 static const Pool POOL32Axf_5_group1[32] = {
18183     { reserved_block      , 0                   , 0   , 32,
18184        0xfc00ffff, 0x2000417f, 0                      , 0,
18185        0x0                 },        /* POOL32Axf_5_group1~*(0) */
18186     { reserved_block      , 0                   , 0   , 32,
18187        0xfc00ffff, 0x2000437f, 0                      , 0,
18188        0x0                 },        /* POOL32Axf_5_group1~*(1) */
18189     { reserved_block      , 0                   , 0   , 32,
18190        0xfc00ffff, 0x2000457f, 0                      , 0,
18191        0x0                 },        /* POOL32Axf_5_group1~*(2) */
18192     { instruction         , 0                   , 0   , 32,
18193        0xfc00ffff, 0x2000477f, &DI               , 0,
18194        0x0                 },        /* DI */
18195     { reserved_block      , 0                   , 0   , 32,
18196        0xfc00ffff, 0x2000497f, 0                      , 0,
18197        0x0                 },        /* POOL32Axf_5_group1~*(4) */
18198     { reserved_block      , 0                   , 0   , 32,
18199        0xfc00ffff, 0x20004b7f, 0                      , 0,
18200        0x0                 },        /* POOL32Axf_5_group1~*(5) */
18201     { reserved_block      , 0                   , 0   , 32,
18202        0xfc00ffff, 0x20004d7f, 0                      , 0,
18203        0x0                 },        /* POOL32Axf_5_group1~*(6) */
18204     { reserved_block      , 0                   , 0   , 32,
18205        0xfc00ffff, 0x20004f7f, 0                      , 0,
18206        0x0                 },        /* POOL32Axf_5_group1~*(7) */
18207     { reserved_block      , 0                   , 0   , 32,
18208        0xfc00ffff, 0x2000517f, 0                      , 0,
18209        0x0                 },        /* POOL32Axf_5_group1~*(8) */
18210     { reserved_block      , 0                   , 0   , 32,
18211        0xfc00ffff, 0x2000537f, 0                      , 0,
18212        0x0                 },        /* POOL32Axf_5_group1~*(9) */
18213     { reserved_block      , 0                   , 0   , 32,
18214        0xfc00ffff, 0x2000557f, 0                      , 0,
18215        0x0                 },        /* POOL32Axf_5_group1~*(10) */
18216     { instruction         , 0                   , 0   , 32,
18217        0xfc00ffff, 0x2000577f, &EI               , 0,
18218        0x0                 },        /* EI */
18219     { reserved_block      , 0                   , 0   , 32,
18220        0xfc00ffff, 0x2000597f, 0                      , 0,
18221        0x0                 },        /* POOL32Axf_5_group1~*(12) */
18222     { reserved_block      , 0                   , 0   , 32,
18223        0xfc00ffff, 0x20005b7f, 0                      , 0,
18224        0x0                 },        /* POOL32Axf_5_group1~*(13) */
18225     { reserved_block      , 0                   , 0   , 32,
18226        0xfc00ffff, 0x20005d7f, 0                      , 0,
18227        0x0                 },        /* POOL32Axf_5_group1~*(14) */
18228     { reserved_block      , 0                   , 0   , 32,
18229        0xfc00ffff, 0x20005f7f, 0                      , 0,
18230        0x0                 },        /* POOL32Axf_5_group1~*(15) */
18231     { reserved_block      , 0                   , 0   , 32,
18232        0xfc00ffff, 0x2000617f, 0                      , 0,
18233        0x0                 },        /* POOL32Axf_5_group1~*(16) */
18234     { reserved_block      , 0                   , 0   , 32,
18235        0xfc00ffff, 0x2000637f, 0                      , 0,
18236        0x0                 },        /* POOL32Axf_5_group1~*(17) */
18237     { reserved_block      , 0                   , 0   , 32,
18238        0xfc00ffff, 0x2000657f, 0                      , 0,
18239        0x0                 },        /* POOL32Axf_5_group1~*(18) */
18240     { reserved_block      , 0                   , 0   , 32,
18241        0xfc00ffff, 0x2000677f, 0                      , 0,
18242        0x0                 },        /* POOL32Axf_5_group1~*(19) */
18243     { reserved_block      , 0                   , 0   , 32,
18244        0xfc00ffff, 0x2000697f, 0                      , 0,
18245        0x0                 },        /* POOL32Axf_5_group1~*(20) */
18246     { reserved_block      , 0                   , 0   , 32,
18247        0xfc00ffff, 0x20006b7f, 0                      , 0,
18248        0x0                 },        /* POOL32Axf_5_group1~*(21) */
18249     { reserved_block      , 0                   , 0   , 32,
18250        0xfc00ffff, 0x20006d7f, 0                      , 0,
18251        0x0                 },        /* POOL32Axf_5_group1~*(22) */
18252     { reserved_block      , 0                   , 0   , 32,
18253        0xfc00ffff, 0x20006f7f, 0                      , 0,
18254        0x0                 },        /* POOL32Axf_5_group1~*(23) */
18255     { reserved_block      , 0                   , 0   , 32,
18256        0xfc00ffff, 0x2000717f, 0                      , 0,
18257        0x0                 },        /* POOL32Axf_5_group1~*(24) */
18258     { reserved_block      , 0                   , 0   , 32,
18259        0xfc00ffff, 0x2000737f, 0                      , 0,
18260        0x0                 },        /* POOL32Axf_5_group1~*(25) */
18261     { reserved_block      , 0                   , 0   , 32,
18262        0xfc00ffff, 0x2000757f, 0                      , 0,
18263        0x0                 },        /* POOL32Axf_5_group1~*(26) */
18264     { reserved_block      , 0                   , 0   , 32,
18265        0xfc00ffff, 0x2000777f, 0                      , 0,
18266        0x0                 },        /* POOL32Axf_5_group1~*(27) */
18267     { reserved_block      , 0                   , 0   , 32,
18268        0xfc00ffff, 0x2000797f, 0                      , 0,
18269        0x0                 },        /* POOL32Axf_5_group1~*(28) */
18270     { reserved_block      , 0                   , 0   , 32,
18271        0xfc00ffff, 0x20007b7f, 0                      , 0,
18272        0x0                 },        /* POOL32Axf_5_group1~*(29) */
18273     { reserved_block      , 0                   , 0   , 32,
18274        0xfc00ffff, 0x20007d7f, 0                      , 0,
18275        0x0                 },        /* POOL32Axf_5_group1~*(30) */
18276     { reserved_block      , 0                   , 0   , 32,
18277        0xfc00ffff, 0x20007f7f, 0                      , 0,
18278        0x0                 },        /* POOL32Axf_5_group1~*(31) */
18279 };
18280 
18281 
18282 static const Pool ERETx[2] = {
18283     { instruction         , 0                   , 0   , 32,
18284        0xfc01ffff, 0x2000f37f, &ERET             , 0,
18285        0x0                 },        /* ERET */
18286     { instruction         , 0                   , 0   , 32,
18287        0xfc01ffff, 0x2001f37f, &ERETNC           , 0,
18288        0x0                 },        /* ERETNC */
18289 };
18290 
18291 
18292 static const Pool POOL32Axf_5_group3[32] = {
18293     { reserved_block      , 0                   , 0   , 32,
18294        0xfc00ffff, 0x2000c17f, 0                      , 0,
18295        0x0                 },        /* POOL32Axf_5_group3~*(0) */
18296     { instruction         , 0                   , 0   , 32,
18297        0xfc00ffff, 0x2000c37f, &WAIT             , 0,
18298        0x0                 },        /* WAIT */
18299     { reserved_block      , 0                   , 0   , 32,
18300        0xfc00ffff, 0x2000c57f, 0                      , 0,
18301        0x0                 },        /* POOL32Axf_5_group3~*(2) */
18302     { reserved_block      , 0                   , 0   , 32,
18303        0xfc00ffff, 0x2000c77f, 0                      , 0,
18304        0x0                 },        /* POOL32Axf_5_group3~*(3) */
18305     { reserved_block      , 0                   , 0   , 32,
18306        0xfc00ffff, 0x2000c97f, 0                      , 0,
18307        0x0                 },        /* POOL32Axf_5_group3~*(4) */
18308     { reserved_block      , 0                   , 0   , 32,
18309        0xfc00ffff, 0x2000cb7f, 0                      , 0,
18310        0x0                 },        /* POOL32Axf_5_group3~*(5) */
18311     { reserved_block      , 0                   , 0   , 32,
18312        0xfc00ffff, 0x2000cd7f, 0                      , 0,
18313        0x0                 },        /* POOL32Axf_5_group3~*(6) */
18314     { reserved_block      , 0                   , 0   , 32,
18315        0xfc00ffff, 0x2000cf7f, 0                      , 0,
18316        0x0                 },        /* POOL32Axf_5_group3~*(7) */
18317     { reserved_block      , 0                   , 0   , 32,
18318        0xfc00ffff, 0x2000d17f, 0                      , 0,
18319        0x0                 },        /* POOL32Axf_5_group3~*(8) */
18320     { instruction         , 0                   , 0   , 32,
18321        0xfc00ffff, 0x2000d37f, &IRET             , 0,
18322        MCU_                },        /* IRET */
18323     { reserved_block      , 0                   , 0   , 32,
18324        0xfc00ffff, 0x2000d57f, 0                      , 0,
18325        0x0                 },        /* POOL32Axf_5_group3~*(10) */
18326     { reserved_block      , 0                   , 0   , 32,
18327        0xfc00ffff, 0x2000d77f, 0                      , 0,
18328        0x0                 },        /* POOL32Axf_5_group3~*(11) */
18329     { reserved_block      , 0                   , 0   , 32,
18330        0xfc00ffff, 0x2000d97f, 0                      , 0,
18331        0x0                 },        /* POOL32Axf_5_group3~*(12) */
18332     { reserved_block      , 0                   , 0   , 32,
18333        0xfc00ffff, 0x2000db7f, 0                      , 0,
18334        0x0                 },        /* POOL32Axf_5_group3~*(13) */
18335     { reserved_block      , 0                   , 0   , 32,
18336        0xfc00ffff, 0x2000dd7f, 0                      , 0,
18337        0x0                 },        /* POOL32Axf_5_group3~*(14) */
18338     { reserved_block      , 0                   , 0   , 32,
18339        0xfc00ffff, 0x2000df7f, 0                      , 0,
18340        0x0                 },        /* POOL32Axf_5_group3~*(15) */
18341     { instruction         , 0                   , 0   , 32,
18342        0xfc00ffff, 0x2000e17f, &RDPGPR           , 0,
18343        CP0_                },        /* RDPGPR */
18344     { instruction         , 0                   , 0   , 32,
18345        0xfc00ffff, 0x2000e37f, &DERET            , 0,
18346        EJTAG_              },        /* DERET */
18347     { reserved_block      , 0                   , 0   , 32,
18348        0xfc00ffff, 0x2000e57f, 0                      , 0,
18349        0x0                 },        /* POOL32Axf_5_group3~*(18) */
18350     { reserved_block      , 0                   , 0   , 32,
18351        0xfc00ffff, 0x2000e77f, 0                      , 0,
18352        0x0                 },        /* POOL32Axf_5_group3~*(19) */
18353     { reserved_block      , 0                   , 0   , 32,
18354        0xfc00ffff, 0x2000e97f, 0                      , 0,
18355        0x0                 },        /* POOL32Axf_5_group3~*(20) */
18356     { reserved_block      , 0                   , 0   , 32,
18357        0xfc00ffff, 0x2000eb7f, 0                      , 0,
18358        0x0                 },        /* POOL32Axf_5_group3~*(21) */
18359     { reserved_block      , 0                   , 0   , 32,
18360        0xfc00ffff, 0x2000ed7f, 0                      , 0,
18361        0x0                 },        /* POOL32Axf_5_group3~*(22) */
18362     { reserved_block      , 0                   , 0   , 32,
18363        0xfc00ffff, 0x2000ef7f, 0                      , 0,
18364        0x0                 },        /* POOL32Axf_5_group3~*(23) */
18365     { instruction         , 0                   , 0   , 32,
18366        0xfc00ffff, 0x2000f17f, &WRPGPR           , 0,
18367        CP0_                },        /* WRPGPR */
18368     { pool                , ERETx               , 2   , 32,
18369        0xfc00ffff, 0x2000f37f, 0                      , 0,
18370        0x0                 },        /* ERETx */
18371     { reserved_block      , 0                   , 0   , 32,
18372        0xfc00ffff, 0x2000f57f, 0                      , 0,
18373        0x0                 },        /* POOL32Axf_5_group3~*(26) */
18374     { reserved_block      , 0                   , 0   , 32,
18375        0xfc00ffff, 0x2000f77f, 0                      , 0,
18376        0x0                 },        /* POOL32Axf_5_group3~*(27) */
18377     { reserved_block      , 0                   , 0   , 32,
18378        0xfc00ffff, 0x2000f97f, 0                      , 0,
18379        0x0                 },        /* POOL32Axf_5_group3~*(28) */
18380     { reserved_block      , 0                   , 0   , 32,
18381        0xfc00ffff, 0x2000fb7f, 0                      , 0,
18382        0x0                 },        /* POOL32Axf_5_group3~*(29) */
18383     { reserved_block      , 0                   , 0   , 32,
18384        0xfc00ffff, 0x2000fd7f, 0                      , 0,
18385        0x0                 },        /* POOL32Axf_5_group3~*(30) */
18386     { reserved_block      , 0                   , 0   , 32,
18387        0xfc00ffff, 0x2000ff7f, 0                      , 0,
18388        0x0                 },        /* POOL32Axf_5_group3~*(31) */
18389 };
18390 
18391 
18392 static const Pool POOL32Axf_5[4] = {
18393     { pool                , POOL32Axf_5_group0  , 32  , 32,
18394        0xfc00c1ff, 0x2000017f, 0                      , 0,
18395        0x0                 },        /* POOL32Axf_5_group0 */
18396     { pool                , POOL32Axf_5_group1  , 32  , 32,
18397        0xfc00c1ff, 0x2000417f, 0                      , 0,
18398        0x0                 },        /* POOL32Axf_5_group1 */
18399     { reserved_block      , 0                   , 0   , 32,
18400        0xfc00c1ff, 0x2000817f, 0                      , 0,
18401        0x0                 },        /* POOL32Axf_5~*(2) */
18402     { pool                , POOL32Axf_5_group3  , 32  , 32,
18403        0xfc00c1ff, 0x2000c17f, 0                      , 0,
18404        0x0                 },        /* POOL32Axf_5_group3 */
18405 };
18406 
18407 
18408 static const Pool SHRA__R__QB[2] = {
18409     { instruction         , 0                   , 0   , 32,
18410        0xfc001fff, 0x200001ff, &SHRA_QB          , 0,
18411        DSP_                },        /* SHRA.QB */
18412     { instruction         , 0                   , 0   , 32,
18413        0xfc001fff, 0x200011ff, &SHRA_R_QB        , 0,
18414        DSP_                },        /* SHRA_R.QB */
18415 };
18416 
18417 
18418 static const Pool POOL32Axf_7[8] = {
18419     { pool                , SHRA__R__QB         , 2   , 32,
18420        0xfc000fff, 0x200001ff, 0                      , 0,
18421        0x0                 },        /* SHRA[_R].QB */
18422     { instruction         , 0                   , 0   , 32,
18423        0xfc000fff, 0x200003ff, &SHRL_PH          , 0,
18424        DSP_                },        /* SHRL.PH */
18425     { instruction         , 0                   , 0   , 32,
18426        0xfc000fff, 0x200005ff, &REPL_QB          , 0,
18427        DSP_                },        /* REPL.QB */
18428     { reserved_block      , 0                   , 0   , 32,
18429        0xfc000fff, 0x200007ff, 0                      , 0,
18430        0x0                 },        /* POOL32Axf_7~*(3) */
18431     { reserved_block      , 0                   , 0   , 32,
18432        0xfc000fff, 0x200009ff, 0                      , 0,
18433        0x0                 },        /* POOL32Axf_7~*(4) */
18434     { reserved_block      , 0                   , 0   , 32,
18435        0xfc000fff, 0x20000bff, 0                      , 0,
18436        0x0                 },        /* POOL32Axf_7~*(5) */
18437     { reserved_block      , 0                   , 0   , 32,
18438        0xfc000fff, 0x20000dff, 0                      , 0,
18439        0x0                 },        /* POOL32Axf_7~*(6) */
18440     { reserved_block      , 0                   , 0   , 32,
18441        0xfc000fff, 0x20000fff, 0                      , 0,
18442        0x0                 },        /* POOL32Axf_7~*(7) */
18443 };
18444 
18445 
18446 static const Pool POOL32Axf[8] = {
18447     { reserved_block      , 0                   , 0   , 32,
18448        0xfc0001ff, 0x2000003f, 0                      , 0,
18449        0x0                 },        /* POOL32Axf~*(0) */
18450     { pool                , POOL32Axf_1         , 8   , 32,
18451        0xfc0001ff, 0x2000007f, 0                      , 0,
18452        0x0                 },        /* POOL32Axf_1 */
18453     { pool                , POOL32Axf_2         , 4   , 32,
18454        0xfc0001ff, 0x200000bf, 0                      , 0,
18455        0x0                 },        /* POOL32Axf_2 */
18456     { reserved_block      , 0                   , 0   , 32,
18457        0xfc0001ff, 0x200000ff, 0                      , 0,
18458        0x0                 },        /* POOL32Axf~*(3) */
18459     { pool                , POOL32Axf_4         , 128 , 32,
18460        0xfc0001ff, 0x2000013f, 0                      , 0,
18461        0x0                 },        /* POOL32Axf_4 */
18462     { pool                , POOL32Axf_5         , 4   , 32,
18463        0xfc0001ff, 0x2000017f, 0                      , 0,
18464        0x0                 },        /* POOL32Axf_5 */
18465     { reserved_block      , 0                   , 0   , 32,
18466        0xfc0001ff, 0x200001bf, 0                      , 0,
18467        0x0                 },        /* POOL32Axf~*(6) */
18468     { pool                , POOL32Axf_7         , 8   , 32,
18469        0xfc0001ff, 0x200001ff, 0                      , 0,
18470        0x0                 },        /* POOL32Axf_7 */
18471 };
18472 
18473 
18474 static const Pool _POOL32A7[8] = {
18475     { pool                , P_LSX               , 2   , 32,
18476        0xfc00003f, 0x20000007, 0                      , 0,
18477        0x0                 },        /* P.LSX */
18478     { instruction         , 0                   , 0   , 32,
18479        0xfc00003f, 0x2000000f, &LSA              , 0,
18480        0x0                 },        /* LSA */
18481     { reserved_block      , 0                   , 0   , 32,
18482        0xfc00003f, 0x20000017, 0                      , 0,
18483        0x0                 },        /* _POOL32A7~*(2) */
18484     { instruction         , 0                   , 0   , 32,
18485        0xfc00003f, 0x2000001f, &EXTW             , 0,
18486        0x0                 },        /* EXTW */
18487     { reserved_block      , 0                   , 0   , 32,
18488        0xfc00003f, 0x20000027, 0                      , 0,
18489        0x0                 },        /* _POOL32A7~*(4) */
18490     { reserved_block      , 0                   , 0   , 32,
18491        0xfc00003f, 0x2000002f, 0                      , 0,
18492        0x0                 },        /* _POOL32A7~*(5) */
18493     { reserved_block      , 0                   , 0   , 32,
18494        0xfc00003f, 0x20000037, 0                      , 0,
18495        0x0                 },        /* _POOL32A7~*(6) */
18496     { pool                , POOL32Axf           , 8   , 32,
18497        0xfc00003f, 0x2000003f, 0                      , 0,
18498        0x0                 },        /* POOL32Axf */
18499 };
18500 
18501 
18502 static const Pool P32A[8] = {
18503     { pool                , _POOL32A0           , 128 , 32,
18504        0xfc000007, 0x20000000, 0                      , 0,
18505        0x0                 },        /* _POOL32A0 */
18506     { instruction         , 0                   , 0   , 32,
18507        0xfc000007, 0x20000001, &SPECIAL2         , 0,
18508        UDI_                },        /* SPECIAL2 */
18509     { instruction         , 0                   , 0   , 32,
18510        0xfc000007, 0x20000002, &COP2_1           , 0,
18511        CP2_                },        /* COP2_1 */
18512     { instruction         , 0                   , 0   , 32,
18513        0xfc000007, 0x20000003, &UDI              , 0,
18514        UDI_                },        /* UDI */
18515     { reserved_block      , 0                   , 0   , 32,
18516        0xfc000007, 0x20000004, 0                      , 0,
18517        0x0                 },        /* P32A~*(4) */
18518     { pool                , _POOL32A5           , 128 , 32,
18519        0xfc000007, 0x20000005, 0                      , 0,
18520        0x0                 },        /* _POOL32A5 */
18521     { reserved_block      , 0                   , 0   , 32,
18522        0xfc000007, 0x20000006, 0                      , 0,
18523        0x0                 },        /* P32A~*(6) */
18524     { pool                , _POOL32A7           , 8   , 32,
18525        0xfc000007, 0x20000007, 0                      , 0,
18526        0x0                 },        /* _POOL32A7 */
18527 };
18528 
18529 
18530 static const Pool P_GP_D[2] = {
18531     { instruction         , 0                   , 0   , 32,
18532        0xfc000007, 0x40000001, &LD_GP_           , 0,
18533        MIPS64_             },        /* LD[GP] */
18534     { instruction         , 0                   , 0   , 32,
18535        0xfc000007, 0x40000005, &SD_GP_           , 0,
18536        MIPS64_             },        /* SD[GP] */
18537 };
18538 
18539 
18540 static const Pool P_GP_W[4] = {
18541     { instruction         , 0                   , 0   , 32,
18542        0xfc000003, 0x40000000, &ADDIU_GP_W_      , 0,
18543        0x0                 },        /* ADDIU[GP.W] */
18544     { pool                , P_GP_D              , 2   , 32,
18545        0xfc000003, 0x40000001, 0                      , 0,
18546        0x0                 },        /* P.GP.D */
18547     { instruction         , 0                   , 0   , 32,
18548        0xfc000003, 0x40000002, &LW_GP_           , 0,
18549        0x0                 },        /* LW[GP] */
18550     { instruction         , 0                   , 0   , 32,
18551        0xfc000003, 0x40000003, &SW_GP_           , 0,
18552        0x0                 },        /* SW[GP] */
18553 };
18554 
18555 
18556 static const Pool POOL48I[32] = {
18557     { instruction         , 0                   , 0   , 48,
18558        0xfc1f00000000ull, 0x600000000000ull, &LI_48_           , 0,
18559        XMMS_               },        /* LI[48] */
18560     { instruction         , 0                   , 0   , 48,
18561        0xfc1f00000000ull, 0x600100000000ull, &ADDIU_48_        , 0,
18562        XMMS_               },        /* ADDIU[48] */
18563     { instruction         , 0                   , 0   , 48,
18564        0xfc1f00000000ull, 0x600200000000ull, &ADDIU_GP48_      , 0,
18565        XMMS_               },        /* ADDIU[GP48] */
18566     { instruction         , 0                   , 0   , 48,
18567        0xfc1f00000000ull, 0x600300000000ull, &ADDIUPC_48_      , 0,
18568        XMMS_               },        /* ADDIUPC[48] */
18569     { reserved_block      , 0                   , 0   , 48,
18570        0xfc1f00000000ull, 0x600400000000ull, 0                      , 0,
18571        0x0                 },        /* POOL48I~*(4) */
18572     { reserved_block      , 0                   , 0   , 48,
18573        0xfc1f00000000ull, 0x600500000000ull, 0                      , 0,
18574        0x0                 },        /* POOL48I~*(5) */
18575     { reserved_block      , 0                   , 0   , 48,
18576        0xfc1f00000000ull, 0x600600000000ull, 0                      , 0,
18577        0x0                 },        /* POOL48I~*(6) */
18578     { reserved_block      , 0                   , 0   , 48,
18579        0xfc1f00000000ull, 0x600700000000ull, 0                      , 0,
18580        0x0                 },        /* POOL48I~*(7) */
18581     { reserved_block      , 0                   , 0   , 48,
18582        0xfc1f00000000ull, 0x600800000000ull, 0                      , 0,
18583        0x0                 },        /* POOL48I~*(8) */
18584     { reserved_block      , 0                   , 0   , 48,
18585        0xfc1f00000000ull, 0x600900000000ull, 0                      , 0,
18586        0x0                 },        /* POOL48I~*(9) */
18587     { reserved_block      , 0                   , 0   , 48,
18588        0xfc1f00000000ull, 0x600a00000000ull, 0                      , 0,
18589        0x0                 },        /* POOL48I~*(10) */
18590     { instruction         , 0                   , 0   , 48,
18591        0xfc1f00000000ull, 0x600b00000000ull, &LWPC_48_         , 0,
18592        XMMS_               },        /* LWPC[48] */
18593     { reserved_block      , 0                   , 0   , 48,
18594        0xfc1f00000000ull, 0x600c00000000ull, 0                      , 0,
18595        0x0                 },        /* POOL48I~*(12) */
18596     { reserved_block      , 0                   , 0   , 48,
18597        0xfc1f00000000ull, 0x600d00000000ull, 0                      , 0,
18598        0x0                 },        /* POOL48I~*(13) */
18599     { reserved_block      , 0                   , 0   , 48,
18600        0xfc1f00000000ull, 0x600e00000000ull, 0                      , 0,
18601        0x0                 },        /* POOL48I~*(14) */
18602     { instruction         , 0                   , 0   , 48,
18603        0xfc1f00000000ull, 0x600f00000000ull, &SWPC_48_         , 0,
18604        XMMS_               },        /* SWPC[48] */
18605     { reserved_block      , 0                   , 0   , 48,
18606        0xfc1f00000000ull, 0x601000000000ull, 0                      , 0,
18607        0x0                 },        /* POOL48I~*(16) */
18608     { instruction         , 0                   , 0   , 48,
18609        0xfc1f00000000ull, 0x601100000000ull, &DADDIU_48_       , 0,
18610        MIPS64_             },        /* DADDIU[48] */
18611     { reserved_block      , 0                   , 0   , 48,
18612        0xfc1f00000000ull, 0x601200000000ull, 0                      , 0,
18613        0x0                 },        /* POOL48I~*(18) */
18614     { reserved_block      , 0                   , 0   , 48,
18615        0xfc1f00000000ull, 0x601300000000ull, 0                      , 0,
18616        0x0                 },        /* POOL48I~*(19) */
18617     { instruction         , 0                   , 0   , 48,
18618        0xfc1f00000000ull, 0x601400000000ull, &DLUI_48_         , 0,
18619        MIPS64_             },        /* DLUI[48] */
18620     { reserved_block      , 0                   , 0   , 48,
18621        0xfc1f00000000ull, 0x601500000000ull, 0                      , 0,
18622        0x0                 },        /* POOL48I~*(21) */
18623     { reserved_block      , 0                   , 0   , 48,
18624        0xfc1f00000000ull, 0x601600000000ull, 0                      , 0,
18625        0x0                 },        /* POOL48I~*(22) */
18626     { reserved_block      , 0                   , 0   , 48,
18627        0xfc1f00000000ull, 0x601700000000ull, 0                      , 0,
18628        0x0                 },        /* POOL48I~*(23) */
18629     { reserved_block      , 0                   , 0   , 48,
18630        0xfc1f00000000ull, 0x601800000000ull, 0                      , 0,
18631        0x0                 },        /* POOL48I~*(24) */
18632     { reserved_block      , 0                   , 0   , 48,
18633        0xfc1f00000000ull, 0x601900000000ull, 0                      , 0,
18634        0x0                 },        /* POOL48I~*(25) */
18635     { reserved_block      , 0                   , 0   , 48,
18636        0xfc1f00000000ull, 0x601a00000000ull, 0                      , 0,
18637        0x0                 },        /* POOL48I~*(26) */
18638     { instruction         , 0                   , 0   , 48,
18639        0xfc1f00000000ull, 0x601b00000000ull, &LDPC_48_         , 0,
18640        MIPS64_             },        /* LDPC[48] */
18641     { reserved_block      , 0                   , 0   , 48,
18642        0xfc1f00000000ull, 0x601c00000000ull, 0                      , 0,
18643        0x0                 },        /* POOL48I~*(28) */
18644     { reserved_block      , 0                   , 0   , 48,
18645        0xfc1f00000000ull, 0x601d00000000ull, 0                      , 0,
18646        0x0                 },        /* POOL48I~*(29) */
18647     { reserved_block      , 0                   , 0   , 48,
18648        0xfc1f00000000ull, 0x601e00000000ull, 0                      , 0,
18649        0x0                 },        /* POOL48I~*(30) */
18650     { instruction         , 0                   , 0   , 48,
18651        0xfc1f00000000ull, 0x601f00000000ull, &SDPC_48_         , 0,
18652        MIPS64_             },        /* SDPC[48] */
18653 };
18654 
18655 
18656 static const Pool PP_SR[4] = {
18657     { instruction         , 0                   , 0   , 32,
18658        0xfc10f003, 0x80003000, &SAVE_32_         , 0,
18659        0x0                 },        /* SAVE[32] */
18660     { reserved_block      , 0                   , 0   , 32,
18661        0xfc10f003, 0x80003001, 0                      , 0,
18662        0x0                 },        /* PP.SR~*(1) */
18663     { instruction         , 0                   , 0   , 32,
18664        0xfc10f003, 0x80003002, &RESTORE_32_      , 0,
18665        0x0                 },        /* RESTORE[32] */
18666     { return_instruction  , 0                   , 0   , 32,
18667        0xfc10f003, 0x80003003, &RESTORE_JRC_32_  , 0,
18668        0x0                 },        /* RESTORE.JRC[32] */
18669 };
18670 
18671 
18672 static const Pool P_SR_F[8] = {
18673     { instruction         , 0                   , 0   , 32,
18674        0xfc10f007, 0x80103000, &SAVEF            , 0,
18675        CP1_                },        /* SAVEF */
18676     { instruction         , 0                   , 0   , 32,
18677        0xfc10f007, 0x80103001, &RESTOREF         , 0,
18678        CP1_                },        /* RESTOREF */
18679     { reserved_block      , 0                   , 0   , 32,
18680        0xfc10f007, 0x80103002, 0                      , 0,
18681        0x0                 },        /* P.SR.F~*(2) */
18682     { reserved_block      , 0                   , 0   , 32,
18683        0xfc10f007, 0x80103003, 0                      , 0,
18684        0x0                 },        /* P.SR.F~*(3) */
18685     { reserved_block      , 0                   , 0   , 32,
18686        0xfc10f007, 0x80103004, 0                      , 0,
18687        0x0                 },        /* P.SR.F~*(4) */
18688     { reserved_block      , 0                   , 0   , 32,
18689        0xfc10f007, 0x80103005, 0                      , 0,
18690        0x0                 },        /* P.SR.F~*(5) */
18691     { reserved_block      , 0                   , 0   , 32,
18692        0xfc10f007, 0x80103006, 0                      , 0,
18693        0x0                 },        /* P.SR.F~*(6) */
18694     { reserved_block      , 0                   , 0   , 32,
18695        0xfc10f007, 0x80103007, 0                      , 0,
18696        0x0                 },        /* P.SR.F~*(7) */
18697 };
18698 
18699 
18700 static const Pool P_SR[2] = {
18701     { pool                , PP_SR               , 4   , 32,
18702        0xfc10f000, 0x80003000, 0                      , 0,
18703        0x0                 },        /* PP.SR */
18704     { pool                , P_SR_F              , 8   , 32,
18705        0xfc10f000, 0x80103000, 0                      , 0,
18706        0x0                 },        /* P.SR.F */
18707 };
18708 
18709 
18710 static const Pool P_SLL[5] = {
18711     { instruction         , 0                   , 0   , 32,
18712        0xffe0f1ff, 0x8000c000, &NOP_32_          , 0,
18713        0x0                 },        /* NOP[32] */
18714     { instruction         , 0                   , 0   , 32,
18715        0xffe0f1ff, 0x8000c003, &EHB              , 0,
18716        0x0                 },        /* EHB */
18717     { instruction         , 0                   , 0   , 32,
18718        0xffe0f1ff, 0x8000c005, &PAUSE            , 0,
18719        0x0                 },        /* PAUSE */
18720     { instruction         , 0                   , 0   , 32,
18721        0xffe0f1ff, 0x8000c006, &SYNC             , 0,
18722        0x0                 },        /* SYNC */
18723     { instruction         , 0                   , 0   , 32,
18724        0xfc00f1e0, 0x8000c000, &SLL_32_          , 0,
18725        0x0                 },        /* SLL[32] */
18726 };
18727 
18728 
18729 static const Pool P_SHIFT[16] = {
18730     { pool                , P_SLL               , 5   , 32,
18731        0xfc00f1e0, 0x8000c000, 0                      , 0,
18732        0x0                 },        /* P.SLL */
18733     { reserved_block      , 0                   , 0   , 32,
18734        0xfc00f1e0, 0x8000c020, 0                      , 0,
18735        0x0                 },        /* P.SHIFT~*(1) */
18736     { instruction         , 0                   , 0   , 32,
18737        0xfc00f1e0, 0x8000c040, &SRL_32_          , 0,
18738        0x0                 },        /* SRL[32] */
18739     { reserved_block      , 0                   , 0   , 32,
18740        0xfc00f1e0, 0x8000c060, 0                      , 0,
18741        0x0                 },        /* P.SHIFT~*(3) */
18742     { instruction         , 0                   , 0   , 32,
18743        0xfc00f1e0, 0x8000c080, &SRA              , 0,
18744        0x0                 },        /* SRA */
18745     { reserved_block      , 0                   , 0   , 32,
18746        0xfc00f1e0, 0x8000c0a0, 0                      , 0,
18747        0x0                 },        /* P.SHIFT~*(5) */
18748     { instruction         , 0                   , 0   , 32,
18749        0xfc00f1e0, 0x8000c0c0, &ROTR             , 0,
18750        0x0                 },        /* ROTR */
18751     { reserved_block      , 0                   , 0   , 32,
18752        0xfc00f1e0, 0x8000c0e0, 0                      , 0,
18753        0x0                 },        /* P.SHIFT~*(7) */
18754     { instruction         , 0                   , 0   , 32,
18755        0xfc00f1e0, 0x8000c100, &DSLL             , 0,
18756        MIPS64_             },        /* DSLL */
18757     { instruction         , 0                   , 0   , 32,
18758        0xfc00f1e0, 0x8000c120, &DSLL32           , 0,
18759        MIPS64_             },        /* DSLL32 */
18760     { instruction         , 0                   , 0   , 32,
18761        0xfc00f1e0, 0x8000c140, &DSRL             , 0,
18762        MIPS64_             },        /* DSRL */
18763     { instruction         , 0                   , 0   , 32,
18764        0xfc00f1e0, 0x8000c160, &DSRL32           , 0,
18765        MIPS64_             },        /* DSRL32 */
18766     { instruction         , 0                   , 0   , 32,
18767        0xfc00f1e0, 0x8000c180, &DSRA             , 0,
18768        MIPS64_             },        /* DSRA */
18769     { instruction         , 0                   , 0   , 32,
18770        0xfc00f1e0, 0x8000c1a0, &DSRA32           , 0,
18771        MIPS64_             },        /* DSRA32 */
18772     { instruction         , 0                   , 0   , 32,
18773        0xfc00f1e0, 0x8000c1c0, &DROTR            , 0,
18774        MIPS64_             },        /* DROTR */
18775     { instruction         , 0                   , 0   , 32,
18776        0xfc00f1e0, 0x8000c1e0, &DROTR32          , 0,
18777        MIPS64_             },        /* DROTR32 */
18778 };
18779 
18780 
18781 static const Pool P_ROTX[4] = {
18782     { instruction         , 0                   , 0   , 32,
18783        0xfc00f820, 0x8000d000, &ROTX             , 0,
18784        XMMS_               },        /* ROTX */
18785     { reserved_block      , 0                   , 0   , 32,
18786        0xfc00f820, 0x8000d020, 0                      , 0,
18787        0x0                 },        /* P.ROTX~*(1) */
18788     { reserved_block      , 0                   , 0   , 32,
18789        0xfc00f820, 0x8000d800, 0                      , 0,
18790        0x0                 },        /* P.ROTX~*(2) */
18791     { reserved_block      , 0                   , 0   , 32,
18792        0xfc00f820, 0x8000d820, 0                      , 0,
18793        0x0                 },        /* P.ROTX~*(3) */
18794 };
18795 
18796 
18797 static const Pool P_INS[4] = {
18798     { instruction         , 0                   , 0   , 32,
18799        0xfc00f820, 0x8000e000, &INS              , 0,
18800        XMMS_               },        /* INS */
18801     { instruction         , 0                   , 0   , 32,
18802        0xfc00f820, 0x8000e020, &DINSU            , 0,
18803        MIPS64_             },        /* DINSU */
18804     { instruction         , 0                   , 0   , 32,
18805        0xfc00f820, 0x8000e800, &DINSM            , 0,
18806        MIPS64_             },        /* DINSM */
18807     { instruction         , 0                   , 0   , 32,
18808        0xfc00f820, 0x8000e820, &DINS             , 0,
18809        MIPS64_             },        /* DINS */
18810 };
18811 
18812 
18813 static const Pool P_EXT[4] = {
18814     { instruction         , 0                   , 0   , 32,
18815        0xfc00f820, 0x8000f000, &EXT              , 0,
18816        XMMS_               },        /* EXT */
18817     { instruction         , 0                   , 0   , 32,
18818        0xfc00f820, 0x8000f020, &DEXTU            , 0,
18819        MIPS64_             },        /* DEXTU */
18820     { instruction         , 0                   , 0   , 32,
18821        0xfc00f820, 0x8000f800, &DEXTM            , 0,
18822        MIPS64_             },        /* DEXTM */
18823     { instruction         , 0                   , 0   , 32,
18824        0xfc00f820, 0x8000f820, &DEXT             , 0,
18825        MIPS64_             },        /* DEXT */
18826 };
18827 
18828 
18829 static const Pool P_U12[16] = {
18830     { instruction         , 0                   , 0   , 32,
18831        0xfc00f000, 0x80000000, &ORI              , 0,
18832        0x0                 },        /* ORI */
18833     { instruction         , 0                   , 0   , 32,
18834        0xfc00f000, 0x80001000, &XORI             , 0,
18835        0x0                 },        /* XORI */
18836     { instruction         , 0                   , 0   , 32,
18837        0xfc00f000, 0x80002000, &ANDI_32_         , 0,
18838        0x0                 },        /* ANDI[32] */
18839     { pool                , P_SR                , 2   , 32,
18840        0xfc00f000, 0x80003000, 0                      , 0,
18841        0x0                 },        /* P.SR */
18842     { instruction         , 0                   , 0   , 32,
18843        0xfc00f000, 0x80004000, &SLTI             , 0,
18844        0x0                 },        /* SLTI */
18845     { instruction         , 0                   , 0   , 32,
18846        0xfc00f000, 0x80005000, &SLTIU            , 0,
18847        0x0                 },        /* SLTIU */
18848     { instruction         , 0                   , 0   , 32,
18849        0xfc00f000, 0x80006000, &SEQI             , 0,
18850        0x0                 },        /* SEQI */
18851     { reserved_block      , 0                   , 0   , 32,
18852        0xfc00f000, 0x80007000, 0                      , 0,
18853        0x0                 },        /* P.U12~*(7) */
18854     { instruction         , 0                   , 0   , 32,
18855        0xfc00f000, 0x80008000, &ADDIU_NEG_       , 0,
18856        0x0                 },        /* ADDIU[NEG] */
18857     { instruction         , 0                   , 0   , 32,
18858        0xfc00f000, 0x80009000, &DADDIU_U12_      , 0,
18859        MIPS64_             },        /* DADDIU[U12] */
18860     { instruction         , 0                   , 0   , 32,
18861        0xfc00f000, 0x8000a000, &DADDIU_NEG_      , 0,
18862        MIPS64_             },        /* DADDIU[NEG] */
18863     { instruction         , 0                   , 0   , 32,
18864        0xfc00f000, 0x8000b000, &DROTX            , 0,
18865        MIPS64_             },        /* DROTX */
18866     { pool                , P_SHIFT             , 16  , 32,
18867        0xfc00f000, 0x8000c000, 0                      , 0,
18868        0x0                 },        /* P.SHIFT */
18869     { pool                , P_ROTX              , 4   , 32,
18870        0xfc00f000, 0x8000d000, 0                      , 0,
18871        0x0                 },        /* P.ROTX */
18872     { pool                , P_INS               , 4   , 32,
18873        0xfc00f000, 0x8000e000, 0                      , 0,
18874        0x0                 },        /* P.INS */
18875     { pool                , P_EXT               , 4   , 32,
18876        0xfc00f000, 0x8000f000, 0                      , 0,
18877        0x0                 },        /* P.EXT */
18878 };
18879 
18880 
18881 static const Pool RINT_fmt[2] = {
18882     { instruction         , 0                   , 0   , 32,
18883        0xfc0003ff, 0xa0000020, &RINT_S           , 0,
18884        CP1_                },        /* RINT.S */
18885     { instruction         , 0                   , 0   , 32,
18886        0xfc0003ff, 0xa0000220, &RINT_D           , 0,
18887        CP1_                },        /* RINT.D */
18888 };
18889 
18890 
18891 static const Pool ADD_fmt0[2] = {
18892     { instruction         , 0                   , 0   , 32,
18893        0xfc0003ff, 0xa0000030, &ADD_S            , 0,
18894        CP1_                },        /* ADD.S */
18895     { reserved_block      , 0                   , 0   , 32,
18896        0xfc0003ff, 0xa0000230, 0                      , 0,
18897        CP1_                },        /* ADD.fmt0~*(1) */
18898 };
18899 
18900 
18901 static const Pool SELEQZ_fmt[2] = {
18902     { instruction         , 0                   , 0   , 32,
18903        0xfc0003ff, 0xa0000038, &SELEQZ_S         , 0,
18904        CP1_                },        /* SELEQZ.S */
18905     { instruction         , 0                   , 0   , 32,
18906        0xfc0003ff, 0xa0000238, &SELEQZ_D         , 0,
18907        CP1_                },        /* SELEQZ.D */
18908 };
18909 
18910 
18911 static const Pool CLASS_fmt[2] = {
18912     { instruction         , 0                   , 0   , 32,
18913        0xfc0003ff, 0xa0000060, &CLASS_S          , 0,
18914        CP1_                },        /* CLASS.S */
18915     { instruction         , 0                   , 0   , 32,
18916        0xfc0003ff, 0xa0000260, &CLASS_D          , 0,
18917        CP1_                },        /* CLASS.D */
18918 };
18919 
18920 
18921 static const Pool SUB_fmt0[2] = {
18922     { instruction         , 0                   , 0   , 32,
18923        0xfc0003ff, 0xa0000070, &SUB_S            , 0,
18924        CP1_                },        /* SUB.S */
18925     { reserved_block      , 0                   , 0   , 32,
18926        0xfc0003ff, 0xa0000270, 0                      , 0,
18927        CP1_                },        /* SUB.fmt0~*(1) */
18928 };
18929 
18930 
18931 static const Pool SELNEZ_fmt[2] = {
18932     { instruction         , 0                   , 0   , 32,
18933        0xfc0003ff, 0xa0000078, &SELNEZ_S         , 0,
18934        CP1_                },        /* SELNEZ.S */
18935     { instruction         , 0                   , 0   , 32,
18936        0xfc0003ff, 0xa0000278, &SELNEZ_D         , 0,
18937        CP1_                },        /* SELNEZ.D */
18938 };
18939 
18940 
18941 static const Pool MUL_fmt0[2] = {
18942     { instruction         , 0                   , 0   , 32,
18943        0xfc0003ff, 0xa00000b0, &MUL_S            , 0,
18944        CP1_                },        /* MUL.S */
18945     { reserved_block      , 0                   , 0   , 32,
18946        0xfc0003ff, 0xa00002b0, 0                      , 0,
18947        CP1_                },        /* MUL.fmt0~*(1) */
18948 };
18949 
18950 
18951 static const Pool SEL_fmt[2] = {
18952     { instruction         , 0                   , 0   , 32,
18953        0xfc0003ff, 0xa00000b8, &SEL_S            , 0,
18954        CP1_                },        /* SEL.S */
18955     { instruction         , 0                   , 0   , 32,
18956        0xfc0003ff, 0xa00002b8, &SEL_D            , 0,
18957        CP1_                },        /* SEL.D */
18958 };
18959 
18960 
18961 static const Pool DIV_fmt0[2] = {
18962     { instruction         , 0                   , 0   , 32,
18963        0xfc0003ff, 0xa00000f0, &DIV_S            , 0,
18964        CP1_                },        /* DIV.S */
18965     { reserved_block      , 0                   , 0   , 32,
18966        0xfc0003ff, 0xa00002f0, 0                      , 0,
18967        CP1_                },        /* DIV.fmt0~*(1) */
18968 };
18969 
18970 
18971 static const Pool ADD_fmt1[2] = {
18972     { instruction         , 0                   , 0   , 32,
18973        0xfc0003ff, 0xa0000130, &ADD_D            , 0,
18974        CP1_                },        /* ADD.D */
18975     { reserved_block      , 0                   , 0   , 32,
18976        0xfc0003ff, 0xa0000330, 0                      , 0,
18977        CP1_                },        /* ADD.fmt1~*(1) */
18978 };
18979 
18980 
18981 static const Pool SUB_fmt1[2] = {
18982     { instruction         , 0                   , 0   , 32,
18983        0xfc0003ff, 0xa0000170, &SUB_D            , 0,
18984        CP1_                },        /* SUB.D */
18985     { reserved_block      , 0                   , 0   , 32,
18986        0xfc0003ff, 0xa0000370, 0                      , 0,
18987        CP1_                },        /* SUB.fmt1~*(1) */
18988 };
18989 
18990 
18991 static const Pool MUL_fmt1[2] = {
18992     { instruction         , 0                   , 0   , 32,
18993        0xfc0003ff, 0xa00001b0, &MUL_D            , 0,
18994        CP1_                },        /* MUL.D */
18995     { reserved_block      , 0                   , 0   , 32,
18996        0xfc0003ff, 0xa00003b0, 0                      , 0,
18997        CP1_                },        /* MUL.fmt1~*(1) */
18998 };
18999 
19000 
19001 static const Pool MADDF_fmt[2] = {
19002     { instruction         , 0                   , 0   , 32,
19003        0xfc0003ff, 0xa00001b8, &MADDF_S          , 0,
19004        CP1_                },        /* MADDF.S */
19005     { instruction         , 0                   , 0   , 32,
19006        0xfc0003ff, 0xa00003b8, &MADDF_D          , 0,
19007        CP1_                },        /* MADDF.D */
19008 };
19009 
19010 
19011 static const Pool DIV_fmt1[2] = {
19012     { instruction         , 0                   , 0   , 32,
19013        0xfc0003ff, 0xa00001f0, &DIV_D            , 0,
19014        CP1_                },        /* DIV.D */
19015     { reserved_block      , 0                   , 0   , 32,
19016        0xfc0003ff, 0xa00003f0, 0                      , 0,
19017        CP1_                },        /* DIV.fmt1~*(1) */
19018 };
19019 
19020 
19021 static const Pool MSUBF_fmt[2] = {
19022     { instruction         , 0                   , 0   , 32,
19023        0xfc0003ff, 0xa00001f8, &MSUBF_S          , 0,
19024        CP1_                },        /* MSUBF.S */
19025     { instruction         , 0                   , 0   , 32,
19026        0xfc0003ff, 0xa00003f8, &MSUBF_D          , 0,
19027        CP1_                },        /* MSUBF.D */
19028 };
19029 
19030 
19031 static const Pool POOL32F_0[64] = {
19032     { reserved_block      , 0                   , 0   , 32,
19033        0xfc0001ff, 0xa0000000, 0                      , 0,
19034        CP1_                },        /* POOL32F_0~*(0) */
19035     { reserved_block      , 0                   , 0   , 32,
19036        0xfc0001ff, 0xa0000008, 0                      , 0,
19037        CP1_                },        /* POOL32F_0~*(1) */
19038     { reserved_block      , 0                   , 0   , 32,
19039        0xfc0001ff, 0xa0000010, 0                      , 0,
19040        CP1_                },        /* POOL32F_0~*(2) */
19041     { reserved_block      , 0                   , 0   , 32,
19042        0xfc0001ff, 0xa0000018, 0                      , 0,
19043        CP1_                },        /* POOL32F_0~*(3) */
19044     { pool                , RINT_fmt            , 2   , 32,
19045        0xfc0001ff, 0xa0000020, 0                      , 0,
19046        CP1_                },        /* RINT.fmt */
19047     { reserved_block      , 0                   , 0   , 32,
19048        0xfc0001ff, 0xa0000028, 0                      , 0,
19049        CP1_                },        /* POOL32F_0~*(5) */
19050     { pool                , ADD_fmt0            , 2   , 32,
19051        0xfc0001ff, 0xa0000030, 0                      , 0,
19052        CP1_                },        /* ADD.fmt0 */
19053     { pool                , SELEQZ_fmt          , 2   , 32,
19054        0xfc0001ff, 0xa0000038, 0                      , 0,
19055        CP1_                },        /* SELEQZ.fmt */
19056     { reserved_block      , 0                   , 0   , 32,
19057        0xfc0001ff, 0xa0000040, 0                      , 0,
19058        CP1_                },        /* POOL32F_0~*(8) */
19059     { reserved_block      , 0                   , 0   , 32,
19060        0xfc0001ff, 0xa0000048, 0                      , 0,
19061        CP1_                },        /* POOL32F_0~*(9) */
19062     { reserved_block      , 0                   , 0   , 32,
19063        0xfc0001ff, 0xa0000050, 0                      , 0,
19064        CP1_                },        /* POOL32F_0~*(10) */
19065     { reserved_block      , 0                   , 0   , 32,
19066        0xfc0001ff, 0xa0000058, 0                      , 0,
19067        CP1_                },        /* POOL32F_0~*(11) */
19068     { pool                , CLASS_fmt           , 2   , 32,
19069        0xfc0001ff, 0xa0000060, 0                      , 0,
19070        CP1_                },        /* CLASS.fmt */
19071     { reserved_block      , 0                   , 0   , 32,
19072        0xfc0001ff, 0xa0000068, 0                      , 0,
19073        CP1_                },        /* POOL32F_0~*(13) */
19074     { pool                , SUB_fmt0            , 2   , 32,
19075        0xfc0001ff, 0xa0000070, 0                      , 0,
19076        CP1_                },        /* SUB.fmt0 */
19077     { pool                , SELNEZ_fmt          , 2   , 32,
19078        0xfc0001ff, 0xa0000078, 0                      , 0,
19079        CP1_                },        /* SELNEZ.fmt */
19080     { reserved_block      , 0                   , 0   , 32,
19081        0xfc0001ff, 0xa0000080, 0                      , 0,
19082        CP1_                },        /* POOL32F_0~*(16) */
19083     { reserved_block      , 0                   , 0   , 32,
19084        0xfc0001ff, 0xa0000088, 0                      , 0,
19085        CP1_                },        /* POOL32F_0~*(17) */
19086     { reserved_block      , 0                   , 0   , 32,
19087        0xfc0001ff, 0xa0000090, 0                      , 0,
19088        CP1_                },        /* POOL32F_0~*(18) */
19089     { reserved_block      , 0                   , 0   , 32,
19090        0xfc0001ff, 0xa0000098, 0                      , 0,
19091        CP1_                },        /* POOL32F_0~*(19) */
19092     { reserved_block      , 0                   , 0   , 32,
19093        0xfc0001ff, 0xa00000a0, 0                      , 0,
19094        CP1_                },        /* POOL32F_0~*(20) */
19095     { reserved_block      , 0                   , 0   , 32,
19096        0xfc0001ff, 0xa00000a8, 0                      , 0,
19097        CP1_                },        /* POOL32F_0~*(21) */
19098     { pool                , MUL_fmt0            , 2   , 32,
19099        0xfc0001ff, 0xa00000b0, 0                      , 0,
19100        CP1_                },        /* MUL.fmt0 */
19101     { pool                , SEL_fmt             , 2   , 32,
19102        0xfc0001ff, 0xa00000b8, 0                      , 0,
19103        CP1_                },        /* SEL.fmt */
19104     { reserved_block      , 0                   , 0   , 32,
19105        0xfc0001ff, 0xa00000c0, 0                      , 0,
19106        CP1_                },        /* POOL32F_0~*(24) */
19107     { reserved_block      , 0                   , 0   , 32,
19108        0xfc0001ff, 0xa00000c8, 0                      , 0,
19109        CP1_                },        /* POOL32F_0~*(25) */
19110     { reserved_block      , 0                   , 0   , 32,
19111        0xfc0001ff, 0xa00000d0, 0                      , 0,
19112        CP1_                },        /* POOL32F_0~*(26) */
19113     { reserved_block      , 0                   , 0   , 32,
19114        0xfc0001ff, 0xa00000d8, 0                      , 0,
19115        CP1_                },        /* POOL32F_0~*(27) */
19116     { reserved_block      , 0                   , 0   , 32,
19117        0xfc0001ff, 0xa00000e0, 0                      , 0,
19118        CP1_                },        /* POOL32F_0~*(28) */
19119     { reserved_block      , 0                   , 0   , 32,
19120        0xfc0001ff, 0xa00000e8, 0                      , 0,
19121        CP1_                },        /* POOL32F_0~*(29) */
19122     { pool                , DIV_fmt0            , 2   , 32,
19123        0xfc0001ff, 0xa00000f0, 0                      , 0,
19124        CP1_                },        /* DIV.fmt0 */
19125     { reserved_block      , 0                   , 0   , 32,
19126        0xfc0001ff, 0xa00000f8, 0                      , 0,
19127        CP1_                },        /* POOL32F_0~*(31) */
19128     { reserved_block      , 0                   , 0   , 32,
19129        0xfc0001ff, 0xa0000100, 0                      , 0,
19130        CP1_                },        /* POOL32F_0~*(32) */
19131     { reserved_block      , 0                   , 0   , 32,
19132        0xfc0001ff, 0xa0000108, 0                      , 0,
19133        CP1_                },        /* POOL32F_0~*(33) */
19134     { reserved_block      , 0                   , 0   , 32,
19135        0xfc0001ff, 0xa0000110, 0                      , 0,
19136        CP1_                },        /* POOL32F_0~*(34) */
19137     { reserved_block      , 0                   , 0   , 32,
19138        0xfc0001ff, 0xa0000118, 0                      , 0,
19139        CP1_                },        /* POOL32F_0~*(35) */
19140     { reserved_block      , 0                   , 0   , 32,
19141        0xfc0001ff, 0xa0000120, 0                      , 0,
19142        CP1_                },        /* POOL32F_0~*(36) */
19143     { reserved_block      , 0                   , 0   , 32,
19144        0xfc0001ff, 0xa0000128, 0                      , 0,
19145        CP1_                },        /* POOL32F_0~*(37) */
19146     { pool                , ADD_fmt1            , 2   , 32,
19147        0xfc0001ff, 0xa0000130, 0                      , 0,
19148        CP1_                },        /* ADD.fmt1 */
19149     { reserved_block      , 0                   , 0   , 32,
19150        0xfc0001ff, 0xa0000138, 0                      , 0,
19151        CP1_                },        /* POOL32F_0~*(39) */
19152     { reserved_block      , 0                   , 0   , 32,
19153        0xfc0001ff, 0xa0000140, 0                      , 0,
19154        CP1_                },        /* POOL32F_0~*(40) */
19155     { reserved_block      , 0                   , 0   , 32,
19156        0xfc0001ff, 0xa0000148, 0                      , 0,
19157        CP1_                },        /* POOL32F_0~*(41) */
19158     { reserved_block      , 0                   , 0   , 32,
19159        0xfc0001ff, 0xa0000150, 0                      , 0,
19160        CP1_                },        /* POOL32F_0~*(42) */
19161     { reserved_block      , 0                   , 0   , 32,
19162        0xfc0001ff, 0xa0000158, 0                      , 0,
19163        CP1_                },        /* POOL32F_0~*(43) */
19164     { reserved_block      , 0                   , 0   , 32,
19165        0xfc0001ff, 0xa0000160, 0                      , 0,
19166        CP1_                },        /* POOL32F_0~*(44) */
19167     { reserved_block      , 0                   , 0   , 32,
19168        0xfc0001ff, 0xa0000168, 0                      , 0,
19169        CP1_                },        /* POOL32F_0~*(45) */
19170     { pool                , SUB_fmt1            , 2   , 32,
19171        0xfc0001ff, 0xa0000170, 0                      , 0,
19172        CP1_                },        /* SUB.fmt1 */
19173     { reserved_block      , 0                   , 0   , 32,
19174        0xfc0001ff, 0xa0000178, 0                      , 0,
19175        CP1_                },        /* POOL32F_0~*(47) */
19176     { reserved_block      , 0                   , 0   , 32,
19177        0xfc0001ff, 0xa0000180, 0                      , 0,
19178        CP1_                },        /* POOL32F_0~*(48) */
19179     { reserved_block      , 0                   , 0   , 32,
19180        0xfc0001ff, 0xa0000188, 0                      , 0,
19181        CP1_                },        /* POOL32F_0~*(49) */
19182     { reserved_block      , 0                   , 0   , 32,
19183        0xfc0001ff, 0xa0000190, 0                      , 0,
19184        CP1_                },        /* POOL32F_0~*(50) */
19185     { reserved_block      , 0                   , 0   , 32,
19186        0xfc0001ff, 0xa0000198, 0                      , 0,
19187        CP1_                },        /* POOL32F_0~*(51) */
19188     { reserved_block      , 0                   , 0   , 32,
19189        0xfc0001ff, 0xa00001a0, 0                      , 0,
19190        CP1_                },        /* POOL32F_0~*(52) */
19191     { reserved_block      , 0                   , 0   , 32,
19192        0xfc0001ff, 0xa00001a8, 0                      , 0,
19193        CP1_                },        /* POOL32F_0~*(53) */
19194     { pool                , MUL_fmt1            , 2   , 32,
19195        0xfc0001ff, 0xa00001b0, 0                      , 0,
19196        CP1_                },        /* MUL.fmt1 */
19197     { pool                , MADDF_fmt           , 2   , 32,
19198        0xfc0001ff, 0xa00001b8, 0                      , 0,
19199        CP1_                },        /* MADDF.fmt */
19200     { reserved_block      , 0                   , 0   , 32,
19201        0xfc0001ff, 0xa00001c0, 0                      , 0,
19202        CP1_                },        /* POOL32F_0~*(56) */
19203     { reserved_block      , 0                   , 0   , 32,
19204        0xfc0001ff, 0xa00001c8, 0                      , 0,
19205        CP1_                },        /* POOL32F_0~*(57) */
19206     { reserved_block      , 0                   , 0   , 32,
19207        0xfc0001ff, 0xa00001d0, 0                      , 0,
19208        CP1_                },        /* POOL32F_0~*(58) */
19209     { reserved_block      , 0                   , 0   , 32,
19210        0xfc0001ff, 0xa00001d8, 0                      , 0,
19211        CP1_                },        /* POOL32F_0~*(59) */
19212     { reserved_block      , 0                   , 0   , 32,
19213        0xfc0001ff, 0xa00001e0, 0                      , 0,
19214        CP1_                },        /* POOL32F_0~*(60) */
19215     { reserved_block      , 0                   , 0   , 32,
19216        0xfc0001ff, 0xa00001e8, 0                      , 0,
19217        CP1_                },        /* POOL32F_0~*(61) */
19218     { pool                , DIV_fmt1            , 2   , 32,
19219        0xfc0001ff, 0xa00001f0, 0                      , 0,
19220        CP1_                },        /* DIV.fmt1 */
19221     { pool                , MSUBF_fmt           , 2   , 32,
19222        0xfc0001ff, 0xa00001f8, 0                      , 0,
19223        CP1_                },        /* MSUBF.fmt */
19224 };
19225 
19226 
19227 static const Pool MIN_fmt[2] = {
19228     { instruction         , 0                   , 0   , 32,
19229        0xfc00023f, 0xa0000003, &MIN_S            , 0,
19230        CP1_                },        /* MIN.S */
19231     { instruction         , 0                   , 0   , 32,
19232        0xfc00023f, 0xa0000203, &MIN_D            , 0,
19233        CP1_                },        /* MIN.D */
19234 };
19235 
19236 
19237 static const Pool MAX_fmt[2] = {
19238     { instruction         , 0                   , 0   , 32,
19239        0xfc00023f, 0xa000000b, &MAX_S            , 0,
19240        CP1_                },        /* MAX.S */
19241     { instruction         , 0                   , 0   , 32,
19242        0xfc00023f, 0xa000020b, &MAX_D            , 0,
19243        CP1_                },        /* MAX.D */
19244 };
19245 
19246 
19247 static const Pool MINA_fmt[2] = {
19248     { instruction         , 0                   , 0   , 32,
19249        0xfc00023f, 0xa0000023, &MINA_S           , 0,
19250        CP1_                },        /* MINA.S */
19251     { instruction         , 0                   , 0   , 32,
19252        0xfc00023f, 0xa0000223, &MINA_D           , 0,
19253        CP1_                },        /* MINA.D */
19254 };
19255 
19256 
19257 static const Pool MAXA_fmt[2] = {
19258     { instruction         , 0                   , 0   , 32,
19259        0xfc00023f, 0xa000002b, &MAXA_S           , 0,
19260        CP1_                },        /* MAXA.S */
19261     { instruction         , 0                   , 0   , 32,
19262        0xfc00023f, 0xa000022b, &MAXA_D           , 0,
19263        CP1_                },        /* MAXA.D */
19264 };
19265 
19266 
19267 static const Pool CVT_L_fmt[2] = {
19268     { instruction         , 0                   , 0   , 32,
19269        0xfc007fff, 0xa000013b, &CVT_L_S          , 0,
19270        CP1_                },        /* CVT.L.S */
19271     { instruction         , 0                   , 0   , 32,
19272        0xfc007fff, 0xa000413b, &CVT_L_D          , 0,
19273        CP1_                },        /* CVT.L.D */
19274 };
19275 
19276 
19277 static const Pool RSQRT_fmt[2] = {
19278     { instruction         , 0                   , 0   , 32,
19279        0xfc007fff, 0xa000023b, &RSQRT_S          , 0,
19280        CP1_                },        /* RSQRT.S */
19281     { instruction         , 0                   , 0   , 32,
19282        0xfc007fff, 0xa000423b, &RSQRT_D          , 0,
19283        CP1_                },        /* RSQRT.D */
19284 };
19285 
19286 
19287 static const Pool FLOOR_L_fmt[2] = {
19288     { instruction         , 0                   , 0   , 32,
19289        0xfc007fff, 0xa000033b, &FLOOR_L_S        , 0,
19290        CP1_                },        /* FLOOR.L.S */
19291     { instruction         , 0                   , 0   , 32,
19292        0xfc007fff, 0xa000433b, &FLOOR_L_D        , 0,
19293        CP1_                },        /* FLOOR.L.D */
19294 };
19295 
19296 
19297 static const Pool CVT_W_fmt[2] = {
19298     { instruction         , 0                   , 0   , 32,
19299        0xfc007fff, 0xa000093b, &CVT_W_S          , 0,
19300        CP1_                },        /* CVT.W.S */
19301     { instruction         , 0                   , 0   , 32,
19302        0xfc007fff, 0xa000493b, &CVT_W_D          , 0,
19303        CP1_                },        /* CVT.W.D */
19304 };
19305 
19306 
19307 static const Pool SQRT_fmt[2] = {
19308     { instruction         , 0                   , 0   , 32,
19309        0xfc007fff, 0xa0000a3b, &SQRT_S           , 0,
19310        CP1_                },        /* SQRT.S */
19311     { instruction         , 0                   , 0   , 32,
19312        0xfc007fff, 0xa0004a3b, &SQRT_D           , 0,
19313        CP1_                },        /* SQRT.D */
19314 };
19315 
19316 
19317 static const Pool FLOOR_W_fmt[2] = {
19318     { instruction         , 0                   , 0   , 32,
19319        0xfc007fff, 0xa0000b3b, &FLOOR_W_S        , 0,
19320        CP1_                },        /* FLOOR.W.S */
19321     { instruction         , 0                   , 0   , 32,
19322        0xfc007fff, 0xa0004b3b, &FLOOR_W_D        , 0,
19323        CP1_                },        /* FLOOR.W.D */
19324 };
19325 
19326 
19327 static const Pool RECIP_fmt[2] = {
19328     { instruction         , 0                   , 0   , 32,
19329        0xfc007fff, 0xa000123b, &RECIP_S          , 0,
19330        CP1_                },        /* RECIP.S */
19331     { instruction         , 0                   , 0   , 32,
19332        0xfc007fff, 0xa000523b, &RECIP_D          , 0,
19333        CP1_                },        /* RECIP.D */
19334 };
19335 
19336 
19337 static const Pool CEIL_L_fmt[2] = {
19338     { instruction         , 0                   , 0   , 32,
19339        0xfc007fff, 0xa000133b, &CEIL_L_S         , 0,
19340        CP1_                },        /* CEIL.L.S */
19341     { instruction         , 0                   , 0   , 32,
19342        0xfc007fff, 0xa000533b, &CEIL_L_D         , 0,
19343        CP1_                },        /* CEIL.L.D */
19344 };
19345 
19346 
19347 static const Pool CEIL_W_fmt[2] = {
19348     { instruction         , 0                   , 0   , 32,
19349        0xfc007fff, 0xa0001b3b, &CEIL_W_S         , 0,
19350        CP1_                },        /* CEIL.W.S */
19351     { instruction         , 0                   , 0   , 32,
19352        0xfc007fff, 0xa0005b3b, &CEIL_W_D         , 0,
19353        CP1_                },        /* CEIL.W.D */
19354 };
19355 
19356 
19357 static const Pool TRUNC_L_fmt[2] = {
19358     { instruction         , 0                   , 0   , 32,
19359        0xfc007fff, 0xa000233b, &TRUNC_L_S        , 0,
19360        CP1_                },        /* TRUNC.L.S */
19361     { instruction         , 0                   , 0   , 32,
19362        0xfc007fff, 0xa000633b, &TRUNC_L_D        , 0,
19363        CP1_                },        /* TRUNC.L.D */
19364 };
19365 
19366 
19367 static const Pool TRUNC_W_fmt[2] = {
19368     { instruction         , 0                   , 0   , 32,
19369        0xfc007fff, 0xa0002b3b, &TRUNC_W_S        , 0,
19370        CP1_                },        /* TRUNC.W.S */
19371     { instruction         , 0                   , 0   , 32,
19372        0xfc007fff, 0xa0006b3b, &TRUNC_W_D        , 0,
19373        CP1_                },        /* TRUNC.W.D */
19374 };
19375 
19376 
19377 static const Pool ROUND_L_fmt[2] = {
19378     { instruction         , 0                   , 0   , 32,
19379        0xfc007fff, 0xa000333b, &ROUND_L_S        , 0,
19380        CP1_                },        /* ROUND.L.S */
19381     { instruction         , 0                   , 0   , 32,
19382        0xfc007fff, 0xa000733b, &ROUND_L_D        , 0,
19383        CP1_                },        /* ROUND.L.D */
19384 };
19385 
19386 
19387 static const Pool ROUND_W_fmt[2] = {
19388     { instruction         , 0                   , 0   , 32,
19389        0xfc007fff, 0xa0003b3b, &ROUND_W_S        , 0,
19390        CP1_                },        /* ROUND.W.S */
19391     { instruction         , 0                   , 0   , 32,
19392        0xfc007fff, 0xa0007b3b, &ROUND_W_D        , 0,
19393        CP1_                },        /* ROUND.W.D */
19394 };
19395 
19396 
19397 static const Pool POOL32Fxf_0[64] = {
19398     { reserved_block      , 0                   , 0   , 32,
19399        0xfc003fff, 0xa000003b, 0                      , 0,
19400        CP1_                },        /* POOL32Fxf_0~*(0) */
19401     { pool                , CVT_L_fmt           , 2   , 32,
19402        0xfc003fff, 0xa000013b, 0                      , 0,
19403        CP1_                },        /* CVT.L.fmt */
19404     { pool                , RSQRT_fmt           , 2   , 32,
19405        0xfc003fff, 0xa000023b, 0                      , 0,
19406        CP1_                },        /* RSQRT.fmt */
19407     { pool                , FLOOR_L_fmt         , 2   , 32,
19408        0xfc003fff, 0xa000033b, 0                      , 0,
19409        CP1_                },        /* FLOOR.L.fmt */
19410     { reserved_block      , 0                   , 0   , 32,
19411        0xfc003fff, 0xa000043b, 0                      , 0,
19412        CP1_                },        /* POOL32Fxf_0~*(4) */
19413     { reserved_block      , 0                   , 0   , 32,
19414        0xfc003fff, 0xa000053b, 0                      , 0,
19415        CP1_                },        /* POOL32Fxf_0~*(5) */
19416     { reserved_block      , 0                   , 0   , 32,
19417        0xfc003fff, 0xa000063b, 0                      , 0,
19418        CP1_                },        /* POOL32Fxf_0~*(6) */
19419     { reserved_block      , 0                   , 0   , 32,
19420        0xfc003fff, 0xa000073b, 0                      , 0,
19421        CP1_                },        /* POOL32Fxf_0~*(7) */
19422     { reserved_block      , 0                   , 0   , 32,
19423        0xfc003fff, 0xa000083b, 0                      , 0,
19424        CP1_                },        /* POOL32Fxf_0~*(8) */
19425     { pool                , CVT_W_fmt           , 2   , 32,
19426        0xfc003fff, 0xa000093b, 0                      , 0,
19427        CP1_                },        /* CVT.W.fmt */
19428     { pool                , SQRT_fmt            , 2   , 32,
19429        0xfc003fff, 0xa0000a3b, 0                      , 0,
19430        CP1_                },        /* SQRT.fmt */
19431     { pool                , FLOOR_W_fmt         , 2   , 32,
19432        0xfc003fff, 0xa0000b3b, 0                      , 0,
19433        CP1_                },        /* FLOOR.W.fmt */
19434     { reserved_block      , 0                   , 0   , 32,
19435        0xfc003fff, 0xa0000c3b, 0                      , 0,
19436        CP1_                },        /* POOL32Fxf_0~*(12) */
19437     { reserved_block      , 0                   , 0   , 32,
19438        0xfc003fff, 0xa0000d3b, 0                      , 0,
19439        CP1_                },        /* POOL32Fxf_0~*(13) */
19440     { reserved_block      , 0                   , 0   , 32,
19441        0xfc003fff, 0xa0000e3b, 0                      , 0,
19442        CP1_                },        /* POOL32Fxf_0~*(14) */
19443     { reserved_block      , 0                   , 0   , 32,
19444        0xfc003fff, 0xa0000f3b, 0                      , 0,
19445        CP1_                },        /* POOL32Fxf_0~*(15) */
19446     { instruction         , 0                   , 0   , 32,
19447        0xfc003fff, 0xa000103b, &CFC1             , 0,
19448        CP1_                },        /* CFC1 */
19449     { reserved_block      , 0                   , 0   , 32,
19450        0xfc003fff, 0xa000113b, 0                      , 0,
19451        CP1_                },        /* POOL32Fxf_0~*(17) */
19452     { pool                , RECIP_fmt           , 2   , 32,
19453        0xfc003fff, 0xa000123b, 0                      , 0,
19454        CP1_                },        /* RECIP.fmt */
19455     { pool                , CEIL_L_fmt          , 2   , 32,
19456        0xfc003fff, 0xa000133b, 0                      , 0,
19457        CP1_                },        /* CEIL.L.fmt */
19458     { reserved_block      , 0                   , 0   , 32,
19459        0xfc003fff, 0xa000143b, 0                      , 0,
19460        CP1_                },        /* POOL32Fxf_0~*(20) */
19461     { reserved_block      , 0                   , 0   , 32,
19462        0xfc003fff, 0xa000153b, 0                      , 0,
19463        CP1_                },        /* POOL32Fxf_0~*(21) */
19464     { reserved_block      , 0                   , 0   , 32,
19465        0xfc003fff, 0xa000163b, 0                      , 0,
19466        CP1_                },        /* POOL32Fxf_0~*(22) */
19467     { reserved_block      , 0                   , 0   , 32,
19468        0xfc003fff, 0xa000173b, 0                      , 0,
19469        CP1_                },        /* POOL32Fxf_0~*(23) */
19470     { instruction         , 0                   , 0   , 32,
19471        0xfc003fff, 0xa000183b, &CTC1             , 0,
19472        CP1_                },        /* CTC1 */
19473     { reserved_block      , 0                   , 0   , 32,
19474        0xfc003fff, 0xa000193b, 0                      , 0,
19475        CP1_                },        /* POOL32Fxf_0~*(25) */
19476     { reserved_block      , 0                   , 0   , 32,
19477        0xfc003fff, 0xa0001a3b, 0                      , 0,
19478        CP1_                },        /* POOL32Fxf_0~*(26) */
19479     { pool                , CEIL_W_fmt          , 2   , 32,
19480        0xfc003fff, 0xa0001b3b, 0                      , 0,
19481        CP1_                },        /* CEIL.W.fmt */
19482     { reserved_block      , 0                   , 0   , 32,
19483        0xfc003fff, 0xa0001c3b, 0                      , 0,
19484        CP1_                },        /* POOL32Fxf_0~*(28) */
19485     { reserved_block      , 0                   , 0   , 32,
19486        0xfc003fff, 0xa0001d3b, 0                      , 0,
19487        CP1_                },        /* POOL32Fxf_0~*(29) */
19488     { reserved_block      , 0                   , 0   , 32,
19489        0xfc003fff, 0xa0001e3b, 0                      , 0,
19490        CP1_                },        /* POOL32Fxf_0~*(30) */
19491     { reserved_block      , 0                   , 0   , 32,
19492        0xfc003fff, 0xa0001f3b, 0                      , 0,
19493        CP1_                },        /* POOL32Fxf_0~*(31) */
19494     { instruction         , 0                   , 0   , 32,
19495        0xfc003fff, 0xa000203b, &MFC1             , 0,
19496        CP1_                },        /* MFC1 */
19497     { instruction         , 0                   , 0   , 32,
19498        0xfc003fff, 0xa000213b, &CVT_S_PL         , 0,
19499        CP1_                },        /* CVT.S.PL */
19500     { reserved_block      , 0                   , 0   , 32,
19501        0xfc003fff, 0xa000223b, 0                      , 0,
19502        CP1_                },        /* POOL32Fxf_0~*(34) */
19503     { pool                , TRUNC_L_fmt         , 2   , 32,
19504        0xfc003fff, 0xa000233b, 0                      , 0,
19505        CP1_                },        /* TRUNC.L.fmt */
19506     { instruction         , 0                   , 0   , 32,
19507        0xfc003fff, 0xa000243b, &DMFC1            , 0,
19508        CP1_ | MIPS64_      },        /* DMFC1 */
19509     { reserved_block      , 0                   , 0   , 32,
19510        0xfc003fff, 0xa000253b, 0                      , 0,
19511        CP1_                },        /* POOL32Fxf_0~*(37) */
19512     { reserved_block      , 0                   , 0   , 32,
19513        0xfc003fff, 0xa000263b, 0                      , 0,
19514        CP1_                },        /* POOL32Fxf_0~*(38) */
19515     { reserved_block      , 0                   , 0   , 32,
19516        0xfc003fff, 0xa000273b, 0                      , 0,
19517        CP1_                },        /* POOL32Fxf_0~*(39) */
19518     { instruction         , 0                   , 0   , 32,
19519        0xfc003fff, 0xa000283b, &MTC1             , 0,
19520        CP1_                },        /* MTC1 */
19521     { instruction         , 0                   , 0   , 32,
19522        0xfc003fff, 0xa000293b, &CVT_S_PU         , 0,
19523        CP1_                },        /* CVT.S.PU */
19524     { reserved_block      , 0                   , 0   , 32,
19525        0xfc003fff, 0xa0002a3b, 0                      , 0,
19526        CP1_                },        /* POOL32Fxf_0~*(42) */
19527     { pool                , TRUNC_W_fmt         , 2   , 32,
19528        0xfc003fff, 0xa0002b3b, 0                      , 0,
19529        CP1_                },        /* TRUNC.W.fmt */
19530     { instruction         , 0                   , 0   , 32,
19531        0xfc003fff, 0xa0002c3b, &DMTC1            , 0,
19532        CP1_ | MIPS64_      },        /* DMTC1 */
19533     { reserved_block      , 0                   , 0   , 32,
19534        0xfc003fff, 0xa0002d3b, 0                      , 0,
19535        CP1_                },        /* POOL32Fxf_0~*(45) */
19536     { reserved_block      , 0                   , 0   , 32,
19537        0xfc003fff, 0xa0002e3b, 0                      , 0,
19538        CP1_                },        /* POOL32Fxf_0~*(46) */
19539     { reserved_block      , 0                   , 0   , 32,
19540        0xfc003fff, 0xa0002f3b, 0                      , 0,
19541        CP1_                },        /* POOL32Fxf_0~*(47) */
19542     { instruction         , 0                   , 0   , 32,
19543        0xfc003fff, 0xa000303b, &MFHC1            , 0,
19544        CP1_                },        /* MFHC1 */
19545     { reserved_block      , 0                   , 0   , 32,
19546        0xfc003fff, 0xa000313b, 0                      , 0,
19547        CP1_                },        /* POOL32Fxf_0~*(49) */
19548     { reserved_block      , 0                   , 0   , 32,
19549        0xfc003fff, 0xa000323b, 0                      , 0,
19550        CP1_                },        /* POOL32Fxf_0~*(50) */
19551     { pool                , ROUND_L_fmt         , 2   , 32,
19552        0xfc003fff, 0xa000333b, 0                      , 0,
19553        CP1_                },        /* ROUND.L.fmt */
19554     { reserved_block      , 0                   , 0   , 32,
19555        0xfc003fff, 0xa000343b, 0                      , 0,
19556        CP1_                },        /* POOL32Fxf_0~*(52) */
19557     { reserved_block      , 0                   , 0   , 32,
19558        0xfc003fff, 0xa000353b, 0                      , 0,
19559        CP1_                },        /* POOL32Fxf_0~*(53) */
19560     { reserved_block      , 0                   , 0   , 32,
19561        0xfc003fff, 0xa000363b, 0                      , 0,
19562        CP1_                },        /* POOL32Fxf_0~*(54) */
19563     { reserved_block      , 0                   , 0   , 32,
19564        0xfc003fff, 0xa000373b, 0                      , 0,
19565        CP1_                },        /* POOL32Fxf_0~*(55) */
19566     { instruction         , 0                   , 0   , 32,
19567        0xfc003fff, 0xa000383b, &MTHC1            , 0,
19568        CP1_                },        /* MTHC1 */
19569     { reserved_block      , 0                   , 0   , 32,
19570        0xfc003fff, 0xa000393b, 0                      , 0,
19571        CP1_                },        /* POOL32Fxf_0~*(57) */
19572     { reserved_block      , 0                   , 0   , 32,
19573        0xfc003fff, 0xa0003a3b, 0                      , 0,
19574        CP1_                },        /* POOL32Fxf_0~*(58) */
19575     { pool                , ROUND_W_fmt         , 2   , 32,
19576        0xfc003fff, 0xa0003b3b, 0                      , 0,
19577        CP1_                },        /* ROUND.W.fmt */
19578     { reserved_block      , 0                   , 0   , 32,
19579        0xfc003fff, 0xa0003c3b, 0                      , 0,
19580        CP1_                },        /* POOL32Fxf_0~*(60) */
19581     { reserved_block      , 0                   , 0   , 32,
19582        0xfc003fff, 0xa0003d3b, 0                      , 0,
19583        CP1_                },        /* POOL32Fxf_0~*(61) */
19584     { reserved_block      , 0                   , 0   , 32,
19585        0xfc003fff, 0xa0003e3b, 0                      , 0,
19586        CP1_                },        /* POOL32Fxf_0~*(62) */
19587     { reserved_block      , 0                   , 0   , 32,
19588        0xfc003fff, 0xa0003f3b, 0                      , 0,
19589        CP1_                },        /* POOL32Fxf_0~*(63) */
19590 };
19591 
19592 
19593 static const Pool MOV_fmt[4] = {
19594     { instruction         , 0                   , 0   , 32,
19595        0xfc007fff, 0xa000007b, &MOV_S            , 0,
19596        CP1_                },        /* MOV.S */
19597     { instruction         , 0                   , 0   , 32,
19598        0xfc007fff, 0xa000207b, &MOV_D            , 0,
19599        CP1_                },        /* MOV.D */
19600     { reserved_block      , 0                   , 0   , 32,
19601        0xfc007fff, 0xa000407b, 0                      , 0,
19602        CP1_                },        /* MOV.fmt~*(2) */
19603     { reserved_block      , 0                   , 0   , 32,
19604        0xfc007fff, 0xa000607b, 0                      , 0,
19605        CP1_                },        /* MOV.fmt~*(3) */
19606 };
19607 
19608 
19609 static const Pool ABS_fmt[4] = {
19610     { instruction         , 0                   , 0   , 32,
19611        0xfc007fff, 0xa000037b, &ABS_S            , 0,
19612        CP1_                },        /* ABS.S */
19613     { instruction         , 0                   , 0   , 32,
19614        0xfc007fff, 0xa000237b, &ABS_D            , 0,
19615        CP1_                },        /* ABS.D */
19616     { reserved_block      , 0                   , 0   , 32,
19617        0xfc007fff, 0xa000437b, 0                      , 0,
19618        CP1_                },        /* ABS.fmt~*(2) */
19619     { reserved_block      , 0                   , 0   , 32,
19620        0xfc007fff, 0xa000637b, 0                      , 0,
19621        CP1_                },        /* ABS.fmt~*(3) */
19622 };
19623 
19624 
19625 static const Pool NEG_fmt[4] = {
19626     { instruction         , 0                   , 0   , 32,
19627        0xfc007fff, 0xa0000b7b, &NEG_S            , 0,
19628        CP1_                },        /* NEG.S */
19629     { instruction         , 0                   , 0   , 32,
19630        0xfc007fff, 0xa0002b7b, &NEG_D            , 0,
19631        CP1_                },        /* NEG.D */
19632     { reserved_block      , 0                   , 0   , 32,
19633        0xfc007fff, 0xa0004b7b, 0                      , 0,
19634        CP1_                },        /* NEG.fmt~*(2) */
19635     { reserved_block      , 0                   , 0   , 32,
19636        0xfc007fff, 0xa0006b7b, 0                      , 0,
19637        CP1_                },        /* NEG.fmt~*(3) */
19638 };
19639 
19640 
19641 static const Pool CVT_D_fmt[4] = {
19642     { instruction         , 0                   , 0   , 32,
19643        0xfc007fff, 0xa000137b, &CVT_D_S          , 0,
19644        CP1_                },        /* CVT.D.S */
19645     { instruction         , 0                   , 0   , 32,
19646        0xfc007fff, 0xa000337b, &CVT_D_W          , 0,
19647        CP1_                },        /* CVT.D.W */
19648     { instruction         , 0                   , 0   , 32,
19649        0xfc007fff, 0xa000537b, &CVT_D_L          , 0,
19650        CP1_                },        /* CVT.D.L */
19651     { reserved_block      , 0                   , 0   , 32,
19652        0xfc007fff, 0xa000737b, 0                      , 0,
19653        CP1_                },        /* CVT.D.fmt~*(3) */
19654 };
19655 
19656 
19657 static const Pool CVT_S_fmt[4] = {
19658     { instruction         , 0                   , 0   , 32,
19659        0xfc007fff, 0xa0001b7b, &CVT_S_D          , 0,
19660        CP1_                },        /* CVT.S.D */
19661     { instruction         , 0                   , 0   , 32,
19662        0xfc007fff, 0xa0003b7b, &CVT_S_W          , 0,
19663        CP1_                },        /* CVT.S.W */
19664     { instruction         , 0                   , 0   , 32,
19665        0xfc007fff, 0xa0005b7b, &CVT_S_L          , 0,
19666        CP1_                },        /* CVT.S.L */
19667     { reserved_block      , 0                   , 0   , 32,
19668        0xfc007fff, 0xa0007b7b, 0                      , 0,
19669        CP1_                },        /* CVT.S.fmt~*(3) */
19670 };
19671 
19672 
19673 static const Pool POOL32Fxf_1[32] = {
19674     { pool                , MOV_fmt             , 4   , 32,
19675        0xfc001fff, 0xa000007b, 0                      , 0,
19676        CP1_                },        /* MOV.fmt */
19677     { reserved_block      , 0                   , 0   , 32,
19678        0xfc001fff, 0xa000017b, 0                      , 0,
19679        CP1_                },        /* POOL32Fxf_1~*(1) */
19680     { reserved_block      , 0                   , 0   , 32,
19681        0xfc001fff, 0xa000027b, 0                      , 0,
19682        CP1_                },        /* POOL32Fxf_1~*(2) */
19683     { pool                , ABS_fmt             , 4   , 32,
19684        0xfc001fff, 0xa000037b, 0                      , 0,
19685        CP1_                },        /* ABS.fmt */
19686     { reserved_block      , 0                   , 0   , 32,
19687        0xfc001fff, 0xa000047b, 0                      , 0,
19688        CP1_                },        /* POOL32Fxf_1~*(4) */
19689     { reserved_block      , 0                   , 0   , 32,
19690        0xfc001fff, 0xa000057b, 0                      , 0,
19691        CP1_                },        /* POOL32Fxf_1~*(5) */
19692     { reserved_block      , 0                   , 0   , 32,
19693        0xfc001fff, 0xa000067b, 0                      , 0,
19694        CP1_                },        /* POOL32Fxf_1~*(6) */
19695     { reserved_block      , 0                   , 0   , 32,
19696        0xfc001fff, 0xa000077b, 0                      , 0,
19697        CP1_                },        /* POOL32Fxf_1~*(7) */
19698     { reserved_block      , 0                   , 0   , 32,
19699        0xfc001fff, 0xa000087b, 0                      , 0,
19700        CP1_                },        /* POOL32Fxf_1~*(8) */
19701     { reserved_block      , 0                   , 0   , 32,
19702        0xfc001fff, 0xa000097b, 0                      , 0,
19703        CP1_                },        /* POOL32Fxf_1~*(9) */
19704     { reserved_block      , 0                   , 0   , 32,
19705        0xfc001fff, 0xa0000a7b, 0                      , 0,
19706        CP1_                },        /* POOL32Fxf_1~*(10) */
19707     { pool                , NEG_fmt             , 4   , 32,
19708        0xfc001fff, 0xa0000b7b, 0                      , 0,
19709        CP1_                },        /* NEG.fmt */
19710     { reserved_block      , 0                   , 0   , 32,
19711        0xfc001fff, 0xa0000c7b, 0                      , 0,
19712        CP1_                },        /* POOL32Fxf_1~*(12) */
19713     { reserved_block      , 0                   , 0   , 32,
19714        0xfc001fff, 0xa0000d7b, 0                      , 0,
19715        CP1_                },        /* POOL32Fxf_1~*(13) */
19716     { reserved_block      , 0                   , 0   , 32,
19717        0xfc001fff, 0xa0000e7b, 0                      , 0,
19718        CP1_                },        /* POOL32Fxf_1~*(14) */
19719     { reserved_block      , 0                   , 0   , 32,
19720        0xfc001fff, 0xa0000f7b, 0                      , 0,
19721        CP1_                },        /* POOL32Fxf_1~*(15) */
19722     { reserved_block      , 0                   , 0   , 32,
19723        0xfc001fff, 0xa000107b, 0                      , 0,
19724        CP1_                },        /* POOL32Fxf_1~*(16) */
19725     { reserved_block      , 0                   , 0   , 32,
19726        0xfc001fff, 0xa000117b, 0                      , 0,
19727        CP1_                },        /* POOL32Fxf_1~*(17) */
19728     { reserved_block      , 0                   , 0   , 32,
19729        0xfc001fff, 0xa000127b, 0                      , 0,
19730        CP1_                },        /* POOL32Fxf_1~*(18) */
19731     { pool                , CVT_D_fmt           , 4   , 32,
19732        0xfc001fff, 0xa000137b, 0                      , 0,
19733        CP1_                },        /* CVT.D.fmt */
19734     { reserved_block      , 0                   , 0   , 32,
19735        0xfc001fff, 0xa000147b, 0                      , 0,
19736        CP1_                },        /* POOL32Fxf_1~*(20) */
19737     { reserved_block      , 0                   , 0   , 32,
19738        0xfc001fff, 0xa000157b, 0                      , 0,
19739        CP1_                },        /* POOL32Fxf_1~*(21) */
19740     { reserved_block      , 0                   , 0   , 32,
19741        0xfc001fff, 0xa000167b, 0                      , 0,
19742        CP1_                },        /* POOL32Fxf_1~*(22) */
19743     { reserved_block      , 0                   , 0   , 32,
19744        0xfc001fff, 0xa000177b, 0                      , 0,
19745        CP1_                },        /* POOL32Fxf_1~*(23) */
19746     { reserved_block      , 0                   , 0   , 32,
19747        0xfc001fff, 0xa000187b, 0                      , 0,
19748        CP1_                },        /* POOL32Fxf_1~*(24) */
19749     { reserved_block      , 0                   , 0   , 32,
19750        0xfc001fff, 0xa000197b, 0                      , 0,
19751        CP1_                },        /* POOL32Fxf_1~*(25) */
19752     { reserved_block      , 0                   , 0   , 32,
19753        0xfc001fff, 0xa0001a7b, 0                      , 0,
19754        CP1_                },        /* POOL32Fxf_1~*(26) */
19755     { pool                , CVT_S_fmt           , 4   , 32,
19756        0xfc001fff, 0xa0001b7b, 0                      , 0,
19757        CP1_                },        /* CVT.S.fmt */
19758     { reserved_block      , 0                   , 0   , 32,
19759        0xfc001fff, 0xa0001c7b, 0                      , 0,
19760        CP1_                },        /* POOL32Fxf_1~*(28) */
19761     { reserved_block      , 0                   , 0   , 32,
19762        0xfc001fff, 0xa0001d7b, 0                      , 0,
19763        CP1_                },        /* POOL32Fxf_1~*(29) */
19764     { reserved_block      , 0                   , 0   , 32,
19765        0xfc001fff, 0xa0001e7b, 0                      , 0,
19766        CP1_                },        /* POOL32Fxf_1~*(30) */
19767     { reserved_block      , 0                   , 0   , 32,
19768        0xfc001fff, 0xa0001f7b, 0                      , 0,
19769        CP1_                },        /* POOL32Fxf_1~*(31) */
19770 };
19771 
19772 
19773 static const Pool POOL32Fxf[4] = {
19774     { pool                , POOL32Fxf_0         , 64  , 32,
19775        0xfc0000ff, 0xa000003b, 0                      , 0,
19776        CP1_                },        /* POOL32Fxf_0 */
19777     { pool                , POOL32Fxf_1         , 32  , 32,
19778        0xfc0000ff, 0xa000007b, 0                      , 0,
19779        CP1_                },        /* POOL32Fxf_1 */
19780     { reserved_block      , 0                   , 0   , 32,
19781        0xfc0000ff, 0xa00000bb, 0                      , 0,
19782        CP1_                },        /* POOL32Fxf~*(2) */
19783     { reserved_block      , 0                   , 0   , 32,
19784        0xfc0000ff, 0xa00000fb, 0                      , 0,
19785        CP1_                },        /* POOL32Fxf~*(3) */
19786 };
19787 
19788 
19789 static const Pool POOL32F_3[8] = {
19790     { pool                , MIN_fmt             , 2   , 32,
19791        0xfc00003f, 0xa0000003, 0                      , 0,
19792        CP1_                },        /* MIN.fmt */
19793     { pool                , MAX_fmt             , 2   , 32,
19794        0xfc00003f, 0xa000000b, 0                      , 0,
19795        CP1_                },        /* MAX.fmt */
19796     { reserved_block      , 0                   , 0   , 32,
19797        0xfc00003f, 0xa0000013, 0                      , 0,
19798        CP1_                },        /* POOL32F_3~*(2) */
19799     { reserved_block      , 0                   , 0   , 32,
19800        0xfc00003f, 0xa000001b, 0                      , 0,
19801        CP1_                },        /* POOL32F_3~*(3) */
19802     { pool                , MINA_fmt            , 2   , 32,
19803        0xfc00003f, 0xa0000023, 0                      , 0,
19804        CP1_                },        /* MINA.fmt */
19805     { pool                , MAXA_fmt            , 2   , 32,
19806        0xfc00003f, 0xa000002b, 0                      , 0,
19807        CP1_                },        /* MAXA.fmt */
19808     { reserved_block      , 0                   , 0   , 32,
19809        0xfc00003f, 0xa0000033, 0                      , 0,
19810        CP1_                },        /* POOL32F_3~*(6) */
19811     { pool                , POOL32Fxf           , 4   , 32,
19812        0xfc00003f, 0xa000003b, 0                      , 0,
19813        CP1_                },        /* POOL32Fxf */
19814 };
19815 
19816 
19817 static const Pool CMP_condn_S[32] = {
19818     { instruction         , 0                   , 0   , 32,
19819        0xfc0007ff, 0xa0000005, &CMP_AF_S         , 0,
19820        CP1_                },        /* CMP.AF.S */
19821     { instruction         , 0                   , 0   , 32,
19822        0xfc0007ff, 0xa0000045, &CMP_UN_S         , 0,
19823        CP1_                },        /* CMP.UN.S */
19824     { instruction         , 0                   , 0   , 32,
19825        0xfc0007ff, 0xa0000085, &CMP_EQ_S         , 0,
19826        CP1_                },        /* CMP.EQ.S */
19827     { instruction         , 0                   , 0   , 32,
19828        0xfc0007ff, 0xa00000c5, &CMP_UEQ_S        , 0,
19829        CP1_                },        /* CMP.UEQ.S */
19830     { instruction         , 0                   , 0   , 32,
19831        0xfc0007ff, 0xa0000105, &CMP_LT_S         , 0,
19832        CP1_                },        /* CMP.LT.S */
19833     { instruction         , 0                   , 0   , 32,
19834        0xfc0007ff, 0xa0000145, &CMP_ULT_S        , 0,
19835        CP1_                },        /* CMP.ULT.S */
19836     { instruction         , 0                   , 0   , 32,
19837        0xfc0007ff, 0xa0000185, &CMP_LE_S         , 0,
19838        CP1_                },        /* CMP.LE.S */
19839     { instruction         , 0                   , 0   , 32,
19840        0xfc0007ff, 0xa00001c5, &CMP_ULE_S        , 0,
19841        CP1_                },        /* CMP.ULE.S */
19842     { instruction         , 0                   , 0   , 32,
19843        0xfc0007ff, 0xa0000205, &CMP_SAF_S        , 0,
19844        CP1_                },        /* CMP.SAF.S */
19845     { instruction         , 0                   , 0   , 32,
19846        0xfc0007ff, 0xa0000245, &CMP_SUN_S        , 0,
19847        CP1_                },        /* CMP.SUN.S */
19848     { instruction         , 0                   , 0   , 32,
19849        0xfc0007ff, 0xa0000285, &CMP_SEQ_S        , 0,
19850        CP1_                },        /* CMP.SEQ.S */
19851     { instruction         , 0                   , 0   , 32,
19852        0xfc0007ff, 0xa00002c5, &CMP_SUEQ_S       , 0,
19853        CP1_                },        /* CMP.SUEQ.S */
19854     { instruction         , 0                   , 0   , 32,
19855        0xfc0007ff, 0xa0000305, &CMP_SLT_S        , 0,
19856        CP1_                },        /* CMP.SLT.S */
19857     { instruction         , 0                   , 0   , 32,
19858        0xfc0007ff, 0xa0000345, &CMP_SULT_S       , 0,
19859        CP1_                },        /* CMP.SULT.S */
19860     { instruction         , 0                   , 0   , 32,
19861        0xfc0007ff, 0xa0000385, &CMP_SLE_S        , 0,
19862        CP1_                },        /* CMP.SLE.S */
19863     { instruction         , 0                   , 0   , 32,
19864        0xfc0007ff, 0xa00003c5, &CMP_SULE_S       , 0,
19865        CP1_                },        /* CMP.SULE.S */
19866     { reserved_block      , 0                   , 0   , 32,
19867        0xfc0007ff, 0xa0000405, 0                      , 0,
19868        CP1_                },        /* CMP.condn.S~*(16) */
19869     { instruction         , 0                   , 0   , 32,
19870        0xfc0007ff, 0xa0000445, &CMP_OR_S         , 0,
19871        CP1_                },        /* CMP.OR.S */
19872     { instruction         , 0                   , 0   , 32,
19873        0xfc0007ff, 0xa0000485, &CMP_UNE_S        , 0,
19874        CP1_                },        /* CMP.UNE.S */
19875     { instruction         , 0                   , 0   , 32,
19876        0xfc0007ff, 0xa00004c5, &CMP_NE_S         , 0,
19877        CP1_                },        /* CMP.NE.S */
19878     { reserved_block      , 0                   , 0   , 32,
19879        0xfc0007ff, 0xa0000505, 0                      , 0,
19880        CP1_                },        /* CMP.condn.S~*(20) */
19881     { reserved_block      , 0                   , 0   , 32,
19882        0xfc0007ff, 0xa0000545, 0                      , 0,
19883        CP1_                },        /* CMP.condn.S~*(21) */
19884     { reserved_block      , 0                   , 0   , 32,
19885        0xfc0007ff, 0xa0000585, 0                      , 0,
19886        CP1_                },        /* CMP.condn.S~*(22) */
19887     { reserved_block      , 0                   , 0   , 32,
19888        0xfc0007ff, 0xa00005c5, 0                      , 0,
19889        CP1_                },        /* CMP.condn.S~*(23) */
19890     { reserved_block      , 0                   , 0   , 32,
19891        0xfc0007ff, 0xa0000605, 0                      , 0,
19892        CP1_                },        /* CMP.condn.S~*(24) */
19893     { instruction         , 0                   , 0   , 32,
19894        0xfc0007ff, 0xa0000645, &CMP_SOR_S        , 0,
19895        CP1_                },        /* CMP.SOR.S */
19896     { instruction         , 0                   , 0   , 32,
19897        0xfc0007ff, 0xa0000685, &CMP_SUNE_S       , 0,
19898        CP1_                },        /* CMP.SUNE.S */
19899     { instruction         , 0                   , 0   , 32,
19900        0xfc0007ff, 0xa00006c5, &CMP_SNE_S        , 0,
19901        CP1_                },        /* CMP.SNE.S */
19902     { reserved_block      , 0                   , 0   , 32,
19903        0xfc0007ff, 0xa0000705, 0                      , 0,
19904        CP1_                },        /* CMP.condn.S~*(28) */
19905     { reserved_block      , 0                   , 0   , 32,
19906        0xfc0007ff, 0xa0000745, 0                      , 0,
19907        CP1_                },        /* CMP.condn.S~*(29) */
19908     { reserved_block      , 0                   , 0   , 32,
19909        0xfc0007ff, 0xa0000785, 0                      , 0,
19910        CP1_                },        /* CMP.condn.S~*(30) */
19911     { reserved_block      , 0                   , 0   , 32,
19912        0xfc0007ff, 0xa00007c5, 0                      , 0,
19913        CP1_                },        /* CMP.condn.S~*(31) */
19914 };
19915 
19916 
19917 static const Pool CMP_condn_D[32] = {
19918     { instruction         , 0                   , 0   , 32,
19919        0xfc0007ff, 0xa0000015, &CMP_AF_D         , 0,
19920        CP1_                },        /* CMP.AF.D */
19921     { instruction         , 0                   , 0   , 32,
19922        0xfc0007ff, 0xa0000055, &CMP_UN_D         , 0,
19923        CP1_                },        /* CMP.UN.D */
19924     { instruction         , 0                   , 0   , 32,
19925        0xfc0007ff, 0xa0000095, &CMP_EQ_D         , 0,
19926        CP1_                },        /* CMP.EQ.D */
19927     { instruction         , 0                   , 0   , 32,
19928        0xfc0007ff, 0xa00000d5, &CMP_UEQ_D        , 0,
19929        CP1_                },        /* CMP.UEQ.D */
19930     { instruction         , 0                   , 0   , 32,
19931        0xfc0007ff, 0xa0000115, &CMP_LT_D         , 0,
19932        CP1_                },        /* CMP.LT.D */
19933     { instruction         , 0                   , 0   , 32,
19934        0xfc0007ff, 0xa0000155, &CMP_ULT_D        , 0,
19935        CP1_                },        /* CMP.ULT.D */
19936     { instruction         , 0                   , 0   , 32,
19937        0xfc0007ff, 0xa0000195, &CMP_LE_D         , 0,
19938        CP1_                },        /* CMP.LE.D */
19939     { instruction         , 0                   , 0   , 32,
19940        0xfc0007ff, 0xa00001d5, &CMP_ULE_D        , 0,
19941        CP1_                },        /* CMP.ULE.D */
19942     { instruction         , 0                   , 0   , 32,
19943        0xfc0007ff, 0xa0000215, &CMP_SAF_D        , 0,
19944        CP1_                },        /* CMP.SAF.D */
19945     { instruction         , 0                   , 0   , 32,
19946        0xfc0007ff, 0xa0000255, &CMP_SUN_D        , 0,
19947        CP1_                },        /* CMP.SUN.D */
19948     { instruction         , 0                   , 0   , 32,
19949        0xfc0007ff, 0xa0000295, &CMP_SEQ_D        , 0,
19950        CP1_                },        /* CMP.SEQ.D */
19951     { instruction         , 0                   , 0   , 32,
19952        0xfc0007ff, 0xa00002d5, &CMP_SUEQ_D       , 0,
19953        CP1_                },        /* CMP.SUEQ.D */
19954     { instruction         , 0                   , 0   , 32,
19955        0xfc0007ff, 0xa0000315, &CMP_SLT_D        , 0,
19956        CP1_                },        /* CMP.SLT.D */
19957     { instruction         , 0                   , 0   , 32,
19958        0xfc0007ff, 0xa0000355, &CMP_SULT_D       , 0,
19959        CP1_                },        /* CMP.SULT.D */
19960     { instruction         , 0                   , 0   , 32,
19961        0xfc0007ff, 0xa0000395, &CMP_SLE_D        , 0,
19962        CP1_                },        /* CMP.SLE.D */
19963     { instruction         , 0                   , 0   , 32,
19964        0xfc0007ff, 0xa00003d5, &CMP_SULE_D       , 0,
19965        CP1_                },        /* CMP.SULE.D */
19966     { reserved_block      , 0                   , 0   , 32,
19967        0xfc0007ff, 0xa0000415, 0                      , 0,
19968        CP1_                },        /* CMP.condn.D~*(16) */
19969     { instruction         , 0                   , 0   , 32,
19970        0xfc0007ff, 0xa0000455, &CMP_OR_D         , 0,
19971        CP1_                },        /* CMP.OR.D */
19972     { instruction         , 0                   , 0   , 32,
19973        0xfc0007ff, 0xa0000495, &CMP_UNE_D        , 0,
19974        CP1_                },        /* CMP.UNE.D */
19975     { instruction         , 0                   , 0   , 32,
19976        0xfc0007ff, 0xa00004d5, &CMP_NE_D         , 0,
19977        CP1_                },        /* CMP.NE.D */
19978     { reserved_block      , 0                   , 0   , 32,
19979        0xfc0007ff, 0xa0000515, 0                      , 0,
19980        CP1_                },        /* CMP.condn.D~*(20) */
19981     { reserved_block      , 0                   , 0   , 32,
19982        0xfc0007ff, 0xa0000555, 0                      , 0,
19983        CP1_                },        /* CMP.condn.D~*(21) */
19984     { reserved_block      , 0                   , 0   , 32,
19985        0xfc0007ff, 0xa0000595, 0                      , 0,
19986        CP1_                },        /* CMP.condn.D~*(22) */
19987     { reserved_block      , 0                   , 0   , 32,
19988        0xfc0007ff, 0xa00005d5, 0                      , 0,
19989        CP1_                },        /* CMP.condn.D~*(23) */
19990     { reserved_block      , 0                   , 0   , 32,
19991        0xfc0007ff, 0xa0000615, 0                      , 0,
19992        CP1_                },        /* CMP.condn.D~*(24) */
19993     { instruction         , 0                   , 0   , 32,
19994        0xfc0007ff, 0xa0000655, &CMP_SOR_D        , 0,
19995        CP1_                },        /* CMP.SOR.D */
19996     { instruction         , 0                   , 0   , 32,
19997        0xfc0007ff, 0xa0000695, &CMP_SUNE_D       , 0,
19998        CP1_                },        /* CMP.SUNE.D */
19999     { instruction         , 0                   , 0   , 32,
20000        0xfc0007ff, 0xa00006d5, &CMP_SNE_D        , 0,
20001        CP1_                },        /* CMP.SNE.D */
20002     { reserved_block      , 0                   , 0   , 32,
20003        0xfc0007ff, 0xa0000715, 0                      , 0,
20004        CP1_                },        /* CMP.condn.D~*(28) */
20005     { reserved_block      , 0                   , 0   , 32,
20006        0xfc0007ff, 0xa0000755, 0                      , 0,
20007        CP1_                },        /* CMP.condn.D~*(29) */
20008     { reserved_block      , 0                   , 0   , 32,
20009        0xfc0007ff, 0xa0000795, 0                      , 0,
20010        CP1_                },        /* CMP.condn.D~*(30) */
20011     { reserved_block      , 0                   , 0   , 32,
20012        0xfc0007ff, 0xa00007d5, 0                      , 0,
20013        CP1_                },        /* CMP.condn.D~*(31) */
20014 };
20015 
20016 
20017 static const Pool POOL32F_5[8] = {
20018     { pool                , CMP_condn_S         , 32  , 32,
20019        0xfc00003f, 0xa0000005, 0                      , 0,
20020        CP1_                },        /* CMP.condn.S */
20021     { reserved_block      , 0                   , 0   , 32,
20022        0xfc00003f, 0xa000000d, 0                      , 0,
20023        CP1_                },        /* POOL32F_5~*(1) */
20024     { pool                , CMP_condn_D         , 32  , 32,
20025        0xfc00003f, 0xa0000015, 0                      , 0,
20026        CP1_                },        /* CMP.condn.D */
20027     { reserved_block      , 0                   , 0   , 32,
20028        0xfc00003f, 0xa000001d, 0                      , 0,
20029        CP1_                },        /* POOL32F_5~*(3) */
20030     { reserved_block      , 0                   , 0   , 32,
20031        0xfc00003f, 0xa0000025, 0                      , 0,
20032        CP1_                },        /* POOL32F_5~*(4) */
20033     { reserved_block      , 0                   , 0   , 32,
20034        0xfc00003f, 0xa000002d, 0                      , 0,
20035        CP1_                },        /* POOL32F_5~*(5) */
20036     { reserved_block      , 0                   , 0   , 32,
20037        0xfc00003f, 0xa0000035, 0                      , 0,
20038        CP1_                },        /* POOL32F_5~*(6) */
20039     { reserved_block      , 0                   , 0   , 32,
20040        0xfc00003f, 0xa000003d, 0                      , 0,
20041        CP1_                },        /* POOL32F_5~*(7) */
20042 };
20043 
20044 
20045 static const Pool POOL32F[8] = {
20046     { pool                , POOL32F_0           , 64  , 32,
20047        0xfc000007, 0xa0000000, 0                      , 0,
20048        CP1_                },        /* POOL32F_0 */
20049     { reserved_block      , 0                   , 0   , 32,
20050        0xfc000007, 0xa0000001, 0                      , 0,
20051        CP1_                },        /* POOL32F~*(1) */
20052     { reserved_block      , 0                   , 0   , 32,
20053        0xfc000007, 0xa0000002, 0                      , 0,
20054        CP1_                },        /* POOL32F~*(2) */
20055     { pool                , POOL32F_3           , 8   , 32,
20056        0xfc000007, 0xa0000003, 0                      , 0,
20057        CP1_                },        /* POOL32F_3 */
20058     { reserved_block      , 0                   , 0   , 32,
20059        0xfc000007, 0xa0000004, 0                      , 0,
20060        CP1_                },        /* POOL32F~*(4) */
20061     { pool                , POOL32F_5           , 8   , 32,
20062        0xfc000007, 0xa0000005, 0                      , 0,
20063        CP1_                },        /* POOL32F_5 */
20064     { reserved_block      , 0                   , 0   , 32,
20065        0xfc000007, 0xa0000006, 0                      , 0,
20066        CP1_                },        /* POOL32F~*(6) */
20067     { reserved_block      , 0                   , 0   , 32,
20068        0xfc000007, 0xa0000007, 0                      , 0,
20069        CP1_                },        /* POOL32F~*(7) */
20070 };
20071 
20072 
20073 static const Pool POOL32S_0[64] = {
20074     { reserved_block      , 0                   , 0   , 32,
20075        0xfc0001ff, 0xc0000000, 0                      , 0,
20076        0x0                 },        /* POOL32S_0~*(0) */
20077     { instruction         , 0                   , 0   , 32,
20078        0xfc0001ff, 0xc0000008, &DLSA             , 0,
20079        MIPS64_             },        /* DLSA */
20080     { instruction         , 0                   , 0   , 32,
20081        0xfc0001ff, 0xc0000010, &DSLLV            , 0,
20082        MIPS64_             },        /* DSLLV */
20083     { instruction         , 0                   , 0   , 32,
20084        0xfc0001ff, 0xc0000018, &DMUL             , 0,
20085        MIPS64_             },        /* DMUL */
20086     { reserved_block      , 0                   , 0   , 32,
20087        0xfc0001ff, 0xc0000020, 0                      , 0,
20088        0x0                 },        /* POOL32S_0~*(4) */
20089     { reserved_block      , 0                   , 0   , 32,
20090        0xfc0001ff, 0xc0000028, 0                      , 0,
20091        0x0                 },        /* POOL32S_0~*(5) */
20092     { reserved_block      , 0                   , 0   , 32,
20093        0xfc0001ff, 0xc0000030, 0                      , 0,
20094        0x0                 },        /* POOL32S_0~*(6) */
20095     { reserved_block      , 0                   , 0   , 32,
20096        0xfc0001ff, 0xc0000038, 0                      , 0,
20097        0x0                 },        /* POOL32S_0~*(7) */
20098     { reserved_block      , 0                   , 0   , 32,
20099        0xfc0001ff, 0xc0000040, 0                      , 0,
20100        0x0                 },        /* POOL32S_0~*(8) */
20101     { reserved_block      , 0                   , 0   , 32,
20102        0xfc0001ff, 0xc0000048, 0                      , 0,
20103        0x0                 },        /* POOL32S_0~*(9) */
20104     { instruction         , 0                   , 0   , 32,
20105        0xfc0001ff, 0xc0000050, &DSRLV            , 0,
20106        MIPS64_             },        /* DSRLV */
20107     { instruction         , 0                   , 0   , 32,
20108        0xfc0001ff, 0xc0000058, &DMUH             , 0,
20109        MIPS64_             },        /* DMUH */
20110     { reserved_block      , 0                   , 0   , 32,
20111        0xfc0001ff, 0xc0000060, 0                      , 0,
20112        0x0                 },        /* POOL32S_0~*(12) */
20113     { reserved_block      , 0                   , 0   , 32,
20114        0xfc0001ff, 0xc0000068, 0                      , 0,
20115        0x0                 },        /* POOL32S_0~*(13) */
20116     { reserved_block      , 0                   , 0   , 32,
20117        0xfc0001ff, 0xc0000070, 0                      , 0,
20118        0x0                 },        /* POOL32S_0~*(14) */
20119     { reserved_block      , 0                   , 0   , 32,
20120        0xfc0001ff, 0xc0000078, 0                      , 0,
20121        0x0                 },        /* POOL32S_0~*(15) */
20122     { reserved_block      , 0                   , 0   , 32,
20123        0xfc0001ff, 0xc0000080, 0                      , 0,
20124        0x0                 },        /* POOL32S_0~*(16) */
20125     { reserved_block      , 0                   , 0   , 32,
20126        0xfc0001ff, 0xc0000088, 0                      , 0,
20127        0x0                 },        /* POOL32S_0~*(17) */
20128     { instruction         , 0                   , 0   , 32,
20129        0xfc0001ff, 0xc0000090, &DSRAV            , 0,
20130        MIPS64_             },        /* DSRAV */
20131     { instruction         , 0                   , 0   , 32,
20132        0xfc0001ff, 0xc0000098, &DMULU            , 0,
20133        MIPS64_             },        /* DMULU */
20134     { reserved_block      , 0                   , 0   , 32,
20135        0xfc0001ff, 0xc00000a0, 0                      , 0,
20136        0x0                 },        /* POOL32S_0~*(20) */
20137     { reserved_block      , 0                   , 0   , 32,
20138        0xfc0001ff, 0xc00000a8, 0                      , 0,
20139        0x0                 },        /* POOL32S_0~*(21) */
20140     { reserved_block      , 0                   , 0   , 32,
20141        0xfc0001ff, 0xc00000b0, 0                      , 0,
20142        0x0                 },        /* POOL32S_0~*(22) */
20143     { reserved_block      , 0                   , 0   , 32,
20144        0xfc0001ff, 0xc00000b8, 0                      , 0,
20145        0x0                 },        /* POOL32S_0~*(23) */
20146     { reserved_block      , 0                   , 0   , 32,
20147        0xfc0001ff, 0xc00000c0, 0                      , 0,
20148        0x0                 },        /* POOL32S_0~*(24) */
20149     { reserved_block      , 0                   , 0   , 32,
20150        0xfc0001ff, 0xc00000c8, 0                      , 0,
20151        0x0                 },        /* POOL32S_0~*(25) */
20152     { instruction         , 0                   , 0   , 32,
20153        0xfc0001ff, 0xc00000d0, &DROTRV           , 0,
20154        MIPS64_             },        /* DROTRV */
20155     { instruction         , 0                   , 0   , 32,
20156        0xfc0001ff, 0xc00000d8, &DMUHU            , 0,
20157        MIPS64_             },        /* DMUHU */
20158     { reserved_block      , 0                   , 0   , 32,
20159        0xfc0001ff, 0xc00000e0, 0                      , 0,
20160        0x0                 },        /* POOL32S_0~*(28) */
20161     { reserved_block      , 0                   , 0   , 32,
20162        0xfc0001ff, 0xc00000e8, 0                      , 0,
20163        0x0                 },        /* POOL32S_0~*(29) */
20164     { reserved_block      , 0                   , 0   , 32,
20165        0xfc0001ff, 0xc00000f0, 0                      , 0,
20166        0x0                 },        /* POOL32S_0~*(30) */
20167     { reserved_block      , 0                   , 0   , 32,
20168        0xfc0001ff, 0xc00000f8, 0                      , 0,
20169        0x0                 },        /* POOL32S_0~*(31) */
20170     { reserved_block      , 0                   , 0   , 32,
20171        0xfc0001ff, 0xc0000100, 0                      , 0,
20172        0x0                 },        /* POOL32S_0~*(32) */
20173     { reserved_block      , 0                   , 0   , 32,
20174        0xfc0001ff, 0xc0000108, 0                      , 0,
20175        0x0                 },        /* POOL32S_0~*(33) */
20176     { instruction         , 0                   , 0   , 32,
20177        0xfc0001ff, 0xc0000110, &DADD             , 0,
20178        MIPS64_             },        /* DADD */
20179     { instruction         , 0                   , 0   , 32,
20180        0xfc0001ff, 0xc0000118, &DDIV             , 0,
20181        MIPS64_             },        /* DDIV */
20182     { reserved_block      , 0                   , 0   , 32,
20183        0xfc0001ff, 0xc0000120, 0                      , 0,
20184        0x0                 },        /* POOL32S_0~*(36) */
20185     { reserved_block      , 0                   , 0   , 32,
20186        0xfc0001ff, 0xc0000128, 0                      , 0,
20187        0x0                 },        /* POOL32S_0~*(37) */
20188     { reserved_block      , 0                   , 0   , 32,
20189        0xfc0001ff, 0xc0000130, 0                      , 0,
20190        0x0                 },        /* POOL32S_0~*(38) */
20191     { reserved_block      , 0                   , 0   , 32,
20192        0xfc0001ff, 0xc0000138, 0                      , 0,
20193        0x0                 },        /* POOL32S_0~*(39) */
20194     { reserved_block      , 0                   , 0   , 32,
20195        0xfc0001ff, 0xc0000140, 0                      , 0,
20196        0x0                 },        /* POOL32S_0~*(40) */
20197     { reserved_block      , 0                   , 0   , 32,
20198        0xfc0001ff, 0xc0000148, 0                      , 0,
20199        0x0                 },        /* POOL32S_0~*(41) */
20200     { instruction         , 0                   , 0   , 32,
20201        0xfc0001ff, 0xc0000150, &DADDU            , 0,
20202        MIPS64_             },        /* DADDU */
20203     { instruction         , 0                   , 0   , 32,
20204        0xfc0001ff, 0xc0000158, &DMOD             , 0,
20205        MIPS64_             },        /* DMOD */
20206     { reserved_block      , 0                   , 0   , 32,
20207        0xfc0001ff, 0xc0000160, 0                      , 0,
20208        0x0                 },        /* POOL32S_0~*(44) */
20209     { reserved_block      , 0                   , 0   , 32,
20210        0xfc0001ff, 0xc0000168, 0                      , 0,
20211        0x0                 },        /* POOL32S_0~*(45) */
20212     { reserved_block      , 0                   , 0   , 32,
20213        0xfc0001ff, 0xc0000170, 0                      , 0,
20214        0x0                 },        /* POOL32S_0~*(46) */
20215     { reserved_block      , 0                   , 0   , 32,
20216        0xfc0001ff, 0xc0000178, 0                      , 0,
20217        0x0                 },        /* POOL32S_0~*(47) */
20218     { reserved_block      , 0                   , 0   , 32,
20219        0xfc0001ff, 0xc0000180, 0                      , 0,
20220        0x0                 },        /* POOL32S_0~*(48) */
20221     { reserved_block      , 0                   , 0   , 32,
20222        0xfc0001ff, 0xc0000188, 0                      , 0,
20223        0x0                 },        /* POOL32S_0~*(49) */
20224     { instruction         , 0                   , 0   , 32,
20225        0xfc0001ff, 0xc0000190, &DSUB             , 0,
20226        MIPS64_             },        /* DSUB */
20227     { instruction         , 0                   , 0   , 32,
20228        0xfc0001ff, 0xc0000198, &DDIVU            , 0,
20229        MIPS64_             },        /* DDIVU */
20230     { reserved_block      , 0                   , 0   , 32,
20231        0xfc0001ff, 0xc00001a0, 0                      , 0,
20232        0x0                 },        /* POOL32S_0~*(52) */
20233     { reserved_block      , 0                   , 0   , 32,
20234        0xfc0001ff, 0xc00001a8, 0                      , 0,
20235        0x0                 },        /* POOL32S_0~*(53) */
20236     { reserved_block      , 0                   , 0   , 32,
20237        0xfc0001ff, 0xc00001b0, 0                      , 0,
20238        0x0                 },        /* POOL32S_0~*(54) */
20239     { reserved_block      , 0                   , 0   , 32,
20240        0xfc0001ff, 0xc00001b8, 0                      , 0,
20241        0x0                 },        /* POOL32S_0~*(55) */
20242     { reserved_block      , 0                   , 0   , 32,
20243        0xfc0001ff, 0xc00001c0, 0                      , 0,
20244        0x0                 },        /* POOL32S_0~*(56) */
20245     { reserved_block      , 0                   , 0   , 32,
20246        0xfc0001ff, 0xc00001c8, 0                      , 0,
20247        0x0                 },        /* POOL32S_0~*(57) */
20248     { instruction         , 0                   , 0   , 32,
20249        0xfc0001ff, 0xc00001d0, &DSUBU            , 0,
20250        MIPS64_             },        /* DSUBU */
20251     { instruction         , 0                   , 0   , 32,
20252        0xfc0001ff, 0xc00001d8, &DMODU            , 0,
20253        MIPS64_             },        /* DMODU */
20254     { reserved_block      , 0                   , 0   , 32,
20255        0xfc0001ff, 0xc00001e0, 0                      , 0,
20256        0x0                 },        /* POOL32S_0~*(60) */
20257     { reserved_block      , 0                   , 0   , 32,
20258        0xfc0001ff, 0xc00001e8, 0                      , 0,
20259        0x0                 },        /* POOL32S_0~*(61) */
20260     { reserved_block      , 0                   , 0   , 32,
20261        0xfc0001ff, 0xc00001f0, 0                      , 0,
20262        0x0                 },        /* POOL32S_0~*(62) */
20263     { reserved_block      , 0                   , 0   , 32,
20264        0xfc0001ff, 0xc00001f8, 0                      , 0,
20265        0x0                 },        /* POOL32S_0~*(63) */
20266 };
20267 
20268 
20269 static const Pool POOL32Sxf_4[128] = {
20270     { reserved_block      , 0                   , 0   , 32,
20271        0xfc00ffff, 0xc000013c, 0                      , 0,
20272        0x0                 },        /* POOL32Sxf_4~*(0) */
20273     { reserved_block      , 0                   , 0   , 32,
20274        0xfc00ffff, 0xc000033c, 0                      , 0,
20275        0x0                 },        /* POOL32Sxf_4~*(1) */
20276     { reserved_block      , 0                   , 0   , 32,
20277        0xfc00ffff, 0xc000053c, 0                      , 0,
20278        0x0                 },        /* POOL32Sxf_4~*(2) */
20279     { reserved_block      , 0                   , 0   , 32,
20280        0xfc00ffff, 0xc000073c, 0                      , 0,
20281        0x0                 },        /* POOL32Sxf_4~*(3) */
20282     { reserved_block      , 0                   , 0   , 32,
20283        0xfc00ffff, 0xc000093c, 0                      , 0,
20284        0x0                 },        /* POOL32Sxf_4~*(4) */
20285     { reserved_block      , 0                   , 0   , 32,
20286        0xfc00ffff, 0xc0000b3c, 0                      , 0,
20287        0x0                 },        /* POOL32Sxf_4~*(5) */
20288     { reserved_block      , 0                   , 0   , 32,
20289        0xfc00ffff, 0xc0000d3c, 0                      , 0,
20290        0x0                 },        /* POOL32Sxf_4~*(6) */
20291     { reserved_block      , 0                   , 0   , 32,
20292        0xfc00ffff, 0xc0000f3c, 0                      , 0,
20293        0x0                 },        /* POOL32Sxf_4~*(7) */
20294     { reserved_block      , 0                   , 0   , 32,
20295        0xfc00ffff, 0xc000113c, 0                      , 0,
20296        0x0                 },        /* POOL32Sxf_4~*(8) */
20297     { reserved_block      , 0                   , 0   , 32,
20298        0xfc00ffff, 0xc000133c, 0                      , 0,
20299        0x0                 },        /* POOL32Sxf_4~*(9) */
20300     { reserved_block      , 0                   , 0   , 32,
20301        0xfc00ffff, 0xc000153c, 0                      , 0,
20302        0x0                 },        /* POOL32Sxf_4~*(10) */
20303     { reserved_block      , 0                   , 0   , 32,
20304        0xfc00ffff, 0xc000173c, 0                      , 0,
20305        0x0                 },        /* POOL32Sxf_4~*(11) */
20306     { reserved_block      , 0                   , 0   , 32,
20307        0xfc00ffff, 0xc000193c, 0                      , 0,
20308        0x0                 },        /* POOL32Sxf_4~*(12) */
20309     { reserved_block      , 0                   , 0   , 32,
20310        0xfc00ffff, 0xc0001b3c, 0                      , 0,
20311        0x0                 },        /* POOL32Sxf_4~*(13) */
20312     { reserved_block      , 0                   , 0   , 32,
20313        0xfc00ffff, 0xc0001d3c, 0                      , 0,
20314        0x0                 },        /* POOL32Sxf_4~*(14) */
20315     { reserved_block      , 0                   , 0   , 32,
20316        0xfc00ffff, 0xc0001f3c, 0                      , 0,
20317        0x0                 },        /* POOL32Sxf_4~*(15) */
20318     { reserved_block      , 0                   , 0   , 32,
20319        0xfc00ffff, 0xc000213c, 0                      , 0,
20320        0x0                 },        /* POOL32Sxf_4~*(16) */
20321     { reserved_block      , 0                   , 0   , 32,
20322        0xfc00ffff, 0xc000233c, 0                      , 0,
20323        0x0                 },        /* POOL32Sxf_4~*(17) */
20324     { reserved_block      , 0                   , 0   , 32,
20325        0xfc00ffff, 0xc000253c, 0                      , 0,
20326        0x0                 },        /* POOL32Sxf_4~*(18) */
20327     { reserved_block      , 0                   , 0   , 32,
20328        0xfc00ffff, 0xc000273c, 0                      , 0,
20329        0x0                 },        /* POOL32Sxf_4~*(19) */
20330     { reserved_block      , 0                   , 0   , 32,
20331        0xfc00ffff, 0xc000293c, 0                      , 0,
20332        0x0                 },        /* POOL32Sxf_4~*(20) */
20333     { reserved_block      , 0                   , 0   , 32,
20334        0xfc00ffff, 0xc0002b3c, 0                      , 0,
20335        0x0                 },        /* POOL32Sxf_4~*(21) */
20336     { reserved_block      , 0                   , 0   , 32,
20337        0xfc00ffff, 0xc0002d3c, 0                      , 0,
20338        0x0                 },        /* POOL32Sxf_4~*(22) */
20339     { reserved_block      , 0                   , 0   , 32,
20340        0xfc00ffff, 0xc0002f3c, 0                      , 0,
20341        0x0                 },        /* POOL32Sxf_4~*(23) */
20342     { reserved_block      , 0                   , 0   , 32,
20343        0xfc00ffff, 0xc000313c, 0                      , 0,
20344        0x0                 },        /* POOL32Sxf_4~*(24) */
20345     { reserved_block      , 0                   , 0   , 32,
20346        0xfc00ffff, 0xc000333c, 0                      , 0,
20347        0x0                 },        /* POOL32Sxf_4~*(25) */
20348     { reserved_block      , 0                   , 0   , 32,
20349        0xfc00ffff, 0xc000353c, 0                      , 0,
20350        0x0                 },        /* POOL32Sxf_4~*(26) */
20351     { reserved_block      , 0                   , 0   , 32,
20352        0xfc00ffff, 0xc000373c, 0                      , 0,
20353        0x0                 },        /* POOL32Sxf_4~*(27) */
20354     { reserved_block      , 0                   , 0   , 32,
20355        0xfc00ffff, 0xc000393c, 0                      , 0,
20356        0x0                 },        /* POOL32Sxf_4~*(28) */
20357     { reserved_block      , 0                   , 0   , 32,
20358        0xfc00ffff, 0xc0003b3c, 0                      , 0,
20359        0x0                 },        /* POOL32Sxf_4~*(29) */
20360     { reserved_block      , 0                   , 0   , 32,
20361        0xfc00ffff, 0xc0003d3c, 0                      , 0,
20362        0x0                 },        /* POOL32Sxf_4~*(30) */
20363     { reserved_block      , 0                   , 0   , 32,
20364        0xfc00ffff, 0xc0003f3c, 0                      , 0,
20365        0x0                 },        /* POOL32Sxf_4~*(31) */
20366     { reserved_block      , 0                   , 0   , 32,
20367        0xfc00ffff, 0xc000413c, 0                      , 0,
20368        0x0                 },        /* POOL32Sxf_4~*(32) */
20369     { reserved_block      , 0                   , 0   , 32,
20370        0xfc00ffff, 0xc000433c, 0                      , 0,
20371        0x0                 },        /* POOL32Sxf_4~*(33) */
20372     { reserved_block      , 0                   , 0   , 32,
20373        0xfc00ffff, 0xc000453c, 0                      , 0,
20374        0x0                 },        /* POOL32Sxf_4~*(34) */
20375     { reserved_block      , 0                   , 0   , 32,
20376        0xfc00ffff, 0xc000473c, 0                      , 0,
20377        0x0                 },        /* POOL32Sxf_4~*(35) */
20378     { reserved_block      , 0                   , 0   , 32,
20379        0xfc00ffff, 0xc000493c, 0                      , 0,
20380        0x0                 },        /* POOL32Sxf_4~*(36) */
20381     { instruction         , 0                   , 0   , 32,
20382        0xfc00ffff, 0xc0004b3c, &DCLO             , 0,
20383        MIPS64_             },        /* DCLO */
20384     { reserved_block      , 0                   , 0   , 32,
20385        0xfc00ffff, 0xc0004d3c, 0                      , 0,
20386        0x0                 },        /* POOL32Sxf_4~*(38) */
20387     { reserved_block      , 0                   , 0   , 32,
20388        0xfc00ffff, 0xc0004f3c, 0                      , 0,
20389        0x0                 },        /* POOL32Sxf_4~*(39) */
20390     { reserved_block      , 0                   , 0   , 32,
20391        0xfc00ffff, 0xc000513c, 0                      , 0,
20392        0x0                 },        /* POOL32Sxf_4~*(40) */
20393     { reserved_block      , 0                   , 0   , 32,
20394        0xfc00ffff, 0xc000533c, 0                      , 0,
20395        0x0                 },        /* POOL32Sxf_4~*(41) */
20396     { reserved_block      , 0                   , 0   , 32,
20397        0xfc00ffff, 0xc000553c, 0                      , 0,
20398        0x0                 },        /* POOL32Sxf_4~*(42) */
20399     { reserved_block      , 0                   , 0   , 32,
20400        0xfc00ffff, 0xc000573c, 0                      , 0,
20401        0x0                 },        /* POOL32Sxf_4~*(43) */
20402     { reserved_block      , 0                   , 0   , 32,
20403        0xfc00ffff, 0xc000593c, 0                      , 0,
20404        0x0                 },        /* POOL32Sxf_4~*(44) */
20405     { instruction         , 0                   , 0   , 32,
20406        0xfc00ffff, 0xc0005b3c, &DCLZ             , 0,
20407        MIPS64_             },        /* DCLZ */
20408     { reserved_block      , 0                   , 0   , 32,
20409        0xfc00ffff, 0xc0005d3c, 0                      , 0,
20410        0x0                 },        /* POOL32Sxf_4~*(46) */
20411     { reserved_block      , 0                   , 0   , 32,
20412        0xfc00ffff, 0xc0005f3c, 0                      , 0,
20413        0x0                 },        /* POOL32Sxf_4~*(47) */
20414     { reserved_block      , 0                   , 0   , 32,
20415        0xfc00ffff, 0xc000613c, 0                      , 0,
20416        0x0                 },        /* POOL32Sxf_4~*(48) */
20417     { reserved_block      , 0                   , 0   , 32,
20418        0xfc00ffff, 0xc000633c, 0                      , 0,
20419        0x0                 },        /* POOL32Sxf_4~*(49) */
20420     { reserved_block      , 0                   , 0   , 32,
20421        0xfc00ffff, 0xc000653c, 0                      , 0,
20422        0x0                 },        /* POOL32Sxf_4~*(50) */
20423     { reserved_block      , 0                   , 0   , 32,
20424        0xfc00ffff, 0xc000673c, 0                      , 0,
20425        0x0                 },        /* POOL32Sxf_4~*(51) */
20426     { reserved_block      , 0                   , 0   , 32,
20427        0xfc00ffff, 0xc000693c, 0                      , 0,
20428        0x0                 },        /* POOL32Sxf_4~*(52) */
20429     { reserved_block      , 0                   , 0   , 32,
20430        0xfc00ffff, 0xc0006b3c, 0                      , 0,
20431        0x0                 },        /* POOL32Sxf_4~*(53) */
20432     { reserved_block      , 0                   , 0   , 32,
20433        0xfc00ffff, 0xc0006d3c, 0                      , 0,
20434        0x0                 },        /* POOL32Sxf_4~*(54) */
20435     { reserved_block      , 0                   , 0   , 32,
20436        0xfc00ffff, 0xc0006f3c, 0                      , 0,
20437        0x0                 },        /* POOL32Sxf_4~*(55) */
20438     { reserved_block      , 0                   , 0   , 32,
20439        0xfc00ffff, 0xc000713c, 0                      , 0,
20440        0x0                 },        /* POOL32Sxf_4~*(56) */
20441     { reserved_block      , 0                   , 0   , 32,
20442        0xfc00ffff, 0xc000733c, 0                      , 0,
20443        0x0                 },        /* POOL32Sxf_4~*(57) */
20444     { reserved_block      , 0                   , 0   , 32,
20445        0xfc00ffff, 0xc000753c, 0                      , 0,
20446        0x0                 },        /* POOL32Sxf_4~*(58) */
20447     { reserved_block      , 0                   , 0   , 32,
20448        0xfc00ffff, 0xc000773c, 0                      , 0,
20449        0x0                 },        /* POOL32Sxf_4~*(59) */
20450     { reserved_block      , 0                   , 0   , 32,
20451        0xfc00ffff, 0xc000793c, 0                      , 0,
20452        0x0                 },        /* POOL32Sxf_4~*(60) */
20453     { reserved_block      , 0                   , 0   , 32,
20454        0xfc00ffff, 0xc0007b3c, 0                      , 0,
20455        0x0                 },        /* POOL32Sxf_4~*(61) */
20456     { reserved_block      , 0                   , 0   , 32,
20457        0xfc00ffff, 0xc0007d3c, 0                      , 0,
20458        0x0                 },        /* POOL32Sxf_4~*(62) */
20459     { reserved_block      , 0                   , 0   , 32,
20460        0xfc00ffff, 0xc0007f3c, 0                      , 0,
20461        0x0                 },        /* POOL32Sxf_4~*(63) */
20462     { reserved_block      , 0                   , 0   , 32,
20463        0xfc00ffff, 0xc000813c, 0                      , 0,
20464        0x0                 },        /* POOL32Sxf_4~*(64) */
20465     { reserved_block      , 0                   , 0   , 32,
20466        0xfc00ffff, 0xc000833c, 0                      , 0,
20467        0x0                 },        /* POOL32Sxf_4~*(65) */
20468     { reserved_block      , 0                   , 0   , 32,
20469        0xfc00ffff, 0xc000853c, 0                      , 0,
20470        0x0                 },        /* POOL32Sxf_4~*(66) */
20471     { reserved_block      , 0                   , 0   , 32,
20472        0xfc00ffff, 0xc000873c, 0                      , 0,
20473        0x0                 },        /* POOL32Sxf_4~*(67) */
20474     { reserved_block      , 0                   , 0   , 32,
20475        0xfc00ffff, 0xc000893c, 0                      , 0,
20476        0x0                 },        /* POOL32Sxf_4~*(68) */
20477     { reserved_block      , 0                   , 0   , 32,
20478        0xfc00ffff, 0xc0008b3c, 0                      , 0,
20479        0x0                 },        /* POOL32Sxf_4~*(69) */
20480     { reserved_block      , 0                   , 0   , 32,
20481        0xfc00ffff, 0xc0008d3c, 0                      , 0,
20482        0x0                 },        /* POOL32Sxf_4~*(70) */
20483     { reserved_block      , 0                   , 0   , 32,
20484        0xfc00ffff, 0xc0008f3c, 0                      , 0,
20485        0x0                 },        /* POOL32Sxf_4~*(71) */
20486     { reserved_block      , 0                   , 0   , 32,
20487        0xfc00ffff, 0xc000913c, 0                      , 0,
20488        0x0                 },        /* POOL32Sxf_4~*(72) */
20489     { reserved_block      , 0                   , 0   , 32,
20490        0xfc00ffff, 0xc000933c, 0                      , 0,
20491        0x0                 },        /* POOL32Sxf_4~*(73) */
20492     { reserved_block      , 0                   , 0   , 32,
20493        0xfc00ffff, 0xc000953c, 0                      , 0,
20494        0x0                 },        /* POOL32Sxf_4~*(74) */
20495     { reserved_block      , 0                   , 0   , 32,
20496        0xfc00ffff, 0xc000973c, 0                      , 0,
20497        0x0                 },        /* POOL32Sxf_4~*(75) */
20498     { reserved_block      , 0                   , 0   , 32,
20499        0xfc00ffff, 0xc000993c, 0                      , 0,
20500        0x0                 },        /* POOL32Sxf_4~*(76) */
20501     { reserved_block      , 0                   , 0   , 32,
20502        0xfc00ffff, 0xc0009b3c, 0                      , 0,
20503        0x0                 },        /* POOL32Sxf_4~*(77) */
20504     { reserved_block      , 0                   , 0   , 32,
20505        0xfc00ffff, 0xc0009d3c, 0                      , 0,
20506        0x0                 },        /* POOL32Sxf_4~*(78) */
20507     { reserved_block      , 0                   , 0   , 32,
20508        0xfc00ffff, 0xc0009f3c, 0                      , 0,
20509        0x0                 },        /* POOL32Sxf_4~*(79) */
20510     { reserved_block      , 0                   , 0   , 32,
20511        0xfc00ffff, 0xc000a13c, 0                      , 0,
20512        0x0                 },        /* POOL32Sxf_4~*(80) */
20513     { reserved_block      , 0                   , 0   , 32,
20514        0xfc00ffff, 0xc000a33c, 0                      , 0,
20515        0x0                 },        /* POOL32Sxf_4~*(81) */
20516     { reserved_block      , 0                   , 0   , 32,
20517        0xfc00ffff, 0xc000a53c, 0                      , 0,
20518        0x0                 },        /* POOL32Sxf_4~*(82) */
20519     { reserved_block      , 0                   , 0   , 32,
20520        0xfc00ffff, 0xc000a73c, 0                      , 0,
20521        0x0                 },        /* POOL32Sxf_4~*(83) */
20522     { reserved_block      , 0                   , 0   , 32,
20523        0xfc00ffff, 0xc000a93c, 0                      , 0,
20524        0x0                 },        /* POOL32Sxf_4~*(84) */
20525     { reserved_block      , 0                   , 0   , 32,
20526        0xfc00ffff, 0xc000ab3c, 0                      , 0,
20527        0x0                 },        /* POOL32Sxf_4~*(85) */
20528     { reserved_block      , 0                   , 0   , 32,
20529        0xfc00ffff, 0xc000ad3c, 0                      , 0,
20530        0x0                 },        /* POOL32Sxf_4~*(86) */
20531     { reserved_block      , 0                   , 0   , 32,
20532        0xfc00ffff, 0xc000af3c, 0                      , 0,
20533        0x0                 },        /* POOL32Sxf_4~*(87) */
20534     { reserved_block      , 0                   , 0   , 32,
20535        0xfc00ffff, 0xc000b13c, 0                      , 0,
20536        0x0                 },        /* POOL32Sxf_4~*(88) */
20537     { reserved_block      , 0                   , 0   , 32,
20538        0xfc00ffff, 0xc000b33c, 0                      , 0,
20539        0x0                 },        /* POOL32Sxf_4~*(89) */
20540     { reserved_block      , 0                   , 0   , 32,
20541        0xfc00ffff, 0xc000b53c, 0                      , 0,
20542        0x0                 },        /* POOL32Sxf_4~*(90) */
20543     { reserved_block      , 0                   , 0   , 32,
20544        0xfc00ffff, 0xc000b73c, 0                      , 0,
20545        0x0                 },        /* POOL32Sxf_4~*(91) */
20546     { reserved_block      , 0                   , 0   , 32,
20547        0xfc00ffff, 0xc000b93c, 0                      , 0,
20548        0x0                 },        /* POOL32Sxf_4~*(92) */
20549     { reserved_block      , 0                   , 0   , 32,
20550        0xfc00ffff, 0xc000bb3c, 0                      , 0,
20551        0x0                 },        /* POOL32Sxf_4~*(93) */
20552     { reserved_block      , 0                   , 0   , 32,
20553        0xfc00ffff, 0xc000bd3c, 0                      , 0,
20554        0x0                 },        /* POOL32Sxf_4~*(94) */
20555     { reserved_block      , 0                   , 0   , 32,
20556        0xfc00ffff, 0xc000bf3c, 0                      , 0,
20557        0x0                 },        /* POOL32Sxf_4~*(95) */
20558     { reserved_block      , 0                   , 0   , 32,
20559        0xfc00ffff, 0xc000c13c, 0                      , 0,
20560        0x0                 },        /* POOL32Sxf_4~*(96) */
20561     { reserved_block      , 0                   , 0   , 32,
20562        0xfc00ffff, 0xc000c33c, 0                      , 0,
20563        0x0                 },        /* POOL32Sxf_4~*(97) */
20564     { reserved_block      , 0                   , 0   , 32,
20565        0xfc00ffff, 0xc000c53c, 0                      , 0,
20566        0x0                 },        /* POOL32Sxf_4~*(98) */
20567     { reserved_block      , 0                   , 0   , 32,
20568        0xfc00ffff, 0xc000c73c, 0                      , 0,
20569        0x0                 },        /* POOL32Sxf_4~*(99) */
20570     { reserved_block      , 0                   , 0   , 32,
20571        0xfc00ffff, 0xc000c93c, 0                      , 0,
20572        0x0                 },        /* POOL32Sxf_4~*(100) */
20573     { reserved_block      , 0                   , 0   , 32,
20574        0xfc00ffff, 0xc000cb3c, 0                      , 0,
20575        0x0                 },        /* POOL32Sxf_4~*(101) */
20576     { reserved_block      , 0                   , 0   , 32,
20577        0xfc00ffff, 0xc000cd3c, 0                      , 0,
20578        0x0                 },        /* POOL32Sxf_4~*(102) */
20579     { reserved_block      , 0                   , 0   , 32,
20580        0xfc00ffff, 0xc000cf3c, 0                      , 0,
20581        0x0                 },        /* POOL32Sxf_4~*(103) */
20582     { reserved_block      , 0                   , 0   , 32,
20583        0xfc00ffff, 0xc000d13c, 0                      , 0,
20584        0x0                 },        /* POOL32Sxf_4~*(104) */
20585     { reserved_block      , 0                   , 0   , 32,
20586        0xfc00ffff, 0xc000d33c, 0                      , 0,
20587        0x0                 },        /* POOL32Sxf_4~*(105) */
20588     { reserved_block      , 0                   , 0   , 32,
20589        0xfc00ffff, 0xc000d53c, 0                      , 0,
20590        0x0                 },        /* POOL32Sxf_4~*(106) */
20591     { reserved_block      , 0                   , 0   , 32,
20592        0xfc00ffff, 0xc000d73c, 0                      , 0,
20593        0x0                 },        /* POOL32Sxf_4~*(107) */
20594     { reserved_block      , 0                   , 0   , 32,
20595        0xfc00ffff, 0xc000d93c, 0                      , 0,
20596        0x0                 },        /* POOL32Sxf_4~*(108) */
20597     { reserved_block      , 0                   , 0   , 32,
20598        0xfc00ffff, 0xc000db3c, 0                      , 0,
20599        0x0                 },        /* POOL32Sxf_4~*(109) */
20600     { reserved_block      , 0                   , 0   , 32,
20601        0xfc00ffff, 0xc000dd3c, 0                      , 0,
20602        0x0                 },        /* POOL32Sxf_4~*(110) */
20603     { reserved_block      , 0                   , 0   , 32,
20604        0xfc00ffff, 0xc000df3c, 0                      , 0,
20605        0x0                 },        /* POOL32Sxf_4~*(111) */
20606     { reserved_block      , 0                   , 0   , 32,
20607        0xfc00ffff, 0xc000e13c, 0                      , 0,
20608        0x0                 },        /* POOL32Sxf_4~*(112) */
20609     { reserved_block      , 0                   , 0   , 32,
20610        0xfc00ffff, 0xc000e33c, 0                      , 0,
20611        0x0                 },        /* POOL32Sxf_4~*(113) */
20612     { reserved_block      , 0                   , 0   , 32,
20613        0xfc00ffff, 0xc000e53c, 0                      , 0,
20614        0x0                 },        /* POOL32Sxf_4~*(114) */
20615     { reserved_block      , 0                   , 0   , 32,
20616        0xfc00ffff, 0xc000e73c, 0                      , 0,
20617        0x0                 },        /* POOL32Sxf_4~*(115) */
20618     { reserved_block      , 0                   , 0   , 32,
20619        0xfc00ffff, 0xc000e93c, 0                      , 0,
20620        0x0                 },        /* POOL32Sxf_4~*(116) */
20621     { reserved_block      , 0                   , 0   , 32,
20622        0xfc00ffff, 0xc000eb3c, 0                      , 0,
20623        0x0                 },        /* POOL32Sxf_4~*(117) */
20624     { reserved_block      , 0                   , 0   , 32,
20625        0xfc00ffff, 0xc000ed3c, 0                      , 0,
20626        0x0                 },        /* POOL32Sxf_4~*(118) */
20627     { reserved_block      , 0                   , 0   , 32,
20628        0xfc00ffff, 0xc000ef3c, 0                      , 0,
20629        0x0                 },        /* POOL32Sxf_4~*(119) */
20630     { reserved_block      , 0                   , 0   , 32,
20631        0xfc00ffff, 0xc000f13c, 0                      , 0,
20632        0x0                 },        /* POOL32Sxf_4~*(120) */
20633     { reserved_block      , 0                   , 0   , 32,
20634        0xfc00ffff, 0xc000f33c, 0                      , 0,
20635        0x0                 },        /* POOL32Sxf_4~*(121) */
20636     { reserved_block      , 0                   , 0   , 32,
20637        0xfc00ffff, 0xc000f53c, 0                      , 0,
20638        0x0                 },        /* POOL32Sxf_4~*(122) */
20639     { reserved_block      , 0                   , 0   , 32,
20640        0xfc00ffff, 0xc000f73c, 0                      , 0,
20641        0x0                 },        /* POOL32Sxf_4~*(123) */
20642     { reserved_block      , 0                   , 0   , 32,
20643        0xfc00ffff, 0xc000f93c, 0                      , 0,
20644        0x0                 },        /* POOL32Sxf_4~*(124) */
20645     { reserved_block      , 0                   , 0   , 32,
20646        0xfc00ffff, 0xc000fb3c, 0                      , 0,
20647        0x0                 },        /* POOL32Sxf_4~*(125) */
20648     { reserved_block      , 0                   , 0   , 32,
20649        0xfc00ffff, 0xc000fd3c, 0                      , 0,
20650        0x0                 },        /* POOL32Sxf_4~*(126) */
20651     { reserved_block      , 0                   , 0   , 32,
20652        0xfc00ffff, 0xc000ff3c, 0                      , 0,
20653        0x0                 },        /* POOL32Sxf_4~*(127) */
20654 };
20655 
20656 
20657 static const Pool POOL32Sxf[8] = {
20658     { reserved_block      , 0                   , 0   , 32,
20659        0xfc0001ff, 0xc000003c, 0                      , 0,
20660        0x0                 },        /* POOL32Sxf~*(0) */
20661     { reserved_block      , 0                   , 0   , 32,
20662        0xfc0001ff, 0xc000007c, 0                      , 0,
20663        0x0                 },        /* POOL32Sxf~*(1) */
20664     { reserved_block      , 0                   , 0   , 32,
20665        0xfc0001ff, 0xc00000bc, 0                      , 0,
20666        0x0                 },        /* POOL32Sxf~*(2) */
20667     { reserved_block      , 0                   , 0   , 32,
20668        0xfc0001ff, 0xc00000fc, 0                      , 0,
20669        0x0                 },        /* POOL32Sxf~*(3) */
20670     { pool                , POOL32Sxf_4         , 128 , 32,
20671        0xfc0001ff, 0xc000013c, 0                      , 0,
20672        0x0                 },        /* POOL32Sxf_4 */
20673     { reserved_block      , 0                   , 0   , 32,
20674        0xfc0001ff, 0xc000017c, 0                      , 0,
20675        0x0                 },        /* POOL32Sxf~*(5) */
20676     { reserved_block      , 0                   , 0   , 32,
20677        0xfc0001ff, 0xc00001bc, 0                      , 0,
20678        0x0                 },        /* POOL32Sxf~*(6) */
20679     { reserved_block      , 0                   , 0   , 32,
20680        0xfc0001ff, 0xc00001fc, 0                      , 0,
20681        0x0                 },        /* POOL32Sxf~*(7) */
20682 };
20683 
20684 
20685 static const Pool POOL32S_4[8] = {
20686     { instruction         , 0                   , 0   , 32,
20687        0xfc00003f, 0xc0000004, &EXTD             , 0,
20688        MIPS64_             },        /* EXTD */
20689     { instruction         , 0                   , 0   , 32,
20690        0xfc00003f, 0xc000000c, &EXTD32           , 0,
20691        MIPS64_             },        /* EXTD32 */
20692     { reserved_block      , 0                   , 0   , 32,
20693        0xfc00003f, 0xc0000014, 0                      , 0,
20694        0x0                 },        /* POOL32S_4~*(2) */
20695     { reserved_block      , 0                   , 0   , 32,
20696        0xfc00003f, 0xc000001c, 0                      , 0,
20697        0x0                 },        /* POOL32S_4~*(3) */
20698     { reserved_block      , 0                   , 0   , 32,
20699        0xfc00003f, 0xc0000024, 0                      , 0,
20700        0x0                 },        /* POOL32S_4~*(4) */
20701     { reserved_block      , 0                   , 0   , 32,
20702        0xfc00003f, 0xc000002c, 0                      , 0,
20703        0x0                 },        /* POOL32S_4~*(5) */
20704     { reserved_block      , 0                   , 0   , 32,
20705        0xfc00003f, 0xc0000034, 0                      , 0,
20706        0x0                 },        /* POOL32S_4~*(6) */
20707     { pool                , POOL32Sxf           , 8   , 32,
20708        0xfc00003f, 0xc000003c, 0                      , 0,
20709        0x0                 },        /* POOL32Sxf */
20710 };
20711 
20712 
20713 static const Pool POOL32S[8] = {
20714     { pool                , POOL32S_0           , 64  , 32,
20715        0xfc000007, 0xc0000000, 0                      , 0,
20716        0x0                 },        /* POOL32S_0 */
20717     { reserved_block      , 0                   , 0   , 32,
20718        0xfc000007, 0xc0000001, 0                      , 0,
20719        0x0                 },        /* POOL32S~*(1) */
20720     { reserved_block      , 0                   , 0   , 32,
20721        0xfc000007, 0xc0000002, 0                      , 0,
20722        0x0                 },        /* POOL32S~*(2) */
20723     { reserved_block      , 0                   , 0   , 32,
20724        0xfc000007, 0xc0000003, 0                      , 0,
20725        0x0                 },        /* POOL32S~*(3) */
20726     { pool                , POOL32S_4           , 8   , 32,
20727        0xfc000007, 0xc0000004, 0                      , 0,
20728        0x0                 },        /* POOL32S_4 */
20729     { reserved_block      , 0                   , 0   , 32,
20730        0xfc000007, 0xc0000005, 0                      , 0,
20731        0x0                 },        /* POOL32S~*(5) */
20732     { reserved_block      , 0                   , 0   , 32,
20733        0xfc000007, 0xc0000006, 0                      , 0,
20734        0x0                 },        /* POOL32S~*(6) */
20735     { reserved_block      , 0                   , 0   , 32,
20736        0xfc000007, 0xc0000007, 0                      , 0,
20737        0x0                 },        /* POOL32S~*(7) */
20738 };
20739 
20740 
20741 static const Pool P_LUI[2] = {
20742     { instruction         , 0                   , 0   , 32,
20743        0xfc000002, 0xe0000000, &LUI              , 0,
20744        0x0                 },        /* LUI */
20745     { instruction         , 0                   , 0   , 32,
20746        0xfc000002, 0xe0000002, &ALUIPC           , 0,
20747        0x0                 },        /* ALUIPC */
20748 };
20749 
20750 
20751 static const Pool P_GP_LH[2] = {
20752     { instruction         , 0                   , 0   , 32,
20753        0xfc1c0001, 0x44100000, &LH_GP_           , 0,
20754        0x0                 },        /* LH[GP] */
20755     { instruction         , 0                   , 0   , 32,
20756        0xfc1c0001, 0x44100001, &LHU_GP_          , 0,
20757        0x0                 },        /* LHU[GP] */
20758 };
20759 
20760 
20761 static const Pool P_GP_SH[2] = {
20762     { instruction         , 0                   , 0   , 32,
20763        0xfc1c0001, 0x44140000, &SH_GP_           , 0,
20764        0x0                 },        /* SH[GP] */
20765     { reserved_block      , 0                   , 0   , 32,
20766        0xfc1c0001, 0x44140001, 0                      , 0,
20767        0x0                 },        /* P.GP.SH~*(1) */
20768 };
20769 
20770 
20771 static const Pool P_GP_CP1[4] = {
20772     { instruction         , 0                   , 0   , 32,
20773        0xfc1c0003, 0x44180000, &LWC1_GP_         , 0,
20774        CP1_                },        /* LWC1[GP] */
20775     { instruction         , 0                   , 0   , 32,
20776        0xfc1c0003, 0x44180001, &SWC1_GP_         , 0,
20777        CP1_                },        /* SWC1[GP] */
20778     { instruction         , 0                   , 0   , 32,
20779        0xfc1c0003, 0x44180002, &LDC1_GP_         , 0,
20780        CP1_                },        /* LDC1[GP] */
20781     { instruction         , 0                   , 0   , 32,
20782        0xfc1c0003, 0x44180003, &SDC1_GP_         , 0,
20783        CP1_                },        /* SDC1[GP] */
20784 };
20785 
20786 
20787 static const Pool P_GP_M64[4] = {
20788     { instruction         , 0                   , 0   , 32,
20789        0xfc1c0003, 0x441c0000, &LWU_GP_          , 0,
20790        MIPS64_             },        /* LWU[GP] */
20791     { reserved_block      , 0                   , 0   , 32,
20792        0xfc1c0003, 0x441c0001, 0                      , 0,
20793        0x0                 },        /* P.GP.M64~*(1) */
20794     { reserved_block      , 0                   , 0   , 32,
20795        0xfc1c0003, 0x441c0002, 0                      , 0,
20796        0x0                 },        /* P.GP.M64~*(2) */
20797     { reserved_block      , 0                   , 0   , 32,
20798        0xfc1c0003, 0x441c0003, 0                      , 0,
20799        0x0                 },        /* P.GP.M64~*(3) */
20800 };
20801 
20802 
20803 static const Pool P_GP_BH[8] = {
20804     { instruction         , 0                   , 0   , 32,
20805        0xfc1c0000, 0x44000000, &LB_GP_           , 0,
20806        0x0                 },        /* LB[GP] */
20807     { instruction         , 0                   , 0   , 32,
20808        0xfc1c0000, 0x44040000, &SB_GP_           , 0,
20809        0x0                 },        /* SB[GP] */
20810     { instruction         , 0                   , 0   , 32,
20811        0xfc1c0000, 0x44080000, &LBU_GP_          , 0,
20812        0x0                 },        /* LBU[GP] */
20813     { instruction         , 0                   , 0   , 32,
20814        0xfc1c0000, 0x440c0000, &ADDIU_GP_B_      , 0,
20815        0x0                 },        /* ADDIU[GP.B] */
20816     { pool                , P_GP_LH             , 2   , 32,
20817        0xfc1c0000, 0x44100000, 0                      , 0,
20818        0x0                 },        /* P.GP.LH */
20819     { pool                , P_GP_SH             , 2   , 32,
20820        0xfc1c0000, 0x44140000, 0                      , 0,
20821        0x0                 },        /* P.GP.SH */
20822     { pool                , P_GP_CP1            , 4   , 32,
20823        0xfc1c0000, 0x44180000, 0                      , 0,
20824        0x0                 },        /* P.GP.CP1 */
20825     { pool                , P_GP_M64            , 4   , 32,
20826        0xfc1c0000, 0x441c0000, 0                      , 0,
20827        0x0                 },        /* P.GP.M64 */
20828 };
20829 
20830 
20831 static const Pool P_LS_U12[16] = {
20832     { instruction         , 0                   , 0   , 32,
20833        0xfc00f000, 0x84000000, &LB_U12_          , 0,
20834        0x0                 },        /* LB[U12] */
20835     { instruction         , 0                   , 0   , 32,
20836        0xfc00f000, 0x84001000, &SB_U12_          , 0,
20837        0x0                 },        /* SB[U12] */
20838     { instruction         , 0                   , 0   , 32,
20839        0xfc00f000, 0x84002000, &LBU_U12_         , 0,
20840        0x0                 },        /* LBU[U12] */
20841     { instruction         , 0                   , 0   , 32,
20842        0xfc00f000, 0x84003000, &PREF_U12_        , 0,
20843        0x0                 },        /* PREF[U12] */
20844     { instruction         , 0                   , 0   , 32,
20845        0xfc00f000, 0x84004000, &LH_U12_          , 0,
20846        0x0                 },        /* LH[U12] */
20847     { instruction         , 0                   , 0   , 32,
20848        0xfc00f000, 0x84005000, &SH_U12_          , 0,
20849        0x0                 },        /* SH[U12] */
20850     { instruction         , 0                   , 0   , 32,
20851        0xfc00f000, 0x84006000, &LHU_U12_         , 0,
20852        0x0                 },        /* LHU[U12] */
20853     { instruction         , 0                   , 0   , 32,
20854        0xfc00f000, 0x84007000, &LWU_U12_         , 0,
20855        MIPS64_             },        /* LWU[U12] */
20856     { instruction         , 0                   , 0   , 32,
20857        0xfc00f000, 0x84008000, &LW_U12_          , 0,
20858        0x0                 },        /* LW[U12] */
20859     { instruction         , 0                   , 0   , 32,
20860        0xfc00f000, 0x84009000, &SW_U12_          , 0,
20861        0x0                 },        /* SW[U12] */
20862     { instruction         , 0                   , 0   , 32,
20863        0xfc00f000, 0x8400a000, &LWC1_U12_        , 0,
20864        CP1_                },        /* LWC1[U12] */
20865     { instruction         , 0                   , 0   , 32,
20866        0xfc00f000, 0x8400b000, &SWC1_U12_        , 0,
20867        CP1_                },        /* SWC1[U12] */
20868     { instruction         , 0                   , 0   , 32,
20869        0xfc00f000, 0x8400c000, &LD_U12_          , 0,
20870        MIPS64_             },        /* LD[U12] */
20871     { instruction         , 0                   , 0   , 32,
20872        0xfc00f000, 0x8400d000, &SD_U12_          , 0,
20873        MIPS64_             },        /* SD[U12] */
20874     { instruction         , 0                   , 0   , 32,
20875        0xfc00f000, 0x8400e000, &LDC1_U12_        , 0,
20876        CP1_                },        /* LDC1[U12] */
20877     { instruction         , 0                   , 0   , 32,
20878        0xfc00f000, 0x8400f000, &SDC1_U12_        , 0,
20879        CP1_                },        /* SDC1[U12] */
20880 };
20881 
20882 
20883 static const Pool P_PREF_S9_[2] = {
20884     { instruction         , 0                   , 0   , 32,
20885        0xffe07f00, 0xa7e01800, &SYNCI            , 0,
20886        0x0                 },        /* SYNCI */
20887     { instruction         , 0                   , 0   , 32,
20888        0xfc007f00, 0xa4001800, &PREF_S9_         , &PREF_S9__cond    ,
20889        0x0                 },        /* PREF[S9] */
20890 };
20891 
20892 
20893 static const Pool P_LS_S0[16] = {
20894     { instruction         , 0                   , 0   , 32,
20895        0xfc007f00, 0xa4000000, &LB_S9_           , 0,
20896        0x0                 },        /* LB[S9] */
20897     { instruction         , 0                   , 0   , 32,
20898        0xfc007f00, 0xa4000800, &SB_S9_           , 0,
20899        0x0                 },        /* SB[S9] */
20900     { instruction         , 0                   , 0   , 32,
20901        0xfc007f00, 0xa4001000, &LBU_S9_          , 0,
20902        0x0                 },        /* LBU[S9] */
20903     { pool                , P_PREF_S9_          , 2   , 32,
20904        0xfc007f00, 0xa4001800, 0                      , 0,
20905        0x0                 },        /* P.PREF[S9] */
20906     { instruction         , 0                   , 0   , 32,
20907        0xfc007f00, 0xa4002000, &LH_S9_           , 0,
20908        0x0                 },        /* LH[S9] */
20909     { instruction         , 0                   , 0   , 32,
20910        0xfc007f00, 0xa4002800, &SH_S9_           , 0,
20911        0x0                 },        /* SH[S9] */
20912     { instruction         , 0                   , 0   , 32,
20913        0xfc007f00, 0xa4003000, &LHU_S9_          , 0,
20914        0x0                 },        /* LHU[S9] */
20915     { instruction         , 0                   , 0   , 32,
20916        0xfc007f00, 0xa4003800, &LWU_S9_          , 0,
20917        MIPS64_             },        /* LWU[S9] */
20918     { instruction         , 0                   , 0   , 32,
20919        0xfc007f00, 0xa4004000, &LW_S9_           , 0,
20920        0x0                 },        /* LW[S9] */
20921     { instruction         , 0                   , 0   , 32,
20922        0xfc007f00, 0xa4004800, &SW_S9_           , 0,
20923        0x0                 },        /* SW[S9] */
20924     { instruction         , 0                   , 0   , 32,
20925        0xfc007f00, 0xa4005000, &LWC1_S9_         , 0,
20926        CP1_                },        /* LWC1[S9] */
20927     { instruction         , 0                   , 0   , 32,
20928        0xfc007f00, 0xa4005800, &SWC1_S9_         , 0,
20929        CP1_                },        /* SWC1[S9] */
20930     { instruction         , 0                   , 0   , 32,
20931        0xfc007f00, 0xa4006000, &LD_S9_           , 0,
20932        MIPS64_             },        /* LD[S9] */
20933     { instruction         , 0                   , 0   , 32,
20934        0xfc007f00, 0xa4006800, &SD_S9_           , 0,
20935        MIPS64_             },        /* SD[S9] */
20936     { instruction         , 0                   , 0   , 32,
20937        0xfc007f00, 0xa4007000, &LDC1_S9_         , 0,
20938        CP1_                },        /* LDC1[S9] */
20939     { instruction         , 0                   , 0   , 32,
20940        0xfc007f00, 0xa4007800, &SDC1_S9_         , 0,
20941        CP1_                },        /* SDC1[S9] */
20942 };
20943 
20944 
20945 static const Pool ASET_ACLR[2] = {
20946     { instruction         , 0                   , 0   , 32,
20947        0xfe007f00, 0xa4001100, &ASET             , 0,
20948        MCU_                },        /* ASET */
20949     { instruction         , 0                   , 0   , 32,
20950        0xfe007f00, 0xa6001100, &ACLR             , 0,
20951        MCU_                },        /* ACLR */
20952 };
20953 
20954 
20955 static const Pool P_LL[4] = {
20956     { instruction         , 0                   , 0   , 32,
20957        0xfc007f03, 0xa4005100, &LL               , 0,
20958        0x0                 },        /* LL */
20959     { instruction         , 0                   , 0   , 32,
20960        0xfc007f03, 0xa4005101, &LLWP             , 0,
20961        XNP_                },        /* LLWP */
20962     { reserved_block      , 0                   , 0   , 32,
20963        0xfc007f03, 0xa4005102, 0                      , 0,
20964        0x0                 },        /* P.LL~*(2) */
20965     { reserved_block      , 0                   , 0   , 32,
20966        0xfc007f03, 0xa4005103, 0                      , 0,
20967        0x0                 },        /* P.LL~*(3) */
20968 };
20969 
20970 
20971 static const Pool P_SC[4] = {
20972     { instruction         , 0                   , 0   , 32,
20973        0xfc007f03, 0xa4005900, &SC               , 0,
20974        0x0                 },        /* SC */
20975     { instruction         , 0                   , 0   , 32,
20976        0xfc007f03, 0xa4005901, &SCWP             , 0,
20977        XNP_                },        /* SCWP */
20978     { reserved_block      , 0                   , 0   , 32,
20979        0xfc007f03, 0xa4005902, 0                      , 0,
20980        0x0                 },        /* P.SC~*(2) */
20981     { reserved_block      , 0                   , 0   , 32,
20982        0xfc007f03, 0xa4005903, 0                      , 0,
20983        0x0                 },        /* P.SC~*(3) */
20984 };
20985 
20986 
20987 static const Pool P_LLD[8] = {
20988     { instruction         , 0                   , 0   , 32,
20989        0xfc007f07, 0xa4007100, &LLD              , 0,
20990        MIPS64_             },        /* LLD */
20991     { instruction         , 0                   , 0   , 32,
20992        0xfc007f07, 0xa4007101, &LLDP             , 0,
20993        MIPS64_             },        /* LLDP */
20994     { reserved_block      , 0                   , 0   , 32,
20995        0xfc007f07, 0xa4007102, 0                      , 0,
20996        0x0                 },        /* P.LLD~*(2) */
20997     { reserved_block      , 0                   , 0   , 32,
20998        0xfc007f07, 0xa4007103, 0                      , 0,
20999        0x0                 },        /* P.LLD~*(3) */
21000     { reserved_block      , 0                   , 0   , 32,
21001        0xfc007f07, 0xa4007104, 0                      , 0,
21002        0x0                 },        /* P.LLD~*(4) */
21003     { reserved_block      , 0                   , 0   , 32,
21004        0xfc007f07, 0xa4007105, 0                      , 0,
21005        0x0                 },        /* P.LLD~*(5) */
21006     { reserved_block      , 0                   , 0   , 32,
21007        0xfc007f07, 0xa4007106, 0                      , 0,
21008        0x0                 },        /* P.LLD~*(6) */
21009     { reserved_block      , 0                   , 0   , 32,
21010        0xfc007f07, 0xa4007107, 0                      , 0,
21011        0x0                 },        /* P.LLD~*(7) */
21012 };
21013 
21014 
21015 static const Pool P_SCD[8] = {
21016     { instruction         , 0                   , 0   , 32,
21017        0xfc007f07, 0xa4007900, &SCD              , 0,
21018        MIPS64_             },        /* SCD */
21019     { instruction         , 0                   , 0   , 32,
21020        0xfc007f07, 0xa4007901, &SCDP             , 0,
21021        MIPS64_             },        /* SCDP */
21022     { reserved_block      , 0                   , 0   , 32,
21023        0xfc007f07, 0xa4007902, 0                      , 0,
21024        0x0                 },        /* P.SCD~*(2) */
21025     { reserved_block      , 0                   , 0   , 32,
21026        0xfc007f07, 0xa4007903, 0                      , 0,
21027        0x0                 },        /* P.SCD~*(3) */
21028     { reserved_block      , 0                   , 0   , 32,
21029        0xfc007f07, 0xa4007904, 0                      , 0,
21030        0x0                 },        /* P.SCD~*(4) */
21031     { reserved_block      , 0                   , 0   , 32,
21032        0xfc007f07, 0xa4007905, 0                      , 0,
21033        0x0                 },        /* P.SCD~*(5) */
21034     { reserved_block      , 0                   , 0   , 32,
21035        0xfc007f07, 0xa4007906, 0                      , 0,
21036        0x0                 },        /* P.SCD~*(6) */
21037     { reserved_block      , 0                   , 0   , 32,
21038        0xfc007f07, 0xa4007907, 0                      , 0,
21039        0x0                 },        /* P.SCD~*(7) */
21040 };
21041 
21042 
21043 static const Pool P_LS_S1[16] = {
21044     { reserved_block      , 0                   , 0   , 32,
21045        0xfc007f00, 0xa4000100, 0                      , 0,
21046        0x0                 },        /* P.LS.S1~*(0) */
21047     { reserved_block      , 0                   , 0   , 32,
21048        0xfc007f00, 0xa4000900, 0                      , 0,
21049        0x0                 },        /* P.LS.S1~*(1) */
21050     { pool                , ASET_ACLR           , 2   , 32,
21051        0xfc007f00, 0xa4001100, 0                      , 0,
21052        0x0                 },        /* ASET_ACLR */
21053     { reserved_block      , 0                   , 0   , 32,
21054        0xfc007f00, 0xa4001900, 0                      , 0,
21055        0x0                 },        /* P.LS.S1~*(3) */
21056     { instruction         , 0                   , 0   , 32,
21057        0xfc007f00, 0xa4002100, &UALH             , 0,
21058        XMMS_               },        /* UALH */
21059     { instruction         , 0                   , 0   , 32,
21060        0xfc007f00, 0xa4002900, &UASH             , 0,
21061        XMMS_               },        /* UASH */
21062     { reserved_block      , 0                   , 0   , 32,
21063        0xfc007f00, 0xa4003100, 0                      , 0,
21064        0x0                 },        /* P.LS.S1~*(6) */
21065     { instruction         , 0                   , 0   , 32,
21066        0xfc007f00, 0xa4003900, &CACHE            , 0,
21067        CP0_                },        /* CACHE */
21068     { instruction         , 0                   , 0   , 32,
21069        0xfc007f00, 0xa4004100, &LWC2             , 0,
21070        CP2_                },        /* LWC2 */
21071     { instruction         , 0                   , 0   , 32,
21072        0xfc007f00, 0xa4004900, &SWC2             , 0,
21073        CP2_                },        /* SWC2 */
21074     { pool                , P_LL                , 4   , 32,
21075        0xfc007f00, 0xa4005100, 0                      , 0,
21076        0x0                 },        /* P.LL */
21077     { pool                , P_SC                , 4   , 32,
21078        0xfc007f00, 0xa4005900, 0                      , 0,
21079        0x0                 },        /* P.SC */
21080     { instruction         , 0                   , 0   , 32,
21081        0xfc007f00, 0xa4006100, &LDC2             , 0,
21082        CP2_                },        /* LDC2 */
21083     { instruction         , 0                   , 0   , 32,
21084        0xfc007f00, 0xa4006900, &SDC2             , 0,
21085        CP2_                },        /* SDC2 */
21086     { pool                , P_LLD               , 8   , 32,
21087        0xfc007f00, 0xa4007100, 0                      , 0,
21088        0x0                 },        /* P.LLD */
21089     { pool                , P_SCD               , 8   , 32,
21090        0xfc007f00, 0xa4007900, 0                      , 0,
21091        0x0                 },        /* P.SCD */
21092 };
21093 
21094 
21095 static const Pool P_PREFE[2] = {
21096     { instruction         , 0                   , 0   , 32,
21097        0xffe07f00, 0xa7e01a00, &SYNCIE           , 0,
21098        CP0_ | EVA_         },        /* SYNCIE */
21099     { instruction         , 0                   , 0   , 32,
21100        0xfc007f00, 0xa4001a00, &PREFE            , &PREFE_cond       ,
21101        CP0_ | EVA_         },        /* PREFE */
21102 };
21103 
21104 
21105 static const Pool P_LLE[4] = {
21106     { instruction         , 0                   , 0   , 32,
21107        0xfc007f03, 0xa4005200, &LLE              , 0,
21108        CP0_ | EVA_         },        /* LLE */
21109     { instruction         , 0                   , 0   , 32,
21110        0xfc007f03, 0xa4005201, &LLWPE            , 0,
21111        CP0_ | EVA_         },        /* LLWPE */
21112     { reserved_block      , 0                   , 0   , 32,
21113        0xfc007f03, 0xa4005202, 0                      , 0,
21114        0x0                 },        /* P.LLE~*(2) */
21115     { reserved_block      , 0                   , 0   , 32,
21116        0xfc007f03, 0xa4005203, 0                      , 0,
21117        0x0                 },        /* P.LLE~*(3) */
21118 };
21119 
21120 
21121 static const Pool P_SCE[4] = {
21122     { instruction         , 0                   , 0   , 32,
21123        0xfc007f03, 0xa4005a00, &SCE              , 0,
21124        CP0_ | EVA_         },        /* SCE */
21125     { instruction         , 0                   , 0   , 32,
21126        0xfc007f03, 0xa4005a01, &SCWPE            , 0,
21127        CP0_ | EVA_         },        /* SCWPE */
21128     { reserved_block      , 0                   , 0   , 32,
21129        0xfc007f03, 0xa4005a02, 0                      , 0,
21130        0x0                 },        /* P.SCE~*(2) */
21131     { reserved_block      , 0                   , 0   , 32,
21132        0xfc007f03, 0xa4005a03, 0                      , 0,
21133        0x0                 },        /* P.SCE~*(3) */
21134 };
21135 
21136 
21137 static const Pool P_LS_E0[16] = {
21138     { instruction         , 0                   , 0   , 32,
21139        0xfc007f00, 0xa4000200, &LBE              , 0,
21140        CP0_ | EVA_         },        /* LBE */
21141     { instruction         , 0                   , 0   , 32,
21142        0xfc007f00, 0xa4000a00, &SBE              , 0,
21143        CP0_ | EVA_         },        /* SBE */
21144     { instruction         , 0                   , 0   , 32,
21145        0xfc007f00, 0xa4001200, &LBUE             , 0,
21146        CP0_ | EVA_         },        /* LBUE */
21147     { pool                , P_PREFE             , 2   , 32,
21148        0xfc007f00, 0xa4001a00, 0                      , 0,
21149        0x0                 },        /* P.PREFE */
21150     { instruction         , 0                   , 0   , 32,
21151        0xfc007f00, 0xa4002200, &LHE              , 0,
21152        CP0_ | EVA_         },        /* LHE */
21153     { instruction         , 0                   , 0   , 32,
21154        0xfc007f00, 0xa4002a00, &SHE              , 0,
21155        CP0_ | EVA_         },        /* SHE */
21156     { instruction         , 0                   , 0   , 32,
21157        0xfc007f00, 0xa4003200, &LHUE             , 0,
21158        CP0_ | EVA_         },        /* LHUE */
21159     { instruction         , 0                   , 0   , 32,
21160        0xfc007f00, 0xa4003a00, &CACHEE           , 0,
21161        CP0_ | EVA_         },        /* CACHEE */
21162     { instruction         , 0                   , 0   , 32,
21163        0xfc007f00, 0xa4004200, &LWE              , 0,
21164        CP0_ | EVA_         },        /* LWE */
21165     { instruction         , 0                   , 0   , 32,
21166        0xfc007f00, 0xa4004a00, &SWE              , 0,
21167        CP0_ | EVA_         },        /* SWE */
21168     { pool                , P_LLE               , 4   , 32,
21169        0xfc007f00, 0xa4005200, 0                      , 0,
21170        0x0                 },        /* P.LLE */
21171     { pool                , P_SCE               , 4   , 32,
21172        0xfc007f00, 0xa4005a00, 0                      , 0,
21173        0x0                 },        /* P.SCE */
21174     { reserved_block      , 0                   , 0   , 32,
21175        0xfc007f00, 0xa4006200, 0                      , 0,
21176        0x0                 },        /* P.LS.E0~*(12) */
21177     { reserved_block      , 0                   , 0   , 32,
21178        0xfc007f00, 0xa4006a00, 0                      , 0,
21179        0x0                 },        /* P.LS.E0~*(13) */
21180     { reserved_block      , 0                   , 0   , 32,
21181        0xfc007f00, 0xa4007200, 0                      , 0,
21182        0x0                 },        /* P.LS.E0~*(14) */
21183     { reserved_block      , 0                   , 0   , 32,
21184        0xfc007f00, 0xa4007a00, 0                      , 0,
21185        0x0                 },        /* P.LS.E0~*(15) */
21186 };
21187 
21188 
21189 static const Pool P_LS_WM[2] = {
21190     { instruction         , 0                   , 0   , 32,
21191        0xfc000f00, 0xa4000400, &LWM              , 0,
21192        XMMS_               },        /* LWM */
21193     { instruction         , 0                   , 0   , 32,
21194        0xfc000f00, 0xa4000c00, &SWM              , 0,
21195        XMMS_               },        /* SWM */
21196 };
21197 
21198 
21199 static const Pool P_LS_UAWM[2] = {
21200     { instruction         , 0                   , 0   , 32,
21201        0xfc000f00, 0xa4000500, &UALWM            , 0,
21202        XMMS_               },        /* UALWM */
21203     { instruction         , 0                   , 0   , 32,
21204        0xfc000f00, 0xa4000d00, &UASWM            , 0,
21205        XMMS_               },        /* UASWM */
21206 };
21207 
21208 
21209 static const Pool P_LS_DM[2] = {
21210     { instruction         , 0                   , 0   , 32,
21211        0xfc000f00, 0xa4000600, &LDM              , 0,
21212        MIPS64_             },        /* LDM */
21213     { instruction         , 0                   , 0   , 32,
21214        0xfc000f00, 0xa4000e00, &SDM              , 0,
21215        MIPS64_             },        /* SDM */
21216 };
21217 
21218 
21219 static const Pool P_LS_UADM[2] = {
21220     { instruction         , 0                   , 0   , 32,
21221        0xfc000f00, 0xa4000700, &UALDM            , 0,
21222        MIPS64_             },        /* UALDM */
21223     { instruction         , 0                   , 0   , 32,
21224        0xfc000f00, 0xa4000f00, &UASDM            , 0,
21225        MIPS64_             },        /* UASDM */
21226 };
21227 
21228 
21229 static const Pool P_LS_S9[8] = {
21230     { pool                , P_LS_S0             , 16  , 32,
21231        0xfc000700, 0xa4000000, 0                      , 0,
21232        0x0                 },        /* P.LS.S0 */
21233     { pool                , P_LS_S1             , 16  , 32,
21234        0xfc000700, 0xa4000100, 0                      , 0,
21235        0x0                 },        /* P.LS.S1 */
21236     { pool                , P_LS_E0             , 16  , 32,
21237        0xfc000700, 0xa4000200, 0                      , 0,
21238        0x0                 },        /* P.LS.E0 */
21239     { reserved_block      , 0                   , 0   , 32,
21240        0xfc000700, 0xa4000300, 0                      , 0,
21241        0x0                 },        /* P.LS.S9~*(3) */
21242     { pool                , P_LS_WM             , 2   , 32,
21243        0xfc000700, 0xa4000400, 0                      , 0,
21244        0x0                 },        /* P.LS.WM */
21245     { pool                , P_LS_UAWM           , 2   , 32,
21246        0xfc000700, 0xa4000500, 0                      , 0,
21247        0x0                 },        /* P.LS.UAWM */
21248     { pool                , P_LS_DM             , 2   , 32,
21249        0xfc000700, 0xa4000600, 0                      , 0,
21250        0x0                 },        /* P.LS.DM */
21251     { pool                , P_LS_UADM           , 2   , 32,
21252        0xfc000700, 0xa4000700, 0                      , 0,
21253        0x0                 },        /* P.LS.UADM */
21254 };
21255 
21256 
21257 static const Pool P_BAL[2] = {
21258     { branch_instruction  , 0                   , 0   , 32,
21259        0xfe000000, 0x28000000, &BC_32_           , 0,
21260        0x0                 },        /* BC[32] */
21261     { call_instruction    , 0                   , 0   , 32,
21262        0xfe000000, 0x2a000000, &BALC_32_         , 0,
21263        0x0                 },        /* BALC[32] */
21264 };
21265 
21266 
21267 static const Pool P_BALRSC[2] = {
21268     { branch_instruction  , 0                   , 0   , 32,
21269        0xffe0f000, 0x48008000, &BRSC             , 0,
21270        0x0                 },        /* BRSC */
21271     { call_instruction    , 0                   , 0   , 32,
21272        0xfc00f000, 0x48008000, &BALRSC           , &BALRSC_cond      ,
21273        0x0                 },        /* BALRSC */
21274 };
21275 
21276 
21277 static const Pool P_J[16] = {
21278     { call_instruction    , 0                   , 0   , 32,
21279        0xfc00f000, 0x48000000, &JALRC_32_        , 0,
21280        0x0                 },        /* JALRC[32] */
21281     { call_instruction    , 0                   , 0   , 32,
21282        0xfc00f000, 0x48001000, &JALRC_HB         , 0,
21283        0x0                 },        /* JALRC.HB */
21284     { reserved_block      , 0                   , 0   , 32,
21285        0xfc00f000, 0x48002000, 0                      , 0,
21286        0x0                 },        /* P.J~*(2) */
21287     { reserved_block      , 0                   , 0   , 32,
21288        0xfc00f000, 0x48003000, 0                      , 0,
21289        0x0                 },        /* P.J~*(3) */
21290     { reserved_block      , 0                   , 0   , 32,
21291        0xfc00f000, 0x48004000, 0                      , 0,
21292        0x0                 },        /* P.J~*(4) */
21293     { reserved_block      , 0                   , 0   , 32,
21294        0xfc00f000, 0x48005000, 0                      , 0,
21295        0x0                 },        /* P.J~*(5) */
21296     { reserved_block      , 0                   , 0   , 32,
21297        0xfc00f000, 0x48006000, 0                      , 0,
21298        0x0                 },        /* P.J~*(6) */
21299     { reserved_block      , 0                   , 0   , 32,
21300        0xfc00f000, 0x48007000, 0                      , 0,
21301        0x0                 },        /* P.J~*(7) */
21302     { pool                , P_BALRSC            , 2   , 32,
21303        0xfc00f000, 0x48008000, 0                      , 0,
21304        0x0                 },        /* P.BALRSC */
21305     { reserved_block      , 0                   , 0   , 32,
21306        0xfc00f000, 0x48009000, 0                      , 0,
21307        0x0                 },        /* P.J~*(9) */
21308     { reserved_block      , 0                   , 0   , 32,
21309        0xfc00f000, 0x4800a000, 0                      , 0,
21310        0x0                 },        /* P.J~*(10) */
21311     { reserved_block      , 0                   , 0   , 32,
21312        0xfc00f000, 0x4800b000, 0                      , 0,
21313        0x0                 },        /* P.J~*(11) */
21314     { reserved_block      , 0                   , 0   , 32,
21315        0xfc00f000, 0x4800c000, 0                      , 0,
21316        0x0                 },        /* P.J~*(12) */
21317     { reserved_block      , 0                   , 0   , 32,
21318        0xfc00f000, 0x4800d000, 0                      , 0,
21319        0x0                 },        /* P.J~*(13) */
21320     { reserved_block      , 0                   , 0   , 32,
21321        0xfc00f000, 0x4800e000, 0                      , 0,
21322        0x0                 },        /* P.J~*(14) */
21323     { reserved_block      , 0                   , 0   , 32,
21324        0xfc00f000, 0x4800f000, 0                      , 0,
21325        0x0                 },        /* P.J~*(15) */
21326 };
21327 
21328 
21329 static const Pool P_BR3A[32] = {
21330     { branch_instruction  , 0                   , 0   , 32,
21331        0xfc1fc000, 0x88004000, &BC1EQZC          , 0,
21332        CP1_                },        /* BC1EQZC */
21333     { branch_instruction  , 0                   , 0   , 32,
21334        0xfc1fc000, 0x88014000, &BC1NEZC          , 0,
21335        CP1_                },        /* BC1NEZC */
21336     { branch_instruction  , 0                   , 0   , 32,
21337        0xfc1fc000, 0x88024000, &BC2EQZC          , 0,
21338        CP2_                },        /* BC2EQZC */
21339     { branch_instruction  , 0                   , 0   , 32,
21340        0xfc1fc000, 0x88034000, &BC2NEZC          , 0,
21341        CP2_                },        /* BC2NEZC */
21342     { branch_instruction  , 0                   , 0   , 32,
21343        0xfc1fc000, 0x88044000, &BPOSGE32C        , 0,
21344        DSP_                },        /* BPOSGE32C */
21345     { reserved_block      , 0                   , 0   , 32,
21346        0xfc1fc000, 0x88054000, 0                      , 0,
21347        0x0                 },        /* P.BR3A~*(5) */
21348     { reserved_block      , 0                   , 0   , 32,
21349        0xfc1fc000, 0x88064000, 0                      , 0,
21350        0x0                 },        /* P.BR3A~*(6) */
21351     { reserved_block      , 0                   , 0   , 32,
21352        0xfc1fc000, 0x88074000, 0                      , 0,
21353        0x0                 },        /* P.BR3A~*(7) */
21354     { reserved_block      , 0                   , 0   , 32,
21355        0xfc1fc000, 0x88084000, 0                      , 0,
21356        0x0                 },        /* P.BR3A~*(8) */
21357     { reserved_block      , 0                   , 0   , 32,
21358        0xfc1fc000, 0x88094000, 0                      , 0,
21359        0x0                 },        /* P.BR3A~*(9) */
21360     { reserved_block      , 0                   , 0   , 32,
21361        0xfc1fc000, 0x880a4000, 0                      , 0,
21362        0x0                 },        /* P.BR3A~*(10) */
21363     { reserved_block      , 0                   , 0   , 32,
21364        0xfc1fc000, 0x880b4000, 0                      , 0,
21365        0x0                 },        /* P.BR3A~*(11) */
21366     { reserved_block      , 0                   , 0   , 32,
21367        0xfc1fc000, 0x880c4000, 0                      , 0,
21368        0x0                 },        /* P.BR3A~*(12) */
21369     { reserved_block      , 0                   , 0   , 32,
21370        0xfc1fc000, 0x880d4000, 0                      , 0,
21371        0x0                 },        /* P.BR3A~*(13) */
21372     { reserved_block      , 0                   , 0   , 32,
21373        0xfc1fc000, 0x880e4000, 0                      , 0,
21374        0x0                 },        /* P.BR3A~*(14) */
21375     { reserved_block      , 0                   , 0   , 32,
21376        0xfc1fc000, 0x880f4000, 0                      , 0,
21377        0x0                 },        /* P.BR3A~*(15) */
21378     { reserved_block      , 0                   , 0   , 32,
21379        0xfc1fc000, 0x88104000, 0                      , 0,
21380        0x0                 },        /* P.BR3A~*(16) */
21381     { reserved_block      , 0                   , 0   , 32,
21382        0xfc1fc000, 0x88114000, 0                      , 0,
21383        0x0                 },        /* P.BR3A~*(17) */
21384     { reserved_block      , 0                   , 0   , 32,
21385        0xfc1fc000, 0x88124000, 0                      , 0,
21386        0x0                 },        /* P.BR3A~*(18) */
21387     { reserved_block      , 0                   , 0   , 32,
21388        0xfc1fc000, 0x88134000, 0                      , 0,
21389        0x0                 },        /* P.BR3A~*(19) */
21390     { reserved_block      , 0                   , 0   , 32,
21391        0xfc1fc000, 0x88144000, 0                      , 0,
21392        0x0                 },        /* P.BR3A~*(20) */
21393     { reserved_block      , 0                   , 0   , 32,
21394        0xfc1fc000, 0x88154000, 0                      , 0,
21395        0x0                 },        /* P.BR3A~*(21) */
21396     { reserved_block      , 0                   , 0   , 32,
21397        0xfc1fc000, 0x88164000, 0                      , 0,
21398        0x0                 },        /* P.BR3A~*(22) */
21399     { reserved_block      , 0                   , 0   , 32,
21400        0xfc1fc000, 0x88174000, 0                      , 0,
21401        0x0                 },        /* P.BR3A~*(23) */
21402     { reserved_block      , 0                   , 0   , 32,
21403        0xfc1fc000, 0x88184000, 0                      , 0,
21404        0x0                 },        /* P.BR3A~*(24) */
21405     { reserved_block      , 0                   , 0   , 32,
21406        0xfc1fc000, 0x88194000, 0                      , 0,
21407        0x0                 },        /* P.BR3A~*(25) */
21408     { reserved_block      , 0                   , 0   , 32,
21409        0xfc1fc000, 0x881a4000, 0                      , 0,
21410        0x0                 },        /* P.BR3A~*(26) */
21411     { reserved_block      , 0                   , 0   , 32,
21412        0xfc1fc000, 0x881b4000, 0                      , 0,
21413        0x0                 },        /* P.BR3A~*(27) */
21414     { reserved_block      , 0                   , 0   , 32,
21415        0xfc1fc000, 0x881c4000, 0                      , 0,
21416        0x0                 },        /* P.BR3A~*(28) */
21417     { reserved_block      , 0                   , 0   , 32,
21418        0xfc1fc000, 0x881d4000, 0                      , 0,
21419        0x0                 },        /* P.BR3A~*(29) */
21420     { reserved_block      , 0                   , 0   , 32,
21421        0xfc1fc000, 0x881e4000, 0                      , 0,
21422        0x0                 },        /* P.BR3A~*(30) */
21423     { reserved_block      , 0                   , 0   , 32,
21424        0xfc1fc000, 0x881f4000, 0                      , 0,
21425        0x0                 },        /* P.BR3A~*(31) */
21426 };
21427 
21428 
21429 static const Pool P_BR1[4] = {
21430     { branch_instruction  , 0                   , 0   , 32,
21431        0xfc00c000, 0x88000000, &BEQC_32_         , 0,
21432        0x0                 },        /* BEQC[32] */
21433     { pool                , P_BR3A              , 32  , 32,
21434        0xfc00c000, 0x88004000, 0                      , 0,
21435        0x0                 },        /* P.BR3A */
21436     { branch_instruction  , 0                   , 0   , 32,
21437        0xfc00c000, 0x88008000, &BGEC             , 0,
21438        0x0                 },        /* BGEC */
21439     { branch_instruction  , 0                   , 0   , 32,
21440        0xfc00c000, 0x8800c000, &BGEUC            , 0,
21441        0x0                 },        /* BGEUC */
21442 };
21443 
21444 
21445 static const Pool P_BR2[4] = {
21446     { branch_instruction  , 0                   , 0   , 32,
21447        0xfc00c000, 0xa8000000, &BNEC_32_         , 0,
21448        0x0                 },        /* BNEC[32] */
21449     { reserved_block      , 0                   , 0   , 32,
21450        0xfc00c000, 0xa8004000, 0                      , 0,
21451        0x0                 },        /* P.BR2~*(1) */
21452     { branch_instruction  , 0                   , 0   , 32,
21453        0xfc00c000, 0xa8008000, &BLTC             , 0,
21454        0x0                 },        /* BLTC */
21455     { branch_instruction  , 0                   , 0   , 32,
21456        0xfc00c000, 0xa800c000, &BLTUC            , 0,
21457        0x0                 },        /* BLTUC */
21458 };
21459 
21460 
21461 static const Pool P_BRI[8] = {
21462     { branch_instruction  , 0                   , 0   , 32,
21463        0xfc1c0000, 0xc8000000, &BEQIC            , 0,
21464        0x0                 },        /* BEQIC */
21465     { branch_instruction  , 0                   , 0   , 32,
21466        0xfc1c0000, 0xc8040000, &BBEQZC           , 0,
21467        XMMS_               },        /* BBEQZC */
21468     { branch_instruction  , 0                   , 0   , 32,
21469        0xfc1c0000, 0xc8080000, &BGEIC            , 0,
21470        0x0                 },        /* BGEIC */
21471     { branch_instruction  , 0                   , 0   , 32,
21472        0xfc1c0000, 0xc80c0000, &BGEIUC           , 0,
21473        0x0                 },        /* BGEIUC */
21474     { branch_instruction  , 0                   , 0   , 32,
21475        0xfc1c0000, 0xc8100000, &BNEIC            , 0,
21476        0x0                 },        /* BNEIC */
21477     { branch_instruction  , 0                   , 0   , 32,
21478        0xfc1c0000, 0xc8140000, &BBNEZC           , 0,
21479        XMMS_               },        /* BBNEZC */
21480     { branch_instruction  , 0                   , 0   , 32,
21481        0xfc1c0000, 0xc8180000, &BLTIC            , 0,
21482        0x0                 },        /* BLTIC */
21483     { branch_instruction  , 0                   , 0   , 32,
21484        0xfc1c0000, 0xc81c0000, &BLTIUC           , 0,
21485        0x0                 },        /* BLTIUC */
21486 };
21487 
21488 
21489 static const Pool P32[32] = {
21490     { pool                , P_ADDIU             , 2   , 32,
21491        0xfc000000, 0x00000000, 0                      , 0,
21492        0x0                 },        /* P.ADDIU */
21493     { pool                , P32A                , 8   , 32,
21494        0xfc000000, 0x20000000, 0                      , 0,
21495        0x0                 },        /* P32A */
21496     { pool                , P_GP_W              , 4   , 32,
21497        0xfc000000, 0x40000000, 0                      , 0,
21498        0x0                 },        /* P.GP.W */
21499     { pool                , POOL48I             , 32  , 48,
21500        0xfc0000000000ull, 0x600000000000ull, 0                      , 0,
21501        0x0                 },        /* POOL48I */
21502     { pool                , P_U12               , 16  , 32,
21503        0xfc000000, 0x80000000, 0                      , 0,
21504        0x0                 },        /* P.U12 */
21505     { pool                , POOL32F             , 8   , 32,
21506        0xfc000000, 0xa0000000, 0                      , 0,
21507        CP1_                },        /* POOL32F */
21508     { pool                , POOL32S             , 8   , 32,
21509        0xfc000000, 0xc0000000, 0                      , 0,
21510        0x0                 },        /* POOL32S */
21511     { pool                , P_LUI               , 2   , 32,
21512        0xfc000000, 0xe0000000, 0                      , 0,
21513        0x0                 },        /* P.LUI */
21514     { instruction         , 0                   , 0   , 32,
21515        0xfc000000, 0x04000000, &ADDIUPC_32_      , 0,
21516        0x0                 },        /* ADDIUPC[32] */
21517     { reserved_block      , 0                   , 0   , 32,
21518        0xfc000000, 0x24000000, 0                      , 0,
21519        0x0                 },        /* P32~*(5) */
21520     { pool                , P_GP_BH             , 8   , 32,
21521        0xfc000000, 0x44000000, 0                      , 0,
21522        0x0                 },        /* P.GP.BH */
21523     { reserved_block      , 0                   , 0   , 32,
21524        0xfc000000, 0x64000000, 0                      , 0,
21525        0x0                 },        /* P32~*(13) */
21526     { pool                , P_LS_U12            , 16  , 32,
21527        0xfc000000, 0x84000000, 0                      , 0,
21528        0x0                 },        /* P.LS.U12 */
21529     { pool                , P_LS_S9             , 8   , 32,
21530        0xfc000000, 0xa4000000, 0                      , 0,
21531        0x0                 },        /* P.LS.S9 */
21532     { reserved_block      , 0                   , 0   , 32,
21533        0xfc000000, 0xc4000000, 0                      , 0,
21534        0x0                 },        /* P32~*(25) */
21535     { reserved_block      , 0                   , 0   , 32,
21536        0xfc000000, 0xe4000000, 0                      , 0,
21537        0x0                 },        /* P32~*(29) */
21538     { call_instruction    , 0                   , 0   , 32,
21539        0xfc000000, 0x08000000, &MOVE_BALC        , 0,
21540        XMMS_               },        /* MOVE.BALC */
21541     { pool                , P_BAL               , 2   , 32,
21542        0xfc000000, 0x28000000, 0                      , 0,
21543        0x0                 },        /* P.BAL */
21544     { pool                , P_J                 , 16  , 32,
21545        0xfc000000, 0x48000000, 0                      , 0,
21546        0x0                 },        /* P.J */
21547     { reserved_block      , 0                   , 0   , 32,
21548        0xfc000000, 0x68000000, 0                      , 0,
21549        0x0                 },        /* P32~*(14) */
21550     { pool                , P_BR1               , 4   , 32,
21551        0xfc000000, 0x88000000, 0                      , 0,
21552        0x0                 },        /* P.BR1 */
21553     { pool                , P_BR2               , 4   , 32,
21554        0xfc000000, 0xa8000000, 0                      , 0,
21555        0x0                 },        /* P.BR2 */
21556     { pool                , P_BRI               , 8   , 32,
21557        0xfc000000, 0xc8000000, 0                      , 0,
21558        0x0                 },        /* P.BRI */
21559     { reserved_block      , 0                   , 0   , 32,
21560        0xfc000000, 0xe8000000, 0                      , 0,
21561        0x0                 },        /* P32~*(30) */
21562     { reserved_block      , 0                   , 0   , 32,
21563        0xfc000000, 0x0c000000, 0                      , 0,
21564        0x0                 },        /* P32~*(3) */
21565     { reserved_block      , 0                   , 0   , 32,
21566        0xfc000000, 0x2c000000, 0                      , 0,
21567        0x0                 },        /* P32~*(7) */
21568     { reserved_block      , 0                   , 0   , 32,
21569        0xfc000000, 0x4c000000, 0                      , 0,
21570        0x0                 },        /* P32~*(11) */
21571     { reserved_block      , 0                   , 0   , 32,
21572        0xfc000000, 0x6c000000, 0                      , 0,
21573        0x0                 },        /* P32~*(15) */
21574     { reserved_block      , 0                   , 0   , 32,
21575        0xfc000000, 0x8c000000, 0                      , 0,
21576        0x0                 },        /* P32~*(19) */
21577     { reserved_block      , 0                   , 0   , 32,
21578        0xfc000000, 0xac000000, 0                      , 0,
21579        0x0                 },        /* P32~*(23) */
21580     { reserved_block      , 0                   , 0   , 32,
21581        0xfc000000, 0xcc000000, 0                      , 0,
21582        0x0                 },        /* P32~*(27) */
21583     { reserved_block      , 0                   , 0   , 32,
21584        0xfc000000, 0xec000000, 0                      , 0,
21585        0x0                 },        /* P32~*(31) */
21586 };
21587 
21588 
21589 static const Pool P16_SYSCALL[2] = {
21590     { instruction         , 0                   , 0   , 16,
21591        0xfffc    , 0x1008    , &SYSCALL_16_      , 0,
21592        0x0                 },        /* SYSCALL[16] */
21593     { instruction         , 0                   , 0   , 16,
21594        0xfffc    , 0x100c    , &HYPCALL_16_      , 0,
21595        CP0_ | VZ_          },        /* HYPCALL[16] */
21596 };
21597 
21598 
21599 static const Pool P16_RI[4] = {
21600     { reserved_block      , 0                   , 0   , 16,
21601        0xfff8    , 0x1000    , 0                      , 0,
21602        0x0                 },        /* P16.RI~*(0) */
21603     { pool                , P16_SYSCALL         , 2   , 16,
21604        0xfff8    , 0x1008    , 0                      , 0,
21605        0x0                 },        /* P16.SYSCALL */
21606     { instruction         , 0                   , 0   , 16,
21607        0xfff8    , 0x1010    , &BREAK_16_        , 0,
21608        0x0                 },        /* BREAK[16] */
21609     { instruction         , 0                   , 0   , 16,
21610        0xfff8    , 0x1018    , &SDBBP_16_        , 0,
21611        EJTAG_              },        /* SDBBP[16] */
21612 };
21613 
21614 
21615 static const Pool P16_MV[2] = {
21616     { pool                , P16_RI              , 4   , 16,
21617        0xffe0    , 0x1000    , 0                      , 0,
21618        0x0                 },        /* P16.RI */
21619     { instruction         , 0                   , 0   , 16,
21620        0xfc00    , 0x1000    , &MOVE             , &MOVE_cond        ,
21621        0x0                 },        /* MOVE */
21622 };
21623 
21624 
21625 static const Pool P16_SHIFT[2] = {
21626     { instruction         , 0                   , 0   , 16,
21627        0xfc08    , 0x3000    , &SLL_16_          , 0,
21628        0x0                 },        /* SLL[16] */
21629     { instruction         , 0                   , 0   , 16,
21630        0xfc08    , 0x3008    , &SRL_16_          , 0,
21631        0x0                 },        /* SRL[16] */
21632 };
21633 
21634 
21635 static const Pool POOL16C_00[4] = {
21636     { instruction         , 0                   , 0   , 16,
21637        0xfc0f    , 0x5000    , &NOT_16_          , 0,
21638        0x0                 },        /* NOT[16] */
21639     { instruction         , 0                   , 0   , 16,
21640        0xfc0f    , 0x5004    , &XOR_16_          , 0,
21641        0x0                 },        /* XOR[16] */
21642     { instruction         , 0                   , 0   , 16,
21643        0xfc0f    , 0x5008    , &AND_16_          , 0,
21644        0x0                 },        /* AND[16] */
21645     { instruction         , 0                   , 0   , 16,
21646        0xfc0f    , 0x500c    , &OR_16_           , 0,
21647        0x0                 },        /* OR[16] */
21648 };
21649 
21650 
21651 static const Pool POOL16C_0[2] = {
21652     { pool                , POOL16C_00          , 4   , 16,
21653        0xfc03    , 0x5000    , 0                      , 0,
21654        0x0                 },        /* POOL16C_00 */
21655     { reserved_block      , 0                   , 0   , 16,
21656        0xfc03    , 0x5002    , 0                      , 0,
21657        0x0                 },        /* POOL16C_0~*(1) */
21658 };
21659 
21660 
21661 static const Pool P16C[2] = {
21662     { pool                , POOL16C_0           , 2   , 16,
21663        0xfc01    , 0x5000    , 0                      , 0,
21664        0x0                 },        /* POOL16C_0 */
21665     { instruction         , 0                   , 0   , 16,
21666        0xfc01    , 0x5001    , &LWXS_16_         , 0,
21667        0x0                 },        /* LWXS[16] */
21668 };
21669 
21670 
21671 static const Pool P16_A1[2] = {
21672     { reserved_block      , 0                   , 0   , 16,
21673        0xfc40    , 0x7000    , 0                      , 0,
21674        0x0                 },        /* P16.A1~*(0) */
21675     { instruction         , 0                   , 0   , 16,
21676        0xfc40    , 0x7040    , &ADDIU_R1_SP_     , 0,
21677        0x0                 },        /* ADDIU[R1.SP] */
21678 };
21679 
21680 
21681 static const Pool P_ADDIU_RS5_[2] = {
21682     { instruction         , 0                   , 0   , 16,
21683        0xffe8    , 0x9008    , &NOP_16_          , 0,
21684        0x0                 },        /* NOP[16] */
21685     { instruction         , 0                   , 0   , 16,
21686        0xfc08    , 0x9008    , &ADDIU_RS5_       , &ADDIU_RS5__cond  ,
21687        0x0                 },        /* ADDIU[RS5] */
21688 };
21689 
21690 
21691 static const Pool P16_A2[2] = {
21692     { instruction         , 0                   , 0   , 16,
21693        0xfc08    , 0x9000    , &ADDIU_R2_        , 0,
21694        0x0                 },        /* ADDIU[R2] */
21695     { pool                , P_ADDIU_RS5_        , 2   , 16,
21696        0xfc08    , 0x9008    , 0                      , 0,
21697        0x0                 },        /* P.ADDIU[RS5] */
21698 };
21699 
21700 
21701 static const Pool P16_ADDU[2] = {
21702     { instruction         , 0                   , 0   , 16,
21703        0xfc01    , 0xb000    , &ADDU_16_         , 0,
21704        0x0                 },        /* ADDU[16] */
21705     { instruction         , 0                   , 0   , 16,
21706        0xfc01    , 0xb001    , &SUBU_16_         , 0,
21707        0x0                 },        /* SUBU[16] */
21708 };
21709 
21710 
21711 static const Pool P16_JRC[2] = {
21712     { branch_instruction  , 0                   , 0   , 16,
21713        0xfc1f    , 0xd800    , &JRC              , 0,
21714        0x0                 },        /* JRC */
21715     { call_instruction    , 0                   , 0   , 16,
21716        0xfc1f    , 0xd810    , &JALRC_16_        , 0,
21717        0x0                 },        /* JALRC[16] */
21718 };
21719 
21720 
21721 static const Pool P16_BR1[2] = {
21722     { branch_instruction  , 0                   , 0   , 16,
21723        0xfc00    , 0xd800    , &BEQC_16_         , &BEQC_16__cond    ,
21724        XMMS_               },        /* BEQC[16] */
21725     { branch_instruction  , 0                   , 0   , 16,
21726        0xfc00    , 0xd800    , &BNEC_16_         , &BNEC_16__cond    ,
21727        XMMS_               },        /* BNEC[16] */
21728 };
21729 
21730 
21731 static const Pool P16_BR[2] = {
21732     { pool                , P16_JRC             , 2   , 16,
21733        0xfc0f    , 0xd800    , 0                      , 0,
21734        0x0                 },        /* P16.JRC */
21735     { pool                , P16_BR1             , 2   , 16,
21736        0xfc00    , 0xd800    , 0                      , &P16_BR1_cond     ,
21737        0x0                 },        /* P16.BR1 */
21738 };
21739 
21740 
21741 static const Pool P16_SR[2] = {
21742     { instruction         , 0                   , 0   , 16,
21743        0xfd00    , 0x1c00    , &SAVE_16_         , 0,
21744        0x0                 },        /* SAVE[16] */
21745     { return_instruction  , 0                   , 0   , 16,
21746        0xfd00    , 0x1d00    , &RESTORE_JRC_16_  , 0,
21747        0x0                 },        /* RESTORE.JRC[16] */
21748 };
21749 
21750 
21751 static const Pool P16_4X4[4] = {
21752     { instruction         , 0                   , 0   , 16,
21753        0xfd08    , 0x3c00    , &ADDU_4X4_        , 0,
21754        XMMS_               },        /* ADDU[4X4] */
21755     { instruction         , 0                   , 0   , 16,
21756        0xfd08    , 0x3c08    , &MUL_4X4_         , 0,
21757        XMMS_               },        /* MUL[4X4] */
21758     { reserved_block      , 0                   , 0   , 16,
21759        0xfd08    , 0x3d00    , 0                      , 0,
21760        0x0                 },        /* P16.4X4~*(2) */
21761     { reserved_block      , 0                   , 0   , 16,
21762        0xfd08    , 0x3d08    , 0                      , 0,
21763        0x0                 },        /* P16.4X4~*(3) */
21764 };
21765 
21766 
21767 static const Pool P16_LB[4] = {
21768     { instruction         , 0                   , 0   , 16,
21769        0xfc0c    , 0x5c00    , &LB_16_           , 0,
21770        0x0                 },        /* LB[16] */
21771     { instruction         , 0                   , 0   , 16,
21772        0xfc0c    , 0x5c04    , &SB_16_           , 0,
21773        0x0                 },        /* SB[16] */
21774     { instruction         , 0                   , 0   , 16,
21775        0xfc0c    , 0x5c08    , &LBU_16_          , 0,
21776        0x0                 },        /* LBU[16] */
21777     { reserved_block      , 0                   , 0   , 16,
21778        0xfc0c    , 0x5c0c    , 0                      , 0,
21779        0x0                 },        /* P16.LB~*(3) */
21780 };
21781 
21782 
21783 static const Pool P16_LH[4] = {
21784     { instruction         , 0                   , 0   , 16,
21785        0xfc09    , 0x7c00    , &LH_16_           , 0,
21786        0x0                 },        /* LH[16] */
21787     { instruction         , 0                   , 0   , 16,
21788        0xfc09    , 0x7c01    , &SH_16_           , 0,
21789        0x0                 },        /* SH[16] */
21790     { instruction         , 0                   , 0   , 16,
21791        0xfc09    , 0x7c08    , &LHU_16_          , 0,
21792        0x0                 },        /* LHU[16] */
21793     { reserved_block      , 0                   , 0   , 16,
21794        0xfc09    , 0x7c09    , 0                      , 0,
21795        0x0                 },        /* P16.LH~*(3) */
21796 };
21797 
21798 
21799 static const Pool P16[32] = {
21800     { pool                , P16_MV              , 2   , 16,
21801        0xfc00    , 0x1000    , 0                      , 0,
21802        0x0                 },        /* P16.MV */
21803     { pool                , P16_SHIFT           , 2   , 16,
21804        0xfc00    , 0x3000    , 0                      , 0,
21805        0x0                 },        /* P16.SHIFT */
21806     { pool                , P16C                , 2   , 16,
21807        0xfc00    , 0x5000    , 0                      , 0,
21808        0x0                 },        /* P16C */
21809     { pool                , P16_A1              , 2   , 16,
21810        0xfc00    , 0x7000    , 0                      , 0,
21811        0x0                 },        /* P16.A1 */
21812     { pool                , P16_A2              , 2   , 16,
21813        0xfc00    , 0x9000    , 0                      , 0,
21814        0x0                 },        /* P16.A2 */
21815     { pool                , P16_ADDU            , 2   , 16,
21816        0xfc00    , 0xb000    , 0                      , 0,
21817        0x0                 },        /* P16.ADDU */
21818     { instruction         , 0                   , 0   , 16,
21819        0xfc00    , 0xd000    , &LI_16_           , 0,
21820        0x0                 },        /* LI[16] */
21821     { instruction         , 0                   , 0   , 16,
21822        0xfc00    , 0xf000    , &ANDI_16_         , 0,
21823        0x0                 },        /* ANDI[16] */
21824     { instruction         , 0                   , 0   , 16,
21825        0xfc00    , 0x1400    , &LW_16_           , 0,
21826        0x0                 },        /* LW[16] */
21827     { instruction         , 0                   , 0   , 16,
21828        0xfc00    , 0x3400    , &LW_SP_           , 0,
21829        0x0                 },        /* LW[SP] */
21830     { instruction         , 0                   , 0   , 16,
21831        0xfc00    , 0x5400    , &LW_GP16_         , 0,
21832        0x0                 },        /* LW[GP16] */
21833     { instruction         , 0                   , 0   , 16,
21834        0xfc00    , 0x7400    , &LW_4X4_          , 0,
21835        XMMS_               },        /* LW[4X4] */
21836     { instruction         , 0                   , 0   , 16,
21837        0xfc00    , 0x9400    , &SW_16_           , 0,
21838        0x0                 },        /* SW[16] */
21839     { instruction         , 0                   , 0   , 16,
21840        0xfc00    , 0xb400    , &SW_SP_           , 0,
21841        0x0                 },        /* SW[SP] */
21842     { instruction         , 0                   , 0   , 16,
21843        0xfc00    , 0xd400    , &SW_GP16_         , 0,
21844        0x0                 },        /* SW[GP16] */
21845     { instruction         , 0                   , 0   , 16,
21846        0xfc00    , 0xf400    , &SW_4X4_          , 0,
21847        XMMS_               },        /* SW[4X4] */
21848     { branch_instruction  , 0                   , 0   , 16,
21849        0xfc00    , 0x1800    , &BC_16_           , 0,
21850        0x0                 },        /* BC[16] */
21851     { call_instruction    , 0                   , 0   , 16,
21852        0xfc00    , 0x3800    , &BALC_16_         , 0,
21853        0x0                 },        /* BALC[16] */
21854     { reserved_block      , 0                   , 0   , 16,
21855        0xfc00    , 0x5800    , 0                      , 0,
21856        0x0                 },        /* P16~*(10) */
21857     { reserved_block      , 0                   , 0   , 16,
21858        0xfc00    , 0x7800    , 0                      , 0,
21859        0x0                 },        /* P16~*(14) */
21860     { branch_instruction  , 0                   , 0   , 16,
21861        0xfc00    , 0x9800    , &BEQZC_16_        , 0,
21862        0x0                 },        /* BEQZC[16] */
21863     { branch_instruction  , 0                   , 0   , 16,
21864        0xfc00    , 0xb800    , &BNEZC_16_        , 0,
21865        0x0                 },        /* BNEZC[16] */
21866     { pool                , P16_BR              , 2   , 16,
21867        0xfc00    , 0xd800    , 0                      , 0,
21868        0x0                 },        /* P16.BR */
21869     { reserved_block      , 0                   , 0   , 16,
21870        0xfc00    , 0xf800    , 0                      , 0,
21871        0x0                 },        /* P16~*(30) */
21872     { pool                , P16_SR              , 2   , 16,
21873        0xfc00    , 0x1c00    , 0                      , 0,
21874        0x0                 },        /* P16.SR */
21875     { pool                , P16_4X4             , 4   , 16,
21876        0xfc00    , 0x3c00    , 0                      , 0,
21877        0x0                 },        /* P16.4X4 */
21878     { pool                , P16_LB              , 4   , 16,
21879        0xfc00    , 0x5c00    , 0                      , 0,
21880        0x0                 },        /* P16.LB */
21881     { pool                , P16_LH              , 4   , 16,
21882        0xfc00    , 0x7c00    , 0                      , 0,
21883        0x0                 },        /* P16.LH */
21884     { reserved_block      , 0                   , 0   , 16,
21885        0xfc00    , 0x9c00    , 0                      , 0,
21886        0x0                 },        /* P16~*(19) */
21887     { instruction         , 0                   , 0   , 16,
21888        0xfc00    , 0xbc00    , &MOVEP            , 0,
21889        XMMS_               },        /* MOVEP */
21890     { reserved_block      , 0                   , 0   , 16,
21891        0xfc00    , 0xdc00    , 0                      , 0,
21892        0x0                 },        /* P16~*(27) */
21893     { instruction         , 0                   , 0   , 16,
21894        0xfc00    , 0xfc00    , &MOVEP_REV_       , 0,
21895        XMMS_               },        /* MOVEP[REV] */
21896 };
21897 
21898 
21899 static const Pool MAJOR[2] = {
21900     { pool                , P32                 , 32  , 32,
21901        0x10000000, 0x00000000, 0                      , 0,
21902        0x0                 },        /* P32 */
21903     { pool                , P16                 , 32  , 16,
21904        0x1000    , 0x1000    , 0                      , 0,
21905        0x0                 },        /* P16 */
21906 };
21907 
21908 static int nanomips_dis(char **buf,
21909                  Dis_info *info,
21910                  unsigned short one,
21911                  unsigned short two,
21912                  unsigned short three)
21913 {
21914     uint16 bits[3] = {one, two, three};
21915 
21916     TABLE_ENTRY_TYPE type;
21917     int size = Disassemble(bits, buf, &type, MAJOR, 2, info);
21918     return size;
21919 }
21920 
21921 int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info)
21922 {
21923     int status;
21924     bfd_byte buffer[2];
21925     uint16_t insn1 = 0, insn2 = 0, insn3 = 0;
21926     g_autofree char *buf = NULL;
21927 
21928     info->bytes_per_chunk = 2;
21929     info->display_endian = info->endian;
21930     info->insn_info_valid = 1;
21931     info->branch_delay_insns = 0;
21932     info->data_size = 0;
21933     info->insn_type = dis_nonbranch;
21934     info->target = 0;
21935     info->target2 = 0;
21936 
21937     Dis_info disassm_info;
21938     disassm_info.m_pc = memaddr;
21939     disassm_info.fprintf_func = info->fprintf_func;
21940     disassm_info.stream = info->stream;
21941 
21942     status = (*info->read_memory_func)(memaddr, buffer, 2, info);
21943     if (status != 0) {
21944         (*info->memory_error_func)(status, memaddr, info);
21945         return -1;
21946     }
21947 
21948     if (info->endian == BFD_ENDIAN_BIG) {
21949         insn1 = bfd_getb16(buffer);
21950     } else {
21951         insn1 = bfd_getl16(buffer);
21952     }
21953     (*info->fprintf_func)(info->stream, "%04x ", insn1);
21954 
21955     /* Handle 32-bit opcodes.  */
21956     if ((insn1 & 0x1000) == 0) {
21957         status = (*info->read_memory_func)(memaddr + 2, buffer, 2, info);
21958         if (status != 0) {
21959             (*info->memory_error_func)(status, memaddr + 2, info);
21960             return -1;
21961         }
21962 
21963         if (info->endian == BFD_ENDIAN_BIG) {
21964             insn2 = bfd_getb16(buffer);
21965         } else {
21966             insn2 = bfd_getl16(buffer);
21967         }
21968         (*info->fprintf_func)(info->stream, "%04x ", insn2);
21969     } else {
21970         (*info->fprintf_func)(info->stream, "     ");
21971     }
21972     /* Handle 48-bit opcodes.  */
21973     if ((insn1 >> 10) == 0x18) {
21974         status = (*info->read_memory_func)(memaddr + 4, buffer, 2, info);
21975         if (status != 0) {
21976             (*info->memory_error_func)(status, memaddr + 4, info);
21977             return -1;
21978         }
21979 
21980         if (info->endian == BFD_ENDIAN_BIG) {
21981             insn3 = bfd_getb16(buffer);
21982         } else {
21983             insn3 = bfd_getl16(buffer);
21984         }
21985         (*info->fprintf_func)(info->stream, "%04x ", insn3);
21986     } else {
21987         (*info->fprintf_func)(info->stream, "     ");
21988     }
21989 
21990     /* Handle runtime errors. */
21991     if (sigsetjmp(disassm_info.buf, 0) != 0) {
21992         info->insn_type = dis_noninsn;
21993         return insn3 ? 6 : insn2 ? 4 : 2;
21994     }
21995 
21996     int length = nanomips_dis(&buf, &disassm_info, insn1, insn2, insn3);
21997 
21998     /* FIXME: Should probably use a hash table on the major opcode here.  */
21999 
22000     (*info->fprintf_func) (info->stream, "%s", buf);
22001     if (length > 0) {
22002         return length / 8;
22003     }
22004 
22005     info->insn_type = dis_noninsn;
22006 
22007     return insn3 ? 6 : insn2 ? 4 : 2;
22008 }
22009