1 /* 2 * Source file for nanoMIPS disassembler component of QEMU 3 * 4 * Copyright (C) 2018 Wave Computing, Inc. 5 * Copyright (C) 2018 Matthew Fortune <matthew.fortune@mips.com> 6 * Copyright (C) 2018 Aleksandar Markovic <amarkovic@wavecomp.com> 7 * 8 * This program is free software: you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation, either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <https://www.gnu.org/licenses/>. 20 * 21 */ 22 23 /* 24 * Documentation used while implementing this component: 25 * 26 * [1] "MIPS® Architecture Base: nanoMIPS32(tm) Instruction Set Technical 27 * Reference Manual", Revision 01.01, April 27, 2018 28 */ 29 30 #include "qemu/osdep.h" 31 #include "disas/dis-asm.h" 32 33 typedef int64_t int64; 34 typedef uint64_t uint64; 35 typedef uint32_t uint32; 36 typedef uint16_t uint16; 37 typedef uint64_t img_address; 38 39 typedef struct Dis_info { 40 img_address m_pc; 41 fprintf_function fprintf_func; 42 FILE *stream; 43 sigjmp_buf buf; 44 } Dis_info; 45 46 #define IMGASSERTONCE(test) 47 48 49 static char * G_GNUC_PRINTF(1, 2) img_format(const char *format, ...) 50 { 51 char *buffer; 52 va_list args; 53 va_start(args, format); 54 buffer = g_strdup_vprintf(format, args); 55 va_end(args); 56 return buffer; 57 } 58 59 60 static char *to_string(img_address a) 61 { 62 return g_strdup_printf("0x%" PRIx64, a); 63 } 64 65 66 static uint64 extract_bits(uint64 data, uint32 bit_offset, uint32 bit_size) 67 { 68 return (data << (64 - (bit_size + bit_offset))) >> (64 - bit_size); 69 } 70 71 72 static int64 sign_extend(int64 data, int msb) 73 { 74 uint64 shift = 63 - msb; 75 return (data << shift) >> shift; 76 } 77 78 79 static uint64 renumber_registers(uint64 index, uint64 *register_list, 80 size_t register_list_size, Dis_info *info) 81 { 82 if (index < register_list_size) { 83 return register_list[index]; 84 } 85 86 info->fprintf_func(info->stream, "Invalid register mapping index %" PRIu64 87 ", size of list = %zu", index, register_list_size); 88 siglongjmp(info->buf, 1); 89 } 90 91 92 /* 93 * decode_gpr_gpr4() - decoder for 'gpr4' gpr encoding type 94 * 95 * Map a 4-bit code to the 5-bit register space according to this pattern: 96 * 97 * 1 0 98 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 99 * | | | | | | | | | | | | | | | | 100 * | | | | | | | | | | | | | | | | 101 * | | | | | | | | | | | └---------------┐ 102 * | | | | | | | | | | └---------------┐ | 103 * | | | | | | | | | └---------------┐ | | 104 * | | | | | | | | └---------------┐ | | | 105 * | | | | | | | | | | | | | | | | 106 * | | | | | | | | | | | | | | | | 107 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 108 * 3 2 1 0 109 * 110 * Used in handling following instructions: 111 * 112 * - ADDU[4X4] 113 * - LW[4X4] 114 * - MOVEP[REV] 115 * - MUL[4X4] 116 * - SW[4X4] 117 */ 118 static uint64 decode_gpr_gpr4(uint64 d, Dis_info *info) 119 { 120 static uint64 register_list[] = { 8, 9, 10, 11, 4, 5, 6, 7, 121 16, 17, 18, 19, 20, 21, 22, 23 }; 122 return renumber_registers(d, register_list, 123 sizeof(register_list) / sizeof(register_list[0]), info); 124 } 125 126 127 /* 128 * decode_gpr_gpr4_zero() - decoder for 'gpr4.zero' gpr encoding type 129 * 130 * Map a 4-bit code to the 5-bit register space according to this pattern: 131 * 132 * 1 0 133 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 134 * | | | | | | | | | | | | | | | | 135 * | | | | | | | | | | | | └---------------------┐ 136 * | | | | | | | | | | | └---------------┐ | 137 * | | | | | | | | | | └---------------┐ | | 138 * | | | | | | | | | └---------------┐ | | | 139 * | | | | | | | | └---------------┐ | | | | 140 * | | | | | | | | | | | | | | | | 141 * | | | | | | | | | | | | | | | | 142 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 143 * 3 2 1 0 144 * 145 * This pattern is the same one used for 'gpr4' gpr encoding type, except for 146 * the input value 3, that is mapped to the output value 0 instead of 11. 147 * 148 * Used in handling following instructions: 149 * 150 * - MOVE.BALC 151 * - MOVEP 152 * - SW[4X4] 153 */ 154 static uint64 decode_gpr_gpr4_zero(uint64 d, Dis_info *info) 155 { 156 static uint64 register_list[] = { 8, 9, 10, 0, 4, 5, 6, 7, 157 16, 17, 18, 19, 20, 21, 22, 23 }; 158 return renumber_registers(d, register_list, 159 sizeof(register_list) / sizeof(register_list[0]), info); 160 } 161 162 163 /* 164 * decode_gpr_gpr3() - decoder for 'gpr3' gpr encoding type 165 * 166 * Map a 3-bit code to the 5-bit register space according to this pattern: 167 * 168 * 7 6 5 4 3 2 1 0 169 * | | | | | | | | 170 * | | | | | | | | 171 * | | | └-----------------------┐ 172 * | | └-----------------------┐ | 173 * | └-----------------------┐ | | 174 * └-----------------------┐ | | | 175 * | | | | | | | | 176 * ┌-------┘ | | | | | | | 177 * | ┌-------┘ | | | | | | 178 * | | ┌-------┘ | | | | | 179 * | | | ┌-------┘ | | | | 180 * | | | | | | | | 181 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 182 * 3 2 1 0 183 * 184 * Used in handling following instructions: 185 * 186 * - ADDIU[R1.SP] 187 * - ADDIU[R2] 188 * - ADDU[16] 189 * - AND[16] 190 * - ANDI[16] 191 * - BEQC[16] 192 * - BEQZC[16] 193 * - BNEC[16] 194 * - BNEZC[16] 195 * - LB[16] 196 * - LBU[16] 197 * - LH[16] 198 * - LHU[16] 199 * - LI[16] 200 * - LW[16] 201 * - LW[GP16] 202 * - LWXS[16] 203 * - NOT[16] 204 * - OR[16] 205 * - SB[16] 206 * - SH[16] 207 * - SLL[16] 208 * - SRL[16] 209 * - SUBU[16] 210 * - SW[16] 211 * - XOR[16] 212 */ 213 static uint64 decode_gpr_gpr3(uint64 d, Dis_info *info) 214 { 215 static uint64 register_list[] = { 16, 17, 18, 19, 4, 5, 6, 7 }; 216 return renumber_registers(d, register_list, 217 sizeof(register_list) / sizeof(register_list[0]), info); 218 } 219 220 221 /* 222 * decode_gpr_gpr3_src_store() - decoder for 'gpr3.src.store' gpr encoding 223 * type 224 * 225 * Map a 3-bit code to the 5-bit register space according to this pattern: 226 * 227 * 7 6 5 4 3 2 1 0 228 * | | | | | | | | 229 * | | | | | | | └-----------------------┐ 230 * | | | └-----------------------┐ | 231 * | | └-----------------------┐ | | 232 * | └-----------------------┐ | | | 233 * └-----------------------┐ | | | | 234 * | | | | | | | | 235 * ┌-------┘ | | | | | | | 236 * | ┌-------┘ | | | | | | 237 * | | ┌-------┘ | | | | | 238 * | | | | | | | | 239 * | | | | | | | | 240 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 241 * 3 2 1 0 242 * 243 * This pattern is the same one used for 'gpr3' gpr encoding type, except for 244 * the input value 0, that is mapped to the output value 0 instead of 16. 245 * 246 * Used in handling following instructions: 247 * 248 * - SB[16] 249 * - SH[16] 250 * - SW[16] 251 * - SW[GP16] 252 */ 253 static uint64 decode_gpr_gpr3_src_store(uint64 d, Dis_info *info) 254 { 255 static uint64 register_list[] = { 0, 17, 18, 19, 4, 5, 6, 7 }; 256 return renumber_registers(d, register_list, 257 sizeof(register_list) / sizeof(register_list[0]), info); 258 } 259 260 261 /* 262 * decode_gpr_gpr2_reg1() - decoder for 'gpr2.reg1' gpr encoding type 263 * 264 * Map a 2-bit code to the 5-bit register space according to this pattern: 265 * 266 * 3 2 1 0 267 * | | | | 268 * | | | | 269 * | | | └-------------------┐ 270 * | | └-------------------┐ | 271 * | └-------------------┐ | | 272 * └-------------------┐ | | | 273 * | | | | 274 * | | | | 275 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 276 * 3 2 1 0 277 * 278 * Used in handling following instructions: 279 * 280 * - MOVEP 281 * - MOVEP[REV] 282 */ 283 static uint64 decode_gpr_gpr2_reg1(uint64 d, Dis_info *info) 284 { 285 static uint64 register_list[] = { 4, 5, 6, 7 }; 286 return renumber_registers(d, register_list, 287 sizeof(register_list) / sizeof(register_list[0]), info); 288 } 289 290 291 /* 292 * decode_gpr_gpr2_reg2() - decoder for 'gpr2.reg2' gpr encoding type 293 * 294 * Map a 2-bit code to the 5-bit register space according to this pattern: 295 * 296 * 3 2 1 0 297 * | | | | 298 * | | | | 299 * | | | └-----------------┐ 300 * | | └-----------------┐ | 301 * | └-----------------┐ | | 302 * └-----------------┐ | | | 303 * | | | | 304 * | | | | 305 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 306 * 3 2 1 0 307 * 308 * Used in handling following instructions: 309 * 310 * - MOVEP 311 * - MOVEP[REV] 312 */ 313 static uint64 decode_gpr_gpr2_reg2(uint64 d, Dis_info *info) 314 { 315 static uint64 register_list[] = { 5, 6, 7, 8 }; 316 return renumber_registers(d, register_list, 317 sizeof(register_list) / sizeof(register_list[0]), info); 318 } 319 320 321 /* 322 * decode_gpr_gpr1() - decoder for 'gpr1' gpr encoding type 323 * 324 * Map a 1-bit code to the 5-bit register space according to this pattern: 325 * 326 * 1 0 327 * | | 328 * | | 329 * | └---------------------┐ 330 * └---------------------┐ | 331 * | | 332 * | | 333 * | | 334 * | | 335 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 336 * 3 2 1 0 337 * 338 * Used in handling following instruction: 339 * 340 * - MOVE.BALC 341 */ 342 static uint64 decode_gpr_gpr1(uint64 d, Dis_info *info) 343 { 344 static uint64 register_list[] = { 4, 5 }; 345 return renumber_registers(d, register_list, 346 sizeof(register_list) / sizeof(register_list[0]), info); 347 } 348 349 350 static int64 neg_copy(uint64 d) 351 { 352 return 0ll - d; 353 } 354 355 356 static uint64 encode_count3_from_count(uint64 d) 357 { 358 IMGASSERTONCE(d < 8); 359 return d == 0ull ? 8ull : d; 360 } 361 362 363 static uint64 encode_shift3_from_shift(uint64 d) 364 { 365 IMGASSERTONCE(d < 8); 366 return d == 0ull ? 8ull : d; 367 } 368 369 370 /* special value for load literal */ 371 static int64 encode_eu_from_s_li16(uint64 d) 372 { 373 IMGASSERTONCE(d < 128); 374 return d == 127 ? -1 : (int64)d; 375 } 376 377 378 static uint64 encode_msbd_from_size(uint64 d) 379 { 380 IMGASSERTONCE(d < 32); 381 return d + 1; 382 } 383 384 385 static uint64 encode_eu_from_u_andi16(uint64 d) 386 { 387 IMGASSERTONCE(d < 16); 388 if (d == 12) { 389 return 0x00ffull; 390 } 391 if (d == 13) { 392 return 0xffffull; 393 } 394 return d; 395 } 396 397 398 /* save16 / restore16 ???? */ 399 static uint64 encode_rt1_from_rt(uint64 d) 400 { 401 return d ? 31 : 30; 402 } 403 404 405 static const char *GPR(uint64 reg, Dis_info *info) 406 { 407 static const char *gpr_reg[32] = { 408 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 409 "a4", "a5", "a6", "a7", "r12", "r13", "r14", "r15", 410 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 411 "r24", "r25", "k0", "k1", "gp", "sp", "fp", "ra" 412 }; 413 414 if (reg < 32) { 415 return gpr_reg[reg]; 416 } 417 418 info->fprintf_func(info->stream, "Invalid GPR register index %" PRIu64, 419 reg); 420 siglongjmp(info->buf, 1); 421 } 422 423 424 static char *save_restore_list(uint64 rt, uint64 count, uint64 gp, 425 Dis_info *info) 426 { 427 char *reg_list[34]; 428 reg_list[0] = (char *)""; 429 430 assert(count <= 32); 431 for (uint64 counter = 0; counter != count; counter++) { 432 bool use_gp = gp && (counter == count - 1); 433 uint64 this_rt = use_gp ? 28 : ((rt & 0x10) | (rt + counter)) & 0x1f; 434 /* glib usage below requires casting away const */ 435 reg_list[counter + 1] = (char *)GPR(this_rt, info); 436 } 437 reg_list[count + 1] = NULL; 438 439 return g_strjoinv(",", reg_list); 440 } 441 442 443 static const char *FPR(uint64 reg, Dis_info *info) 444 { 445 static const char *fpr_reg[32] = { 446 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 447 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 448 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 449 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" 450 }; 451 452 if (reg < 32) { 453 return fpr_reg[reg]; 454 } 455 456 info->fprintf_func(info->stream, "Invalid FPR register index %" PRIu64, 457 reg); 458 siglongjmp(info->buf, 1); 459 } 460 461 462 static const char *AC(uint64 reg, Dis_info *info) 463 { 464 static const char *ac_reg[4] = { 465 "ac0", "ac1", "ac2", "ac3" 466 }; 467 468 if (reg < 4) { 469 return ac_reg[reg]; 470 } 471 472 info->fprintf_func(info->stream, "Invalid AC register index %" PRIu64, 473 reg); 474 siglongjmp(info->buf, 1); 475 } 476 477 478 static char *ADDRESS(uint64 value, int instruction_size, Dis_info *info) 479 { 480 /* token for string replace */ 481 img_address address = info->m_pc + value + instruction_size; 482 /* symbol replacement */ 483 return to_string(address); 484 } 485 486 487 static uint64 extract_op_code_value(const uint16 *data, int size) 488 { 489 switch (size) { 490 case 16: 491 return data[0]; 492 case 32: 493 return ((uint64)data[0] << 16) | data[1]; 494 case 48: 495 return ((uint64)data[0] << 32) | ((uint64)data[1] << 16) | data[2]; 496 default: 497 return data[0]; 498 } 499 } 500 501 502 static uint64 extract_code_18_to_0(uint64 instruction) 503 { 504 uint64 value = 0; 505 value |= extract_bits(instruction, 0, 19); 506 return value; 507 } 508 509 510 static uint64 extract_shift3_2_1_0(uint64 instruction) 511 { 512 uint64 value = 0; 513 value |= extract_bits(instruction, 0, 3); 514 return value; 515 } 516 517 518 static uint64 extract_u_11_10_9_8_7_6_5_4_3__s3(uint64 instruction) 519 { 520 uint64 value = 0; 521 value |= extract_bits(instruction, 3, 9) << 3; 522 return value; 523 } 524 525 526 static uint64 extract_count_3_2_1_0(uint64 instruction) 527 { 528 uint64 value = 0; 529 value |= extract_bits(instruction, 0, 4); 530 return value; 531 } 532 533 534 static uint64 extract_rtz3_9_8_7(uint64 instruction) 535 { 536 uint64 value = 0; 537 value |= extract_bits(instruction, 7, 3); 538 return value; 539 } 540 541 542 static uint64 extract_u_17_to_1__s1(uint64 instruction) 543 { 544 uint64 value = 0; 545 value |= extract_bits(instruction, 1, 17) << 1; 546 return value; 547 } 548 549 550 static int64 extract_s__se9_20_19_18_17_16_15_14_13_12_11(uint64 instruction) 551 { 552 int64 value = 0; 553 value |= extract_bits(instruction, 11, 10); 554 value = sign_extend(value, 9); 555 return value; 556 } 557 558 559 static int64 extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(uint64 instruction) 560 { 561 int64 value = 0; 562 value |= extract_bits(instruction, 0, 1) << 11; 563 value |= extract_bits(instruction, 1, 10) << 1; 564 value = sign_extend(value, 11); 565 return value; 566 } 567 568 569 static uint64 extract_u_10(uint64 instruction) 570 { 571 uint64 value = 0; 572 value |= extract_bits(instruction, 10, 1); 573 return value; 574 } 575 576 577 static uint64 extract_rtz4_27_26_25_23_22_21(uint64 instruction) 578 { 579 uint64 value = 0; 580 value |= extract_bits(instruction, 21, 3); 581 value |= extract_bits(instruction, 25, 1) << 3; 582 return value; 583 } 584 585 586 static uint64 extract_sa_15_14_13_12_11(uint64 instruction) 587 { 588 uint64 value = 0; 589 value |= extract_bits(instruction, 11, 5); 590 return value; 591 } 592 593 594 static uint64 extract_shift_4_3_2_1_0(uint64 instruction) 595 { 596 uint64 value = 0; 597 value |= extract_bits(instruction, 0, 5); 598 return value; 599 } 600 601 602 static uint64 extract_shiftx_10_9_8_7__s1(uint64 instruction) 603 { 604 uint64 value = 0; 605 value |= extract_bits(instruction, 7, 4) << 1; 606 return value; 607 } 608 609 610 static uint64 extract_hint_25_24_23_22_21(uint64 instruction) 611 { 612 uint64 value = 0; 613 value |= extract_bits(instruction, 21, 5); 614 return value; 615 } 616 617 618 static uint64 extract_count3_14_13_12(uint64 instruction) 619 { 620 uint64 value = 0; 621 value |= extract_bits(instruction, 12, 3); 622 return value; 623 } 624 625 626 static int64 extract_s__se31_0_11_to_2_20_to_12_s12(uint64 instruction) 627 { 628 int64 value = 0; 629 value |= extract_bits(instruction, 0, 1) << 31; 630 value |= extract_bits(instruction, 2, 10) << 21; 631 value |= extract_bits(instruction, 12, 9) << 12; 632 value = sign_extend(value, 31); 633 return value; 634 } 635 636 637 static int64 extract_s__se7_0_6_5_4_3_2_1_s1(uint64 instruction) 638 { 639 int64 value = 0; 640 value |= extract_bits(instruction, 0, 1) << 7; 641 value |= extract_bits(instruction, 1, 6) << 1; 642 value = sign_extend(value, 7); 643 return value; 644 } 645 646 647 static uint64 extract_u2_10_9(uint64 instruction) 648 { 649 uint64 value = 0; 650 value |= extract_bits(instruction, 9, 2); 651 return value; 652 } 653 654 655 static uint64 extract_code_25_24_23_22_21_20_19_18_17_16(uint64 instruction) 656 { 657 uint64 value = 0; 658 value |= extract_bits(instruction, 16, 10); 659 return value; 660 } 661 662 663 static uint64 extract_rs_20_19_18_17_16(uint64 instruction) 664 { 665 uint64 value = 0; 666 value |= extract_bits(instruction, 16, 5); 667 return value; 668 } 669 670 671 static uint64 extract_u_2_1__s1(uint64 instruction) 672 { 673 uint64 value = 0; 674 value |= extract_bits(instruction, 1, 2) << 1; 675 return value; 676 } 677 678 679 static uint64 extract_stripe_6(uint64 instruction) 680 { 681 uint64 value = 0; 682 value |= extract_bits(instruction, 6, 1); 683 return value; 684 } 685 686 687 static uint64 extract_ac_15_14(uint64 instruction) 688 { 689 uint64 value = 0; 690 value |= extract_bits(instruction, 14, 2); 691 return value; 692 } 693 694 695 static uint64 extract_shift_20_19_18_17_16(uint64 instruction) 696 { 697 uint64 value = 0; 698 value |= extract_bits(instruction, 16, 5); 699 return value; 700 } 701 702 703 static uint64 extract_rdl_25_24(uint64 instruction) 704 { 705 uint64 value = 0; 706 value |= extract_bits(instruction, 24, 1); 707 return value; 708 } 709 710 711 static int64 extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(uint64 instruction) 712 { 713 int64 value = 0; 714 value |= extract_bits(instruction, 0, 1) << 10; 715 value |= extract_bits(instruction, 1, 9) << 1; 716 value = sign_extend(value, 10); 717 return value; 718 } 719 720 721 static uint64 extract_eu_6_5_4_3_2_1_0(uint64 instruction) 722 { 723 uint64 value = 0; 724 value |= extract_bits(instruction, 0, 7); 725 return value; 726 } 727 728 729 static uint64 extract_shift_5_4_3_2_1_0(uint64 instruction) 730 { 731 uint64 value = 0; 732 value |= extract_bits(instruction, 0, 6); 733 return value; 734 } 735 736 737 static uint64 extract_count_19_18_17_16(uint64 instruction) 738 { 739 uint64 value = 0; 740 value |= extract_bits(instruction, 16, 4); 741 return value; 742 } 743 744 745 static uint64 extract_code_2_1_0(uint64 instruction) 746 { 747 uint64 value = 0; 748 value |= extract_bits(instruction, 0, 3); 749 return value; 750 } 751 752 753 static uint64 extract_u_11_10_9_8_7_6_5_4_3_2_1_0(uint64 instruction) 754 { 755 uint64 value = 0; 756 value |= extract_bits(instruction, 0, 12); 757 return value; 758 } 759 760 761 static uint64 extract_rs_4_3_2_1_0(uint64 instruction) 762 { 763 uint64 value = 0; 764 value |= extract_bits(instruction, 0, 5); 765 return value; 766 } 767 768 769 static uint64 extract_u_20_to_3__s3(uint64 instruction) 770 { 771 uint64 value = 0; 772 value |= extract_bits(instruction, 3, 18) << 3; 773 return value; 774 } 775 776 777 static uint64 extract_u_3_2_1_0__s2(uint64 instruction) 778 { 779 uint64 value = 0; 780 value |= extract_bits(instruction, 0, 4) << 2; 781 return value; 782 } 783 784 785 static uint64 extract_cofun_25_24_23(uint64 instruction) 786 { 787 uint64 value = 0; 788 value |= extract_bits(instruction, 3, 23); 789 return value; 790 } 791 792 793 static uint64 extract_u_2_1_0__s2(uint64 instruction) 794 { 795 uint64 value = 0; 796 value |= extract_bits(instruction, 0, 3) << 2; 797 return value; 798 } 799 800 801 static uint64 extract_rd3_3_2_1(uint64 instruction) 802 { 803 uint64 value = 0; 804 value |= extract_bits(instruction, 1, 3); 805 return value; 806 } 807 808 809 static uint64 extract_sa_15_14_13_12(uint64 instruction) 810 { 811 uint64 value = 0; 812 value |= extract_bits(instruction, 12, 4); 813 return value; 814 } 815 816 817 static uint64 extract_rt_25_24_23_22_21(uint64 instruction) 818 { 819 uint64 value = 0; 820 value |= extract_bits(instruction, 21, 5); 821 return value; 822 } 823 824 825 static uint64 extract_ru_7_6_5_4_3(uint64 instruction) 826 { 827 uint64 value = 0; 828 value |= extract_bits(instruction, 3, 5); 829 return value; 830 } 831 832 833 static uint64 extract_u_17_to_0(uint64 instruction) 834 { 835 uint64 value = 0; 836 value |= extract_bits(instruction, 0, 18); 837 return value; 838 } 839 840 841 static uint64 extract_rsz4_4_2_1_0(uint64 instruction) 842 { 843 uint64 value = 0; 844 value |= extract_bits(instruction, 0, 3); 845 value |= extract_bits(instruction, 4, 1) << 3; 846 return value; 847 } 848 849 850 static int64 extract_s__se21_0_20_to_1_s1(uint64 instruction) 851 { 852 int64 value = 0; 853 value |= extract_bits(instruction, 0, 1) << 21; 854 value |= extract_bits(instruction, 1, 20) << 1; 855 value = sign_extend(value, 21); 856 return value; 857 } 858 859 860 static uint64 extract_op_25_to_3(uint64 instruction) 861 { 862 uint64 value = 0; 863 value |= extract_bits(instruction, 3, 23); 864 return value; 865 } 866 867 868 static uint64 extract_rs4_4_2_1_0(uint64 instruction) 869 { 870 uint64 value = 0; 871 value |= extract_bits(instruction, 0, 3); 872 value |= extract_bits(instruction, 4, 1) << 3; 873 return value; 874 } 875 876 877 static uint64 extract_bit_23_22_21(uint64 instruction) 878 { 879 uint64 value = 0; 880 value |= extract_bits(instruction, 21, 3); 881 return value; 882 } 883 884 885 static uint64 extract_rt_41_40_39_38_37(uint64 instruction) 886 { 887 uint64 value = 0; 888 value |= extract_bits(instruction, 37, 5); 889 return value; 890 } 891 892 893 static int64 extract_shift__se5_21_20_19_18_17_16(uint64 instruction) 894 { 895 int64 value = 0; 896 value |= extract_bits(instruction, 16, 6); 897 value = sign_extend(value, 5); 898 return value; 899 } 900 901 902 static uint64 extract_rd2_3_8(uint64 instruction) 903 { 904 uint64 value = 0; 905 value |= extract_bits(instruction, 3, 1) << 1; 906 value |= extract_bits(instruction, 8, 1); 907 return value; 908 } 909 910 911 static uint64 extract_code_17_to_0(uint64 instruction) 912 { 913 uint64 value = 0; 914 value |= extract_bits(instruction, 0, 18); 915 return value; 916 } 917 918 919 static uint64 extract_size_20_19_18_17_16(uint64 instruction) 920 { 921 uint64 value = 0; 922 value |= extract_bits(instruction, 16, 5); 923 return value; 924 } 925 926 927 static int64 extract_s__se8_15_7_6_5_4_3_2_s2(uint64 instruction) 928 { 929 int64 value = 0; 930 value |= extract_bits(instruction, 2, 6) << 2; 931 value |= extract_bits(instruction, 15, 1) << 8; 932 value = sign_extend(value, 8); 933 return value; 934 } 935 936 937 static uint64 extract_u_15_to_0(uint64 instruction) 938 { 939 uint64 value = 0; 940 value |= extract_bits(instruction, 0, 16); 941 return value; 942 } 943 944 945 static uint64 extract_fs_20_19_18_17_16(uint64 instruction) 946 { 947 uint64 value = 0; 948 value |= extract_bits(instruction, 16, 5); 949 return value; 950 } 951 952 953 static int64 extract_s__se8_15_7_6_5_4_3_2_1_0(uint64 instruction) 954 { 955 int64 value = 0; 956 value |= extract_bits(instruction, 0, 8); 957 value |= extract_bits(instruction, 15, 1) << 8; 958 value = sign_extend(value, 8); 959 return value; 960 } 961 962 963 static uint64 extract_stype_20_19_18_17_16(uint64 instruction) 964 { 965 uint64 value = 0; 966 value |= extract_bits(instruction, 16, 5); 967 return value; 968 } 969 970 971 static uint64 extract_rtl_11(uint64 instruction) 972 { 973 uint64 value = 0; 974 value |= extract_bits(instruction, 9, 1); 975 return value; 976 } 977 978 979 static uint64 extract_hs_20_19_18_17_16(uint64 instruction) 980 { 981 uint64 value = 0; 982 value |= extract_bits(instruction, 16, 5); 983 return value; 984 } 985 986 987 static uint64 extract_sel_13_12_11(uint64 instruction) 988 { 989 uint64 value = 0; 990 value |= extract_bits(instruction, 11, 3); 991 return value; 992 } 993 994 995 static uint64 extract_lsb_4_3_2_1_0(uint64 instruction) 996 { 997 uint64 value = 0; 998 value |= extract_bits(instruction, 0, 5); 999 return value; 1000 } 1001 1002 1003 static uint64 extract_gp_2(uint64 instruction) 1004 { 1005 uint64 value = 0; 1006 value |= extract_bits(instruction, 2, 1); 1007 return value; 1008 } 1009 1010 1011 static uint64 extract_rt3_9_8_7(uint64 instruction) 1012 { 1013 uint64 value = 0; 1014 value |= extract_bits(instruction, 7, 3); 1015 return value; 1016 } 1017 1018 1019 static uint64 extract_ft_25_24_23_22_21(uint64 instruction) 1020 { 1021 uint64 value = 0; 1022 value |= extract_bits(instruction, 21, 5); 1023 return value; 1024 } 1025 1026 1027 static uint64 extract_u_17_16_15_14_13_12_11(uint64 instruction) 1028 { 1029 uint64 value = 0; 1030 value |= extract_bits(instruction, 11, 7); 1031 return value; 1032 } 1033 1034 1035 static uint64 extract_cs_20_19_18_17_16(uint64 instruction) 1036 { 1037 uint64 value = 0; 1038 value |= extract_bits(instruction, 16, 5); 1039 return value; 1040 } 1041 1042 1043 static uint64 extract_rt4_9_7_6_5(uint64 instruction) 1044 { 1045 uint64 value = 0; 1046 value |= extract_bits(instruction, 5, 3); 1047 value |= extract_bits(instruction, 9, 1) << 3; 1048 return value; 1049 } 1050 1051 1052 static uint64 extract_msbt_10_9_8_7_6(uint64 instruction) 1053 { 1054 uint64 value = 0; 1055 value |= extract_bits(instruction, 6, 5); 1056 return value; 1057 } 1058 1059 1060 static uint64 extract_u_5_4_3_2_1_0__s2(uint64 instruction) 1061 { 1062 uint64 value = 0; 1063 value |= extract_bits(instruction, 0, 6) << 2; 1064 return value; 1065 } 1066 1067 1068 static uint64 extract_sa_15_14_13(uint64 instruction) 1069 { 1070 uint64 value = 0; 1071 value |= extract_bits(instruction, 13, 3); 1072 return value; 1073 } 1074 1075 1076 static int64 extract_s__se14_0_13_to_1_s1(uint64 instruction) 1077 { 1078 int64 value = 0; 1079 value |= extract_bits(instruction, 0, 1) << 14; 1080 value |= extract_bits(instruction, 1, 13) << 1; 1081 value = sign_extend(value, 14); 1082 return value; 1083 } 1084 1085 1086 static uint64 extract_rs3_6_5_4(uint64 instruction) 1087 { 1088 uint64 value = 0; 1089 value |= extract_bits(instruction, 4, 3); 1090 return value; 1091 } 1092 1093 1094 static uint64 extract_u_31_to_0__s32(uint64 instruction) 1095 { 1096 uint64 value = 0; 1097 value |= extract_bits(instruction, 0, 32) << 32; 1098 return value; 1099 } 1100 1101 1102 static uint64 extract_shift_10_9_8_7_6(uint64 instruction) 1103 { 1104 uint64 value = 0; 1105 value |= extract_bits(instruction, 6, 5); 1106 return value; 1107 } 1108 1109 1110 static uint64 extract_cs_25_24_23_22_21(uint64 instruction) 1111 { 1112 uint64 value = 0; 1113 value |= extract_bits(instruction, 21, 5); 1114 return value; 1115 } 1116 1117 1118 static uint64 extract_shiftx_11_10_9_8_7_6(uint64 instruction) 1119 { 1120 uint64 value = 0; 1121 value |= extract_bits(instruction, 6, 6); 1122 return value; 1123 } 1124 1125 1126 static uint64 extract_rt_9_8_7_6_5(uint64 instruction) 1127 { 1128 uint64 value = 0; 1129 value |= extract_bits(instruction, 5, 5); 1130 return value; 1131 } 1132 1133 1134 static uint64 extract_op_25_24_23_22_21(uint64 instruction) 1135 { 1136 uint64 value = 0; 1137 value |= extract_bits(instruction, 21, 5); 1138 return value; 1139 } 1140 1141 1142 static uint64 extract_u_6_5_4_3_2_1_0__s2(uint64 instruction) 1143 { 1144 uint64 value = 0; 1145 value |= extract_bits(instruction, 0, 7) << 2; 1146 return value; 1147 } 1148 1149 1150 static uint64 extract_bit_16_15_14_13_12_11(uint64 instruction) 1151 { 1152 uint64 value = 0; 1153 value |= extract_bits(instruction, 11, 6); 1154 return value; 1155 } 1156 1157 1158 static uint64 extract_mask_20_19_18_17_16_15_14(uint64 instruction) 1159 { 1160 uint64 value = 0; 1161 value |= extract_bits(instruction, 14, 7); 1162 return value; 1163 } 1164 1165 1166 static uint64 extract_eu_3_2_1_0(uint64 instruction) 1167 { 1168 uint64 value = 0; 1169 value |= extract_bits(instruction, 0, 4); 1170 return value; 1171 } 1172 1173 1174 static uint64 extract_u_7_6_5_4__s4(uint64 instruction) 1175 { 1176 uint64 value = 0; 1177 value |= extract_bits(instruction, 4, 4) << 4; 1178 return value; 1179 } 1180 1181 1182 static int64 extract_s__se8_15_7_6_5_4_3_s3(uint64 instruction) 1183 { 1184 int64 value = 0; 1185 value |= extract_bits(instruction, 3, 5) << 3; 1186 value |= extract_bits(instruction, 15, 1) << 8; 1187 value = sign_extend(value, 8); 1188 return value; 1189 } 1190 1191 1192 static uint64 extract_ft_15_14_13_12_11(uint64 instruction) 1193 { 1194 uint64 value = 0; 1195 value |= extract_bits(instruction, 11, 5); 1196 return value; 1197 } 1198 1199 1200 static int64 extract_s__se31_15_to_0_31_to_16(uint64 instruction) 1201 { 1202 int64 value = 0; 1203 value |= extract_bits(instruction, 0, 16) << 16; 1204 value |= extract_bits(instruction, 16, 16); 1205 value = sign_extend(value, 31); 1206 return value; 1207 } 1208 1209 1210 static uint64 extract_u_20_19_18_17_16_15_14_13(uint64 instruction) 1211 { 1212 uint64 value = 0; 1213 value |= extract_bits(instruction, 13, 8); 1214 return value; 1215 } 1216 1217 1218 static uint64 extract_u_17_to_2__s2(uint64 instruction) 1219 { 1220 uint64 value = 0; 1221 value |= extract_bits(instruction, 2, 16) << 2; 1222 return value; 1223 } 1224 1225 1226 static uint64 extract_rd_15_14_13_12_11(uint64 instruction) 1227 { 1228 uint64 value = 0; 1229 value |= extract_bits(instruction, 11, 5); 1230 return value; 1231 } 1232 1233 1234 static uint64 extract_c0s_20_19_18_17_16(uint64 instruction) 1235 { 1236 uint64 value = 0; 1237 value |= extract_bits(instruction, 16, 5); 1238 return value; 1239 } 1240 1241 1242 static uint64 extract_code_1_0(uint64 instruction) 1243 { 1244 uint64 value = 0; 1245 value |= extract_bits(instruction, 0, 2); 1246 return value; 1247 } 1248 1249 1250 static int64 extract_s__se25_0_24_to_1_s1(uint64 instruction) 1251 { 1252 int64 value = 0; 1253 value |= extract_bits(instruction, 0, 1) << 25; 1254 value |= extract_bits(instruction, 1, 24) << 1; 1255 value = sign_extend(value, 25); 1256 return value; 1257 } 1258 1259 1260 static uint64 extract_u_1_0(uint64 instruction) 1261 { 1262 uint64 value = 0; 1263 value |= extract_bits(instruction, 0, 2); 1264 return value; 1265 } 1266 1267 1268 static uint64 extract_u_3_8__s2(uint64 instruction) 1269 { 1270 uint64 value = 0; 1271 value |= extract_bits(instruction, 3, 1) << 3; 1272 value |= extract_bits(instruction, 8, 1) << 2; 1273 return value; 1274 } 1275 1276 1277 static uint64 extract_fd_15_14_13_12_11(uint64 instruction) 1278 { 1279 uint64 value = 0; 1280 value |= extract_bits(instruction, 11, 5); 1281 return value; 1282 } 1283 1284 1285 static uint64 extract_u_4_3_2_1_0__s2(uint64 instruction) 1286 { 1287 uint64 value = 0; 1288 value |= extract_bits(instruction, 0, 5) << 2; 1289 return value; 1290 } 1291 1292 1293 static uint64 extract_rtz4_9_7_6_5(uint64 instruction) 1294 { 1295 uint64 value = 0; 1296 value |= extract_bits(instruction, 5, 3); 1297 value |= extract_bits(instruction, 9, 1) << 3; 1298 return value; 1299 } 1300 1301 1302 static uint64 extract_sel_15_14_13_12_11(uint64 instruction) 1303 { 1304 uint64 value = 0; 1305 value |= extract_bits(instruction, 11, 5); 1306 return value; 1307 } 1308 1309 1310 static uint64 extract_ct_25_24_23_22_21(uint64 instruction) 1311 { 1312 uint64 value = 0; 1313 value |= extract_bits(instruction, 21, 5); 1314 return value; 1315 } 1316 1317 1318 static uint64 extract_u_20_to_2__s2(uint64 instruction) 1319 { 1320 uint64 value = 0; 1321 value |= extract_bits(instruction, 2, 19) << 2; 1322 return value; 1323 } 1324 1325 1326 static int64 extract_s__se3_4_2_1_0(uint64 instruction) 1327 { 1328 int64 value = 0; 1329 value |= extract_bits(instruction, 0, 3); 1330 value |= extract_bits(instruction, 4, 1) << 3; 1331 value = sign_extend(value, 3); 1332 return value; 1333 } 1334 1335 1336 static uint64 extract_u_3_2_1_0__s1(uint64 instruction) 1337 { 1338 uint64 value = 0; 1339 value |= extract_bits(instruction, 0, 4) << 1; 1340 return value; 1341 } 1342 1343 1344 1345 static bool ADDIU_32__cond(uint64 instruction) 1346 { 1347 uint64 rt = extract_rt_25_24_23_22_21(instruction); 1348 return rt != 0; 1349 } 1350 1351 1352 static bool ADDIU_RS5__cond(uint64 instruction) 1353 { 1354 uint64 rt = extract_rt_9_8_7_6_5(instruction); 1355 return rt != 0; 1356 } 1357 1358 1359 static bool BALRSC_cond(uint64 instruction) 1360 { 1361 uint64 rt = extract_rt_25_24_23_22_21(instruction); 1362 return rt != 0; 1363 } 1364 1365 1366 static bool BEQC_16__cond(uint64 instruction) 1367 { 1368 uint64 rs3 = extract_rs3_6_5_4(instruction); 1369 uint64 rt3 = extract_rt3_9_8_7(instruction); 1370 uint64 u = extract_u_3_2_1_0__s1(instruction); 1371 return rs3 < rt3 && u != 0; 1372 } 1373 1374 1375 static bool BNEC_16__cond(uint64 instruction) 1376 { 1377 uint64 rs3 = extract_rs3_6_5_4(instruction); 1378 uint64 rt3 = extract_rt3_9_8_7(instruction); 1379 uint64 u = extract_u_3_2_1_0__s1(instruction); 1380 return rs3 >= rt3 && u != 0; 1381 } 1382 1383 1384 static bool MOVE_cond(uint64 instruction) 1385 { 1386 uint64 rt = extract_rt_9_8_7_6_5(instruction); 1387 return rt != 0; 1388 } 1389 1390 1391 static bool P16_BR1_cond(uint64 instruction) 1392 { 1393 uint64 u = extract_u_3_2_1_0__s1(instruction); 1394 return u != 0; 1395 } 1396 1397 1398 static bool PREF_S9__cond(uint64 instruction) 1399 { 1400 uint64 hint = extract_hint_25_24_23_22_21(instruction); 1401 return hint != 31; 1402 } 1403 1404 1405 static bool PREFE_cond(uint64 instruction) 1406 { 1407 uint64 hint = extract_hint_25_24_23_22_21(instruction); 1408 return hint != 31; 1409 } 1410 1411 1412 static bool SLTU_cond(uint64 instruction) 1413 { 1414 uint64 rd = extract_rd_15_14_13_12_11(instruction); 1415 return rd != 0; 1416 } 1417 1418 1419 1420 /* 1421 * ABS.D fd, fs - Floating Point Absolute Value 1422 * 1423 * 3 2 1 1424 * 10987654321098765432109876543210 1425 * 010001 00000 000101 1426 * fmt ----- 1427 * fs ----- 1428 * fd ----- 1429 */ 1430 static char *ABS_D(uint64 instruction, Dis_info *info) 1431 { 1432 uint64 fd_value = extract_ft_25_24_23_22_21(instruction); 1433 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 1434 1435 const char *fs = FPR(fs_value, info); 1436 const char *fd = FPR(fd_value, info); 1437 1438 return img_format("ABS.D %s, %s", fd, fs); 1439 } 1440 1441 1442 /* 1443 * ABS.S fd, fs - Floating Point Absolute Value 1444 * 1445 * 3 2 1 1446 * 10987654321098765432109876543210 1447 * 010001 00000 000101 1448 * fmt ----- 1449 * fd ----- 1450 * fs ----- 1451 */ 1452 static char *ABS_S(uint64 instruction, Dis_info *info) 1453 { 1454 uint64 fd_value = extract_ft_25_24_23_22_21(instruction); 1455 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 1456 1457 const char *fs = FPR(fs_value, info); 1458 const char *fd = FPR(fd_value, info); 1459 1460 return img_format("ABS.S %s, %s", fd, fs); 1461 } 1462 1463 1464 /* 1465 * [DSP] ABSQ_S.PH rt, rs - Find absolute value of two fractional halfwords 1466 * with 16-bit saturation 1467 * 1468 * 3 2 1 1469 * 10987654321098765432109876543210 1470 * 001000 0001000100111111 1471 * rt ----- 1472 * rs ----- 1473 */ 1474 static char *ABSQ_S_PH(uint64 instruction, Dis_info *info) 1475 { 1476 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1477 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1478 1479 const char *rt = GPR(rt_value, info); 1480 const char *rs = GPR(rs_value, info); 1481 1482 return img_format("ABSQ_S.PH %s, %s", rt, rs); 1483 } 1484 1485 1486 /* 1487 * [DSP] ABSQ_S.QB rt, rs - Find absolute value of four fractional byte values 1488 * with 8-bit saturation 1489 * 1490 * 3 2 1 1491 * 10987654321098765432109876543210 1492 * 001000 0000000100111111 1493 * rt ----- 1494 * rs ----- 1495 */ 1496 static char *ABSQ_S_QB(uint64 instruction, Dis_info *info) 1497 { 1498 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1499 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1500 1501 const char *rt = GPR(rt_value, info); 1502 const char *rs = GPR(rs_value, info); 1503 1504 return img_format("ABSQ_S.QB %s, %s", rt, rs); 1505 } 1506 1507 1508 /* 1509 * [DSP] ABSQ_S.W rt, rs - Find absolute value of fractional word with 32-bit 1510 * saturation 1511 * 1512 * 3 2 1 1513 * 10987654321098765432109876543210 1514 * 001000 0010000100111111 1515 * rt ----- 1516 * rs ----- 1517 */ 1518 static char *ABSQ_S_W(uint64 instruction, Dis_info *info) 1519 { 1520 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1521 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1522 1523 const char *rt = GPR(rt_value, info); 1524 const char *rs = GPR(rs_value, info); 1525 1526 return img_format("ABSQ_S.W %s, %s", rt, rs); 1527 } 1528 1529 1530 /* 1531 * 1532 * 1533 * 3 2 1 1534 * 10987654321098765432109876543210 1535 * 001000 0010000100111111 1536 * rt ----- 1537 * rs ----- 1538 */ 1539 static char *ACLR(uint64 instruction, Dis_info *info) 1540 { 1541 uint64 bit_value = extract_bit_23_22_21(instruction); 1542 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1543 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 1544 1545 const char *rs = GPR(rs_value, info); 1546 1547 return img_format("ACLR 0x%" PRIx64 ", %" PRId64 "(%s)", 1548 bit_value, s_value, rs); 1549 } 1550 1551 1552 /* 1553 * 1554 * 1555 * 3 2 1 1556 * 10987654321098765432109876543210 1557 * 001000 0010000100111111 1558 * rt ----- 1559 * rs ----- 1560 */ 1561 static char *ADD(uint64 instruction, Dis_info *info) 1562 { 1563 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1564 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1565 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 1566 1567 const char *rd = GPR(rd_value, info); 1568 const char *rs = GPR(rs_value, info); 1569 const char *rt = GPR(rt_value, info); 1570 1571 return img_format("ADD %s, %s, %s", rd, rs, rt); 1572 } 1573 1574 1575 /* 1576 * ADD.D fd, fs, ft - Floating Point Add 1577 * 1578 * 3 2 1 1579 * 10987654321098765432109876543210 1580 * 010001 000101 1581 * fmt ----- 1582 * ft ----- 1583 * fs ----- 1584 * fd ----- 1585 */ 1586 static char *ADD_D(uint64 instruction, Dis_info *info) 1587 { 1588 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 1589 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 1590 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 1591 1592 const char *ft = FPR(ft_value, info); 1593 const char *fs = FPR(fs_value, info); 1594 const char *fd = FPR(fd_value, info); 1595 1596 return img_format("ADD.D %s, %s, %s", fd, fs, ft); 1597 } 1598 1599 1600 /* 1601 * ADD.S fd, fs, ft - Floating Point Add 1602 * 1603 * 3 2 1 1604 * 10987654321098765432109876543210 1605 * 010001 000101 1606 * fmt ----- 1607 * ft ----- 1608 * fs ----- 1609 * fd ----- 1610 */ 1611 static char *ADD_S(uint64 instruction, Dis_info *info) 1612 { 1613 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 1614 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 1615 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 1616 1617 const char *ft = FPR(ft_value, info); 1618 const char *fs = FPR(fs_value, info); 1619 const char *fd = FPR(fd_value, info); 1620 1621 return img_format("ADD.S %s, %s, %s", fd, fs, ft); 1622 } 1623 1624 1625 /* 1626 * 1627 * 1628 * 3 2 1 1629 * 10987654321098765432109876543210 1630 * 001000 0010000100111111 1631 * rt ----- 1632 * rs ----- 1633 */ 1634 static char *ADDIU_32_(uint64 instruction, Dis_info *info) 1635 { 1636 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1637 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1638 uint64 u_value = extract_u_15_to_0(instruction); 1639 1640 const char *rt = GPR(rt_value, info); 1641 const char *rs = GPR(rs_value, info); 1642 1643 return img_format("ADDIU %s, %s, 0x%" PRIx64, rt, rs, u_value); 1644 } 1645 1646 1647 /* 1648 * 1649 * 1650 * 3 2 1 1651 * 10987654321098765432109876543210 1652 * 001000 0010000100111111 1653 * rt ----- 1654 * rs ----- 1655 */ 1656 static char *ADDIU_48_(uint64 instruction, Dis_info *info) 1657 { 1658 uint64 rt_value = extract_rt_41_40_39_38_37(instruction); 1659 int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); 1660 1661 const char *rt = GPR(rt_value, info); 1662 1663 return img_format("ADDIU %s, %" PRId64, rt, s_value); 1664 } 1665 1666 1667 /* 1668 * 1669 * 1670 * 3 2 1 1671 * 10987654321098765432109876543210 1672 * 001000 0010000100111111 1673 * rt ----- 1674 * rs ----- 1675 */ 1676 static char *ADDIU_GP48_(uint64 instruction, Dis_info *info) 1677 { 1678 uint64 rt_value = extract_rt_41_40_39_38_37(instruction); 1679 int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); 1680 1681 const char *rt = GPR(rt_value, info); 1682 1683 return img_format("ADDIU %s, $%d, %" PRId64, rt, 28, s_value); 1684 } 1685 1686 1687 /* 1688 * 1689 * 1690 * 3 2 1 1691 * 10987654321098765432109876543210 1692 * 001000 0010000100111111 1693 * rt ----- 1694 * rs ----- 1695 */ 1696 static char *ADDIU_GP_B_(uint64 instruction, Dis_info *info) 1697 { 1698 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1699 uint64 u_value = extract_u_17_to_0(instruction); 1700 1701 const char *rt = GPR(rt_value, info); 1702 1703 return img_format("ADDIU %s, $%d, 0x%" PRIx64, rt, 28, u_value); 1704 } 1705 1706 1707 /* 1708 * 1709 * 1710 * 3 2 1 1711 * 10987654321098765432109876543210 1712 * 001000 0010000100111111 1713 * rt ----- 1714 * rs ----- 1715 */ 1716 static char *ADDIU_GP_W_(uint64 instruction, Dis_info *info) 1717 { 1718 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1719 uint64 u_value = extract_u_20_to_2__s2(instruction); 1720 1721 const char *rt = GPR(rt_value, info); 1722 1723 return img_format("ADDIU %s, $%d, 0x%" PRIx64, rt, 28, u_value); 1724 } 1725 1726 1727 /* 1728 * 1729 * 1730 * 3 2 1 1731 * 10987654321098765432109876543210 1732 * 001000 0010000100111111 1733 * rt ----- 1734 * rs ----- 1735 */ 1736 static char *ADDIU_NEG_(uint64 instruction, Dis_info *info) 1737 { 1738 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1739 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1740 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 1741 1742 const char *rt = GPR(rt_value, info); 1743 const char *rs = GPR(rs_value, info); 1744 int64 u = neg_copy(u_value); 1745 1746 return img_format("ADDIU %s, %s, %" PRId64, rt, rs, u); 1747 } 1748 1749 1750 /* 1751 * 1752 * 1753 * 3 2 1 1754 * 10987654321098765432109876543210 1755 * 001000 0010000100111111 1756 * rt ----- 1757 * rs ----- 1758 */ 1759 static char *ADDIU_R1_SP_(uint64 instruction, Dis_info *info) 1760 { 1761 uint64 u_value = extract_u_5_4_3_2_1_0__s2(instruction); 1762 uint64 rt3_value = extract_rt3_9_8_7(instruction); 1763 1764 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 1765 1766 return img_format("ADDIU %s, $%d, 0x%" PRIx64, rt3, 29, u_value); 1767 } 1768 1769 1770 /* 1771 * 1772 * 1773 * 3 2 1 1774 * 10987654321098765432109876543210 1775 * 001000 0010000100111111 1776 * rt ----- 1777 * rs ----- 1778 */ 1779 static char *ADDIU_R2_(uint64 instruction, Dis_info *info) 1780 { 1781 uint64 rt3_value = extract_rt3_9_8_7(instruction); 1782 uint64 rs3_value = extract_rs3_6_5_4(instruction); 1783 uint64 u_value = extract_u_2_1_0__s2(instruction); 1784 1785 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 1786 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 1787 1788 return img_format("ADDIU %s, %s, 0x%" PRIx64, rt3, rs3, u_value); 1789 } 1790 1791 1792 /* 1793 * ADDIU[RS5] rt, s5 - Add Signed Word and Set Carry Bit 1794 * 1795 * 5432109876543210 1796 * 100100 1 1797 * rt ----- 1798 * s - --- 1799 */ 1800 static char *ADDIU_RS5_(uint64 instruction, Dis_info *info) 1801 { 1802 uint64 rt_value = extract_rt_9_8_7_6_5(instruction); 1803 int64 s_value = extract_s__se3_4_2_1_0(instruction); 1804 1805 const char *rt = GPR(rt_value, info); 1806 1807 return img_format("ADDIU %s, %" PRId64, rt, s_value); 1808 } 1809 1810 1811 /* 1812 * 1813 * 1814 * 3 2 1 1815 * 10987654321098765432109876543210 1816 * 001000 x1110000101 1817 * rt ----- 1818 * rs ----- 1819 * rd ----- 1820 */ 1821 static char *ADDIUPC_32_(uint64 instruction, Dis_info *info) 1822 { 1823 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1824 int64 s_value = extract_s__se21_0_20_to_1_s1(instruction); 1825 1826 const char *rt = GPR(rt_value, info); 1827 g_autofree char *s = ADDRESS(s_value, 4, info); 1828 1829 return img_format("ADDIUPC %s, %s", rt, s); 1830 } 1831 1832 1833 /* 1834 * 1835 * 1836 * 3 2 1 1837 * 10987654321098765432109876543210 1838 * 001000 x1110000101 1839 * rt ----- 1840 * rs ----- 1841 * rd ----- 1842 */ 1843 static char *ADDIUPC_48_(uint64 instruction, Dis_info *info) 1844 { 1845 uint64 rt_value = extract_rt_41_40_39_38_37(instruction); 1846 int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); 1847 1848 const char *rt = GPR(rt_value, info); 1849 g_autofree char *s = ADDRESS(s_value, 6, info); 1850 1851 return img_format("ADDIUPC %s, %s", rt, s); 1852 } 1853 1854 1855 /* 1856 * [DSP] ADDQ.PH rd, rt, rs - Add fractional halfword vectors 1857 * 1858 * 3 2 1 1859 * 10987654321098765432109876543210 1860 * 001000 00000001101 1861 * rt ----- 1862 * rs ----- 1863 * rd ----- 1864 */ 1865 static char *ADDQ_PH(uint64 instruction, Dis_info *info) 1866 { 1867 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1868 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1869 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 1870 1871 const char *rd = GPR(rd_value, info); 1872 const char *rs = GPR(rs_value, info); 1873 const char *rt = GPR(rt_value, info); 1874 1875 return img_format("ADDQ.PH %s, %s, %s", rd, rs, rt); 1876 } 1877 1878 1879 /* 1880 * [DSP] ADDQ_S.PH rd, rt, rs - Add fractional halfword vectors with 16-bit 1881 * saturation 1882 * 1883 * 3 2 1 1884 * 10987654321098765432109876543210 1885 * 001000 10000001101 1886 * rt ----- 1887 * rs ----- 1888 * rd ----- 1889 */ 1890 static char *ADDQ_S_PH(uint64 instruction, Dis_info *info) 1891 { 1892 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1893 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1894 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 1895 1896 const char *rd = GPR(rd_value, info); 1897 const char *rs = GPR(rs_value, info); 1898 const char *rt = GPR(rt_value, info); 1899 1900 return img_format("ADDQ_S.PH %s, %s, %s", rd, rs, rt); 1901 } 1902 1903 1904 /* 1905 * [DSP] ADDQ_S.W rd, rt, rs - Add fractional words with 32-bit saturation 1906 * 1907 * 3 2 1 1908 * 10987654321098765432109876543210 1909 * 001000 x1100000101 1910 * rt ----- 1911 * rs ----- 1912 * rd ----- 1913 */ 1914 static char *ADDQ_S_W(uint64 instruction, Dis_info *info) 1915 { 1916 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1917 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1918 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 1919 1920 const char *rd = GPR(rd_value, info); 1921 const char *rs = GPR(rs_value, info); 1922 const char *rt = GPR(rt_value, info); 1923 1924 return img_format("ADDQ_S.W %s, %s, %s", rd, rs, rt); 1925 } 1926 1927 1928 /* 1929 * [DSP] ADDQH.PH rd, rt, rs - Add fractional halfword vectors and shift 1930 * right to halve results 1931 * 1932 * 3 2 1 1933 * 10987654321098765432109876543210 1934 * 001000 00001001101 1935 * rt ----- 1936 * rs ----- 1937 * rd ----- 1938 */ 1939 static char *ADDQH_PH(uint64 instruction, Dis_info *info) 1940 { 1941 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1942 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1943 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 1944 1945 const char *rd = GPR(rd_value, info); 1946 const char *rs = GPR(rs_value, info); 1947 const char *rt = GPR(rt_value, info); 1948 1949 return img_format("ADDQH.PH %s, %s, %s", rd, rs, rt); 1950 } 1951 1952 1953 /* 1954 * [DSP] ADDQH_R.PH rd, rt, rs - Add fractional halfword vectors and shift 1955 * right to halve results with rounding 1956 * 1957 * 3 2 1 1958 * 10987654321098765432109876543210 1959 * 001000 10001001101 1960 * rt ----- 1961 * rs ----- 1962 * rd ----- 1963 */ 1964 static char *ADDQH_R_PH(uint64 instruction, Dis_info *info) 1965 { 1966 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1967 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1968 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 1969 1970 const char *rd = GPR(rd_value, info); 1971 const char *rs = GPR(rs_value, info); 1972 const char *rt = GPR(rt_value, info); 1973 1974 return img_format("ADDQH_R.PH %s, %s, %s", rd, rs, rt); 1975 } 1976 1977 1978 /* 1979 * [DSP] ADDQH_R.W rd, rt, rs - Add fractional words and shift right to halve 1980 * results with rounding 1981 * 1982 * 3 2 1 1983 * 10987654321098765432109876543210 1984 * 001000 00010001101 1985 * rt ----- 1986 * rs ----- 1987 * rd ----- 1988 */ 1989 static char *ADDQH_R_W(uint64 instruction, Dis_info *info) 1990 { 1991 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 1992 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 1993 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 1994 1995 const char *rd = GPR(rd_value, info); 1996 const char *rs = GPR(rs_value, info); 1997 const char *rt = GPR(rt_value, info); 1998 1999 return img_format("ADDQH_R.W %s, %s, %s", rd, rs, rt); 2000 } 2001 2002 2003 /* 2004 * [DSP] ADDQH.W rd, rt, rs - Add fractional words and shift right to halve 2005 * results 2006 * 2007 * 3 2 1 2008 * 10987654321098765432109876543210 2009 * 001000 10010001101 2010 * rt ----- 2011 * rs ----- 2012 * rd ----- 2013 */ 2014 static char *ADDQH_W(uint64 instruction, Dis_info *info) 2015 { 2016 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2017 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2018 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 2019 2020 const char *rd = GPR(rd_value, info); 2021 const char *rs = GPR(rs_value, info); 2022 const char *rt = GPR(rt_value, info); 2023 2024 return img_format("ADDQH.W %s, %s, %s", rd, rs, rt); 2025 } 2026 2027 2028 /* 2029 * [DSP] ADDSC rd, rt, rs - Add two signed words and set carry bit 2030 * 2031 * 3 2 1 2032 * 10987654321098765432109876543210 2033 * 001000 x1110000101 2034 * rt ----- 2035 * rs ----- 2036 * rd ----- 2037 */ 2038 static char *ADDSC(uint64 instruction, Dis_info *info) 2039 { 2040 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2041 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2042 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 2043 2044 const char *rd = GPR(rd_value, info); 2045 const char *rs = GPR(rs_value, info); 2046 const char *rt = GPR(rt_value, info); 2047 2048 return img_format("ADDSC %s, %s, %s", rd, rs, rt); 2049 } 2050 2051 2052 /* 2053 * ADDU[16] rd3, rs3, rt3 - 2054 * 2055 * 5432109876543210 2056 * 101100 0 2057 * rt3 --- 2058 * rs3 --- 2059 * rd3 --- 2060 */ 2061 static char *ADDU_16_(uint64 instruction, Dis_info *info) 2062 { 2063 uint64 rt3_value = extract_rt3_9_8_7(instruction); 2064 uint64 rs3_value = extract_rs3_6_5_4(instruction); 2065 uint64 rd3_value = extract_rd3_3_2_1(instruction); 2066 2067 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 2068 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 2069 const char *rd3 = GPR(decode_gpr_gpr3(rd3_value, info), info); 2070 2071 return img_format("ADDU %s, %s, %s", rd3, rs3, rt3); 2072 } 2073 2074 2075 /* 2076 * 2077 * 2078 * 3 2 1 2079 * 10987654321098765432109876543210 2080 * 001000 x1110000101 2081 * rt ----- 2082 * rs ----- 2083 * rd ----- 2084 */ 2085 static char *ADDU_32_(uint64 instruction, Dis_info *info) 2086 { 2087 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2088 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2089 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 2090 2091 const char *rd = GPR(rd_value, info); 2092 const char *rs = GPR(rs_value, info); 2093 const char *rt = GPR(rt_value, info); 2094 2095 return img_format("ADDU %s, %s, %s", rd, rs, rt); 2096 } 2097 2098 2099 /* 2100 * 2101 * 2102 * 3 2 1 2103 * 10987654321098765432109876543210 2104 * 001000 x1110000101 2105 * rt ----- 2106 * rs ----- 2107 * rd ----- 2108 */ 2109 static char *ADDU_4X4_(uint64 instruction, Dis_info *info) 2110 { 2111 uint64 rt4_value = extract_rt4_9_7_6_5(instruction); 2112 uint64 rs4_value = extract_rs4_4_2_1_0(instruction); 2113 2114 const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info); 2115 const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info); 2116 2117 return img_format("ADDU %s, %s", rs4, rt4); 2118 } 2119 2120 2121 /* 2122 * [DSP] ADDU.PH rd, rt, rs - Add two pairs of unsigned halfwords 2123 * 2124 * 3 2 1 2125 * 10987654321098765432109876543210 2126 * 001000 00100001101 2127 * rt ----- 2128 * rs ----- 2129 * rd ----- 2130 */ 2131 static char *ADDU_PH(uint64 instruction, Dis_info *info) 2132 { 2133 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2134 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2135 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 2136 2137 const char *rd = GPR(rd_value, info); 2138 const char *rs = GPR(rs_value, info); 2139 const char *rt = GPR(rt_value, info); 2140 2141 return img_format("ADDU.PH %s, %s, %s", rd, rs, rt); 2142 } 2143 2144 2145 /* 2146 * ADDU.QB rd, rt, rs - Unsigned Add Quad Byte Vectors 2147 * 2148 * 3 2 1 2149 * 10987654321098765432109876543210 2150 * 001000 00011001101 2151 * rt ----- 2152 * rs ----- 2153 * rd ----- 2154 */ 2155 static char *ADDU_QB(uint64 instruction, Dis_info *info) 2156 { 2157 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2158 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2159 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 2160 2161 const char *rd = GPR(rd_value, info); 2162 const char *rs = GPR(rs_value, info); 2163 const char *rt = GPR(rt_value, info); 2164 2165 return img_format("ADDU.QB %s, %s, %s", rd, rs, rt); 2166 } 2167 2168 2169 /* 2170 * [DSP] ADDU_S.PH rd, rt, rs - Add two pairs of unsigned halfwords with 16-bit 2171 * saturation 2172 * 2173 * 3 2 1 2174 * 10987654321098765432109876543210 2175 * 001000 10100001101 2176 * rt ----- 2177 * rs ----- 2178 * rd ----- 2179 */ 2180 static char *ADDU_S_PH(uint64 instruction, Dis_info *info) 2181 { 2182 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2183 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2184 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 2185 2186 const char *rd = GPR(rd_value, info); 2187 const char *rs = GPR(rs_value, info); 2188 const char *rt = GPR(rt_value, info); 2189 2190 return img_format("ADDU_S.PH %s, %s, %s", rd, rs, rt); 2191 } 2192 2193 2194 /* 2195 * ADDU_S.QB rd, rt, rs - Unsigned Add Quad Byte Vectors 2196 * 2197 * 3 2 1 2198 * 10987654321098765432109876543210 2199 * 001000 10011001101 2200 * rt ----- 2201 * rs ----- 2202 * rd ----- 2203 */ 2204 static char *ADDU_S_QB(uint64 instruction, Dis_info *info) 2205 { 2206 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2207 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2208 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 2209 2210 const char *rd = GPR(rd_value, info); 2211 const char *rs = GPR(rs_value, info); 2212 const char *rt = GPR(rt_value, info); 2213 2214 return img_format("ADDU_S.QB %s, %s, %s", rd, rs, rt); 2215 } 2216 2217 2218 /* 2219 * ADDUH.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift 2220 * to Halve Results 2221 * 2222 * 3 2 1 2223 * 10987654321098765432109876543210 2224 * 001000 00101001101 2225 * rt ----- 2226 * rs ----- 2227 * rd ----- 2228 */ 2229 static char *ADDUH_QB(uint64 instruction, Dis_info *info) 2230 { 2231 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2232 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2233 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 2234 2235 const char *rd = GPR(rd_value, info); 2236 const char *rs = GPR(rs_value, info); 2237 const char *rt = GPR(rt_value, info); 2238 2239 return img_format("ADDUH.QB %s, %s, %s", rd, rs, rt); 2240 } 2241 2242 2243 /* 2244 * ADDUH_R.QB rd, rt, rs - Unsigned Add Vector Quad-Bytes And Right Shift 2245 * to Halve Results 2246 * 2247 * 3 2 1 2248 * 10987654321098765432109876543210 2249 * 001000 10101001101 2250 * rt ----- 2251 * rs ----- 2252 * rd ----- 2253 */ 2254 static char *ADDUH_R_QB(uint64 instruction, Dis_info *info) 2255 { 2256 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2257 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2258 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 2259 2260 const char *rd = GPR(rd_value, info); 2261 const char *rs = GPR(rs_value, info); 2262 const char *rt = GPR(rt_value, info); 2263 2264 return img_format("ADDUH_R.QB %s, %s, %s", rd, rs, rt); 2265 } 2266 2267 /* 2268 * ADDWC rd, rt, rs - Add Word with Carry Bit 2269 * 2270 * 3 2 1 2271 * 10987654321098765432109876543210 2272 * 001000 x1111000101 2273 * rt ----- 2274 * rs ----- 2275 * rd ----- 2276 */ 2277 static char *ADDWC(uint64 instruction, Dis_info *info) 2278 { 2279 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2280 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2281 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 2282 2283 const char *rd = GPR(rd_value, info); 2284 const char *rs = GPR(rs_value, info); 2285 const char *rt = GPR(rt_value, info); 2286 2287 return img_format("ADDWC %s, %s, %s", rd, rs, rt); 2288 } 2289 2290 2291 /* 2292 * 2293 * 2294 * 3 2 1 2295 * 10987654321098765432109876543210 2296 * 001000 x1110000101 2297 * rt ----- 2298 * rs ----- 2299 * rd ----- 2300 */ 2301 static char *ALUIPC(uint64 instruction, Dis_info *info) 2302 { 2303 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2304 int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction); 2305 2306 const char *rt = GPR(rt_value, info); 2307 g_autofree char *s = ADDRESS(s_value, 4, info); 2308 2309 return img_format("ALUIPC %s, %%pcrel_hi(%s)", rt, s); 2310 } 2311 2312 2313 /* 2314 * AND[16] rt3, rs3 - 2315 * 2316 * 5432109876543210 2317 * 101100 2318 * rt3 --- 2319 * rs3 --- 2320 * eu ---- 2321 */ 2322 static char *AND_16_(uint64 instruction, Dis_info *info) 2323 { 2324 uint64 rt3_value = extract_rt3_9_8_7(instruction); 2325 uint64 rs3_value = extract_rs3_6_5_4(instruction); 2326 2327 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 2328 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 2329 2330 return img_format("AND %s, %s", rs3, rt3); 2331 } 2332 2333 2334 /* 2335 * 2336 * 2337 * 3 2 1 2338 * 10987654321098765432109876543210 2339 * 001000 x1110000101 2340 * rt ----- 2341 * rs ----- 2342 * rd ----- 2343 */ 2344 static char *AND_32_(uint64 instruction, Dis_info *info) 2345 { 2346 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2347 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2348 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 2349 2350 const char *rd = GPR(rd_value, info); 2351 const char *rs = GPR(rs_value, info); 2352 const char *rt = GPR(rt_value, info); 2353 2354 return img_format("AND %s, %s, %s", rd, rs, rt); 2355 } 2356 2357 2358 /* 2359 * ANDI rt, rs, u - 2360 * 2361 * 5432109876543210 2362 * 101100 2363 * rt3 --- 2364 * rs3 --- 2365 * eu ---- 2366 */ 2367 static char *ANDI_16_(uint64 instruction, Dis_info *info) 2368 { 2369 uint64 rt3_value = extract_rt3_9_8_7(instruction); 2370 uint64 rs3_value = extract_rs3_6_5_4(instruction); 2371 uint64 eu_value = extract_eu_3_2_1_0(instruction); 2372 2373 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 2374 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 2375 uint64 eu = encode_eu_from_u_andi16(eu_value); 2376 2377 return img_format("ANDI %s, %s, 0x%" PRIx64, rt3, rs3, eu); 2378 } 2379 2380 2381 /* 2382 * 2383 * 2384 * 3 2 1 2385 * 10987654321098765432109876543210 2386 * 001000 x1110000101 2387 * rt ----- 2388 * rs ----- 2389 * rd ----- 2390 */ 2391 static char *ANDI_32_(uint64 instruction, Dis_info *info) 2392 { 2393 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2394 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2395 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 2396 2397 const char *rt = GPR(rt_value, info); 2398 const char *rs = GPR(rs_value, info); 2399 2400 return img_format("ANDI %s, %s, 0x%" PRIx64, rt, rs, u_value); 2401 } 2402 2403 2404 /* 2405 * 2406 * 2407 * 3 2 1 2408 * 10987654321098765432109876543210 2409 * 001000 x1110000101 2410 * rt ----- 2411 * rs ----- 2412 * rd ----- 2413 */ 2414 static char *APPEND(uint64 instruction, Dis_info *info) 2415 { 2416 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2417 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2418 uint64 sa_value = extract_sa_15_14_13_12_11(instruction); 2419 2420 const char *rt = GPR(rt_value, info); 2421 const char *rs = GPR(rs_value, info); 2422 2423 return img_format("APPEND %s, %s, 0x%" PRIx64, rt, rs, sa_value); 2424 } 2425 2426 2427 /* 2428 * 2429 * 2430 * 3 2 1 2431 * 10987654321098765432109876543210 2432 * 001000 x1110000101 2433 * rt ----- 2434 * rs ----- 2435 * rd ----- 2436 */ 2437 static char *ASET(uint64 instruction, Dis_info *info) 2438 { 2439 uint64 bit_value = extract_bit_23_22_21(instruction); 2440 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2441 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 2442 2443 const char *rs = GPR(rs_value, info); 2444 2445 return img_format("ASET 0x%" PRIx64 ", %" PRId64 "(%s)", 2446 bit_value, s_value, rs); 2447 } 2448 2449 2450 /* 2451 * 2452 * 2453 * 3 2 1 2454 * 10987654321098765432109876543210 2455 * 001000 x1110000101 2456 * rt ----- 2457 * rs ----- 2458 * rd ----- 2459 */ 2460 static char *BALC_16_(uint64 instruction, Dis_info *info) 2461 { 2462 int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction); 2463 2464 g_autofree char *s = ADDRESS(s_value, 2, info); 2465 2466 return img_format("BALC %s", s); 2467 } 2468 2469 2470 /* 2471 * 2472 * 2473 * 3 2 1 2474 * 10987654321098765432109876543210 2475 * 001000 x1110000101 2476 * rt ----- 2477 * rs ----- 2478 * rd ----- 2479 */ 2480 static char *BALC_32_(uint64 instruction, Dis_info *info) 2481 { 2482 int64 s_value = extract_s__se25_0_24_to_1_s1(instruction); 2483 2484 g_autofree char *s = ADDRESS(s_value, 4, info); 2485 2486 return img_format("BALC %s", s); 2487 } 2488 2489 2490 /* 2491 * 2492 * 2493 * 3 2 1 2494 * 10987654321098765432109876543210 2495 * 001000 x1110000101 2496 * rt ----- 2497 * rs ----- 2498 * rd ----- 2499 */ 2500 static char *BALRSC(uint64 instruction, Dis_info *info) 2501 { 2502 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2503 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2504 2505 const char *rt = GPR(rt_value, info); 2506 const char *rs = GPR(rs_value, info); 2507 2508 return img_format("BALRSC %s, %s", rt, rs); 2509 } 2510 2511 2512 /* 2513 * 2514 * 2515 * 3 2 1 2516 * 10987654321098765432109876543210 2517 * 001000 x1110000101 2518 * rt ----- 2519 * rs ----- 2520 * rd ----- 2521 */ 2522 static char *BBEQZC(uint64 instruction, Dis_info *info) 2523 { 2524 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2525 uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction); 2526 int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); 2527 2528 const char *rt = GPR(rt_value, info); 2529 g_autofree char *s = ADDRESS(s_value, 4, info); 2530 2531 return img_format("BBEQZC %s, 0x%" PRIx64 ", %s", rt, bit_value, s); 2532 } 2533 2534 2535 /* 2536 * 2537 * 2538 * 3 2 1 2539 * 10987654321098765432109876543210 2540 * 001000 x1110000101 2541 * rt ----- 2542 * rs ----- 2543 * rd ----- 2544 */ 2545 static char *BBNEZC(uint64 instruction, Dis_info *info) 2546 { 2547 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2548 uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction); 2549 int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); 2550 2551 const char *rt = GPR(rt_value, info); 2552 g_autofree char *s = ADDRESS(s_value, 4, info); 2553 2554 return img_format("BBNEZC %s, 0x%" PRIx64 ", %s", rt, bit_value, s); 2555 } 2556 2557 2558 /* 2559 * 2560 * 2561 * 3 2 1 2562 * 10987654321098765432109876543210 2563 * 001000 x1110000101 2564 * rt ----- 2565 * rs ----- 2566 * rd ----- 2567 */ 2568 static char *BC_16_(uint64 instruction, Dis_info *info) 2569 { 2570 int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction); 2571 2572 g_autofree char *s = ADDRESS(s_value, 2, info); 2573 2574 return img_format("BC %s", s); 2575 } 2576 2577 2578 /* 2579 * 2580 * 2581 * 3 2 1 2582 * 10987654321098765432109876543210 2583 * 001000 x1110000101 2584 * rt ----- 2585 * rs ----- 2586 * rd ----- 2587 */ 2588 static char *BC_32_(uint64 instruction, Dis_info *info) 2589 { 2590 int64 s_value = extract_s__se25_0_24_to_1_s1(instruction); 2591 2592 g_autofree char *s = ADDRESS(s_value, 4, info); 2593 2594 return img_format("BC %s", s); 2595 } 2596 2597 2598 /* 2599 * 2600 * 2601 * 3 2 1 2602 * 10987654321098765432109876543210 2603 * 001000 x1110000101 2604 * rt ----- 2605 * rs ----- 2606 * rd ----- 2607 */ 2608 static char *BC1EQZC(uint64 instruction, Dis_info *info) 2609 { 2610 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 2611 int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); 2612 2613 const char *ft = FPR(ft_value, info); 2614 g_autofree char *s = ADDRESS(s_value, 4, info); 2615 2616 return img_format("BC1EQZC %s, %s", ft, s); 2617 } 2618 2619 2620 /* 2621 * 2622 * 2623 * 3 2 1 2624 * 10987654321098765432109876543210 2625 * 001000 x1110000101 2626 * rt ----- 2627 * rs ----- 2628 * rd ----- 2629 */ 2630 static char *BC1NEZC(uint64 instruction, Dis_info *info) 2631 { 2632 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 2633 int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); 2634 2635 const char *ft = FPR(ft_value, info); 2636 g_autofree char *s = ADDRESS(s_value, 4, info); 2637 2638 return img_format("BC1NEZC %s, %s", ft, s); 2639 } 2640 2641 2642 /* 2643 * 2644 * 2645 * 3 2 1 2646 * 10987654321098765432109876543210 2647 * 001000 x1110000101 2648 * rt ----- 2649 * rs ----- 2650 * rd ----- 2651 */ 2652 static char *BC2EQZC(uint64 instruction, Dis_info *info) 2653 { 2654 uint64 ct_value = extract_ct_25_24_23_22_21(instruction); 2655 int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); 2656 2657 g_autofree char *s = ADDRESS(s_value, 4, info); 2658 2659 return img_format("BC2EQZC CP%" PRIu64 ", %s", ct_value, s); 2660 } 2661 2662 2663 /* 2664 * 2665 * 2666 * 3 2 1 2667 * 10987654321098765432109876543210 2668 * 001000 x1110000101 2669 * rt ----- 2670 * rs ----- 2671 * rd ----- 2672 */ 2673 static char *BC2NEZC(uint64 instruction, Dis_info *info) 2674 { 2675 uint64 ct_value = extract_ct_25_24_23_22_21(instruction); 2676 int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); 2677 2678 g_autofree char *s = ADDRESS(s_value, 4, info); 2679 2680 return img_format("BC2NEZC CP%" PRIu64 ", %s", ct_value, s); 2681 } 2682 2683 2684 /* 2685 * 2686 * 2687 * 3 2 1 2688 * 10987654321098765432109876543210 2689 * 001000 x1110000101 2690 * rt ----- 2691 * rs ----- 2692 * rd ----- 2693 */ 2694 static char *BEQC_16_(uint64 instruction, Dis_info *info) 2695 { 2696 uint64 rt3_value = extract_rt3_9_8_7(instruction); 2697 uint64 rs3_value = extract_rs3_6_5_4(instruction); 2698 uint64 u_value = extract_u_3_2_1_0__s1(instruction); 2699 2700 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 2701 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 2702 g_autofree char *u = ADDRESS(u_value, 2, info); 2703 2704 return img_format("BEQC %s, %s, %s", rs3, rt3, u); 2705 } 2706 2707 2708 /* 2709 * 2710 * 2711 * 3 2 1 2712 * 10987654321098765432109876543210 2713 * 001000 x1110000101 2714 * rt ----- 2715 * rs ----- 2716 * rd ----- 2717 */ 2718 static char *BEQC_32_(uint64 instruction, Dis_info *info) 2719 { 2720 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2721 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2722 int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); 2723 2724 const char *rs = GPR(rs_value, info); 2725 const char *rt = GPR(rt_value, info); 2726 g_autofree char *s = ADDRESS(s_value, 4, info); 2727 2728 return img_format("BEQC %s, %s, %s", rs, rt, s); 2729 } 2730 2731 2732 /* 2733 * 2734 * 2735 * 3 2 1 2736 * 10987654321098765432109876543210 2737 * 001000 x1110000101 2738 * rt ----- 2739 * rs ----- 2740 * rd ----- 2741 */ 2742 static char *BEQIC(uint64 instruction, Dis_info *info) 2743 { 2744 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2745 uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); 2746 int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); 2747 2748 const char *rt = GPR(rt_value, info); 2749 g_autofree char *s = ADDRESS(s_value, 4, info); 2750 2751 return img_format("BEQIC %s, 0x%" PRIx64 ", %s", rt, u_value, s); 2752 } 2753 2754 2755 /* 2756 * 2757 * 2758 * 3 2 1 2759 * 10987654321098765432109876543210 2760 * 001000 x1110000101 2761 * rt ----- 2762 * rs ----- 2763 * rd ----- 2764 */ 2765 static char *BEQZC_16_(uint64 instruction, Dis_info *info) 2766 { 2767 uint64 rt3_value = extract_rt3_9_8_7(instruction); 2768 int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction); 2769 2770 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 2771 g_autofree char *s = ADDRESS(s_value, 2, info); 2772 2773 return img_format("BEQZC %s, %s", rt3, s); 2774 } 2775 2776 2777 /* 2778 * 2779 * 2780 * 3 2 1 2781 * 10987654321098765432109876543210 2782 * 001000 x1110000101 2783 * rt ----- 2784 * rs ----- 2785 * rd ----- 2786 */ 2787 static char *BGEC(uint64 instruction, Dis_info *info) 2788 { 2789 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2790 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2791 int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); 2792 2793 const char *rs = GPR(rs_value, info); 2794 const char *rt = GPR(rt_value, info); 2795 g_autofree char *s = ADDRESS(s_value, 4, info); 2796 2797 return img_format("BGEC %s, %s, %s", rs, rt, s); 2798 } 2799 2800 2801 /* 2802 * 2803 * 2804 * 3 2 1 2805 * 10987654321098765432109876543210 2806 * 001000 x1110000101 2807 * rt ----- 2808 * rs ----- 2809 * rd ----- 2810 */ 2811 static char *BGEIC(uint64 instruction, Dis_info *info) 2812 { 2813 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2814 uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); 2815 int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); 2816 2817 const char *rt = GPR(rt_value, info); 2818 g_autofree char *s = ADDRESS(s_value, 4, info); 2819 2820 return img_format("BGEIC %s, 0x%" PRIx64 ", %s", rt, u_value, s); 2821 } 2822 2823 2824 /* 2825 * 2826 * 2827 * 3 2 1 2828 * 10987654321098765432109876543210 2829 * 001000 x1110000101 2830 * rt ----- 2831 * rs ----- 2832 * rd ----- 2833 */ 2834 static char *BGEIUC(uint64 instruction, Dis_info *info) 2835 { 2836 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2837 uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); 2838 int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); 2839 2840 const char *rt = GPR(rt_value, info); 2841 g_autofree char *s = ADDRESS(s_value, 4, info); 2842 2843 return img_format("BGEIUC %s, 0x%" PRIx64 ", %s", rt, u_value, s); 2844 } 2845 2846 2847 /* 2848 * 2849 * 2850 * 3 2 1 2851 * 10987654321098765432109876543210 2852 * 001000 x1110000101 2853 * rt ----- 2854 * rs ----- 2855 * rd ----- 2856 */ 2857 static char *BGEUC(uint64 instruction, Dis_info *info) 2858 { 2859 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2860 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2861 int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); 2862 2863 const char *rs = GPR(rs_value, info); 2864 const char *rt = GPR(rt_value, info); 2865 g_autofree char *s = ADDRESS(s_value, 4, info); 2866 2867 return img_format("BGEUC %s, %s, %s", rs, rt, s); 2868 } 2869 2870 2871 /* 2872 * 2873 * 2874 * 3 2 1 2875 * 10987654321098765432109876543210 2876 * 001000 x1110000101 2877 * rt ----- 2878 * rs ----- 2879 * rd ----- 2880 */ 2881 static char *BLTC(uint64 instruction, Dis_info *info) 2882 { 2883 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2884 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2885 int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); 2886 2887 const char *rs = GPR(rs_value, info); 2888 const char *rt = GPR(rt_value, info); 2889 g_autofree char *s = ADDRESS(s_value, 4, info); 2890 2891 return img_format("BLTC %s, %s, %s", rs, rt, s); 2892 } 2893 2894 2895 /* 2896 * 2897 * 2898 * 3 2 1 2899 * 10987654321098765432109876543210 2900 * 001000 x1110000101 2901 * rt ----- 2902 * rs ----- 2903 * rd ----- 2904 */ 2905 static char *BLTIC(uint64 instruction, Dis_info *info) 2906 { 2907 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2908 uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); 2909 int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); 2910 2911 const char *rt = GPR(rt_value, info); 2912 g_autofree char *s = ADDRESS(s_value, 4, info); 2913 2914 return img_format("BLTIC %s, 0x%" PRIx64 ", %s", rt, u_value, s); 2915 } 2916 2917 2918 /* 2919 * 2920 * 2921 * 3 2 1 2922 * 10987654321098765432109876543210 2923 * 001000 x1110000101 2924 * rt ----- 2925 * rs ----- 2926 * rd ----- 2927 */ 2928 static char *BLTIUC(uint64 instruction, Dis_info *info) 2929 { 2930 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2931 uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); 2932 int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); 2933 2934 const char *rt = GPR(rt_value, info); 2935 g_autofree char *s = ADDRESS(s_value, 4, info); 2936 2937 return img_format("BLTIUC %s, 0x%" PRIx64 ", %s", rt, u_value, s); 2938 } 2939 2940 2941 /* 2942 * 2943 * 2944 * 3 2 1 2945 * 10987654321098765432109876543210 2946 * 001000 x1110000101 2947 * rt ----- 2948 * rs ----- 2949 * rd ----- 2950 */ 2951 static char *BLTUC(uint64 instruction, Dis_info *info) 2952 { 2953 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 2954 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 2955 int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); 2956 2957 const char *rs = GPR(rs_value, info); 2958 const char *rt = GPR(rt_value, info); 2959 g_autofree char *s = ADDRESS(s_value, 4, info); 2960 2961 return img_format("BLTUC %s, %s, %s", rs, rt, s); 2962 } 2963 2964 2965 /* 2966 * 2967 * 2968 * 3 2 1 2969 * 10987654321098765432109876543210 2970 * 001000 x1110000101 2971 * rt ----- 2972 * rs ----- 2973 * rd ----- 2974 */ 2975 static char *BNEC_16_(uint64 instruction, Dis_info *info) 2976 { 2977 uint64 rt3_value = extract_rt3_9_8_7(instruction); 2978 uint64 rs3_value = extract_rs3_6_5_4(instruction); 2979 uint64 u_value = extract_u_3_2_1_0__s1(instruction); 2980 2981 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 2982 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 2983 g_autofree char *u = ADDRESS(u_value, 2, info); 2984 2985 return img_format("BNEC %s, %s, %s", rs3, rt3, u); 2986 } 2987 2988 2989 /* 2990 * 2991 * 2992 * 3 2 1 2993 * 10987654321098765432109876543210 2994 * 001000 x1110000101 2995 * rt ----- 2996 * rs ----- 2997 * rd ----- 2998 */ 2999 static char *BNEC_32_(uint64 instruction, Dis_info *info) 3000 { 3001 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 3002 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 3003 int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); 3004 3005 const char *rs = GPR(rs_value, info); 3006 const char *rt = GPR(rt_value, info); 3007 g_autofree char *s = ADDRESS(s_value, 4, info); 3008 3009 return img_format("BNEC %s, %s, %s", rs, rt, s); 3010 } 3011 3012 3013 /* 3014 * 3015 * 3016 * 3 2 1 3017 * 10987654321098765432109876543210 3018 * 001000 x1110000101 3019 * rt ----- 3020 * rs ----- 3021 * rd ----- 3022 */ 3023 static char *BNEIC(uint64 instruction, Dis_info *info) 3024 { 3025 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 3026 uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); 3027 int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); 3028 3029 const char *rt = GPR(rt_value, info); 3030 g_autofree char *s = ADDRESS(s_value, 4, info); 3031 3032 return img_format("BNEIC %s, 0x%" PRIx64 ", %s", rt, u_value, s); 3033 } 3034 3035 3036 /* 3037 * 3038 * 3039 * 3 2 1 3040 * 10987654321098765432109876543210 3041 * 001000 x1110000101 3042 * rt ----- 3043 * rs ----- 3044 * rd ----- 3045 */ 3046 static char *BNEZC_16_(uint64 instruction, Dis_info *info) 3047 { 3048 uint64 rt3_value = extract_rt3_9_8_7(instruction); 3049 int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction); 3050 3051 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 3052 g_autofree char *s = ADDRESS(s_value, 2, info); 3053 3054 return img_format("BNEZC %s, %s", rt3, s); 3055 } 3056 3057 3058 /* 3059 * [DSP] BPOSGE32C offset - Branch on greater than or equal to value 32 in 3060 * DSPControl Pos field 3061 * 3062 * 3 2 1 3063 * 10987654321098765432109876543210 3064 * 100010xxxxx0010001 3065 * s[13:1] ------------- 3066 * s[14] - 3067 */ 3068 static char *BPOSGE32C(uint64 instruction, Dis_info *info) 3069 { 3070 int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); 3071 3072 g_autofree char *s = ADDRESS(s_value, 4, info); 3073 3074 return img_format("BPOSGE32C %s", s); 3075 } 3076 3077 3078 /* 3079 * 3080 * 3081 * 3 2 1 3082 * 10987654321098765432109876543210 3083 * 001000 x1110000101 3084 * rt ----- 3085 * rs ----- 3086 * rd ----- 3087 */ 3088 static char *BREAK_16_(uint64 instruction, Dis_info *info) 3089 { 3090 uint64 code_value = extract_code_2_1_0(instruction); 3091 3092 3093 return img_format("BREAK 0x%" PRIx64, code_value); 3094 } 3095 3096 3097 /* 3098 * BREAK code - Break. Cause a Breakpoint exception 3099 * 3100 * 3 2 1 3101 * 10987654321098765432109876543210 3102 * 001000 x1110000101 3103 * rt ----- 3104 * rs ----- 3105 * rd ----- 3106 */ 3107 static char *BREAK_32_(uint64 instruction, Dis_info *info) 3108 { 3109 uint64 code_value = extract_code_18_to_0(instruction); 3110 3111 3112 return img_format("BREAK 0x%" PRIx64, code_value); 3113 } 3114 3115 3116 /* 3117 * 3118 * 3119 * 3 2 1 3120 * 10987654321098765432109876543210 3121 * 001000 x1110000101 3122 * rt ----- 3123 * rs ----- 3124 * rd ----- 3125 */ 3126 static char *BRSC(uint64 instruction, Dis_info *info) 3127 { 3128 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 3129 3130 const char *rs = GPR(rs_value, info); 3131 3132 return img_format("BRSC %s", rs); 3133 } 3134 3135 3136 /* 3137 * 3138 * 3139 * 3 2 1 3140 * 10987654321098765432109876543210 3141 * 001000 x1110000101 3142 * rt ----- 3143 * rs ----- 3144 * rd ----- 3145 */ 3146 static char *CACHE(uint64 instruction, Dis_info *info) 3147 { 3148 uint64 op_value = extract_op_25_24_23_22_21(instruction); 3149 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 3150 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 3151 3152 const char *rs = GPR(rs_value, info); 3153 3154 return img_format("CACHE 0x%" PRIx64 ", %" PRId64 "(%s)", 3155 op_value, s_value, rs); 3156 } 3157 3158 3159 /* 3160 * 3161 * 3162 * 3 2 1 3163 * 10987654321098765432109876543210 3164 * 001000 x1110000101 3165 * rt ----- 3166 * rs ----- 3167 * rd ----- 3168 */ 3169 static char *CACHEE(uint64 instruction, Dis_info *info) 3170 { 3171 uint64 op_value = extract_op_25_24_23_22_21(instruction); 3172 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 3173 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 3174 3175 const char *rs = GPR(rs_value, info); 3176 3177 return img_format("CACHEE 0x%" PRIx64 ", %" PRId64 "(%s)", 3178 op_value, s_value, rs); 3179 } 3180 3181 3182 /* 3183 * 3184 * 3185 * 3 2 1 3186 * 10987654321098765432109876543210 3187 * 001000 x1110000101 3188 * rt ----- 3189 * rs ----- 3190 * rd ----- 3191 */ 3192 static char *CEIL_L_D(uint64 instruction, Dis_info *info) 3193 { 3194 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3195 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3196 3197 const char *ft = FPR(ft_value, info); 3198 const char *fs = FPR(fs_value, info); 3199 3200 return img_format("CEIL.L.D %s, %s", ft, fs); 3201 } 3202 3203 3204 /* 3205 * 3206 * 3207 * 3 2 1 3208 * 10987654321098765432109876543210 3209 * 001000 x1110000101 3210 * rt ----- 3211 * rs ----- 3212 * rd ----- 3213 */ 3214 static char *CEIL_L_S(uint64 instruction, Dis_info *info) 3215 { 3216 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3217 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3218 3219 const char *ft = FPR(ft_value, info); 3220 const char *fs = FPR(fs_value, info); 3221 3222 return img_format("CEIL.L.S %s, %s", ft, fs); 3223 } 3224 3225 3226 /* 3227 * 3228 * 3229 * 3 2 1 3230 * 10987654321098765432109876543210 3231 * 001000 x1110000101 3232 * rt ----- 3233 * rs ----- 3234 * rd ----- 3235 */ 3236 static char *CEIL_W_D(uint64 instruction, Dis_info *info) 3237 { 3238 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3239 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3240 3241 const char *ft = FPR(ft_value, info); 3242 const char *fs = FPR(fs_value, info); 3243 3244 return img_format("CEIL.W.D %s, %s", ft, fs); 3245 } 3246 3247 3248 /* 3249 * 3250 * 3251 * 3 2 1 3252 * 10987654321098765432109876543210 3253 * 001000 x1110000101 3254 * rt ----- 3255 * rs ----- 3256 * rd ----- 3257 */ 3258 static char *CEIL_W_S(uint64 instruction, Dis_info *info) 3259 { 3260 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3261 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3262 3263 const char *ft = FPR(ft_value, info); 3264 const char *fs = FPR(fs_value, info); 3265 3266 return img_format("CEIL.W.S %s, %s", ft, fs); 3267 } 3268 3269 3270 /* 3271 * 3272 * 3273 * 3 2 1 3274 * 10987654321098765432109876543210 3275 * 001000 x1110000101 3276 * rt ----- 3277 * rs ----- 3278 * rd ----- 3279 */ 3280 static char *CFC1(uint64 instruction, Dis_info *info) 3281 { 3282 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 3283 uint64 cs_value = extract_cs_20_19_18_17_16(instruction); 3284 3285 const char *rt = GPR(rt_value, info); 3286 3287 return img_format("CFC1 %s, CP%" PRIu64, rt, cs_value); 3288 } 3289 3290 3291 /* 3292 * 3293 * 3294 * 3 2 1 3295 * 10987654321098765432109876543210 3296 * 001000 x1110000101 3297 * rt ----- 3298 * rs ----- 3299 * rd ----- 3300 */ 3301 static char *CFC2(uint64 instruction, Dis_info *info) 3302 { 3303 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 3304 uint64 cs_value = extract_cs_20_19_18_17_16(instruction); 3305 3306 const char *rt = GPR(rt_value, info); 3307 3308 return img_format("CFC2 %s, CP%" PRIu64, rt, cs_value); 3309 } 3310 3311 3312 /* 3313 * 3314 * 3315 * 3 2 1 3316 * 10987654321098765432109876543210 3317 * 001000 x1110000101 3318 * rt ----- 3319 * rs ----- 3320 * rd ----- 3321 */ 3322 static char *CLASS_D(uint64 instruction, Dis_info *info) 3323 { 3324 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3325 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3326 3327 const char *ft = FPR(ft_value, info); 3328 const char *fs = FPR(fs_value, info); 3329 3330 return img_format("CLASS.D %s, %s", ft, fs); 3331 } 3332 3333 3334 /* 3335 * 3336 * 3337 * 3 2 1 3338 * 10987654321098765432109876543210 3339 * 001000 x1110000101 3340 * rt ----- 3341 * rs ----- 3342 * rd ----- 3343 */ 3344 static char *CLASS_S(uint64 instruction, Dis_info *info) 3345 { 3346 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3347 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3348 3349 const char *ft = FPR(ft_value, info); 3350 const char *fs = FPR(fs_value, info); 3351 3352 return img_format("CLASS.S %s, %s", ft, fs); 3353 } 3354 3355 3356 /* 3357 * 3358 * 3359 * 3 2 1 3360 * 10987654321098765432109876543210 3361 * 001000 x1110000101 3362 * rt ----- 3363 * rs ----- 3364 * rd ----- 3365 */ 3366 static char *CLO(uint64 instruction, Dis_info *info) 3367 { 3368 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 3369 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 3370 3371 const char *rt = GPR(rt_value, info); 3372 const char *rs = GPR(rs_value, info); 3373 3374 return img_format("CLO %s, %s", rt, rs); 3375 } 3376 3377 3378 /* 3379 * 3380 * 3381 * 3 2 1 3382 * 10987654321098765432109876543210 3383 * 001000 x1110000101 3384 * rt ----- 3385 * rs ----- 3386 * rd ----- 3387 */ 3388 static char *CLZ(uint64 instruction, Dis_info *info) 3389 { 3390 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 3391 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 3392 3393 const char *rt = GPR(rt_value, info); 3394 const char *rs = GPR(rs_value, info); 3395 3396 return img_format("CLZ %s, %s", rt, rs); 3397 } 3398 3399 3400 /* 3401 * 3402 * 3403 * 3 2 1 3404 * 10987654321098765432109876543210 3405 * 001000 x1110000101 3406 * rt ----- 3407 * rs ----- 3408 * rd ----- 3409 */ 3410 static char *CMP_AF_D(uint64 instruction, Dis_info *info) 3411 { 3412 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3413 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3414 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3415 3416 const char *fd = FPR(fd_value, info); 3417 const char *fs = FPR(fs_value, info); 3418 const char *ft = FPR(ft_value, info); 3419 3420 return img_format("CMP.AF.D %s, %s, %s", fd, fs, ft); 3421 } 3422 3423 3424 /* 3425 * 3426 * 3427 * 3 2 1 3428 * 10987654321098765432109876543210 3429 * 001000 x1110000101 3430 * rt ----- 3431 * rs ----- 3432 * rd ----- 3433 */ 3434 static char *CMP_AF_S(uint64 instruction, Dis_info *info) 3435 { 3436 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3437 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3438 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3439 3440 const char *fd = FPR(fd_value, info); 3441 const char *fs = FPR(fs_value, info); 3442 const char *ft = FPR(ft_value, info); 3443 3444 return img_format("CMP.AF.S %s, %s, %s", fd, fs, ft); 3445 } 3446 3447 3448 /* 3449 * 3450 * 3451 * 3 2 1 3452 * 10987654321098765432109876543210 3453 * 001000 x1110000101 3454 * rt ----- 3455 * rs ----- 3456 * rd ----- 3457 */ 3458 static char *CMP_EQ_D(uint64 instruction, Dis_info *info) 3459 { 3460 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3461 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3462 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3463 3464 const char *fd = FPR(fd_value, info); 3465 const char *fs = FPR(fs_value, info); 3466 const char *ft = FPR(ft_value, info); 3467 3468 return img_format("CMP.EQ.D %s, %s, %s", fd, fs, ft); 3469 } 3470 3471 3472 /* 3473 * [DSP] CMP.EQ.PH rs, rt - Compare vectors of signed integer halfword values 3474 * 3475 * 3 2 1 3476 * 10987654321098765432109876543210 3477 * 001000 xxxxxx0000000101 3478 * rt ----- 3479 * rs ----- 3480 */ 3481 static char *CMP_EQ_PH(uint64 instruction, Dis_info *info) 3482 { 3483 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 3484 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 3485 3486 const char *rs = GPR(rs_value, info); 3487 const char *rt = GPR(rt_value, info); 3488 3489 return img_format("CMP.EQ.PH %s, %s", rs, rt); 3490 } 3491 3492 3493 /* 3494 * 3495 * 3496 * 3 2 1 3497 * 10987654321098765432109876543210 3498 * 001000 x1110000101 3499 * rt ----- 3500 * rs ----- 3501 * rd ----- 3502 */ 3503 static char *CMP_EQ_S(uint64 instruction, Dis_info *info) 3504 { 3505 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3506 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3507 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3508 3509 const char *fd = FPR(fd_value, info); 3510 const char *fs = FPR(fs_value, info); 3511 const char *ft = FPR(ft_value, info); 3512 3513 return img_format("CMP.EQ.S %s, %s, %s", fd, fs, ft); 3514 } 3515 3516 3517 /* 3518 * 3519 * 3520 * 3 2 1 3521 * 10987654321098765432109876543210 3522 * 001000 x1110000101 3523 * rt ----- 3524 * rs ----- 3525 * rd ----- 3526 */ 3527 static char *CMP_LE_D(uint64 instruction, Dis_info *info) 3528 { 3529 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3530 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3531 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3532 3533 const char *fd = FPR(fd_value, info); 3534 const char *fs = FPR(fs_value, info); 3535 const char *ft = FPR(ft_value, info); 3536 3537 return img_format("CMP.LE.D %s, %s, %s", fd, fs, ft); 3538 } 3539 3540 3541 /* 3542 * [DSP] CMP.LE.PH rs, rt - Compare vectors of signed integer halfword values 3543 * 3544 * 3 2 1 3545 * 10987654321098765432109876543210 3546 * 001000 xxxxxx0010000101 3547 * rt ----- 3548 * rs ----- 3549 */ 3550 static char *CMP_LE_PH(uint64 instruction, Dis_info *info) 3551 { 3552 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 3553 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 3554 3555 const char *rs = GPR(rs_value, info); 3556 const char *rt = GPR(rt_value, info); 3557 3558 return img_format("CMP.LE.PH %s, %s", rs, rt); 3559 } 3560 3561 3562 /* 3563 * 3564 * 3565 * 3 2 1 3566 * 10987654321098765432109876543210 3567 * 001000 x1110000101 3568 * rt ----- 3569 * rs ----- 3570 * rd ----- 3571 */ 3572 static char *CMP_LE_S(uint64 instruction, Dis_info *info) 3573 { 3574 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3575 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3576 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3577 3578 const char *fd = FPR(fd_value, info); 3579 const char *fs = FPR(fs_value, info); 3580 const char *ft = FPR(ft_value, info); 3581 3582 return img_format("CMP.LE.S %s, %s, %s", fd, fs, ft); 3583 } 3584 3585 3586 /* 3587 * 3588 * 3589 * 3 2 1 3590 * 10987654321098765432109876543210 3591 * 001000 x1110000101 3592 * rt ----- 3593 * rs ----- 3594 * rd ----- 3595 */ 3596 static char *CMP_LT_D(uint64 instruction, Dis_info *info) 3597 { 3598 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3599 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3600 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3601 3602 const char *fd = FPR(fd_value, info); 3603 const char *fs = FPR(fs_value, info); 3604 const char *ft = FPR(ft_value, info); 3605 3606 return img_format("CMP.LT.D %s, %s, %s", fd, fs, ft); 3607 } 3608 3609 3610 /* 3611 * [DSP] CMP.LT.PH rs, rt - Compare vectors of signed integer halfword values 3612 * 3613 * 3 2 1 3614 * 10987654321098765432109876543210 3615 * 001000 xxxxxx0001000101 3616 * rt ----- 3617 * rs ----- 3618 */ 3619 static char *CMP_LT_PH(uint64 instruction, Dis_info *info) 3620 { 3621 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 3622 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 3623 3624 const char *rs = GPR(rs_value, info); 3625 const char *rt = GPR(rt_value, info); 3626 3627 return img_format("CMP.LT.PH %s, %s", rs, rt); 3628 } 3629 3630 3631 /* 3632 * 3633 * 3634 * 3 2 1 3635 * 10987654321098765432109876543210 3636 * 001000 x1110000101 3637 * rt ----- 3638 * rs ----- 3639 * rd ----- 3640 */ 3641 static char *CMP_LT_S(uint64 instruction, Dis_info *info) 3642 { 3643 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3644 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3645 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3646 3647 const char *fd = FPR(fd_value, info); 3648 const char *fs = FPR(fs_value, info); 3649 const char *ft = FPR(ft_value, info); 3650 3651 return img_format("CMP.LT.S %s, %s, %s", fd, fs, ft); 3652 } 3653 3654 3655 /* 3656 * 3657 * 3658 * 3 2 1 3659 * 10987654321098765432109876543210 3660 * 001000 x1110000101 3661 * rt ----- 3662 * rs ----- 3663 * rd ----- 3664 */ 3665 static char *CMP_NE_D(uint64 instruction, Dis_info *info) 3666 { 3667 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3668 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3669 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3670 3671 const char *fd = FPR(fd_value, info); 3672 const char *fs = FPR(fs_value, info); 3673 const char *ft = FPR(ft_value, info); 3674 3675 return img_format("CMP.NE.D %s, %s, %s", fd, fs, ft); 3676 } 3677 3678 3679 /* 3680 * 3681 * 3682 * 3 2 1 3683 * 10987654321098765432109876543210 3684 * 001000 x1110000101 3685 * rt ----- 3686 * rs ----- 3687 * rd ----- 3688 */ 3689 static char *CMP_NE_S(uint64 instruction, Dis_info *info) 3690 { 3691 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3692 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3693 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3694 3695 const char *fd = FPR(fd_value, info); 3696 const char *fs = FPR(fs_value, info); 3697 const char *ft = FPR(ft_value, info); 3698 3699 return img_format("CMP.NE.S %s, %s, %s", fd, fs, ft); 3700 } 3701 3702 3703 /* 3704 * 3705 * 3706 * 3 2 1 3707 * 10987654321098765432109876543210 3708 * 001000 x1110000101 3709 * rt ----- 3710 * rs ----- 3711 * rd ----- 3712 */ 3713 static char *CMP_OR_D(uint64 instruction, Dis_info *info) 3714 { 3715 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3716 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3717 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3718 3719 const char *fd = FPR(fd_value, info); 3720 const char *fs = FPR(fs_value, info); 3721 const char *ft = FPR(ft_value, info); 3722 3723 return img_format("CMP.OR.D %s, %s, %s", fd, fs, ft); 3724 } 3725 3726 3727 /* 3728 * 3729 * 3730 * 3 2 1 3731 * 10987654321098765432109876543210 3732 * 001000 x1110000101 3733 * rt ----- 3734 * rs ----- 3735 * rd ----- 3736 */ 3737 static char *CMP_OR_S(uint64 instruction, Dis_info *info) 3738 { 3739 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3740 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3741 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3742 3743 const char *fd = FPR(fd_value, info); 3744 const char *fs = FPR(fs_value, info); 3745 const char *ft = FPR(ft_value, info); 3746 3747 return img_format("CMP.OR.S %s, %s, %s", fd, fs, ft); 3748 } 3749 3750 3751 /* 3752 * 3753 * 3754 * 3 2 1 3755 * 10987654321098765432109876543210 3756 * 001000 x1110000101 3757 * rt ----- 3758 * rs ----- 3759 * rd ----- 3760 */ 3761 static char *CMP_SAF_D(uint64 instruction, Dis_info *info) 3762 { 3763 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3764 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3765 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3766 3767 const char *fd = FPR(fd_value, info); 3768 const char *fs = FPR(fs_value, info); 3769 const char *ft = FPR(ft_value, info); 3770 3771 return img_format("CMP.SAF.D %s, %s, %s", fd, fs, ft); 3772 } 3773 3774 3775 /* 3776 * 3777 * 3778 * 3 2 1 3779 * 10987654321098765432109876543210 3780 * 001000 x1110000101 3781 * rt ----- 3782 * rs ----- 3783 * rd ----- 3784 */ 3785 static char *CMP_SAF_S(uint64 instruction, Dis_info *info) 3786 { 3787 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3788 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3789 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3790 3791 const char *fd = FPR(fd_value, info); 3792 const char *fs = FPR(fs_value, info); 3793 const char *ft = FPR(ft_value, info); 3794 3795 return img_format("CMP.SAF.S %s, %s, %s", fd, fs, ft); 3796 } 3797 3798 3799 /* 3800 * 3801 * 3802 * 3 2 1 3803 * 10987654321098765432109876543210 3804 * 001000 x1110000101 3805 * rt ----- 3806 * rs ----- 3807 * rd ----- 3808 */ 3809 static char *CMP_SEQ_D(uint64 instruction, Dis_info *info) 3810 { 3811 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3812 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3813 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3814 3815 const char *fd = FPR(fd_value, info); 3816 const char *fs = FPR(fs_value, info); 3817 const char *ft = FPR(ft_value, info); 3818 3819 return img_format("CMP.SEQ.D %s, %s, %s", fd, fs, ft); 3820 } 3821 3822 3823 /* 3824 * 3825 * 3826 * 3 2 1 3827 * 10987654321098765432109876543210 3828 * 001000 x1110000101 3829 * rt ----- 3830 * rs ----- 3831 * rd ----- 3832 */ 3833 static char *CMP_SEQ_S(uint64 instruction, Dis_info *info) 3834 { 3835 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3836 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3837 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3838 3839 const char *fd = FPR(fd_value, info); 3840 const char *fs = FPR(fs_value, info); 3841 const char *ft = FPR(ft_value, info); 3842 3843 return img_format("CMP.SEQ.S %s, %s, %s", fd, fs, ft); 3844 } 3845 3846 3847 /* 3848 * 3849 * 3850 * 3 2 1 3851 * 10987654321098765432109876543210 3852 * 001000 x1110000101 3853 * rt ----- 3854 * rs ----- 3855 * rd ----- 3856 */ 3857 static char *CMP_SLE_D(uint64 instruction, Dis_info *info) 3858 { 3859 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3860 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3861 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3862 3863 const char *fd = FPR(fd_value, info); 3864 const char *fs = FPR(fs_value, info); 3865 const char *ft = FPR(ft_value, info); 3866 3867 return img_format("CMP.SLE.D %s, %s, %s", fd, fs, ft); 3868 } 3869 3870 3871 /* 3872 * 3873 * 3874 * 3 2 1 3875 * 10987654321098765432109876543210 3876 * 001000 x1110000101 3877 * rt ----- 3878 * rs ----- 3879 * rd ----- 3880 */ 3881 static char *CMP_SLE_S(uint64 instruction, Dis_info *info) 3882 { 3883 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3884 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3885 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3886 3887 const char *fd = FPR(fd_value, info); 3888 const char *fs = FPR(fs_value, info); 3889 const char *ft = FPR(ft_value, info); 3890 3891 return img_format("CMP.SLE.S %s, %s, %s", fd, fs, ft); 3892 } 3893 3894 3895 /* 3896 * 3897 * 3898 * 3 2 1 3899 * 10987654321098765432109876543210 3900 * 001000 x1110000101 3901 * rt ----- 3902 * rs ----- 3903 * rd ----- 3904 */ 3905 static char *CMP_SLT_D(uint64 instruction, Dis_info *info) 3906 { 3907 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3908 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3909 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3910 3911 const char *fd = FPR(fd_value, info); 3912 const char *fs = FPR(fs_value, info); 3913 const char *ft = FPR(ft_value, info); 3914 3915 return img_format("CMP.SLT.D %s, %s, %s", fd, fs, ft); 3916 } 3917 3918 3919 /* 3920 * 3921 * 3922 * 3 2 1 3923 * 10987654321098765432109876543210 3924 * 001000 x1110000101 3925 * rt ----- 3926 * rs ----- 3927 * rd ----- 3928 */ 3929 static char *CMP_SLT_S(uint64 instruction, Dis_info *info) 3930 { 3931 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3932 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3933 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3934 3935 const char *fd = FPR(fd_value, info); 3936 const char *fs = FPR(fs_value, info); 3937 const char *ft = FPR(ft_value, info); 3938 3939 return img_format("CMP.SLT.S %s, %s, %s", fd, fs, ft); 3940 } 3941 3942 3943 /* 3944 * 3945 * 3946 * 3 2 1 3947 * 10987654321098765432109876543210 3948 * 001000 x1110000101 3949 * rt ----- 3950 * rs ----- 3951 * rd ----- 3952 */ 3953 static char *CMP_SNE_D(uint64 instruction, Dis_info *info) 3954 { 3955 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3956 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3957 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3958 3959 const char *fd = FPR(fd_value, info); 3960 const char *fs = FPR(fs_value, info); 3961 const char *ft = FPR(ft_value, info); 3962 3963 return img_format("CMP.SNE.D %s, %s, %s", fd, fs, ft); 3964 } 3965 3966 3967 /* 3968 * 3969 * 3970 * 3 2 1 3971 * 10987654321098765432109876543210 3972 * 001000 x1110000101 3973 * rt ----- 3974 * rs ----- 3975 * rd ----- 3976 */ 3977 static char *CMP_SNE_S(uint64 instruction, Dis_info *info) 3978 { 3979 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 3980 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 3981 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 3982 3983 const char *fd = FPR(fd_value, info); 3984 const char *fs = FPR(fs_value, info); 3985 const char *ft = FPR(ft_value, info); 3986 3987 return img_format("CMP.SNE.S %s, %s, %s", fd, fs, ft); 3988 } 3989 3990 3991 /* 3992 * 3993 * 3994 * 3 2 1 3995 * 10987654321098765432109876543210 3996 * 001000 x1110000101 3997 * rt ----- 3998 * rs ----- 3999 * rd ----- 4000 */ 4001 static char *CMP_SOR_D(uint64 instruction, Dis_info *info) 4002 { 4003 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4004 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4005 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4006 4007 const char *fd = FPR(fd_value, info); 4008 const char *fs = FPR(fs_value, info); 4009 const char *ft = FPR(ft_value, info); 4010 4011 return img_format("CMP.SOR.D %s, %s, %s", fd, fs, ft); 4012 } 4013 4014 4015 /* 4016 * 4017 * 4018 * 3 2 1 4019 * 10987654321098765432109876543210 4020 * 001000 x1110000101 4021 * rt ----- 4022 * rs ----- 4023 * rd ----- 4024 */ 4025 static char *CMP_SOR_S(uint64 instruction, Dis_info *info) 4026 { 4027 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4028 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4029 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4030 4031 const char *fd = FPR(fd_value, info); 4032 const char *fs = FPR(fs_value, info); 4033 const char *ft = FPR(ft_value, info); 4034 4035 return img_format("CMP.SOR.S %s, %s, %s", fd, fs, ft); 4036 } 4037 4038 4039 /* 4040 * 4041 * 4042 * 3 2 1 4043 * 10987654321098765432109876543210 4044 * 001000 x1110000101 4045 * rt ----- 4046 * rs ----- 4047 * rd ----- 4048 */ 4049 static char *CMP_SUEQ_D(uint64 instruction, Dis_info *info) 4050 { 4051 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4052 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4053 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4054 4055 const char *fd = FPR(fd_value, info); 4056 const char *fs = FPR(fs_value, info); 4057 const char *ft = FPR(ft_value, info); 4058 4059 return img_format("CMP.SUEQ.D %s, %s, %s", fd, fs, ft); 4060 } 4061 4062 4063 /* 4064 * 4065 * 4066 * 3 2 1 4067 * 10987654321098765432109876543210 4068 * 001000 x1110000101 4069 * rt ----- 4070 * rs ----- 4071 * rd ----- 4072 */ 4073 static char *CMP_SUEQ_S(uint64 instruction, Dis_info *info) 4074 { 4075 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4076 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4077 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4078 4079 const char *fd = FPR(fd_value, info); 4080 const char *fs = FPR(fs_value, info); 4081 const char *ft = FPR(ft_value, info); 4082 4083 return img_format("CMP.SUEQ.S %s, %s, %s", fd, fs, ft); 4084 } 4085 4086 4087 /* 4088 * 4089 * 4090 * 3 2 1 4091 * 10987654321098765432109876543210 4092 * 001000 x1110000101 4093 * rt ----- 4094 * rs ----- 4095 * rd ----- 4096 */ 4097 static char *CMP_SULE_D(uint64 instruction, Dis_info *info) 4098 { 4099 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4100 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4101 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4102 4103 const char *fd = FPR(fd_value, info); 4104 const char *fs = FPR(fs_value, info); 4105 const char *ft = FPR(ft_value, info); 4106 4107 return img_format("CMP.SULE.D %s, %s, %s", fd, fs, ft); 4108 } 4109 4110 4111 /* 4112 * 4113 * 4114 * 3 2 1 4115 * 10987654321098765432109876543210 4116 * 001000 x1110000101 4117 * rt ----- 4118 * rs ----- 4119 * rd ----- 4120 */ 4121 static char *CMP_SULE_S(uint64 instruction, Dis_info *info) 4122 { 4123 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4124 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4125 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4126 4127 const char *fd = FPR(fd_value, info); 4128 const char *fs = FPR(fs_value, info); 4129 const char *ft = FPR(ft_value, info); 4130 4131 return img_format("CMP.SULE.S %s, %s, %s", fd, fs, ft); 4132 } 4133 4134 4135 /* 4136 * 4137 * 4138 * 3 2 1 4139 * 10987654321098765432109876543210 4140 * 001000 x1110000101 4141 * rt ----- 4142 * rs ----- 4143 * rd ----- 4144 */ 4145 static char *CMP_SULT_D(uint64 instruction, Dis_info *info) 4146 { 4147 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4148 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4149 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4150 4151 const char *fd = FPR(fd_value, info); 4152 const char *fs = FPR(fs_value, info); 4153 const char *ft = FPR(ft_value, info); 4154 4155 return img_format("CMP.SULT.D %s, %s, %s", fd, fs, ft); 4156 } 4157 4158 4159 /* 4160 * 4161 * 4162 * 3 2 1 4163 * 10987654321098765432109876543210 4164 * 001000 x1110000101 4165 * rt ----- 4166 * rs ----- 4167 * rd ----- 4168 */ 4169 static char *CMP_SULT_S(uint64 instruction, Dis_info *info) 4170 { 4171 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4172 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4173 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4174 4175 const char *fd = FPR(fd_value, info); 4176 const char *fs = FPR(fs_value, info); 4177 const char *ft = FPR(ft_value, info); 4178 4179 return img_format("CMP.SULT.S %s, %s, %s", fd, fs, ft); 4180 } 4181 4182 4183 /* 4184 * 4185 * 4186 * 3 2 1 4187 * 10987654321098765432109876543210 4188 * 001000 x1110000101 4189 * rt ----- 4190 * rs ----- 4191 * rd ----- 4192 */ 4193 static char *CMP_SUN_D(uint64 instruction, Dis_info *info) 4194 { 4195 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4196 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4197 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4198 4199 const char *fd = FPR(fd_value, info); 4200 const char *fs = FPR(fs_value, info); 4201 const char *ft = FPR(ft_value, info); 4202 4203 return img_format("CMP.SUN.D %s, %s, %s", fd, fs, ft); 4204 } 4205 4206 4207 /* 4208 * 4209 * 4210 * 3 2 1 4211 * 10987654321098765432109876543210 4212 * 001000 x1110000101 4213 * rt ----- 4214 * rs ----- 4215 * rd ----- 4216 */ 4217 static char *CMP_SUNE_D(uint64 instruction, Dis_info *info) 4218 { 4219 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4220 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4221 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4222 4223 const char *fd = FPR(fd_value, info); 4224 const char *fs = FPR(fs_value, info); 4225 const char *ft = FPR(ft_value, info); 4226 4227 return img_format("CMP.SUNE.D %s, %s, %s", fd, fs, ft); 4228 } 4229 4230 4231 /* 4232 * 4233 * 4234 * 3 2 1 4235 * 10987654321098765432109876543210 4236 * 001000 x1110000101 4237 * rt ----- 4238 * rs ----- 4239 * rd ----- 4240 */ 4241 static char *CMP_SUNE_S(uint64 instruction, Dis_info *info) 4242 { 4243 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4244 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4245 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4246 4247 const char *fd = FPR(fd_value, info); 4248 const char *fs = FPR(fs_value, info); 4249 const char *ft = FPR(ft_value, info); 4250 4251 return img_format("CMP.SUNE.S %s, %s, %s", fd, fs, ft); 4252 } 4253 4254 4255 /* 4256 * 4257 * 4258 * 3 2 1 4259 * 10987654321098765432109876543210 4260 * 001000 x1110000101 4261 * rt ----- 4262 * rs ----- 4263 * rd ----- 4264 */ 4265 static char *CMP_SUN_S(uint64 instruction, Dis_info *info) 4266 { 4267 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4268 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4269 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4270 4271 const char *fd = FPR(fd_value, info); 4272 const char *fs = FPR(fs_value, info); 4273 const char *ft = FPR(ft_value, info); 4274 4275 return img_format("CMP.SUN.S %s, %s, %s", fd, fs, ft); 4276 } 4277 4278 4279 /* 4280 * 4281 * 4282 * 3 2 1 4283 * 10987654321098765432109876543210 4284 * 001000 x1110000101 4285 * rt ----- 4286 * rs ----- 4287 * rd ----- 4288 */ 4289 static char *CMP_UEQ_D(uint64 instruction, Dis_info *info) 4290 { 4291 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4292 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4293 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4294 4295 const char *fd = FPR(fd_value, info); 4296 const char *fs = FPR(fs_value, info); 4297 const char *ft = FPR(ft_value, info); 4298 4299 return img_format("CMP.UEQ.D %s, %s, %s", fd, fs, ft); 4300 } 4301 4302 4303 /* 4304 * 4305 * 4306 * 3 2 1 4307 * 10987654321098765432109876543210 4308 * 001000 x1110000101 4309 * rt ----- 4310 * rs ----- 4311 * rd ----- 4312 */ 4313 static char *CMP_UEQ_S(uint64 instruction, Dis_info *info) 4314 { 4315 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4316 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4317 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4318 4319 const char *fd = FPR(fd_value, info); 4320 const char *fs = FPR(fs_value, info); 4321 const char *ft = FPR(ft_value, info); 4322 4323 return img_format("CMP.UEQ.S %s, %s, %s", fd, fs, ft); 4324 } 4325 4326 4327 /* 4328 * 4329 * 4330 * 3 2 1 4331 * 10987654321098765432109876543210 4332 * 001000 x1110000101 4333 * rt ----- 4334 * rs ----- 4335 * rd ----- 4336 */ 4337 static char *CMP_ULE_D(uint64 instruction, Dis_info *info) 4338 { 4339 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4340 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4341 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4342 4343 const char *fd = FPR(fd_value, info); 4344 const char *fs = FPR(fs_value, info); 4345 const char *ft = FPR(ft_value, info); 4346 4347 return img_format("CMP.ULE.D %s, %s, %s", fd, fs, ft); 4348 } 4349 4350 4351 /* 4352 * 4353 * 4354 * 3 2 1 4355 * 10987654321098765432109876543210 4356 * 001000 x1110000101 4357 * rt ----- 4358 * rs ----- 4359 * rd ----- 4360 */ 4361 static char *CMP_ULE_S(uint64 instruction, Dis_info *info) 4362 { 4363 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4364 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4365 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4366 4367 const char *fd = FPR(fd_value, info); 4368 const char *fs = FPR(fs_value, info); 4369 const char *ft = FPR(ft_value, info); 4370 4371 return img_format("CMP.ULE.S %s, %s, %s", fd, fs, ft); 4372 } 4373 4374 4375 /* 4376 * 4377 * 4378 * 3 2 1 4379 * 10987654321098765432109876543210 4380 * 001000 x1110000101 4381 * rt ----- 4382 * rs ----- 4383 * rd ----- 4384 */ 4385 static char *CMP_ULT_D(uint64 instruction, Dis_info *info) 4386 { 4387 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4388 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4389 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4390 4391 const char *fd = FPR(fd_value, info); 4392 const char *fs = FPR(fs_value, info); 4393 const char *ft = FPR(ft_value, info); 4394 4395 return img_format("CMP.ULT.D %s, %s, %s", fd, fs, ft); 4396 } 4397 4398 4399 /* 4400 * 4401 * 4402 * 3 2 1 4403 * 10987654321098765432109876543210 4404 * 001000 x1110000101 4405 * rt ----- 4406 * rs ----- 4407 * rd ----- 4408 */ 4409 static char *CMP_ULT_S(uint64 instruction, Dis_info *info) 4410 { 4411 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4412 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4413 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4414 4415 const char *fd = FPR(fd_value, info); 4416 const char *fs = FPR(fs_value, info); 4417 const char *ft = FPR(ft_value, info); 4418 4419 return img_format("CMP.ULT.S %s, %s, %s", fd, fs, ft); 4420 } 4421 4422 4423 /* 4424 * 4425 * 4426 * 3 2 1 4427 * 10987654321098765432109876543210 4428 * 001000 x1110000101 4429 * rt ----- 4430 * rs ----- 4431 * rd ----- 4432 */ 4433 static char *CMP_UN_D(uint64 instruction, Dis_info *info) 4434 { 4435 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4436 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4437 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4438 4439 const char *fd = FPR(fd_value, info); 4440 const char *fs = FPR(fs_value, info); 4441 const char *ft = FPR(ft_value, info); 4442 4443 return img_format("CMP.UN.D %s, %s, %s", fd, fs, ft); 4444 } 4445 4446 4447 /* 4448 * 4449 * 4450 * 3 2 1 4451 * 10987654321098765432109876543210 4452 * 001000 x1110000101 4453 * rt ----- 4454 * rs ----- 4455 * rd ----- 4456 */ 4457 static char *CMP_UNE_D(uint64 instruction, Dis_info *info) 4458 { 4459 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4460 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4461 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4462 4463 const char *fd = FPR(fd_value, info); 4464 const char *fs = FPR(fs_value, info); 4465 const char *ft = FPR(ft_value, info); 4466 4467 return img_format("CMP.UNE.D %s, %s, %s", fd, fs, ft); 4468 } 4469 4470 4471 /* 4472 * 4473 * 4474 * 3 2 1 4475 * 10987654321098765432109876543210 4476 * 001000 x1110000101 4477 * rt ----- 4478 * rs ----- 4479 * rd ----- 4480 */ 4481 static char *CMP_UNE_S(uint64 instruction, Dis_info *info) 4482 { 4483 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4484 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4485 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4486 4487 const char *fd = FPR(fd_value, info); 4488 const char *fs = FPR(fs_value, info); 4489 const char *ft = FPR(ft_value, info); 4490 4491 return img_format("CMP.UNE.S %s, %s, %s", fd, fs, ft); 4492 } 4493 4494 4495 /* 4496 * 4497 * 4498 * 3 2 1 4499 * 10987654321098765432109876543210 4500 * 001000 x1110000101 4501 * rt ----- 4502 * rs ----- 4503 * rd ----- 4504 */ 4505 static char *CMP_UN_S(uint64 instruction, Dis_info *info) 4506 { 4507 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4508 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4509 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 4510 4511 const char *fd = FPR(fd_value, info); 4512 const char *fs = FPR(fs_value, info); 4513 const char *ft = FPR(ft_value, info); 4514 4515 return img_format("CMP.UN.S %s, %s, %s", fd, fs, ft); 4516 } 4517 4518 4519 /* 4520 * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of 4521 * four bytes and write result to GPR and DSPControl 4522 * 4523 * 3 2 1 4524 * 10987654321098765432109876543210 4525 * 001000 x0110000101 4526 * rt ----- 4527 * rs ----- 4528 * rd ----- 4529 */ 4530 static char *CMPGDU_EQ_QB(uint64 instruction, Dis_info *info) 4531 { 4532 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 4533 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 4534 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 4535 4536 const char *rd = GPR(rd_value, info); 4537 const char *rs = GPR(rs_value, info); 4538 const char *rt = GPR(rt_value, info); 4539 4540 return img_format("CMPGDU.EQ.QB %s, %s, %s", rd, rs, rt); 4541 } 4542 4543 4544 /* 4545 * [DSP] CMPGDU.LE.QB rd, rs, rt - Compare unsigned vector of 4546 * four bytes and write result to GPR and DSPControl 4547 * 4548 * 3 2 1 4549 * 10987654321098765432109876543210 4550 * 001000 x1000000101 4551 * rt ----- 4552 * rs ----- 4553 * rd ----- 4554 */ 4555 static char *CMPGDU_LE_QB(uint64 instruction, Dis_info *info) 4556 { 4557 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 4558 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 4559 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 4560 4561 const char *rd = GPR(rd_value, info); 4562 const char *rs = GPR(rs_value, info); 4563 const char *rt = GPR(rt_value, info); 4564 4565 return img_format("CMPGDU.LE.QB %s, %s, %s", rd, rs, rt); 4566 } 4567 4568 4569 /* 4570 * [DSP] CMPGDU.EQ.QB rd, rs, rt - Compare unsigned vector of 4571 * four bytes and write result to GPR and DSPControl 4572 * 4573 * 3 2 1 4574 * 10987654321098765432109876543210 4575 * 001000 x0111000101 4576 * rt ----- 4577 * rs ----- 4578 * rd ----- 4579 */ 4580 static char *CMPGDU_LT_QB(uint64 instruction, Dis_info *info) 4581 { 4582 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 4583 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 4584 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 4585 4586 const char *rd = GPR(rd_value, info); 4587 const char *rs = GPR(rs_value, info); 4588 const char *rt = GPR(rt_value, info); 4589 4590 return img_format("CMPGDU.LT.QB %s, %s, %s", rd, rs, rt); 4591 } 4592 4593 4594 /* 4595 * [DSP] CMPGU.EQ.QB rd, rs, rt - Compare vectors of unsigned 4596 * byte values and write result to a GPR 4597 * 4598 * 3 2 1 4599 * 10987654321098765432109876543210 4600 * 001000 x0011000101 4601 * rt ----- 4602 * rs ----- 4603 * rd ----- 4604 */ 4605 static char *CMPGU_EQ_QB(uint64 instruction, Dis_info *info) 4606 { 4607 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 4608 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 4609 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 4610 4611 const char *rd = GPR(rd_value, info); 4612 const char *rs = GPR(rs_value, info); 4613 const char *rt = GPR(rt_value, info); 4614 4615 return img_format("CMPGU.EQ.QB %s, %s, %s", rd, rs, rt); 4616 } 4617 4618 4619 /* 4620 * [DSP] CMPGU.LE.QB rd, rs, rt - Compare vectors of unsigned 4621 * byte values and write result to a GPR 4622 * 4623 * 3 2 1 4624 * 10987654321098765432109876543210 4625 * 001000 x0101000101 4626 * rt ----- 4627 * rs ----- 4628 * rd ----- 4629 */ 4630 static char *CMPGU_LE_QB(uint64 instruction, Dis_info *info) 4631 { 4632 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 4633 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 4634 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 4635 4636 const char *rd = GPR(rd_value, info); 4637 const char *rs = GPR(rs_value, info); 4638 const char *rt = GPR(rt_value, info); 4639 4640 return img_format("CMPGU.LE.QB %s, %s, %s", rd, rs, rt); 4641 } 4642 4643 4644 /* 4645 * [DSP] CMPGU.LT.QB rd, rs, rt - Compare vectors of unsigned 4646 * byte values and write result to a GPR 4647 * 4648 * 3 2 1 4649 * 10987654321098765432109876543210 4650 * 001000 x0100000101 4651 * rt ----- 4652 * rs ----- 4653 * rd ----- 4654 */ 4655 static char *CMPGU_LT_QB(uint64 instruction, Dis_info *info) 4656 { 4657 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 4658 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 4659 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 4660 4661 const char *rd = GPR(rd_value, info); 4662 const char *rs = GPR(rs_value, info); 4663 const char *rt = GPR(rt_value, info); 4664 4665 return img_format("CMPGU.LT.QB %s, %s, %s", rd, rs, rt); 4666 } 4667 4668 4669 /* 4670 * [DSP] CMPU.EQ.QB rd, rs, rt - Compare vectors of unsigned 4671 * byte values 4672 * 4673 * 3 2 1 4674 * 10987654321098765432109876543210 4675 * 001000 xxxxxx1001000101 4676 * rt ----- 4677 * rs ----- 4678 */ 4679 static char *CMPU_EQ_QB(uint64 instruction, Dis_info *info) 4680 { 4681 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 4682 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 4683 4684 const char *rs = GPR(rs_value, info); 4685 const char *rt = GPR(rt_value, info); 4686 4687 return img_format("CMPU.EQ.QB %s, %s", rs, rt); 4688 } 4689 4690 4691 /* 4692 * [DSP] CMPU.LE.QB rd, rs, rt - Compare vectors of unsigned 4693 * byte values 4694 * 4695 * 3 2 1 4696 * 10987654321098765432109876543210 4697 * 001000 xxxxxx1011000101 4698 * rt ----- 4699 * rs ----- 4700 */ 4701 static char *CMPU_LE_QB(uint64 instruction, Dis_info *info) 4702 { 4703 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 4704 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 4705 4706 const char *rs = GPR(rs_value, info); 4707 const char *rt = GPR(rt_value, info); 4708 4709 return img_format("CMPU.LE.QB %s, %s", rs, rt); 4710 } 4711 4712 4713 /* 4714 * [DSP] CMPU.LT.QB rd, rs, rt - Compare vectors of unsigned 4715 * byte values 4716 * 4717 * 3 2 1 4718 * 10987654321098765432109876543210 4719 * 001000 xxxxxx1010000101 4720 * rt ----- 4721 * rs ----- 4722 */ 4723 static char *CMPU_LT_QB(uint64 instruction, Dis_info *info) 4724 { 4725 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 4726 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 4727 4728 const char *rs = GPR(rs_value, info); 4729 const char *rt = GPR(rt_value, info); 4730 4731 return img_format("CMPU.LT.QB %s, %s", rs, rt); 4732 } 4733 4734 4735 /* 4736 * 4737 * 4738 * 3 2 1 4739 * 10987654321098765432109876543210 4740 * 001000 x1110000101 4741 * rt ----- 4742 * rs ----- 4743 * rd ----- 4744 */ 4745 static char *COP2_1(uint64 instruction, Dis_info *info) 4746 { 4747 uint64 cofun_value = extract_cofun_25_24_23(instruction); 4748 4749 4750 return img_format("COP2_1 0x%" PRIx64, cofun_value); 4751 } 4752 4753 4754 /* 4755 * 4756 * 4757 * 3 2 1 4758 * 10987654321098765432109876543210 4759 * 001000 x1110000101 4760 * rt ----- 4761 * rs ----- 4762 * rd ----- 4763 */ 4764 static char *CTC1(uint64 instruction, Dis_info *info) 4765 { 4766 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 4767 uint64 cs_value = extract_cs_20_19_18_17_16(instruction); 4768 4769 const char *rt = GPR(rt_value, info); 4770 4771 return img_format("CTC1 %s, CP%" PRIu64, rt, cs_value); 4772 } 4773 4774 4775 /* 4776 * 4777 * 4778 * 3 2 1 4779 * 10987654321098765432109876543210 4780 * 001000 x1110000101 4781 * rt ----- 4782 * rs ----- 4783 * rd ----- 4784 */ 4785 static char *CTC2(uint64 instruction, Dis_info *info) 4786 { 4787 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 4788 uint64 cs_value = extract_cs_20_19_18_17_16(instruction); 4789 4790 const char *rt = GPR(rt_value, info); 4791 4792 return img_format("CTC2 %s, CP%" PRIu64, rt, cs_value); 4793 } 4794 4795 4796 /* 4797 * 4798 * 4799 * 3 2 1 4800 * 10987654321098765432109876543210 4801 * 001000 x1110000101 4802 * rt ----- 4803 * rs ----- 4804 * rd ----- 4805 */ 4806 static char *CVT_D_L(uint64 instruction, Dis_info *info) 4807 { 4808 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4809 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4810 4811 const char *ft = FPR(ft_value, info); 4812 const char *fs = FPR(fs_value, info); 4813 4814 return img_format("CVT.D.L %s, %s", ft, fs); 4815 } 4816 4817 4818 /* 4819 * 4820 * 4821 * 3 2 1 4822 * 10987654321098765432109876543210 4823 * 001000 x1110000101 4824 * rt ----- 4825 * rs ----- 4826 * rd ----- 4827 */ 4828 static char *CVT_D_S(uint64 instruction, Dis_info *info) 4829 { 4830 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4831 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4832 4833 const char *ft = FPR(ft_value, info); 4834 const char *fs = FPR(fs_value, info); 4835 4836 return img_format("CVT.D.S %s, %s", ft, fs); 4837 } 4838 4839 4840 /* 4841 * 4842 * 4843 * 3 2 1 4844 * 10987654321098765432109876543210 4845 * 001000 x1110000101 4846 * rt ----- 4847 * rs ----- 4848 * rd ----- 4849 */ 4850 static char *CVT_D_W(uint64 instruction, Dis_info *info) 4851 { 4852 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4853 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4854 4855 const char *ft = FPR(ft_value, info); 4856 const char *fs = FPR(fs_value, info); 4857 4858 return img_format("CVT.D.W %s, %s", ft, fs); 4859 } 4860 4861 4862 /* 4863 * 4864 * 4865 * 3 2 1 4866 * 10987654321098765432109876543210 4867 * 001000 x1110000101 4868 * rt ----- 4869 * rs ----- 4870 * rd ----- 4871 */ 4872 static char *CVT_L_D(uint64 instruction, Dis_info *info) 4873 { 4874 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4875 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4876 4877 const char *ft = FPR(ft_value, info); 4878 const char *fs = FPR(fs_value, info); 4879 4880 return img_format("CVT.L.D %s, %s", ft, fs); 4881 } 4882 4883 4884 /* 4885 * 4886 * 4887 * 3 2 1 4888 * 10987654321098765432109876543210 4889 * 001000 x1110000101 4890 * rt ----- 4891 * rs ----- 4892 * rd ----- 4893 */ 4894 static char *CVT_L_S(uint64 instruction, Dis_info *info) 4895 { 4896 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4897 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4898 4899 const char *ft = FPR(ft_value, info); 4900 const char *fs = FPR(fs_value, info); 4901 4902 return img_format("CVT.L.S %s, %s", ft, fs); 4903 } 4904 4905 4906 /* 4907 * 4908 * 4909 * 3 2 1 4910 * 10987654321098765432109876543210 4911 * 001000 x1110000101 4912 * rt ----- 4913 * rs ----- 4914 * rd ----- 4915 */ 4916 static char *CVT_S_D(uint64 instruction, Dis_info *info) 4917 { 4918 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4919 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4920 4921 const char *ft = FPR(ft_value, info); 4922 const char *fs = FPR(fs_value, info); 4923 4924 return img_format("CVT.S.D %s, %s", ft, fs); 4925 } 4926 4927 4928 /* 4929 * 4930 * 4931 * 3 2 1 4932 * 10987654321098765432109876543210 4933 * 001000 x1110000101 4934 * rt ----- 4935 * rs ----- 4936 * rd ----- 4937 */ 4938 static char *CVT_S_L(uint64 instruction, Dis_info *info) 4939 { 4940 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4941 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4942 4943 const char *ft = FPR(ft_value, info); 4944 const char *fs = FPR(fs_value, info); 4945 4946 return img_format("CVT.S.L %s, %s", ft, fs); 4947 } 4948 4949 4950 /* 4951 * 4952 * 4953 * 3 2 1 4954 * 10987654321098765432109876543210 4955 * 001000 x1110000101 4956 * rt ----- 4957 * rs ----- 4958 * rd ----- 4959 */ 4960 static char *CVT_S_PL(uint64 instruction, Dis_info *info) 4961 { 4962 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4963 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4964 4965 const char *ft = FPR(ft_value, info); 4966 const char *fs = FPR(fs_value, info); 4967 4968 return img_format("CVT.S.PL %s, %s", ft, fs); 4969 } 4970 4971 4972 /* 4973 * 4974 * 4975 * 3 2 1 4976 * 10987654321098765432109876543210 4977 * 001000 x1110000101 4978 * rt ----- 4979 * rs ----- 4980 * rd ----- 4981 */ 4982 static char *CVT_S_PU(uint64 instruction, Dis_info *info) 4983 { 4984 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 4985 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 4986 4987 const char *ft = FPR(ft_value, info); 4988 const char *fs = FPR(fs_value, info); 4989 4990 return img_format("CVT.S.PU %s, %s", ft, fs); 4991 } 4992 4993 4994 /* 4995 * 4996 * 4997 * 3 2 1 4998 * 10987654321098765432109876543210 4999 * 001000 x1110000101 5000 * rt ----- 5001 * rs ----- 5002 * rd ----- 5003 */ 5004 static char *CVT_S_W(uint64 instruction, Dis_info *info) 5005 { 5006 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 5007 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 5008 5009 const char *ft = FPR(ft_value, info); 5010 const char *fs = FPR(fs_value, info); 5011 5012 return img_format("CVT.S.W %s, %s", ft, fs); 5013 } 5014 5015 5016 /* 5017 * 5018 * 5019 * 3 2 1 5020 * 10987654321098765432109876543210 5021 * 001000 x1110000101 5022 * rt ----- 5023 * rs ----- 5024 * rd ----- 5025 */ 5026 static char *CVT_W_D(uint64 instruction, Dis_info *info) 5027 { 5028 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 5029 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 5030 5031 const char *ft = FPR(ft_value, info); 5032 const char *fs = FPR(fs_value, info); 5033 5034 return img_format("CVT.W.D %s, %s", ft, fs); 5035 } 5036 5037 5038 /* 5039 * 5040 * 5041 * 3 2 1 5042 * 10987654321098765432109876543210 5043 * 001000 x1110000101 5044 * rt ----- 5045 * rs ----- 5046 * rd ----- 5047 */ 5048 static char *CVT_W_S(uint64 instruction, Dis_info *info) 5049 { 5050 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 5051 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 5052 5053 const char *ft = FPR(ft_value, info); 5054 const char *fs = FPR(fs_value, info); 5055 5056 return img_format("CVT.W.S %s, %s", ft, fs); 5057 } 5058 5059 5060 /* 5061 * 5062 * 5063 * 3 2 1 5064 * 10987654321098765432109876543210 5065 * 001000 x1110000101 5066 * rt ----- 5067 * rs ----- 5068 * rd ----- 5069 */ 5070 static char *DADDIU_48_(uint64 instruction, Dis_info *info) 5071 { 5072 uint64 rt_value = extract_rt_41_40_39_38_37(instruction); 5073 int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); 5074 5075 const char *rt = GPR(rt_value, info); 5076 5077 return img_format("DADDIU %s, %" PRId64, rt, s_value); 5078 } 5079 5080 5081 /* 5082 * 5083 * 5084 * 3 2 1 5085 * 10987654321098765432109876543210 5086 * 001000 x1110000101 5087 * rt ----- 5088 * rs ----- 5089 * rd ----- 5090 */ 5091 static char *DADDIU_NEG_(uint64 instruction, Dis_info *info) 5092 { 5093 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5094 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5095 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 5096 5097 const char *rt = GPR(rt_value, info); 5098 const char *rs = GPR(rs_value, info); 5099 int64 u = neg_copy(u_value); 5100 5101 return img_format("DADDIU %s, %s, %" PRId64, rt, rs, u); 5102 } 5103 5104 5105 /* 5106 * 5107 * 5108 * 3 2 1 5109 * 10987654321098765432109876543210 5110 * 001000 x1110000101 5111 * rt ----- 5112 * rs ----- 5113 * rd ----- 5114 */ 5115 static char *DADDIU_U12_(uint64 instruction, Dis_info *info) 5116 { 5117 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5118 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5119 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 5120 5121 const char *rt = GPR(rt_value, info); 5122 const char *rs = GPR(rs_value, info); 5123 5124 return img_format("DADDIU %s, %s, 0x%" PRIx64, rt, rs, u_value); 5125 } 5126 5127 5128 /* 5129 * 5130 * 5131 * 3 2 1 5132 * 10987654321098765432109876543210 5133 * 001000 x1110000101 5134 * rt ----- 5135 * rs ----- 5136 * rd ----- 5137 */ 5138 static char *DADD(uint64 instruction, Dis_info *info) 5139 { 5140 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5141 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5142 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5143 5144 const char *rd = GPR(rd_value, info); 5145 const char *rs = GPR(rs_value, info); 5146 const char *rt = GPR(rt_value, info); 5147 5148 return img_format("DADD %s, %s, %s", rd, rs, rt); 5149 } 5150 5151 5152 /* 5153 * 5154 * 5155 * 3 2 1 5156 * 10987654321098765432109876543210 5157 * 001000 x1110000101 5158 * rt ----- 5159 * rs ----- 5160 * rd ----- 5161 */ 5162 static char *DADDU(uint64 instruction, Dis_info *info) 5163 { 5164 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5165 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5166 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5167 5168 const char *rd = GPR(rd_value, info); 5169 const char *rs = GPR(rs_value, info); 5170 const char *rt = GPR(rt_value, info); 5171 5172 return img_format("DADDU %s, %s, %s", rd, rs, rt); 5173 } 5174 5175 5176 /* 5177 * 5178 * 5179 * 3 2 1 5180 * 10987654321098765432109876543210 5181 * 001000 x1110000101 5182 * rt ----- 5183 * rs ----- 5184 * rd ----- 5185 */ 5186 static char *DCLO(uint64 instruction, Dis_info *info) 5187 { 5188 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5189 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5190 5191 const char *rt = GPR(rt_value, info); 5192 const char *rs = GPR(rs_value, info); 5193 5194 return img_format("DCLO %s, %s", rt, rs); 5195 } 5196 5197 5198 /* 5199 * 5200 * 5201 * 3 2 1 5202 * 10987654321098765432109876543210 5203 * 001000 x1110000101 5204 * rt ----- 5205 * rs ----- 5206 * rd ----- 5207 */ 5208 static char *DCLZ(uint64 instruction, Dis_info *info) 5209 { 5210 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5211 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5212 5213 const char *rt = GPR(rt_value, info); 5214 const char *rs = GPR(rs_value, info); 5215 5216 return img_format("DCLZ %s, %s", rt, rs); 5217 } 5218 5219 5220 /* 5221 * 5222 * 5223 * 3 2 1 5224 * 10987654321098765432109876543210 5225 * 001000 x1110000101 5226 * rt ----- 5227 * rs ----- 5228 * rd ----- 5229 */ 5230 static char *DDIV(uint64 instruction, Dis_info *info) 5231 { 5232 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5233 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5234 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5235 5236 const char *rd = GPR(rd_value, info); 5237 const char *rs = GPR(rs_value, info); 5238 const char *rt = GPR(rt_value, info); 5239 5240 return img_format("DDIV %s, %s, %s", rd, rs, rt); 5241 } 5242 5243 5244 /* 5245 * 5246 * 5247 * 3 2 1 5248 * 10987654321098765432109876543210 5249 * 001000 x1110000101 5250 * rt ----- 5251 * rs ----- 5252 * rd ----- 5253 */ 5254 static char *DDIVU(uint64 instruction, Dis_info *info) 5255 { 5256 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5257 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5258 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5259 5260 const char *rd = GPR(rd_value, info); 5261 const char *rs = GPR(rs_value, info); 5262 const char *rt = GPR(rt_value, info); 5263 5264 return img_format("DDIVU %s, %s, %s", rd, rs, rt); 5265 } 5266 5267 5268 /* 5269 * 5270 * 5271 * 3 2 1 5272 * 10987654321098765432109876543210 5273 * 001000 x1110000101 5274 * rt ----- 5275 * rs ----- 5276 * rd ----- 5277 */ 5278 static char *DERET(uint64 instruction, Dis_info *info) 5279 { 5280 (void)instruction; 5281 5282 return g_strdup("DERET "); 5283 } 5284 5285 5286 /* 5287 * 5288 * 5289 * 3 2 1 5290 * 10987654321098765432109876543210 5291 * 001000 x1110000101 5292 * rt ----- 5293 * rs ----- 5294 * rd ----- 5295 */ 5296 static char *DEXTM(uint64 instruction, Dis_info *info) 5297 { 5298 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5299 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5300 uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); 5301 uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); 5302 5303 const char *rt = GPR(rt_value, info); 5304 const char *rs = GPR(rs_value, info); 5305 uint64 msbd = encode_msbd_from_size(msbd_value); 5306 5307 return img_format("DEXTM %s, %s, 0x%" PRIx64 ", 0x%" PRIx64, 5308 rt, rs, lsb_value, msbd); 5309 } 5310 5311 5312 /* 5313 * 5314 * 5315 * 3 2 1 5316 * 10987654321098765432109876543210 5317 * 001000 x1110000101 5318 * rt ----- 5319 * rs ----- 5320 * rd ----- 5321 */ 5322 static char *DEXT(uint64 instruction, Dis_info *info) 5323 { 5324 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5325 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5326 uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); 5327 uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); 5328 5329 const char *rt = GPR(rt_value, info); 5330 const char *rs = GPR(rs_value, info); 5331 uint64 msbd = encode_msbd_from_size(msbd_value); 5332 5333 return img_format("DEXT %s, %s, 0x%" PRIx64 ", 0x%" PRIx64, 5334 rt, rs, lsb_value, msbd); 5335 } 5336 5337 5338 /* 5339 * 5340 * 5341 * 3 2 1 5342 * 10987654321098765432109876543210 5343 * 001000 x1110000101 5344 * rt ----- 5345 * rs ----- 5346 * rd ----- 5347 */ 5348 static char *DEXTU(uint64 instruction, Dis_info *info) 5349 { 5350 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5351 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5352 uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); 5353 uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); 5354 5355 const char *rt = GPR(rt_value, info); 5356 const char *rs = GPR(rs_value, info); 5357 uint64 msbd = encode_msbd_from_size(msbd_value); 5358 5359 return img_format("DEXTU %s, %s, 0x%" PRIx64 ", 0x%" PRIx64, 5360 rt, rs, lsb_value, msbd); 5361 } 5362 5363 5364 /* 5365 * 5366 * 5367 * 3 2 1 5368 * 10987654321098765432109876543210 5369 * 001000 x1110000101 5370 * rt ----- 5371 * rs ----- 5372 * rd ----- 5373 */ 5374 static char *DINSM(uint64 instruction, Dis_info *info) 5375 { 5376 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5377 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5378 uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); 5379 uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); 5380 5381 const char *rt = GPR(rt_value, info); 5382 const char *rs = GPR(rs_value, info); 5383 /* !!!!!!!!!! - no conversion function */ 5384 5385 return img_format("DINSM %s, %s, 0x%" PRIx64 ", 0x%" PRIx64, 5386 rt, rs, lsb_value, msbd_value); 5387 /* hand edited */ 5388 } 5389 5390 5391 /* 5392 * 5393 * 5394 * 3 2 1 5395 * 10987654321098765432109876543210 5396 * 001000 x1110000101 5397 * rt ----- 5398 * rs ----- 5399 * rd ----- 5400 */ 5401 static char *DINS(uint64 instruction, Dis_info *info) 5402 { 5403 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5404 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5405 uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); 5406 uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); 5407 5408 const char *rt = GPR(rt_value, info); 5409 const char *rs = GPR(rs_value, info); 5410 /* !!!!!!!!!! - no conversion function */ 5411 5412 return img_format("DINS %s, %s, 0x%" PRIx64 ", 0x%" PRIx64, 5413 rt, rs, lsb_value, msbd_value); 5414 /* hand edited */ 5415 } 5416 5417 5418 /* 5419 * 5420 * 5421 * 3 2 1 5422 * 10987654321098765432109876543210 5423 * 001000 x1110000101 5424 * rt ----- 5425 * rs ----- 5426 * rd ----- 5427 */ 5428 static char *DINSU(uint64 instruction, Dis_info *info) 5429 { 5430 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5431 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5432 uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); 5433 uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); 5434 5435 const char *rt = GPR(rt_value, info); 5436 const char *rs = GPR(rs_value, info); 5437 /* !!!!!!!!!! - no conversion function */ 5438 5439 return img_format("DINSU %s, %s, 0x%" PRIx64 ", 0x%" PRIx64, 5440 rt, rs, lsb_value, msbd_value); 5441 /* hand edited */ 5442 } 5443 5444 5445 /* 5446 * 5447 * 5448 * 3 2 1 5449 * 10987654321098765432109876543210 5450 * 001000 x1110000101 5451 * rt ----- 5452 * rs ----- 5453 * rd ----- 5454 */ 5455 static char *DI(uint64 instruction, Dis_info *info) 5456 { 5457 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5458 5459 const char *rt = GPR(rt_value, info); 5460 5461 return img_format("DI %s", rt); 5462 } 5463 5464 5465 /* 5466 * 5467 * 5468 * 3 2 1 5469 * 10987654321098765432109876543210 5470 * 001000 x1110000101 5471 * rt ----- 5472 * rs ----- 5473 * rd ----- 5474 */ 5475 static char *DIV(uint64 instruction, Dis_info *info) 5476 { 5477 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5478 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5479 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5480 5481 const char *rd = GPR(rd_value, info); 5482 const char *rs = GPR(rs_value, info); 5483 const char *rt = GPR(rt_value, info); 5484 5485 return img_format("DIV %s, %s, %s", rd, rs, rt); 5486 } 5487 5488 5489 /* 5490 * 5491 * 5492 * 3 2 1 5493 * 10987654321098765432109876543210 5494 * 001000 x1110000101 5495 * rt ----- 5496 * rs ----- 5497 * rd ----- 5498 */ 5499 static char *DIV_D(uint64 instruction, Dis_info *info) 5500 { 5501 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 5502 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 5503 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 5504 5505 const char *fd = FPR(fd_value, info); 5506 const char *fs = FPR(fs_value, info); 5507 const char *ft = FPR(ft_value, info); 5508 5509 return img_format("DIV.D %s, %s, %s", fd, fs, ft); 5510 } 5511 5512 5513 /* 5514 * 5515 * 5516 * 3 2 1 5517 * 10987654321098765432109876543210 5518 * 001000 x1110000101 5519 * rt ----- 5520 * rs ----- 5521 * rd ----- 5522 */ 5523 static char *DIV_S(uint64 instruction, Dis_info *info) 5524 { 5525 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 5526 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 5527 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 5528 5529 const char *fd = FPR(fd_value, info); 5530 const char *fs = FPR(fs_value, info); 5531 const char *ft = FPR(ft_value, info); 5532 5533 return img_format("DIV.S %s, %s, %s", fd, fs, ft); 5534 } 5535 5536 5537 /* 5538 * 5539 * 5540 * 3 2 1 5541 * 10987654321098765432109876543210 5542 * 001000 x1110000101 5543 * rt ----- 5544 * rs ----- 5545 * rd ----- 5546 */ 5547 static char *DIVU(uint64 instruction, Dis_info *info) 5548 { 5549 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5550 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5551 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5552 5553 const char *rd = GPR(rd_value, info); 5554 const char *rs = GPR(rs_value, info); 5555 const char *rt = GPR(rt_value, info); 5556 5557 return img_format("DIVU %s, %s, %s", rd, rs, rt); 5558 } 5559 5560 5561 /* 5562 * 5563 * 5564 * 3 2 1 5565 * 10987654321098765432109876543210 5566 * 001000 x1110000101 5567 * rt ----- 5568 * rs ----- 5569 * rd ----- 5570 */ 5571 static char *DLSA(uint64 instruction, Dis_info *info) 5572 { 5573 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5574 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5575 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5576 uint64 u2_value = extract_u2_10_9(instruction); 5577 5578 const char *rd = GPR(rd_value, info); 5579 const char *rs = GPR(rs_value, info); 5580 const char *rt = GPR(rt_value, info); 5581 5582 return img_format("DLSA %s, %s, %s, 0x%" PRIx64, rd, rs, rt, u2_value); 5583 } 5584 5585 5586 /* 5587 * 5588 * 5589 * 3 2 1 5590 * 10987654321098765432109876543210 5591 * 001000 x1110000101 5592 * rt ----- 5593 * rs ----- 5594 * rd ----- 5595 */ 5596 static char *DLUI_48_(uint64 instruction, Dis_info *info) 5597 { 5598 uint64 rt_value = extract_rt_41_40_39_38_37(instruction); 5599 uint64 u_value = extract_u_31_to_0__s32(instruction); 5600 5601 const char *rt = GPR(rt_value, info); 5602 5603 return img_format("DLUI %s, 0x%" PRIx64, rt, u_value); 5604 } 5605 5606 5607 /* 5608 * 5609 * 5610 * 3 2 1 5611 * 10987654321098765432109876543210 5612 * 001000 x1110000101 5613 * rt ----- 5614 * rs ----- 5615 * rd ----- 5616 */ 5617 static char *DMFC0(uint64 instruction, Dis_info *info) 5618 { 5619 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5620 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 5621 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 5622 5623 const char *rt = GPR(rt_value, info); 5624 5625 return img_format("DMFC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 5626 rt, c0s_value, sel_value); 5627 } 5628 5629 5630 /* 5631 * 5632 * 5633 * 3 2 1 5634 * 10987654321098765432109876543210 5635 * 001000 x1110000101 5636 * rt ----- 5637 * rs ----- 5638 * rd ----- 5639 */ 5640 static char *DMFC1(uint64 instruction, Dis_info *info) 5641 { 5642 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5643 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 5644 5645 const char *rt = GPR(rt_value, info); 5646 const char *fs = FPR(fs_value, info); 5647 5648 return img_format("DMFC1 %s, %s", rt, fs); 5649 } 5650 5651 5652 /* 5653 * 5654 * 5655 * 3 2 1 5656 * 10987654321098765432109876543210 5657 * 001000 x1110000101 5658 * rt ----- 5659 * rs ----- 5660 * rd ----- 5661 */ 5662 static char *DMFC2(uint64 instruction, Dis_info *info) 5663 { 5664 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5665 uint64 cs_value = extract_cs_20_19_18_17_16(instruction); 5666 5667 const char *rt = GPR(rt_value, info); 5668 5669 return img_format("DMFC2 %s, CP%" PRIu64, rt, cs_value); 5670 } 5671 5672 5673 /* 5674 * 5675 * 5676 * 3 2 1 5677 * 10987654321098765432109876543210 5678 * 001000 x1110000101 5679 * rt ----- 5680 * rs ----- 5681 * rd ----- 5682 */ 5683 static char *DMFGC0(uint64 instruction, Dis_info *info) 5684 { 5685 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5686 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 5687 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 5688 5689 const char *rt = GPR(rt_value, info); 5690 5691 return img_format("DMFGC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 5692 rt, c0s_value, sel_value); 5693 } 5694 5695 5696 /* 5697 * 5698 * 5699 * 3 2 1 5700 * 10987654321098765432109876543210 5701 * 001000 x1110000101 5702 * rt ----- 5703 * rs ----- 5704 * rd ----- 5705 */ 5706 static char *DMOD(uint64 instruction, Dis_info *info) 5707 { 5708 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5709 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5710 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5711 5712 const char *rd = GPR(rd_value, info); 5713 const char *rs = GPR(rs_value, info); 5714 const char *rt = GPR(rt_value, info); 5715 5716 return img_format("DMOD %s, %s, %s", rd, rs, rt); 5717 } 5718 5719 5720 /* 5721 * 5722 * 5723 * 3 2 1 5724 * 10987654321098765432109876543210 5725 * 001000 x1110000101 5726 * rt ----- 5727 * rs ----- 5728 * rd ----- 5729 */ 5730 static char *DMODU(uint64 instruction, Dis_info *info) 5731 { 5732 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5733 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5734 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5735 5736 const char *rd = GPR(rd_value, info); 5737 const char *rs = GPR(rs_value, info); 5738 const char *rt = GPR(rt_value, info); 5739 5740 return img_format("DMODU %s, %s, %s", rd, rs, rt); 5741 } 5742 5743 5744 /* 5745 * 5746 * 5747 * 3 2 1 5748 * 10987654321098765432109876543210 5749 * 001000 x1110000101 5750 * rt ----- 5751 * rs ----- 5752 * rd ----- 5753 */ 5754 static char *DMTC0(uint64 instruction, Dis_info *info) 5755 { 5756 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5757 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 5758 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 5759 5760 const char *rt = GPR(rt_value, info); 5761 5762 return img_format("DMTC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 5763 rt, c0s_value, sel_value); 5764 } 5765 5766 5767 /* 5768 * 5769 * 5770 * 3 2 1 5771 * 10987654321098765432109876543210 5772 * 001000 x1110000101 5773 * rt ----- 5774 * rs ----- 5775 * rd ----- 5776 */ 5777 static char *DMTC1(uint64 instruction, Dis_info *info) 5778 { 5779 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5780 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 5781 5782 const char *rt = GPR(rt_value, info); 5783 const char *fs = FPR(fs_value, info); 5784 5785 return img_format("DMTC1 %s, %s", rt, fs); 5786 } 5787 5788 5789 /* 5790 * 5791 * 5792 * 3 2 1 5793 * 10987654321098765432109876543210 5794 * 001000 x1110000101 5795 * rt ----- 5796 * rs ----- 5797 * rd ----- 5798 */ 5799 static char *DMTC2(uint64 instruction, Dis_info *info) 5800 { 5801 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5802 uint64 cs_value = extract_cs_20_19_18_17_16(instruction); 5803 5804 const char *rt = GPR(rt_value, info); 5805 5806 return img_format("DMTC2 %s, CP%" PRIu64, rt, cs_value); 5807 } 5808 5809 5810 /* 5811 * 5812 * 5813 * 3 2 1 5814 * 10987654321098765432109876543210 5815 * 001000 x1110000101 5816 * rt ----- 5817 * rs ----- 5818 * rd ----- 5819 */ 5820 static char *DMTGC0(uint64 instruction, Dis_info *info) 5821 { 5822 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5823 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 5824 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 5825 5826 const char *rt = GPR(rt_value, info); 5827 5828 return img_format("DMTGC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 5829 rt, c0s_value, sel_value); 5830 } 5831 5832 5833 /* 5834 * 5835 * 5836 * 3 2 1 5837 * 10987654321098765432109876543210 5838 * 001000 x1110000101 5839 * rt ----- 5840 * rs ----- 5841 * rd ----- 5842 */ 5843 static char *DMT(uint64 instruction, Dis_info *info) 5844 { 5845 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5846 5847 const char *rt = GPR(rt_value, info); 5848 5849 return img_format("DMT %s", rt); 5850 } 5851 5852 5853 /* 5854 * 5855 * 5856 * 3 2 1 5857 * 10987654321098765432109876543210 5858 * 001000 x1110000101 5859 * rt ----- 5860 * rs ----- 5861 * rd ----- 5862 */ 5863 static char *DMUH(uint64 instruction, Dis_info *info) 5864 { 5865 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5866 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5867 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5868 5869 const char *rd = GPR(rd_value, info); 5870 const char *rs = GPR(rs_value, info); 5871 const char *rt = GPR(rt_value, info); 5872 5873 return img_format("DMUH %s, %s, %s", rd, rs, rt); 5874 } 5875 5876 5877 /* 5878 * 5879 * 5880 * 3 2 1 5881 * 10987654321098765432109876543210 5882 * 001000 x1110000101 5883 * rt ----- 5884 * rs ----- 5885 * rd ----- 5886 */ 5887 static char *DMUHU(uint64 instruction, Dis_info *info) 5888 { 5889 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5890 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5891 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5892 5893 const char *rd = GPR(rd_value, info); 5894 const char *rs = GPR(rs_value, info); 5895 const char *rt = GPR(rt_value, info); 5896 5897 return img_format("DMUHU %s, %s, %s", rd, rs, rt); 5898 } 5899 5900 5901 /* 5902 * 5903 * 5904 * 3 2 1 5905 * 10987654321098765432109876543210 5906 * 001000 x1110000101 5907 * rt ----- 5908 * rs ----- 5909 * rd ----- 5910 */ 5911 static char *DMUL(uint64 instruction, Dis_info *info) 5912 { 5913 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5914 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5915 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5916 5917 const char *rd = GPR(rd_value, info); 5918 const char *rs = GPR(rs_value, info); 5919 const char *rt = GPR(rt_value, info); 5920 5921 return img_format("DMUL %s, %s, %s", rd, rs, rt); 5922 } 5923 5924 5925 /* 5926 * 5927 * 5928 * 3 2 1 5929 * 10987654321098765432109876543210 5930 * 001000 x1110000101 5931 * rt ----- 5932 * rs ----- 5933 * rd ----- 5934 */ 5935 static char *DMULU(uint64 instruction, Dis_info *info) 5936 { 5937 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5938 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5939 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 5940 5941 const char *rd = GPR(rd_value, info); 5942 const char *rs = GPR(rs_value, info); 5943 const char *rt = GPR(rt_value, info); 5944 5945 return img_format("DMULU %s, %s, %s", rd, rs, rt); 5946 } 5947 5948 5949 /* 5950 * [DSP] DPA.W.PH ac, rs, rt - Dot product with accumulate on 5951 * vector integer halfword elements 5952 * 5953 * 3 2 1 5954 * 10987654321098765432109876543210 5955 * 001000 00000010111111 5956 * rt ----- 5957 * rs ----- 5958 * ac -- 5959 */ 5960 static char *DPA_W_PH(uint64 instruction, Dis_info *info) 5961 { 5962 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5963 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5964 uint64 ac_value = extract_ac_15_14(instruction); 5965 5966 const char *ac = AC(ac_value, info); 5967 const char *rs = GPR(rs_value, info); 5968 const char *rt = GPR(rt_value, info); 5969 5970 return img_format("DPA.W.PH %s, %s, %s", ac, rs, rt); 5971 } 5972 5973 5974 /* 5975 * 5976 * 5977 * 3 2 1 5978 * 10987654321098765432109876543210 5979 * 001000 x1110000101 5980 * rt ----- 5981 * rs ----- 5982 * rd ----- 5983 */ 5984 static char *DPAQ_SA_L_W(uint64 instruction, Dis_info *info) 5985 { 5986 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 5987 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 5988 uint64 ac_value = extract_ac_15_14(instruction); 5989 5990 const char *ac = AC(ac_value, info); 5991 const char *rs = GPR(rs_value, info); 5992 const char *rt = GPR(rt_value, info); 5993 5994 return img_format("DPAQ_SA.L.W %s, %s, %s", ac, rs, rt); 5995 } 5996 5997 5998 /* 5999 * 6000 * 6001 * 3 2 1 6002 * 10987654321098765432109876543210 6003 * 001000 x1110000101 6004 * rt ----- 6005 * rs ----- 6006 * rd ----- 6007 */ 6008 static char *DPAQ_S_W_PH(uint64 instruction, Dis_info *info) 6009 { 6010 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6011 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6012 uint64 ac_value = extract_ac_15_14(instruction); 6013 6014 const char *ac = AC(ac_value, info); 6015 const char *rs = GPR(rs_value, info); 6016 const char *rt = GPR(rt_value, info); 6017 6018 return img_format("DPAQ_S.W.PH %s, %s, %s", ac, rs, rt); 6019 } 6020 6021 6022 /* 6023 * 6024 * 6025 * 3 2 1 6026 * 10987654321098765432109876543210 6027 * 001000 x1110000101 6028 * rt ----- 6029 * rs ----- 6030 * rd ----- 6031 */ 6032 static char *DPAQX_SA_W_PH(uint64 instruction, Dis_info *info) 6033 { 6034 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6035 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6036 uint64 ac_value = extract_ac_15_14(instruction); 6037 6038 const char *ac = AC(ac_value, info); 6039 const char *rs = GPR(rs_value, info); 6040 const char *rt = GPR(rt_value, info); 6041 6042 return img_format("DPAQX_SA.W.PH %s, %s, %s", ac, rs, rt); 6043 } 6044 6045 6046 /* 6047 * 6048 * 6049 * 3 2 1 6050 * 10987654321098765432109876543210 6051 * 001000 x1110000101 6052 * rt ----- 6053 * rs ----- 6054 * rd ----- 6055 */ 6056 static char *DPAQX_S_W_PH(uint64 instruction, Dis_info *info) 6057 { 6058 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6059 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6060 uint64 ac_value = extract_ac_15_14(instruction); 6061 6062 const char *ac = AC(ac_value, info); 6063 const char *rs = GPR(rs_value, info); 6064 const char *rt = GPR(rt_value, info); 6065 6066 return img_format("DPAQX_S.W.PH %s, %s, %s", ac, rs, rt); 6067 } 6068 6069 6070 /* 6071 * 6072 * 6073 * 3 2 1 6074 * 10987654321098765432109876543210 6075 * 001000 x1110000101 6076 * rt ----- 6077 * rs ----- 6078 * rd ----- 6079 */ 6080 static char *DPAU_H_QBL(uint64 instruction, Dis_info *info) 6081 { 6082 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6083 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6084 uint64 ac_value = extract_ac_15_14(instruction); 6085 6086 const char *ac = AC(ac_value, info); 6087 const char *rs = GPR(rs_value, info); 6088 const char *rt = GPR(rt_value, info); 6089 6090 return img_format("DPAU.H.QBL %s, %s, %s", ac, rs, rt); 6091 } 6092 6093 6094 /* 6095 * 6096 * 6097 * 3 2 1 6098 * 10987654321098765432109876543210 6099 * 001000 x1110000101 6100 * rt ----- 6101 * rs ----- 6102 * rd ----- 6103 */ 6104 static char *DPAU_H_QBR(uint64 instruction, Dis_info *info) 6105 { 6106 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6107 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6108 uint64 ac_value = extract_ac_15_14(instruction); 6109 6110 const char *ac = AC(ac_value, info); 6111 const char *rs = GPR(rs_value, info); 6112 const char *rt = GPR(rt_value, info); 6113 6114 return img_format("DPAU.H.QBR %s, %s, %s", ac, rs, rt); 6115 } 6116 6117 6118 /* 6119 * 6120 * 6121 * 3 2 1 6122 * 10987654321098765432109876543210 6123 * 001000 x1110000101 6124 * rt ----- 6125 * rs ----- 6126 * rd ----- 6127 */ 6128 static char *DPAX_W_PH(uint64 instruction, Dis_info *info) 6129 { 6130 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6131 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6132 uint64 ac_value = extract_ac_15_14(instruction); 6133 6134 const char *ac = AC(ac_value, info); 6135 const char *rs = GPR(rs_value, info); 6136 const char *rt = GPR(rt_value, info); 6137 6138 return img_format("DPAX.W.PH %s, %s, %s", ac, rs, rt); 6139 } 6140 6141 6142 /* 6143 * 6144 * 6145 * 3 2 1 6146 * 10987654321098765432109876543210 6147 * 001000 x1110000101 6148 * rt ----- 6149 * rs ----- 6150 * rd ----- 6151 */ 6152 static char *DPS_W_PH(uint64 instruction, Dis_info *info) 6153 { 6154 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6155 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6156 uint64 ac_value = extract_ac_15_14(instruction); 6157 6158 const char *ac = AC(ac_value, info); 6159 const char *rs = GPR(rs_value, info); 6160 const char *rt = GPR(rt_value, info); 6161 6162 return img_format("DPS.W.PH %s, %s, %s", ac, rs, rt); 6163 } 6164 6165 6166 /* 6167 * 6168 * 6169 * 3 2 1 6170 * 10987654321098765432109876543210 6171 * 001000 x1110000101 6172 * rt ----- 6173 * rs ----- 6174 * rd ----- 6175 */ 6176 static char *DPSQ_SA_L_W(uint64 instruction, Dis_info *info) 6177 { 6178 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6179 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6180 uint64 ac_value = extract_ac_15_14(instruction); 6181 6182 const char *ac = AC(ac_value, info); 6183 const char *rs = GPR(rs_value, info); 6184 const char *rt = GPR(rt_value, info); 6185 6186 return img_format("DPSQ_SA.L.W %s, %s, %s", ac, rs, rt); 6187 } 6188 6189 6190 /* 6191 * 6192 * 6193 * 3 2 1 6194 * 10987654321098765432109876543210 6195 * 001000 x1110000101 6196 * rt ----- 6197 * rs ----- 6198 * rd ----- 6199 */ 6200 static char *DPSQ_S_W_PH(uint64 instruction, Dis_info *info) 6201 { 6202 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6203 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6204 uint64 ac_value = extract_ac_15_14(instruction); 6205 6206 const char *ac = AC(ac_value, info); 6207 const char *rs = GPR(rs_value, info); 6208 const char *rt = GPR(rt_value, info); 6209 6210 return img_format("DPSQ_S.W.PH %s, %s, %s", ac, rs, rt); 6211 } 6212 6213 6214 /* 6215 * 6216 * 6217 * 3 2 1 6218 * 10987654321098765432109876543210 6219 * 001000 x1110000101 6220 * rt ----- 6221 * rs ----- 6222 * rd ----- 6223 */ 6224 static char *DPSQX_SA_W_PH(uint64 instruction, Dis_info *info) 6225 { 6226 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6227 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6228 uint64 ac_value = extract_ac_15_14(instruction); 6229 6230 const char *ac = AC(ac_value, info); 6231 const char *rs = GPR(rs_value, info); 6232 const char *rt = GPR(rt_value, info); 6233 6234 return img_format("DPSQX_SA.W.PH %s, %s, %s", ac, rs, rt); 6235 } 6236 6237 6238 /* 6239 * 6240 * 6241 * 3 2 1 6242 * 10987654321098765432109876543210 6243 * 001000 x1110000101 6244 * rt ----- 6245 * rs ----- 6246 * rd ----- 6247 */ 6248 static char *DPSQX_S_W_PH(uint64 instruction, Dis_info *info) 6249 { 6250 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6251 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6252 uint64 ac_value = extract_ac_15_14(instruction); 6253 6254 const char *ac = AC(ac_value, info); 6255 const char *rs = GPR(rs_value, info); 6256 const char *rt = GPR(rt_value, info); 6257 6258 return img_format("DPSQX_S.W.PH %s, %s, %s", ac, rs, rt); 6259 } 6260 6261 6262 /* 6263 * 6264 * 6265 * 3 2 1 6266 * 10987654321098765432109876543210 6267 * 001000 x1110000101 6268 * rt ----- 6269 * rs ----- 6270 * rd ----- 6271 */ 6272 static char *DPSU_H_QBL(uint64 instruction, Dis_info *info) 6273 { 6274 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6275 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6276 uint64 ac_value = extract_ac_15_14(instruction); 6277 6278 const char *ac = AC(ac_value, info); 6279 const char *rs = GPR(rs_value, info); 6280 const char *rt = GPR(rt_value, info); 6281 6282 return img_format("DPSU.H.QBL %s, %s, %s", ac, rs, rt); 6283 } 6284 6285 6286 /* 6287 * 6288 * 6289 * 3 2 1 6290 * 10987654321098765432109876543210 6291 * 001000 x1110000101 6292 * rt ----- 6293 * rs ----- 6294 * rd ----- 6295 */ 6296 static char *DPSU_H_QBR(uint64 instruction, Dis_info *info) 6297 { 6298 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6299 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6300 uint64 ac_value = extract_ac_15_14(instruction); 6301 6302 const char *ac = AC(ac_value, info); 6303 const char *rs = GPR(rs_value, info); 6304 const char *rt = GPR(rt_value, info); 6305 6306 return img_format("DPSU.H.QBR %s, %s, %s", ac, rs, rt); 6307 } 6308 6309 6310 /* 6311 * 6312 * 6313 * 3 2 1 6314 * 10987654321098765432109876543210 6315 * 001000 x1110000101 6316 * rt ----- 6317 * rs ----- 6318 * rd ----- 6319 */ 6320 static char *DPSX_W_PH(uint64 instruction, Dis_info *info) 6321 { 6322 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6323 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6324 uint64 ac_value = extract_ac_15_14(instruction); 6325 6326 const char *ac = AC(ac_value, info); 6327 const char *rs = GPR(rs_value, info); 6328 const char *rt = GPR(rt_value, info); 6329 6330 return img_format("DPSX.W.PH %s, %s, %s", ac, rs, rt); 6331 } 6332 6333 6334 /* 6335 * DROTR - 6336 * 6337 * 3 2 1 6338 * 10987654321098765432109876543210 6339 * 001000 x1110000101 6340 * rt ----- 6341 * rs ----- 6342 * rd ----- 6343 */ 6344 static char *DROTR(uint64 instruction, Dis_info *info) 6345 { 6346 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6347 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6348 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 6349 6350 const char *rt = GPR(rt_value, info); 6351 const char *rs = GPR(rs_value, info); 6352 6353 return img_format("DROTR %s, %s, 0x%" PRIx64, rt, rs, shift_value); 6354 } 6355 6356 6357 /* 6358 * DROTR[32] - 6359 * 6360 * 3 2 1 6361 * 10987654321098765432109876543210 6362 * 10o000 1100xxx0110 6363 * rt ----- 6364 * rs ----- 6365 * shift ----- 6366 */ 6367 static char *DROTR32(uint64 instruction, Dis_info *info) 6368 { 6369 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6370 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6371 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 6372 6373 const char *rt = GPR(rt_value, info); 6374 const char *rs = GPR(rs_value, info); 6375 6376 return img_format("DROTR32 %s, %s, 0x%" PRIx64, rt, rs, shift_value); 6377 } 6378 6379 6380 /* 6381 * 6382 * 6383 * 3 2 1 6384 * 10987654321098765432109876543210 6385 * 001000 x1110000101 6386 * rt ----- 6387 * rs ----- 6388 * rd ----- 6389 */ 6390 static char *DROTRV(uint64 instruction, Dis_info *info) 6391 { 6392 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6393 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6394 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 6395 6396 const char *rd = GPR(rd_value, info); 6397 const char *rs = GPR(rs_value, info); 6398 const char *rt = GPR(rt_value, info); 6399 6400 return img_format("DROTRV %s, %s, %s", rd, rs, rt); 6401 } 6402 6403 6404 /* 6405 * 6406 * 6407 * 3 2 1 6408 * 10987654321098765432109876543210 6409 * 001000 x1110000101 6410 * rt ----- 6411 * rs ----- 6412 * rd ----- 6413 */ 6414 static char *DROTX(uint64 instruction, Dis_info *info) 6415 { 6416 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6417 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6418 uint64 shiftx_value = extract_shiftx_11_10_9_8_7_6(instruction); 6419 uint64 shift_value = extract_shift_5_4_3_2_1_0(instruction); 6420 6421 const char *rt = GPR(rt_value, info); 6422 const char *rs = GPR(rs_value, info); 6423 6424 return img_format("DROTX %s, %s, 0x%" PRIx64 ", 0x%" PRIx64, 6425 rt, rs, shift_value, shiftx_value); 6426 } 6427 6428 6429 /* 6430 * DSLL - 6431 * 6432 * 3 2 1 6433 * 10987654321098765432109876543210 6434 * 10o000 1100xxx0000 6435 * rt ----- 6436 * rs ----- 6437 * shift ----- 6438 */ 6439 static char *DSLL(uint64 instruction, Dis_info *info) 6440 { 6441 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6442 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6443 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 6444 6445 const char *rt = GPR(rt_value, info); 6446 const char *rs = GPR(rs_value, info); 6447 6448 return img_format("DSLL %s, %s, 0x%" PRIx64, rt, rs, shift_value); 6449 } 6450 6451 6452 /* 6453 * DSLL[32] - 6454 * 6455 * 3 2 1 6456 * 10987654321098765432109876543210 6457 * 10o000 1100xxx0000 6458 * rt ----- 6459 * rs ----- 6460 * shift ----- 6461 */ 6462 static char *DSLL32(uint64 instruction, Dis_info *info) 6463 { 6464 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6465 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6466 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 6467 6468 const char *rt = GPR(rt_value, info); 6469 const char *rs = GPR(rs_value, info); 6470 6471 return img_format("DSLL32 %s, %s, 0x%" PRIx64, rt, rs, shift_value); 6472 } 6473 6474 6475 /* 6476 * 6477 * 6478 * 3 2 1 6479 * 10987654321098765432109876543210 6480 * 001000 x1110000101 6481 * rt ----- 6482 * rs ----- 6483 * rd ----- 6484 */ 6485 static char *DSLLV(uint64 instruction, Dis_info *info) 6486 { 6487 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6488 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6489 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 6490 6491 const char *rd = GPR(rd_value, info); 6492 const char *rs = GPR(rs_value, info); 6493 const char *rt = GPR(rt_value, info); 6494 6495 return img_format("DSLLV %s, %s, %s", rd, rs, rt); 6496 } 6497 6498 6499 /* 6500 * DSRA - 6501 * 6502 * 3 2 1 6503 * 10987654321098765432109876543210 6504 * 10o000 1100xxx0100 6505 * rt ----- 6506 * rs ----- 6507 * shift ----- 6508 */ 6509 static char *DSRA(uint64 instruction, Dis_info *info) 6510 { 6511 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6512 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6513 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 6514 6515 const char *rt = GPR(rt_value, info); 6516 const char *rs = GPR(rs_value, info); 6517 6518 return img_format("DSRA %s, %s, 0x%" PRIx64, rt, rs, shift_value); 6519 } 6520 6521 6522 /* 6523 * DSRA[32] - 6524 * 6525 * 3 2 1 6526 * 10987654321098765432109876543210 6527 * 10o000 1100xxx0100 6528 * rt ----- 6529 * rs ----- 6530 * shift ----- 6531 */ 6532 static char *DSRA32(uint64 instruction, Dis_info *info) 6533 { 6534 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6535 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6536 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 6537 6538 const char *rt = GPR(rt_value, info); 6539 const char *rs = GPR(rs_value, info); 6540 6541 return img_format("DSRA32 %s, %s, 0x%" PRIx64, rt, rs, shift_value); 6542 } 6543 6544 6545 /* 6546 * 6547 * 6548 * 3 2 1 6549 * 10987654321098765432109876543210 6550 * 001000 x1110000101 6551 * rt ----- 6552 * rs ----- 6553 * rd ----- 6554 */ 6555 static char *DSRAV(uint64 instruction, Dis_info *info) 6556 { 6557 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6558 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6559 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 6560 6561 const char *rd = GPR(rd_value, info); 6562 const char *rs = GPR(rs_value, info); 6563 const char *rt = GPR(rt_value, info); 6564 6565 return img_format("DSRAV %s, %s, %s", rd, rs, rt); 6566 } 6567 6568 6569 /* 6570 * DSRL - 6571 * 6572 * 3 2 1 6573 * 10987654321098765432109876543210 6574 * 10o000 1100xxx0100 6575 * rt ----- 6576 * rs ----- 6577 * shift ----- 6578 */ 6579 static char *DSRL(uint64 instruction, Dis_info *info) 6580 { 6581 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6582 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6583 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 6584 6585 const char *rt = GPR(rt_value, info); 6586 const char *rs = GPR(rs_value, info); 6587 6588 return img_format("DSRL %s, %s, 0x%" PRIx64, rt, rs, shift_value); 6589 } 6590 6591 6592 /* 6593 * DSRL[32] - 6594 * 6595 * 3 2 1 6596 * 10987654321098765432109876543210 6597 * 10o000 1100xxx0010 6598 * rt ----- 6599 * rs ----- 6600 * shift ----- 6601 */ 6602 static char *DSRL32(uint64 instruction, Dis_info *info) 6603 { 6604 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6605 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6606 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 6607 6608 const char *rt = GPR(rt_value, info); 6609 const char *rs = GPR(rs_value, info); 6610 6611 return img_format("DSRL32 %s, %s, 0x%" PRIx64, rt, rs, shift_value); 6612 } 6613 6614 6615 /* 6616 * 6617 * 6618 * 3 2 1 6619 * 10987654321098765432109876543210 6620 * 001000 x1110000101 6621 * rt ----- 6622 * rs ----- 6623 * rd ----- 6624 */ 6625 static char *DSRLV(uint64 instruction, Dis_info *info) 6626 { 6627 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6628 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6629 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 6630 6631 const char *rd = GPR(rd_value, info); 6632 const char *rs = GPR(rs_value, info); 6633 const char *rt = GPR(rt_value, info); 6634 6635 return img_format("DSRLV %s, %s, %s", rd, rs, rt); 6636 } 6637 6638 6639 /* 6640 * 6641 * 6642 * 3 2 1 6643 * 10987654321098765432109876543210 6644 * 001000 x1110000101 6645 * rt ----- 6646 * rs ----- 6647 * rd ----- 6648 */ 6649 static char *DSUB(uint64 instruction, Dis_info *info) 6650 { 6651 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6652 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6653 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 6654 6655 const char *rd = GPR(rd_value, info); 6656 const char *rs = GPR(rs_value, info); 6657 const char *rt = GPR(rt_value, info); 6658 6659 return img_format("DSUB %s, %s, %s", rd, rs, rt); 6660 } 6661 6662 6663 /* 6664 * 6665 * 6666 * 3 2 1 6667 * 10987654321098765432109876543210 6668 * 001000 x1110000101 6669 * rt ----- 6670 * rs ----- 6671 * rd ----- 6672 */ 6673 static char *DSUBU(uint64 instruction, Dis_info *info) 6674 { 6675 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6676 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6677 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 6678 6679 const char *rd = GPR(rd_value, info); 6680 const char *rs = GPR(rs_value, info); 6681 const char *rt = GPR(rt_value, info); 6682 6683 return img_format("DSUBU %s, %s, %s", rd, rs, rt); 6684 } 6685 6686 6687 /* 6688 * 6689 * 6690 * 3 2 1 6691 * 10987654321098765432109876543210 6692 * 001000 x1110000101 6693 * rt ----- 6694 * rs ----- 6695 * rd ----- 6696 */ 6697 static char *DVPE(uint64 instruction, Dis_info *info) 6698 { 6699 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6700 6701 const char *rt = GPR(rt_value, info); 6702 6703 return img_format("DVPE %s", rt); 6704 } 6705 6706 6707 /* 6708 * 6709 * 6710 * 3 2 1 6711 * 10987654321098765432109876543210 6712 * 001000 x1110000101 6713 * rt ----- 6714 * rs ----- 6715 * rd ----- 6716 */ 6717 static char *DVP(uint64 instruction, Dis_info *info) 6718 { 6719 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6720 6721 const char *rt = GPR(rt_value, info); 6722 6723 return img_format("DVP %s", rt); 6724 } 6725 6726 6727 /* 6728 * 6729 * 6730 * 3 2 1 6731 * 10987654321098765432109876543210 6732 * 001000 x1110000101 6733 * rt ----- 6734 * rs ----- 6735 * rd ----- 6736 */ 6737 static char *EHB(uint64 instruction, Dis_info *info) 6738 { 6739 (void)instruction; 6740 6741 return g_strdup("EHB "); 6742 } 6743 6744 6745 /* 6746 * 6747 * 6748 * 3 2 1 6749 * 10987654321098765432109876543210 6750 * 001000 x1110000101 6751 * rt ----- 6752 * rs ----- 6753 * rd ----- 6754 */ 6755 static char *EI(uint64 instruction, Dis_info *info) 6756 { 6757 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6758 6759 const char *rt = GPR(rt_value, info); 6760 6761 return img_format("EI %s", rt); 6762 } 6763 6764 6765 /* 6766 * 6767 * 6768 * 3 2 1 6769 * 10987654321098765432109876543210 6770 * 001000 x1110000101 6771 * rt ----- 6772 * rs ----- 6773 * rd ----- 6774 */ 6775 static char *EMT(uint64 instruction, Dis_info *info) 6776 { 6777 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6778 6779 const char *rt = GPR(rt_value, info); 6780 6781 return img_format("EMT %s", rt); 6782 } 6783 6784 6785 /* 6786 * 6787 * 6788 * 3 2 1 6789 * 10987654321098765432109876543210 6790 * 001000 x1110000101 6791 * rt ----- 6792 * rs ----- 6793 * rd ----- 6794 */ 6795 static char *ERET(uint64 instruction, Dis_info *info) 6796 { 6797 (void)instruction; 6798 6799 return g_strdup("ERET "); 6800 } 6801 6802 6803 /* 6804 * 6805 * 6806 * 3 2 1 6807 * 10987654321098765432109876543210 6808 * 001000 x1110000101 6809 * rt ----- 6810 * rs ----- 6811 * rd ----- 6812 */ 6813 static char *ERETNC(uint64 instruction, Dis_info *info) 6814 { 6815 (void)instruction; 6816 6817 return g_strdup("ERETNC "); 6818 } 6819 6820 6821 /* 6822 * 6823 * 6824 * 3 2 1 6825 * 10987654321098765432109876543210 6826 * 001000 x1110000101 6827 * rt ----- 6828 * rs ----- 6829 * rd ----- 6830 */ 6831 static char *EVP(uint64 instruction, Dis_info *info) 6832 { 6833 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6834 6835 const char *rt = GPR(rt_value, info); 6836 6837 return img_format("EVP %s", rt); 6838 } 6839 6840 6841 /* 6842 * 6843 * 6844 * 3 2 1 6845 * 10987654321098765432109876543210 6846 * 001000 x1110000101 6847 * rt ----- 6848 * rs ----- 6849 * rd ----- 6850 */ 6851 static char *EVPE(uint64 instruction, Dis_info *info) 6852 { 6853 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6854 6855 const char *rt = GPR(rt_value, info); 6856 6857 return img_format("EVPE %s", rt); 6858 } 6859 6860 6861 /* 6862 * 6863 * 6864 * 3 2 1 6865 * 10987654321098765432109876543210 6866 * 001000 x1110000101 6867 * rt ----- 6868 * rs ----- 6869 * rd ----- 6870 */ 6871 static char *EXT(uint64 instruction, Dis_info *info) 6872 { 6873 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6874 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6875 uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); 6876 uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); 6877 6878 const char *rt = GPR(rt_value, info); 6879 const char *rs = GPR(rs_value, info); 6880 uint64 msbd = encode_msbd_from_size(msbd_value); 6881 6882 return img_format("EXT %s, %s, 0x%" PRIx64 ", 0x%" PRIx64, 6883 rt, rs, lsb_value, msbd); 6884 } 6885 6886 6887 /* 6888 * 6889 * 6890 * 3 2 1 6891 * 10987654321098765432109876543210 6892 * 001000 x1110000101 6893 * rt ----- 6894 * rs ----- 6895 * rd ----- 6896 */ 6897 static char *EXTD(uint64 instruction, Dis_info *info) 6898 { 6899 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6900 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6901 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 6902 uint64 shift_value = extract_shift_10_9_8_7_6(instruction); 6903 6904 const char *rd = GPR(rd_value, info); 6905 const char *rs = GPR(rs_value, info); 6906 const char *rt = GPR(rt_value, info); 6907 6908 return img_format("EXTD %s, %s, %s, 0x%" PRIx64, rd, rs, rt, shift_value); 6909 } 6910 6911 6912 /* 6913 * 6914 * 6915 * 3 2 1 6916 * 10987654321098765432109876543210 6917 * 001000 x1110000101 6918 * rt ----- 6919 * rs ----- 6920 * rd ----- 6921 */ 6922 static char *EXTD32(uint64 instruction, Dis_info *info) 6923 { 6924 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6925 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6926 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 6927 uint64 shift_value = extract_shift_10_9_8_7_6(instruction); 6928 6929 const char *rd = GPR(rd_value, info); 6930 const char *rs = GPR(rs_value, info); 6931 const char *rt = GPR(rt_value, info); 6932 6933 return img_format("EXTD32 %s, %s, %s, 0x%" PRIx64, rd, rs, rt, shift_value); 6934 } 6935 6936 6937 /* 6938 * 6939 * 6940 * 3 2 1 6941 * 10987654321098765432109876543210 6942 * 001000 x1110000101 6943 * rt ----- 6944 * rs ----- 6945 * rd ----- 6946 */ 6947 static char *EXTPDP(uint64 instruction, Dis_info *info) 6948 { 6949 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6950 uint64 size_value = extract_size_20_19_18_17_16(instruction); 6951 uint64 ac_value = extract_ac_15_14(instruction); 6952 6953 const char *rt = GPR(rt_value, info); 6954 const char *ac = AC(ac_value, info); 6955 6956 return img_format("EXTPDP %s, %s, 0x%" PRIx64, rt, ac, size_value); 6957 } 6958 6959 6960 /* 6961 * 6962 * 6963 * 3 2 1 6964 * 10987654321098765432109876543210 6965 * 001000 x1110000101 6966 * rt ----- 6967 * rs ----- 6968 * rd ----- 6969 */ 6970 static char *EXTPDPV(uint64 instruction, Dis_info *info) 6971 { 6972 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6973 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 6974 uint64 ac_value = extract_ac_15_14(instruction); 6975 6976 const char *rt = GPR(rt_value, info); 6977 const char *ac = AC(ac_value, info); 6978 const char *rs = GPR(rs_value, info); 6979 6980 return img_format("EXTPDPV %s, %s, %s", rt, ac, rs); 6981 } 6982 6983 6984 /* 6985 * 6986 * 6987 * 3 2 1 6988 * 10987654321098765432109876543210 6989 * 001000 x1110000101 6990 * rt ----- 6991 * rs ----- 6992 * rd ----- 6993 */ 6994 static char *EXTP(uint64 instruction, Dis_info *info) 6995 { 6996 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 6997 uint64 size_value = extract_size_20_19_18_17_16(instruction); 6998 uint64 ac_value = extract_ac_15_14(instruction); 6999 7000 const char *rt = GPR(rt_value, info); 7001 const char *ac = AC(ac_value, info); 7002 7003 return img_format("EXTP %s, %s, 0x%" PRIx64, rt, ac, size_value); 7004 } 7005 7006 7007 /* 7008 * 7009 * 7010 * 3 2 1 7011 * 10987654321098765432109876543210 7012 * 001000 x1110000101 7013 * rt ----- 7014 * rs ----- 7015 * rd ----- 7016 */ 7017 static char *EXTPV(uint64 instruction, Dis_info *info) 7018 { 7019 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7020 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7021 uint64 ac_value = extract_ac_15_14(instruction); 7022 7023 const char *rt = GPR(rt_value, info); 7024 const char *ac = AC(ac_value, info); 7025 const char *rs = GPR(rs_value, info); 7026 7027 return img_format("EXTPV %s, %s, %s", rt, ac, rs); 7028 } 7029 7030 7031 /* 7032 * [DSP] EXTR_RS.W rt, ac, shift - Extract word value from accumulator to GPR 7033 * with right shift 7034 * 7035 * 3 2 1 7036 * 10987654321098765432109876543210 7037 * 001000 10111001111111 7038 * rt ----- 7039 * shift ----- 7040 * ac -- 7041 */ 7042 static char *EXTR_RS_W(uint64 instruction, Dis_info *info) 7043 { 7044 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7045 uint64 shift_value = extract_shift_20_19_18_17_16(instruction); 7046 uint64 ac_value = extract_ac_15_14(instruction); 7047 7048 const char *rt = GPR(rt_value, info); 7049 const char *ac = AC(ac_value, info); 7050 7051 return img_format("EXTR_RS.W %s, %s, 0x%" PRIx64, rt, ac, shift_value); 7052 } 7053 7054 7055 /* 7056 * [DSP] EXTR_R.W rt, ac, shift - Extract word value from accumulator to GPR 7057 * with right shift 7058 * 7059 * 3 2 1 7060 * 10987654321098765432109876543210 7061 * 001000 01111001111111 7062 * rt ----- 7063 * shift ----- 7064 * ac -- 7065 */ 7066 static char *EXTR_R_W(uint64 instruction, Dis_info *info) 7067 { 7068 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7069 uint64 shift_value = extract_shift_20_19_18_17_16(instruction); 7070 uint64 ac_value = extract_ac_15_14(instruction); 7071 7072 const char *rt = GPR(rt_value, info); 7073 const char *ac = AC(ac_value, info); 7074 7075 return img_format("EXTR_R.W %s, %s, 0x%" PRIx64, rt, ac, shift_value); 7076 } 7077 7078 7079 /* 7080 * [DSP] EXTR_S.H rt, ac, shift - Extract halfword value from accumulator 7081 * to GPR with right shift and saturate 7082 * 7083 * 3 2 1 7084 * 10987654321098765432109876543210 7085 * 001000 11111001111111 7086 * rt ----- 7087 * shift ----- 7088 * ac -- 7089 */ 7090 static char *EXTR_S_H(uint64 instruction, Dis_info *info) 7091 { 7092 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7093 uint64 shift_value = extract_shift_20_19_18_17_16(instruction); 7094 uint64 ac_value = extract_ac_15_14(instruction); 7095 7096 const char *rt = GPR(rt_value, info); 7097 const char *ac = AC(ac_value, info); 7098 7099 return img_format("EXTR_S.H %s, %s, 0x%" PRIx64, rt, ac, shift_value); 7100 } 7101 7102 7103 /* 7104 * [DSP] EXTR.W rt, ac, shift - Extract word value from accumulator to GPR 7105 * with right shift 7106 * 7107 * 3 2 1 7108 * 10987654321098765432109876543210 7109 * 001000 00111001111111 7110 * rt ----- 7111 * shift ----- 7112 * ac -- 7113 */ 7114 static char *EXTR_W(uint64 instruction, Dis_info *info) 7115 { 7116 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7117 uint64 shift_value = extract_shift_20_19_18_17_16(instruction); 7118 uint64 ac_value = extract_ac_15_14(instruction); 7119 7120 const char *rt = GPR(rt_value, info); 7121 const char *ac = AC(ac_value, info); 7122 7123 return img_format("EXTR.W %s, %s, 0x%" PRIx64, rt, ac, shift_value); 7124 } 7125 7126 7127 /* 7128 * [DSP] EXTRV_RS.W rt, ac, rs - Extract word value with variable 7129 * right shift from accumulator to GPR 7130 * 7131 * 3 2 1 7132 * 10987654321098765432109876543210 7133 * 001000 10111010111111 7134 * rt ----- 7135 * rs ----- 7136 * ac -- 7137 */ 7138 static char *EXTRV_RS_W(uint64 instruction, Dis_info *info) 7139 { 7140 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7141 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7142 uint64 ac_value = extract_ac_15_14(instruction); 7143 7144 const char *rt = GPR(rt_value, info); 7145 const char *ac = AC(ac_value, info); 7146 const char *rs = GPR(rs_value, info); 7147 7148 return img_format("EXTRV_RS.W %s, %s, %s", rt, ac, rs); 7149 } 7150 7151 7152 /* 7153 * [DSP] EXTRV_R.W rt, ac, rs - Extract word value with variable 7154 * right shift from accumulator to GPR 7155 * 7156 * 3 2 1 7157 * 10987654321098765432109876543210 7158 * 001000 01111010111111 7159 * rt ----- 7160 * rs ----- 7161 * ac -- 7162 */ 7163 static char *EXTRV_R_W(uint64 instruction, Dis_info *info) 7164 { 7165 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7166 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7167 uint64 ac_value = extract_ac_15_14(instruction); 7168 7169 const char *rt = GPR(rt_value, info); 7170 const char *ac = AC(ac_value, info); 7171 const char *rs = GPR(rs_value, info); 7172 7173 return img_format("EXTRV_R.W %s, %s, %s", rt, ac, rs); 7174 } 7175 7176 7177 /* 7178 * [DSP] EXTRV_S.H rt, ac, rs - Extract halfword value variable from 7179 * accumulator to GPR with right shift and saturate 7180 * 7181 * 3 2 1 7182 * 10987654321098765432109876543210 7183 * 001000 11111010111111 7184 * rt ----- 7185 * rs ----- 7186 * ac -- 7187 */ 7188 static char *EXTRV_S_H(uint64 instruction, Dis_info *info) 7189 { 7190 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7191 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7192 uint64 ac_value = extract_ac_15_14(instruction); 7193 7194 const char *rt = GPR(rt_value, info); 7195 const char *ac = AC(ac_value, info); 7196 const char *rs = GPR(rs_value, info); 7197 7198 return img_format("EXTRV_S.H %s, %s, %s", rt, ac, rs); 7199 } 7200 7201 7202 /* 7203 * [DSP] EXTRV.W rt, ac, rs - Extract word value with variable 7204 * right shift from accumulator to GPR 7205 * 7206 * 3 2 1 7207 * 10987654321098765432109876543210 7208 * 001000 00111010111111 7209 * rt ----- 7210 * rs ----- 7211 * ac -- 7212 */ 7213 static char *EXTRV_W(uint64 instruction, Dis_info *info) 7214 { 7215 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7216 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7217 uint64 ac_value = extract_ac_15_14(instruction); 7218 7219 const char *rt = GPR(rt_value, info); 7220 const char *ac = AC(ac_value, info); 7221 const char *rs = GPR(rs_value, info); 7222 7223 return img_format("EXTRV.W %s, %s, %s", rt, ac, rs); 7224 } 7225 7226 7227 /* 7228 * EXTW - Extract Word 7229 * 7230 * 3 2 1 7231 * 10987654321098765432109876543210 7232 * 001000 011111 7233 * rt ----- 7234 * rs ----- 7235 * rd ----- 7236 * shift ----- 7237 */ 7238 static char *EXTW(uint64 instruction, Dis_info *info) 7239 { 7240 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7241 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7242 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 7243 uint64 shift_value = extract_shift_10_9_8_7_6(instruction); 7244 7245 const char *rd = GPR(rd_value, info); 7246 const char *rs = GPR(rs_value, info); 7247 const char *rt = GPR(rt_value, info); 7248 7249 return img_format("EXTW %s, %s, %s, 0x%" PRIx64, rd, rs, rt, shift_value); 7250 } 7251 7252 7253 /* 7254 * 7255 * 7256 * 3 2 1 7257 * 10987654321098765432109876543210 7258 * 001000 x1110000101 7259 * rt ----- 7260 * rs ----- 7261 * rd ----- 7262 */ 7263 static char *FLOOR_L_D(uint64 instruction, Dis_info *info) 7264 { 7265 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 7266 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 7267 7268 const char *ft = FPR(ft_value, info); 7269 const char *fs = FPR(fs_value, info); 7270 7271 return img_format("FLOOR.L.D %s, %s", ft, fs); 7272 } 7273 7274 7275 /* 7276 * 7277 * 7278 * 3 2 1 7279 * 10987654321098765432109876543210 7280 * 001000 x1110000101 7281 * rt ----- 7282 * rs ----- 7283 * rd ----- 7284 */ 7285 static char *FLOOR_L_S(uint64 instruction, Dis_info *info) 7286 { 7287 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 7288 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 7289 7290 const char *ft = FPR(ft_value, info); 7291 const char *fs = FPR(fs_value, info); 7292 7293 return img_format("FLOOR.L.S %s, %s", ft, fs); 7294 } 7295 7296 7297 /* 7298 * 7299 * 7300 * 3 2 1 7301 * 10987654321098765432109876543210 7302 * 001000 x1110000101 7303 * rt ----- 7304 * rs ----- 7305 * rd ----- 7306 */ 7307 static char *FLOOR_W_D(uint64 instruction, Dis_info *info) 7308 { 7309 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 7310 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 7311 7312 const char *ft = FPR(ft_value, info); 7313 const char *fs = FPR(fs_value, info); 7314 7315 return img_format("FLOOR.W.D %s, %s", ft, fs); 7316 } 7317 7318 7319 /* 7320 * 7321 * 7322 * 3 2 1 7323 * 10987654321098765432109876543210 7324 * 001000 x1110000101 7325 * rt ----- 7326 * rs ----- 7327 * rd ----- 7328 */ 7329 static char *FLOOR_W_S(uint64 instruction, Dis_info *info) 7330 { 7331 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 7332 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 7333 7334 const char *ft = FPR(ft_value, info); 7335 const char *fs = FPR(fs_value, info); 7336 7337 return img_format("FLOOR.W.S %s, %s", ft, fs); 7338 } 7339 7340 7341 /* 7342 * 7343 * 7344 * 3 2 1 7345 * 10987654321098765432109876543210 7346 * 001000 x1110000101 7347 * rt ----- 7348 * rs ----- 7349 * rd ----- 7350 */ 7351 static char *FORK(uint64 instruction, Dis_info *info) 7352 { 7353 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7354 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7355 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 7356 7357 const char *rd = GPR(rd_value, info); 7358 const char *rs = GPR(rs_value, info); 7359 const char *rt = GPR(rt_value, info); 7360 7361 return img_format("FORK %s, %s, %s", rd, rs, rt); 7362 } 7363 7364 7365 /* 7366 * 7367 * 7368 * 3 2 1 7369 * 10987654321098765432109876543210 7370 * 001000 x1110000101 7371 * rt ----- 7372 * rs ----- 7373 * rd ----- 7374 */ 7375 static char *HYPCALL(uint64 instruction, Dis_info *info) 7376 { 7377 uint64 code_value = extract_code_17_to_0(instruction); 7378 7379 7380 return img_format("HYPCALL 0x%" PRIx64, code_value); 7381 } 7382 7383 7384 /* 7385 * 7386 * 7387 * 3 2 1 7388 * 10987654321098765432109876543210 7389 * 001000 x1110000101 7390 * rt ----- 7391 * rs ----- 7392 * rd ----- 7393 */ 7394 static char *HYPCALL_16_(uint64 instruction, Dis_info *info) 7395 { 7396 uint64 code_value = extract_code_1_0(instruction); 7397 7398 7399 return img_format("HYPCALL 0x%" PRIx64, code_value); 7400 } 7401 7402 7403 /* 7404 * 7405 * 7406 * 3 2 1 7407 * 10987654321098765432109876543210 7408 * 001000 x1110000101 7409 * rt ----- 7410 * rs ----- 7411 * rd ----- 7412 */ 7413 static char *INS(uint64 instruction, Dis_info *info) 7414 { 7415 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7416 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7417 uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); 7418 uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); 7419 7420 const char *rt = GPR(rt_value, info); 7421 const char *rs = GPR(rs_value, info); 7422 /* !!!!!!!!!! - no conversion function */ 7423 7424 return img_format("INS %s, %s, 0x%" PRIx64 ", 0x%" PRIx64, 7425 rt, rs, lsb_value, msbd_value); 7426 /* hand edited */ 7427 } 7428 7429 7430 /* 7431 * [DSP] INSV rt, rs - Insert bit field variable 7432 * 7433 * 3 2 1 7434 * 10987654321098765432109876543210 7435 * 001000 0100000100111111 7436 * rt ----- 7437 * rs ----- 7438 */ 7439 static char *INSV(uint64 instruction, Dis_info *info) 7440 { 7441 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7442 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7443 7444 const char *rt = GPR(rt_value, info); 7445 const char *rs = GPR(rs_value, info); 7446 7447 return img_format("INSV %s, %s", rt, rs); 7448 } 7449 7450 7451 /* 7452 * 7453 * 7454 * 3 2 1 7455 * 10987654321098765432109876543210 7456 * 001000 x1110000101 7457 * rt ----- 7458 * rs ----- 7459 * rd ----- 7460 */ 7461 static char *IRET(uint64 instruction, Dis_info *info) 7462 { 7463 (void)instruction; 7464 7465 return g_strdup("IRET "); 7466 } 7467 7468 7469 /* 7470 * 7471 * 7472 * 3 2 1 7473 * 10987654321098765432109876543210 7474 * 001000 x1110000101 7475 * rt ----- 7476 * rs ----- 7477 * rd ----- 7478 */ 7479 static char *JALRC_16_(uint64 instruction, Dis_info *info) 7480 { 7481 uint64 rt_value = extract_rt_9_8_7_6_5(instruction); 7482 7483 const char *rt = GPR(rt_value, info); 7484 7485 return img_format("JALRC $%d, %s", 31, rt); 7486 } 7487 7488 7489 /* 7490 * 7491 * 7492 * 3 2 1 7493 * 10987654321098765432109876543210 7494 * 001000 x1110000101 7495 * rt ----- 7496 * rs ----- 7497 * rd ----- 7498 */ 7499 static char *JALRC_32_(uint64 instruction, Dis_info *info) 7500 { 7501 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7502 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7503 7504 const char *rt = GPR(rt_value, info); 7505 const char *rs = GPR(rs_value, info); 7506 7507 return img_format("JALRC %s, %s", rt, rs); 7508 } 7509 7510 7511 /* 7512 * 7513 * 7514 * 3 2 1 7515 * 10987654321098765432109876543210 7516 * 001000 x1110000101 7517 * rt ----- 7518 * rs ----- 7519 * rd ----- 7520 */ 7521 static char *JALRC_HB(uint64 instruction, Dis_info *info) 7522 { 7523 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7524 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7525 7526 const char *rt = GPR(rt_value, info); 7527 const char *rs = GPR(rs_value, info); 7528 7529 return img_format("JALRC.HB %s, %s", rt, rs); 7530 } 7531 7532 7533 /* 7534 * 7535 * 7536 * 3 2 1 7537 * 10987654321098765432109876543210 7538 * 001000 x1110000101 7539 * rt ----- 7540 * rs ----- 7541 * rd ----- 7542 */ 7543 static char *JRC(uint64 instruction, Dis_info *info) 7544 { 7545 uint64 rt_value = extract_rt_9_8_7_6_5(instruction); 7546 7547 const char *rt = GPR(rt_value, info); 7548 7549 return img_format("JRC %s", rt); 7550 } 7551 7552 7553 /* 7554 * 7555 * 7556 * 3 2 1 7557 * 10987654321098765432109876543210 7558 * 001000 x1110000101 7559 * rt ----- 7560 * rs ----- 7561 * rd ----- 7562 */ 7563 static char *LB_16_(uint64 instruction, Dis_info *info) 7564 { 7565 uint64 rt3_value = extract_rt3_9_8_7(instruction); 7566 uint64 rs3_value = extract_rs3_6_5_4(instruction); 7567 uint64 u_value = extract_u_1_0(instruction); 7568 7569 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 7570 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 7571 7572 return img_format("LB %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3); 7573 } 7574 7575 7576 /* 7577 * 7578 * 7579 * 3 2 1 7580 * 10987654321098765432109876543210 7581 * 001000 x1110000101 7582 * rt ----- 7583 * rs ----- 7584 * rd ----- 7585 */ 7586 static char *LB_GP_(uint64 instruction, Dis_info *info) 7587 { 7588 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7589 uint64 u_value = extract_u_17_to_0(instruction); 7590 7591 const char *rt = GPR(rt_value, info); 7592 7593 return img_format("LB %s, 0x%" PRIx64 "($%d)", rt, u_value, 28); 7594 } 7595 7596 7597 /* 7598 * 7599 * 7600 * 3 2 1 7601 * 10987654321098765432109876543210 7602 * 001000 x1110000101 7603 * rt ----- 7604 * rs ----- 7605 * rd ----- 7606 */ 7607 static char *LB_S9_(uint64 instruction, Dis_info *info) 7608 { 7609 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7610 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7611 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 7612 7613 const char *rt = GPR(rt_value, info); 7614 const char *rs = GPR(rs_value, info); 7615 7616 return img_format("LB %s, %" PRId64 "(%s)", rt, s_value, rs); 7617 } 7618 7619 7620 /* 7621 * 7622 * 7623 * 3 2 1 7624 * 10987654321098765432109876543210 7625 * 001000 x1110000101 7626 * rt ----- 7627 * rs ----- 7628 * rd ----- 7629 */ 7630 static char *LB_U12_(uint64 instruction, Dis_info *info) 7631 { 7632 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7633 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7634 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 7635 7636 const char *rt = GPR(rt_value, info); 7637 const char *rs = GPR(rs_value, info); 7638 7639 return img_format("LB %s, 0x%" PRIx64 "(%s)", rt, u_value, rs); 7640 } 7641 7642 7643 /* 7644 * 7645 * 7646 * 3 2 1 7647 * 10987654321098765432109876543210 7648 * 001000 x1110000101 7649 * rt ----- 7650 * rs ----- 7651 * rd ----- 7652 */ 7653 static char *LBE(uint64 instruction, Dis_info *info) 7654 { 7655 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7656 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7657 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 7658 7659 const char *rt = GPR(rt_value, info); 7660 const char *rs = GPR(rs_value, info); 7661 7662 return img_format("LBE %s, %" PRId64 "(%s)", rt, s_value, rs); 7663 } 7664 7665 7666 /* 7667 * 7668 * 7669 * 3 2 1 7670 * 10987654321098765432109876543210 7671 * 001000 x1110000101 7672 * rt ----- 7673 * rs ----- 7674 * rd ----- 7675 */ 7676 static char *LBU_16_(uint64 instruction, Dis_info *info) 7677 { 7678 uint64 rt3_value = extract_rt3_9_8_7(instruction); 7679 uint64 rs3_value = extract_rs3_6_5_4(instruction); 7680 uint64 u_value = extract_u_1_0(instruction); 7681 7682 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 7683 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 7684 7685 return img_format("LBU %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3); 7686 } 7687 7688 7689 /* 7690 * 7691 * 7692 * 3 2 1 7693 * 10987654321098765432109876543210 7694 * 001000 x1110000101 7695 * rt ----- 7696 * rs ----- 7697 * rd ----- 7698 */ 7699 static char *LBU_GP_(uint64 instruction, Dis_info *info) 7700 { 7701 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7702 uint64 u_value = extract_u_17_to_0(instruction); 7703 7704 const char *rt = GPR(rt_value, info); 7705 7706 return img_format("LBU %s, 0x%" PRIx64 "($%d)", rt, u_value, 28); 7707 } 7708 7709 7710 /* 7711 * 7712 * 7713 * 3 2 1 7714 * 10987654321098765432109876543210 7715 * 001000 x1110000101 7716 * rt ----- 7717 * rs ----- 7718 * rd ----- 7719 */ 7720 static char *LBU_S9_(uint64 instruction, Dis_info *info) 7721 { 7722 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7723 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7724 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 7725 7726 const char *rt = GPR(rt_value, info); 7727 const char *rs = GPR(rs_value, info); 7728 7729 return img_format("LBU %s, %" PRId64 "(%s)", rt, s_value, rs); 7730 } 7731 7732 7733 /* 7734 * 7735 * 7736 * 3 2 1 7737 * 10987654321098765432109876543210 7738 * 001000 x1110000101 7739 * rt ----- 7740 * rs ----- 7741 * rd ----- 7742 */ 7743 static char *LBU_U12_(uint64 instruction, Dis_info *info) 7744 { 7745 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7746 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7747 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 7748 7749 const char *rt = GPR(rt_value, info); 7750 const char *rs = GPR(rs_value, info); 7751 7752 return img_format("LBU %s, 0x%" PRIx64 "(%s)", rt, u_value, rs); 7753 } 7754 7755 7756 /* 7757 * 7758 * 7759 * 3 2 1 7760 * 10987654321098765432109876543210 7761 * 001000 x1110000101 7762 * rt ----- 7763 * rs ----- 7764 * rd ----- 7765 */ 7766 static char *LBUE(uint64 instruction, Dis_info *info) 7767 { 7768 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7769 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7770 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 7771 7772 const char *rt = GPR(rt_value, info); 7773 const char *rs = GPR(rs_value, info); 7774 7775 return img_format("LBUE %s, %" PRId64 "(%s)", rt, s_value, rs); 7776 } 7777 7778 7779 /* 7780 * 7781 * 7782 * 3 2 1 7783 * 10987654321098765432109876543210 7784 * 001000 x1110000101 7785 * rt ----- 7786 * rs ----- 7787 * rd ----- 7788 */ 7789 static char *LBUX(uint64 instruction, Dis_info *info) 7790 { 7791 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7792 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7793 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 7794 7795 const char *rd = GPR(rd_value, info); 7796 const char *rs = GPR(rs_value, info); 7797 const char *rt = GPR(rt_value, info); 7798 7799 return img_format("LBUX %s, %s(%s)", rd, rs, rt); 7800 } 7801 7802 7803 /* 7804 * 7805 * 7806 * 3 2 1 7807 * 10987654321098765432109876543210 7808 * 001000 x1110000101 7809 * rt ----- 7810 * rs ----- 7811 * rd ----- 7812 */ 7813 static char *LBX(uint64 instruction, Dis_info *info) 7814 { 7815 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7816 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7817 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 7818 7819 const char *rd = GPR(rd_value, info); 7820 const char *rs = GPR(rs_value, info); 7821 const char *rt = GPR(rt_value, info); 7822 7823 return img_format("LBX %s, %s(%s)", rd, rs, rt); 7824 } 7825 7826 7827 /* 7828 * 7829 * 7830 * 3 2 1 7831 * 10987654321098765432109876543210 7832 * 001000 x1110000101 7833 * rt ----- 7834 * rs ----- 7835 * rd ----- 7836 */ 7837 static char *LD_GP_(uint64 instruction, Dis_info *info) 7838 { 7839 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7840 uint64 u_value = extract_u_20_to_3__s3(instruction); 7841 7842 const char *rt = GPR(rt_value, info); 7843 7844 return img_format("LD %s, 0x%" PRIx64 "($%d)", rt, u_value, 28); 7845 } 7846 7847 7848 /* 7849 * 7850 * 7851 * 3 2 1 7852 * 10987654321098765432109876543210 7853 * 001000 x1110000101 7854 * rt ----- 7855 * rs ----- 7856 * rd ----- 7857 */ 7858 static char *LD_S9_(uint64 instruction, Dis_info *info) 7859 { 7860 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7861 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7862 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 7863 7864 const char *rt = GPR(rt_value, info); 7865 const char *rs = GPR(rs_value, info); 7866 7867 return img_format("LD %s, %" PRId64 "(%s)", rt, s_value, rs); 7868 } 7869 7870 7871 /* 7872 * 7873 * 7874 * 3 2 1 7875 * 10987654321098765432109876543210 7876 * 001000 x1110000101 7877 * rt ----- 7878 * rs ----- 7879 * rd ----- 7880 */ 7881 static char *LD_U12_(uint64 instruction, Dis_info *info) 7882 { 7883 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7884 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7885 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 7886 7887 const char *rt = GPR(rt_value, info); 7888 const char *rs = GPR(rs_value, info); 7889 7890 return img_format("LD %s, 0x%" PRIx64 "(%s)", rt, u_value, rs); 7891 } 7892 7893 7894 /* 7895 * 7896 * 7897 * 3 2 1 7898 * 10987654321098765432109876543210 7899 * 001000 x1110000101 7900 * rt ----- 7901 * rs ----- 7902 * rd ----- 7903 */ 7904 static char *LDC1_GP_(uint64 instruction, Dis_info *info) 7905 { 7906 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 7907 uint64 u_value = extract_u_17_to_2__s2(instruction); 7908 7909 const char *ft = FPR(ft_value, info); 7910 7911 return img_format("LDC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28); 7912 } 7913 7914 7915 /* 7916 * 7917 * 7918 * 3 2 1 7919 * 10987654321098765432109876543210 7920 * 001000 x1110000101 7921 * rt ----- 7922 * rs ----- 7923 * rd ----- 7924 */ 7925 static char *LDC1_S9_(uint64 instruction, Dis_info *info) 7926 { 7927 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 7928 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7929 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 7930 7931 const char *ft = FPR(ft_value, info); 7932 const char *rs = GPR(rs_value, info); 7933 7934 return img_format("LDC1 %s, %" PRId64 "(%s)", ft, s_value, rs); 7935 } 7936 7937 7938 /* 7939 * 7940 * 7941 * 3 2 1 7942 * 10987654321098765432109876543210 7943 * 001000 x1110000101 7944 * rt ----- 7945 * rs ----- 7946 * rd ----- 7947 */ 7948 static char *LDC1_U12_(uint64 instruction, Dis_info *info) 7949 { 7950 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 7951 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7952 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 7953 7954 const char *ft = FPR(ft_value, info); 7955 const char *rs = GPR(rs_value, info); 7956 7957 return img_format("LDC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs); 7958 } 7959 7960 7961 /* 7962 * 7963 * 7964 * 3 2 1 7965 * 10987654321098765432109876543210 7966 * 001000 x1110000101 7967 * rt ----- 7968 * rs ----- 7969 * rd ----- 7970 */ 7971 static char *LDC1XS(uint64 instruction, Dis_info *info) 7972 { 7973 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7974 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7975 uint64 ft_value = extract_ft_15_14_13_12_11(instruction); 7976 7977 const char *ft = FPR(ft_value, info); 7978 const char *rs = GPR(rs_value, info); 7979 const char *rt = GPR(rt_value, info); 7980 7981 return img_format("LDC1XS %s, %s(%s)", ft, rs, rt); 7982 } 7983 7984 7985 /* 7986 * 7987 * 7988 * 3 2 1 7989 * 10987654321098765432109876543210 7990 * 001000 x1110000101 7991 * rt ----- 7992 * rs ----- 7993 * rd ----- 7994 */ 7995 static char *LDC1X(uint64 instruction, Dis_info *info) 7996 { 7997 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 7998 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 7999 uint64 ft_value = extract_ft_15_14_13_12_11(instruction); 8000 8001 const char *ft = FPR(ft_value, info); 8002 const char *rs = GPR(rs_value, info); 8003 const char *rt = GPR(rt_value, info); 8004 8005 return img_format("LDC1X %s, %s(%s)", ft, rs, rt); 8006 } 8007 8008 8009 /* 8010 * 8011 * 8012 * 3 2 1 8013 * 10987654321098765432109876543210 8014 * 001000 x1110000101 8015 * rt ----- 8016 * rs ----- 8017 * rd ----- 8018 */ 8019 static char *LDC2(uint64 instruction, Dis_info *info) 8020 { 8021 uint64 ct_value = extract_ct_25_24_23_22_21(instruction); 8022 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8023 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 8024 8025 const char *rs = GPR(rs_value, info); 8026 8027 return img_format("LDC2 CP%" PRIu64 ", %" PRId64 "(%s)", 8028 ct_value, s_value, rs); 8029 } 8030 8031 8032 /* 8033 * 8034 * 8035 * 3 2 1 8036 * 10987654321098765432109876543210 8037 * 001000 x1110000101 8038 * rt ----- 8039 * rs ----- 8040 * rd ----- 8041 */ 8042 static char *LDM(uint64 instruction, Dis_info *info) 8043 { 8044 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8045 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8046 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 8047 uint64 count3_value = extract_count3_14_13_12(instruction); 8048 8049 const char *rt = GPR(rt_value, info); 8050 const char *rs = GPR(rs_value, info); 8051 uint64 count3 = encode_count3_from_count(count3_value); 8052 8053 return img_format("LDM %s, %" PRId64 "(%s), 0x%" PRIx64, 8054 rt, s_value, rs, count3); 8055 } 8056 8057 8058 /* 8059 * 8060 * 8061 * 3 2 1 8062 * 10987654321098765432109876543210 8063 * 001000 x1110000101 8064 * rt ----- 8065 * rs ----- 8066 * rd ----- 8067 */ 8068 static char *LDPC_48_(uint64 instruction, Dis_info *info) 8069 { 8070 uint64 rt_value = extract_rt_41_40_39_38_37(instruction); 8071 int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); 8072 8073 const char *rt = GPR(rt_value, info); 8074 g_autofree char *s = ADDRESS(s_value, 6, info); 8075 8076 return img_format("LDPC %s, %s", rt, s); 8077 } 8078 8079 8080 /* 8081 * 8082 * 8083 * 3 2 1 8084 * 10987654321098765432109876543210 8085 * 001000 x1110000101 8086 * rt ----- 8087 * rs ----- 8088 * rd ----- 8089 */ 8090 static char *LDX(uint64 instruction, Dis_info *info) 8091 { 8092 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8093 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8094 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 8095 8096 const char *rd = GPR(rd_value, info); 8097 const char *rs = GPR(rs_value, info); 8098 const char *rt = GPR(rt_value, info); 8099 8100 return img_format("LDX %s, %s(%s)", rd, rs, rt); 8101 } 8102 8103 8104 /* 8105 * 8106 * 8107 * 3 2 1 8108 * 10987654321098765432109876543210 8109 * 001000 x1110000101 8110 * rt ----- 8111 * rs ----- 8112 * rd ----- 8113 */ 8114 static char *LDXS(uint64 instruction, Dis_info *info) 8115 { 8116 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8117 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8118 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 8119 8120 const char *rd = GPR(rd_value, info); 8121 const char *rs = GPR(rs_value, info); 8122 const char *rt = GPR(rt_value, info); 8123 8124 return img_format("LDXS %s, %s(%s)", rd, rs, rt); 8125 } 8126 8127 8128 /* 8129 * 8130 * 8131 * 3 2 1 8132 * 10987654321098765432109876543210 8133 * 001000 x1110000101 8134 * rt ----- 8135 * rs ----- 8136 * rd ----- 8137 */ 8138 static char *LH_16_(uint64 instruction, Dis_info *info) 8139 { 8140 uint64 rt3_value = extract_rt3_9_8_7(instruction); 8141 uint64 rs3_value = extract_rs3_6_5_4(instruction); 8142 uint64 u_value = extract_u_2_1__s1(instruction); 8143 8144 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 8145 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 8146 8147 return img_format("LH %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3); 8148 } 8149 8150 8151 /* 8152 * 8153 * 8154 * 3 2 1 8155 * 10987654321098765432109876543210 8156 * 001000 x1110000101 8157 * rt ----- 8158 * rs ----- 8159 * rd ----- 8160 */ 8161 static char *LH_GP_(uint64 instruction, Dis_info *info) 8162 { 8163 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8164 uint64 u_value = extract_u_17_to_1__s1(instruction); 8165 8166 const char *rt = GPR(rt_value, info); 8167 8168 return img_format("LH %s, 0x%" PRIx64 "($%d)", rt, u_value, 28); 8169 } 8170 8171 8172 /* 8173 * 8174 * 8175 * 3 2 1 8176 * 10987654321098765432109876543210 8177 * 001000 x1110000101 8178 * rt ----- 8179 * rs ----- 8180 * rd ----- 8181 */ 8182 static char *LH_S9_(uint64 instruction, Dis_info *info) 8183 { 8184 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8185 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8186 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 8187 8188 const char *rt = GPR(rt_value, info); 8189 const char *rs = GPR(rs_value, info); 8190 8191 return img_format("LH %s, %" PRId64 "(%s)", rt, s_value, rs); 8192 } 8193 8194 8195 /* 8196 * 8197 * 8198 * 3 2 1 8199 * 10987654321098765432109876543210 8200 * 001000 x1110000101 8201 * rt ----- 8202 * rs ----- 8203 * rd ----- 8204 */ 8205 static char *LH_U12_(uint64 instruction, Dis_info *info) 8206 { 8207 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8208 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8209 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 8210 8211 const char *rt = GPR(rt_value, info); 8212 const char *rs = GPR(rs_value, info); 8213 8214 return img_format("LH %s, 0x%" PRIx64 "(%s)", rt, u_value, rs); 8215 } 8216 8217 8218 /* 8219 * 8220 * 8221 * 3 2 1 8222 * 10987654321098765432109876543210 8223 * 001000 x1110000101 8224 * rt ----- 8225 * rs ----- 8226 * rd ----- 8227 */ 8228 static char *LHE(uint64 instruction, Dis_info *info) 8229 { 8230 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8231 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8232 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 8233 8234 const char *rt = GPR(rt_value, info); 8235 const char *rs = GPR(rs_value, info); 8236 8237 return img_format("LHE %s, %" PRId64 "(%s)", rt, s_value, rs); 8238 } 8239 8240 8241 /* 8242 * 8243 * 8244 * 3 2 1 8245 * 10987654321098765432109876543210 8246 * 001000 x1110000101 8247 * rt ----- 8248 * rs ----- 8249 * rd ----- 8250 */ 8251 static char *LHU_16_(uint64 instruction, Dis_info *info) 8252 { 8253 uint64 rt3_value = extract_rt3_9_8_7(instruction); 8254 uint64 rs3_value = extract_rs3_6_5_4(instruction); 8255 uint64 u_value = extract_u_2_1__s1(instruction); 8256 8257 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 8258 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 8259 8260 return img_format("LHU %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3); 8261 } 8262 8263 8264 /* 8265 * 8266 * 8267 * 3 2 1 8268 * 10987654321098765432109876543210 8269 * 001000 x1110000101 8270 * rt ----- 8271 * rs ----- 8272 * rd ----- 8273 */ 8274 static char *LHU_GP_(uint64 instruction, Dis_info *info) 8275 { 8276 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8277 uint64 u_value = extract_u_17_to_1__s1(instruction); 8278 8279 const char *rt = GPR(rt_value, info); 8280 8281 return img_format("LHU %s, 0x%" PRIx64 "($%d)", rt, u_value, 28); 8282 } 8283 8284 8285 /* 8286 * 8287 * 8288 * 3 2 1 8289 * 10987654321098765432109876543210 8290 * 001000 x1110000101 8291 * rt ----- 8292 * rs ----- 8293 * rd ----- 8294 */ 8295 static char *LHU_S9_(uint64 instruction, Dis_info *info) 8296 { 8297 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8298 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8299 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 8300 8301 const char *rt = GPR(rt_value, info); 8302 const char *rs = GPR(rs_value, info); 8303 8304 return img_format("LHU %s, %" PRId64 "(%s)", rt, s_value, rs); 8305 } 8306 8307 8308 /* 8309 * 8310 * 8311 * 3 2 1 8312 * 10987654321098765432109876543210 8313 * 001000 x1110000101 8314 * rt ----- 8315 * rs ----- 8316 * rd ----- 8317 */ 8318 static char *LHU_U12_(uint64 instruction, Dis_info *info) 8319 { 8320 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8321 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8322 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 8323 8324 const char *rt = GPR(rt_value, info); 8325 const char *rs = GPR(rs_value, info); 8326 8327 return img_format("LHU %s, 0x%" PRIx64 "(%s)", rt, u_value, rs); 8328 } 8329 8330 8331 /* 8332 * 8333 * 8334 * 3 2 1 8335 * 10987654321098765432109876543210 8336 * 001000 x1110000101 8337 * rt ----- 8338 * rs ----- 8339 * rd ----- 8340 */ 8341 static char *LHUE(uint64 instruction, Dis_info *info) 8342 { 8343 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8344 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8345 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 8346 8347 const char *rt = GPR(rt_value, info); 8348 const char *rs = GPR(rs_value, info); 8349 8350 return img_format("LHUE %s, %" PRId64 "(%s)", rt, s_value, rs); 8351 } 8352 8353 8354 /* 8355 * 8356 * 8357 * 3 2 1 8358 * 10987654321098765432109876543210 8359 * 001000 x1110000101 8360 * rt ----- 8361 * rs ----- 8362 * rd ----- 8363 */ 8364 static char *LHUX(uint64 instruction, Dis_info *info) 8365 { 8366 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8367 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8368 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 8369 8370 const char *rd = GPR(rd_value, info); 8371 const char *rs = GPR(rs_value, info); 8372 const char *rt = GPR(rt_value, info); 8373 8374 return img_format("LHUX %s, %s(%s)", rd, rs, rt); 8375 } 8376 8377 8378 /* 8379 * 8380 * 8381 * 3 2 1 8382 * 10987654321098765432109876543210 8383 * 001000 x1110000101 8384 * rt ----- 8385 * rs ----- 8386 * rd ----- 8387 */ 8388 static char *LHUXS(uint64 instruction, Dis_info *info) 8389 { 8390 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8391 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8392 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 8393 8394 const char *rd = GPR(rd_value, info); 8395 const char *rs = GPR(rs_value, info); 8396 const char *rt = GPR(rt_value, info); 8397 8398 return img_format("LHUXS %s, %s(%s)", rd, rs, rt); 8399 } 8400 8401 8402 /* 8403 * 8404 * 8405 * 3 2 1 8406 * 10987654321098765432109876543210 8407 * 001000 x1110000101 8408 * rt ----- 8409 * rs ----- 8410 * rd ----- 8411 */ 8412 static char *LHXS(uint64 instruction, Dis_info *info) 8413 { 8414 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8415 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8416 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 8417 8418 const char *rd = GPR(rd_value, info); 8419 const char *rs = GPR(rs_value, info); 8420 const char *rt = GPR(rt_value, info); 8421 8422 return img_format("LHXS %s, %s(%s)", rd, rs, rt); 8423 } 8424 8425 8426 /* 8427 * 8428 * 8429 * 3 2 1 8430 * 10987654321098765432109876543210 8431 * 001000 x1110000101 8432 * rt ----- 8433 * rs ----- 8434 * rd ----- 8435 */ 8436 static char *LHX(uint64 instruction, Dis_info *info) 8437 { 8438 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8439 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8440 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 8441 8442 const char *rd = GPR(rd_value, info); 8443 const char *rs = GPR(rs_value, info); 8444 const char *rt = GPR(rt_value, info); 8445 8446 return img_format("LHX %s, %s(%s)", rd, rs, rt); 8447 } 8448 8449 8450 /* 8451 * 8452 * 8453 * 3 2 1 8454 * 10987654321098765432109876543210 8455 * 001000 x1110000101 8456 * rt ----- 8457 * rs ----- 8458 * rd ----- 8459 */ 8460 static char *LI_16_(uint64 instruction, Dis_info *info) 8461 { 8462 uint64 rt3_value = extract_rt3_9_8_7(instruction); 8463 uint64 eu_value = extract_eu_6_5_4_3_2_1_0(instruction); 8464 8465 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 8466 int64 eu = encode_eu_from_s_li16(eu_value); 8467 8468 return img_format("LI %s, %" PRId64, rt3, eu); 8469 } 8470 8471 8472 /* 8473 * 8474 * 8475 * 3 2 1 8476 * 10987654321098765432109876543210 8477 * 001000 x1110000101 8478 * rt ----- 8479 * rs ----- 8480 * rd ----- 8481 */ 8482 static char *LI_48_(uint64 instruction, Dis_info *info) 8483 { 8484 uint64 rt_value = extract_rt_41_40_39_38_37(instruction); 8485 int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); 8486 8487 const char *rt = GPR(rt_value, info); 8488 8489 return img_format("LI %s, %" PRId64, rt, s_value); 8490 } 8491 8492 8493 /* 8494 * 8495 * 8496 * 3 2 1 8497 * 10987654321098765432109876543210 8498 * 001000 x1110000101 8499 * rt ----- 8500 * rs ----- 8501 * rd ----- 8502 */ 8503 static char *LL(uint64 instruction, Dis_info *info) 8504 { 8505 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8506 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8507 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction); 8508 8509 const char *rt = GPR(rt_value, info); 8510 const char *rs = GPR(rs_value, info); 8511 8512 return img_format("LL %s, %" PRId64 "(%s)", rt, s_value, rs); 8513 } 8514 8515 8516 /* 8517 * 8518 * 8519 * 3 2 1 8520 * 10987654321098765432109876543210 8521 * 001000 x1110000101 8522 * rt ----- 8523 * rs ----- 8524 * rd ----- 8525 */ 8526 static char *LLD(uint64 instruction, Dis_info *info) 8527 { 8528 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8529 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8530 int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction); 8531 8532 const char *rt = GPR(rt_value, info); 8533 const char *rs = GPR(rs_value, info); 8534 8535 return img_format("LLD %s, %" PRId64 "(%s)", rt, s_value, rs); 8536 } 8537 8538 8539 /* 8540 * 8541 * 8542 * 3 2 1 8543 * 10987654321098765432109876543210 8544 * 001000 x1110000101 8545 * rt ----- 8546 * rs ----- 8547 * rd ----- 8548 */ 8549 static char *LLDP(uint64 instruction, Dis_info *info) 8550 { 8551 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8552 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8553 uint64 ru_value = extract_ru_7_6_5_4_3(instruction); 8554 8555 const char *rt = GPR(rt_value, info); 8556 const char *ru = GPR(ru_value, info); 8557 const char *rs = GPR(rs_value, info); 8558 8559 return img_format("LLDP %s, %s, (%s)", rt, ru, rs); 8560 } 8561 8562 8563 /* 8564 * 8565 * 8566 * 3 2 1 8567 * 10987654321098765432109876543210 8568 * 001000 x1110000101 8569 * rt ----- 8570 * rs ----- 8571 * rd ----- 8572 */ 8573 static char *LLE(uint64 instruction, Dis_info *info) 8574 { 8575 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8576 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8577 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction); 8578 8579 const char *rt = GPR(rt_value, info); 8580 const char *rs = GPR(rs_value, info); 8581 8582 return img_format("LLE %s, %" PRId64 "(%s)", rt, s_value, rs); 8583 } 8584 8585 8586 /* 8587 * 8588 * 8589 * 3 2 1 8590 * 10987654321098765432109876543210 8591 * 001000 x1110000101 8592 * rt ----- 8593 * rs ----- 8594 * rd ----- 8595 */ 8596 static char *LLWP(uint64 instruction, Dis_info *info) 8597 { 8598 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8599 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8600 uint64 ru_value = extract_ru_7_6_5_4_3(instruction); 8601 8602 const char *rt = GPR(rt_value, info); 8603 const char *ru = GPR(ru_value, info); 8604 const char *rs = GPR(rs_value, info); 8605 8606 return img_format("LLWP %s, %s, (%s)", rt, ru, rs); 8607 } 8608 8609 8610 /* 8611 * 8612 * 8613 * 3 2 1 8614 * 10987654321098765432109876543210 8615 * 001000 x1110000101 8616 * rt ----- 8617 * rs ----- 8618 * rd ----- 8619 */ 8620 static char *LLWPE(uint64 instruction, Dis_info *info) 8621 { 8622 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8623 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8624 uint64 ru_value = extract_ru_7_6_5_4_3(instruction); 8625 8626 const char *rt = GPR(rt_value, info); 8627 const char *ru = GPR(ru_value, info); 8628 const char *rs = GPR(rs_value, info); 8629 8630 return img_format("LLWPE %s, %s, (%s)", rt, ru, rs); 8631 } 8632 8633 8634 /* 8635 * 8636 * 8637 * 3 2 1 8638 * 10987654321098765432109876543210 8639 * 001000 x1110000101 8640 * rt ----- 8641 * rs ----- 8642 * rd ----- 8643 */ 8644 static char *LSA(uint64 instruction, Dis_info *info) 8645 { 8646 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8647 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8648 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 8649 uint64 u2_value = extract_u2_10_9(instruction); 8650 8651 const char *rd = GPR(rd_value, info); 8652 const char *rs = GPR(rs_value, info); 8653 const char *rt = GPR(rt_value, info); 8654 8655 return img_format("LSA %s, %s, %s, 0x%" PRIx64, rd, rs, rt, u2_value); 8656 } 8657 8658 8659 /* 8660 * 8661 * 8662 * 3 2 1 8663 * 10987654321098765432109876543210 8664 * 001000 x1110000101 8665 * rt ----- 8666 * rs ----- 8667 * rd ----- 8668 */ 8669 static char *LUI(uint64 instruction, Dis_info *info) 8670 { 8671 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8672 int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction); 8673 8674 const char *rt = GPR(rt_value, info); 8675 8676 return img_format("LUI %s, %%hi(%" PRId64 ")", rt, s_value); 8677 } 8678 8679 8680 /* 8681 * 8682 * 8683 * 3 2 1 8684 * 10987654321098765432109876543210 8685 * 001000 x1110000101 8686 * rt ----- 8687 * rs ----- 8688 * rd ----- 8689 */ 8690 static char *LW_16_(uint64 instruction, Dis_info *info) 8691 { 8692 uint64 rt3_value = extract_rt3_9_8_7(instruction); 8693 uint64 rs3_value = extract_rs3_6_5_4(instruction); 8694 uint64 u_value = extract_u_3_2_1_0__s2(instruction); 8695 8696 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 8697 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 8698 8699 return img_format("LW %s, 0x%" PRIx64 "(%s)", rt3, u_value, rs3); 8700 } 8701 8702 8703 /* 8704 * 8705 * 8706 * 3 2 1 8707 * 10987654321098765432109876543210 8708 * 001000 x1110000101 8709 * rt ----- 8710 * rs ----- 8711 * rd ----- 8712 */ 8713 static char *LW_4X4_(uint64 instruction, Dis_info *info) 8714 { 8715 uint64 rt4_value = extract_rt4_9_7_6_5(instruction); 8716 uint64 rs4_value = extract_rs4_4_2_1_0(instruction); 8717 uint64 u_value = extract_u_3_8__s2(instruction); 8718 8719 const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info); 8720 const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info); 8721 8722 return img_format("LW %s, 0x%" PRIx64 "(%s)", rt4, u_value, rs4); 8723 } 8724 8725 8726 /* 8727 * 8728 * 8729 * 3 2 1 8730 * 10987654321098765432109876543210 8731 * 001000 x1110000101 8732 * rt ----- 8733 * rs ----- 8734 * rd ----- 8735 */ 8736 static char *LW_GP_(uint64 instruction, Dis_info *info) 8737 { 8738 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8739 uint64 u_value = extract_u_20_to_2__s2(instruction); 8740 8741 const char *rt = GPR(rt_value, info); 8742 8743 return img_format("LW %s, 0x%" PRIx64 "($%d)", rt, u_value, 28); 8744 } 8745 8746 8747 /* 8748 * 8749 * 8750 * 3 2 1 8751 * 10987654321098765432109876543210 8752 * 001000 x1110000101 8753 * rt ----- 8754 * rs ----- 8755 * rd ----- 8756 */ 8757 static char *LW_GP16_(uint64 instruction, Dis_info *info) 8758 { 8759 uint64 rt3_value = extract_rt3_9_8_7(instruction); 8760 uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction); 8761 8762 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 8763 8764 return img_format("LW %s, 0x%" PRIx64 "($%d)", rt3, u_value, 28); 8765 } 8766 8767 8768 /* 8769 * 8770 * 8771 * 3 2 1 8772 * 10987654321098765432109876543210 8773 * 001000 x1110000101 8774 * rt ----- 8775 * rs ----- 8776 * rd ----- 8777 */ 8778 static char *LW_S9_(uint64 instruction, Dis_info *info) 8779 { 8780 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8781 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8782 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 8783 8784 const char *rt = GPR(rt_value, info); 8785 const char *rs = GPR(rs_value, info); 8786 8787 return img_format("LW %s, %" PRId64 "(%s)", rt, s_value, rs); 8788 } 8789 8790 8791 /* 8792 * 8793 * 8794 * 3 2 1 8795 * 10987654321098765432109876543210 8796 * 001000 x1110000101 8797 * rt ----- 8798 * rs ----- 8799 * rd ----- 8800 */ 8801 static char *LW_SP_(uint64 instruction, Dis_info *info) 8802 { 8803 uint64 rt_value = extract_rt_9_8_7_6_5(instruction); 8804 uint64 u_value = extract_u_4_3_2_1_0__s2(instruction); 8805 8806 const char *rt = GPR(rt_value, info); 8807 8808 return img_format("LW %s, 0x%" PRIx64 "($%d)", rt, u_value, 29); 8809 } 8810 8811 8812 /* 8813 * 8814 * 8815 * 3 2 1 8816 * 10987654321098765432109876543210 8817 * 001000 x1110000101 8818 * rt ----- 8819 * rs ----- 8820 * rd ----- 8821 */ 8822 static char *LW_U12_(uint64 instruction, Dis_info *info) 8823 { 8824 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8825 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8826 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 8827 8828 const char *rt = GPR(rt_value, info); 8829 const char *rs = GPR(rs_value, info); 8830 8831 return img_format("LW %s, 0x%" PRIx64 "(%s)", rt, u_value, rs); 8832 } 8833 8834 8835 /* 8836 * 8837 * 8838 * 3 2 1 8839 * 10987654321098765432109876543210 8840 * 001000 x1110000101 8841 * rt ----- 8842 * rs ----- 8843 * rd ----- 8844 */ 8845 static char *LWC1_GP_(uint64 instruction, Dis_info *info) 8846 { 8847 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 8848 uint64 u_value = extract_u_17_to_2__s2(instruction); 8849 8850 const char *ft = FPR(ft_value, info); 8851 8852 return img_format("LWC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28); 8853 } 8854 8855 8856 /* 8857 * 8858 * 8859 * 3 2 1 8860 * 10987654321098765432109876543210 8861 * 001000 x1110000101 8862 * rt ----- 8863 * rs ----- 8864 * rd ----- 8865 */ 8866 static char *LWC1_S9_(uint64 instruction, Dis_info *info) 8867 { 8868 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 8869 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8870 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 8871 8872 const char *ft = FPR(ft_value, info); 8873 const char *rs = GPR(rs_value, info); 8874 8875 return img_format("LWC1 %s, %" PRId64 "(%s)", ft, s_value, rs); 8876 } 8877 8878 8879 /* 8880 * 8881 * 8882 * 3 2 1 8883 * 10987654321098765432109876543210 8884 * 001000 x1110000101 8885 * rt ----- 8886 * rs ----- 8887 * rd ----- 8888 */ 8889 static char *LWC1_U12_(uint64 instruction, Dis_info *info) 8890 { 8891 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 8892 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8893 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 8894 8895 const char *ft = FPR(ft_value, info); 8896 const char *rs = GPR(rs_value, info); 8897 8898 return img_format("LWC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs); 8899 } 8900 8901 8902 /* 8903 * 8904 * 8905 * 3 2 1 8906 * 10987654321098765432109876543210 8907 * 001000 x1110000101 8908 * rt ----- 8909 * rs ----- 8910 * rd ----- 8911 */ 8912 static char *LWC1X(uint64 instruction, Dis_info *info) 8913 { 8914 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8915 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8916 uint64 ft_value = extract_ft_15_14_13_12_11(instruction); 8917 8918 const char *ft = FPR(ft_value, info); 8919 const char *rs = GPR(rs_value, info); 8920 const char *rt = GPR(rt_value, info); 8921 8922 return img_format("LWC1X %s, %s(%s)", ft, rs, rt); 8923 } 8924 8925 8926 /* 8927 * 8928 * 8929 * 3 2 1 8930 * 10987654321098765432109876543210 8931 * 001000 x1110000101 8932 * rt ----- 8933 * rs ----- 8934 * rd ----- 8935 */ 8936 static char *LWC1XS(uint64 instruction, Dis_info *info) 8937 { 8938 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8939 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8940 uint64 ft_value = extract_ft_15_14_13_12_11(instruction); 8941 8942 const char *ft = FPR(ft_value, info); 8943 const char *rs = GPR(rs_value, info); 8944 const char *rt = GPR(rt_value, info); 8945 8946 return img_format("LWC1XS %s, %s(%s)", ft, rs, rt); 8947 } 8948 8949 8950 /* 8951 * 8952 * 8953 * 3 2 1 8954 * 10987654321098765432109876543210 8955 * 001000 x1110000101 8956 * rt ----- 8957 * rs ----- 8958 * rd ----- 8959 */ 8960 static char *LWC2(uint64 instruction, Dis_info *info) 8961 { 8962 uint64 ct_value = extract_ct_25_24_23_22_21(instruction); 8963 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8964 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 8965 8966 const char *rs = GPR(rs_value, info); 8967 8968 return img_format("LWC2 CP%" PRIu64 ", %" PRId64 "(%s)", 8969 ct_value, s_value, rs); 8970 } 8971 8972 8973 /* 8974 * 8975 * 8976 * 3 2 1 8977 * 10987654321098765432109876543210 8978 * 001000 x1110000101 8979 * rt ----- 8980 * rs ----- 8981 * rd ----- 8982 */ 8983 static char *LWE(uint64 instruction, Dis_info *info) 8984 { 8985 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 8986 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 8987 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 8988 8989 const char *rt = GPR(rt_value, info); 8990 const char *rs = GPR(rs_value, info); 8991 8992 return img_format("LWE %s, %" PRId64 "(%s)", rt, s_value, rs); 8993 } 8994 8995 8996 /* 8997 * 8998 * 8999 * 3 2 1 9000 * 10987654321098765432109876543210 9001 * 001000 x1110000101 9002 * rt ----- 9003 * rs ----- 9004 * rd ----- 9005 */ 9006 static char *LWM(uint64 instruction, Dis_info *info) 9007 { 9008 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9009 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9010 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 9011 uint64 count3_value = extract_count3_14_13_12(instruction); 9012 9013 const char *rt = GPR(rt_value, info); 9014 const char *rs = GPR(rs_value, info); 9015 uint64 count3 = encode_count3_from_count(count3_value); 9016 9017 return img_format("LWM %s, %" PRId64 "(%s), 0x%" PRIx64, 9018 rt, s_value, rs, count3); 9019 } 9020 9021 9022 /* 9023 * 9024 * 9025 * 3 2 1 9026 * 10987654321098765432109876543210 9027 * 001000 x1110000101 9028 * rt ----- 9029 * rs ----- 9030 * rd ----- 9031 */ 9032 static char *LWPC_48_(uint64 instruction, Dis_info *info) 9033 { 9034 uint64 rt_value = extract_rt_41_40_39_38_37(instruction); 9035 int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); 9036 9037 const char *rt = GPR(rt_value, info); 9038 g_autofree char *s = ADDRESS(s_value, 6, info); 9039 9040 return img_format("LWPC %s, %s", rt, s); 9041 } 9042 9043 9044 /* 9045 * 9046 * 9047 * 3 2 1 9048 * 10987654321098765432109876543210 9049 * 001000 x1110000101 9050 * rt ----- 9051 * rs ----- 9052 * rd ----- 9053 */ 9054 static char *LWU_GP_(uint64 instruction, Dis_info *info) 9055 { 9056 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9057 uint64 u_value = extract_u_17_to_2__s2(instruction); 9058 9059 const char *rt = GPR(rt_value, info); 9060 9061 return img_format("LWU %s, 0x%" PRIx64 "($%d)", rt, u_value, 28); 9062 } 9063 9064 9065 /* 9066 * 9067 * 9068 * 3 2 1 9069 * 10987654321098765432109876543210 9070 * 001000 x1110000101 9071 * rt ----- 9072 * rs ----- 9073 * rd ----- 9074 */ 9075 static char *LWU_S9_(uint64 instruction, Dis_info *info) 9076 { 9077 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9078 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9079 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 9080 9081 const char *rt = GPR(rt_value, info); 9082 const char *rs = GPR(rs_value, info); 9083 9084 return img_format("LWU %s, %" PRId64 "(%s)", rt, s_value, rs); 9085 } 9086 9087 9088 /* 9089 * 9090 * 9091 * 3 2 1 9092 * 10987654321098765432109876543210 9093 * 001000 x1110000101 9094 * rt ----- 9095 * rs ----- 9096 * rd ----- 9097 */ 9098 static char *LWU_U12_(uint64 instruction, Dis_info *info) 9099 { 9100 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9101 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9102 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 9103 9104 const char *rt = GPR(rt_value, info); 9105 const char *rs = GPR(rs_value, info); 9106 9107 return img_format("LWU %s, 0x%" PRIx64 "(%s)", rt, u_value, rs); 9108 } 9109 9110 9111 /* 9112 * 9113 * 9114 * 3 2 1 9115 * 10987654321098765432109876543210 9116 * 001000 x1110000101 9117 * rt ----- 9118 * rs ----- 9119 * rd ----- 9120 */ 9121 static char *LWUX(uint64 instruction, Dis_info *info) 9122 { 9123 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9124 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9125 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 9126 9127 const char *rd = GPR(rd_value, info); 9128 const char *rs = GPR(rs_value, info); 9129 const char *rt = GPR(rt_value, info); 9130 9131 return img_format("LWUX %s, %s(%s)", rd, rs, rt); 9132 } 9133 9134 9135 /* 9136 * 9137 * 9138 * 3 2 1 9139 * 10987654321098765432109876543210 9140 * 001000 x1110000101 9141 * rt ----- 9142 * rs ----- 9143 * rd ----- 9144 */ 9145 static char *LWUXS(uint64 instruction, Dis_info *info) 9146 { 9147 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9148 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9149 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 9150 9151 const char *rd = GPR(rd_value, info); 9152 const char *rs = GPR(rs_value, info); 9153 const char *rt = GPR(rt_value, info); 9154 9155 return img_format("LWUXS %s, %s(%s)", rd, rs, rt); 9156 } 9157 9158 9159 /* 9160 * 9161 * 9162 * 3 2 1 9163 * 10987654321098765432109876543210 9164 * 001000 x1110000101 9165 * rt ----- 9166 * rs ----- 9167 * rd ----- 9168 */ 9169 static char *LWX(uint64 instruction, Dis_info *info) 9170 { 9171 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9172 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9173 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 9174 9175 const char *rd = GPR(rd_value, info); 9176 const char *rs = GPR(rs_value, info); 9177 const char *rt = GPR(rt_value, info); 9178 9179 return img_format("LWX %s, %s(%s)", rd, rs, rt); 9180 } 9181 9182 9183 /* 9184 * 9185 * 9186 * 3 2 1 9187 * 10987654321098765432109876543210 9188 * 001000 x1110000101 9189 * rt ----- 9190 * rs ----- 9191 * rd ----- 9192 */ 9193 static char *LWXS_16_(uint64 instruction, Dis_info *info) 9194 { 9195 uint64 rt3_value = extract_rt3_9_8_7(instruction); 9196 uint64 rs3_value = extract_rs3_6_5_4(instruction); 9197 uint64 rd3_value = extract_rd3_3_2_1(instruction); 9198 9199 const char *rd3 = GPR(decode_gpr_gpr3(rd3_value, info), info); 9200 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 9201 uint64 rt3 = decode_gpr_gpr3(rt3_value, info); 9202 9203 return img_format("LWXS %s, %s(0x%" PRIx64 ")", rd3, rs3, rt3); 9204 } 9205 9206 9207 /* 9208 * 9209 * 9210 * 3 2 1 9211 * 10987654321098765432109876543210 9212 * 001000 x1110000101 9213 * rt ----- 9214 * rs ----- 9215 * rd ----- 9216 */ 9217 static char *LWXS_32_(uint64 instruction, Dis_info *info) 9218 { 9219 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9220 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9221 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 9222 9223 const char *rd = GPR(rd_value, info); 9224 const char *rs = GPR(rs_value, info); 9225 const char *rt = GPR(rt_value, info); 9226 9227 return img_format("LWXS %s, %s(%s)", rd, rs, rt); 9228 } 9229 9230 9231 /* 9232 * [DSP] MADD ac, rs, rt - Multiply two words and add to the specified 9233 * accumulator 9234 * 9235 * 3 2 1 9236 * 10987654321098765432109876543210 9237 * 001000 x1110000101 9238 * rt ----- 9239 * rs ----- 9240 * rd ----- 9241 */ 9242 static char *MADD_DSP_(uint64 instruction, Dis_info *info) 9243 { 9244 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9245 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9246 uint64 ac_value = extract_ac_15_14(instruction); 9247 9248 const char *ac = AC(ac_value, info); 9249 const char *rs = GPR(rs_value, info); 9250 const char *rt = GPR(rt_value, info); 9251 9252 return img_format("MADD %s, %s, %s", ac, rs, rt); 9253 } 9254 9255 9256 /* 9257 * 9258 * 9259 * 3 2 1 9260 * 10987654321098765432109876543210 9261 * 001000 x1110000101 9262 * rt ----- 9263 * rs ----- 9264 * rd ----- 9265 */ 9266 static char *MADDF_D(uint64 instruction, Dis_info *info) 9267 { 9268 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9269 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9270 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 9271 9272 const char *fd = FPR(fd_value, info); 9273 const char *fs = FPR(fs_value, info); 9274 const char *ft = FPR(ft_value, info); 9275 9276 return img_format("MADDF.D %s, %s, %s", fd, fs, ft); 9277 } 9278 9279 9280 /* 9281 * 9282 * 9283 * 3 2 1 9284 * 10987654321098765432109876543210 9285 * 001000 x1110000101 9286 * rt ----- 9287 * rs ----- 9288 * rd ----- 9289 */ 9290 static char *MADDF_S(uint64 instruction, Dis_info *info) 9291 { 9292 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9293 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9294 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 9295 9296 const char *fd = FPR(fd_value, info); 9297 const char *fs = FPR(fs_value, info); 9298 const char *ft = FPR(ft_value, info); 9299 9300 return img_format("MADDF.S %s, %s, %s", fd, fs, ft); 9301 } 9302 9303 9304 /* 9305 * [DSP] MADDU ac, rs, rt - Multiply two unsigned words and add to the 9306 * specified accumulator 9307 * 9308 * 3 2 1 9309 * 10987654321098765432109876543210 9310 * 001000 x1110000101 9311 * rt ----- 9312 * rs ----- 9313 * rd ----- 9314 */ 9315 static char *MADDU_DSP_(uint64 instruction, Dis_info *info) 9316 { 9317 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9318 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9319 uint64 ac_value = extract_ac_15_14(instruction); 9320 9321 const char *ac = AC(ac_value, info); 9322 const char *rs = GPR(rs_value, info); 9323 const char *rt = GPR(rt_value, info); 9324 9325 return img_format("MADDU %s, %s, %s", ac, rs, rt); 9326 } 9327 9328 9329 /* 9330 * [DSP] MAQ_S.W.PHL ac, rs, rt - Multiply the left-most single vector 9331 * fractional halfword elements with accumulation 9332 * 9333 * 3 2 1 9334 * 10987654321098765432109876543210 9335 * 001000 x1110000101 9336 * rt ----- 9337 * rs ----- 9338 * rd ----- 9339 */ 9340 static char *MAQ_S_W_PHL(uint64 instruction, Dis_info *info) 9341 { 9342 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9343 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9344 uint64 ac_value = extract_ac_15_14(instruction); 9345 9346 const char *ac = AC(ac_value, info); 9347 const char *rs = GPR(rs_value, info); 9348 const char *rt = GPR(rt_value, info); 9349 9350 return img_format("MAQ_S.W.PHL %s, %s, %s", ac, rs, rt); 9351 } 9352 9353 9354 /* 9355 * [DSP] MAQ_S.W.PHR ac, rs, rt - Multiply the right-most single vector 9356 * fractional halfword elements with accumulation 9357 * 9358 * 3 2 1 9359 * 10987654321098765432109876543210 9360 * 001000 x1110000101 9361 * rt ----- 9362 * rs ----- 9363 * rd ----- 9364 */ 9365 static char *MAQ_S_W_PHR(uint64 instruction, Dis_info *info) 9366 { 9367 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9368 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9369 uint64 ac_value = extract_ac_15_14(instruction); 9370 9371 const char *ac = AC(ac_value, info); 9372 const char *rs = GPR(rs_value, info); 9373 const char *rt = GPR(rt_value, info); 9374 9375 return img_format("MAQ_S.W.PHR %s, %s, %s", ac, rs, rt); 9376 } 9377 9378 9379 /* 9380 * [DSP] MAQ_SA.W.PHL ac, rs, rt - Multiply the left-most single vector 9381 * fractional halfword elements with saturating accumulation 9382 * 9383 * 3 2 1 9384 * 10987654321098765432109876543210 9385 * 001000 x1110000101 9386 * rt ----- 9387 * rs ----- 9388 * rd ----- 9389 */ 9390 static char *MAQ_SA_W_PHL(uint64 instruction, Dis_info *info) 9391 { 9392 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9393 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9394 uint64 ac_value = extract_ac_15_14(instruction); 9395 9396 const char *ac = AC(ac_value, info); 9397 const char *rs = GPR(rs_value, info); 9398 const char *rt = GPR(rt_value, info); 9399 9400 return img_format("MAQ_SA.W.PHL %s, %s, %s", ac, rs, rt); 9401 } 9402 9403 9404 /* 9405 * [DSP] MAQ_SA.W.PHR ac, rs, rt - Multiply the right-most single vector 9406 * fractional halfword elements with saturating accumulation 9407 * 9408 * 3 2 1 9409 * 10987654321098765432109876543210 9410 * 001000 x1110000101 9411 * rt ----- 9412 * rs ----- 9413 * rd ----- 9414 */ 9415 static char *MAQ_SA_W_PHR(uint64 instruction, Dis_info *info) 9416 { 9417 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9418 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9419 uint64 ac_value = extract_ac_15_14(instruction); 9420 9421 const char *ac = AC(ac_value, info); 9422 const char *rs = GPR(rs_value, info); 9423 const char *rt = GPR(rt_value, info); 9424 9425 return img_format("MAQ_SA.W.PHR %s, %s, %s", ac, rs, rt); 9426 } 9427 9428 9429 /* 9430 * 9431 * 9432 * 3 2 1 9433 * 10987654321098765432109876543210 9434 * 001000 x1110000101 9435 * rt ----- 9436 * rs ----- 9437 * rd ----- 9438 */ 9439 static char *MAX_D(uint64 instruction, Dis_info *info) 9440 { 9441 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9442 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9443 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 9444 9445 const char *fd = FPR(fd_value, info); 9446 const char *fs = FPR(fs_value, info); 9447 const char *ft = FPR(ft_value, info); 9448 9449 return img_format("MAX.D %s, %s, %s", fd, fs, ft); 9450 } 9451 9452 9453 /* 9454 * 9455 * 9456 * 3 2 1 9457 * 10987654321098765432109876543210 9458 * 001000 x1110000101 9459 * rt ----- 9460 * rs ----- 9461 * rd ----- 9462 */ 9463 static char *MAX_S(uint64 instruction, Dis_info *info) 9464 { 9465 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9466 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9467 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 9468 9469 const char *fd = FPR(fd_value, info); 9470 const char *fs = FPR(fs_value, info); 9471 const char *ft = FPR(ft_value, info); 9472 9473 return img_format("MAX.S %s, %s, %s", fd, fs, ft); 9474 } 9475 9476 9477 /* 9478 * 9479 * 9480 * 3 2 1 9481 * 10987654321098765432109876543210 9482 * 001000 x1110000101 9483 * rt ----- 9484 * rs ----- 9485 * rd ----- 9486 */ 9487 static char *MAXA_D(uint64 instruction, Dis_info *info) 9488 { 9489 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9490 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9491 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 9492 9493 const char *fd = FPR(fd_value, info); 9494 const char *fs = FPR(fs_value, info); 9495 const char *ft = FPR(ft_value, info); 9496 9497 return img_format("MAXA.D %s, %s, %s", fd, fs, ft); 9498 } 9499 9500 9501 /* 9502 * 9503 * 9504 * 3 2 1 9505 * 10987654321098765432109876543210 9506 * 001000 x1110000101 9507 * rt ----- 9508 * rs ----- 9509 * rd ----- 9510 */ 9511 static char *MAXA_S(uint64 instruction, Dis_info *info) 9512 { 9513 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9514 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9515 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 9516 9517 const char *fd = FPR(fd_value, info); 9518 const char *fs = FPR(fs_value, info); 9519 const char *ft = FPR(ft_value, info); 9520 9521 return img_format("MAXA.S %s, %s, %s", fd, fs, ft); 9522 } 9523 9524 9525 /* 9526 * 9527 * 9528 * 3 2 1 9529 * 10987654321098765432109876543210 9530 * 001000 x1110000101 9531 * rt ----- 9532 * rs ----- 9533 * rd ----- 9534 */ 9535 static char *MFC0(uint64 instruction, Dis_info *info) 9536 { 9537 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9538 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 9539 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 9540 9541 const char *rt = GPR(rt_value, info); 9542 9543 return img_format("MFC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 9544 rt, c0s_value, sel_value); 9545 } 9546 9547 9548 /* 9549 * 9550 * 9551 * 3 2 1 9552 * 10987654321098765432109876543210 9553 * 001000 x1110000101 9554 * rt ----- 9555 * rs ----- 9556 * rd ----- 9557 */ 9558 static char *MFC1(uint64 instruction, Dis_info *info) 9559 { 9560 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9561 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9562 9563 const char *rt = GPR(rt_value, info); 9564 const char *fs = FPR(fs_value, info); 9565 9566 return img_format("MFC1 %s, %s", rt, fs); 9567 } 9568 9569 9570 /* 9571 * 9572 * 9573 * 3 2 1 9574 * 10987654321098765432109876543210 9575 * 001000 x1110000101 9576 * rt ----- 9577 * rs ----- 9578 * rd ----- 9579 */ 9580 static char *MFC2(uint64 instruction, Dis_info *info) 9581 { 9582 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9583 uint64 cs_value = extract_cs_20_19_18_17_16(instruction); 9584 9585 const char *rt = GPR(rt_value, info); 9586 9587 return img_format("MFC2 %s, CP%" PRIu64, rt, cs_value); 9588 } 9589 9590 9591 /* 9592 * 9593 * 9594 * 3 2 1 9595 * 10987654321098765432109876543210 9596 * 001000 x1110000101 9597 * rt ----- 9598 * rs ----- 9599 * rd ----- 9600 */ 9601 static char *MFGC0(uint64 instruction, Dis_info *info) 9602 { 9603 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9604 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 9605 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 9606 9607 const char *rt = GPR(rt_value, info); 9608 9609 return img_format("MFGC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 9610 rt, c0s_value, sel_value); 9611 } 9612 9613 9614 /* 9615 * 9616 * 9617 * 3 2 1 9618 * 10987654321098765432109876543210 9619 * 001000 x1110000101 9620 * rt ----- 9621 * rs ----- 9622 * rd ----- 9623 */ 9624 static char *MFHC0(uint64 instruction, Dis_info *info) 9625 { 9626 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9627 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 9628 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 9629 9630 const char *rt = GPR(rt_value, info); 9631 9632 return img_format("MFHC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 9633 rt, c0s_value, sel_value); 9634 } 9635 9636 9637 /* 9638 * 9639 * 9640 * 3 2 1 9641 * 10987654321098765432109876543210 9642 * 001000 x1110000101 9643 * rt ----- 9644 * rs ----- 9645 * rd ----- 9646 */ 9647 static char *MFHC1(uint64 instruction, Dis_info *info) 9648 { 9649 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9650 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9651 9652 const char *rt = GPR(rt_value, info); 9653 const char *fs = FPR(fs_value, info); 9654 9655 return img_format("MFHC1 %s, %s", rt, fs); 9656 } 9657 9658 9659 /* 9660 * 9661 * 9662 * 3 2 1 9663 * 10987654321098765432109876543210 9664 * 001000 x1110000101 9665 * rt ----- 9666 * rs ----- 9667 * rd ----- 9668 */ 9669 static char *MFHC2(uint64 instruction, Dis_info *info) 9670 { 9671 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9672 uint64 cs_value = extract_cs_20_19_18_17_16(instruction); 9673 9674 const char *rt = GPR(rt_value, info); 9675 9676 return img_format("MFHC2 %s, CP%" PRIu64, rt, cs_value); 9677 } 9678 9679 9680 /* 9681 * 9682 * 9683 * 3 2 1 9684 * 10987654321098765432109876543210 9685 * 001000 x1110000101 9686 * rt ----- 9687 * rs ----- 9688 * rd ----- 9689 */ 9690 static char *MFHGC0(uint64 instruction, Dis_info *info) 9691 { 9692 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9693 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 9694 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 9695 9696 const char *rt = GPR(rt_value, info); 9697 9698 return img_format("MFHGC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 9699 rt, c0s_value, sel_value); 9700 } 9701 9702 9703 /* 9704 * [DSP] MFHI rs, ac - Move from HI register 9705 * 9706 * 3 2 1 9707 * 10987654321098765432109876543210 9708 * 001000 xxxxx 00000001111111 9709 * rt ----- 9710 * ac -- 9711 */ 9712 static char *MFHI_DSP_(uint64 instruction, Dis_info *info) 9713 { 9714 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9715 uint64 ac_value = extract_ac_15_14(instruction); 9716 9717 const char *rt = GPR(rt_value, info); 9718 const char *ac = AC(ac_value, info); 9719 9720 return img_format("MFHI %s, %s", rt, ac); 9721 } 9722 9723 9724 /* 9725 * 9726 * 9727 * 3 2 1 9728 * 10987654321098765432109876543210 9729 * 001000 x1110000101 9730 * rt ----- 9731 * rs ----- 9732 * rd ----- 9733 */ 9734 static char *MFHTR(uint64 instruction, Dis_info *info) 9735 { 9736 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9737 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 9738 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 9739 uint64 u_value = extract_u_10(instruction); 9740 9741 const char *rt = GPR(rt_value, info); 9742 9743 return img_format("MFHTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64, 9744 rt, c0s_value, u_value, sel_value); 9745 } 9746 9747 9748 /* 9749 * [DSP] MFLO rs, ac - Move from HI register 9750 * 9751 * 3 2 1 9752 * 10987654321098765432109876543210 9753 * 001000 xxxxx 01000001111111 9754 * rt ----- 9755 * ac -- 9756 */ 9757 static char *MFLO_DSP_(uint64 instruction, Dis_info *info) 9758 { 9759 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9760 uint64 ac_value = extract_ac_15_14(instruction); 9761 9762 const char *rt = GPR(rt_value, info); 9763 const char *ac = AC(ac_value, info); 9764 9765 return img_format("MFLO %s, %s", rt, ac); 9766 } 9767 9768 9769 /* 9770 * 9771 * 9772 * 3 2 1 9773 * 10987654321098765432109876543210 9774 * 001000 x1110000101 9775 * rt ----- 9776 * rs ----- 9777 * rd ----- 9778 */ 9779 static char *MFTR(uint64 instruction, Dis_info *info) 9780 { 9781 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9782 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 9783 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 9784 uint64 u_value = extract_u_10(instruction); 9785 9786 const char *rt = GPR(rt_value, info); 9787 9788 return img_format("MFTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64, 9789 rt, c0s_value, u_value, sel_value); 9790 } 9791 9792 9793 /* 9794 * 9795 * 9796 * 3 2 1 9797 * 10987654321098765432109876543210 9798 * 001000 x1110000101 9799 * rt ----- 9800 * rs ----- 9801 * rd ----- 9802 */ 9803 static char *MIN_D(uint64 instruction, Dis_info *info) 9804 { 9805 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9806 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9807 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 9808 9809 const char *fd = FPR(fd_value, info); 9810 const char *fs = FPR(fs_value, info); 9811 const char *ft = FPR(ft_value, info); 9812 9813 return img_format("MIN.D %s, %s, %s", fd, fs, ft); 9814 } 9815 9816 9817 /* 9818 * 9819 * 9820 * 3 2 1 9821 * 10987654321098765432109876543210 9822 * 001000 x1110000101 9823 * rt ----- 9824 * rs ----- 9825 * rd ----- 9826 */ 9827 static char *MIN_S(uint64 instruction, Dis_info *info) 9828 { 9829 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9830 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9831 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 9832 9833 const char *fd = FPR(fd_value, info); 9834 const char *fs = FPR(fs_value, info); 9835 const char *ft = FPR(ft_value, info); 9836 9837 return img_format("MIN.S %s, %s, %s", fd, fs, ft); 9838 } 9839 9840 9841 /* 9842 * 9843 * 9844 * 3 2 1 9845 * 10987654321098765432109876543210 9846 * 001000 x1110000101 9847 * rt ----- 9848 * rs ----- 9849 * rd ----- 9850 */ 9851 static char *MINA_D(uint64 instruction, Dis_info *info) 9852 { 9853 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9854 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9855 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 9856 9857 const char *fd = FPR(fd_value, info); 9858 const char *fs = FPR(fs_value, info); 9859 const char *ft = FPR(ft_value, info); 9860 9861 return img_format("MINA.D %s, %s, %s", fd, fs, ft); 9862 } 9863 9864 9865 /* 9866 * 9867 * 9868 * 3 2 1 9869 * 10987654321098765432109876543210 9870 * 001000 x1110000101 9871 * rt ----- 9872 * rs ----- 9873 * rd ----- 9874 */ 9875 static char *MINA_S(uint64 instruction, Dis_info *info) 9876 { 9877 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9878 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9879 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 9880 9881 const char *fd = FPR(fd_value, info); 9882 const char *fs = FPR(fs_value, info); 9883 const char *ft = FPR(ft_value, info); 9884 9885 return img_format("MINA.S %s, %s, %s", fd, fs, ft); 9886 } 9887 9888 9889 /* 9890 * 9891 * 9892 * 3 2 1 9893 * 10987654321098765432109876543210 9894 * 001000 x1110000101 9895 * rt ----- 9896 * rs ----- 9897 * rd ----- 9898 */ 9899 static char *MOD(uint64 instruction, Dis_info *info) 9900 { 9901 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9902 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9903 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 9904 9905 const char *rd = GPR(rd_value, info); 9906 const char *rs = GPR(rs_value, info); 9907 const char *rt = GPR(rt_value, info); 9908 9909 return img_format("MOD %s, %s, %s", rd, rs, rt); 9910 } 9911 9912 9913 /* 9914 * [DSP] MODSUB rd, rs, rt - Modular subtraction on an index value 9915 * 9916 * 3 2 1 9917 * 10987654321098765432109876543210 9918 * 001000 x1110000101 9919 * rt ----- 9920 * rs ----- 9921 * rd ----- 9922 */ 9923 static char *MODSUB(uint64 instruction, Dis_info *info) 9924 { 9925 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9926 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9927 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 9928 9929 const char *rd = GPR(rd_value, info); 9930 const char *rs = GPR(rs_value, info); 9931 const char *rt = GPR(rt_value, info); 9932 9933 return img_format("MODSUB %s, %s, %s", rd, rs, rt); 9934 } 9935 9936 9937 /* 9938 * 9939 * 9940 * 3 2 1 9941 * 10987654321098765432109876543210 9942 * 001000 x1010010101 9943 * rt ----- 9944 * rs ----- 9945 * rd ----- 9946 */ 9947 static char *MODU(uint64 instruction, Dis_info *info) 9948 { 9949 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 9950 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 9951 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 9952 9953 const char *rd = GPR(rd_value, info); 9954 const char *rs = GPR(rs_value, info); 9955 const char *rt = GPR(rt_value, info); 9956 9957 return img_format("MODU %s, %s, %s", rd, rs, rt); 9958 } 9959 9960 9961 /* 9962 * 9963 * 9964 * 3 2 1 9965 * 10987654321098765432109876543210 9966 * 001000 x1110000101 9967 * rt ----- 9968 * rs ----- 9969 * rd ----- 9970 */ 9971 static char *MOV_D(uint64 instruction, Dis_info *info) 9972 { 9973 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9974 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9975 9976 const char *ft = FPR(ft_value, info); 9977 const char *fs = FPR(fs_value, info); 9978 9979 return img_format("MOV.D %s, %s", ft, fs); 9980 } 9981 9982 9983 /* 9984 * 9985 * 9986 * 3 2 1 9987 * 10987654321098765432109876543210 9988 * 001000 x1110000101 9989 * rt ----- 9990 * rs ----- 9991 * rd ----- 9992 */ 9993 static char *MOV_S(uint64 instruction, Dis_info *info) 9994 { 9995 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 9996 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 9997 9998 const char *ft = FPR(ft_value, info); 9999 const char *fs = FPR(fs_value, info); 10000 10001 return img_format("MOV.S %s, %s", ft, fs); 10002 } 10003 10004 10005 /* 10006 * 10007 * 10008 * 3 2 1 10009 * 10987654321098765432109876543210 10010 * 001000 x1110000101 10011 * rt ----- 10012 * rs ----- 10013 * rd ----- 10014 */ 10015 static char *MOVE_BALC(uint64 instruction, Dis_info *info) 10016 { 10017 uint64 rtz4_value = extract_rtz4_27_26_25_23_22_21(instruction); 10018 uint64 rd1_value = extract_rdl_25_24(instruction); 10019 int64 s_value = extract_s__se21_0_20_to_1_s1(instruction); 10020 10021 const char *rd1 = GPR(decode_gpr_gpr1(rd1_value, info), info); 10022 const char *rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value, info), info); 10023 g_autofree char *s = ADDRESS(s_value, 4, info); 10024 10025 return img_format("MOVE.BALC %s, %s, %s", rd1, rtz4, s); 10026 } 10027 10028 10029 /* 10030 * 10031 * 10032 * 3 2 1 10033 * 10987654321098765432109876543210 10034 * 001000 x1110000101 10035 * rt ----- 10036 * rs ----- 10037 * rd ----- 10038 */ 10039 static char *MOVEP(uint64 instruction, Dis_info *info) 10040 { 10041 uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction); 10042 uint64 rd2_value = extract_rd2_3_8(instruction); 10043 uint64 rsz4_value = extract_rsz4_4_2_1_0(instruction); 10044 10045 const char *rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value, info), info); 10046 const char *re2 = GPR(decode_gpr_gpr2_reg2(rd2_value, info), info); 10047 /* !!!!!!!!!! - no conversion function */ 10048 const char *rsz4 = GPR(decode_gpr_gpr4_zero(rsz4_value, info), info); 10049 const char *rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value, info), info); 10050 10051 return img_format("MOVEP %s, %s, %s, %s", rd2, re2, rsz4, rtz4); 10052 /* hand edited */ 10053 } 10054 10055 10056 /* 10057 * 10058 * 10059 * 3 2 1 10060 * 10987654321098765432109876543210 10061 * 001000 x1110000101 10062 * rt ----- 10063 * rs ----- 10064 * rd ----- 10065 */ 10066 static char *MOVEP_REV_(uint64 instruction, Dis_info *info) 10067 { 10068 uint64 rt4_value = extract_rt4_9_7_6_5(instruction); 10069 uint64 rd2_value = extract_rd2_3_8(instruction); 10070 uint64 rs4_value = extract_rs4_4_2_1_0(instruction); 10071 10072 const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info); 10073 const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info); 10074 const char *rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value, info), info); 10075 const char *rs2 = GPR(decode_gpr_gpr2_reg2(rd2_value, info), info); 10076 /* !!!!!!!!!! - no conversion function */ 10077 10078 return img_format("MOVEP %s, %s, %s, %s", rs4, rt4, rd2, rs2); 10079 /* hand edited */ 10080 } 10081 10082 10083 /* 10084 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10085 * 10086 * 3 2 1 10087 * 10987654321098765432109876543210 10088 * 001000 00010001101 10089 * rt ----- 10090 * rs ----- 10091 * rd ----- 10092 */ 10093 static char *MOVE(uint64 instruction, Dis_info *info) 10094 { 10095 uint64 rt_value = extract_rt_9_8_7_6_5(instruction); 10096 uint64 rs_value = extract_rs_4_3_2_1_0(instruction); 10097 10098 const char *rt = GPR(rt_value, info); 10099 const char *rs = GPR(rs_value, info); 10100 10101 return img_format("MOVE %s, %s", rt, rs); 10102 } 10103 10104 10105 /* 10106 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10107 * 10108 * 3 2 1 10109 * 10987654321098765432109876543210 10110 * 001000 00010001101 10111 * rt ----- 10112 * rs ----- 10113 * rd ----- 10114 */ 10115 static char *MOVN(uint64 instruction, Dis_info *info) 10116 { 10117 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10118 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10119 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10120 10121 const char *rd = GPR(rd_value, info); 10122 const char *rs = GPR(rs_value, info); 10123 const char *rt = GPR(rt_value, info); 10124 10125 return img_format("MOVN %s, %s, %s", rd, rs, rt); 10126 } 10127 10128 10129 /* 10130 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10131 * 10132 * 3 2 1 10133 * 10987654321098765432109876543210 10134 * 001000 00010001101 10135 * rt ----- 10136 * rs ----- 10137 * rd ----- 10138 */ 10139 static char *MOVZ(uint64 instruction, Dis_info *info) 10140 { 10141 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10142 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10143 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10144 10145 const char *rd = GPR(rd_value, info); 10146 const char *rs = GPR(rs_value, info); 10147 const char *rt = GPR(rt_value, info); 10148 10149 return img_format("MOVZ %s, %s, %s", rd, rs, rt); 10150 } 10151 10152 10153 /* 10154 * [DSP] MSUB ac, rs, rt - Multiply word and subtract from accumulator 10155 * 10156 * 3 2 1 10157 * 10987654321098765432109876543210 10158 * 001000 10101010111111 10159 * rt ----- 10160 * rs ----- 10161 * ac -- 10162 */ 10163 static char *MSUB_DSP_(uint64 instruction, Dis_info *info) 10164 { 10165 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10166 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10167 uint64 ac_value = extract_ac_15_14(instruction); 10168 10169 const char *ac = AC(ac_value, info); 10170 const char *rs = GPR(rs_value, info); 10171 const char *rt = GPR(rt_value, info); 10172 10173 return img_format("MSUB %s, %s, %s", ac, rs, rt); 10174 } 10175 10176 10177 /* 10178 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10179 * 10180 * 3 2 1 10181 * 10987654321098765432109876543210 10182 * 001000 00010001101 10183 * rt ----- 10184 * rs ----- 10185 * rd ----- 10186 */ 10187 static char *MSUBF_D(uint64 instruction, Dis_info *info) 10188 { 10189 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 10190 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 10191 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 10192 10193 const char *fd = FPR(fd_value, info); 10194 const char *fs = FPR(fs_value, info); 10195 const char *ft = FPR(ft_value, info); 10196 10197 return img_format("MSUBF.D %s, %s, %s", fd, fs, ft); 10198 } 10199 10200 10201 /* 10202 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10203 * 10204 * 3 2 1 10205 * 10987654321098765432109876543210 10206 * 001000 00010001101 10207 * rt ----- 10208 * rs ----- 10209 * rd ----- 10210 */ 10211 static char *MSUBF_S(uint64 instruction, Dis_info *info) 10212 { 10213 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 10214 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 10215 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 10216 10217 const char *fd = FPR(fd_value, info); 10218 const char *fs = FPR(fs_value, info); 10219 const char *ft = FPR(ft_value, info); 10220 10221 return img_format("MSUBF.S %s, %s, %s", fd, fs, ft); 10222 } 10223 10224 10225 /* 10226 * [DSP] MSUBU ac, rs, rt - Multiply word and add to accumulator 10227 * 10228 * 3 2 1 10229 * 10987654321098765432109876543210 10230 * 001000 11101010111111 10231 * rt ----- 10232 * rs ----- 10233 * ac -- 10234 */ 10235 static char *MSUBU_DSP_(uint64 instruction, Dis_info *info) 10236 { 10237 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10238 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10239 uint64 ac_value = extract_ac_15_14(instruction); 10240 10241 const char *ac = AC(ac_value, info); 10242 const char *rs = GPR(rs_value, info); 10243 const char *rt = GPR(rt_value, info); 10244 10245 return img_format("MSUBU %s, %s, %s", ac, rs, rt); 10246 } 10247 10248 10249 /* 10250 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10251 * 10252 * 3 2 1 10253 * 10987654321098765432109876543210 10254 * 001000 00010001101 10255 * rt ----- 10256 * rs ----- 10257 * rd ----- 10258 */ 10259 static char *MTC0(uint64 instruction, Dis_info *info) 10260 { 10261 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10262 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 10263 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 10264 10265 const char *rt = GPR(rt_value, info); 10266 10267 return img_format("MTC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 10268 rt, c0s_value, sel_value); 10269 } 10270 10271 10272 /* 10273 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10274 * 10275 * 3 2 1 10276 * 10987654321098765432109876543210 10277 * 001000 00010001101 10278 * rt ----- 10279 * rs ----- 10280 * rd ----- 10281 */ 10282 static char *MTC1(uint64 instruction, Dis_info *info) 10283 { 10284 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10285 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 10286 10287 const char *rt = GPR(rt_value, info); 10288 const char *fs = FPR(fs_value, info); 10289 10290 return img_format("MTC1 %s, %s", rt, fs); 10291 } 10292 10293 10294 /* 10295 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10296 * 10297 * 3 2 1 10298 * 10987654321098765432109876543210 10299 * 001000 00010001101 10300 * rt ----- 10301 * rs ----- 10302 * rd ----- 10303 */ 10304 static char *MTC2(uint64 instruction, Dis_info *info) 10305 { 10306 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10307 uint64 cs_value = extract_cs_20_19_18_17_16(instruction); 10308 10309 const char *rt = GPR(rt_value, info); 10310 10311 return img_format("MTC2 %s, CP%" PRIu64, rt, cs_value); 10312 } 10313 10314 10315 /* 10316 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10317 * 10318 * 3 2 1 10319 * 10987654321098765432109876543210 10320 * 001000 00010001101 10321 * rt ----- 10322 * rs ----- 10323 * rd ----- 10324 */ 10325 static char *MTGC0(uint64 instruction, Dis_info *info) 10326 { 10327 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10328 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 10329 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 10330 10331 const char *rt = GPR(rt_value, info); 10332 10333 return img_format("MTGC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 10334 rt, c0s_value, sel_value); 10335 } 10336 10337 10338 /* 10339 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10340 * 10341 * 3 2 1 10342 * 10987654321098765432109876543210 10343 * 001000 00010001101 10344 * rt ----- 10345 * rs ----- 10346 * rd ----- 10347 */ 10348 static char *MTHC0(uint64 instruction, Dis_info *info) 10349 { 10350 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10351 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 10352 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 10353 10354 const char *rt = GPR(rt_value, info); 10355 10356 return img_format("MTHC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 10357 rt, c0s_value, sel_value); 10358 } 10359 10360 10361 /* 10362 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10363 * 10364 * 3 2 1 10365 * 10987654321098765432109876543210 10366 * 001000 00010001101 10367 * rt ----- 10368 * rs ----- 10369 * rd ----- 10370 */ 10371 static char *MTHC1(uint64 instruction, Dis_info *info) 10372 { 10373 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10374 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 10375 10376 const char *rt = GPR(rt_value, info); 10377 const char *fs = FPR(fs_value, info); 10378 10379 return img_format("MTHC1 %s, %s", rt, fs); 10380 } 10381 10382 10383 /* 10384 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10385 * 10386 * 3 2 1 10387 * 10987654321098765432109876543210 10388 * 001000 00010001101 10389 * rt ----- 10390 * rs ----- 10391 * rd ----- 10392 */ 10393 static char *MTHC2(uint64 instruction, Dis_info *info) 10394 { 10395 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10396 uint64 cs_value = extract_cs_20_19_18_17_16(instruction); 10397 10398 const char *rt = GPR(rt_value, info); 10399 10400 return img_format("MTHC2 %s, CP%" PRIu64, rt, cs_value); 10401 } 10402 10403 10404 /* 10405 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10406 * 10407 * 3 2 1 10408 * 10987654321098765432109876543210 10409 * 001000 00010001101 10410 * rt ----- 10411 * rs ----- 10412 * rd ----- 10413 */ 10414 static char *MTHGC0(uint64 instruction, Dis_info *info) 10415 { 10416 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10417 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 10418 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 10419 10420 const char *rt = GPR(rt_value, info); 10421 10422 return img_format("MTHGC0 %s, CP%" PRIu64 ", 0x%" PRIx64, 10423 rt, c0s_value, sel_value); 10424 } 10425 10426 10427 /* 10428 * [DSP] MTHI rs, ac - Move to HI register 10429 * 10430 * 3 2 1 10431 * 10987654321098765432109876543210 10432 * 001000xxxxx 10000001111111 10433 * rs ----- 10434 * ac -- 10435 */ 10436 static char *MTHI_DSP_(uint64 instruction, Dis_info *info) 10437 { 10438 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10439 uint64 ac_value = extract_ac_15_14(instruction); 10440 10441 const char *rs = GPR(rs_value, info); 10442 const char *ac = AC(ac_value, info); 10443 10444 return img_format("MTHI %s, %s", rs, ac); 10445 } 10446 10447 10448 /* 10449 * [DSP] MTHLIP rs, ac - Copy LO to HI and a GPR to LO and increment pos by 32 10450 * 10451 * 3 2 1 10452 * 10987654321098765432109876543210 10453 * 001000xxxxx 00001001111111 10454 * rs ----- 10455 * ac -- 10456 */ 10457 static char *MTHLIP(uint64 instruction, Dis_info *info) 10458 { 10459 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10460 uint64 ac_value = extract_ac_15_14(instruction); 10461 10462 const char *rs = GPR(rs_value, info); 10463 const char *ac = AC(ac_value, info); 10464 10465 return img_format("MTHLIP %s, %s", rs, ac); 10466 } 10467 10468 10469 /* 10470 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10471 * 10472 * 3 2 1 10473 * 10987654321098765432109876543210 10474 * 001000 00010001101 10475 * rt ----- 10476 * rs ----- 10477 * rd ----- 10478 */ 10479 static char *MTHTR(uint64 instruction, Dis_info *info) 10480 { 10481 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10482 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 10483 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 10484 uint64 u_value = extract_u_10(instruction); 10485 10486 const char *rt = GPR(rt_value, info); 10487 10488 return img_format("MTHTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64, 10489 rt, c0s_value, u_value, sel_value); 10490 } 10491 10492 10493 /* 10494 * [DSP] MTLO rs, ac - Move to LO register 10495 * 10496 * 3 2 1 10497 * 10987654321098765432109876543210 10498 * 001000xxxxx 11000001111111 10499 * rs ----- 10500 * ac -- 10501 */ 10502 static char *MTLO_DSP_(uint64 instruction, Dis_info *info) 10503 { 10504 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10505 uint64 ac_value = extract_ac_15_14(instruction); 10506 10507 const char *rs = GPR(rs_value, info); 10508 const char *ac = AC(ac_value, info); 10509 10510 return img_format("MTLO %s, %s", rs, ac); 10511 } 10512 10513 10514 /* 10515 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10516 * 10517 * 3 2 1 10518 * 10987654321098765432109876543210 10519 * 001000 00010001101 10520 * rt ----- 10521 * rs ----- 10522 * rd ----- 10523 */ 10524 static char *MTTR(uint64 instruction, Dis_info *info) 10525 { 10526 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10527 uint64 c0s_value = extract_c0s_20_19_18_17_16(instruction); 10528 uint64 sel_value = extract_sel_15_14_13_12_11(instruction); 10529 uint64 u_value = extract_u_10(instruction); 10530 10531 const char *rt = GPR(rt_value, info); 10532 10533 return img_format("MTTR %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64, 10534 rt, c0s_value, u_value, sel_value); 10535 } 10536 10537 10538 /* 10539 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10540 * 10541 * 3 2 1 10542 * 10987654321098765432109876543210 10543 * 001000 00010001101 10544 * rt ----- 10545 * rs ----- 10546 * rd ----- 10547 */ 10548 static char *MUH(uint64 instruction, Dis_info *info) 10549 { 10550 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10551 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10552 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10553 10554 const char *rd = GPR(rd_value, info); 10555 const char *rs = GPR(rs_value, info); 10556 const char *rt = GPR(rt_value, info); 10557 10558 return img_format("MUH %s, %s, %s", rd, rs, rt); 10559 } 10560 10561 10562 /* 10563 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10564 * 10565 * 3 2 1 10566 * 10987654321098765432109876543210 10567 * 001000 00010001101 10568 * rt ----- 10569 * rs ----- 10570 * rd ----- 10571 */ 10572 static char *MUHU(uint64 instruction, Dis_info *info) 10573 { 10574 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10575 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10576 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10577 10578 const char *rd = GPR(rd_value, info); 10579 const char *rs = GPR(rs_value, info); 10580 const char *rt = GPR(rt_value, info); 10581 10582 return img_format("MUHU %s, %s, %s", rd, rs, rt); 10583 } 10584 10585 10586 /* 10587 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10588 * 10589 * 3 2 1 10590 * 10987654321098765432109876543210 10591 * 001000 00010001101 10592 * rt ----- 10593 * rs ----- 10594 * rd ----- 10595 */ 10596 static char *MUL_32_(uint64 instruction, Dis_info *info) 10597 { 10598 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10599 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10600 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10601 10602 const char *rd = GPR(rd_value, info); 10603 const char *rs = GPR(rs_value, info); 10604 const char *rt = GPR(rt_value, info); 10605 10606 return img_format("MUL %s, %s, %s", rd, rs, rt); 10607 } 10608 10609 10610 /* 10611 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10612 * 10613 * 3 2 1 10614 * 10987654321098765432109876543210 10615 * 001000 00010001101 10616 * rt ----- 10617 * rs ----- 10618 * rd ----- 10619 */ 10620 static char *MUL_4X4_(uint64 instruction, Dis_info *info) 10621 { 10622 uint64 rt4_value = extract_rt4_9_7_6_5(instruction); 10623 uint64 rs4_value = extract_rs4_4_2_1_0(instruction); 10624 10625 const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info); 10626 const char *rt4 = GPR(decode_gpr_gpr4(rt4_value, info), info); 10627 10628 return img_format("MUL %s, %s", rs4, rt4); 10629 } 10630 10631 10632 /* 10633 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10634 * 10635 * 3 2 1 10636 * 10987654321098765432109876543210 10637 * 001000 00010001101 10638 * rt ----- 10639 * rs ----- 10640 * rd ----- 10641 */ 10642 static char *MUL_D(uint64 instruction, Dis_info *info) 10643 { 10644 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 10645 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 10646 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 10647 10648 const char *fd = FPR(fd_value, info); 10649 const char *fs = FPR(fs_value, info); 10650 const char *ft = FPR(ft_value, info); 10651 10652 return img_format("MUL.D %s, %s, %s", fd, fs, ft); 10653 } 10654 10655 10656 /* 10657 * [DSP] MUL.PH rd, rs, rt - Multiply vector integer half words to same size 10658 * products 10659 * 10660 * 3 2 1 10661 * 10987654321098765432109876543210 10662 * 001000 00000101101 10663 * rt ----- 10664 * rs ----- 10665 * rd ----- 10666 */ 10667 static char *MUL_PH(uint64 instruction, Dis_info *info) 10668 { 10669 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10670 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10671 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10672 10673 const char *rd = GPR(rd_value, info); 10674 const char *rs = GPR(rs_value, info); 10675 const char *rt = GPR(rt_value, info); 10676 10677 return img_format("MUL.PH %s, %s, %s", rd, rs, rt); 10678 } 10679 10680 10681 /* 10682 * [DSP] MUL_S.PH rd, rs, rt - Multiply vector integer half words to same size 10683 * products (saturated) 10684 * 10685 * 3 2 1 10686 * 10987654321098765432109876543210 10687 * 001000 10000101101 10688 * rt ----- 10689 * rs ----- 10690 * rd ----- 10691 */ 10692 static char *MUL_S_PH(uint64 instruction, Dis_info *info) 10693 { 10694 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10695 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10696 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10697 10698 const char *rd = GPR(rd_value, info); 10699 const char *rs = GPR(rs_value, info); 10700 const char *rt = GPR(rt_value, info); 10701 10702 return img_format("MUL_S.PH %s, %s, %s", rd, rs, rt); 10703 } 10704 10705 10706 /* 10707 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 10708 * 10709 * 3 2 1 10710 * 10987654321098765432109876543210 10711 * 001000 00010001101 10712 * rt ----- 10713 * rs ----- 10714 * rd ----- 10715 */ 10716 static char *MUL_S(uint64 instruction, Dis_info *info) 10717 { 10718 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 10719 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 10720 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 10721 10722 const char *fd = FPR(fd_value, info); 10723 const char *fs = FPR(fs_value, info); 10724 const char *ft = FPR(ft_value, info); 10725 10726 return img_format("MUL.S %s, %s, %s", fd, fs, ft); 10727 } 10728 10729 10730 /* 10731 * [DSP] MULEQ_S.W.PHL rd, rs, rt - Multiply vector fractional left halfwords 10732 * to expanded width products 10733 * 10734 * 3 2 1 10735 * 10987654321098765432109876543210 10736 * 001000 x0000100101 10737 * rt ----- 10738 * rs ----- 10739 * rd ----- 10740 */ 10741 static char *MULEQ_S_W_PHL(uint64 instruction, Dis_info *info) 10742 { 10743 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10744 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10745 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10746 10747 const char *rd = GPR(rd_value, info); 10748 const char *rs = GPR(rs_value, info); 10749 const char *rt = GPR(rt_value, info); 10750 10751 return img_format("MULEQ_S.W.PHL %s, %s, %s", rd, rs, rt); 10752 } 10753 10754 10755 /* 10756 * [DSP] MULEQ_S.W.PHR rd, rs, rt - Multiply vector fractional right halfwords 10757 * to expanded width products 10758 * 10759 * 3 2 1 10760 * 10987654321098765432109876543210 10761 * 001000 x0001100101 10762 * rt ----- 10763 * rs ----- 10764 * rd ----- 10765 */ 10766 static char *MULEQ_S_W_PHR(uint64 instruction, Dis_info *info) 10767 { 10768 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10769 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10770 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10771 10772 const char *rd = GPR(rd_value, info); 10773 const char *rs = GPR(rs_value, info); 10774 const char *rt = GPR(rt_value, info); 10775 10776 return img_format("MULEQ_S.W.PHR %s, %s, %s", rd, rs, rt); 10777 } 10778 10779 10780 /* 10781 * [DSP] MULEU_S.PH.QBL rd, rs, rt - Multiply vector fractional left bytes 10782 * by halfwords to halfword products 10783 * 10784 * 3 2 1 10785 * 10987654321098765432109876543210 10786 * 001000 x0010010101 10787 * rt ----- 10788 * rs ----- 10789 * rd ----- 10790 */ 10791 static char *MULEU_S_PH_QBL(uint64 instruction, Dis_info *info) 10792 { 10793 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10794 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10795 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10796 10797 const char *rd = GPR(rd_value, info); 10798 const char *rs = GPR(rs_value, info); 10799 const char *rt = GPR(rt_value, info); 10800 10801 return img_format("MULEU_S.PH.QBL %s, %s, %s", rd, rs, rt); 10802 } 10803 10804 10805 /* 10806 * [DSP] MULEU_S.PH.QBR rd, rs, rt - Multiply vector fractional right bytes 10807 * by halfwords to halfword products 10808 * 10809 * 3 2 1 10810 * 10987654321098765432109876543210 10811 * 001000 x0011010101 10812 * rt ----- 10813 * rs ----- 10814 * rd ----- 10815 */ 10816 static char *MULEU_S_PH_QBR(uint64 instruction, Dis_info *info) 10817 { 10818 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10819 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10820 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10821 10822 const char *rd = GPR(rd_value, info); 10823 const char *rs = GPR(rs_value, info); 10824 const char *rt = GPR(rt_value, info); 10825 10826 return img_format("MULEU_S.PH.QBR %s, %s, %s", rd, rs, rt); 10827 } 10828 10829 10830 /* 10831 * [DSP] MULQ_RS.PH rd, rs, rt - Multiply vector fractional halfwords 10832 * to fractional halfword products 10833 * 10834 * 3 2 1 10835 * 10987654321098765432109876543210 10836 * 001000 x0100010101 10837 * rt ----- 10838 * rs ----- 10839 * rd ----- 10840 */ 10841 static char *MULQ_RS_PH(uint64 instruction, Dis_info *info) 10842 { 10843 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10844 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10845 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10846 10847 const char *rd = GPR(rd_value, info); 10848 const char *rs = GPR(rs_value, info); 10849 const char *rt = GPR(rt_value, info); 10850 10851 return img_format("MULQ_RS.PH %s, %s, %s", rd, rs, rt); 10852 } 10853 10854 10855 /* 10856 * [DSP] MULQ_RS.W rd, rs, rt - Multiply fractional words to same size 10857 * product with saturation and rounding 10858 * 10859 * 3 2 1 10860 * 10987654321098765432109876543210 10861 * 001000 x0110010101 10862 * rt ----- 10863 * rs ----- 10864 * rd ----- 10865 */ 10866 static char *MULQ_RS_W(uint64 instruction, Dis_info *info) 10867 { 10868 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10869 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10870 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10871 10872 const char *rd = GPR(rd_value, info); 10873 const char *rs = GPR(rs_value, info); 10874 const char *rt = GPR(rt_value, info); 10875 10876 return img_format("MULQ_RS.W %s, %s, %s", rd, rs, rt); 10877 } 10878 10879 10880 /* 10881 * [DSP] MULQ_S.PH rd, rs, rt - Multiply fractional halfwords to same size 10882 * products 10883 * 10884 * 3 2 1 10885 * 10987654321098765432109876543210 10886 * 001000 x0101010101 10887 * rt ----- 10888 * rs ----- 10889 * rd ----- 10890 */ 10891 static char *MULQ_S_PH(uint64 instruction, Dis_info *info) 10892 { 10893 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10894 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10895 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10896 10897 const char *rd = GPR(rd_value, info); 10898 const char *rs = GPR(rs_value, info); 10899 const char *rt = GPR(rt_value, info); 10900 10901 return img_format("MULQ_S.PH %s, %s, %s", rd, rs, rt); 10902 } 10903 10904 10905 /* 10906 * [DSP] MULQ_S.W rd, rs, rt - Multiply fractional words to same size product 10907 * with saturation 10908 * 10909 * 3 2 1 10910 * 10987654321098765432109876543210 10911 * 001000 x0111010101 10912 * rt ----- 10913 * rs ----- 10914 * rd ----- 10915 */ 10916 static char *MULQ_S_W(uint64 instruction, Dis_info *info) 10917 { 10918 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10919 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10920 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 10921 10922 const char *rd = GPR(rd_value, info); 10923 const char *rs = GPR(rs_value, info); 10924 const char *rt = GPR(rt_value, info); 10925 10926 return img_format("MULQ_S.W %s, %s, %s", rd, rs, rt); 10927 } 10928 10929 10930 /* 10931 * [DSP] MULSA.W.PH ac, rs, rt - Multiply and subtract vector integer halfword 10932 * elements and accumulate 10933 * 10934 * 3 2 1 10935 * 10987654321098765432109876543210 10936 * 001000 10110010111111 10937 * rt ----- 10938 * rs ----- 10939 * ac -- 10940 */ 10941 static char *MULSA_W_PH(uint64 instruction, Dis_info *info) 10942 { 10943 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10944 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10945 uint64 ac_value = extract_ac_15_14(instruction); 10946 10947 const char *ac = AC(ac_value, info); 10948 const char *rs = GPR(rs_value, info); 10949 const char *rt = GPR(rt_value, info); 10950 10951 return img_format("MULSA.W.PH %s, %s, %s", ac, rs, rt); 10952 } 10953 10954 10955 /* 10956 * [DSP] MULSAQ_S.W.PH ac, rs, rt - Multiply and subtract vector fractional 10957 * halfwords and accumulate 10958 * 10959 * 3 2 1 10960 * 10987654321098765432109876543210 10961 * 001000 11110010111111 10962 * rt ----- 10963 * rs ----- 10964 * ac -- 10965 */ 10966 static char *MULSAQ_S_W_PH(uint64 instruction, Dis_info *info) 10967 { 10968 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10969 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10970 uint64 ac_value = extract_ac_15_14(instruction); 10971 10972 const char *ac = AC(ac_value, info); 10973 const char *rs = GPR(rs_value, info); 10974 const char *rt = GPR(rt_value, info); 10975 10976 return img_format("MULSAQ_S.W.PH %s, %s, %s", ac, rs, rt); 10977 } 10978 10979 10980 /* 10981 * [DSP] MULT ac, rs, rt - Multiply word 10982 * 10983 * 3 2 1 10984 * 10987654321098765432109876543210 10985 * 001000 00110010111111 10986 * rt ----- 10987 * rs ----- 10988 * ac -- 10989 */ 10990 static char *MULT_DSP_(uint64 instruction, Dis_info *info) 10991 { 10992 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 10993 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 10994 uint64 ac_value = extract_ac_15_14(instruction); 10995 10996 const char *ac = AC(ac_value, info); 10997 const char *rs = GPR(rs_value, info); 10998 const char *rt = GPR(rt_value, info); 10999 11000 return img_format("MULT %s, %s, %s", ac, rs, rt); 11001 } 11002 11003 11004 /* 11005 * [DSP] MULTU ac, rs, rt - Multiply unsigned word 11006 * 11007 * 3 2 1 11008 * 10987654321098765432109876543210 11009 * 001000 01110010111111 11010 * rt ----- 11011 * rs ----- 11012 * ac -- 11013 */ 11014 static char *MULTU_DSP_(uint64 instruction, Dis_info *info) 11015 { 11016 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11017 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11018 uint64 ac_value = extract_ac_15_14(instruction); 11019 11020 const char *ac = AC(ac_value, info); 11021 const char *rs = GPR(rs_value, info); 11022 const char *rt = GPR(rt_value, info); 11023 11024 return img_format("MULTU %s, %s, %s", ac, rs, rt); 11025 } 11026 11027 11028 /* 11029 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 11030 * 11031 * 3 2 1 11032 * 10987654321098765432109876543210 11033 * 001000 00010001101 11034 * rt ----- 11035 * rs ----- 11036 * rd ----- 11037 */ 11038 static char *MULU(uint64 instruction, Dis_info *info) 11039 { 11040 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11041 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11042 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 11043 11044 const char *rd = GPR(rd_value, info); 11045 const char *rs = GPR(rs_value, info); 11046 const char *rt = GPR(rt_value, info); 11047 11048 return img_format("MULU %s, %s, %s", rd, rs, rt); 11049 } 11050 11051 11052 /* 11053 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 11054 * 11055 * 3 2 1 11056 * 10987654321098765432109876543210 11057 * 001000 00010001101 11058 * rt ----- 11059 * rs ----- 11060 * rd ----- 11061 */ 11062 static char *NEG_D(uint64 instruction, Dis_info *info) 11063 { 11064 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 11065 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 11066 11067 const char *ft = FPR(ft_value, info); 11068 const char *fs = FPR(fs_value, info); 11069 11070 return img_format("NEG.D %s, %s", ft, fs); 11071 } 11072 11073 11074 /* 11075 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 11076 * 11077 * 3 2 1 11078 * 10987654321098765432109876543210 11079 * 001000 00010001101 11080 * rt ----- 11081 * rs ----- 11082 * rd ----- 11083 */ 11084 static char *NEG_S(uint64 instruction, Dis_info *info) 11085 { 11086 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 11087 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 11088 11089 const char *ft = FPR(ft_value, info); 11090 const char *fs = FPR(fs_value, info); 11091 11092 return img_format("NEG.S %s, %s", ft, fs); 11093 } 11094 11095 11096 /* 11097 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 11098 * 11099 * 3 2 1 11100 * 10987654321098765432109876543210 11101 * 001000 00010001101 11102 * rt ----- 11103 * rs ----- 11104 * rd ----- 11105 */ 11106 static char *NOP_16_(uint64 instruction, Dis_info *info) 11107 { 11108 (void)instruction; 11109 11110 return g_strdup("NOP "); 11111 } 11112 11113 11114 /* 11115 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 11116 * 11117 * 3 2 1 11118 * 10987654321098765432109876543210 11119 * 001000 00010001101 11120 * rt ----- 11121 * rs ----- 11122 * rd ----- 11123 */ 11124 static char *NOP_32_(uint64 instruction, Dis_info *info) 11125 { 11126 (void)instruction; 11127 11128 return g_strdup("NOP "); 11129 } 11130 11131 11132 /* 11133 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 11134 * 11135 * 3 2 1 11136 * 10987654321098765432109876543210 11137 * 001000 00010001101 11138 * rt ----- 11139 * rs ----- 11140 * rd ----- 11141 */ 11142 static char *NOR(uint64 instruction, Dis_info *info) 11143 { 11144 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11145 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11146 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 11147 11148 const char *rd = GPR(rd_value, info); 11149 const char *rs = GPR(rs_value, info); 11150 const char *rt = GPR(rt_value, info); 11151 11152 return img_format("NOR %s, %s, %s", rd, rs, rt); 11153 } 11154 11155 11156 /* 11157 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 11158 * 11159 * 3 2 1 11160 * 10987654321098765432109876543210 11161 * 001000 00010001101 11162 * rt ----- 11163 * rs ----- 11164 * rd ----- 11165 */ 11166 static char *NOT_16_(uint64 instruction, Dis_info *info) 11167 { 11168 uint64 rt3_value = extract_rt3_9_8_7(instruction); 11169 uint64 rs3_value = extract_rs3_6_5_4(instruction); 11170 11171 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 11172 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 11173 11174 return img_format("NOT %s, %s", rt3, rs3); 11175 } 11176 11177 11178 /* 11179 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 11180 * 11181 * 3 2 1 11182 * 10987654321098765432109876543210 11183 * 001000 00010001101 11184 * rt ----- 11185 * rs ----- 11186 * rd ----- 11187 */ 11188 static char *OR_16_(uint64 instruction, Dis_info *info) 11189 { 11190 uint64 rt3_value = extract_rt3_9_8_7(instruction); 11191 uint64 rs3_value = extract_rs3_6_5_4(instruction); 11192 11193 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 11194 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 11195 11196 return img_format("OR %s, %s", rs3, rt3); 11197 } 11198 11199 11200 /* 11201 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 11202 * 11203 * 3 2 1 11204 * 10987654321098765432109876543210 11205 * 001000 00010001101 11206 * rt ----- 11207 * rs ----- 11208 * rd ----- 11209 */ 11210 static char *OR_32_(uint64 instruction, Dis_info *info) 11211 { 11212 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11213 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11214 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 11215 11216 const char *rd = GPR(rd_value, info); 11217 const char *rs = GPR(rs_value, info); 11218 const char *rt = GPR(rt_value, info); 11219 11220 return img_format("OR %s, %s, %s", rd, rs, rt); 11221 } 11222 11223 11224 /* 11225 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 11226 * 11227 * 3 2 1 11228 * 10987654321098765432109876543210 11229 * 001000 00010001101 11230 * rt ----- 11231 * rs ----- 11232 * rd ----- 11233 */ 11234 static char *ORI(uint64 instruction, Dis_info *info) 11235 { 11236 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11237 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11238 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 11239 11240 const char *rt = GPR(rt_value, info); 11241 const char *rs = GPR(rs_value, info); 11242 11243 return img_format("ORI %s, %s, 0x%" PRIx64, rt, rs, u_value); 11244 } 11245 11246 11247 /* 11248 * [DSP] PACKRL.PH rd, rs, rt - Pack a word using the right halfword from one 11249 * source register and left halfword from another source register 11250 * 11251 * 3 2 1 11252 * 10987654321098765432109876543210 11253 * 001000 00010001101 11254 * rt ----- 11255 * rs ----- 11256 * rd ----- 11257 */ 11258 static char *PACKRL_PH(uint64 instruction, Dis_info *info) 11259 { 11260 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11261 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11262 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 11263 11264 const char *rd = GPR(rd_value, info); 11265 const char *rs = GPR(rs_value, info); 11266 const char *rt = GPR(rt_value, info); 11267 11268 return img_format("PACKRL.PH %s, %s, %s", rd, rs, rt); 11269 } 11270 11271 11272 /* 11273 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 11274 * 11275 * 3 2 1 11276 * 10987654321098765432109876543210 11277 * 001000 00010001101 11278 * rt ----- 11279 * rs ----- 11280 * rd ----- 11281 */ 11282 static char *PAUSE(uint64 instruction, Dis_info *info) 11283 { 11284 (void)instruction; 11285 11286 return g_strdup("PAUSE "); 11287 } 11288 11289 11290 /* 11291 * [DSP] PICK.PH rd, rs, rt - Pick a vector of halfwords based on condition 11292 * code bits 11293 * 11294 * 3 2 1 11295 * 10987654321098765432109876543210 11296 * 001000 00010001101 11297 * rt ----- 11298 * rs ----- 11299 * rd ----- 11300 */ 11301 static char *PICK_PH(uint64 instruction, Dis_info *info) 11302 { 11303 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11304 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11305 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 11306 11307 const char *rd = GPR(rd_value, info); 11308 const char *rs = GPR(rs_value, info); 11309 const char *rt = GPR(rt_value, info); 11310 11311 return img_format("PICK.PH %s, %s, %s", rd, rs, rt); 11312 } 11313 11314 11315 /* 11316 * [DSP] PICK.QB rd, rs, rt - Pick a vector of byte values based on condition 11317 * code bits 11318 * 11319 * 3 2 1 11320 * 10987654321098765432109876543210 11321 * 001000 00010001101 11322 * rt ----- 11323 * rs ----- 11324 * rd ----- 11325 */ 11326 static char *PICK_QB(uint64 instruction, Dis_info *info) 11327 { 11328 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11329 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11330 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 11331 11332 const char *rd = GPR(rd_value, info); 11333 const char *rs = GPR(rs_value, info); 11334 const char *rt = GPR(rt_value, info); 11335 11336 return img_format("PICK.QB %s, %s, %s", rd, rs, rt); 11337 } 11338 11339 11340 /* 11341 * [DSP] PRECEQ.W.PHL rt, rs - Expand the precision of the left-most element 11342 * of a paired halfword 11343 * 11344 * 3 2 1 11345 * 10987654321098765432109876543210 11346 * 001000 00010001101 11347 * rt ----- 11348 * rs ----- 11349 * rd ----- 11350 */ 11351 static char *PRECEQ_W_PHL(uint64 instruction, Dis_info *info) 11352 { 11353 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11354 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11355 11356 const char *rt = GPR(rt_value, info); 11357 const char *rs = GPR(rs_value, info); 11358 11359 return img_format("PRECEQ.W.PHL %s, %s", rt, rs); 11360 } 11361 11362 11363 /* 11364 * [DSP] PRECEQ.W.PHR rt, rs - Expand the precision of the right-most element 11365 * of a paired halfword 11366 * 11367 * 3 2 1 11368 * 10987654321098765432109876543210 11369 * 001000 00010001101 11370 * rt ----- 11371 * rs ----- 11372 * rd ----- 11373 */ 11374 static char *PRECEQ_W_PHR(uint64 instruction, Dis_info *info) 11375 { 11376 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11377 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11378 11379 const char *rt = GPR(rt_value, info); 11380 const char *rs = GPR(rs_value, info); 11381 11382 return img_format("PRECEQ.W.PHR %s, %s", rt, rs); 11383 } 11384 11385 11386 /* 11387 * [DSP] PRECEQU.PH.QBLA rt, rs - Expand the precision of the two 11388 * left-alternate elements of a quad byte vector 11389 * 11390 * 3 2 1 11391 * 10987654321098765432109876543210 11392 * 001000 00010001101 11393 * rt ----- 11394 * rs ----- 11395 * rd ----- 11396 */ 11397 static char *PRECEQU_PH_QBLA(uint64 instruction, Dis_info *info) 11398 { 11399 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11400 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11401 11402 const char *rt = GPR(rt_value, info); 11403 const char *rs = GPR(rs_value, info); 11404 11405 return img_format("PRECEQU.PH.QBLA %s, %s", rt, rs); 11406 } 11407 11408 11409 /* 11410 * [DSP] PRECEQU.PH.QBL rt, rs - Expand the precision of the two left-most 11411 * elements of a quad byte vector 11412 * 11413 * 3 2 1 11414 * 10987654321098765432109876543210 11415 * 001000 00010001101 11416 * rt ----- 11417 * rs ----- 11418 * rd ----- 11419 */ 11420 static char *PRECEQU_PH_QBL(uint64 instruction, Dis_info *info) 11421 { 11422 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11423 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11424 11425 const char *rt = GPR(rt_value, info); 11426 const char *rs = GPR(rs_value, info); 11427 11428 return img_format("PRECEQU.PH.QBL %s, %s", rt, rs); 11429 } 11430 11431 11432 /* 11433 * [DSP] PRECEQU.PH.QBRA rt, rs - Expand the precision of the two 11434 * right-alternate elements of a quad byte vector 11435 * 11436 * 3 2 1 11437 * 10987654321098765432109876543210 11438 * 001000 00010001101 11439 * rt ----- 11440 * rs ----- 11441 * rd ----- 11442 */ 11443 static char *PRECEQU_PH_QBRA(uint64 instruction, Dis_info *info) 11444 { 11445 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11446 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11447 11448 const char *rt = GPR(rt_value, info); 11449 const char *rs = GPR(rs_value, info); 11450 11451 return img_format("PRECEQU.PH.QBRA %s, %s", rt, rs); 11452 } 11453 11454 11455 /* 11456 * [DSP] PRECEQU.PH.QBR rt, rs - Expand the precision of the two right-most 11457 * elements of a quad byte vector 11458 * 11459 * 3 2 1 11460 * 10987654321098765432109876543210 11461 * 001000 00010001101 11462 * rt ----- 11463 * rs ----- 11464 * rd ----- 11465 */ 11466 static char *PRECEQU_PH_QBR(uint64 instruction, Dis_info *info) 11467 { 11468 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11469 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11470 11471 const char *rt = GPR(rt_value, info); 11472 const char *rs = GPR(rs_value, info); 11473 11474 return img_format("PRECEQU.PH.QBR %s, %s", rt, rs); 11475 } 11476 11477 11478 /* 11479 * [DSP] PRECEU.PH.QBLA rt, rs - Expand the precision of the two 11480 * left-alternate elements of a quad byte vector to four unsigned 11481 * halfwords 11482 * 11483 * 3 2 1 11484 * 10987654321098765432109876543210 11485 * 001000 00010001101 11486 * rt ----- 11487 * rs ----- 11488 * rd ----- 11489 */ 11490 static char *PRECEU_PH_QBLA(uint64 instruction, Dis_info *info) 11491 { 11492 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11493 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11494 11495 const char *rt = GPR(rt_value, info); 11496 const char *rs = GPR(rs_value, info); 11497 11498 return img_format("PRECEU.PH.QBLA %s, %s", rt, rs); 11499 } 11500 11501 11502 /* 11503 * [DSP] PRECEU.PH.QBL rt, rs - Expand the precision of the two left-most 11504 * elements of a quad byte vector to form unsigned halfwords 11505 * 11506 * 3 2 1 11507 * 10987654321098765432109876543210 11508 * 001000 00010001101 11509 * rt ----- 11510 * rs ----- 11511 * rd ----- 11512 */ 11513 static char *PRECEU_PH_QBL(uint64 instruction, Dis_info *info) 11514 { 11515 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11516 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11517 11518 const char *rt = GPR(rt_value, info); 11519 const char *rs = GPR(rs_value, info); 11520 11521 return img_format("PRECEU.PH.QBL %s, %s", rt, rs); 11522 } 11523 11524 11525 /* 11526 * [DSP] PRECEU.PH.QBRA rt, rs - Expand the precision of the two 11527 * right-alternate elements of a quad byte vector to form four 11528 * unsigned halfwords 11529 * 11530 * 3 2 1 11531 * 10987654321098765432109876543210 11532 * 001000 00010001101 11533 * rt ----- 11534 * rs ----- 11535 * rd ----- 11536 */ 11537 static char *PRECEU_PH_QBRA(uint64 instruction, Dis_info *info) 11538 { 11539 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11540 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11541 11542 const char *rt = GPR(rt_value, info); 11543 const char *rs = GPR(rs_value, info); 11544 11545 return img_format("PRECEU.PH.QBRA %s, %s", rt, rs); 11546 } 11547 11548 11549 /* 11550 * [DSP] PRECEU.PH.QBR rt, rs - Expand the precision of the two right-most 11551 * elements of a quad byte vector to form unsigned halfwords 11552 * 11553 * 3 2 1 11554 * 10987654321098765432109876543210 11555 * 001000 00010001101 11556 * rt ----- 11557 * rs ----- 11558 * rd ----- 11559 */ 11560 static char *PRECEU_PH_QBR(uint64 instruction, Dis_info *info) 11561 { 11562 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11563 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11564 11565 const char *rt = GPR(rt_value, info); 11566 const char *rs = GPR(rs_value, info); 11567 11568 return img_format("PRECEU.PH.QBR %s, %s", rt, rs); 11569 } 11570 11571 11572 /* 11573 * [DSP] PRECR.QB.PH rd, rs, rt - Reduce the precision of four integer 11574 * halfwords to four bytes 11575 * 11576 * 3 2 1 11577 * 10987654321098765432109876543210 11578 * 001000 x0001101101 11579 * rt ----- 11580 * rs ----- 11581 * rd ----- 11582 */ 11583 static char *PRECR_QB_PH(uint64 instruction, Dis_info *info) 11584 { 11585 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11586 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11587 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 11588 11589 const char *rd = GPR(rd_value, info); 11590 const char *rs = GPR(rs_value, info); 11591 const char *rt = GPR(rt_value, info); 11592 11593 return img_format("PRECR.QB.PH %s, %s, %s", rd, rs, rt); 11594 } 11595 11596 11597 /* 11598 * [DSP] PRECR_SRA.PH.W rt, rs, sa - Reduce the precision of two integer 11599 * words to halfwords after a right shift 11600 * 11601 * 3 2 1 11602 * 10987654321098765432109876543210 11603 * 001000 x1110000101 11604 * rt ----- 11605 * rs ----- 11606 * rd ----- 11607 */ 11608 static char *PRECR_SRA_PH_W(uint64 instruction, Dis_info *info) 11609 { 11610 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11611 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11612 uint64 sa_value = extract_sa_15_14_13_12_11(instruction); 11613 11614 const char *rt = GPR(rt_value, info); 11615 const char *rs = GPR(rs_value, info); 11616 11617 return img_format("PRECR_SRA.PH.W %s, %s, 0x%" PRIx64, rt, rs, sa_value); 11618 } 11619 11620 11621 /* 11622 * [DSP] PRECR_SRA_R.PH.W rt, rs, sa - Reduce the precision of two integer 11623 * words to halfwords after a right shift with rounding 11624 * 11625 * 3 2 1 11626 * 10987654321098765432109876543210 11627 * 001000 x1110000101 11628 * rt ----- 11629 * rs ----- 11630 * rd ----- 11631 */ 11632 static char *PRECR_SRA_R_PH_W(uint64 instruction, Dis_info *info) 11633 { 11634 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11635 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11636 uint64 sa_value = extract_sa_15_14_13_12_11(instruction); 11637 11638 const char *rt = GPR(rt_value, info); 11639 const char *rs = GPR(rs_value, info); 11640 11641 return img_format("PRECR_SRA_R.PH.W %s, %s, 0x%" PRIx64, rt, rs, sa_value); 11642 } 11643 11644 11645 /* 11646 * [DSP] PRECRQ.PH.W rd, rs, rt - Reduce the precision of fractional 11647 * words to fractional halfwords 11648 * 11649 * 3 2 1 11650 * 10987654321098765432109876543210 11651 * 001000 x1110000101 11652 * rt ----- 11653 * rs ----- 11654 * rd ----- 11655 */ 11656 static char *PRECRQ_PH_W(uint64 instruction, Dis_info *info) 11657 { 11658 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11659 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11660 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 11661 11662 const char *rd = GPR(rd_value, info); 11663 const char *rs = GPR(rs_value, info); 11664 const char *rt = GPR(rt_value, info); 11665 11666 return img_format("PRECRQ.PH.W %s, %s, %s", rd, rs, rt); 11667 } 11668 11669 11670 /* 11671 * [DSP] PRECRQ.QB.PH rd, rs, rt - Reduce the precision of four fractional 11672 * halfwords to four bytes 11673 * 11674 * 3 2 1 11675 * 10987654321098765432109876543210 11676 * 001000 x0010101101 11677 * rt ----- 11678 * rs ----- 11679 * rd ----- 11680 */ 11681 static char *PRECRQ_QB_PH(uint64 instruction, Dis_info *info) 11682 { 11683 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11684 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11685 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 11686 11687 const char *rd = GPR(rd_value, info); 11688 const char *rs = GPR(rs_value, info); 11689 const char *rt = GPR(rt_value, info); 11690 11691 return img_format("PRECRQ.QB.PH %s, %s, %s", rd, rs, rt); 11692 } 11693 11694 11695 /* 11696 * [DSP] PRECRQ_RS.PH.W rd, rs, rt - Reduce the precision of fractional 11697 * words to halfwords with rounding and saturation 11698 * 11699 * 3 2 1 11700 * 10987654321098765432109876543210 11701 * 001000 x1110000101 11702 * rt ----- 11703 * rs ----- 11704 * rd ----- 11705 */ 11706 static char *PRECRQ_RS_PH_W(uint64 instruction, Dis_info *info) 11707 { 11708 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11709 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11710 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 11711 11712 const char *rd = GPR(rd_value, info); 11713 const char *rs = GPR(rs_value, info); 11714 const char *rt = GPR(rt_value, info); 11715 11716 return img_format("PRECRQ_RS.PH.W %s, %s, %s", rd, rs, rt); 11717 } 11718 11719 11720 /* 11721 * [DSP] PRECRQU_S.QB.PH rd, rs, rt - Reduce the precision of fractional 11722 * halfwords to unsigned bytes with saturation 11723 * 11724 * 3 2 1 11725 * 10987654321098765432109876543210 11726 * 001000 x1110000101 11727 * rt ----- 11728 * rs ----- 11729 * rd ----- 11730 */ 11731 static char *PRECRQU_S_QB_PH(uint64 instruction, Dis_info *info) 11732 { 11733 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11734 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11735 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 11736 11737 const char *rd = GPR(rd_value, info); 11738 const char *rs = GPR(rs_value, info); 11739 const char *rt = GPR(rt_value, info); 11740 11741 return img_format("PRECRQU_S.QB.PH %s, %s, %s", rd, rs, rt); 11742 } 11743 11744 11745 /* 11746 * 11747 * 11748 * 3 2 1 11749 * 10987654321098765432109876543210 11750 * 001000 x1110000101 11751 * rt ----- 11752 * rs ----- 11753 * rd ----- 11754 */ 11755 static char *PREF_S9_(uint64 instruction, Dis_info *info) 11756 { 11757 uint64 hint_value = extract_hint_25_24_23_22_21(instruction); 11758 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11759 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 11760 11761 const char *rs = GPR(rs_value, info); 11762 11763 return img_format("PREF 0x%" PRIx64 ", %" PRId64 "(%s)", 11764 hint_value, s_value, rs); 11765 } 11766 11767 11768 /* 11769 * 11770 * 11771 * 3 2 1 11772 * 10987654321098765432109876543210 11773 * 001000 x1110000101 11774 * rt ----- 11775 * rs ----- 11776 * rd ----- 11777 */ 11778 static char *PREF_U12_(uint64 instruction, Dis_info *info) 11779 { 11780 uint64 hint_value = extract_hint_25_24_23_22_21(instruction); 11781 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11782 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 11783 11784 const char *rs = GPR(rs_value, info); 11785 11786 return img_format("PREF 0x%" PRIx64 ", 0x%" PRIx64 "(%s)", 11787 hint_value, u_value, rs); 11788 } 11789 11790 11791 /* 11792 * 11793 * 11794 * 3 2 1 11795 * 10987654321098765432109876543210 11796 * 001000 x1110000101 11797 * rt ----- 11798 * rs ----- 11799 * rd ----- 11800 */ 11801 static char *PREFE(uint64 instruction, Dis_info *info) 11802 { 11803 uint64 hint_value = extract_hint_25_24_23_22_21(instruction); 11804 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11805 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 11806 11807 const char *rs = GPR(rs_value, info); 11808 11809 return img_format("PREFE 0x%" PRIx64 ", %" PRId64 "(%s)", 11810 hint_value, s_value, rs); 11811 } 11812 11813 11814 /* 11815 * [DSP] PREPEND rt, rs, sa - Right shift and prepend bits to the MSB 11816 * 11817 * 3 2 1 11818 * 10987654321098765432109876543210 11819 * 001000 x1110000101 11820 * rt ----- 11821 * rs ----- 11822 * rd ----- 11823 */ 11824 static char *PREPEND(uint64 instruction, Dis_info *info) 11825 { 11826 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11827 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11828 uint64 sa_value = extract_sa_15_14_13_12_11(instruction); 11829 11830 const char *rt = GPR(rt_value, info); 11831 const char *rs = GPR(rs_value, info); 11832 11833 return img_format("PREPEND %s, %s, 0x%" PRIx64, rt, rs, sa_value); 11834 } 11835 11836 11837 /* 11838 * [DSP] RADDU.W.QB rt, rs - Unsigned reduction add of vector quad bytes 11839 * 11840 * 3 2 1 11841 * 10987654321098765432109876543210 11842 * 001000 1111000100111111 11843 * rt ----- 11844 * rs ----- 11845 */ 11846 static char *RADDU_W_QB(uint64 instruction, Dis_info *info) 11847 { 11848 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11849 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11850 11851 const char *rt = GPR(rt_value, info); 11852 const char *rs = GPR(rs_value, info); 11853 11854 return img_format("RADDU.W.QB %s, %s", rt, rs); 11855 } 11856 11857 11858 /* 11859 * [DSP] RDDSP rt, mask - Read DSPControl register fields to a GPR 11860 * 11861 * 3 2 1 11862 * 10987654321098765432109876543210 11863 * 001000 00011001111111 11864 * rt ----- 11865 * mask ------- 11866 */ 11867 static char *RDDSP(uint64 instruction, Dis_info *info) 11868 { 11869 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11870 uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction); 11871 11872 const char *rt = GPR(rt_value, info); 11873 11874 return img_format("RDDSP %s, 0x%" PRIx64, rt, mask_value); 11875 } 11876 11877 11878 /* 11879 * 11880 * 11881 * 3 2 1 11882 * 10987654321098765432109876543210 11883 * 001000 x1110000101 11884 * rt ----- 11885 * rs ----- 11886 * rd ----- 11887 */ 11888 static char *RDHWR(uint64 instruction, Dis_info *info) 11889 { 11890 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11891 uint64 hs_value = extract_hs_20_19_18_17_16(instruction); 11892 uint64 sel_value = extract_sel_13_12_11(instruction); 11893 11894 const char *rt = GPR(rt_value, info); 11895 11896 return img_format("RDHWR %s, CP%" PRIu64 ", 0x%" PRIx64, 11897 rt, hs_value, sel_value); 11898 } 11899 11900 11901 /* 11902 * 11903 * 11904 * 3 2 1 11905 * 10987654321098765432109876543210 11906 * 001000 x1110000101 11907 * rt ----- 11908 * rs ----- 11909 * rd ----- 11910 */ 11911 static char *RDPGPR(uint64 instruction, Dis_info *info) 11912 { 11913 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11914 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 11915 11916 const char *rt = GPR(rt_value, info); 11917 const char *rs = GPR(rs_value, info); 11918 11919 return img_format("RDPGPR %s, %s", rt, rs); 11920 } 11921 11922 11923 /* 11924 * 11925 * 11926 * 3 2 1 11927 * 10987654321098765432109876543210 11928 * 001000 x1110000101 11929 * rt ----- 11930 * rs ----- 11931 * rd ----- 11932 */ 11933 static char *RECIP_D(uint64 instruction, Dis_info *info) 11934 { 11935 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 11936 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 11937 11938 const char *ft = FPR(ft_value, info); 11939 const char *fs = FPR(fs_value, info); 11940 11941 return img_format("RECIP.D %s, %s", ft, fs); 11942 } 11943 11944 11945 /* 11946 * 11947 * 11948 * 3 2 1 11949 * 10987654321098765432109876543210 11950 * 001000 x1110000101 11951 * rt ----- 11952 * rs ----- 11953 * rd ----- 11954 */ 11955 static char *RECIP_S(uint64 instruction, Dis_info *info) 11956 { 11957 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 11958 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 11959 11960 const char *ft = FPR(ft_value, info); 11961 const char *fs = FPR(fs_value, info); 11962 11963 return img_format("RECIP.S %s, %s", ft, fs); 11964 } 11965 11966 11967 /* 11968 * [DSP] REPL.PH rd, s - Replicate immediate integer into all vector element 11969 * positions 11970 * 11971 * 3 2 1 11972 * 10987654321098765432109876543210 11973 * 001000 x0000111101 11974 * rt ----- 11975 * s ---------- 11976 */ 11977 static char *REPL_PH(uint64 instruction, Dis_info *info) 11978 { 11979 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 11980 int64 s_value = extract_s__se9_20_19_18_17_16_15_14_13_12_11(instruction); 11981 11982 const char *rt = GPR(rt_value, info); 11983 11984 return img_format("REPL.PH %s, %" PRId64, rt, s_value); 11985 } 11986 11987 11988 /* 11989 * [DSP] REPL.QB rd, u - Replicate immediate integer into all vector element 11990 * positions 11991 * 11992 * 3 2 1 11993 * 10987654321098765432109876543210 11994 * 001000 x010111111111 11995 * rt ----- 11996 * u -------- 11997 */ 11998 static char *REPL_QB(uint64 instruction, Dis_info *info) 11999 { 12000 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12001 uint64 u_value = extract_u_20_19_18_17_16_15_14_13(instruction); 12002 12003 const char *rt = GPR(rt_value, info); 12004 12005 return img_format("REPL.QB %s, 0x%" PRIx64, rt, u_value); 12006 } 12007 12008 12009 /* 12010 * [DSP] REPLV.PH rt, rs - Replicate a halfword into all vector element 12011 * positions 12012 * 12013 * 3 2 1 12014 * 10987654321098765432109876543210 12015 * 001000 0000001100111111 12016 * rt ----- 12017 * rs ----- 12018 */ 12019 static char *REPLV_PH(uint64 instruction, Dis_info *info) 12020 { 12021 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12022 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12023 12024 const char *rt = GPR(rt_value, info); 12025 const char *rs = GPR(rs_value, info); 12026 12027 return img_format("REPLV.PH %s, %s", rt, rs); 12028 } 12029 12030 12031 /* 12032 * [DSP] REPLV.QB rt, rs - Replicate byte into all vector element positions 12033 * 12034 * 3 2 1 12035 * 10987654321098765432109876543210 12036 * 001000 0001001100111111 12037 * rt ----- 12038 * rs ----- 12039 */ 12040 static char *REPLV_QB(uint64 instruction, Dis_info *info) 12041 { 12042 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12043 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12044 12045 const char *rt = GPR(rt_value, info); 12046 const char *rs = GPR(rs_value, info); 12047 12048 return img_format("REPLV.QB %s, %s", rt, rs); 12049 } 12050 12051 12052 /* 12053 * 12054 * 12055 * 3 2 1 12056 * 10987654321098765432109876543210 12057 * 001000 x1110000101 12058 * rt ----- 12059 * rs ----- 12060 * rd ----- 12061 */ 12062 static char *RESTORE_32_(uint64 instruction, Dis_info *info) 12063 { 12064 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12065 uint64 count_value = extract_count_19_18_17_16(instruction); 12066 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction); 12067 uint64 gp_value = extract_gp_2(instruction); 12068 12069 g_autofree char *save_restore_str = save_restore_list( 12070 rt_value, count_value, gp_value, info); 12071 return img_format("RESTORE 0x%" PRIx64 "%s", u_value, save_restore_str); 12072 } 12073 12074 12075 /* 12076 * 12077 * 12078 * 3 2 1 12079 * 10987654321098765432109876543210 12080 * 001000 x1110000101 12081 * rt ----- 12082 * rs ----- 12083 * rd ----- 12084 */ 12085 static char *RESTORE_JRC_16_(uint64 instruction, Dis_info *info) 12086 { 12087 uint64 rt1_value = extract_rtl_11(instruction); 12088 uint64 u_value = extract_u_7_6_5_4__s4(instruction); 12089 uint64 count_value = extract_count_3_2_1_0(instruction); 12090 12091 g_autofree char *save_restore_str = save_restore_list( 12092 encode_rt1_from_rt(rt1_value), count_value, 0, info); 12093 return img_format("RESTORE.JRC 0x%" PRIx64 "%s", u_value, save_restore_str); 12094 } 12095 12096 12097 /* 12098 * 12099 * 12100 * 3 2 1 12101 * 10987654321098765432109876543210 12102 * 001000 x1110000101 12103 * rt ----- 12104 * rs ----- 12105 * rd ----- 12106 */ 12107 static char *RESTORE_JRC_32_(uint64 instruction, Dis_info *info) 12108 { 12109 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12110 uint64 count_value = extract_count_19_18_17_16(instruction); 12111 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction); 12112 uint64 gp_value = extract_gp_2(instruction); 12113 12114 g_autofree char *save_restore_str = save_restore_list( 12115 rt_value, count_value, gp_value, info); 12116 return img_format("RESTORE.JRC 0x%" PRIx64 "%s", u_value, 12117 save_restore_str); 12118 } 12119 12120 12121 /* 12122 * 12123 * 12124 * 3 2 1 12125 * 10987654321098765432109876543210 12126 * 001000 x1110000101 12127 * rt ----- 12128 * rs ----- 12129 * rd ----- 12130 */ 12131 static char *RESTOREF(uint64 instruction, Dis_info *info) 12132 { 12133 uint64 count_value = extract_count_19_18_17_16(instruction); 12134 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction); 12135 12136 12137 return img_format("RESTOREF 0x%" PRIx64 ", 0x%" PRIx64, 12138 u_value, count_value); 12139 } 12140 12141 12142 /* 12143 * 12144 * 12145 * 3 2 1 12146 * 10987654321098765432109876543210 12147 * 001000 x1110000101 12148 * rt ----- 12149 * rs ----- 12150 * rd ----- 12151 */ 12152 static char *RINT_D(uint64 instruction, Dis_info *info) 12153 { 12154 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 12155 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 12156 12157 const char *ft = FPR(ft_value, info); 12158 const char *fs = FPR(fs_value, info); 12159 12160 return img_format("RINT.D %s, %s", ft, fs); 12161 } 12162 12163 12164 /* 12165 * 12166 * 12167 * 3 2 1 12168 * 10987654321098765432109876543210 12169 * 001000 x1110000101 12170 * rt ----- 12171 * rs ----- 12172 * rd ----- 12173 */ 12174 static char *RINT_S(uint64 instruction, Dis_info *info) 12175 { 12176 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 12177 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 12178 12179 const char *ft = FPR(ft_value, info); 12180 const char *fs = FPR(fs_value, info); 12181 12182 return img_format("RINT.S %s, %s", ft, fs); 12183 } 12184 12185 12186 /* 12187 * 12188 * 12189 * 3 2 1 12190 * 10987654321098765432109876543210 12191 * 001000 x1110000101 12192 * rt ----- 12193 * rs ----- 12194 * rd ----- 12195 */ 12196 static char *ROTR(uint64 instruction, Dis_info *info) 12197 { 12198 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12199 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12200 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 12201 12202 const char *rt = GPR(rt_value, info); 12203 const char *rs = GPR(rs_value, info); 12204 12205 return img_format("ROTR %s, %s, 0x%" PRIx64, rt, rs, shift_value); 12206 } 12207 12208 12209 /* 12210 * 12211 * 12212 * 3 2 1 12213 * 10987654321098765432109876543210 12214 * 001000 x1110000101 12215 * rt ----- 12216 * rs ----- 12217 * rd ----- 12218 */ 12219 static char *ROTRV(uint64 instruction, Dis_info *info) 12220 { 12221 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12222 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12223 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 12224 12225 const char *rd = GPR(rd_value, info); 12226 const char *rs = GPR(rs_value, info); 12227 const char *rt = GPR(rt_value, info); 12228 12229 return img_format("ROTRV %s, %s, %s", rd, rs, rt); 12230 } 12231 12232 12233 /* 12234 * 12235 * 12236 * 3 2 1 12237 * 10987654321098765432109876543210 12238 * 001000 x1110000101 12239 * rt ----- 12240 * rs ----- 12241 * rd ----- 12242 */ 12243 static char *ROTX(uint64 instruction, Dis_info *info) 12244 { 12245 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12246 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12247 uint64 shiftx_value = extract_shiftx_10_9_8_7__s1(instruction); 12248 uint64 stripe_value = extract_stripe_6(instruction); 12249 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 12250 12251 const char *rt = GPR(rt_value, info); 12252 const char *rs = GPR(rs_value, info); 12253 12254 return img_format("ROTX %s, %s, 0x%" PRIx64 ", 0x%" PRIx64 ", 0x%" PRIx64, 12255 rt, rs, shift_value, shiftx_value, stripe_value); 12256 } 12257 12258 12259 /* 12260 * 12261 * 12262 * 3 2 1 12263 * 10987654321098765432109876543210 12264 * 001000 x1110000101 12265 * rt ----- 12266 * rs ----- 12267 * rd ----- 12268 */ 12269 static char *ROUND_L_D(uint64 instruction, Dis_info *info) 12270 { 12271 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 12272 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 12273 12274 const char *ft = FPR(ft_value, info); 12275 const char *fs = FPR(fs_value, info); 12276 12277 return img_format("ROUND.L.D %s, %s", ft, fs); 12278 } 12279 12280 12281 /* 12282 * 12283 * 12284 * 3 2 1 12285 * 10987654321098765432109876543210 12286 * 001000 x1110000101 12287 * rt ----- 12288 * rs ----- 12289 * rd ----- 12290 */ 12291 static char *ROUND_L_S(uint64 instruction, Dis_info *info) 12292 { 12293 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 12294 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 12295 12296 const char *ft = FPR(ft_value, info); 12297 const char *fs = FPR(fs_value, info); 12298 12299 return img_format("ROUND.L.S %s, %s", ft, fs); 12300 } 12301 12302 12303 /* 12304 * 12305 * 12306 * 3 2 1 12307 * 10987654321098765432109876543210 12308 * 001000 x1110000101 12309 * rt ----- 12310 * rs ----- 12311 * rd ----- 12312 */ 12313 static char *ROUND_W_D(uint64 instruction, Dis_info *info) 12314 { 12315 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 12316 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 12317 12318 const char *ft = FPR(ft_value, info); 12319 const char *fs = FPR(fs_value, info); 12320 12321 return img_format("ROUND.W.D %s, %s", ft, fs); 12322 } 12323 12324 12325 /* 12326 * 12327 * 12328 * 3 2 1 12329 * 10987654321098765432109876543210 12330 * 001000 x1110000101 12331 * rt ----- 12332 * rs ----- 12333 * rd ----- 12334 */ 12335 static char *ROUND_W_S(uint64 instruction, Dis_info *info) 12336 { 12337 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 12338 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 12339 12340 const char *ft = FPR(ft_value, info); 12341 const char *fs = FPR(fs_value, info); 12342 12343 return img_format("ROUND.W.S %s, %s", ft, fs); 12344 } 12345 12346 12347 /* 12348 * 12349 * 12350 * 3 2 1 12351 * 10987654321098765432109876543210 12352 * 001000 x1110000101 12353 * rt ----- 12354 * rs ----- 12355 * rd ----- 12356 */ 12357 static char *RSQRT_D(uint64 instruction, Dis_info *info) 12358 { 12359 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 12360 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 12361 12362 const char *ft = FPR(ft_value, info); 12363 const char *fs = FPR(fs_value, info); 12364 12365 return img_format("RSQRT.D %s, %s", ft, fs); 12366 } 12367 12368 12369 /* 12370 * 12371 * 12372 * 3 2 1 12373 * 10987654321098765432109876543210 12374 * 001000 x1110000101 12375 * rt ----- 12376 * rs ----- 12377 * rd ----- 12378 */ 12379 static char *RSQRT_S(uint64 instruction, Dis_info *info) 12380 { 12381 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 12382 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 12383 12384 const char *ft = FPR(ft_value, info); 12385 const char *fs = FPR(fs_value, info); 12386 12387 return img_format("RSQRT.S %s, %s", ft, fs); 12388 } 12389 12390 12391 /* 12392 * 12393 * 12394 * 3 2 1 12395 * 10987654321098765432109876543210 12396 * 001000 01001001101 12397 * rt ----- 12398 * rs ----- 12399 * rd ----- 12400 */ 12401 static char *SAVE_16_(uint64 instruction, Dis_info *info) 12402 { 12403 uint64 rt1_value = extract_rtl_11(instruction); 12404 uint64 u_value = extract_u_7_6_5_4__s4(instruction); 12405 uint64 count_value = extract_count_3_2_1_0(instruction); 12406 12407 g_autofree char *save_restore_str = save_restore_list( 12408 encode_rt1_from_rt(rt1_value), count_value, 0, info); 12409 return img_format("SAVE 0x%" PRIx64 "%s", u_value, save_restore_str); 12410 } 12411 12412 12413 /* 12414 * 12415 * 12416 * 3 2 1 12417 * 10987654321098765432109876543210 12418 * 001000 01001001101 12419 * rt ----- 12420 * rs ----- 12421 * rd ----- 12422 */ 12423 static char *SAVE_32_(uint64 instruction, Dis_info *info) 12424 { 12425 uint64 count_value = extract_count_19_18_17_16(instruction); 12426 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12427 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction); 12428 uint64 gp_value = extract_gp_2(instruction); 12429 12430 g_autofree char *save_restore_str = save_restore_list( 12431 rt_value, count_value, gp_value, info); 12432 return img_format("SAVE 0x%" PRIx64 "%s", u_value, save_restore_str); 12433 } 12434 12435 12436 /* 12437 * 12438 * 12439 * 3 2 1 12440 * 10987654321098765432109876543210 12441 * 001000 01001001101 12442 * rt ----- 12443 * rs ----- 12444 * rd ----- 12445 */ 12446 static char *SAVEF(uint64 instruction, Dis_info *info) 12447 { 12448 uint64 count_value = extract_count_19_18_17_16(instruction); 12449 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction); 12450 12451 12452 return img_format("SAVEF 0x%" PRIx64 ", 0x%" PRIx64, u_value, count_value); 12453 } 12454 12455 12456 /* 12457 * 12458 * 12459 * 3 2 1 12460 * 10987654321098765432109876543210 12461 * 001000 01001001101 12462 * rt ----- 12463 * rs ----- 12464 * rd ----- 12465 */ 12466 static char *SB_16_(uint64 instruction, Dis_info *info) 12467 { 12468 uint64 rtz3_value = extract_rtz3_9_8_7(instruction); 12469 uint64 rs3_value = extract_rs3_6_5_4(instruction); 12470 uint64 u_value = extract_u_1_0(instruction); 12471 12472 const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info); 12473 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 12474 12475 return img_format("SB %s, 0x%" PRIx64 "(%s)", rtz3, u_value, rs3); 12476 } 12477 12478 12479 /* 12480 * 12481 * 12482 * 3 2 1 12483 * 10987654321098765432109876543210 12484 * 001000 01001001101 12485 * rt ----- 12486 * rs ----- 12487 * rd ----- 12488 */ 12489 static char *SB_GP_(uint64 instruction, Dis_info *info) 12490 { 12491 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12492 uint64 u_value = extract_u_17_to_0(instruction); 12493 12494 const char *rt = GPR(rt_value, info); 12495 12496 return img_format("SB %s, 0x%" PRIx64 "($%d)", rt, u_value, 28); 12497 } 12498 12499 12500 /* 12501 * 12502 * 12503 * 3 2 1 12504 * 10987654321098765432109876543210 12505 * 001000 01001001101 12506 * rt ----- 12507 * rs ----- 12508 * rd ----- 12509 */ 12510 static char *SB_S9_(uint64 instruction, Dis_info *info) 12511 { 12512 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12513 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12514 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 12515 12516 const char *rt = GPR(rt_value, info); 12517 const char *rs = GPR(rs_value, info); 12518 12519 return img_format("SB %s, %" PRId64 "(%s)", rt, s_value, rs); 12520 } 12521 12522 12523 /* 12524 * 12525 * 12526 * 3 2 1 12527 * 10987654321098765432109876543210 12528 * 001000 01001001101 12529 * rt ----- 12530 * rs ----- 12531 * rd ----- 12532 */ 12533 static char *SB_U12_(uint64 instruction, Dis_info *info) 12534 { 12535 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12536 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12537 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 12538 12539 const char *rt = GPR(rt_value, info); 12540 const char *rs = GPR(rs_value, info); 12541 12542 return img_format("SB %s, 0x%" PRIx64 "(%s)", rt, u_value, rs); 12543 } 12544 12545 12546 /* 12547 * 12548 * 12549 * 3 2 1 12550 * 10987654321098765432109876543210 12551 * 001000 01001001101 12552 * rt ----- 12553 * rs ----- 12554 * rd ----- 12555 */ 12556 static char *SBE(uint64 instruction, Dis_info *info) 12557 { 12558 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12559 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12560 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 12561 12562 const char *rt = GPR(rt_value, info); 12563 const char *rs = GPR(rs_value, info); 12564 12565 return img_format("SBE %s, %" PRId64 "(%s)", rt, s_value, rs); 12566 } 12567 12568 12569 /* 12570 * 12571 * 12572 * 3 2 1 12573 * 10987654321098765432109876543210 12574 * 001000 01001001101 12575 * rt ----- 12576 * rs ----- 12577 * rd ----- 12578 */ 12579 static char *SBX(uint64 instruction, Dis_info *info) 12580 { 12581 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12582 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12583 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 12584 12585 const char *rd = GPR(rd_value, info); 12586 const char *rs = GPR(rs_value, info); 12587 const char *rt = GPR(rt_value, info); 12588 12589 return img_format("SBX %s, %s(%s)", rd, rs, rt); 12590 } 12591 12592 12593 /* 12594 * 12595 * 12596 * 3 2 1 12597 * 10987654321098765432109876543210 12598 * 001000 01001001101 12599 * rt ----- 12600 * rs ----- 12601 * rd ----- 12602 */ 12603 static char *SC(uint64 instruction, Dis_info *info) 12604 { 12605 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12606 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12607 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction); 12608 12609 const char *rt = GPR(rt_value, info); 12610 const char *rs = GPR(rs_value, info); 12611 12612 return img_format("SC %s, %" PRId64 "(%s)", rt, s_value, rs); 12613 } 12614 12615 12616 /* 12617 * 12618 * 12619 * 3 2 1 12620 * 10987654321098765432109876543210 12621 * 001000 01001001101 12622 * rt ----- 12623 * rs ----- 12624 * rd ----- 12625 */ 12626 static char *SCD(uint64 instruction, Dis_info *info) 12627 { 12628 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12629 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12630 int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction); 12631 12632 const char *rt = GPR(rt_value, info); 12633 const char *rs = GPR(rs_value, info); 12634 12635 return img_format("SCD %s, %" PRId64 "(%s)", rt, s_value, rs); 12636 } 12637 12638 12639 /* 12640 * 12641 * 12642 * 3 2 1 12643 * 10987654321098765432109876543210 12644 * 001000 01001001101 12645 * rt ----- 12646 * rs ----- 12647 * rd ----- 12648 */ 12649 static char *SCDP(uint64 instruction, Dis_info *info) 12650 { 12651 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12652 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12653 uint64 ru_value = extract_ru_7_6_5_4_3(instruction); 12654 12655 const char *rt = GPR(rt_value, info); 12656 const char *ru = GPR(ru_value, info); 12657 const char *rs = GPR(rs_value, info); 12658 12659 return img_format("SCDP %s, %s, (%s)", rt, ru, rs); 12660 } 12661 12662 12663 /* 12664 * 12665 * 12666 * 3 2 1 12667 * 10987654321098765432109876543210 12668 * 001000 01001001101 12669 * rt ----- 12670 * rs ----- 12671 * rd ----- 12672 */ 12673 static char *SCE(uint64 instruction, Dis_info *info) 12674 { 12675 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12676 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12677 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction); 12678 12679 const char *rt = GPR(rt_value, info); 12680 const char *rs = GPR(rs_value, info); 12681 12682 return img_format("SCE %s, %" PRId64 "(%s)", rt, s_value, rs); 12683 } 12684 12685 12686 /* 12687 * 12688 * 12689 * 3 2 1 12690 * 10987654321098765432109876543210 12691 * 001000 01001001101 12692 * rt ----- 12693 * rs ----- 12694 * rd ----- 12695 */ 12696 static char *SCWP(uint64 instruction, Dis_info *info) 12697 { 12698 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12699 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12700 uint64 ru_value = extract_ru_7_6_5_4_3(instruction); 12701 12702 const char *rt = GPR(rt_value, info); 12703 const char *ru = GPR(ru_value, info); 12704 const char *rs = GPR(rs_value, info); 12705 12706 return img_format("SCWP %s, %s, (%s)", rt, ru, rs); 12707 } 12708 12709 12710 /* 12711 * 12712 * 12713 * 3 2 1 12714 * 10987654321098765432109876543210 12715 * 001000 01001001101 12716 * rt ----- 12717 * rs ----- 12718 * rd ----- 12719 */ 12720 static char *SCWPE(uint64 instruction, Dis_info *info) 12721 { 12722 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12723 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12724 uint64 ru_value = extract_ru_7_6_5_4_3(instruction); 12725 12726 const char *rt = GPR(rt_value, info); 12727 const char *ru = GPR(ru_value, info); 12728 const char *rs = GPR(rs_value, info); 12729 12730 return img_format("SCWPE %s, %s, (%s)", rt, ru, rs); 12731 } 12732 12733 12734 /* 12735 * 12736 * 12737 * 3 2 1 12738 * 10987654321098765432109876543210 12739 * 001000 01001001101 12740 * rt ----- 12741 * rs ----- 12742 * rd ----- 12743 */ 12744 static char *SD_GP_(uint64 instruction, Dis_info *info) 12745 { 12746 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12747 uint64 u_value = extract_u_20_to_3__s3(instruction); 12748 12749 const char *rt = GPR(rt_value, info); 12750 12751 return img_format("SD %s, 0x%" PRIx64 "($%d)", rt, u_value, 28); 12752 } 12753 12754 12755 /* 12756 * 12757 * 12758 * 3 2 1 12759 * 10987654321098765432109876543210 12760 * 001000 01001001101 12761 * rt ----- 12762 * rs ----- 12763 * rd ----- 12764 */ 12765 static char *SD_S9_(uint64 instruction, Dis_info *info) 12766 { 12767 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12768 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12769 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 12770 12771 const char *rt = GPR(rt_value, info); 12772 const char *rs = GPR(rs_value, info); 12773 12774 return img_format("SD %s, %" PRId64 "(%s)", rt, s_value, rs); 12775 } 12776 12777 12778 /* 12779 * 12780 * 12781 * 3 2 1 12782 * 10987654321098765432109876543210 12783 * 001000 01001001101 12784 * rt ----- 12785 * rs ----- 12786 * rd ----- 12787 */ 12788 static char *SD_U12_(uint64 instruction, Dis_info *info) 12789 { 12790 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12791 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12792 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 12793 12794 const char *rt = GPR(rt_value, info); 12795 const char *rs = GPR(rs_value, info); 12796 12797 return img_format("SD %s, 0x%" PRIx64 "(%s)", rt, u_value, rs); 12798 } 12799 12800 12801 /* 12802 * 12803 * 12804 * 3 2 1 12805 * 10987654321098765432109876543210 12806 * 001000 01001001101 12807 * rt ----- 12808 * rs ----- 12809 * rd ----- 12810 */ 12811 static char *SDBBP_16_(uint64 instruction, Dis_info *info) 12812 { 12813 uint64 code_value = extract_code_2_1_0(instruction); 12814 12815 12816 return img_format("SDBBP 0x%" PRIx64, code_value); 12817 } 12818 12819 12820 /* 12821 * 12822 * 12823 * 3 2 1 12824 * 10987654321098765432109876543210 12825 * 001000 01001001101 12826 * rt ----- 12827 * rs ----- 12828 * rd ----- 12829 */ 12830 static char *SDBBP_32_(uint64 instruction, Dis_info *info) 12831 { 12832 uint64 code_value = extract_code_18_to_0(instruction); 12833 12834 12835 return img_format("SDBBP 0x%" PRIx64, code_value); 12836 } 12837 12838 12839 /* 12840 * 12841 * 12842 * 3 2 1 12843 * 10987654321098765432109876543210 12844 * 001000 01001001101 12845 * rt ----- 12846 * rs ----- 12847 * rd ----- 12848 */ 12849 static char *SDC1_GP_(uint64 instruction, Dis_info *info) 12850 { 12851 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 12852 uint64 u_value = extract_u_17_to_2__s2(instruction); 12853 12854 const char *ft = FPR(ft_value, info); 12855 12856 return img_format("SDC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28); 12857 } 12858 12859 12860 /* 12861 * 12862 * 12863 * 3 2 1 12864 * 10987654321098765432109876543210 12865 * 001000 01001001101 12866 * rt ----- 12867 * rs ----- 12868 * rd ----- 12869 */ 12870 static char *SDC1_S9_(uint64 instruction, Dis_info *info) 12871 { 12872 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 12873 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12874 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 12875 12876 const char *ft = FPR(ft_value, info); 12877 const char *rs = GPR(rs_value, info); 12878 12879 return img_format("SDC1 %s, %" PRId64 "(%s)", ft, s_value, rs); 12880 } 12881 12882 12883 /* 12884 * 12885 * 12886 * 3 2 1 12887 * 10987654321098765432109876543210 12888 * 001000 01001001101 12889 * rt ----- 12890 * rs ----- 12891 * rd ----- 12892 */ 12893 static char *SDC1_U12_(uint64 instruction, Dis_info *info) 12894 { 12895 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 12896 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12897 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 12898 12899 const char *ft = FPR(ft_value, info); 12900 const char *rs = GPR(rs_value, info); 12901 12902 return img_format("SDC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs); 12903 } 12904 12905 12906 /* 12907 * 12908 * 12909 * 3 2 1 12910 * 10987654321098765432109876543210 12911 * 001000 01001001101 12912 * rt ----- 12913 * rs ----- 12914 * rd ----- 12915 */ 12916 static char *SDC1X(uint64 instruction, Dis_info *info) 12917 { 12918 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12919 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12920 uint64 ft_value = extract_ft_15_14_13_12_11(instruction); 12921 12922 const char *ft = FPR(ft_value, info); 12923 const char *rs = GPR(rs_value, info); 12924 const char *rt = GPR(rt_value, info); 12925 12926 return img_format("SDC1X %s, %s(%s)", ft, rs, rt); 12927 } 12928 12929 12930 /* 12931 * 12932 * 12933 * 3 2 1 12934 * 10987654321098765432109876543210 12935 * 001000 01001001101 12936 * rt ----- 12937 * rs ----- 12938 * rd ----- 12939 */ 12940 static char *SDC1XS(uint64 instruction, Dis_info *info) 12941 { 12942 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12943 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12944 uint64 ft_value = extract_ft_15_14_13_12_11(instruction); 12945 12946 const char *ft = FPR(ft_value, info); 12947 const char *rs = GPR(rs_value, info); 12948 const char *rt = GPR(rt_value, info); 12949 12950 return img_format("SDC1XS %s, %s(%s)", ft, rs, rt); 12951 } 12952 12953 12954 /* 12955 * 12956 * 12957 * 3 2 1 12958 * 10987654321098765432109876543210 12959 * 001000 01001001101 12960 * rt ----- 12961 * rs ----- 12962 * rd ----- 12963 */ 12964 static char *SDC2(uint64 instruction, Dis_info *info) 12965 { 12966 uint64 cs_value = extract_cs_25_24_23_22_21(instruction); 12967 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12968 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 12969 12970 const char *rs = GPR(rs_value, info); 12971 12972 return img_format("SDC2 CP%" PRIu64 ", %" PRId64 "(%s)", 12973 cs_value, s_value, rs); 12974 } 12975 12976 12977 /* 12978 * 12979 * 12980 * 3 2 1 12981 * 10987654321098765432109876543210 12982 * 001000 01001001101 12983 * rt ----- 12984 * rs ----- 12985 * rd ----- 12986 */ 12987 static char *SDM(uint64 instruction, Dis_info *info) 12988 { 12989 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 12990 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 12991 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 12992 uint64 count3_value = extract_count3_14_13_12(instruction); 12993 12994 const char *rt = GPR(rt_value, info); 12995 const char *rs = GPR(rs_value, info); 12996 uint64 count3 = encode_count3_from_count(count3_value); 12997 12998 return img_format("SDM %s, %" PRId64 "(%s), 0x%" PRIx64, 12999 rt, s_value, rs, count3); 13000 } 13001 13002 13003 /* 13004 * 13005 * 13006 * 3 2 1 13007 * 10987654321098765432109876543210 13008 * 001000 01001001101 13009 * rt ----- 13010 * rs ----- 13011 * rd ----- 13012 */ 13013 static char *SDPC_48_(uint64 instruction, Dis_info *info) 13014 { 13015 uint64 rt_value = extract_rt_41_40_39_38_37(instruction); 13016 int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); 13017 13018 const char *rt = GPR(rt_value, info); 13019 g_autofree char *s = ADDRESS(s_value, 6, info); 13020 13021 return img_format("SDPC %s, %s", rt, s); 13022 } 13023 13024 13025 /* 13026 * 13027 * 13028 * 3 2 1 13029 * 10987654321098765432109876543210 13030 * 001000 01001001101 13031 * rt ----- 13032 * rs ----- 13033 * rd ----- 13034 */ 13035 static char *SDXS(uint64 instruction, Dis_info *info) 13036 { 13037 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13038 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13039 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13040 13041 const char *rd = GPR(rd_value, info); 13042 const char *rs = GPR(rs_value, info); 13043 const char *rt = GPR(rt_value, info); 13044 13045 return img_format("SDXS %s, %s(%s)", rd, rs, rt); 13046 } 13047 13048 13049 /* 13050 * 13051 * 13052 * 3 2 1 13053 * 10987654321098765432109876543210 13054 * 001000 01001001101 13055 * rt ----- 13056 * rs ----- 13057 * rd ----- 13058 */ 13059 static char *SDX(uint64 instruction, Dis_info *info) 13060 { 13061 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13062 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13063 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13064 13065 const char *rd = GPR(rd_value, info); 13066 const char *rs = GPR(rs_value, info); 13067 const char *rt = GPR(rt_value, info); 13068 13069 return img_format("SDX %s, %s(%s)", rd, rs, rt); 13070 } 13071 13072 13073 /* 13074 * 13075 * 13076 * 3 2 1 13077 * 10987654321098765432109876543210 13078 * 001000 01001001101 13079 * rt ----- 13080 * rs ----- 13081 * rd ----- 13082 */ 13083 static char *SEB(uint64 instruction, Dis_info *info) 13084 { 13085 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13086 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13087 13088 const char *rt = GPR(rt_value, info); 13089 const char *rs = GPR(rs_value, info); 13090 13091 return img_format("SEB %s, %s", rt, rs); 13092 } 13093 13094 13095 /* 13096 * 13097 * 13098 * 3 2 1 13099 * 10987654321098765432109876543210 13100 * 001000 01001001101 13101 * rt ----- 13102 * rs ----- 13103 * rd ----- 13104 */ 13105 static char *SEH(uint64 instruction, Dis_info *info) 13106 { 13107 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13108 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13109 13110 const char *rt = GPR(rt_value, info); 13111 const char *rs = GPR(rs_value, info); 13112 13113 return img_format("SEH %s, %s", rt, rs); 13114 } 13115 13116 13117 /* 13118 * 13119 * 13120 * 3 2 1 13121 * 10987654321098765432109876543210 13122 * 001000 01001001101 13123 * rt ----- 13124 * rs ----- 13125 * rd ----- 13126 */ 13127 static char *SEL_D(uint64 instruction, Dis_info *info) 13128 { 13129 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 13130 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 13131 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 13132 13133 const char *fd = FPR(fd_value, info); 13134 const char *fs = FPR(fs_value, info); 13135 const char *ft = FPR(ft_value, info); 13136 13137 return img_format("SEL.D %s, %s, %s", fd, fs, ft); 13138 } 13139 13140 13141 /* 13142 * 13143 * 13144 * 3 2 1 13145 * 10987654321098765432109876543210 13146 * 001000 01001001101 13147 * rt ----- 13148 * rs ----- 13149 * rd ----- 13150 */ 13151 static char *SEL_S(uint64 instruction, Dis_info *info) 13152 { 13153 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 13154 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 13155 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 13156 13157 const char *fd = FPR(fd_value, info); 13158 const char *fs = FPR(fs_value, info); 13159 const char *ft = FPR(ft_value, info); 13160 13161 return img_format("SEL.S %s, %s, %s", fd, fs, ft); 13162 } 13163 13164 13165 /* 13166 * 13167 * 13168 * 3 2 1 13169 * 10987654321098765432109876543210 13170 * 001000 01001001101 13171 * rt ----- 13172 * rs ----- 13173 * rd ----- 13174 */ 13175 static char *SELEQZ_D(uint64 instruction, Dis_info *info) 13176 { 13177 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 13178 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 13179 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 13180 13181 const char *fd = FPR(fd_value, info); 13182 const char *fs = FPR(fs_value, info); 13183 const char *ft = FPR(ft_value, info); 13184 13185 return img_format("SELEQZ.D %s, %s, %s", fd, fs, ft); 13186 } 13187 13188 13189 /* 13190 * 13191 * 13192 * 3 2 1 13193 * 10987654321098765432109876543210 13194 * 001000 01001001101 13195 * rt ----- 13196 * rs ----- 13197 * rd ----- 13198 */ 13199 static char *SELEQZ_S(uint64 instruction, Dis_info *info) 13200 { 13201 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 13202 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 13203 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 13204 13205 const char *fd = FPR(fd_value, info); 13206 const char *fs = FPR(fs_value, info); 13207 const char *ft = FPR(ft_value, info); 13208 13209 return img_format("SELEQZ.S %s, %s, %s", fd, fs, ft); 13210 } 13211 13212 13213 /* 13214 * 13215 * 13216 * 3 2 1 13217 * 10987654321098765432109876543210 13218 * 001000 01001001101 13219 * rt ----- 13220 * rs ----- 13221 * rd ----- 13222 */ 13223 static char *SELNEZ_D(uint64 instruction, Dis_info *info) 13224 { 13225 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 13226 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 13227 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 13228 13229 const char *fd = FPR(fd_value, info); 13230 const char *fs = FPR(fs_value, info); 13231 const char *ft = FPR(ft_value, info); 13232 13233 return img_format("SELNEZ.D %s, %s, %s", fd, fs, ft); 13234 } 13235 13236 13237 /* 13238 * 13239 * 13240 * 3 2 1 13241 * 10987654321098765432109876543210 13242 * 001000 01001001101 13243 * rt ----- 13244 * rs ----- 13245 * rd ----- 13246 */ 13247 static char *SELNEZ_S(uint64 instruction, Dis_info *info) 13248 { 13249 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 13250 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 13251 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 13252 13253 const char *fd = FPR(fd_value, info); 13254 const char *fs = FPR(fs_value, info); 13255 const char *ft = FPR(ft_value, info); 13256 13257 return img_format("SELNEZ.S %s, %s, %s", fd, fs, ft); 13258 } 13259 13260 13261 /* 13262 * 13263 * 13264 * 3 2 1 13265 * 10987654321098765432109876543210 13266 * 001000 01001001101 13267 * rt ----- 13268 * rs ----- 13269 * rd ----- 13270 */ 13271 static char *SEQI(uint64 instruction, Dis_info *info) 13272 { 13273 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13274 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13275 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 13276 13277 const char *rt = GPR(rt_value, info); 13278 const char *rs = GPR(rs_value, info); 13279 13280 return img_format("SEQI %s, %s, 0x%" PRIx64, rt, rs, u_value); 13281 } 13282 13283 13284 /* 13285 * 13286 * 13287 * 3 2 1 13288 * 10987654321098765432109876543210 13289 * 001000 01001001101 13290 * rt ----- 13291 * rs ----- 13292 * rd ----- 13293 */ 13294 static char *SH_16_(uint64 instruction, Dis_info *info) 13295 { 13296 uint64 rtz3_value = extract_rtz3_9_8_7(instruction); 13297 uint64 rs3_value = extract_rs3_6_5_4(instruction); 13298 uint64 u_value = extract_u_2_1__s1(instruction); 13299 13300 const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info); 13301 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 13302 13303 return img_format("SH %s, 0x%" PRIx64 "(%s)", rtz3, u_value, rs3); 13304 } 13305 13306 13307 /* 13308 * 13309 * 13310 * 3 2 1 13311 * 10987654321098765432109876543210 13312 * 001000 01001001101 13313 * rt ----- 13314 * rs ----- 13315 * rd ----- 13316 */ 13317 static char *SH_GP_(uint64 instruction, Dis_info *info) 13318 { 13319 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13320 uint64 u_value = extract_u_17_to_1__s1(instruction); 13321 13322 const char *rt = GPR(rt_value, info); 13323 13324 return img_format("SH %s, 0x%" PRIx64 "($%d)", rt, u_value, 28); 13325 } 13326 13327 13328 /* 13329 * 13330 * 13331 * 3 2 1 13332 * 10987654321098765432109876543210 13333 * 001000 01001001101 13334 * rt ----- 13335 * rs ----- 13336 * rd ----- 13337 */ 13338 static char *SH_S9_(uint64 instruction, Dis_info *info) 13339 { 13340 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13341 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13342 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 13343 13344 const char *rt = GPR(rt_value, info); 13345 const char *rs = GPR(rs_value, info); 13346 13347 return img_format("SH %s, %" PRId64 "(%s)", rt, s_value, rs); 13348 } 13349 13350 13351 /* 13352 * 13353 * 13354 * 3 2 1 13355 * 10987654321098765432109876543210 13356 * 001000 01001001101 13357 * rt ----- 13358 * rs ----- 13359 * rd ----- 13360 */ 13361 static char *SH_U12_(uint64 instruction, Dis_info *info) 13362 { 13363 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13364 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13365 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 13366 13367 const char *rt = GPR(rt_value, info); 13368 const char *rs = GPR(rs_value, info); 13369 13370 return img_format("SH %s, 0x%" PRIx64 "(%s)", rt, u_value, rs); 13371 } 13372 13373 13374 /* 13375 * 13376 * 13377 * 3 2 1 13378 * 10987654321098765432109876543210 13379 * 001000 01001001101 13380 * rt ----- 13381 * rs ----- 13382 * rd ----- 13383 */ 13384 static char *SHE(uint64 instruction, Dis_info *info) 13385 { 13386 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13387 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13388 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 13389 13390 const char *rt = GPR(rt_value, info); 13391 const char *rs = GPR(rs_value, info); 13392 13393 return img_format("SHE %s, %" PRId64 "(%s)", rt, s_value, rs); 13394 } 13395 13396 13397 /* 13398 * [DSP] SHILO ac, shift - Shift an accumulator value leaving the result in 13399 * the same accumulator 13400 * 13401 * 3 2 1 13402 * 10987654321098765432109876543210 13403 * 001000xxxx xxxx0000011101 13404 * shift ------ 13405 * ac -- 13406 */ 13407 static char *SHILO(uint64 instruction, Dis_info *info) 13408 { 13409 int64 shift_value = extract_shift__se5_21_20_19_18_17_16(instruction); 13410 uint64 ac_value = extract_ac_15_14(instruction); 13411 13412 const char *ac = AC(ac_value, info); 13413 13414 return img_format("SHILO %s, 0x%" PRIx64, ac, shift_value); 13415 } 13416 13417 13418 /* 13419 * [DSP] SHILOV ac, rs - Variable shift of accumulator value leaving the result 13420 * in the same accumulator 13421 * 13422 * 3 2 1 13423 * 10987654321098765432109876543210 13424 * 001000xxxxx 01001001111111 13425 * rs ----- 13426 * ac -- 13427 */ 13428 static char *SHILOV(uint64 instruction, Dis_info *info) 13429 { 13430 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13431 uint64 ac_value = extract_ac_15_14(instruction); 13432 13433 const char *rs = GPR(rs_value, info); 13434 const char *ac = AC(ac_value, info); 13435 13436 return img_format("SHILOV %s, %s", ac, rs); 13437 } 13438 13439 13440 /* 13441 * [DSP] SHLL.PH rt, rs, sa - Shift left logical vector pair halfwords 13442 * 13443 * 3 2 1 13444 * 10987654321098765432109876543210 13445 * 001000 001110110101 13446 * rt ----- 13447 * rs ----- 13448 * sa ---- 13449 */ 13450 static char *SHLL_PH(uint64 instruction, Dis_info *info) 13451 { 13452 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13453 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13454 uint64 sa_value = extract_sa_15_14_13_12(instruction); 13455 13456 const char *rt = GPR(rt_value, info); 13457 const char *rs = GPR(rs_value, info); 13458 13459 return img_format("SHLL.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value); 13460 } 13461 13462 13463 /* 13464 * [DSP] SHLL.QB rt, rs, sa - Shift left logical vector quad bytes 13465 * 13466 * 3 2 1 13467 * 10987654321098765432109876543210 13468 * 001000 0100001111111 13469 * rt ----- 13470 * rs ----- 13471 * sa --- 13472 */ 13473 static char *SHLL_QB(uint64 instruction, Dis_info *info) 13474 { 13475 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13476 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13477 uint64 sa_value = extract_sa_15_14_13(instruction); 13478 13479 const char *rt = GPR(rt_value, info); 13480 const char *rs = GPR(rs_value, info); 13481 13482 return img_format("SHLL.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value); 13483 } 13484 13485 13486 /* 13487 * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical vector pair halfwords 13488 * with saturation 13489 * 13490 * 3 2 1 13491 * 10987654321098765432109876543210 13492 * 001000 001110110101 13493 * rt ----- 13494 * rs ----- 13495 * sa ---- 13496 */ 13497 static char *SHLL_S_PH(uint64 instruction, Dis_info *info) 13498 { 13499 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13500 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13501 uint64 sa_value = extract_sa_15_14_13_12(instruction); 13502 13503 const char *rt = GPR(rt_value, info); 13504 const char *rs = GPR(rs_value, info); 13505 13506 return img_format("SHLL_S.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value); 13507 } 13508 13509 13510 /* 13511 * [DSP] SHLL_S.PH rt, rs, sa - Shift left logical word with saturation 13512 * 13513 * 3 2 1 13514 * 10987654321098765432109876543210 13515 * 001000 x1111110101 13516 * rt ----- 13517 * rs ----- 13518 * sa ----- 13519 */ 13520 static char *SHLL_S_W(uint64 instruction, Dis_info *info) 13521 { 13522 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13523 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13524 uint64 sa_value = extract_sa_15_14_13_12_11(instruction); 13525 13526 const char *rt = GPR(rt_value, info); 13527 const char *rs = GPR(rs_value, info); 13528 13529 return img_format("SHLL_S.W %s, %s, 0x%" PRIx64, rt, rs, sa_value); 13530 } 13531 13532 13533 /* 13534 * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair 13535 * halfwords 13536 * 13537 * 3 2 1 13538 * 10987654321098765432109876543210 13539 * 001000 01110001101 13540 * rt ----- 13541 * rs ----- 13542 * rd ----- 13543 */ 13544 static char *SHLLV_PH(uint64 instruction, Dis_info *info) 13545 { 13546 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13547 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13548 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13549 13550 const char *rd = GPR(rd_value, info); 13551 const char *rt = GPR(rt_value, info); 13552 const char *rs = GPR(rs_value, info); 13553 13554 return img_format("SHLLV.PH %s, %s, %s", rd, rt, rs); 13555 } 13556 13557 13558 /* 13559 * [DSP] SHLLV_S.QB rd, rt, rs - Shift left logical variable vector quad bytes 13560 * 13561 * 3 2 1 13562 * 10987654321098765432109876543210 13563 * 001000 x1110010101 13564 * rt ----- 13565 * rs ----- 13566 * rd ----- 13567 */ 13568 static char *SHLLV_QB(uint64 instruction, Dis_info *info) 13569 { 13570 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13571 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13572 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13573 13574 const char *rd = GPR(rd_value, info); 13575 const char *rt = GPR(rt_value, info); 13576 const char *rs = GPR(rs_value, info); 13577 13578 return img_format("SHLLV.QB %s, %s, %s", rd, rt, rs); 13579 } 13580 13581 13582 /* 13583 * [DSP] SHLLV.PH rd, rt, rs - Shift left logical variable vector pair 13584 * halfwords with saturation 13585 * 13586 * 3 2 1 13587 * 10987654321098765432109876543210 13588 * 001000 11110001101 13589 * rt ----- 13590 * rs ----- 13591 * rd ----- 13592 */ 13593 static char *SHLLV_S_PH(uint64 instruction, Dis_info *info) 13594 { 13595 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13596 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13597 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13598 13599 const char *rd = GPR(rd_value, info); 13600 const char *rt = GPR(rt_value, info); 13601 const char *rs = GPR(rs_value, info); 13602 13603 return img_format("SHLLV_S.PH %s, %s, %s", rd, rt, rs); 13604 } 13605 13606 13607 /* 13608 * [DSP] SHLLV_S.W rd, rt, rs - Shift left logical variable vector word 13609 * 13610 * 3 2 1 13611 * 10987654321098765432109876543210 13612 * 001000 x1111010101 13613 * rt ----- 13614 * rs ----- 13615 * rd ----- 13616 */ 13617 static char *SHLLV_S_W(uint64 instruction, Dis_info *info) 13618 { 13619 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13620 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13621 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13622 13623 const char *rd = GPR(rd_value, info); 13624 const char *rt = GPR(rt_value, info); 13625 const char *rs = GPR(rs_value, info); 13626 13627 return img_format("SHLLV_S.W %s, %s, %s", rd, rt, rs); 13628 } 13629 13630 13631 /* 13632 * 13633 * 13634 * 3 2 1 13635 * 10987654321098765432109876543210 13636 * 001000 01001001101 13637 * rt ----- 13638 * rs ----- 13639 * rd ----- 13640 */ 13641 static char *SHRA_PH(uint64 instruction, Dis_info *info) 13642 { 13643 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13644 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13645 uint64 sa_value = extract_sa_15_14_13_12(instruction); 13646 13647 const char *rt = GPR(rt_value, info); 13648 const char *rs = GPR(rs_value, info); 13649 13650 return img_format("SHRA.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value); 13651 } 13652 13653 13654 /* 13655 * 13656 * 13657 * 3 2 1 13658 * 10987654321098765432109876543210 13659 * 001000 01001001101 13660 * rt ----- 13661 * rs ----- 13662 * rd ----- 13663 */ 13664 static char *SHRA_QB(uint64 instruction, Dis_info *info) 13665 { 13666 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13667 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13668 uint64 sa_value = extract_sa_15_14_13(instruction); 13669 13670 const char *rt = GPR(rt_value, info); 13671 const char *rs = GPR(rs_value, info); 13672 13673 return img_format("SHRA.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value); 13674 } 13675 13676 13677 /* 13678 * 13679 * 13680 * 3 2 1 13681 * 10987654321098765432109876543210 13682 * 001000 01001001101 13683 * rt ----- 13684 * rs ----- 13685 * rd ----- 13686 */ 13687 static char *SHRA_R_PH(uint64 instruction, Dis_info *info) 13688 { 13689 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13690 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13691 uint64 sa_value = extract_sa_15_14_13_12(instruction); 13692 13693 const char *rt = GPR(rt_value, info); 13694 const char *rs = GPR(rs_value, info); 13695 13696 return img_format("SHRA_R.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value); 13697 } 13698 13699 13700 /* 13701 * 13702 * 13703 * 3 2 1 13704 * 10987654321098765432109876543210 13705 * 001000 01001001101 13706 * rt ----- 13707 * rs ----- 13708 * rd ----- 13709 */ 13710 static char *SHRA_R_QB(uint64 instruction, Dis_info *info) 13711 { 13712 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13713 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13714 uint64 sa_value = extract_sa_15_14_13(instruction); 13715 13716 const char *rt = GPR(rt_value, info); 13717 const char *rs = GPR(rs_value, info); 13718 13719 return img_format("SHRA_R.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value); 13720 } 13721 13722 13723 /* 13724 * 13725 * 13726 * 3 2 1 13727 * 10987654321098765432109876543210 13728 * 001000 01001001101 13729 * rt ----- 13730 * rs ----- 13731 * rd ----- 13732 */ 13733 static char *SHRA_R_W(uint64 instruction, Dis_info *info) 13734 { 13735 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13736 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13737 uint64 sa_value = extract_sa_15_14_13_12_11(instruction); 13738 13739 const char *rt = GPR(rt_value, info); 13740 const char *rs = GPR(rs_value, info); 13741 13742 return img_format("SHRA_R.W %s, %s, 0x%" PRIx64, rt, rs, sa_value); 13743 } 13744 13745 13746 /* 13747 * 13748 * 13749 * 3 2 1 13750 * 10987654321098765432109876543210 13751 * 001000 01001001101 13752 * rt ----- 13753 * rs ----- 13754 * rd ----- 13755 */ 13756 static char *SHRAV_PH(uint64 instruction, Dis_info *info) 13757 { 13758 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13759 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13760 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13761 13762 const char *rd = GPR(rd_value, info); 13763 const char *rt = GPR(rt_value, info); 13764 const char *rs = GPR(rs_value, info); 13765 13766 return img_format("SHRAV.PH %s, %s, %s", rd, rt, rs); 13767 } 13768 13769 13770 /* 13771 * 13772 * 13773 * 3 2 1 13774 * 10987654321098765432109876543210 13775 * 001000 01001001101 13776 * rt ----- 13777 * rs ----- 13778 * rd ----- 13779 */ 13780 static char *SHRAV_QB(uint64 instruction, Dis_info *info) 13781 { 13782 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13783 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13784 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13785 13786 const char *rd = GPR(rd_value, info); 13787 const char *rt = GPR(rt_value, info); 13788 const char *rs = GPR(rs_value, info); 13789 13790 return img_format("SHRAV.QB %s, %s, %s", rd, rt, rs); 13791 } 13792 13793 13794 /* 13795 * 13796 * 13797 * 3 2 1 13798 * 10987654321098765432109876543210 13799 * 001000 01001001101 13800 * rt ----- 13801 * rs ----- 13802 * rd ----- 13803 */ 13804 static char *SHRAV_R_PH(uint64 instruction, Dis_info *info) 13805 { 13806 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13807 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13808 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13809 13810 const char *rd = GPR(rd_value, info); 13811 const char *rt = GPR(rt_value, info); 13812 const char *rs = GPR(rs_value, info); 13813 13814 return img_format("SHRAV_R.PH %s, %s, %s", rd, rt, rs); 13815 } 13816 13817 13818 /* 13819 * 13820 * 13821 * 3 2 1 13822 * 10987654321098765432109876543210 13823 * 001000 01001001101 13824 * rt ----- 13825 * rs ----- 13826 * rd ----- 13827 */ 13828 static char *SHRAV_R_QB(uint64 instruction, Dis_info *info) 13829 { 13830 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13831 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13832 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13833 13834 const char *rd = GPR(rd_value, info); 13835 const char *rt = GPR(rt_value, info); 13836 const char *rs = GPR(rs_value, info); 13837 13838 return img_format("SHRAV_R.QB %s, %s, %s", rd, rt, rs); 13839 } 13840 13841 13842 /* 13843 * 13844 * 13845 * 3 2 1 13846 * 10987654321098765432109876543210 13847 * 001000 01001001101 13848 * rt ----- 13849 * rs ----- 13850 * rd ----- 13851 */ 13852 static char *SHRAV_R_W(uint64 instruction, Dis_info *info) 13853 { 13854 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13855 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13856 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13857 13858 const char *rd = GPR(rd_value, info); 13859 const char *rt = GPR(rt_value, info); 13860 const char *rs = GPR(rs_value, info); 13861 13862 return img_format("SHRAV_R.W %s, %s, %s", rd, rt, rs); 13863 } 13864 13865 13866 /* 13867 * [DSP] SHRL.PH rt, rs, sa - Shift right logical two halfwords 13868 * 13869 * 3 2 1 13870 * 10987654321098765432109876543210 13871 * 001000 001111111111 13872 * rt ----- 13873 * rs ----- 13874 * sa ---- 13875 */ 13876 static char *SHRL_PH(uint64 instruction, Dis_info *info) 13877 { 13878 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13879 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13880 uint64 sa_value = extract_sa_15_14_13_12(instruction); 13881 13882 const char *rt = GPR(rt_value, info); 13883 const char *rs = GPR(rs_value, info); 13884 13885 return img_format("SHRL.PH %s, %s, 0x%" PRIx64, rt, rs, sa_value); 13886 } 13887 13888 13889 /* 13890 * [DSP] SHRL.QB rt, rs, sa - Shift right logical vector quad bytes 13891 * 13892 * 3 2 1 13893 * 10987654321098765432109876543210 13894 * 001000 1100001111111 13895 * rt ----- 13896 * rs ----- 13897 * sa --- 13898 */ 13899 static char *SHRL_QB(uint64 instruction, Dis_info *info) 13900 { 13901 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13902 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13903 uint64 sa_value = extract_sa_15_14_13(instruction); 13904 13905 const char *rt = GPR(rt_value, info); 13906 const char *rs = GPR(rs_value, info); 13907 13908 return img_format("SHRL.QB %s, %s, 0x%" PRIx64, rt, rs, sa_value); 13909 } 13910 13911 13912 /* 13913 * [DSP] SHLLV.PH rd, rt, rs - Shift right logical variable vector pair of 13914 * halfwords 13915 * 13916 * 3 2 1 13917 * 10987654321098765432109876543210 13918 * 001000 x1100010101 13919 * rt ----- 13920 * rs ----- 13921 * rd ----- 13922 */ 13923 static char *SHRLV_PH(uint64 instruction, Dis_info *info) 13924 { 13925 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13926 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13927 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13928 13929 const char *rd = GPR(rd_value, info); 13930 const char *rt = GPR(rt_value, info); 13931 const char *rs = GPR(rs_value, info); 13932 13933 return img_format("SHRLV.PH %s, %s, %s", rd, rt, rs); 13934 } 13935 13936 13937 /* 13938 * [DSP] SHLLV.QB rd, rt, rs - Shift right logical variable vector quad bytes 13939 * 13940 * 3 2 1 13941 * 10987654321098765432109876543210 13942 * 001000 x1101010101 13943 * rt ----- 13944 * rs ----- 13945 * rd ----- 13946 */ 13947 static char *SHRLV_QB(uint64 instruction, Dis_info *info) 13948 { 13949 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13950 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13951 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13952 13953 const char *rd = GPR(rd_value, info); 13954 const char *rt = GPR(rt_value, info); 13955 const char *rs = GPR(rs_value, info); 13956 13957 return img_format("SHRLV.QB %s, %s, %s", rd, rt, rs); 13958 } 13959 13960 13961 /* 13962 * 13963 * 13964 * 3 2 1 13965 * 10987654321098765432109876543210 13966 * 001000 01001001101 13967 * rt ----- 13968 * rs ----- 13969 * rd ----- 13970 */ 13971 static char *SHX(uint64 instruction, Dis_info *info) 13972 { 13973 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13974 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13975 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 13976 13977 const char *rd = GPR(rd_value, info); 13978 const char *rs = GPR(rs_value, info); 13979 const char *rt = GPR(rt_value, info); 13980 13981 return img_format("SHX %s, %s(%s)", rd, rs, rt); 13982 } 13983 13984 13985 /* 13986 * 13987 * 13988 * 3 2 1 13989 * 10987654321098765432109876543210 13990 * 001000 01001001101 13991 * rt ----- 13992 * rs ----- 13993 * rd ----- 13994 */ 13995 static char *SHXS(uint64 instruction, Dis_info *info) 13996 { 13997 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 13998 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 13999 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14000 14001 const char *rd = GPR(rd_value, info); 14002 const char *rs = GPR(rs_value, info); 14003 const char *rt = GPR(rt_value, info); 14004 14005 return img_format("SHXS %s, %s(%s)", rd, rs, rt); 14006 } 14007 14008 14009 /* 14010 * 14011 * 14012 * 3 2 1 14013 * 10987654321098765432109876543210 14014 * 001000 01001001101 14015 * rt ----- 14016 * rs ----- 14017 * rd ----- 14018 */ 14019 static char *SIGRIE(uint64 instruction, Dis_info *info) 14020 { 14021 uint64 code_value = extract_code_18_to_0(instruction); 14022 14023 14024 return img_format("SIGRIE 0x%" PRIx64, code_value); 14025 } 14026 14027 14028 /* 14029 * 14030 * 14031 * 3 2 1 14032 * 10987654321098765432109876543210 14033 * 001000 01001001101 14034 * rt ----- 14035 * rs ----- 14036 * rd ----- 14037 */ 14038 static char *SLL_16_(uint64 instruction, Dis_info *info) 14039 { 14040 uint64 rt3_value = extract_rt3_9_8_7(instruction); 14041 uint64 rs3_value = extract_rs3_6_5_4(instruction); 14042 uint64 shift3_value = extract_shift3_2_1_0(instruction); 14043 14044 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 14045 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 14046 uint64 shift3 = encode_shift3_from_shift(shift3_value); 14047 14048 return img_format("SLL %s, %s, 0x%" PRIx64, rt3, rs3, shift3); 14049 } 14050 14051 14052 /* 14053 * 14054 * 14055 * 3 2 1 14056 * 10987654321098765432109876543210 14057 * 001000 01001001101 14058 * rt ----- 14059 * rs ----- 14060 * rd ----- 14061 */ 14062 static char *SLL_32_(uint64 instruction, Dis_info *info) 14063 { 14064 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14065 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14066 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 14067 14068 const char *rt = GPR(rt_value, info); 14069 const char *rs = GPR(rs_value, info); 14070 14071 return img_format("SLL %s, %s, 0x%" PRIx64, rt, rs, shift_value); 14072 } 14073 14074 14075 /* 14076 * 14077 * 14078 * 3 2 1 14079 * 10987654321098765432109876543210 14080 * 001000 01001001101 14081 * rt ----- 14082 * rs ----- 14083 * rd ----- 14084 */ 14085 static char *SLLV(uint64 instruction, Dis_info *info) 14086 { 14087 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14088 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14089 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14090 14091 const char *rd = GPR(rd_value, info); 14092 const char *rs = GPR(rs_value, info); 14093 const char *rt = GPR(rt_value, info); 14094 14095 return img_format("SLLV %s, %s, %s", rd, rs, rt); 14096 } 14097 14098 14099 /* 14100 * 14101 * 14102 * 3 2 1 14103 * 10987654321098765432109876543210 14104 * 001000 01001001101 14105 * rt ----- 14106 * rs ----- 14107 * rd ----- 14108 */ 14109 static char *SLT(uint64 instruction, Dis_info *info) 14110 { 14111 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14112 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14113 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14114 14115 const char *rd = GPR(rd_value, info); 14116 const char *rs = GPR(rs_value, info); 14117 const char *rt = GPR(rt_value, info); 14118 14119 return img_format("SLT %s, %s, %s", rd, rs, rt); 14120 } 14121 14122 14123 /* 14124 * 14125 * 14126 * 3 2 1 14127 * 10987654321098765432109876543210 14128 * 001000 01001001101 14129 * rt ----- 14130 * rs ----- 14131 * rd ----- 14132 */ 14133 static char *SLTI(uint64 instruction, Dis_info *info) 14134 { 14135 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14136 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14137 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 14138 14139 const char *rt = GPR(rt_value, info); 14140 const char *rs = GPR(rs_value, info); 14141 14142 return img_format("SLTI %s, %s, 0x%" PRIx64, rt, rs, u_value); 14143 } 14144 14145 14146 /* 14147 * 14148 * 14149 * 3 2 1 14150 * 10987654321098765432109876543210 14151 * 001000 01001001101 14152 * rt ----- 14153 * rs ----- 14154 * rd ----- 14155 */ 14156 static char *SLTIU(uint64 instruction, Dis_info *info) 14157 { 14158 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14159 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14160 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 14161 14162 const char *rt = GPR(rt_value, info); 14163 const char *rs = GPR(rs_value, info); 14164 14165 return img_format("SLTIU %s, %s, 0x%" PRIx64, rt, rs, u_value); 14166 } 14167 14168 14169 /* 14170 * 14171 * 14172 * 3 2 1 14173 * 10987654321098765432109876543210 14174 * 001000 01001001101 14175 * rt ----- 14176 * rs ----- 14177 * rd ----- 14178 */ 14179 static char *SLTU(uint64 instruction, Dis_info *info) 14180 { 14181 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14182 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14183 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14184 14185 const char *rd = GPR(rd_value, info); 14186 const char *rs = GPR(rs_value, info); 14187 const char *rt = GPR(rt_value, info); 14188 14189 return img_format("SLTU %s, %s, %s", rd, rs, rt); 14190 } 14191 14192 14193 /* 14194 * 14195 * 14196 * 3 2 1 14197 * 10987654321098765432109876543210 14198 * 001000 01001001101 14199 * rt ----- 14200 * rs ----- 14201 * rd ----- 14202 */ 14203 static char *SOV(uint64 instruction, Dis_info *info) 14204 { 14205 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14206 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14207 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14208 14209 const char *rd = GPR(rd_value, info); 14210 const char *rs = GPR(rs_value, info); 14211 const char *rt = GPR(rt_value, info); 14212 14213 return img_format("SOV %s, %s, %s", rd, rs, rt); 14214 } 14215 14216 14217 /* 14218 * 14219 * 14220 * 3 2 1 14221 * 10987654321098765432109876543210 14222 * 001000 01001001101 14223 * rt ----- 14224 * rs ----- 14225 * rd ----- 14226 */ 14227 static char *SPECIAL2(uint64 instruction, Dis_info *info) 14228 { 14229 uint64 op_value = extract_op_25_to_3(instruction); 14230 14231 14232 return img_format("SPECIAL2 0x%" PRIx64, op_value); 14233 } 14234 14235 14236 /* 14237 * 14238 * 14239 * 3 2 1 14240 * 10987654321098765432109876543210 14241 * 001000 01001001101 14242 * rt ----- 14243 * rs ----- 14244 * rd ----- 14245 */ 14246 static char *SQRT_D(uint64 instruction, Dis_info *info) 14247 { 14248 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 14249 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 14250 14251 const char *ft = FPR(ft_value, info); 14252 const char *fs = FPR(fs_value, info); 14253 14254 return img_format("SQRT.D %s, %s", ft, fs); 14255 } 14256 14257 14258 /* 14259 * 14260 * 14261 * 3 2 1 14262 * 10987654321098765432109876543210 14263 * 001000 01001001101 14264 * rt ----- 14265 * rs ----- 14266 * rd ----- 14267 */ 14268 static char *SQRT_S(uint64 instruction, Dis_info *info) 14269 { 14270 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 14271 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 14272 14273 const char *ft = FPR(ft_value, info); 14274 const char *fs = FPR(fs_value, info); 14275 14276 return img_format("SQRT.S %s, %s", ft, fs); 14277 } 14278 14279 14280 /* 14281 * SRA rd, rt, sa - Shift Word Right Arithmetic 14282 * 14283 * 3 2 1 14284 * 10987654321098765432109876543210 14285 * 00000000000 000011 14286 * rt ----- 14287 * rd ----- 14288 * sa ----- 14289 */ 14290 static char *SRA(uint64 instruction, Dis_info *info) 14291 { 14292 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14293 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14294 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 14295 14296 const char *rt = GPR(rt_value, info); 14297 const char *rs = GPR(rs_value, info); 14298 14299 return img_format("SRA %s, %s, 0x%" PRIx64, rt, rs, shift_value); 14300 } 14301 14302 14303 /* 14304 * SRAV rd, rt, rs - Shift Word Right Arithmetic Variable 14305 * 14306 * 3 2 1 14307 * 10987654321098765432109876543210 14308 * 001000 00000000111 14309 * rs ----- 14310 * rt ----- 14311 * rd ----- 14312 */ 14313 static char *SRAV(uint64 instruction, Dis_info *info) 14314 { 14315 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14316 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14317 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14318 14319 const char *rd = GPR(rd_value, info); 14320 const char *rs = GPR(rs_value, info); 14321 const char *rt = GPR(rt_value, info); 14322 14323 return img_format("SRAV %s, %s, %s", rd, rs, rt); 14324 } 14325 14326 14327 /* 14328 * 14329 * 14330 * 3 2 1 14331 * 10987654321098765432109876543210 14332 * 001000 00000000111 14333 * rs ----- 14334 * rt ----- 14335 * rd ----- 14336 */ 14337 static char *SRL_16_(uint64 instruction, Dis_info *info) 14338 { 14339 uint64 rt3_value = extract_rt3_9_8_7(instruction); 14340 uint64 rs3_value = extract_rs3_6_5_4(instruction); 14341 uint64 shift3_value = extract_shift3_2_1_0(instruction); 14342 14343 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 14344 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 14345 uint64 shift3 = encode_shift3_from_shift(shift3_value); 14346 14347 return img_format("SRL %s, %s, 0x%" PRIx64, rt3, rs3, shift3); 14348 } 14349 14350 14351 /* 14352 * 14353 * 14354 * 3 2 1 14355 * 10987654321098765432109876543210 14356 * 001000 01001001101 14357 * rt ----- 14358 * rs ----- 14359 * rd ----- 14360 */ 14361 static char *SRL_32_(uint64 instruction, Dis_info *info) 14362 { 14363 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14364 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14365 uint64 shift_value = extract_shift_4_3_2_1_0(instruction); 14366 14367 const char *rt = GPR(rt_value, info); 14368 const char *rs = GPR(rs_value, info); 14369 14370 return img_format("SRL %s, %s, 0x%" PRIx64, rt, rs, shift_value); 14371 } 14372 14373 14374 /* 14375 * 14376 * 14377 * 3 2 1 14378 * 10987654321098765432109876543210 14379 * 001000 01001001101 14380 * rt ----- 14381 * rs ----- 14382 * rd ----- 14383 */ 14384 static char *SRLV(uint64 instruction, Dis_info *info) 14385 { 14386 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14387 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14388 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14389 14390 const char *rd = GPR(rd_value, info); 14391 const char *rs = GPR(rs_value, info); 14392 const char *rt = GPR(rt_value, info); 14393 14394 return img_format("SRLV %s, %s, %s", rd, rs, rt); 14395 } 14396 14397 14398 /* 14399 * 14400 * 14401 * 3 2 1 14402 * 10987654321098765432109876543210 14403 * 001000 01001001101 14404 * rt ----- 14405 * rs ----- 14406 * rd ----- 14407 */ 14408 static char *SUB(uint64 instruction, Dis_info *info) 14409 { 14410 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14411 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14412 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14413 14414 const char *rd = GPR(rd_value, info); 14415 const char *rs = GPR(rs_value, info); 14416 const char *rt = GPR(rt_value, info); 14417 14418 return img_format("SUB %s, %s, %s", rd, rs, rt); 14419 } 14420 14421 14422 /* 14423 * 14424 * 14425 * 3 2 1 14426 * 10987654321098765432109876543210 14427 * 001000 01001001101 14428 * rt ----- 14429 * rs ----- 14430 * rd ----- 14431 */ 14432 static char *SUB_D(uint64 instruction, Dis_info *info) 14433 { 14434 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 14435 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 14436 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 14437 14438 const char *fd = FPR(fd_value, info); 14439 const char *fs = FPR(fs_value, info); 14440 const char *ft = FPR(ft_value, info); 14441 14442 return img_format("SUB.D %s, %s, %s", fd, fs, ft); 14443 } 14444 14445 14446 /* 14447 * 14448 * 14449 * 3 2 1 14450 * 10987654321098765432109876543210 14451 * 001000 01001001101 14452 * rt ----- 14453 * rs ----- 14454 * rd ----- 14455 */ 14456 static char *SUB_S(uint64 instruction, Dis_info *info) 14457 { 14458 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 14459 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 14460 uint64 fd_value = extract_fd_15_14_13_12_11(instruction); 14461 14462 const char *fd = FPR(fd_value, info); 14463 const char *fs = FPR(fs_value, info); 14464 const char *ft = FPR(ft_value, info); 14465 14466 return img_format("SUB.S %s, %s, %s", fd, fs, ft); 14467 } 14468 14469 14470 /* 14471 * 14472 * 14473 * 3 2 1 14474 * 10987654321098765432109876543210 14475 * 001000 01001001101 14476 * rt ----- 14477 * rs ----- 14478 * rd ----- 14479 */ 14480 static char *SUBQ_PH(uint64 instruction, Dis_info *info) 14481 { 14482 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14483 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14484 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14485 14486 const char *rd = GPR(rd_value, info); 14487 const char *rs = GPR(rs_value, info); 14488 const char *rt = GPR(rt_value, info); 14489 14490 return img_format("SUBQ.PH %s, %s, %s", rd, rs, rt); 14491 } 14492 14493 14494 /* 14495 * [DSP] SUBQ.S.PH rd, rt, rs - Subtract fractional halfword vectors and shift 14496 * right to halve results 14497 * 14498 * 3 2 1 14499 * 10987654321098765432109876543210 14500 * 001000 01001001101 14501 * rt ----- 14502 * rs ----- 14503 * rd ----- 14504 */ 14505 static char *SUBQ_S_PH(uint64 instruction, Dis_info *info) 14506 { 14507 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14508 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14509 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14510 14511 const char *rd = GPR(rd_value, info); 14512 const char *rs = GPR(rs_value, info); 14513 const char *rt = GPR(rt_value, info); 14514 14515 return img_format("SUBQ_S.PH %s, %s, %s", rd, rs, rt); 14516 } 14517 14518 14519 /* 14520 * [DSP] SUBQ.S.W rd, rt, rs - Subtract fractional halfword vectors and shift 14521 * right to halve results 14522 * 14523 * 3 2 1 14524 * 10987654321098765432109876543210 14525 * 001000 01001001101 14526 * rt ----- 14527 * rs ----- 14528 * rd ----- 14529 */ 14530 static char *SUBQ_S_W(uint64 instruction, Dis_info *info) 14531 { 14532 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14533 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14534 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14535 14536 const char *rd = GPR(rd_value, info); 14537 const char *rs = GPR(rs_value, info); 14538 const char *rt = GPR(rt_value, info); 14539 14540 return img_format("SUBQ_S.W %s, %s, %s", rd, rs, rt); 14541 } 14542 14543 14544 /* 14545 * [DSP] SUBQH.PH rd, rt, rs - Subtract fractional halfword vectors and shift 14546 * right to halve results 14547 * 14548 * 3 2 1 14549 * 10987654321098765432109876543210 14550 * 001000 01001001101 14551 * rt ----- 14552 * rs ----- 14553 * rd ----- 14554 */ 14555 static char *SUBQH_PH(uint64 instruction, Dis_info *info) 14556 { 14557 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14558 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14559 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14560 14561 const char *rd = GPR(rd_value, info); 14562 const char *rs = GPR(rs_value, info); 14563 const char *rt = GPR(rt_value, info); 14564 14565 return img_format("SUBQH.PH %s, %s, %s", rd, rs, rt); 14566 } 14567 14568 14569 /* 14570 * [DSP] SUBQH_R.PH rd, rt, rs - Subtract fractional halfword vectors and shift 14571 * right to halve results 14572 * 14573 * 3 2 1 14574 * 10987654321098765432109876543210 14575 * 001000 01001001101 14576 * rt ----- 14577 * rs ----- 14578 * rd ----- 14579 */ 14580 static char *SUBQH_R_PH(uint64 instruction, Dis_info *info) 14581 { 14582 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14583 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14584 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14585 14586 const char *rd = GPR(rd_value, info); 14587 const char *rs = GPR(rs_value, info); 14588 const char *rt = GPR(rt_value, info); 14589 14590 return img_format("SUBQH_R.PH %s, %s, %s", rd, rs, rt); 14591 } 14592 14593 14594 /* 14595 * [DSP] SUBQH_R.W rd, rt, rs - Subtract fractional halfword vectors and shift 14596 * right to halve results with rounding 14597 * 14598 * 3 2 1 14599 * 10987654321098765432109876543210 14600 * 001000 11001001101 14601 * rt ----- 14602 * rs ----- 14603 * rd ----- 14604 */ 14605 static char *SUBQH_R_W(uint64 instruction, Dis_info *info) 14606 { 14607 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14608 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14609 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14610 14611 const char *rd = GPR(rd_value, info); 14612 const char *rs = GPR(rs_value, info); 14613 const char *rt = GPR(rt_value, info); 14614 14615 return img_format("SUBQH_R.W %s, %s, %s", rd, rs, rt); 14616 } 14617 14618 14619 /* 14620 * [DSP] SUBQH.W rd, rs, rt - Subtract fractional words and shift right to 14621 * halve results 14622 * 14623 * 3 2 1 14624 * 10987654321098765432109876543210 14625 * 001000 01010001101 14626 * rt ----- 14627 * rs ----- 14628 * rd ----- 14629 */ 14630 static char *SUBQH_W(uint64 instruction, Dis_info *info) 14631 { 14632 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14633 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14634 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14635 14636 const char *rd = GPR(rd_value, info); 14637 const char *rs = GPR(rs_value, info); 14638 const char *rt = GPR(rt_value, info); 14639 14640 return img_format("SUBQH.W %s, %s, %s", rd, rs, rt); 14641 } 14642 14643 14644 /* 14645 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 14646 * 14647 * 3 2 1 14648 * 10987654321098765432109876543210 14649 * 001000 00010001101 14650 * rt ----- 14651 * rs ----- 14652 * rd ----- 14653 */ 14654 static char *SUBU_16_(uint64 instruction, Dis_info *info) 14655 { 14656 uint64 rt3_value = extract_rt3_9_8_7(instruction); 14657 uint64 rs3_value = extract_rs3_6_5_4(instruction); 14658 uint64 rd3_value = extract_rd3_3_2_1(instruction); 14659 14660 const char *rd3 = GPR(decode_gpr_gpr3(rd3_value, info), info); 14661 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 14662 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 14663 14664 return img_format("SUBU %s, %s, %s", rd3, rs3, rt3); 14665 } 14666 14667 14668 /* 14669 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 14670 * 14671 * 3 2 1 14672 * 10987654321098765432109876543210 14673 * 001000 00010001101 14674 * rt ----- 14675 * rs ----- 14676 * rd ----- 14677 */ 14678 static char *SUBU_32_(uint64 instruction, Dis_info *info) 14679 { 14680 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14681 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14682 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14683 14684 const char *rd = GPR(rd_value, info); 14685 const char *rs = GPR(rs_value, info); 14686 const char *rt = GPR(rt_value, info); 14687 14688 return img_format("SUBU %s, %s, %s", rd, rs, rt); 14689 } 14690 14691 14692 /* 14693 * [DSP] SUBU.PH rd, rs, rt - Subtract unsigned unsigned halfwords 14694 * 14695 * 3 2 1 14696 * 10987654321098765432109876543210 14697 * 001000 01100001101 14698 * rt ----- 14699 * rs ----- 14700 * rd ----- 14701 */ 14702 static char *SUBU_PH(uint64 instruction, Dis_info *info) 14703 { 14704 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14705 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14706 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14707 14708 const char *rd = GPR(rd_value, info); 14709 const char *rs = GPR(rs_value, info); 14710 const char *rt = GPR(rt_value, info); 14711 14712 return img_format("SUBU.PH %s, %s, %s", rd, rs, rt); 14713 } 14714 14715 14716 /* 14717 * [DSP] SUBU.QB rd, rs, rt - Subtract unsigned quad byte vectors 14718 * 14719 * 3 2 1 14720 * 10987654321098765432109876543210 14721 * 001000 01011001101 14722 * rt ----- 14723 * rs ----- 14724 * rd ----- 14725 */ 14726 static char *SUBU_QB(uint64 instruction, Dis_info *info) 14727 { 14728 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14729 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14730 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14731 14732 const char *rd = GPR(rd_value, info); 14733 const char *rs = GPR(rs_value, info); 14734 const char *rt = GPR(rt_value, info); 14735 14736 return img_format("SUBU.QB %s, %s, %s", rd, rs, rt); 14737 } 14738 14739 14740 /* 14741 * [DSP] SUBU_S.PH rd, rs, rt - Subtract unsigned unsigned halfwords with 14742 * 8-bit saturation 14743 * 14744 * 3 2 1 14745 * 10987654321098765432109876543210 14746 * 001000 11100001101 14747 * rt ----- 14748 * rs ----- 14749 * rd ----- 14750 */ 14751 static char *SUBU_S_PH(uint64 instruction, Dis_info *info) 14752 { 14753 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14754 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14755 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14756 14757 const char *rd = GPR(rd_value, info); 14758 const char *rs = GPR(rs_value, info); 14759 const char *rt = GPR(rt_value, info); 14760 14761 return img_format("SUBU_S.PH %s, %s, %s", rd, rs, rt); 14762 } 14763 14764 14765 /* 14766 * [DSP] SUBU_S.QB rd, rs, rt - Subtract unsigned quad byte vectors with 14767 * 8-bit saturation 14768 * 14769 * 3 2 1 14770 * 10987654321098765432109876543210 14771 * 001000 11011001101 14772 * rt ----- 14773 * rs ----- 14774 * rd ----- 14775 */ 14776 static char *SUBU_S_QB(uint64 instruction, Dis_info *info) 14777 { 14778 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14779 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14780 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14781 14782 const char *rd = GPR(rd_value, info); 14783 const char *rs = GPR(rs_value, info); 14784 const char *rt = GPR(rt_value, info); 14785 14786 return img_format("SUBU_S.QB %s, %s, %s", rd, rs, rt); 14787 } 14788 14789 14790 /* 14791 * [DSP] SUBUH.QB rd, rs, rt - Subtract unsigned bytes and right shift 14792 * to halve results 14793 * 14794 * 3 2 1 14795 * 10987654321098765432109876543210 14796 * 001000 01101001101 14797 * rt ----- 14798 * rs ----- 14799 * rd ----- 14800 */ 14801 static char *SUBUH_QB(uint64 instruction, Dis_info *info) 14802 { 14803 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14804 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14805 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14806 14807 const char *rd = GPR(rd_value, info); 14808 const char *rs = GPR(rs_value, info); 14809 const char *rt = GPR(rt_value, info); 14810 14811 return img_format("SUBUH.QB %s, %s, %s", rd, rs, rt); 14812 } 14813 14814 14815 /* 14816 * [DSP] SUBUH_R.QB rd, rs, rt - Subtract unsigned bytes and right shift 14817 * to halve results with rounding 14818 * 14819 * 3 2 1 14820 * 10987654321098765432109876543210 14821 * 001000 11101001101 14822 * rt ----- 14823 * rs ----- 14824 * rd ----- 14825 */ 14826 static char *SUBUH_R_QB(uint64 instruction, Dis_info *info) 14827 { 14828 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14829 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14830 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 14831 14832 const char *rd = GPR(rd_value, info); 14833 const char *rs = GPR(rs_value, info); 14834 const char *rt = GPR(rt_value, info); 14835 14836 return img_format("SUBUH_R.QB %s, %s, %s", rd, rs, rt); 14837 } 14838 14839 14840 /* 14841 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 14842 * 14843 * 3 2 1 14844 * 10987654321098765432109876543210 14845 * 001000 00010001101 14846 * rt ----- 14847 * rs ----- 14848 * rd ----- 14849 */ 14850 static char *SW_16_(uint64 instruction, Dis_info *info) 14851 { 14852 uint64 rtz3_value = extract_rtz3_9_8_7(instruction); 14853 uint64 rs3_value = extract_rs3_6_5_4(instruction); 14854 uint64 u_value = extract_u_3_2_1_0__s2(instruction); 14855 14856 const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info); 14857 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 14858 14859 return img_format("SW %s, 0x%" PRIx64 "(%s)", rtz3, u_value, rs3); 14860 } 14861 14862 14863 /* 14864 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 14865 * 14866 * 3 2 1 14867 * 10987654321098765432109876543210 14868 * 001000 00010001101 14869 * rt ----- 14870 * rs ----- 14871 * rd ----- 14872 */ 14873 static char *SW_4X4_(uint64 instruction, Dis_info *info) 14874 { 14875 uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction); 14876 uint64 rs4_value = extract_rs4_4_2_1_0(instruction); 14877 uint64 u_value = extract_u_3_8__s2(instruction); 14878 14879 const char *rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value, info), info); 14880 const char *rs4 = GPR(decode_gpr_gpr4(rs4_value, info), info); 14881 14882 return img_format("SW %s, 0x%" PRIx64 "(%s)", rtz4, u_value, rs4); 14883 } 14884 14885 14886 /* 14887 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 14888 * 14889 * 3 2 1 14890 * 10987654321098765432109876543210 14891 * 001000 00010001101 14892 * rt ----- 14893 * rs ----- 14894 * rd ----- 14895 */ 14896 static char *SW_GP16_(uint64 instruction, Dis_info *info) 14897 { 14898 uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction); 14899 uint64 rtz3_value = extract_rtz3_9_8_7(instruction); 14900 14901 const char *rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value, info), info); 14902 14903 return img_format("SW %s, 0x%" PRIx64 "($%d)", rtz3, u_value, 28); 14904 } 14905 14906 14907 /* 14908 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 14909 * 14910 * 3 2 1 14911 * 10987654321098765432109876543210 14912 * 001000 00010001101 14913 * rt ----- 14914 * rs ----- 14915 * rd ----- 14916 */ 14917 static char *SW_GP_(uint64 instruction, Dis_info *info) 14918 { 14919 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14920 uint64 u_value = extract_u_20_to_2__s2(instruction); 14921 14922 const char *rt = GPR(rt_value, info); 14923 14924 return img_format("SW %s, 0x%" PRIx64 "($%d)", rt, u_value, 28); 14925 } 14926 14927 14928 /* 14929 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 14930 * 14931 * 3 2 1 14932 * 10987654321098765432109876543210 14933 * 001000 00010001101 14934 * rt ----- 14935 * rs ----- 14936 * rd ----- 14937 */ 14938 static char *SW_S9_(uint64 instruction, Dis_info *info) 14939 { 14940 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14941 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 14942 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14943 14944 const char *rt = GPR(rt_value, info); 14945 const char *rs = GPR(rs_value, info); 14946 14947 return img_format("SW %s, %" PRId64 "(%s)", rt, s_value, rs); 14948 } 14949 14950 14951 /* 14952 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 14953 * 14954 * 3 2 1 14955 * 10987654321098765432109876543210 14956 * 001000 00010001101 14957 * rt ----- 14958 * rs ----- 14959 * rd ----- 14960 */ 14961 static char *SW_SP_(uint64 instruction, Dis_info *info) 14962 { 14963 uint64 rt_value = extract_rt_9_8_7_6_5(instruction); 14964 uint64 u_value = extract_u_4_3_2_1_0__s2(instruction); 14965 14966 const char *rt = GPR(rt_value, info); 14967 14968 return img_format("SW %s, 0x%" PRIx64 "($%d)", rt, u_value, 29); 14969 } 14970 14971 14972 /* 14973 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 14974 * 14975 * 3 2 1 14976 * 10987654321098765432109876543210 14977 * 001000 00010001101 14978 * rt ----- 14979 * rs ----- 14980 * rd ----- 14981 */ 14982 static char *SW_U12_(uint64 instruction, Dis_info *info) 14983 { 14984 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 14985 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 14986 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 14987 14988 const char *rt = GPR(rt_value, info); 14989 const char *rs = GPR(rs_value, info); 14990 14991 return img_format("SW %s, 0x%" PRIx64 "(%s)", rt, u_value, rs); 14992 } 14993 14994 14995 /* 14996 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 14997 * 14998 * 3 2 1 14999 * 10987654321098765432109876543210 15000 * 001000 00010001101 15001 * rt ----- 15002 * rs ----- 15003 * rd ----- 15004 */ 15005 static char *SWC1_GP_(uint64 instruction, Dis_info *info) 15006 { 15007 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 15008 uint64 u_value = extract_u_17_to_2__s2(instruction); 15009 15010 const char *ft = FPR(ft_value, info); 15011 15012 return img_format("SWC1 %s, 0x%" PRIx64 "($%d)", ft, u_value, 28); 15013 } 15014 15015 15016 /* 15017 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15018 * 15019 * 3 2 1 15020 * 10987654321098765432109876543210 15021 * 001000 00010001101 15022 * rt ----- 15023 * rs ----- 15024 * rd ----- 15025 */ 15026 static char *SWC1_S9_(uint64 instruction, Dis_info *info) 15027 { 15028 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 15029 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15030 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15031 15032 const char *ft = FPR(ft_value, info); 15033 const char *rs = GPR(rs_value, info); 15034 15035 return img_format("SWC1 %s, %" PRId64 "(%s)", ft, s_value, rs); 15036 } 15037 15038 15039 /* 15040 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15041 * 15042 * 3 2 1 15043 * 10987654321098765432109876543210 15044 * 001000 00010001101 15045 * rt ----- 15046 * rs ----- 15047 * rd ----- 15048 */ 15049 static char *SWC1_U12_(uint64 instruction, Dis_info *info) 15050 { 15051 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 15052 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15053 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 15054 15055 const char *ft = FPR(ft_value, info); 15056 const char *rs = GPR(rs_value, info); 15057 15058 return img_format("SWC1 %s, 0x%" PRIx64 "(%s)", ft, u_value, rs); 15059 } 15060 15061 15062 /* 15063 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15064 * 15065 * 3 2 1 15066 * 10987654321098765432109876543210 15067 * 001000 00010001101 15068 * rt ----- 15069 * rs ----- 15070 * rd ----- 15071 */ 15072 static char *SWC1X(uint64 instruction, Dis_info *info) 15073 { 15074 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15075 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15076 uint64 ft_value = extract_ft_15_14_13_12_11(instruction); 15077 15078 const char *ft = FPR(ft_value, info); 15079 const char *rs = GPR(rs_value, info); 15080 const char *rt = GPR(rt_value, info); 15081 15082 return img_format("SWC1X %s, %s(%s)", ft, rs, rt); 15083 } 15084 15085 15086 /* 15087 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15088 * 15089 * 3 2 1 15090 * 10987654321098765432109876543210 15091 * 001000 00010001101 15092 * rt ----- 15093 * rs ----- 15094 * rd ----- 15095 */ 15096 static char *SWC1XS(uint64 instruction, Dis_info *info) 15097 { 15098 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15099 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15100 uint64 ft_value = extract_ft_15_14_13_12_11(instruction); 15101 15102 const char *ft = FPR(ft_value, info); 15103 const char *rs = GPR(rs_value, info); 15104 const char *rt = GPR(rt_value, info); 15105 15106 return img_format("SWC1XS %s, %s(%s)", ft, rs, rt); 15107 } 15108 15109 15110 /* 15111 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15112 * 15113 * 3 2 1 15114 * 10987654321098765432109876543210 15115 * 001000 00010001101 15116 * rt ----- 15117 * rs ----- 15118 * rd ----- 15119 */ 15120 static char *SWC2(uint64 instruction, Dis_info *info) 15121 { 15122 uint64 cs_value = extract_cs_25_24_23_22_21(instruction); 15123 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15124 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15125 15126 const char *rs = GPR(rs_value, info); 15127 15128 return img_format("SWC2 CP%" PRIu64 ", %" PRId64 "(%s)", 15129 cs_value, s_value, rs); 15130 } 15131 15132 15133 /* 15134 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15135 * 15136 * 3 2 1 15137 * 10987654321098765432109876543210 15138 * 001000 00010001101 15139 * rt ----- 15140 * rs ----- 15141 * rd ----- 15142 */ 15143 static char *SWE(uint64 instruction, Dis_info *info) 15144 { 15145 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15146 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15147 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15148 15149 const char *rt = GPR(rt_value, info); 15150 const char *rs = GPR(rs_value, info); 15151 15152 return img_format("SWE %s, %" PRId64 "(%s)", rt, s_value, rs); 15153 } 15154 15155 15156 /* 15157 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15158 * 15159 * 3 2 1 15160 * 10987654321098765432109876543210 15161 * 001000 00010001101 15162 * rt ----- 15163 * rs ----- 15164 * rd ----- 15165 */ 15166 static char *SWM(uint64 instruction, Dis_info *info) 15167 { 15168 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15169 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15170 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15171 uint64 count3_value = extract_count3_14_13_12(instruction); 15172 15173 const char *rt = GPR(rt_value, info); 15174 const char *rs = GPR(rs_value, info); 15175 uint64 count3 = encode_count3_from_count(count3_value); 15176 15177 return img_format("SWM %s, %" PRId64 "(%s), 0x%" PRIx64, 15178 rt, s_value, rs, count3); 15179 } 15180 15181 15182 /* 15183 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15184 * 15185 * 3 2 1 15186 * 10987654321098765432109876543210 15187 * 001000 00010001101 15188 * rt ----- 15189 * rs ----- 15190 * rd ----- 15191 */ 15192 static char *SWPC_48_(uint64 instruction, Dis_info *info) 15193 { 15194 uint64 rt_value = extract_rt_41_40_39_38_37(instruction); 15195 int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); 15196 15197 const char *rt = GPR(rt_value, info); 15198 g_autofree char *s = ADDRESS(s_value, 6, info); 15199 15200 return img_format("SWPC %s, %s", rt, s); 15201 } 15202 15203 15204 /* 15205 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15206 * 15207 * 3 2 1 15208 * 10987654321098765432109876543210 15209 * 001000 00010001101 15210 * rt ----- 15211 * rs ----- 15212 * rd ----- 15213 */ 15214 static char *SWX(uint64 instruction, Dis_info *info) 15215 { 15216 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15217 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15218 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 15219 15220 const char *rd = GPR(rd_value, info); 15221 const char *rs = GPR(rs_value, info); 15222 const char *rt = GPR(rt_value, info); 15223 15224 return img_format("SWX %s, %s(%s)", rd, rs, rt); 15225 } 15226 15227 15228 /* 15229 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15230 * 15231 * 3 2 1 15232 * 10987654321098765432109876543210 15233 * 001000 00010001101 15234 * rt ----- 15235 * rs ----- 15236 * rd ----- 15237 */ 15238 static char *SWXS(uint64 instruction, Dis_info *info) 15239 { 15240 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15241 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15242 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 15243 15244 const char *rd = GPR(rd_value, info); 15245 const char *rs = GPR(rs_value, info); 15246 const char *rt = GPR(rt_value, info); 15247 15248 return img_format("SWXS %s, %s(%s)", rd, rs, rt); 15249 } 15250 15251 15252 /* 15253 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15254 * 15255 * 3 2 1 15256 * 10987654321098765432109876543210 15257 * 001000 00010001101 15258 * rt ----- 15259 * rs ----- 15260 * rd ----- 15261 */ 15262 static char *SYNC(uint64 instruction, Dis_info *info) 15263 { 15264 uint64 stype_value = extract_stype_20_19_18_17_16(instruction); 15265 15266 15267 return img_format("SYNC 0x%" PRIx64, stype_value); 15268 } 15269 15270 15271 /* 15272 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15273 * 15274 * 3 2 1 15275 * 10987654321098765432109876543210 15276 * 001000 00010001101 15277 * rt ----- 15278 * rs ----- 15279 * rd ----- 15280 */ 15281 static char *SYNCI(uint64 instruction, Dis_info *info) 15282 { 15283 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15284 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15285 15286 const char *rs = GPR(rs_value, info); 15287 15288 return img_format("SYNCI %" PRId64 "(%s)", s_value, rs); 15289 } 15290 15291 15292 /* 15293 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15294 * 15295 * 3 2 1 15296 * 10987654321098765432109876543210 15297 * 001000 00010001101 15298 * rt ----- 15299 * rs ----- 15300 * rd ----- 15301 */ 15302 static char *SYNCIE(uint64 instruction, Dis_info *info) 15303 { 15304 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15305 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15306 15307 const char *rs = GPR(rs_value, info); 15308 15309 return img_format("SYNCIE %" PRId64 "(%s)", s_value, rs); 15310 } 15311 15312 15313 /* 15314 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15315 * 15316 * 3 2 1 15317 * 10987654321098765432109876543210 15318 * 001000 00010001101 15319 * rt ----- 15320 * rs ----- 15321 * rd ----- 15322 */ 15323 static char *SYSCALL_16_(uint64 instruction, Dis_info *info) 15324 { 15325 uint64 code_value = extract_code_1_0(instruction); 15326 15327 15328 return img_format("SYSCALL 0x%" PRIx64, code_value); 15329 } 15330 15331 15332 /* 15333 * SYSCALL code - System Call. Cause a System Call Exception 15334 * 15335 * 3 2 1 15336 * 10987654321098765432109876543210 15337 * 00000000000010 15338 * code ------------------ 15339 */ 15340 static char *SYSCALL_32_(uint64 instruction, Dis_info *info) 15341 { 15342 uint64 code_value = extract_code_17_to_0(instruction); 15343 15344 15345 return img_format("SYSCALL 0x%" PRIx64, code_value); 15346 } 15347 15348 15349 /* 15350 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15351 * 15352 * 3 2 1 15353 * 10987654321098765432109876543210 15354 * 001000 00010001101 15355 * rt ----- 15356 * rs ----- 15357 * rd ----- 15358 */ 15359 static char *TEQ(uint64 instruction, Dis_info *info) 15360 { 15361 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15362 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15363 15364 const char *rs = GPR(rs_value, info); 15365 const char *rt = GPR(rt_value, info); 15366 15367 return img_format("TEQ %s, %s", rs, rt); 15368 } 15369 15370 15371 /* 15372 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15373 * 15374 * 3 2 1 15375 * 10987654321098765432109876543210 15376 * 001000 00010001101 15377 * rt ----- 15378 * rs ----- 15379 * rd ----- 15380 */ 15381 static char *TLBGINV(uint64 instruction, Dis_info *info) 15382 { 15383 (void)instruction; 15384 15385 return g_strdup("TLBGINV "); 15386 } 15387 15388 15389 /* 15390 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15391 * 15392 * 3 2 1 15393 * 10987654321098765432109876543210 15394 * 001000 00010001101 15395 * rt ----- 15396 * rs ----- 15397 * rd ----- 15398 */ 15399 static char *TLBGINVF(uint64 instruction, Dis_info *info) 15400 { 15401 (void)instruction; 15402 15403 return g_strdup("TLBGINVF "); 15404 } 15405 15406 15407 /* 15408 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15409 * 15410 * 3 2 1 15411 * 10987654321098765432109876543210 15412 * 001000 00010001101 15413 * rt ----- 15414 * rs ----- 15415 * rd ----- 15416 */ 15417 static char *TLBGP(uint64 instruction, Dis_info *info) 15418 { 15419 (void)instruction; 15420 15421 return g_strdup("TLBGP "); 15422 } 15423 15424 15425 /* 15426 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15427 * 15428 * 3 2 1 15429 * 10987654321098765432109876543210 15430 * 001000 00010001101 15431 * rt ----- 15432 * rs ----- 15433 * rd ----- 15434 */ 15435 static char *TLBGR(uint64 instruction, Dis_info *info) 15436 { 15437 (void)instruction; 15438 15439 return g_strdup("TLBGR "); 15440 } 15441 15442 15443 /* 15444 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15445 * 15446 * 3 2 1 15447 * 10987654321098765432109876543210 15448 * 001000 00010001101 15449 * rt ----- 15450 * rs ----- 15451 * rd ----- 15452 */ 15453 static char *TLBGWI(uint64 instruction, Dis_info *info) 15454 { 15455 (void)instruction; 15456 15457 return g_strdup("TLBGWI "); 15458 } 15459 15460 15461 /* 15462 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15463 * 15464 * 3 2 1 15465 * 10987654321098765432109876543210 15466 * 001000 00010001101 15467 * rt ----- 15468 * rs ----- 15469 * rd ----- 15470 */ 15471 static char *TLBGWR(uint64 instruction, Dis_info *info) 15472 { 15473 (void)instruction; 15474 15475 return g_strdup("TLBGWR "); 15476 } 15477 15478 15479 /* 15480 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15481 * 15482 * 3 2 1 15483 * 10987654321098765432109876543210 15484 * 001000 00010001101 15485 * rt ----- 15486 * rs ----- 15487 * rd ----- 15488 */ 15489 static char *TLBINV(uint64 instruction, Dis_info *info) 15490 { 15491 (void)instruction; 15492 15493 return g_strdup("TLBINV "); 15494 } 15495 15496 15497 /* 15498 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15499 * 15500 * 3 2 1 15501 * 10987654321098765432109876543210 15502 * 001000 00010001101 15503 * rt ----- 15504 * rs ----- 15505 * rd ----- 15506 */ 15507 static char *TLBINVF(uint64 instruction, Dis_info *info) 15508 { 15509 (void)instruction; 15510 15511 return g_strdup("TLBINVF "); 15512 } 15513 15514 15515 /* 15516 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15517 * 15518 * 3 2 1 15519 * 10987654321098765432109876543210 15520 * 001000 00010001101 15521 * rt ----- 15522 * rs ----- 15523 * rd ----- 15524 */ 15525 static char *TLBP(uint64 instruction, Dis_info *info) 15526 { 15527 (void)instruction; 15528 15529 return g_strdup("TLBP "); 15530 } 15531 15532 15533 /* 15534 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15535 * 15536 * 3 2 1 15537 * 10987654321098765432109876543210 15538 * 001000 00010001101 15539 * rt ----- 15540 * rs ----- 15541 * rd ----- 15542 */ 15543 static char *TLBR(uint64 instruction, Dis_info *info) 15544 { 15545 (void)instruction; 15546 15547 return g_strdup("TLBR "); 15548 } 15549 15550 15551 /* 15552 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15553 * 15554 * 3 2 1 15555 * 10987654321098765432109876543210 15556 * 001000 00010001101 15557 * rt ----- 15558 * rs ----- 15559 * rd ----- 15560 */ 15561 static char *TLBWI(uint64 instruction, Dis_info *info) 15562 { 15563 (void)instruction; 15564 15565 return g_strdup("TLBWI "); 15566 } 15567 15568 15569 /* 15570 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15571 * 15572 * 3 2 1 15573 * 10987654321098765432109876543210 15574 * 001000 00010001101 15575 * rt ----- 15576 * rs ----- 15577 * rd ----- 15578 */ 15579 static char *TLBWR(uint64 instruction, Dis_info *info) 15580 { 15581 (void)instruction; 15582 15583 return g_strdup("TLBWR "); 15584 } 15585 15586 15587 /* 15588 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15589 * 15590 * 3 2 1 15591 * 10987654321098765432109876543210 15592 * 001000 00010001101 15593 * rt ----- 15594 * rs ----- 15595 * rd ----- 15596 */ 15597 static char *TNE(uint64 instruction, Dis_info *info) 15598 { 15599 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15600 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15601 15602 const char *rs = GPR(rs_value, info); 15603 const char *rt = GPR(rt_value, info); 15604 15605 return img_format("TNE %s, %s", rs, rt); 15606 } 15607 15608 15609 /* 15610 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15611 * 15612 * 3 2 1 15613 * 10987654321098765432109876543210 15614 * 001000 00010001101 15615 * rt ----- 15616 * rs ----- 15617 * rd ----- 15618 */ 15619 static char *TRUNC_L_D(uint64 instruction, Dis_info *info) 15620 { 15621 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 15622 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 15623 15624 const char *ft = FPR(ft_value, info); 15625 const char *fs = FPR(fs_value, info); 15626 15627 return img_format("TRUNC.L.D %s, %s", ft, fs); 15628 } 15629 15630 15631 /* 15632 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15633 * 15634 * 3 2 1 15635 * 10987654321098765432109876543210 15636 * 001000 00010001101 15637 * rt ----- 15638 * rs ----- 15639 * rd ----- 15640 */ 15641 static char *TRUNC_L_S(uint64 instruction, Dis_info *info) 15642 { 15643 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 15644 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 15645 15646 const char *ft = FPR(ft_value, info); 15647 const char *fs = FPR(fs_value, info); 15648 15649 return img_format("TRUNC.L.S %s, %s", ft, fs); 15650 } 15651 15652 15653 /* 15654 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15655 * 15656 * 3 2 1 15657 * 10987654321098765432109876543210 15658 * 001000 00010001101 15659 * rt ----- 15660 * rs ----- 15661 * rd ----- 15662 */ 15663 static char *TRUNC_W_D(uint64 instruction, Dis_info *info) 15664 { 15665 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 15666 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 15667 15668 const char *ft = FPR(ft_value, info); 15669 const char *fs = FPR(fs_value, info); 15670 15671 return img_format("TRUNC.W.D %s, %s", ft, fs); 15672 } 15673 15674 15675 /* 15676 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15677 * 15678 * 3 2 1 15679 * 10987654321098765432109876543210 15680 * 001000 00010001101 15681 * rt ----- 15682 * rs ----- 15683 * rd ----- 15684 */ 15685 static char *TRUNC_W_S(uint64 instruction, Dis_info *info) 15686 { 15687 uint64 ft_value = extract_ft_25_24_23_22_21(instruction); 15688 uint64 fs_value = extract_fs_20_19_18_17_16(instruction); 15689 15690 const char *ft = FPR(ft_value, info); 15691 const char *fs = FPR(fs_value, info); 15692 15693 return img_format("TRUNC.W.S %s, %s", ft, fs); 15694 } 15695 15696 15697 /* 15698 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15699 * 15700 * 3 2 1 15701 * 10987654321098765432109876543210 15702 * 001000 00010001101 15703 * rt ----- 15704 * rs ----- 15705 * rd ----- 15706 */ 15707 static char *UALDM(uint64 instruction, Dis_info *info) 15708 { 15709 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15710 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15711 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15712 uint64 count3_value = extract_count3_14_13_12(instruction); 15713 15714 const char *rt = GPR(rt_value, info); 15715 const char *rs = GPR(rs_value, info); 15716 uint64 count3 = encode_count3_from_count(count3_value); 15717 15718 return img_format("UALDM %s, %" PRId64 "(%s), 0x%" PRIx64, 15719 rt, s_value, rs, count3); 15720 } 15721 15722 15723 /* 15724 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15725 * 15726 * 3 2 1 15727 * 10987654321098765432109876543210 15728 * 001000 00010001101 15729 * rt ----- 15730 * rs ----- 15731 * rd ----- 15732 */ 15733 static char *UALH(uint64 instruction, Dis_info *info) 15734 { 15735 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15736 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15737 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15738 15739 const char *rt = GPR(rt_value, info); 15740 const char *rs = GPR(rs_value, info); 15741 15742 return img_format("UALH %s, %" PRId64 "(%s)", rt, s_value, rs); 15743 } 15744 15745 15746 /* 15747 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15748 * 15749 * 3 2 1 15750 * 10987654321098765432109876543210 15751 * 001000 00010001101 15752 * rt ----- 15753 * rs ----- 15754 * rd ----- 15755 */ 15756 static char *UALWM(uint64 instruction, Dis_info *info) 15757 { 15758 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15759 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15760 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15761 uint64 count3_value = extract_count3_14_13_12(instruction); 15762 15763 const char *rt = GPR(rt_value, info); 15764 const char *rs = GPR(rs_value, info); 15765 uint64 count3 = encode_count3_from_count(count3_value); 15766 15767 return img_format("UALWM %s, %" PRId64 "(%s), 0x%" PRIx64, 15768 rt, s_value, rs, count3); 15769 } 15770 15771 15772 /* 15773 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15774 * 15775 * 3 2 1 15776 * 10987654321098765432109876543210 15777 * 001000 00010001101 15778 * rt ----- 15779 * rs ----- 15780 * rd ----- 15781 */ 15782 static char *UASDM(uint64 instruction, Dis_info *info) 15783 { 15784 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15785 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15786 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15787 uint64 count3_value = extract_count3_14_13_12(instruction); 15788 15789 const char *rt = GPR(rt_value, info); 15790 const char *rs = GPR(rs_value, info); 15791 uint64 count3 = encode_count3_from_count(count3_value); 15792 15793 return img_format("UASDM %s, %" PRId64 "(%s), 0x%" PRIx64, 15794 rt, s_value, rs, count3); 15795 } 15796 15797 15798 /* 15799 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15800 * 15801 * 3 2 1 15802 * 10987654321098765432109876543210 15803 * 001000 00010001101 15804 * rt ----- 15805 * rs ----- 15806 * rd ----- 15807 */ 15808 static char *UASH(uint64 instruction, Dis_info *info) 15809 { 15810 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15811 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15812 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15813 15814 const char *rt = GPR(rt_value, info); 15815 const char *rs = GPR(rs_value, info); 15816 15817 return img_format("UASH %s, %" PRId64 "(%s)", rt, s_value, rs); 15818 } 15819 15820 15821 /* 15822 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15823 * 15824 * 3 2 1 15825 * 10987654321098765432109876543210 15826 * 001000 00010001101 15827 * rt ----- 15828 * rs ----- 15829 * rd ----- 15830 */ 15831 static char *UASWM(uint64 instruction, Dis_info *info) 15832 { 15833 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15834 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15835 int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); 15836 uint64 count3_value = extract_count3_14_13_12(instruction); 15837 15838 const char *rt = GPR(rt_value, info); 15839 const char *rs = GPR(rs_value, info); 15840 uint64 count3 = encode_count3_from_count(count3_value); 15841 15842 return img_format("UASWM %s, %" PRId64 "(%s), 0x%" PRIx64, 15843 rt, s_value, rs, count3); 15844 } 15845 15846 15847 /* 15848 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15849 * 15850 * 3 2 1 15851 * 10987654321098765432109876543210 15852 * 001000 00010001101 15853 * rt ----- 15854 * rs ----- 15855 * rd ----- 15856 */ 15857 static char *UDI(uint64 instruction, Dis_info *info) 15858 { 15859 uint64 op_value = extract_op_25_to_3(instruction); 15860 15861 15862 return img_format("UDI 0x%" PRIx64, op_value); 15863 } 15864 15865 15866 /* 15867 * WAIT code - Enter Wait State 15868 * 15869 * 3 2 1 15870 * 10987654321098765432109876543210 15871 * 001000 1100001101111111 15872 * code ---------- 15873 */ 15874 static char *WAIT(uint64 instruction, Dis_info *info) 15875 { 15876 uint64 code_value = extract_code_25_24_23_22_21_20_19_18_17_16(instruction); 15877 15878 15879 return img_format("WAIT 0x%" PRIx64, code_value); 15880 } 15881 15882 15883 /* 15884 * [DSP] WRDSP rt, mask - Write selected fields from a GPR to the DSPControl 15885 * register 15886 * 15887 * 3 2 1 15888 * 10987654321098765432109876543210 15889 * 001000 01011001111111 15890 * rt ----- 15891 * mask ------- 15892 */ 15893 static char *WRDSP(uint64 instruction, Dis_info *info) 15894 { 15895 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15896 uint64 mask_value = extract_mask_20_19_18_17_16_15_14(instruction); 15897 15898 const char *rt = GPR(rt_value, info); 15899 15900 return img_format("WRDSP %s, 0x%" PRIx64, rt, mask_value); 15901 } 15902 15903 15904 /* 15905 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15906 * 15907 * 3 2 1 15908 * 10987654321098765432109876543210 15909 * 001000 00010001101 15910 * rt ----- 15911 * rs ----- 15912 * rd ----- 15913 */ 15914 static char *WRPGPR(uint64 instruction, Dis_info *info) 15915 { 15916 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15917 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15918 15919 const char *rt = GPR(rt_value, info); 15920 const char *rs = GPR(rs_value, info); 15921 15922 return img_format("WRPGPR %s, %s", rt, rs); 15923 } 15924 15925 15926 /* 15927 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15928 * 15929 * 3 2 1 15930 * 10987654321098765432109876543210 15931 * 001000 00010001101 15932 * rt ----- 15933 * rs ----- 15934 * rd ----- 15935 */ 15936 static char *XOR_16_(uint64 instruction, Dis_info *info) 15937 { 15938 uint64 rt3_value = extract_rt3_9_8_7(instruction); 15939 uint64 rs3_value = extract_rs3_6_5_4(instruction); 15940 15941 const char *rs3 = GPR(decode_gpr_gpr3(rs3_value, info), info); 15942 const char *rt3 = GPR(decode_gpr_gpr3(rt3_value, info), info); 15943 15944 return img_format("XOR %s, %s", rs3, rt3); 15945 } 15946 15947 15948 /* 15949 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15950 * 15951 * 3 2 1 15952 * 10987654321098765432109876543210 15953 * 001000 00010001101 15954 * rt ----- 15955 * rs ----- 15956 * rd ----- 15957 */ 15958 static char *XOR_32_(uint64 instruction, Dis_info *info) 15959 { 15960 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15961 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15962 uint64 rd_value = extract_rd_15_14_13_12_11(instruction); 15963 15964 const char *rd = GPR(rd_value, info); 15965 const char *rs = GPR(rs_value, info); 15966 const char *rt = GPR(rt_value, info); 15967 15968 return img_format("XOR %s, %s, %s", rd, rs, rt); 15969 } 15970 15971 15972 /* 15973 * ADDQH_R.W rd, rt, rs - Add Fractional Words And Shift Right to Halve Results 15974 * 15975 * 3 2 1 15976 * 10987654321098765432109876543210 15977 * 001000 00010001101 15978 * rt ----- 15979 * rs ----- 15980 * rd ----- 15981 */ 15982 static char *XORI(uint64 instruction, Dis_info *info) 15983 { 15984 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 15985 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 15986 uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); 15987 15988 const char *rt = GPR(rt_value, info); 15989 const char *rs = GPR(rs_value, info); 15990 15991 return img_format("XORI %s, %s, 0x%" PRIx64, rt, rs, u_value); 15992 } 15993 15994 15995 /* 15996 * YIELD rt, rs - 15997 * 15998 * 3 2 1 15999 * 10987654321098765432109876543210 16000 * 001000 00010001101 16001 * rt ----- 16002 * rs ----- 16003 */ 16004 static char *YIELD(uint64 instruction, Dis_info *info) 16005 { 16006 uint64 rt_value = extract_rt_25_24_23_22_21(instruction); 16007 uint64 rs_value = extract_rs_20_19_18_17_16(instruction); 16008 16009 const char *rt = GPR(rt_value, info); 16010 const char *rs = GPR(rs_value, info); 16011 16012 return img_format("YIELD %s, %s", rt, rs); 16013 } 16014 16015 16016 16017 /* 16018 * nanoMIPS instruction pool organization 16019 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 16020 * 16021 * 16022 * ┌─ P.ADDIU ─── P.RI ─── P.SYSCALL 16023 * │ 16024 * │ ┌─ P.TRAP 16025 * │ │ 16026 * │ ┌─ _POOL32A0_0 ─┼─ P.CMOVE 16027 * │ │ │ 16028 * │ │ └─ P.SLTU 16029 * │ ┌─ _POOL32A0 ─┤ 16030 * │ │ │ 16031 * │ │ │ 16032 * │ │ └─ _POOL32A0_1 ─── CRC32 16033 * │ │ 16034 * ├─ P32A ─┤ 16035 * │ │ ┌─ PP.LSX 16036 * │ │ ┌─ P.LSX ─────┤ 16037 * │ │ │ └─ PP.LSXS 16038 * │ └─ _POOL32A7 ─┤ 16039 * │ │ ┌─ POOL32Axf_4 16040 * │ └─ POOL32Axf ─┤ 16041 * │ └─ POOL32Axf_5 16042 * │ 16043 * ├─ PBAL 16044 * │ 16045 * ├─ P.GP.W ┌─ PP.LSX 16046 * ┌─ P32 ─┤ │ 16047 * │ ├─ P.GP.BH ─┴─ PP.LSXS 16048 * │ │ 16049 * │ ├─ P.J ─────── PP.BALRSC 16050 * │ │ 16051 * │ ├─ P48I 16052 * │ │ ┌─ P.SR 16053 * │ │ │ 16054 * │ │ ├─ P.SHIFT 16055 * │ │ │ 16056 * │ ├─ P.U12 ───┼─ P.ROTX 16057 * │ │ │ 16058 * │ │ ├─ P.INS 16059 * │ │ │ 16060 * │ │ └─ P.EXT 16061 * │ │ 16062 * │ ├─ P.LS.U12 ── P.PREF.U12 16063 * │ │ 16064 * │ ├─ P.BR1 ───── P.BR3A 16065 * │ │ 16066 * │ │ ┌─ P.LS.S0 ─── P16.SYSCALL 16067 * │ │ │ 16068 * │ │ │ ┌─ P.LL 16069 * │ │ ├─ P.LS.S1 ─┤ 16070 * │ │ │ └─ P.SC 16071 * │ │ │ 16072 * │ │ │ ┌─ P.PREFE 16073 * MAJOR ─┤ ├─ P.LS.S9 ─┤ │ 16074 * │ │ ├─ P.LS.E0 ─┼─ P.LLE 16075 * │ │ │ │ 16076 * │ │ │ └─ P.SCE 16077 * │ │ │ 16078 * │ │ ├─ P.LS.WM 16079 * │ │ │ 16080 * │ │ └─ P.LS.UAWM 16081 * │ │ 16082 * │ │ 16083 * │ ├─ P.BR2 16084 * │ │ 16085 * │ ├─ P.BRI 16086 * │ │ 16087 * │ └─ P.LUI 16088 * │ 16089 * │ 16090 * │ ┌─ P16.MV ──── P16.RI ─── P16.SYSCALL 16091 * │ │ 16092 * │ ├─ P16.SR 16093 * │ │ 16094 * │ ├─ P16.SHIFT 16095 * │ │ 16096 * │ ├─ P16.4x4 16097 * │ │ 16098 * │ ├─ P16C ────── POOL16C_0 ── POOL16C_00 16099 * │ │ 16100 * └─ P16 ─┼─ P16.LB 16101 * │ 16102 * ├─ P16.A1 16103 * │ 16104 * ├─ P16.LH 16105 * │ 16106 * ├─ P16.A2 ──── P.ADDIU[RS5] 16107 * │ 16108 * ├─ P16.ADDU 16109 * │ 16110 * └─ P16.BR ──┬─ P16.JRC 16111 * │ 16112 * └─ P16.BR1 16113 * 16114 * 16115 * (FP, DPS, and some minor instruction pools are omitted from the diagram) 16116 * 16117 */ 16118 16119 typedef enum { 16120 instruction, 16121 call_instruction, 16122 branch_instruction, 16123 return_instruction, 16124 reserved_block, 16125 pool, 16126 } TABLE_ENTRY_TYPE; 16127 16128 typedef enum { 16129 MIPS64_ = 0x00000001, 16130 XNP_ = 0x00000002, 16131 XMMS_ = 0x00000004, 16132 EVA_ = 0x00000008, 16133 DSP_ = 0x00000010, 16134 MT_ = 0x00000020, 16135 EJTAG_ = 0x00000040, 16136 TLBINV_ = 0x00000080, 16137 CP0_ = 0x00000100, 16138 CP1_ = 0x00000200, 16139 CP2_ = 0x00000400, 16140 UDI_ = 0x00000800, 16141 MCU_ = 0x00001000, 16142 VZ_ = 0x00002000, 16143 TLB_ = 0x00004000, 16144 MVH_ = 0x00008000, 16145 ALL_ATTRIBUTES = 0xffffffffull, 16146 } TABLE_ATTRIBUTE_TYPE; 16147 16148 typedef bool (*conditional_function)(uint64 instruction); 16149 typedef char * (*disassembly_function)(uint64 instruction, 16150 Dis_info *info); 16151 16152 typedef struct Pool { 16153 TABLE_ENTRY_TYPE type; 16154 const struct Pool *next_table; 16155 int next_table_size; 16156 int instructions_size; 16157 uint64 mask; 16158 uint64 value; 16159 disassembly_function disassembly; 16160 conditional_function condition; 16161 uint64 attributes; 16162 } Pool; 16163 16164 static const Pool P_SYSCALL[2] = { 16165 { instruction , 0 , 0 , 32, 16166 0xfffc0000, 0x00080000, &SYSCALL_32_ , 0, 16167 0x0 }, /* SYSCALL[32] */ 16168 { instruction , 0 , 0 , 32, 16169 0xfffc0000, 0x000c0000, &HYPCALL , 0, 16170 CP0_ | VZ_ }, /* HYPCALL */ 16171 }; 16172 16173 16174 static const Pool P_RI[4] = { 16175 { instruction , 0 , 0 , 32, 16176 0xfff80000, 0x00000000, &SIGRIE , 0, 16177 0x0 }, /* SIGRIE */ 16178 { pool , P_SYSCALL , 2 , 32, 16179 0xfff80000, 0x00080000, 0 , 0, 16180 0x0 }, /* P.SYSCALL */ 16181 { instruction , 0 , 0 , 32, 16182 0xfff80000, 0x00100000, &BREAK_32_ , 0, 16183 0x0 }, /* BREAK[32] */ 16184 { instruction , 0 , 0 , 32, 16185 0xfff80000, 0x00180000, &SDBBP_32_ , 0, 16186 EJTAG_ }, /* SDBBP[32] */ 16187 }; 16188 16189 16190 static const Pool P_ADDIU[2] = { 16191 { pool , P_RI , 4 , 32, 16192 0xffe00000, 0x00000000, 0 , 0, 16193 0x0 }, /* P.RI */ 16194 { instruction , 0 , 0 , 32, 16195 0xfc000000, 0x00000000, &ADDIU_32_ , &ADDIU_32__cond , 16196 0x0 }, /* ADDIU[32] */ 16197 }; 16198 16199 16200 static const Pool P_TRAP[2] = { 16201 { instruction , 0 , 0 , 32, 16202 0xfc0007ff, 0x20000000, &TEQ , 0, 16203 XMMS_ }, /* TEQ */ 16204 { instruction , 0 , 0 , 32, 16205 0xfc0007ff, 0x20000400, &TNE , 0, 16206 XMMS_ }, /* TNE */ 16207 }; 16208 16209 16210 static const Pool P_CMOVE[2] = { 16211 { instruction , 0 , 0 , 32, 16212 0xfc0007ff, 0x20000210, &MOVZ , 0, 16213 0x0 }, /* MOVZ */ 16214 { instruction , 0 , 0 , 32, 16215 0xfc0007ff, 0x20000610, &MOVN , 0, 16216 0x0 }, /* MOVN */ 16217 }; 16218 16219 16220 static const Pool P_D_MT_VPE[2] = { 16221 { instruction , 0 , 0 , 32, 16222 0xfc1f3fff, 0x20010ab0, &DMT , 0, 16223 MT_ }, /* DMT */ 16224 { instruction , 0 , 0 , 32, 16225 0xfc1f3fff, 0x20000ab0, &DVPE , 0, 16226 MT_ }, /* DVPE */ 16227 }; 16228 16229 16230 static const Pool P_E_MT_VPE[2] = { 16231 { instruction , 0 , 0 , 32, 16232 0xfc1f3fff, 0x20010eb0, &EMT , 0, 16233 MT_ }, /* EMT */ 16234 { instruction , 0 , 0 , 32, 16235 0xfc1f3fff, 0x20000eb0, &EVPE , 0, 16236 MT_ }, /* EVPE */ 16237 }; 16238 16239 16240 static const Pool _P_MT_VPE[2] = { 16241 { pool , P_D_MT_VPE , 2 , 32, 16242 0xfc003fff, 0x20000ab0, 0 , 0, 16243 0x0 }, /* P.D_MT_VPE */ 16244 { pool , P_E_MT_VPE , 2 , 32, 16245 0xfc003fff, 0x20000eb0, 0 , 0, 16246 0x0 }, /* P.E_MT_VPE */ 16247 }; 16248 16249 16250 static const Pool P_MT_VPE[8] = { 16251 { reserved_block , 0 , 0 , 32, 16252 0xfc003bff, 0x200002b0, 0 , 0, 16253 0x0 }, /* P.MT_VPE~*(0) */ 16254 { pool , _P_MT_VPE , 2 , 32, 16255 0xfc003bff, 0x20000ab0, 0 , 0, 16256 0x0 }, /* _P.MT_VPE */ 16257 { reserved_block , 0 , 0 , 32, 16258 0xfc003bff, 0x200012b0, 0 , 0, 16259 0x0 }, /* P.MT_VPE~*(2) */ 16260 { reserved_block , 0 , 0 , 32, 16261 0xfc003bff, 0x20001ab0, 0 , 0, 16262 0x0 }, /* P.MT_VPE~*(3) */ 16263 { reserved_block , 0 , 0 , 32, 16264 0xfc003bff, 0x200022b0, 0 , 0, 16265 0x0 }, /* P.MT_VPE~*(4) */ 16266 { reserved_block , 0 , 0 , 32, 16267 0xfc003bff, 0x20002ab0, 0 , 0, 16268 0x0 }, /* P.MT_VPE~*(5) */ 16269 { reserved_block , 0 , 0 , 32, 16270 0xfc003bff, 0x200032b0, 0 , 0, 16271 0x0 }, /* P.MT_VPE~*(6) */ 16272 { reserved_block , 0 , 0 , 32, 16273 0xfc003bff, 0x20003ab0, 0 , 0, 16274 0x0 }, /* P.MT_VPE~*(7) */ 16275 }; 16276 16277 16278 static const Pool P_DVP[2] = { 16279 { instruction , 0 , 0 , 32, 16280 0xfc00ffff, 0x20000390, &DVP , 0, 16281 0x0 }, /* DVP */ 16282 { instruction , 0 , 0 , 32, 16283 0xfc00ffff, 0x20000790, &EVP , 0, 16284 0x0 }, /* EVP */ 16285 }; 16286 16287 16288 static const Pool P_SLTU[2] = { 16289 { pool , P_DVP , 2 , 32, 16290 0xfc00fbff, 0x20000390, 0 , 0, 16291 0x0 }, /* P.DVP */ 16292 { instruction , 0 , 0 , 32, 16293 0xfc0003ff, 0x20000390, &SLTU , &SLTU_cond , 16294 0x0 }, /* SLTU */ 16295 }; 16296 16297 16298 static const Pool _POOL32A0[128] = { 16299 { pool , P_TRAP , 2 , 32, 16300 0xfc0003ff, 0x20000000, 0 , 0, 16301 0x0 }, /* P.TRAP */ 16302 { instruction , 0 , 0 , 32, 16303 0xfc0003ff, 0x20000008, &SEB , 0, 16304 XMMS_ }, /* SEB */ 16305 { instruction , 0 , 0 , 32, 16306 0xfc0003ff, 0x20000010, &SLLV , 0, 16307 0x0 }, /* SLLV */ 16308 { instruction , 0 , 0 , 32, 16309 0xfc0003ff, 0x20000018, &MUL_32_ , 0, 16310 0x0 }, /* MUL[32] */ 16311 { reserved_block , 0 , 0 , 32, 16312 0xfc0003ff, 0x20000020, 0 , 0, 16313 0x0 }, /* _POOL32A0~*(4) */ 16314 { reserved_block , 0 , 0 , 32, 16315 0xfc0003ff, 0x20000028, 0 , 0, 16316 0x0 }, /* _POOL32A0~*(5) */ 16317 { instruction , 0 , 0 , 32, 16318 0xfc0003ff, 0x20000030, &MFC0 , 0, 16319 0x0 }, /* MFC0 */ 16320 { instruction , 0 , 0 , 32, 16321 0xfc0003ff, 0x20000038, &MFHC0 , 0, 16322 CP0_ | MVH_ }, /* MFHC0 */ 16323 { reserved_block , 0 , 0 , 32, 16324 0xfc0003ff, 0x20000040, 0 , 0, 16325 0x0 }, /* _POOL32A0~*(8) */ 16326 { instruction , 0 , 0 , 32, 16327 0xfc0003ff, 0x20000048, &SEH , 0, 16328 0x0 }, /* SEH */ 16329 { instruction , 0 , 0 , 32, 16330 0xfc0003ff, 0x20000050, &SRLV , 0, 16331 0x0 }, /* SRLV */ 16332 { instruction , 0 , 0 , 32, 16333 0xfc0003ff, 0x20000058, &MUH , 0, 16334 0x0 }, /* MUH */ 16335 { reserved_block , 0 , 0 , 32, 16336 0xfc0003ff, 0x20000060, 0 , 0, 16337 0x0 }, /* _POOL32A0~*(12) */ 16338 { reserved_block , 0 , 0 , 32, 16339 0xfc0003ff, 0x20000068, 0 , 0, 16340 0x0 }, /* _POOL32A0~*(13) */ 16341 { instruction , 0 , 0 , 32, 16342 0xfc0003ff, 0x20000070, &MTC0 , 0, 16343 CP0_ }, /* MTC0 */ 16344 { instruction , 0 , 0 , 32, 16345 0xfc0003ff, 0x20000078, &MTHC0 , 0, 16346 CP0_ | MVH_ }, /* MTHC0 */ 16347 { reserved_block , 0 , 0 , 32, 16348 0xfc0003ff, 0x20000080, 0 , 0, 16349 0x0 }, /* _POOL32A0~*(16) */ 16350 { reserved_block , 0 , 0 , 32, 16351 0xfc0003ff, 0x20000088, 0 , 0, 16352 0x0 }, /* _POOL32A0~*(17) */ 16353 { instruction , 0 , 0 , 32, 16354 0xfc0003ff, 0x20000090, &SRAV , 0, 16355 0x0 }, /* SRAV */ 16356 { instruction , 0 , 0 , 32, 16357 0xfc0003ff, 0x20000098, &MULU , 0, 16358 0x0 }, /* MULU */ 16359 { reserved_block , 0 , 0 , 32, 16360 0xfc0003ff, 0x200000a0, 0 , 0, 16361 0x0 }, /* _POOL32A0~*(20) */ 16362 { reserved_block , 0 , 0 , 32, 16363 0xfc0003ff, 0x200000a8, 0 , 0, 16364 0x0 }, /* _POOL32A0~*(21) */ 16365 { instruction , 0 , 0 , 32, 16366 0xfc0003ff, 0x200000b0, &MFGC0 , 0, 16367 CP0_ | VZ_ }, /* MFGC0 */ 16368 { instruction , 0 , 0 , 32, 16369 0xfc0003ff, 0x200000b8, &MFHGC0 , 0, 16370 CP0_ | VZ_ | MVH_ }, /* MFHGC0 */ 16371 { reserved_block , 0 , 0 , 32, 16372 0xfc0003ff, 0x200000c0, 0 , 0, 16373 0x0 }, /* _POOL32A0~*(24) */ 16374 { reserved_block , 0 , 0 , 32, 16375 0xfc0003ff, 0x200000c8, 0 , 0, 16376 0x0 }, /* _POOL32A0~*(25) */ 16377 { instruction , 0 , 0 , 32, 16378 0xfc0003ff, 0x200000d0, &ROTRV , 0, 16379 0x0 }, /* ROTRV */ 16380 { instruction , 0 , 0 , 32, 16381 0xfc0003ff, 0x200000d8, &MUHU , 0, 16382 0x0 }, /* MUHU */ 16383 { reserved_block , 0 , 0 , 32, 16384 0xfc0003ff, 0x200000e0, 0 , 0, 16385 0x0 }, /* _POOL32A0~*(28) */ 16386 { reserved_block , 0 , 0 , 32, 16387 0xfc0003ff, 0x200000e8, 0 , 0, 16388 0x0 }, /* _POOL32A0~*(29) */ 16389 { instruction , 0 , 0 , 32, 16390 0xfc0003ff, 0x200000f0, &MTGC0 , 0, 16391 CP0_ | VZ_ }, /* MTGC0 */ 16392 { instruction , 0 , 0 , 32, 16393 0xfc0003ff, 0x200000f8, &MTHGC0 , 0, 16394 CP0_ | VZ_ | MVH_ }, /* MTHGC0 */ 16395 { reserved_block , 0 , 0 , 32, 16396 0xfc0003ff, 0x20000100, 0 , 0, 16397 0x0 }, /* _POOL32A0~*(32) */ 16398 { reserved_block , 0 , 0 , 32, 16399 0xfc0003ff, 0x20000108, 0 , 0, 16400 0x0 }, /* _POOL32A0~*(33) */ 16401 { instruction , 0 , 0 , 32, 16402 0xfc0003ff, 0x20000110, &ADD , 0, 16403 XMMS_ }, /* ADD */ 16404 { instruction , 0 , 0 , 32, 16405 0xfc0003ff, 0x20000118, &DIV , 0, 16406 0x0 }, /* DIV */ 16407 { reserved_block , 0 , 0 , 32, 16408 0xfc0003ff, 0x20000120, 0 , 0, 16409 0x0 }, /* _POOL32A0~*(36) */ 16410 { reserved_block , 0 , 0 , 32, 16411 0xfc0003ff, 0x20000128, 0 , 0, 16412 0x0 }, /* _POOL32A0~*(37) */ 16413 { instruction , 0 , 0 , 32, 16414 0xfc0003ff, 0x20000130, &DMFC0 , 0, 16415 CP0_ | MIPS64_ }, /* DMFC0 */ 16416 { reserved_block , 0 , 0 , 32, 16417 0xfc0003ff, 0x20000138, 0 , 0, 16418 0x0 }, /* _POOL32A0~*(39) */ 16419 { reserved_block , 0 , 0 , 32, 16420 0xfc0003ff, 0x20000140, 0 , 0, 16421 0x0 }, /* _POOL32A0~*(40) */ 16422 { reserved_block , 0 , 0 , 32, 16423 0xfc0003ff, 0x20000148, 0 , 0, 16424 0x0 }, /* _POOL32A0~*(41) */ 16425 { instruction , 0 , 0 , 32, 16426 0xfc0003ff, 0x20000150, &ADDU_32_ , 0, 16427 0x0 }, /* ADDU[32] */ 16428 { instruction , 0 , 0 , 32, 16429 0xfc0003ff, 0x20000158, &MOD , 0, 16430 0x0 }, /* MOD */ 16431 { reserved_block , 0 , 0 , 32, 16432 0xfc0003ff, 0x20000160, 0 , 0, 16433 0x0 }, /* _POOL32A0~*(44) */ 16434 { reserved_block , 0 , 0 , 32, 16435 0xfc0003ff, 0x20000168, 0 , 0, 16436 0x0 }, /* _POOL32A0~*(45) */ 16437 { instruction , 0 , 0 , 32, 16438 0xfc0003ff, 0x20000170, &DMTC0 , 0, 16439 CP0_ | MIPS64_ }, /* DMTC0 */ 16440 { reserved_block , 0 , 0 , 32, 16441 0xfc0003ff, 0x20000178, 0 , 0, 16442 0x0 }, /* _POOL32A0~*(47) */ 16443 { reserved_block , 0 , 0 , 32, 16444 0xfc0003ff, 0x20000180, 0 , 0, 16445 0x0 }, /* _POOL32A0~*(48) */ 16446 { reserved_block , 0 , 0 , 32, 16447 0xfc0003ff, 0x20000188, 0 , 0, 16448 0x0 }, /* _POOL32A0~*(49) */ 16449 { instruction , 0 , 0 , 32, 16450 0xfc0003ff, 0x20000190, &SUB , 0, 16451 XMMS_ }, /* SUB */ 16452 { instruction , 0 , 0 , 32, 16453 0xfc0003ff, 0x20000198, &DIVU , 0, 16454 0x0 }, /* DIVU */ 16455 { reserved_block , 0 , 0 , 32, 16456 0xfc0003ff, 0x200001a0, 0 , 0, 16457 0x0 }, /* _POOL32A0~*(52) */ 16458 { reserved_block , 0 , 0 , 32, 16459 0xfc0003ff, 0x200001a8, 0 , 0, 16460 0x0 }, /* _POOL32A0~*(53) */ 16461 { instruction , 0 , 0 , 32, 16462 0xfc0003ff, 0x200001b0, &DMFGC0 , 0, 16463 CP0_ | MIPS64_ | VZ_}, /* DMFGC0 */ 16464 { reserved_block , 0 , 0 , 32, 16465 0xfc0003ff, 0x200001b8, 0 , 0, 16466 0x0 }, /* _POOL32A0~*(55) */ 16467 { instruction , 0 , 0 , 32, 16468 0xfc0003ff, 0x200001c0, &RDHWR , 0, 16469 XMMS_ }, /* RDHWR */ 16470 { reserved_block , 0 , 0 , 32, 16471 0xfc0003ff, 0x200001c8, 0 , 0, 16472 0x0 }, /* _POOL32A0~*(57) */ 16473 { instruction , 0 , 0 , 32, 16474 0xfc0003ff, 0x200001d0, &SUBU_32_ , 0, 16475 0x0 }, /* SUBU[32] */ 16476 { instruction , 0 , 0 , 32, 16477 0xfc0003ff, 0x200001d8, &MODU , 0, 16478 0x0 }, /* MODU */ 16479 { reserved_block , 0 , 0 , 32, 16480 0xfc0003ff, 0x200001e0, 0 , 0, 16481 0x0 }, /* _POOL32A0~*(60) */ 16482 { reserved_block , 0 , 0 , 32, 16483 0xfc0003ff, 0x200001e8, 0 , 0, 16484 0x0 }, /* _POOL32A0~*(61) */ 16485 { instruction , 0 , 0 , 32, 16486 0xfc0003ff, 0x200001f0, &DMTGC0 , 0, 16487 CP0_ | MIPS64_ | VZ_}, /* DMTGC0 */ 16488 { reserved_block , 0 , 0 , 32, 16489 0xfc0003ff, 0x200001f8, 0 , 0, 16490 0x0 }, /* _POOL32A0~*(63) */ 16491 { reserved_block , 0 , 0 , 32, 16492 0xfc0003ff, 0x20000200, 0 , 0, 16493 0x0 }, /* _POOL32A0~*(64) */ 16494 { reserved_block , 0 , 0 , 32, 16495 0xfc0003ff, 0x20000208, 0 , 0, 16496 0x0 }, /* _POOL32A0~*(65) */ 16497 { pool , P_CMOVE , 2 , 32, 16498 0xfc0003ff, 0x20000210, 0 , 0, 16499 0x0 }, /* P.CMOVE */ 16500 { reserved_block , 0 , 0 , 32, 16501 0xfc0003ff, 0x20000218, 0 , 0, 16502 0x0 }, /* _POOL32A0~*(67) */ 16503 { reserved_block , 0 , 0 , 32, 16504 0xfc0003ff, 0x20000220, 0 , 0, 16505 0x0 }, /* _POOL32A0~*(68) */ 16506 { instruction , 0 , 0 , 32, 16507 0xfc0003ff, 0x20000228, &FORK , 0, 16508 MT_ }, /* FORK */ 16509 { instruction , 0 , 0 , 32, 16510 0xfc0003ff, 0x20000230, &MFTR , 0, 16511 MT_ }, /* MFTR */ 16512 { instruction , 0 , 0 , 32, 16513 0xfc0003ff, 0x20000238, &MFHTR , 0, 16514 MT_ }, /* MFHTR */ 16515 { reserved_block , 0 , 0 , 32, 16516 0xfc0003ff, 0x20000240, 0 , 0, 16517 0x0 }, /* _POOL32A0~*(72) */ 16518 { reserved_block , 0 , 0 , 32, 16519 0xfc0003ff, 0x20000248, 0 , 0, 16520 0x0 }, /* _POOL32A0~*(73) */ 16521 { instruction , 0 , 0 , 32, 16522 0xfc0003ff, 0x20000250, &AND_32_ , 0, 16523 0x0 }, /* AND[32] */ 16524 { reserved_block , 0 , 0 , 32, 16525 0xfc0003ff, 0x20000258, 0 , 0, 16526 0x0 }, /* _POOL32A0~*(75) */ 16527 { reserved_block , 0 , 0 , 32, 16528 0xfc0003ff, 0x20000260, 0 , 0, 16529 0x0 }, /* _POOL32A0~*(76) */ 16530 { instruction , 0 , 0 , 32, 16531 0xfc0003ff, 0x20000268, &YIELD , 0, 16532 MT_ }, /* YIELD */ 16533 { instruction , 0 , 0 , 32, 16534 0xfc0003ff, 0x20000270, &MTTR , 0, 16535 MT_ }, /* MTTR */ 16536 { instruction , 0 , 0 , 32, 16537 0xfc0003ff, 0x20000278, &MTHTR , 0, 16538 MT_ }, /* MTHTR */ 16539 { reserved_block , 0 , 0 , 32, 16540 0xfc0003ff, 0x20000280, 0 , 0, 16541 0x0 }, /* _POOL32A0~*(80) */ 16542 { reserved_block , 0 , 0 , 32, 16543 0xfc0003ff, 0x20000288, 0 , 0, 16544 0x0 }, /* _POOL32A0~*(81) */ 16545 { instruction , 0 , 0 , 32, 16546 0xfc0003ff, 0x20000290, &OR_32_ , 0, 16547 0x0 }, /* OR[32] */ 16548 { reserved_block , 0 , 0 , 32, 16549 0xfc0003ff, 0x20000298, 0 , 0, 16550 0x0 }, /* _POOL32A0~*(83) */ 16551 { reserved_block , 0 , 0 , 32, 16552 0xfc0003ff, 0x200002a0, 0 , 0, 16553 0x0 }, /* _POOL32A0~*(84) */ 16554 { reserved_block , 0 , 0 , 32, 16555 0xfc0003ff, 0x200002a8, 0 , 0, 16556 0x0 }, /* _POOL32A0~*(85) */ 16557 { pool , P_MT_VPE , 8 , 32, 16558 0xfc0003ff, 0x200002b0, 0 , 0, 16559 0x0 }, /* P.MT_VPE */ 16560 { reserved_block , 0 , 0 , 32, 16561 0xfc0003ff, 0x200002b8, 0 , 0, 16562 0x0 }, /* _POOL32A0~*(87) */ 16563 { reserved_block , 0 , 0 , 32, 16564 0xfc0003ff, 0x200002c0, 0 , 0, 16565 0x0 }, /* _POOL32A0~*(88) */ 16566 { reserved_block , 0 , 0 , 32, 16567 0xfc0003ff, 0x200002c8, 0 , 0, 16568 0x0 }, /* _POOL32A0~*(89) */ 16569 { instruction , 0 , 0 , 32, 16570 0xfc0003ff, 0x200002d0, &NOR , 0, 16571 0x0 }, /* NOR */ 16572 { reserved_block , 0 , 0 , 32, 16573 0xfc0003ff, 0x200002d8, 0 , 0, 16574 0x0 }, /* _POOL32A0~*(91) */ 16575 { reserved_block , 0 , 0 , 32, 16576 0xfc0003ff, 0x200002e0, 0 , 0, 16577 0x0 }, /* _POOL32A0~*(92) */ 16578 { reserved_block , 0 , 0 , 32, 16579 0xfc0003ff, 0x200002e8, 0 , 0, 16580 0x0 }, /* _POOL32A0~*(93) */ 16581 { reserved_block , 0 , 0 , 32, 16582 0xfc0003ff, 0x200002f0, 0 , 0, 16583 0x0 }, /* _POOL32A0~*(94) */ 16584 { reserved_block , 0 , 0 , 32, 16585 0xfc0003ff, 0x200002f8, 0 , 0, 16586 0x0 }, /* _POOL32A0~*(95) */ 16587 { reserved_block , 0 , 0 , 32, 16588 0xfc0003ff, 0x20000300, 0 , 0, 16589 0x0 }, /* _POOL32A0~*(96) */ 16590 { reserved_block , 0 , 0 , 32, 16591 0xfc0003ff, 0x20000308, 0 , 0, 16592 0x0 }, /* _POOL32A0~*(97) */ 16593 { instruction , 0 , 0 , 32, 16594 0xfc0003ff, 0x20000310, &XOR_32_ , 0, 16595 0x0 }, /* XOR[32] */ 16596 { reserved_block , 0 , 0 , 32, 16597 0xfc0003ff, 0x20000318, 0 , 0, 16598 0x0 }, /* _POOL32A0~*(99) */ 16599 { reserved_block , 0 , 0 , 32, 16600 0xfc0003ff, 0x20000320, 0 , 0, 16601 0x0 }, /* _POOL32A0~*(100) */ 16602 { reserved_block , 0 , 0 , 32, 16603 0xfc0003ff, 0x20000328, 0 , 0, 16604 0x0 }, /* _POOL32A0~*(101) */ 16605 { reserved_block , 0 , 0 , 32, 16606 0xfc0003ff, 0x20000330, 0 , 0, 16607 0x0 }, /* _POOL32A0~*(102) */ 16608 { reserved_block , 0 , 0 , 32, 16609 0xfc0003ff, 0x20000338, 0 , 0, 16610 0x0 }, /* _POOL32A0~*(103) */ 16611 { reserved_block , 0 , 0 , 32, 16612 0xfc0003ff, 0x20000340, 0 , 0, 16613 0x0 }, /* _POOL32A0~*(104) */ 16614 { reserved_block , 0 , 0 , 32, 16615 0xfc0003ff, 0x20000348, 0 , 0, 16616 0x0 }, /* _POOL32A0~*(105) */ 16617 { instruction , 0 , 0 , 32, 16618 0xfc0003ff, 0x20000350, &SLT , 0, 16619 0x0 }, /* SLT */ 16620 { reserved_block , 0 , 0 , 32, 16621 0xfc0003ff, 0x20000358, 0 , 0, 16622 0x0 }, /* _POOL32A0~*(107) */ 16623 { reserved_block , 0 , 0 , 32, 16624 0xfc0003ff, 0x20000360, 0 , 0, 16625 0x0 }, /* _POOL32A0~*(108) */ 16626 { reserved_block , 0 , 0 , 32, 16627 0xfc0003ff, 0x20000368, 0 , 0, 16628 0x0 }, /* _POOL32A0~*(109) */ 16629 { reserved_block , 0 , 0 , 32, 16630 0xfc0003ff, 0x20000370, 0 , 0, 16631 0x0 }, /* _POOL32A0~*(110) */ 16632 { reserved_block , 0 , 0 , 32, 16633 0xfc0003ff, 0x20000378, 0 , 0, 16634 0x0 }, /* _POOL32A0~*(111) */ 16635 { reserved_block , 0 , 0 , 32, 16636 0xfc0003ff, 0x20000380, 0 , 0, 16637 0x0 }, /* _POOL32A0~*(112) */ 16638 { reserved_block , 0 , 0 , 32, 16639 0xfc0003ff, 0x20000388, 0 , 0, 16640 0x0 }, /* _POOL32A0~*(113) */ 16641 { pool , P_SLTU , 2 , 32, 16642 0xfc0003ff, 0x20000390, 0 , 0, 16643 0x0 }, /* P.SLTU */ 16644 { reserved_block , 0 , 0 , 32, 16645 0xfc0003ff, 0x20000398, 0 , 0, 16646 0x0 }, /* _POOL32A0~*(115) */ 16647 { reserved_block , 0 , 0 , 32, 16648 0xfc0003ff, 0x200003a0, 0 , 0, 16649 0x0 }, /* _POOL32A0~*(116) */ 16650 { reserved_block , 0 , 0 , 32, 16651 0xfc0003ff, 0x200003a8, 0 , 0, 16652 0x0 }, /* _POOL32A0~*(117) */ 16653 { reserved_block , 0 , 0 , 32, 16654 0xfc0003ff, 0x200003b0, 0 , 0, 16655 0x0 }, /* _POOL32A0~*(118) */ 16656 { reserved_block , 0 , 0 , 32, 16657 0xfc0003ff, 0x200003b8, 0 , 0, 16658 0x0 }, /* _POOL32A0~*(119) */ 16659 { reserved_block , 0 , 0 , 32, 16660 0xfc0003ff, 0x200003c0, 0 , 0, 16661 0x0 }, /* _POOL32A0~*(120) */ 16662 { reserved_block , 0 , 0 , 32, 16663 0xfc0003ff, 0x200003c8, 0 , 0, 16664 0x0 }, /* _POOL32A0~*(121) */ 16665 { instruction , 0 , 0 , 32, 16666 0xfc0003ff, 0x200003d0, &SOV , 0, 16667 0x0 }, /* SOV */ 16668 { reserved_block , 0 , 0 , 32, 16669 0xfc0003ff, 0x200003d8, 0 , 0, 16670 0x0 }, /* _POOL32A0~*(123) */ 16671 { reserved_block , 0 , 0 , 32, 16672 0xfc0003ff, 0x200003e0, 0 , 0, 16673 0x0 }, /* _POOL32A0~*(124) */ 16674 { reserved_block , 0 , 0 , 32, 16675 0xfc0003ff, 0x200003e8, 0 , 0, 16676 0x0 }, /* _POOL32A0~*(125) */ 16677 { reserved_block , 0 , 0 , 32, 16678 0xfc0003ff, 0x200003f0, 0 , 0, 16679 0x0 }, /* _POOL32A0~*(126) */ 16680 { reserved_block , 0 , 0 , 32, 16681 0xfc0003ff, 0x200003f8, 0 , 0, 16682 0x0 }, /* _POOL32A0~*(127) */ 16683 }; 16684 16685 16686 static const Pool ADDQ__S__PH[2] = { 16687 { instruction , 0 , 0 , 32, 16688 0xfc0007ff, 0x2000000d, &ADDQ_PH , 0, 16689 DSP_ }, /* ADDQ.PH */ 16690 { instruction , 0 , 0 , 32, 16691 0xfc0007ff, 0x2000040d, &ADDQ_S_PH , 0, 16692 DSP_ }, /* ADDQ_S.PH */ 16693 }; 16694 16695 16696 static const Pool MUL__S__PH[2] = { 16697 { instruction , 0 , 0 , 32, 16698 0xfc0007ff, 0x2000002d, &MUL_PH , 0, 16699 DSP_ }, /* MUL.PH */ 16700 { instruction , 0 , 0 , 32, 16701 0xfc0007ff, 0x2000042d, &MUL_S_PH , 0, 16702 DSP_ }, /* MUL_S.PH */ 16703 }; 16704 16705 16706 static const Pool ADDQH__R__PH[2] = { 16707 { instruction , 0 , 0 , 32, 16708 0xfc0007ff, 0x2000004d, &ADDQH_PH , 0, 16709 DSP_ }, /* ADDQH.PH */ 16710 { instruction , 0 , 0 , 32, 16711 0xfc0007ff, 0x2000044d, &ADDQH_R_PH , 0, 16712 DSP_ }, /* ADDQH_R.PH */ 16713 }; 16714 16715 16716 static const Pool ADDQH__R__W[2] = { 16717 { instruction , 0 , 0 , 32, 16718 0xfc0007ff, 0x2000008d, &ADDQH_W , 0, 16719 DSP_ }, /* ADDQH.W */ 16720 { instruction , 0 , 0 , 32, 16721 0xfc0007ff, 0x2000048d, &ADDQH_R_W , 0, 16722 DSP_ }, /* ADDQH_R.W */ 16723 }; 16724 16725 16726 static const Pool ADDU__S__QB[2] = { 16727 { instruction , 0 , 0 , 32, 16728 0xfc0007ff, 0x200000cd, &ADDU_QB , 0, 16729 DSP_ }, /* ADDU.QB */ 16730 { instruction , 0 , 0 , 32, 16731 0xfc0007ff, 0x200004cd, &ADDU_S_QB , 0, 16732 DSP_ }, /* ADDU_S.QB */ 16733 }; 16734 16735 16736 static const Pool ADDU__S__PH[2] = { 16737 { instruction , 0 , 0 , 32, 16738 0xfc0007ff, 0x2000010d, &ADDU_PH , 0, 16739 DSP_ }, /* ADDU.PH */ 16740 { instruction , 0 , 0 , 32, 16741 0xfc0007ff, 0x2000050d, &ADDU_S_PH , 0, 16742 DSP_ }, /* ADDU_S.PH */ 16743 }; 16744 16745 16746 static const Pool ADDUH__R__QB[2] = { 16747 { instruction , 0 , 0 , 32, 16748 0xfc0007ff, 0x2000014d, &ADDUH_QB , 0, 16749 DSP_ }, /* ADDUH.QB */ 16750 { instruction , 0 , 0 , 32, 16751 0xfc0007ff, 0x2000054d, &ADDUH_R_QB , 0, 16752 DSP_ }, /* ADDUH_R.QB */ 16753 }; 16754 16755 16756 static const Pool SHRAV__R__PH[2] = { 16757 { instruction , 0 , 0 , 32, 16758 0xfc0007ff, 0x2000018d, &SHRAV_PH , 0, 16759 DSP_ }, /* SHRAV.PH */ 16760 { instruction , 0 , 0 , 32, 16761 0xfc0007ff, 0x2000058d, &SHRAV_R_PH , 0, 16762 DSP_ }, /* SHRAV_R.PH */ 16763 }; 16764 16765 16766 static const Pool SHRAV__R__QB[2] = { 16767 { instruction , 0 , 0 , 32, 16768 0xfc0007ff, 0x200001cd, &SHRAV_QB , 0, 16769 DSP_ }, /* SHRAV.QB */ 16770 { instruction , 0 , 0 , 32, 16771 0xfc0007ff, 0x200005cd, &SHRAV_R_QB , 0, 16772 DSP_ }, /* SHRAV_R.QB */ 16773 }; 16774 16775 16776 static const Pool SUBQ__S__PH[2] = { 16777 { instruction , 0 , 0 , 32, 16778 0xfc0007ff, 0x2000020d, &SUBQ_PH , 0, 16779 DSP_ }, /* SUBQ.PH */ 16780 { instruction , 0 , 0 , 32, 16781 0xfc0007ff, 0x2000060d, &SUBQ_S_PH , 0, 16782 DSP_ }, /* SUBQ_S.PH */ 16783 }; 16784 16785 16786 static const Pool SUBQH__R__PH[2] = { 16787 { instruction , 0 , 0 , 32, 16788 0xfc0007ff, 0x2000024d, &SUBQH_PH , 0, 16789 DSP_ }, /* SUBQH.PH */ 16790 { instruction , 0 , 0 , 32, 16791 0xfc0007ff, 0x2000064d, &SUBQH_R_PH , 0, 16792 DSP_ }, /* SUBQH_R.PH */ 16793 }; 16794 16795 16796 static const Pool SUBQH__R__W[2] = { 16797 { instruction , 0 , 0 , 32, 16798 0xfc0007ff, 0x2000028d, &SUBQH_W , 0, 16799 DSP_ }, /* SUBQH.W */ 16800 { instruction , 0 , 0 , 32, 16801 0xfc0007ff, 0x2000068d, &SUBQH_R_W , 0, 16802 DSP_ }, /* SUBQH_R.W */ 16803 }; 16804 16805 16806 static const Pool SUBU__S__QB[2] = { 16807 { instruction , 0 , 0 , 32, 16808 0xfc0007ff, 0x200002cd, &SUBU_QB , 0, 16809 DSP_ }, /* SUBU.QB */ 16810 { instruction , 0 , 0 , 32, 16811 0xfc0007ff, 0x200006cd, &SUBU_S_QB , 0, 16812 DSP_ }, /* SUBU_S.QB */ 16813 }; 16814 16815 16816 static const Pool SUBU__S__PH[2] = { 16817 { instruction , 0 , 0 , 32, 16818 0xfc0007ff, 0x2000030d, &SUBU_PH , 0, 16819 DSP_ }, /* SUBU.PH */ 16820 { instruction , 0 , 0 , 32, 16821 0xfc0007ff, 0x2000070d, &SUBU_S_PH , 0, 16822 DSP_ }, /* SUBU_S.PH */ 16823 }; 16824 16825 16826 static const Pool SHRA__R__PH[2] = { 16827 { instruction , 0 , 0 , 32, 16828 0xfc0007ff, 0x20000335, &SHRA_PH , 0, 16829 DSP_ }, /* SHRA.PH */ 16830 { instruction , 0 , 0 , 32, 16831 0xfc0007ff, 0x20000735, &SHRA_R_PH , 0, 16832 DSP_ }, /* SHRA_R.PH */ 16833 }; 16834 16835 16836 static const Pool SUBUH__R__QB[2] = { 16837 { instruction , 0 , 0 , 32, 16838 0xfc0007ff, 0x2000034d, &SUBUH_QB , 0, 16839 DSP_ }, /* SUBUH.QB */ 16840 { instruction , 0 , 0 , 32, 16841 0xfc0007ff, 0x2000074d, &SUBUH_R_QB , 0, 16842 DSP_ }, /* SUBUH_R.QB */ 16843 }; 16844 16845 16846 static const Pool SHLLV__S__PH[2] = { 16847 { instruction , 0 , 0 , 32, 16848 0xfc0007ff, 0x2000038d, &SHLLV_PH , 0, 16849 DSP_ }, /* SHLLV.PH */ 16850 { instruction , 0 , 0 , 32, 16851 0xfc0007ff, 0x2000078d, &SHLLV_S_PH , 0, 16852 DSP_ }, /* SHLLV_S.PH */ 16853 }; 16854 16855 16856 static const Pool SHLL__S__PH[4] = { 16857 { instruction , 0 , 0 , 32, 16858 0xfc000fff, 0x200003b5, &SHLL_PH , 0, 16859 DSP_ }, /* SHLL.PH */ 16860 { reserved_block , 0 , 0 , 32, 16861 0xfc000fff, 0x200007b5, 0 , 0, 16862 0x0 }, /* SHLL[_S].PH~*(1) */ 16863 { instruction , 0 , 0 , 32, 16864 0xfc000fff, 0x20000bb5, &SHLL_S_PH , 0, 16865 DSP_ }, /* SHLL_S.PH */ 16866 { reserved_block , 0 , 0 , 32, 16867 0xfc000fff, 0x20000fb5, 0 , 0, 16868 0x0 }, /* SHLL[_S].PH~*(3) */ 16869 }; 16870 16871 16872 static const Pool PRECR_SRA__R__PH_W[2] = { 16873 { instruction , 0 , 0 , 32, 16874 0xfc0007ff, 0x200003cd, &PRECR_SRA_PH_W , 0, 16875 DSP_ }, /* PRECR_SRA.PH.W */ 16876 { instruction , 0 , 0 , 32, 16877 0xfc0007ff, 0x200007cd, &PRECR_SRA_R_PH_W , 0, 16878 DSP_ }, /* PRECR_SRA_R.PH.W */ 16879 }; 16880 16881 16882 static const Pool _POOL32A5[128] = { 16883 { instruction , 0 , 0 , 32, 16884 0xfc0003ff, 0x20000005, &CMP_EQ_PH , 0, 16885 DSP_ }, /* CMP.EQ.PH */ 16886 { pool , ADDQ__S__PH , 2 , 32, 16887 0xfc0003ff, 0x2000000d, 0 , 0, 16888 0x0 }, /* ADDQ[_S].PH */ 16889 { reserved_block , 0 , 0 , 32, 16890 0xfc0003ff, 0x20000015, 0 , 0, 16891 0x0 }, /* _POOL32A5~*(2) */ 16892 { instruction , 0 , 0 , 32, 16893 0xfc0003ff, 0x2000001d, &SHILO , 0, 16894 DSP_ }, /* SHILO */ 16895 { instruction , 0 , 0 , 32, 16896 0xfc0003ff, 0x20000025, &MULEQ_S_W_PHL , 0, 16897 DSP_ }, /* MULEQ_S.W.PHL */ 16898 { pool , MUL__S__PH , 2 , 32, 16899 0xfc0003ff, 0x2000002d, 0 , 0, 16900 0x0 }, /* MUL[_S].PH */ 16901 { reserved_block , 0 , 0 , 32, 16902 0xfc0003ff, 0x20000035, 0 , 0, 16903 0x0 }, /* _POOL32A5~*(6) */ 16904 { instruction , 0 , 0 , 32, 16905 0xfc0003ff, 0x2000003d, &REPL_PH , 0, 16906 DSP_ }, /* REPL.PH */ 16907 { instruction , 0 , 0 , 32, 16908 0xfc0003ff, 0x20000045, &CMP_LT_PH , 0, 16909 DSP_ }, /* CMP.LT.PH */ 16910 { pool , ADDQH__R__PH , 2 , 32, 16911 0xfc0003ff, 0x2000004d, 0 , 0, 16912 0x0 }, /* ADDQH[_R].PH */ 16913 { reserved_block , 0 , 0 , 32, 16914 0xfc0003ff, 0x20000055, 0 , 0, 16915 0x0 }, /* _POOL32A5~*(10) */ 16916 { reserved_block , 0 , 0 , 32, 16917 0xfc0003ff, 0x2000005d, 0 , 0, 16918 0x0 }, /* _POOL32A5~*(11) */ 16919 { instruction , 0 , 0 , 32, 16920 0xfc0003ff, 0x20000065, &MULEQ_S_W_PHR , 0, 16921 DSP_ }, /* MULEQ_S.W.PHR */ 16922 { instruction , 0 , 0 , 32, 16923 0xfc0003ff, 0x2000006d, &PRECR_QB_PH , 0, 16924 DSP_ }, /* PRECR.QB.PH */ 16925 { reserved_block , 0 , 0 , 32, 16926 0xfc0003ff, 0x20000075, 0 , 0, 16927 0x0 }, /* _POOL32A5~*(14) */ 16928 { reserved_block , 0 , 0 , 32, 16929 0xfc0003ff, 0x2000007d, 0 , 0, 16930 0x0 }, /* _POOL32A5~*(15) */ 16931 { instruction , 0 , 0 , 32, 16932 0xfc0003ff, 0x20000085, &CMP_LE_PH , 0, 16933 DSP_ }, /* CMP.LE.PH */ 16934 { pool , ADDQH__R__W , 2 , 32, 16935 0xfc0003ff, 0x2000008d, 0 , 0, 16936 0x0 }, /* ADDQH[_R].W */ 16937 { instruction , 0 , 0 , 32, 16938 0xfc0003ff, 0x20000095, &MULEU_S_PH_QBL , 0, 16939 DSP_ }, /* MULEU_S.PH.QBL */ 16940 { reserved_block , 0 , 0 , 32, 16941 0xfc0003ff, 0x2000009d, 0 , 0, 16942 0x0 }, /* _POOL32A5~*(19) */ 16943 { reserved_block , 0 , 0 , 32, 16944 0xfc0003ff, 0x200000a5, 0 , 0, 16945 0x0 }, /* _POOL32A5~*(20) */ 16946 { instruction , 0 , 0 , 32, 16947 0xfc0003ff, 0x200000ad, &PRECRQ_QB_PH , 0, 16948 DSP_ }, /* PRECRQ.QB.PH */ 16949 { reserved_block , 0 , 0 , 32, 16950 0xfc0003ff, 0x200000b5, 0 , 0, 16951 0x0 }, /* _POOL32A5~*(22) */ 16952 { reserved_block , 0 , 0 , 32, 16953 0xfc0003ff, 0x200000bd, 0 , 0, 16954 0x0 }, /* _POOL32A5~*(23) */ 16955 { instruction , 0 , 0 , 32, 16956 0xfc0003ff, 0x200000c5, &CMPGU_EQ_QB , 0, 16957 DSP_ }, /* CMPGU.EQ.QB */ 16958 { pool , ADDU__S__QB , 2 , 32, 16959 0xfc0003ff, 0x200000cd, 0 , 0, 16960 0x0 }, /* ADDU[_S].QB */ 16961 { instruction , 0 , 0 , 32, 16962 0xfc0003ff, 0x200000d5, &MULEU_S_PH_QBR , 0, 16963 DSP_ }, /* MULEU_S.PH.QBR */ 16964 { reserved_block , 0 , 0 , 32, 16965 0xfc0003ff, 0x200000dd, 0 , 0, 16966 0x0 }, /* _POOL32A5~*(27) */ 16967 { reserved_block , 0 , 0 , 32, 16968 0xfc0003ff, 0x200000e5, 0 , 0, 16969 0x0 }, /* _POOL32A5~*(28) */ 16970 { instruction , 0 , 0 , 32, 16971 0xfc0003ff, 0x200000ed, &PRECRQ_PH_W , 0, 16972 DSP_ }, /* PRECRQ.PH.W */ 16973 { reserved_block , 0 , 0 , 32, 16974 0xfc0003ff, 0x200000f5, 0 , 0, 16975 0x0 }, /* _POOL32A5~*(30) */ 16976 { reserved_block , 0 , 0 , 32, 16977 0xfc0003ff, 0x200000fd, 0 , 0, 16978 0x0 }, /* _POOL32A5~*(31) */ 16979 { instruction , 0 , 0 , 32, 16980 0xfc0003ff, 0x20000105, &CMPGU_LT_QB , 0, 16981 DSP_ }, /* CMPGU.LT.QB */ 16982 { pool , ADDU__S__PH , 2 , 32, 16983 0xfc0003ff, 0x2000010d, 0 , 0, 16984 0x0 }, /* ADDU[_S].PH */ 16985 { instruction , 0 , 0 , 32, 16986 0xfc0003ff, 0x20000115, &MULQ_RS_PH , 0, 16987 DSP_ }, /* MULQ_RS.PH */ 16988 { reserved_block , 0 , 0 , 32, 16989 0xfc0003ff, 0x2000011d, 0 , 0, 16990 0x0 }, /* _POOL32A5~*(35) */ 16991 { reserved_block , 0 , 0 , 32, 16992 0xfc0003ff, 0x20000125, 0 , 0, 16993 0x0 }, /* _POOL32A5~*(36) */ 16994 { instruction , 0 , 0 , 32, 16995 0xfc0003ff, 0x2000012d, &PRECRQ_RS_PH_W , 0, 16996 DSP_ }, /* PRECRQ_RS.PH.W */ 16997 { reserved_block , 0 , 0 , 32, 16998 0xfc0003ff, 0x20000135, 0 , 0, 16999 0x0 }, /* _POOL32A5~*(38) */ 17000 { reserved_block , 0 , 0 , 32, 17001 0xfc0003ff, 0x2000013d, 0 , 0, 17002 0x0 }, /* _POOL32A5~*(39) */ 17003 { instruction , 0 , 0 , 32, 17004 0xfc0003ff, 0x20000145, &CMPGU_LE_QB , 0, 17005 DSP_ }, /* CMPGU.LE.QB */ 17006 { pool , ADDUH__R__QB , 2 , 32, 17007 0xfc0003ff, 0x2000014d, 0 , 0, 17008 0x0 }, /* ADDUH[_R].QB */ 17009 { instruction , 0 , 0 , 32, 17010 0xfc0003ff, 0x20000155, &MULQ_S_PH , 0, 17011 DSP_ }, /* MULQ_S.PH */ 17012 { reserved_block , 0 , 0 , 32, 17013 0xfc0003ff, 0x2000015d, 0 , 0, 17014 0x0 }, /* _POOL32A5~*(43) */ 17015 { reserved_block , 0 , 0 , 32, 17016 0xfc0003ff, 0x20000165, 0 , 0, 17017 0x0 }, /* _POOL32A5~*(44) */ 17018 { instruction , 0 , 0 , 32, 17019 0xfc0003ff, 0x2000016d, &PRECRQU_S_QB_PH , 0, 17020 DSP_ }, /* PRECRQU_S.QB.PH */ 17021 { reserved_block , 0 , 0 , 32, 17022 0xfc0003ff, 0x20000175, 0 , 0, 17023 0x0 }, /* _POOL32A5~*(46) */ 17024 { reserved_block , 0 , 0 , 32, 17025 0xfc0003ff, 0x2000017d, 0 , 0, 17026 0x0 }, /* _POOL32A5~*(47) */ 17027 { instruction , 0 , 0 , 32, 17028 0xfc0003ff, 0x20000185, &CMPGDU_EQ_QB , 0, 17029 DSP_ }, /* CMPGDU.EQ.QB */ 17030 { pool , SHRAV__R__PH , 2 , 32, 17031 0xfc0003ff, 0x2000018d, 0 , 0, 17032 0x0 }, /* SHRAV[_R].PH */ 17033 { instruction , 0 , 0 , 32, 17034 0xfc0003ff, 0x20000195, &MULQ_RS_W , 0, 17035 DSP_ }, /* MULQ_RS.W */ 17036 { reserved_block , 0 , 0 , 32, 17037 0xfc0003ff, 0x2000019d, 0 , 0, 17038 0x0 }, /* _POOL32A5~*(51) */ 17039 { reserved_block , 0 , 0 , 32, 17040 0xfc0003ff, 0x200001a5, 0 , 0, 17041 0x0 }, /* _POOL32A5~*(52) */ 17042 { instruction , 0 , 0 , 32, 17043 0xfc0003ff, 0x200001ad, &PACKRL_PH , 0, 17044 DSP_ }, /* PACKRL.PH */ 17045 { reserved_block , 0 , 0 , 32, 17046 0xfc0003ff, 0x200001b5, 0 , 0, 17047 0x0 }, /* _POOL32A5~*(54) */ 17048 { reserved_block , 0 , 0 , 32, 17049 0xfc0003ff, 0x200001bd, 0 , 0, 17050 0x0 }, /* _POOL32A5~*(55) */ 17051 { instruction , 0 , 0 , 32, 17052 0xfc0003ff, 0x200001c5, &CMPGDU_LT_QB , 0, 17053 DSP_ }, /* CMPGDU.LT.QB */ 17054 { pool , SHRAV__R__QB , 2 , 32, 17055 0xfc0003ff, 0x200001cd, 0 , 0, 17056 0x0 }, /* SHRAV[_R].QB */ 17057 { instruction , 0 , 0 , 32, 17058 0xfc0003ff, 0x200001d5, &MULQ_S_W , 0, 17059 DSP_ }, /* MULQ_S.W */ 17060 { reserved_block , 0 , 0 , 32, 17061 0xfc0003ff, 0x200001dd, 0 , 0, 17062 0x0 }, /* _POOL32A5~*(59) */ 17063 { reserved_block , 0 , 0 , 32, 17064 0xfc0003ff, 0x200001e5, 0 , 0, 17065 0x0 }, /* _POOL32A5~*(60) */ 17066 { instruction , 0 , 0 , 32, 17067 0xfc0003ff, 0x200001ed, &PICK_QB , 0, 17068 DSP_ }, /* PICK.QB */ 17069 { reserved_block , 0 , 0 , 32, 17070 0xfc0003ff, 0x200001f5, 0 , 0, 17071 0x0 }, /* _POOL32A5~*(62) */ 17072 { reserved_block , 0 , 0 , 32, 17073 0xfc0003ff, 0x200001fd, 0 , 0, 17074 0x0 }, /* _POOL32A5~*(63) */ 17075 { instruction , 0 , 0 , 32, 17076 0xfc0003ff, 0x20000205, &CMPGDU_LE_QB , 0, 17077 DSP_ }, /* CMPGDU.LE.QB */ 17078 { pool , SUBQ__S__PH , 2 , 32, 17079 0xfc0003ff, 0x2000020d, 0 , 0, 17080 0x0 }, /* SUBQ[_S].PH */ 17081 { instruction , 0 , 0 , 32, 17082 0xfc0003ff, 0x20000215, &APPEND , 0, 17083 DSP_ }, /* APPEND */ 17084 { reserved_block , 0 , 0 , 32, 17085 0xfc0003ff, 0x2000021d, 0 , 0, 17086 0x0 }, /* _POOL32A5~*(67) */ 17087 { reserved_block , 0 , 0 , 32, 17088 0xfc0003ff, 0x20000225, 0 , 0, 17089 0x0 }, /* _POOL32A5~*(68) */ 17090 { instruction , 0 , 0 , 32, 17091 0xfc0003ff, 0x2000022d, &PICK_PH , 0, 17092 DSP_ }, /* PICK.PH */ 17093 { reserved_block , 0 , 0 , 32, 17094 0xfc0003ff, 0x20000235, 0 , 0, 17095 0x0 }, /* _POOL32A5~*(70) */ 17096 { reserved_block , 0 , 0 , 32, 17097 0xfc0003ff, 0x2000023d, 0 , 0, 17098 0x0 }, /* _POOL32A5~*(71) */ 17099 { instruction , 0 , 0 , 32, 17100 0xfc0003ff, 0x20000245, &CMPU_EQ_QB , 0, 17101 DSP_ }, /* CMPU.EQ.QB */ 17102 { pool , SUBQH__R__PH , 2 , 32, 17103 0xfc0003ff, 0x2000024d, 0 , 0, 17104 0x0 }, /* SUBQH[_R].PH */ 17105 { instruction , 0 , 0 , 32, 17106 0xfc0003ff, 0x20000255, &PREPEND , 0, 17107 DSP_ }, /* PREPEND */ 17108 { reserved_block , 0 , 0 , 32, 17109 0xfc0003ff, 0x2000025d, 0 , 0, 17110 0x0 }, /* _POOL32A5~*(75) */ 17111 { reserved_block , 0 , 0 , 32, 17112 0xfc0003ff, 0x20000265, 0 , 0, 17113 0x0 }, /* _POOL32A5~*(76) */ 17114 { reserved_block , 0 , 0 , 32, 17115 0xfc0003ff, 0x2000026d, 0 , 0, 17116 0x0 }, /* _POOL32A5~*(77) */ 17117 { reserved_block , 0 , 0 , 32, 17118 0xfc0003ff, 0x20000275, 0 , 0, 17119 0x0 }, /* _POOL32A5~*(78) */ 17120 { reserved_block , 0 , 0 , 32, 17121 0xfc0003ff, 0x2000027d, 0 , 0, 17122 0x0 }, /* _POOL32A5~*(79) */ 17123 { instruction , 0 , 0 , 32, 17124 0xfc0003ff, 0x20000285, &CMPU_LT_QB , 0, 17125 DSP_ }, /* CMPU.LT.QB */ 17126 { pool , SUBQH__R__W , 2 , 32, 17127 0xfc0003ff, 0x2000028d, 0 , 0, 17128 0x0 }, /* SUBQH[_R].W */ 17129 { instruction , 0 , 0 , 32, 17130 0xfc0003ff, 0x20000295, &MODSUB , 0, 17131 DSP_ }, /* MODSUB */ 17132 { reserved_block , 0 , 0 , 32, 17133 0xfc0003ff, 0x2000029d, 0 , 0, 17134 0x0 }, /* _POOL32A5~*(83) */ 17135 { reserved_block , 0 , 0 , 32, 17136 0xfc0003ff, 0x200002a5, 0 , 0, 17137 0x0 }, /* _POOL32A5~*(84) */ 17138 { reserved_block , 0 , 0 , 32, 17139 0xfc0003ff, 0x200002ad, 0 , 0, 17140 0x0 }, /* _POOL32A5~*(85) */ 17141 { reserved_block , 0 , 0 , 32, 17142 0xfc0003ff, 0x200002b5, 0 , 0, 17143 0x0 }, /* _POOL32A5~*(86) */ 17144 { reserved_block , 0 , 0 , 32, 17145 0xfc0003ff, 0x200002bd, 0 , 0, 17146 0x0 }, /* _POOL32A5~*(87) */ 17147 { instruction , 0 , 0 , 32, 17148 0xfc0003ff, 0x200002c5, &CMPU_LE_QB , 0, 17149 DSP_ }, /* CMPU.LE.QB */ 17150 { pool , SUBU__S__QB , 2 , 32, 17151 0xfc0003ff, 0x200002cd, 0 , 0, 17152 0x0 }, /* SUBU[_S].QB */ 17153 { instruction , 0 , 0 , 32, 17154 0xfc0003ff, 0x200002d5, &SHRAV_R_W , 0, 17155 DSP_ }, /* SHRAV_R.W */ 17156 { reserved_block , 0 , 0 , 32, 17157 0xfc0003ff, 0x200002dd, 0 , 0, 17158 0x0 }, /* _POOL32A5~*(91) */ 17159 { reserved_block , 0 , 0 , 32, 17160 0xfc0003ff, 0x200002e5, 0 , 0, 17161 0x0 }, /* _POOL32A5~*(92) */ 17162 { reserved_block , 0 , 0 , 32, 17163 0xfc0003ff, 0x200002ed, 0 , 0, 17164 0x0 }, /* _POOL32A5~*(93) */ 17165 { instruction , 0 , 0 , 32, 17166 0xfc0003ff, 0x200002f5, &SHRA_R_W , 0, 17167 DSP_ }, /* SHRA_R.W */ 17168 { reserved_block , 0 , 0 , 32, 17169 0xfc0003ff, 0x200002fd, 0 , 0, 17170 0x0 }, /* _POOL32A5~*(95) */ 17171 { instruction , 0 , 0 , 32, 17172 0xfc0003ff, 0x20000305, &ADDQ_S_W , 0, 17173 DSP_ }, /* ADDQ_S.W */ 17174 { pool , SUBU__S__PH , 2 , 32, 17175 0xfc0003ff, 0x2000030d, 0 , 0, 17176 0x0 }, /* SUBU[_S].PH */ 17177 { instruction , 0 , 0 , 32, 17178 0xfc0003ff, 0x20000315, &SHRLV_PH , 0, 17179 DSP_ }, /* SHRLV.PH */ 17180 { reserved_block , 0 , 0 , 32, 17181 0xfc0003ff, 0x2000031d, 0 , 0, 17182 0x0 }, /* _POOL32A5~*(99) */ 17183 { reserved_block , 0 , 0 , 32, 17184 0xfc0003ff, 0x20000325, 0 , 0, 17185 0x0 }, /* _POOL32A5~*(100) */ 17186 { reserved_block , 0 , 0 , 32, 17187 0xfc0003ff, 0x2000032d, 0 , 0, 17188 0x0 }, /* _POOL32A5~*(101) */ 17189 { pool , SHRA__R__PH , 2 , 32, 17190 0xfc0003ff, 0x20000335, 0 , 0, 17191 0x0 }, /* SHRA[_R].PH */ 17192 { reserved_block , 0 , 0 , 32, 17193 0xfc0003ff, 0x2000033d, 0 , 0, 17194 0x0 }, /* _POOL32A5~*(103) */ 17195 { instruction , 0 , 0 , 32, 17196 0xfc0003ff, 0x20000345, &SUBQ_S_W , 0, 17197 DSP_ }, /* SUBQ_S.W */ 17198 { pool , SUBUH__R__QB , 2 , 32, 17199 0xfc0003ff, 0x2000034d, 0 , 0, 17200 0x0 }, /* SUBUH[_R].QB */ 17201 { instruction , 0 , 0 , 32, 17202 0xfc0003ff, 0x20000355, &SHRLV_QB , 0, 17203 DSP_ }, /* SHRLV.QB */ 17204 { reserved_block , 0 , 0 , 32, 17205 0xfc0003ff, 0x2000035d, 0 , 0, 17206 0x0 }, /* _POOL32A5~*(107) */ 17207 { reserved_block , 0 , 0 , 32, 17208 0xfc0003ff, 0x20000365, 0 , 0, 17209 0x0 }, /* _POOL32A5~*(108) */ 17210 { reserved_block , 0 , 0 , 32, 17211 0xfc0003ff, 0x2000036d, 0 , 0, 17212 0x0 }, /* _POOL32A5~*(109) */ 17213 { reserved_block , 0 , 0 , 32, 17214 0xfc0003ff, 0x20000375, 0 , 0, 17215 0x0 }, /* _POOL32A5~*(110) */ 17216 { reserved_block , 0 , 0 , 32, 17217 0xfc0003ff, 0x2000037d, 0 , 0, 17218 0x0 }, /* _POOL32A5~*(111) */ 17219 { instruction , 0 , 0 , 32, 17220 0xfc0003ff, 0x20000385, &ADDSC , 0, 17221 DSP_ }, /* ADDSC */ 17222 { pool , SHLLV__S__PH , 2 , 32, 17223 0xfc0003ff, 0x2000038d, 0 , 0, 17224 0x0 }, /* SHLLV[_S].PH */ 17225 { instruction , 0 , 0 , 32, 17226 0xfc0003ff, 0x20000395, &SHLLV_QB , 0, 17227 DSP_ }, /* SHLLV.QB */ 17228 { reserved_block , 0 , 0 , 32, 17229 0xfc0003ff, 0x2000039d, 0 , 0, 17230 0x0 }, /* _POOL32A5~*(115) */ 17231 { reserved_block , 0 , 0 , 32, 17232 0xfc0003ff, 0x200003a5, 0 , 0, 17233 0x0 }, /* _POOL32A5~*(116) */ 17234 { reserved_block , 0 , 0 , 32, 17235 0xfc0003ff, 0x200003ad, 0 , 0, 17236 0x0 }, /* _POOL32A5~*(117) */ 17237 { pool , SHLL__S__PH , 4 , 32, 17238 0xfc0003ff, 0x200003b5, 0 , 0, 17239 0x0 }, /* SHLL[_S].PH */ 17240 { reserved_block , 0 , 0 , 32, 17241 0xfc0003ff, 0x200003bd, 0 , 0, 17242 0x0 }, /* _POOL32A5~*(119) */ 17243 { instruction , 0 , 0 , 32, 17244 0xfc0003ff, 0x200003c5, &ADDWC , 0, 17245 DSP_ }, /* ADDWC */ 17246 { pool , PRECR_SRA__R__PH_W , 2 , 32, 17247 0xfc0003ff, 0x200003cd, 0 , 0, 17248 0x0 }, /* PRECR_SRA[_R].PH.W */ 17249 { instruction , 0 , 0 , 32, 17250 0xfc0003ff, 0x200003d5, &SHLLV_S_W , 0, 17251 DSP_ }, /* SHLLV_S.W */ 17252 { reserved_block , 0 , 0 , 32, 17253 0xfc0003ff, 0x200003dd, 0 , 0, 17254 0x0 }, /* _POOL32A5~*(123) */ 17255 { reserved_block , 0 , 0 , 32, 17256 0xfc0003ff, 0x200003e5, 0 , 0, 17257 0x0 }, /* _POOL32A5~*(124) */ 17258 { reserved_block , 0 , 0 , 32, 17259 0xfc0003ff, 0x200003ed, 0 , 0, 17260 0x0 }, /* _POOL32A5~*(125) */ 17261 { instruction , 0 , 0 , 32, 17262 0xfc0003ff, 0x200003f5, &SHLL_S_W , 0, 17263 DSP_ }, /* SHLL_S.W */ 17264 { reserved_block , 0 , 0 , 32, 17265 0xfc0003ff, 0x200003fd, 0 , 0, 17266 0x0 }, /* _POOL32A5~*(127) */ 17267 }; 17268 17269 17270 static const Pool PP_LSX[16] = { 17271 { instruction , 0 , 0 , 32, 17272 0xfc0007ff, 0x20000007, &LBX , 0, 17273 0x0 }, /* LBX */ 17274 { instruction , 0 , 0 , 32, 17275 0xfc0007ff, 0x20000087, &SBX , 0, 17276 XMMS_ }, /* SBX */ 17277 { instruction , 0 , 0 , 32, 17278 0xfc0007ff, 0x20000107, &LBUX , 0, 17279 0x0 }, /* LBUX */ 17280 { reserved_block , 0 , 0 , 32, 17281 0xfc0007ff, 0x20000187, 0 , 0, 17282 0x0 }, /* PP.LSX~*(3) */ 17283 { instruction , 0 , 0 , 32, 17284 0xfc0007ff, 0x20000207, &LHX , 0, 17285 0x0 }, /* LHX */ 17286 { instruction , 0 , 0 , 32, 17287 0xfc0007ff, 0x20000287, &SHX , 0, 17288 XMMS_ }, /* SHX */ 17289 { instruction , 0 , 0 , 32, 17290 0xfc0007ff, 0x20000307, &LHUX , 0, 17291 0x0 }, /* LHUX */ 17292 { instruction , 0 , 0 , 32, 17293 0xfc0007ff, 0x20000387, &LWUX , 0, 17294 MIPS64_ }, /* LWUX */ 17295 { instruction , 0 , 0 , 32, 17296 0xfc0007ff, 0x20000407, &LWX , 0, 17297 0x0 }, /* LWX */ 17298 { instruction , 0 , 0 , 32, 17299 0xfc0007ff, 0x20000487, &SWX , 0, 17300 XMMS_ }, /* SWX */ 17301 { instruction , 0 , 0 , 32, 17302 0xfc0007ff, 0x20000507, &LWC1X , 0, 17303 CP1_ }, /* LWC1X */ 17304 { instruction , 0 , 0 , 32, 17305 0xfc0007ff, 0x20000587, &SWC1X , 0, 17306 CP1_ }, /* SWC1X */ 17307 { instruction , 0 , 0 , 32, 17308 0xfc0007ff, 0x20000607, &LDX , 0, 17309 MIPS64_ }, /* LDX */ 17310 { instruction , 0 , 0 , 32, 17311 0xfc0007ff, 0x20000687, &SDX , 0, 17312 MIPS64_ }, /* SDX */ 17313 { instruction , 0 , 0 , 32, 17314 0xfc0007ff, 0x20000707, &LDC1X , 0, 17315 CP1_ }, /* LDC1X */ 17316 { instruction , 0 , 0 , 32, 17317 0xfc0007ff, 0x20000787, &SDC1X , 0, 17318 CP1_ }, /* SDC1X */ 17319 }; 17320 17321 17322 static const Pool PP_LSXS[16] = { 17323 { reserved_block , 0 , 0 , 32, 17324 0xfc0007ff, 0x20000047, 0 , 0, 17325 0x0 }, /* PP.LSXS~*(0) */ 17326 { reserved_block , 0 , 0 , 32, 17327 0xfc0007ff, 0x200000c7, 0 , 0, 17328 0x0 }, /* PP.LSXS~*(1) */ 17329 { reserved_block , 0 , 0 , 32, 17330 0xfc0007ff, 0x20000147, 0 , 0, 17331 0x0 }, /* PP.LSXS~*(2) */ 17332 { reserved_block , 0 , 0 , 32, 17333 0xfc0007ff, 0x200001c7, 0 , 0, 17334 0x0 }, /* PP.LSXS~*(3) */ 17335 { instruction , 0 , 0 , 32, 17336 0xfc0007ff, 0x20000247, &LHXS , 0, 17337 0x0 }, /* LHXS */ 17338 { instruction , 0 , 0 , 32, 17339 0xfc0007ff, 0x200002c7, &SHXS , 0, 17340 XMMS_ }, /* SHXS */ 17341 { instruction , 0 , 0 , 32, 17342 0xfc0007ff, 0x20000347, &LHUXS , 0, 17343 0x0 }, /* LHUXS */ 17344 { instruction , 0 , 0 , 32, 17345 0xfc0007ff, 0x200003c7, &LWUXS , 0, 17346 MIPS64_ }, /* LWUXS */ 17347 { instruction , 0 , 0 , 32, 17348 0xfc0007ff, 0x20000447, &LWXS_32_ , 0, 17349 0x0 }, /* LWXS[32] */ 17350 { instruction , 0 , 0 , 32, 17351 0xfc0007ff, 0x200004c7, &SWXS , 0, 17352 XMMS_ }, /* SWXS */ 17353 { instruction , 0 , 0 , 32, 17354 0xfc0007ff, 0x20000547, &LWC1XS , 0, 17355 CP1_ }, /* LWC1XS */ 17356 { instruction , 0 , 0 , 32, 17357 0xfc0007ff, 0x200005c7, &SWC1XS , 0, 17358 CP1_ }, /* SWC1XS */ 17359 { instruction , 0 , 0 , 32, 17360 0xfc0007ff, 0x20000647, &LDXS , 0, 17361 MIPS64_ }, /* LDXS */ 17362 { instruction , 0 , 0 , 32, 17363 0xfc0007ff, 0x200006c7, &SDXS , 0, 17364 MIPS64_ }, /* SDXS */ 17365 { instruction , 0 , 0 , 32, 17366 0xfc0007ff, 0x20000747, &LDC1XS , 0, 17367 CP1_ }, /* LDC1XS */ 17368 { instruction , 0 , 0 , 32, 17369 0xfc0007ff, 0x200007c7, &SDC1XS , 0, 17370 CP1_ }, /* SDC1XS */ 17371 }; 17372 17373 17374 static const Pool P_LSX[2] = { 17375 { pool , PP_LSX , 16 , 32, 17376 0xfc00007f, 0x20000007, 0 , 0, 17377 0x0 }, /* PP.LSX */ 17378 { pool , PP_LSXS , 16 , 32, 17379 0xfc00007f, 0x20000047, 0 , 0, 17380 0x0 }, /* PP.LSXS */ 17381 }; 17382 17383 17384 static const Pool POOL32Axf_1_0[4] = { 17385 { instruction , 0 , 0 , 32, 17386 0xfc003fff, 0x2000007f, &MFHI_DSP_ , 0, 17387 DSP_ }, /* MFHI[DSP] */ 17388 { instruction , 0 , 0 , 32, 17389 0xfc003fff, 0x2000107f, &MFLO_DSP_ , 0, 17390 DSP_ }, /* MFLO[DSP] */ 17391 { instruction , 0 , 0 , 32, 17392 0xfc003fff, 0x2000207f, &MTHI_DSP_ , 0, 17393 DSP_ }, /* MTHI[DSP] */ 17394 { instruction , 0 , 0 , 32, 17395 0xfc003fff, 0x2000307f, &MTLO_DSP_ , 0, 17396 DSP_ }, /* MTLO[DSP] */ 17397 }; 17398 17399 17400 static const Pool POOL32Axf_1_1[4] = { 17401 { instruction , 0 , 0 , 32, 17402 0xfc003fff, 0x2000027f, &MTHLIP , 0, 17403 DSP_ }, /* MTHLIP */ 17404 { instruction , 0 , 0 , 32, 17405 0xfc003fff, 0x2000127f, &SHILOV , 0, 17406 DSP_ }, /* SHILOV */ 17407 { reserved_block , 0 , 0 , 32, 17408 0xfc003fff, 0x2000227f, 0 , 0, 17409 0x0 }, /* POOL32Axf_1_1~*(2) */ 17410 { reserved_block , 0 , 0 , 32, 17411 0xfc003fff, 0x2000327f, 0 , 0, 17412 0x0 }, /* POOL32Axf_1_1~*(3) */ 17413 }; 17414 17415 17416 static const Pool POOL32Axf_1_3[4] = { 17417 { instruction , 0 , 0 , 32, 17418 0xfc003fff, 0x2000067f, &RDDSP , 0, 17419 DSP_ }, /* RDDSP */ 17420 { instruction , 0 , 0 , 32, 17421 0xfc003fff, 0x2000167f, &WRDSP , 0, 17422 DSP_ }, /* WRDSP */ 17423 { instruction , 0 , 0 , 32, 17424 0xfc003fff, 0x2000267f, &EXTP , 0, 17425 DSP_ }, /* EXTP */ 17426 { instruction , 0 , 0 , 32, 17427 0xfc003fff, 0x2000367f, &EXTPDP , 0, 17428 DSP_ }, /* EXTPDP */ 17429 }; 17430 17431 17432 static const Pool POOL32Axf_1_4[2] = { 17433 { instruction , 0 , 0 , 32, 17434 0xfc001fff, 0x2000087f, &SHLL_QB , 0, 17435 DSP_ }, /* SHLL.QB */ 17436 { instruction , 0 , 0 , 32, 17437 0xfc001fff, 0x2000187f, &SHRL_QB , 0, 17438 DSP_ }, /* SHRL.QB */ 17439 }; 17440 17441 17442 static const Pool MAQ_S_A__W_PHR[2] = { 17443 { instruction , 0 , 0 , 32, 17444 0xfc003fff, 0x20000a7f, &MAQ_S_W_PHR , 0, 17445 DSP_ }, /* MAQ_S.W.PHR */ 17446 { instruction , 0 , 0 , 32, 17447 0xfc003fff, 0x20002a7f, &MAQ_SA_W_PHR , 0, 17448 DSP_ }, /* MAQ_SA.W.PHR */ 17449 }; 17450 17451 17452 static const Pool MAQ_S_A__W_PHL[2] = { 17453 { instruction , 0 , 0 , 32, 17454 0xfc003fff, 0x20001a7f, &MAQ_S_W_PHL , 0, 17455 DSP_ }, /* MAQ_S.W.PHL */ 17456 { instruction , 0 , 0 , 32, 17457 0xfc003fff, 0x20003a7f, &MAQ_SA_W_PHL , 0, 17458 DSP_ }, /* MAQ_SA.W.PHL */ 17459 }; 17460 17461 17462 static const Pool POOL32Axf_1_5[2] = { 17463 { pool , MAQ_S_A__W_PHR , 2 , 32, 17464 0xfc001fff, 0x20000a7f, 0 , 0, 17465 0x0 }, /* MAQ_S[A].W.PHR */ 17466 { pool , MAQ_S_A__W_PHL , 2 , 32, 17467 0xfc001fff, 0x20001a7f, 0 , 0, 17468 0x0 }, /* MAQ_S[A].W.PHL */ 17469 }; 17470 17471 17472 static const Pool POOL32Axf_1_7[4] = { 17473 { instruction , 0 , 0 , 32, 17474 0xfc003fff, 0x20000e7f, &EXTR_W , 0, 17475 DSP_ }, /* EXTR.W */ 17476 { instruction , 0 , 0 , 32, 17477 0xfc003fff, 0x20001e7f, &EXTR_R_W , 0, 17478 DSP_ }, /* EXTR_R.W */ 17479 { instruction , 0 , 0 , 32, 17480 0xfc003fff, 0x20002e7f, &EXTR_RS_W , 0, 17481 DSP_ }, /* EXTR_RS.W */ 17482 { instruction , 0 , 0 , 32, 17483 0xfc003fff, 0x20003e7f, &EXTR_S_H , 0, 17484 DSP_ }, /* EXTR_S.H */ 17485 }; 17486 17487 17488 static const Pool POOL32Axf_1[8] = { 17489 { pool , POOL32Axf_1_0 , 4 , 32, 17490 0xfc000fff, 0x2000007f, 0 , 0, 17491 0x0 }, /* POOL32Axf_1_0 */ 17492 { pool , POOL32Axf_1_1 , 4 , 32, 17493 0xfc000fff, 0x2000027f, 0 , 0, 17494 0x0 }, /* POOL32Axf_1_1 */ 17495 { reserved_block , 0 , 0 , 32, 17496 0xfc000fff, 0x2000047f, 0 , 0, 17497 0x0 }, /* POOL32Axf_1~*(2) */ 17498 { pool , POOL32Axf_1_3 , 4 , 32, 17499 0xfc000fff, 0x2000067f, 0 , 0, 17500 0x0 }, /* POOL32Axf_1_3 */ 17501 { pool , POOL32Axf_1_4 , 2 , 32, 17502 0xfc000fff, 0x2000087f, 0 , 0, 17503 0x0 }, /* POOL32Axf_1_4 */ 17504 { pool , POOL32Axf_1_5 , 2 , 32, 17505 0xfc000fff, 0x20000a7f, 0 , 0, 17506 0x0 }, /* POOL32Axf_1_5 */ 17507 { reserved_block , 0 , 0 , 32, 17508 0xfc000fff, 0x20000c7f, 0 , 0, 17509 0x0 }, /* POOL32Axf_1~*(6) */ 17510 { pool , POOL32Axf_1_7 , 4 , 32, 17511 0xfc000fff, 0x20000e7f, 0 , 0, 17512 0x0 }, /* POOL32Axf_1_7 */ 17513 }; 17514 17515 17516 static const Pool POOL32Axf_2_DSP__0_7[8] = { 17517 { instruction , 0 , 0 , 32, 17518 0xfc003fff, 0x200000bf, &DPA_W_PH , 0, 17519 DSP_ }, /* DPA.W.PH */ 17520 { instruction , 0 , 0 , 32, 17521 0xfc003fff, 0x200002bf, &DPAQ_S_W_PH , 0, 17522 DSP_ }, /* DPAQ_S.W.PH */ 17523 { instruction , 0 , 0 , 32, 17524 0xfc003fff, 0x200004bf, &DPS_W_PH , 0, 17525 DSP_ }, /* DPS.W.PH */ 17526 { instruction , 0 , 0 , 32, 17527 0xfc003fff, 0x200006bf, &DPSQ_S_W_PH , 0, 17528 DSP_ }, /* DPSQ_S.W.PH */ 17529 { reserved_block , 0 , 0 , 32, 17530 0xfc003fff, 0x200008bf, 0 , 0, 17531 0x0 }, /* POOL32Axf_2(DSP)_0_7~*(4) */ 17532 { instruction , 0 , 0 , 32, 17533 0xfc003fff, 0x20000abf, &MADD_DSP_ , 0, 17534 DSP_ }, /* MADD[DSP] */ 17535 { instruction , 0 , 0 , 32, 17536 0xfc003fff, 0x20000cbf, &MULT_DSP_ , 0, 17537 DSP_ }, /* MULT[DSP] */ 17538 { instruction , 0 , 0 , 32, 17539 0xfc003fff, 0x20000ebf, &EXTRV_W , 0, 17540 DSP_ }, /* EXTRV.W */ 17541 }; 17542 17543 17544 static const Pool POOL32Axf_2_DSP__8_15[8] = { 17545 { instruction , 0 , 0 , 32, 17546 0xfc003fff, 0x200010bf, &DPAX_W_PH , 0, 17547 DSP_ }, /* DPAX.W.PH */ 17548 { instruction , 0 , 0 , 32, 17549 0xfc003fff, 0x200012bf, &DPAQ_SA_L_W , 0, 17550 DSP_ }, /* DPAQ_SA.L.W */ 17551 { instruction , 0 , 0 , 32, 17552 0xfc003fff, 0x200014bf, &DPSX_W_PH , 0, 17553 DSP_ }, /* DPSX.W.PH */ 17554 { instruction , 0 , 0 , 32, 17555 0xfc003fff, 0x200016bf, &DPSQ_SA_L_W , 0, 17556 DSP_ }, /* DPSQ_SA.L.W */ 17557 { reserved_block , 0 , 0 , 32, 17558 0xfc003fff, 0x200018bf, 0 , 0, 17559 0x0 }, /* POOL32Axf_2(DSP)_8_15~*(4) */ 17560 { instruction , 0 , 0 , 32, 17561 0xfc003fff, 0x20001abf, &MADDU_DSP_ , 0, 17562 DSP_ }, /* MADDU[DSP] */ 17563 { instruction , 0 , 0 , 32, 17564 0xfc003fff, 0x20001cbf, &MULTU_DSP_ , 0, 17565 DSP_ }, /* MULTU[DSP] */ 17566 { instruction , 0 , 0 , 32, 17567 0xfc003fff, 0x20001ebf, &EXTRV_R_W , 0, 17568 DSP_ }, /* EXTRV_R.W */ 17569 }; 17570 17571 17572 static const Pool POOL32Axf_2_DSP__16_23[8] = { 17573 { instruction , 0 , 0 , 32, 17574 0xfc003fff, 0x200020bf, &DPAU_H_QBL , 0, 17575 DSP_ }, /* DPAU.H.QBL */ 17576 { instruction , 0 , 0 , 32, 17577 0xfc003fff, 0x200022bf, &DPAQX_S_W_PH , 0, 17578 DSP_ }, /* DPAQX_S.W.PH */ 17579 { instruction , 0 , 0 , 32, 17580 0xfc003fff, 0x200024bf, &DPSU_H_QBL , 0, 17581 DSP_ }, /* DPSU.H.QBL */ 17582 { instruction , 0 , 0 , 32, 17583 0xfc003fff, 0x200026bf, &DPSQX_S_W_PH , 0, 17584 DSP_ }, /* DPSQX_S.W.PH */ 17585 { instruction , 0 , 0 , 32, 17586 0xfc003fff, 0x200028bf, &EXTPV , 0, 17587 DSP_ }, /* EXTPV */ 17588 { instruction , 0 , 0 , 32, 17589 0xfc003fff, 0x20002abf, &MSUB_DSP_ , 0, 17590 DSP_ }, /* MSUB[DSP] */ 17591 { instruction , 0 , 0 , 32, 17592 0xfc003fff, 0x20002cbf, &MULSA_W_PH , 0, 17593 DSP_ }, /* MULSA.W.PH */ 17594 { instruction , 0 , 0 , 32, 17595 0xfc003fff, 0x20002ebf, &EXTRV_RS_W , 0, 17596 DSP_ }, /* EXTRV_RS.W */ 17597 }; 17598 17599 17600 static const Pool POOL32Axf_2_DSP__24_31[8] = { 17601 { instruction , 0 , 0 , 32, 17602 0xfc003fff, 0x200030bf, &DPAU_H_QBR , 0, 17603 DSP_ }, /* DPAU.H.QBR */ 17604 { instruction , 0 , 0 , 32, 17605 0xfc003fff, 0x200032bf, &DPAQX_SA_W_PH , 0, 17606 DSP_ }, /* DPAQX_SA.W.PH */ 17607 { instruction , 0 , 0 , 32, 17608 0xfc003fff, 0x200034bf, &DPSU_H_QBR , 0, 17609 DSP_ }, /* DPSU.H.QBR */ 17610 { instruction , 0 , 0 , 32, 17611 0xfc003fff, 0x200036bf, &DPSQX_SA_W_PH , 0, 17612 DSP_ }, /* DPSQX_SA.W.PH */ 17613 { instruction , 0 , 0 , 32, 17614 0xfc003fff, 0x200038bf, &EXTPDPV , 0, 17615 DSP_ }, /* EXTPDPV */ 17616 { instruction , 0 , 0 , 32, 17617 0xfc003fff, 0x20003abf, &MSUBU_DSP_ , 0, 17618 DSP_ }, /* MSUBU[DSP] */ 17619 { instruction , 0 , 0 , 32, 17620 0xfc003fff, 0x20003cbf, &MULSAQ_S_W_PH , 0, 17621 DSP_ }, /* MULSAQ_S.W.PH */ 17622 { instruction , 0 , 0 , 32, 17623 0xfc003fff, 0x20003ebf, &EXTRV_S_H , 0, 17624 DSP_ }, /* EXTRV_S.H */ 17625 }; 17626 17627 17628 static const Pool POOL32Axf_2[4] = { 17629 { pool , POOL32Axf_2_DSP__0_7, 8 , 32, 17630 0xfc0031ff, 0x200000bf, 0 , 0, 17631 0x0 }, /* POOL32Axf_2(DSP)_0_7 */ 17632 { pool , POOL32Axf_2_DSP__8_15, 8 , 32, 17633 0xfc0031ff, 0x200010bf, 0 , 0, 17634 0x0 }, /* POOL32Axf_2(DSP)_8_15 */ 17635 { pool , POOL32Axf_2_DSP__16_23, 8 , 32, 17636 0xfc0031ff, 0x200020bf, 0 , 0, 17637 0x0 }, /* POOL32Axf_2(DSP)_16_23 */ 17638 { pool , POOL32Axf_2_DSP__24_31, 8 , 32, 17639 0xfc0031ff, 0x200030bf, 0 , 0, 17640 0x0 }, /* POOL32Axf_2(DSP)_24_31 */ 17641 }; 17642 17643 17644 static const Pool POOL32Axf_4[128] = { 17645 { instruction , 0 , 0 , 32, 17646 0xfc00ffff, 0x2000013f, &ABSQ_S_QB , 0, 17647 DSP_ }, /* ABSQ_S.QB */ 17648 { instruction , 0 , 0 , 32, 17649 0xfc00ffff, 0x2000033f, &REPLV_PH , 0, 17650 DSP_ }, /* REPLV.PH */ 17651 { reserved_block , 0 , 0 , 32, 17652 0xfc00ffff, 0x2000053f, 0 , 0, 17653 0x0 }, /* POOL32Axf_4~*(2) */ 17654 { reserved_block , 0 , 0 , 32, 17655 0xfc00ffff, 0x2000073f, 0 , 0, 17656 0x0 }, /* POOL32Axf_4~*(3) */ 17657 { reserved_block , 0 , 0 , 32, 17658 0xfc00ffff, 0x2000093f, 0 , 0, 17659 0x0 }, /* POOL32Axf_4~*(4) */ 17660 { reserved_block , 0 , 0 , 32, 17661 0xfc00ffff, 0x20000b3f, 0 , 0, 17662 0x0 }, /* POOL32Axf_4~*(5) */ 17663 { reserved_block , 0 , 0 , 32, 17664 0xfc00ffff, 0x20000d3f, 0 , 0, 17665 0x0 }, /* POOL32Axf_4~*(6) */ 17666 { reserved_block , 0 , 0 , 32, 17667 0xfc00ffff, 0x20000f3f, 0 , 0, 17668 0x0 }, /* POOL32Axf_4~*(7) */ 17669 { instruction , 0 , 0 , 32, 17670 0xfc00ffff, 0x2000113f, &ABSQ_S_PH , 0, 17671 DSP_ }, /* ABSQ_S.PH */ 17672 { instruction , 0 , 0 , 32, 17673 0xfc00ffff, 0x2000133f, &REPLV_QB , 0, 17674 DSP_ }, /* REPLV.QB */ 17675 { reserved_block , 0 , 0 , 32, 17676 0xfc00ffff, 0x2000153f, 0 , 0, 17677 0x0 }, /* POOL32Axf_4~*(10) */ 17678 { reserved_block , 0 , 0 , 32, 17679 0xfc00ffff, 0x2000173f, 0 , 0, 17680 0x0 }, /* POOL32Axf_4~*(11) */ 17681 { reserved_block , 0 , 0 , 32, 17682 0xfc00ffff, 0x2000193f, 0 , 0, 17683 0x0 }, /* POOL32Axf_4~*(12) */ 17684 { reserved_block , 0 , 0 , 32, 17685 0xfc00ffff, 0x20001b3f, 0 , 0, 17686 0x0 }, /* POOL32Axf_4~*(13) */ 17687 { reserved_block , 0 , 0 , 32, 17688 0xfc00ffff, 0x20001d3f, 0 , 0, 17689 0x0 }, /* POOL32Axf_4~*(14) */ 17690 { reserved_block , 0 , 0 , 32, 17691 0xfc00ffff, 0x20001f3f, 0 , 0, 17692 0x0 }, /* POOL32Axf_4~*(15) */ 17693 { instruction , 0 , 0 , 32, 17694 0xfc00ffff, 0x2000213f, &ABSQ_S_W , 0, 17695 DSP_ }, /* ABSQ_S.W */ 17696 { reserved_block , 0 , 0 , 32, 17697 0xfc00ffff, 0x2000233f, 0 , 0, 17698 0x0 }, /* POOL32Axf_4~*(17) */ 17699 { reserved_block , 0 , 0 , 32, 17700 0xfc00ffff, 0x2000253f, 0 , 0, 17701 0x0 }, /* POOL32Axf_4~*(18) */ 17702 { reserved_block , 0 , 0 , 32, 17703 0xfc00ffff, 0x2000273f, 0 , 0, 17704 0x0 }, /* POOL32Axf_4~*(19) */ 17705 { reserved_block , 0 , 0 , 32, 17706 0xfc00ffff, 0x2000293f, 0 , 0, 17707 0x0 }, /* POOL32Axf_4~*(20) */ 17708 { reserved_block , 0 , 0 , 32, 17709 0xfc00ffff, 0x20002b3f, 0 , 0, 17710 0x0 }, /* POOL32Axf_4~*(21) */ 17711 { reserved_block , 0 , 0 , 32, 17712 0xfc00ffff, 0x20002d3f, 0 , 0, 17713 0x0 }, /* POOL32Axf_4~*(22) */ 17714 { reserved_block , 0 , 0 , 32, 17715 0xfc00ffff, 0x20002f3f, 0 , 0, 17716 0x0 }, /* POOL32Axf_4~*(23) */ 17717 { reserved_block , 0 , 0 , 32, 17718 0xfc00ffff, 0x2000313f, 0 , 0, 17719 0x0 }, /* POOL32Axf_4~*(24) */ 17720 { reserved_block , 0 , 0 , 32, 17721 0xfc00ffff, 0x2000333f, 0 , 0, 17722 0x0 }, /* POOL32Axf_4~*(25) */ 17723 { reserved_block , 0 , 0 , 32, 17724 0xfc00ffff, 0x2000353f, 0 , 0, 17725 0x0 }, /* POOL32Axf_4~*(26) */ 17726 { reserved_block , 0 , 0 , 32, 17727 0xfc00ffff, 0x2000373f, 0 , 0, 17728 0x0 }, /* POOL32Axf_4~*(27) */ 17729 { reserved_block , 0 , 0 , 32, 17730 0xfc00ffff, 0x2000393f, 0 , 0, 17731 0x0 }, /* POOL32Axf_4~*(28) */ 17732 { reserved_block , 0 , 0 , 32, 17733 0xfc00ffff, 0x20003b3f, 0 , 0, 17734 0x0 }, /* POOL32Axf_4~*(29) */ 17735 { reserved_block , 0 , 0 , 32, 17736 0xfc00ffff, 0x20003d3f, 0 , 0, 17737 0x0 }, /* POOL32Axf_4~*(30) */ 17738 { reserved_block , 0 , 0 , 32, 17739 0xfc00ffff, 0x20003f3f, 0 , 0, 17740 0x0 }, /* POOL32Axf_4~*(31) */ 17741 { instruction , 0 , 0 , 32, 17742 0xfc00ffff, 0x2000413f, &INSV , 0, 17743 DSP_ }, /* INSV */ 17744 { reserved_block , 0 , 0 , 32, 17745 0xfc00ffff, 0x2000433f, 0 , 0, 17746 0x0 }, /* POOL32Axf_4~*(33) */ 17747 { reserved_block , 0 , 0 , 32, 17748 0xfc00ffff, 0x2000453f, 0 , 0, 17749 0x0 }, /* POOL32Axf_4~*(34) */ 17750 { reserved_block , 0 , 0 , 32, 17751 0xfc00ffff, 0x2000473f, 0 , 0, 17752 0x0 }, /* POOL32Axf_4~*(35) */ 17753 { reserved_block , 0 , 0 , 32, 17754 0xfc00ffff, 0x2000493f, 0 , 0, 17755 0x0 }, /* POOL32Axf_4~*(36) */ 17756 { instruction , 0 , 0 , 32, 17757 0xfc00ffff, 0x20004b3f, &CLO , 0, 17758 XMMS_ }, /* CLO */ 17759 { instruction , 0 , 0 , 32, 17760 0xfc00ffff, 0x20004d3f, &MFC2 , 0, 17761 CP2_ }, /* MFC2 */ 17762 { reserved_block , 0 , 0 , 32, 17763 0xfc00ffff, 0x20004f3f, 0 , 0, 17764 0x0 }, /* POOL32Axf_4~*(39) */ 17765 { instruction , 0 , 0 , 32, 17766 0xfc00ffff, 0x2000513f, &PRECEQ_W_PHL , 0, 17767 DSP_ }, /* PRECEQ.W.PHL */ 17768 { reserved_block , 0 , 0 , 32, 17769 0xfc00ffff, 0x2000533f, 0 , 0, 17770 0x0 }, /* POOL32Axf_4~*(41) */ 17771 { reserved_block , 0 , 0 , 32, 17772 0xfc00ffff, 0x2000553f, 0 , 0, 17773 0x0 }, /* POOL32Axf_4~*(42) */ 17774 { reserved_block , 0 , 0 , 32, 17775 0xfc00ffff, 0x2000573f, 0 , 0, 17776 0x0 }, /* POOL32Axf_4~*(43) */ 17777 { reserved_block , 0 , 0 , 32, 17778 0xfc00ffff, 0x2000593f, 0 , 0, 17779 0x0 }, /* POOL32Axf_4~*(44) */ 17780 { instruction , 0 , 0 , 32, 17781 0xfc00ffff, 0x20005b3f, &CLZ , 0, 17782 XMMS_ }, /* CLZ */ 17783 { instruction , 0 , 0 , 32, 17784 0xfc00ffff, 0x20005d3f, &MTC2 , 0, 17785 CP2_ }, /* MTC2 */ 17786 { reserved_block , 0 , 0 , 32, 17787 0xfc00ffff, 0x20005f3f, 0 , 0, 17788 0x0 }, /* POOL32Axf_4~*(47) */ 17789 { instruction , 0 , 0 , 32, 17790 0xfc00ffff, 0x2000613f, &PRECEQ_W_PHR , 0, 17791 DSP_ }, /* PRECEQ.W.PHR */ 17792 { reserved_block , 0 , 0 , 32, 17793 0xfc00ffff, 0x2000633f, 0 , 0, 17794 0x0 }, /* POOL32Axf_4~*(49) */ 17795 { reserved_block , 0 , 0 , 32, 17796 0xfc00ffff, 0x2000653f, 0 , 0, 17797 0x0 }, /* POOL32Axf_4~*(50) */ 17798 { reserved_block , 0 , 0 , 32, 17799 0xfc00ffff, 0x2000673f, 0 , 0, 17800 0x0 }, /* POOL32Axf_4~*(51) */ 17801 { reserved_block , 0 , 0 , 32, 17802 0xfc00ffff, 0x2000693f, 0 , 0, 17803 0x0 }, /* POOL32Axf_4~*(52) */ 17804 { reserved_block , 0 , 0 , 32, 17805 0xfc00ffff, 0x20006b3f, 0 , 0, 17806 0x0 }, /* POOL32Axf_4~*(53) */ 17807 { instruction , 0 , 0 , 32, 17808 0xfc00ffff, 0x20006d3f, &DMFC2 , 0, 17809 CP2_ }, /* DMFC2 */ 17810 { reserved_block , 0 , 0 , 32, 17811 0xfc00ffff, 0x20006f3f, 0 , 0, 17812 0x0 }, /* POOL32Axf_4~*(55) */ 17813 { instruction , 0 , 0 , 32, 17814 0xfc00ffff, 0x2000713f, &PRECEQU_PH_QBL , 0, 17815 DSP_ }, /* PRECEQU.PH.QBL */ 17816 { instruction , 0 , 0 , 32, 17817 0xfc00ffff, 0x2000733f, &PRECEQU_PH_QBLA , 0, 17818 DSP_ }, /* PRECEQU.PH.QBLA */ 17819 { reserved_block , 0 , 0 , 32, 17820 0xfc00ffff, 0x2000753f, 0 , 0, 17821 0x0 }, /* POOL32Axf_4~*(58) */ 17822 { reserved_block , 0 , 0 , 32, 17823 0xfc00ffff, 0x2000773f, 0 , 0, 17824 0x0 }, /* POOL32Axf_4~*(59) */ 17825 { reserved_block , 0 , 0 , 32, 17826 0xfc00ffff, 0x2000793f, 0 , 0, 17827 0x0 }, /* POOL32Axf_4~*(60) */ 17828 { reserved_block , 0 , 0 , 32, 17829 0xfc00ffff, 0x20007b3f, 0 , 0, 17830 0x0 }, /* POOL32Axf_4~*(61) */ 17831 { instruction , 0 , 0 , 32, 17832 0xfc00ffff, 0x20007d3f, &DMTC2 , 0, 17833 CP2_ }, /* DMTC2 */ 17834 { reserved_block , 0 , 0 , 32, 17835 0xfc00ffff, 0x20007f3f, 0 , 0, 17836 0x0 }, /* POOL32Axf_4~*(63) */ 17837 { reserved_block , 0 , 0 , 32, 17838 0xfc00ffff, 0x2000813f, 0 , 0, 17839 0x0 }, /* POOL32Axf_4~*(64) */ 17840 { reserved_block , 0 , 0 , 32, 17841 0xfc00ffff, 0x2000833f, 0 , 0, 17842 0x0 }, /* POOL32Axf_4~*(65) */ 17843 { reserved_block , 0 , 0 , 32, 17844 0xfc00ffff, 0x2000853f, 0 , 0, 17845 0x0 }, /* POOL32Axf_4~*(66) */ 17846 { reserved_block , 0 , 0 , 32, 17847 0xfc00ffff, 0x2000873f, 0 , 0, 17848 0x0 }, /* POOL32Axf_4~*(67) */ 17849 { reserved_block , 0 , 0 , 32, 17850 0xfc00ffff, 0x2000893f, 0 , 0, 17851 0x0 }, /* POOL32Axf_4~*(68) */ 17852 { reserved_block , 0 , 0 , 32, 17853 0xfc00ffff, 0x20008b3f, 0 , 0, 17854 0x0 }, /* POOL32Axf_4~*(69) */ 17855 { instruction , 0 , 0 , 32, 17856 0xfc00ffff, 0x20008d3f, &MFHC2 , 0, 17857 CP2_ }, /* MFHC2 */ 17858 { reserved_block , 0 , 0 , 32, 17859 0xfc00ffff, 0x20008f3f, 0 , 0, 17860 0x0 }, /* POOL32Axf_4~*(71) */ 17861 { instruction , 0 , 0 , 32, 17862 0xfc00ffff, 0x2000913f, &PRECEQU_PH_QBR , 0, 17863 DSP_ }, /* PRECEQU.PH.QBR */ 17864 { instruction , 0 , 0 , 32, 17865 0xfc00ffff, 0x2000933f, &PRECEQU_PH_QBRA , 0, 17866 DSP_ }, /* PRECEQU.PH.QBRA */ 17867 { reserved_block , 0 , 0 , 32, 17868 0xfc00ffff, 0x2000953f, 0 , 0, 17869 0x0 }, /* POOL32Axf_4~*(74) */ 17870 { reserved_block , 0 , 0 , 32, 17871 0xfc00ffff, 0x2000973f, 0 , 0, 17872 0x0 }, /* POOL32Axf_4~*(75) */ 17873 { reserved_block , 0 , 0 , 32, 17874 0xfc00ffff, 0x2000993f, 0 , 0, 17875 0x0 }, /* POOL32Axf_4~*(76) */ 17876 { reserved_block , 0 , 0 , 32, 17877 0xfc00ffff, 0x20009b3f, 0 , 0, 17878 0x0 }, /* POOL32Axf_4~*(77) */ 17879 { instruction , 0 , 0 , 32, 17880 0xfc00ffff, 0x20009d3f, &MTHC2 , 0, 17881 CP2_ }, /* MTHC2 */ 17882 { reserved_block , 0 , 0 , 32, 17883 0xfc00ffff, 0x20009f3f, 0 , 0, 17884 0x0 }, /* POOL32Axf_4~*(79) */ 17885 { reserved_block , 0 , 0 , 32, 17886 0xfc00ffff, 0x2000a13f, 0 , 0, 17887 0x0 }, /* POOL32Axf_4~*(80) */ 17888 { reserved_block , 0 , 0 , 32, 17889 0xfc00ffff, 0x2000a33f, 0 , 0, 17890 0x0 }, /* POOL32Axf_4~*(81) */ 17891 { reserved_block , 0 , 0 , 32, 17892 0xfc00ffff, 0x2000a53f, 0 , 0, 17893 0x0 }, /* POOL32Axf_4~*(82) */ 17894 { reserved_block , 0 , 0 , 32, 17895 0xfc00ffff, 0x2000a73f, 0 , 0, 17896 0x0 }, /* POOL32Axf_4~*(83) */ 17897 { reserved_block , 0 , 0 , 32, 17898 0xfc00ffff, 0x2000a93f, 0 , 0, 17899 0x0 }, /* POOL32Axf_4~*(84) */ 17900 { reserved_block , 0 , 0 , 32, 17901 0xfc00ffff, 0x2000ab3f, 0 , 0, 17902 0x0 }, /* POOL32Axf_4~*(85) */ 17903 { reserved_block , 0 , 0 , 32, 17904 0xfc00ffff, 0x2000ad3f, 0 , 0, 17905 0x0 }, /* POOL32Axf_4~*(86) */ 17906 { reserved_block , 0 , 0 , 32, 17907 0xfc00ffff, 0x2000af3f, 0 , 0, 17908 0x0 }, /* POOL32Axf_4~*(87) */ 17909 { instruction , 0 , 0 , 32, 17910 0xfc00ffff, 0x2000b13f, &PRECEU_PH_QBL , 0, 17911 DSP_ }, /* PRECEU.PH.QBL */ 17912 { instruction , 0 , 0 , 32, 17913 0xfc00ffff, 0x2000b33f, &PRECEU_PH_QBLA , 0, 17914 DSP_ }, /* PRECEU.PH.QBLA */ 17915 { reserved_block , 0 , 0 , 32, 17916 0xfc00ffff, 0x2000b53f, 0 , 0, 17917 0x0 }, /* POOL32Axf_4~*(90) */ 17918 { reserved_block , 0 , 0 , 32, 17919 0xfc00ffff, 0x2000b73f, 0 , 0, 17920 0x0 }, /* POOL32Axf_4~*(91) */ 17921 { reserved_block , 0 , 0 , 32, 17922 0xfc00ffff, 0x2000b93f, 0 , 0, 17923 0x0 }, /* POOL32Axf_4~*(92) */ 17924 { reserved_block , 0 , 0 , 32, 17925 0xfc00ffff, 0x2000bb3f, 0 , 0, 17926 0x0 }, /* POOL32Axf_4~*(93) */ 17927 { reserved_block , 0 , 0 , 32, 17928 0xfc00ffff, 0x2000bd3f, 0 , 0, 17929 0x0 }, /* POOL32Axf_4~*(94) */ 17930 { reserved_block , 0 , 0 , 32, 17931 0xfc00ffff, 0x2000bf3f, 0 , 0, 17932 0x0 }, /* POOL32Axf_4~*(95) */ 17933 { reserved_block , 0 , 0 , 32, 17934 0xfc00ffff, 0x2000c13f, 0 , 0, 17935 0x0 }, /* POOL32Axf_4~*(96) */ 17936 { reserved_block , 0 , 0 , 32, 17937 0xfc00ffff, 0x2000c33f, 0 , 0, 17938 0x0 }, /* POOL32Axf_4~*(97) */ 17939 { reserved_block , 0 , 0 , 32, 17940 0xfc00ffff, 0x2000c53f, 0 , 0, 17941 0x0 }, /* POOL32Axf_4~*(98) */ 17942 { reserved_block , 0 , 0 , 32, 17943 0xfc00ffff, 0x2000c73f, 0 , 0, 17944 0x0 }, /* POOL32Axf_4~*(99) */ 17945 { reserved_block , 0 , 0 , 32, 17946 0xfc00ffff, 0x2000c93f, 0 , 0, 17947 0x0 }, /* POOL32Axf_4~*(100) */ 17948 { reserved_block , 0 , 0 , 32, 17949 0xfc00ffff, 0x2000cb3f, 0 , 0, 17950 0x0 }, /* POOL32Axf_4~*(101) */ 17951 { instruction , 0 , 0 , 32, 17952 0xfc00ffff, 0x2000cd3f, &CFC2 , 0, 17953 CP2_ }, /* CFC2 */ 17954 { reserved_block , 0 , 0 , 32, 17955 0xfc00ffff, 0x2000cf3f, 0 , 0, 17956 0x0 }, /* POOL32Axf_4~*(103) */ 17957 { instruction , 0 , 0 , 32, 17958 0xfc00ffff, 0x2000d13f, &PRECEU_PH_QBR , 0, 17959 DSP_ }, /* PRECEU.PH.QBR */ 17960 { instruction , 0 , 0 , 32, 17961 0xfc00ffff, 0x2000d33f, &PRECEU_PH_QBRA , 0, 17962 DSP_ }, /* PRECEU.PH.QBRA */ 17963 { reserved_block , 0 , 0 , 32, 17964 0xfc00ffff, 0x2000d53f, 0 , 0, 17965 0x0 }, /* POOL32Axf_4~*(106) */ 17966 { reserved_block , 0 , 0 , 32, 17967 0xfc00ffff, 0x2000d73f, 0 , 0, 17968 0x0 }, /* POOL32Axf_4~*(107) */ 17969 { reserved_block , 0 , 0 , 32, 17970 0xfc00ffff, 0x2000d93f, 0 , 0, 17971 0x0 }, /* POOL32Axf_4~*(108) */ 17972 { reserved_block , 0 , 0 , 32, 17973 0xfc00ffff, 0x2000db3f, 0 , 0, 17974 0x0 }, /* POOL32Axf_4~*(109) */ 17975 { instruction , 0 , 0 , 32, 17976 0xfc00ffff, 0x2000dd3f, &CTC2 , 0, 17977 CP2_ }, /* CTC2 */ 17978 { reserved_block , 0 , 0 , 32, 17979 0xfc00ffff, 0x2000df3f, 0 , 0, 17980 0x0 }, /* POOL32Axf_4~*(111) */ 17981 { reserved_block , 0 , 0 , 32, 17982 0xfc00ffff, 0x2000e13f, 0 , 0, 17983 0x0 }, /* POOL32Axf_4~*(112) */ 17984 { reserved_block , 0 , 0 , 32, 17985 0xfc00ffff, 0x2000e33f, 0 , 0, 17986 0x0 }, /* POOL32Axf_4~*(113) */ 17987 { reserved_block , 0 , 0 , 32, 17988 0xfc00ffff, 0x2000e53f, 0 , 0, 17989 0x0 }, /* POOL32Axf_4~*(114) */ 17990 { reserved_block , 0 , 0 , 32, 17991 0xfc00ffff, 0x2000e73f, 0 , 0, 17992 0x0 }, /* POOL32Axf_4~*(115) */ 17993 { reserved_block , 0 , 0 , 32, 17994 0xfc00ffff, 0x2000e93f, 0 , 0, 17995 0x0 }, /* POOL32Axf_4~*(116) */ 17996 { reserved_block , 0 , 0 , 32, 17997 0xfc00ffff, 0x2000eb3f, 0 , 0, 17998 0x0 }, /* POOL32Axf_4~*(117) */ 17999 { reserved_block , 0 , 0 , 32, 18000 0xfc00ffff, 0x2000ed3f, 0 , 0, 18001 0x0 }, /* POOL32Axf_4~*(118) */ 18002 { reserved_block , 0 , 0 , 32, 18003 0xfc00ffff, 0x2000ef3f, 0 , 0, 18004 0x0 }, /* POOL32Axf_4~*(119) */ 18005 { instruction , 0 , 0 , 32, 18006 0xfc00ffff, 0x2000f13f, &RADDU_W_QB , 0, 18007 DSP_ }, /* RADDU.W.QB */ 18008 { reserved_block , 0 , 0 , 32, 18009 0xfc00ffff, 0x2000f33f, 0 , 0, 18010 0x0 }, /* POOL32Axf_4~*(121) */ 18011 { reserved_block , 0 , 0 , 32, 18012 0xfc00ffff, 0x2000f53f, 0 , 0, 18013 0x0 }, /* POOL32Axf_4~*(122) */ 18014 { reserved_block , 0 , 0 , 32, 18015 0xfc00ffff, 0x2000f73f, 0 , 0, 18016 0x0 }, /* POOL32Axf_4~*(123) */ 18017 { reserved_block , 0 , 0 , 32, 18018 0xfc00ffff, 0x2000f93f, 0 , 0, 18019 0x0 }, /* POOL32Axf_4~*(124) */ 18020 { reserved_block , 0 , 0 , 32, 18021 0xfc00ffff, 0x2000fb3f, 0 , 0, 18022 0x0 }, /* POOL32Axf_4~*(125) */ 18023 { reserved_block , 0 , 0 , 32, 18024 0xfc00ffff, 0x2000fd3f, 0 , 0, 18025 0x0 }, /* POOL32Axf_4~*(126) */ 18026 { reserved_block , 0 , 0 , 32, 18027 0xfc00ffff, 0x2000ff3f, 0 , 0, 18028 0x0 }, /* POOL32Axf_4~*(127) */ 18029 }; 18030 18031 18032 static const Pool POOL32Axf_5_group0[32] = { 18033 { instruction , 0 , 0 , 32, 18034 0xfc00ffff, 0x2000017f, &TLBGP , 0, 18035 CP0_ | VZ_ | TLB_ }, /* TLBGP */ 18036 { instruction , 0 , 0 , 32, 18037 0xfc00ffff, 0x2000037f, &TLBP , 0, 18038 CP0_ | TLB_ }, /* TLBP */ 18039 { instruction , 0 , 0 , 32, 18040 0xfc00ffff, 0x2000057f, &TLBGINV , 0, 18041 CP0_ | VZ_ | TLB_ | TLBINV_}, /* TLBGINV */ 18042 { instruction , 0 , 0 , 32, 18043 0xfc00ffff, 0x2000077f, &TLBINV , 0, 18044 CP0_ | TLB_ | TLBINV_}, /* TLBINV */ 18045 { reserved_block , 0 , 0 , 32, 18046 0xfc00ffff, 0x2000097f, 0 , 0, 18047 0x0 }, /* POOL32Axf_5_group0~*(4) */ 18048 { reserved_block , 0 , 0 , 32, 18049 0xfc00ffff, 0x20000b7f, 0 , 0, 18050 0x0 }, /* POOL32Axf_5_group0~*(5) */ 18051 { reserved_block , 0 , 0 , 32, 18052 0xfc00ffff, 0x20000d7f, 0 , 0, 18053 0x0 }, /* POOL32Axf_5_group0~*(6) */ 18054 { reserved_block , 0 , 0 , 32, 18055 0xfc00ffff, 0x20000f7f, 0 , 0, 18056 0x0 }, /* POOL32Axf_5_group0~*(7) */ 18057 { instruction , 0 , 0 , 32, 18058 0xfc00ffff, 0x2000117f, &TLBGR , 0, 18059 CP0_ | VZ_ | TLB_ }, /* TLBGR */ 18060 { instruction , 0 , 0 , 32, 18061 0xfc00ffff, 0x2000137f, &TLBR , 0, 18062 CP0_ | TLB_ }, /* TLBR */ 18063 { instruction , 0 , 0 , 32, 18064 0xfc00ffff, 0x2000157f, &TLBGINVF , 0, 18065 CP0_ | VZ_ | TLB_ | TLBINV_}, /* TLBGINVF */ 18066 { instruction , 0 , 0 , 32, 18067 0xfc00ffff, 0x2000177f, &TLBINVF , 0, 18068 CP0_ | TLB_ | TLBINV_}, /* TLBINVF */ 18069 { reserved_block , 0 , 0 , 32, 18070 0xfc00ffff, 0x2000197f, 0 , 0, 18071 0x0 }, /* POOL32Axf_5_group0~*(12) */ 18072 { reserved_block , 0 , 0 , 32, 18073 0xfc00ffff, 0x20001b7f, 0 , 0, 18074 0x0 }, /* POOL32Axf_5_group0~*(13) */ 18075 { reserved_block , 0 , 0 , 32, 18076 0xfc00ffff, 0x20001d7f, 0 , 0, 18077 0x0 }, /* POOL32Axf_5_group0~*(14) */ 18078 { reserved_block , 0 , 0 , 32, 18079 0xfc00ffff, 0x20001f7f, 0 , 0, 18080 0x0 }, /* POOL32Axf_5_group0~*(15) */ 18081 { instruction , 0 , 0 , 32, 18082 0xfc00ffff, 0x2000217f, &TLBGWI , 0, 18083 CP0_ | VZ_ | TLB_ }, /* TLBGWI */ 18084 { instruction , 0 , 0 , 32, 18085 0xfc00ffff, 0x2000237f, &TLBWI , 0, 18086 CP0_ | TLB_ }, /* TLBWI */ 18087 { reserved_block , 0 , 0 , 32, 18088 0xfc00ffff, 0x2000257f, 0 , 0, 18089 0x0 }, /* POOL32Axf_5_group0~*(18) */ 18090 { reserved_block , 0 , 0 , 32, 18091 0xfc00ffff, 0x2000277f, 0 , 0, 18092 0x0 }, /* POOL32Axf_5_group0~*(19) */ 18093 { reserved_block , 0 , 0 , 32, 18094 0xfc00ffff, 0x2000297f, 0 , 0, 18095 0x0 }, /* POOL32Axf_5_group0~*(20) */ 18096 { reserved_block , 0 , 0 , 32, 18097 0xfc00ffff, 0x20002b7f, 0 , 0, 18098 0x0 }, /* POOL32Axf_5_group0~*(21) */ 18099 { reserved_block , 0 , 0 , 32, 18100 0xfc00ffff, 0x20002d7f, 0 , 0, 18101 0x0 }, /* POOL32Axf_5_group0~*(22) */ 18102 { reserved_block , 0 , 0 , 32, 18103 0xfc00ffff, 0x20002f7f, 0 , 0, 18104 0x0 }, /* POOL32Axf_5_group0~*(23) */ 18105 { instruction , 0 , 0 , 32, 18106 0xfc00ffff, 0x2000317f, &TLBGWR , 0, 18107 CP0_ | VZ_ | TLB_ }, /* TLBGWR */ 18108 { instruction , 0 , 0 , 32, 18109 0xfc00ffff, 0x2000337f, &TLBWR , 0, 18110 CP0_ | TLB_ }, /* TLBWR */ 18111 { reserved_block , 0 , 0 , 32, 18112 0xfc00ffff, 0x2000357f, 0 , 0, 18113 0x0 }, /* POOL32Axf_5_group0~*(26) */ 18114 { reserved_block , 0 , 0 , 32, 18115 0xfc00ffff, 0x2000377f, 0 , 0, 18116 0x0 }, /* POOL32Axf_5_group0~*(27) */ 18117 { reserved_block , 0 , 0 , 32, 18118 0xfc00ffff, 0x2000397f, 0 , 0, 18119 0x0 }, /* POOL32Axf_5_group0~*(28) */ 18120 { reserved_block , 0 , 0 , 32, 18121 0xfc00ffff, 0x20003b7f, 0 , 0, 18122 0x0 }, /* POOL32Axf_5_group0~*(29) */ 18123 { reserved_block , 0 , 0 , 32, 18124 0xfc00ffff, 0x20003d7f, 0 , 0, 18125 0x0 }, /* POOL32Axf_5_group0~*(30) */ 18126 { reserved_block , 0 , 0 , 32, 18127 0xfc00ffff, 0x20003f7f, 0 , 0, 18128 0x0 }, /* POOL32Axf_5_group0~*(31) */ 18129 }; 18130 18131 18132 static const Pool POOL32Axf_5_group1[32] = { 18133 { reserved_block , 0 , 0 , 32, 18134 0xfc00ffff, 0x2000417f, 0 , 0, 18135 0x0 }, /* POOL32Axf_5_group1~*(0) */ 18136 { reserved_block , 0 , 0 , 32, 18137 0xfc00ffff, 0x2000437f, 0 , 0, 18138 0x0 }, /* POOL32Axf_5_group1~*(1) */ 18139 { reserved_block , 0 , 0 , 32, 18140 0xfc00ffff, 0x2000457f, 0 , 0, 18141 0x0 }, /* POOL32Axf_5_group1~*(2) */ 18142 { instruction , 0 , 0 , 32, 18143 0xfc00ffff, 0x2000477f, &DI , 0, 18144 0x0 }, /* DI */ 18145 { reserved_block , 0 , 0 , 32, 18146 0xfc00ffff, 0x2000497f, 0 , 0, 18147 0x0 }, /* POOL32Axf_5_group1~*(4) */ 18148 { reserved_block , 0 , 0 , 32, 18149 0xfc00ffff, 0x20004b7f, 0 , 0, 18150 0x0 }, /* POOL32Axf_5_group1~*(5) */ 18151 { reserved_block , 0 , 0 , 32, 18152 0xfc00ffff, 0x20004d7f, 0 , 0, 18153 0x0 }, /* POOL32Axf_5_group1~*(6) */ 18154 { reserved_block , 0 , 0 , 32, 18155 0xfc00ffff, 0x20004f7f, 0 , 0, 18156 0x0 }, /* POOL32Axf_5_group1~*(7) */ 18157 { reserved_block , 0 , 0 , 32, 18158 0xfc00ffff, 0x2000517f, 0 , 0, 18159 0x0 }, /* POOL32Axf_5_group1~*(8) */ 18160 { reserved_block , 0 , 0 , 32, 18161 0xfc00ffff, 0x2000537f, 0 , 0, 18162 0x0 }, /* POOL32Axf_5_group1~*(9) */ 18163 { reserved_block , 0 , 0 , 32, 18164 0xfc00ffff, 0x2000557f, 0 , 0, 18165 0x0 }, /* POOL32Axf_5_group1~*(10) */ 18166 { instruction , 0 , 0 , 32, 18167 0xfc00ffff, 0x2000577f, &EI , 0, 18168 0x0 }, /* EI */ 18169 { reserved_block , 0 , 0 , 32, 18170 0xfc00ffff, 0x2000597f, 0 , 0, 18171 0x0 }, /* POOL32Axf_5_group1~*(12) */ 18172 { reserved_block , 0 , 0 , 32, 18173 0xfc00ffff, 0x20005b7f, 0 , 0, 18174 0x0 }, /* POOL32Axf_5_group1~*(13) */ 18175 { reserved_block , 0 , 0 , 32, 18176 0xfc00ffff, 0x20005d7f, 0 , 0, 18177 0x0 }, /* POOL32Axf_5_group1~*(14) */ 18178 { reserved_block , 0 , 0 , 32, 18179 0xfc00ffff, 0x20005f7f, 0 , 0, 18180 0x0 }, /* POOL32Axf_5_group1~*(15) */ 18181 { reserved_block , 0 , 0 , 32, 18182 0xfc00ffff, 0x2000617f, 0 , 0, 18183 0x0 }, /* POOL32Axf_5_group1~*(16) */ 18184 { reserved_block , 0 , 0 , 32, 18185 0xfc00ffff, 0x2000637f, 0 , 0, 18186 0x0 }, /* POOL32Axf_5_group1~*(17) */ 18187 { reserved_block , 0 , 0 , 32, 18188 0xfc00ffff, 0x2000657f, 0 , 0, 18189 0x0 }, /* POOL32Axf_5_group1~*(18) */ 18190 { reserved_block , 0 , 0 , 32, 18191 0xfc00ffff, 0x2000677f, 0 , 0, 18192 0x0 }, /* POOL32Axf_5_group1~*(19) */ 18193 { reserved_block , 0 , 0 , 32, 18194 0xfc00ffff, 0x2000697f, 0 , 0, 18195 0x0 }, /* POOL32Axf_5_group1~*(20) */ 18196 { reserved_block , 0 , 0 , 32, 18197 0xfc00ffff, 0x20006b7f, 0 , 0, 18198 0x0 }, /* POOL32Axf_5_group1~*(21) */ 18199 { reserved_block , 0 , 0 , 32, 18200 0xfc00ffff, 0x20006d7f, 0 , 0, 18201 0x0 }, /* POOL32Axf_5_group1~*(22) */ 18202 { reserved_block , 0 , 0 , 32, 18203 0xfc00ffff, 0x20006f7f, 0 , 0, 18204 0x0 }, /* POOL32Axf_5_group1~*(23) */ 18205 { reserved_block , 0 , 0 , 32, 18206 0xfc00ffff, 0x2000717f, 0 , 0, 18207 0x0 }, /* POOL32Axf_5_group1~*(24) */ 18208 { reserved_block , 0 , 0 , 32, 18209 0xfc00ffff, 0x2000737f, 0 , 0, 18210 0x0 }, /* POOL32Axf_5_group1~*(25) */ 18211 { reserved_block , 0 , 0 , 32, 18212 0xfc00ffff, 0x2000757f, 0 , 0, 18213 0x0 }, /* POOL32Axf_5_group1~*(26) */ 18214 { reserved_block , 0 , 0 , 32, 18215 0xfc00ffff, 0x2000777f, 0 , 0, 18216 0x0 }, /* POOL32Axf_5_group1~*(27) */ 18217 { reserved_block , 0 , 0 , 32, 18218 0xfc00ffff, 0x2000797f, 0 , 0, 18219 0x0 }, /* POOL32Axf_5_group1~*(28) */ 18220 { reserved_block , 0 , 0 , 32, 18221 0xfc00ffff, 0x20007b7f, 0 , 0, 18222 0x0 }, /* POOL32Axf_5_group1~*(29) */ 18223 { reserved_block , 0 , 0 , 32, 18224 0xfc00ffff, 0x20007d7f, 0 , 0, 18225 0x0 }, /* POOL32Axf_5_group1~*(30) */ 18226 { reserved_block , 0 , 0 , 32, 18227 0xfc00ffff, 0x20007f7f, 0 , 0, 18228 0x0 }, /* POOL32Axf_5_group1~*(31) */ 18229 }; 18230 18231 18232 static const Pool ERETx[2] = { 18233 { instruction , 0 , 0 , 32, 18234 0xfc01ffff, 0x2000f37f, &ERET , 0, 18235 0x0 }, /* ERET */ 18236 { instruction , 0 , 0 , 32, 18237 0xfc01ffff, 0x2001f37f, &ERETNC , 0, 18238 0x0 }, /* ERETNC */ 18239 }; 18240 18241 18242 static const Pool POOL32Axf_5_group3[32] = { 18243 { reserved_block , 0 , 0 , 32, 18244 0xfc00ffff, 0x2000c17f, 0 , 0, 18245 0x0 }, /* POOL32Axf_5_group3~*(0) */ 18246 { instruction , 0 , 0 , 32, 18247 0xfc00ffff, 0x2000c37f, &WAIT , 0, 18248 0x0 }, /* WAIT */ 18249 { reserved_block , 0 , 0 , 32, 18250 0xfc00ffff, 0x2000c57f, 0 , 0, 18251 0x0 }, /* POOL32Axf_5_group3~*(2) */ 18252 { reserved_block , 0 , 0 , 32, 18253 0xfc00ffff, 0x2000c77f, 0 , 0, 18254 0x0 }, /* POOL32Axf_5_group3~*(3) */ 18255 { reserved_block , 0 , 0 , 32, 18256 0xfc00ffff, 0x2000c97f, 0 , 0, 18257 0x0 }, /* POOL32Axf_5_group3~*(4) */ 18258 { reserved_block , 0 , 0 , 32, 18259 0xfc00ffff, 0x2000cb7f, 0 , 0, 18260 0x0 }, /* POOL32Axf_5_group3~*(5) */ 18261 { reserved_block , 0 , 0 , 32, 18262 0xfc00ffff, 0x2000cd7f, 0 , 0, 18263 0x0 }, /* POOL32Axf_5_group3~*(6) */ 18264 { reserved_block , 0 , 0 , 32, 18265 0xfc00ffff, 0x2000cf7f, 0 , 0, 18266 0x0 }, /* POOL32Axf_5_group3~*(7) */ 18267 { reserved_block , 0 , 0 , 32, 18268 0xfc00ffff, 0x2000d17f, 0 , 0, 18269 0x0 }, /* POOL32Axf_5_group3~*(8) */ 18270 { instruction , 0 , 0 , 32, 18271 0xfc00ffff, 0x2000d37f, &IRET , 0, 18272 MCU_ }, /* IRET */ 18273 { reserved_block , 0 , 0 , 32, 18274 0xfc00ffff, 0x2000d57f, 0 , 0, 18275 0x0 }, /* POOL32Axf_5_group3~*(10) */ 18276 { reserved_block , 0 , 0 , 32, 18277 0xfc00ffff, 0x2000d77f, 0 , 0, 18278 0x0 }, /* POOL32Axf_5_group3~*(11) */ 18279 { reserved_block , 0 , 0 , 32, 18280 0xfc00ffff, 0x2000d97f, 0 , 0, 18281 0x0 }, /* POOL32Axf_5_group3~*(12) */ 18282 { reserved_block , 0 , 0 , 32, 18283 0xfc00ffff, 0x2000db7f, 0 , 0, 18284 0x0 }, /* POOL32Axf_5_group3~*(13) */ 18285 { reserved_block , 0 , 0 , 32, 18286 0xfc00ffff, 0x2000dd7f, 0 , 0, 18287 0x0 }, /* POOL32Axf_5_group3~*(14) */ 18288 { reserved_block , 0 , 0 , 32, 18289 0xfc00ffff, 0x2000df7f, 0 , 0, 18290 0x0 }, /* POOL32Axf_5_group3~*(15) */ 18291 { instruction , 0 , 0 , 32, 18292 0xfc00ffff, 0x2000e17f, &RDPGPR , 0, 18293 CP0_ }, /* RDPGPR */ 18294 { instruction , 0 , 0 , 32, 18295 0xfc00ffff, 0x2000e37f, &DERET , 0, 18296 EJTAG_ }, /* DERET */ 18297 { reserved_block , 0 , 0 , 32, 18298 0xfc00ffff, 0x2000e57f, 0 , 0, 18299 0x0 }, /* POOL32Axf_5_group3~*(18) */ 18300 { reserved_block , 0 , 0 , 32, 18301 0xfc00ffff, 0x2000e77f, 0 , 0, 18302 0x0 }, /* POOL32Axf_5_group3~*(19) */ 18303 { reserved_block , 0 , 0 , 32, 18304 0xfc00ffff, 0x2000e97f, 0 , 0, 18305 0x0 }, /* POOL32Axf_5_group3~*(20) */ 18306 { reserved_block , 0 , 0 , 32, 18307 0xfc00ffff, 0x2000eb7f, 0 , 0, 18308 0x0 }, /* POOL32Axf_5_group3~*(21) */ 18309 { reserved_block , 0 , 0 , 32, 18310 0xfc00ffff, 0x2000ed7f, 0 , 0, 18311 0x0 }, /* POOL32Axf_5_group3~*(22) */ 18312 { reserved_block , 0 , 0 , 32, 18313 0xfc00ffff, 0x2000ef7f, 0 , 0, 18314 0x0 }, /* POOL32Axf_5_group3~*(23) */ 18315 { instruction , 0 , 0 , 32, 18316 0xfc00ffff, 0x2000f17f, &WRPGPR , 0, 18317 CP0_ }, /* WRPGPR */ 18318 { pool , ERETx , 2 , 32, 18319 0xfc00ffff, 0x2000f37f, 0 , 0, 18320 0x0 }, /* ERETx */ 18321 { reserved_block , 0 , 0 , 32, 18322 0xfc00ffff, 0x2000f57f, 0 , 0, 18323 0x0 }, /* POOL32Axf_5_group3~*(26) */ 18324 { reserved_block , 0 , 0 , 32, 18325 0xfc00ffff, 0x2000f77f, 0 , 0, 18326 0x0 }, /* POOL32Axf_5_group3~*(27) */ 18327 { reserved_block , 0 , 0 , 32, 18328 0xfc00ffff, 0x2000f97f, 0 , 0, 18329 0x0 }, /* POOL32Axf_5_group3~*(28) */ 18330 { reserved_block , 0 , 0 , 32, 18331 0xfc00ffff, 0x2000fb7f, 0 , 0, 18332 0x0 }, /* POOL32Axf_5_group3~*(29) */ 18333 { reserved_block , 0 , 0 , 32, 18334 0xfc00ffff, 0x2000fd7f, 0 , 0, 18335 0x0 }, /* POOL32Axf_5_group3~*(30) */ 18336 { reserved_block , 0 , 0 , 32, 18337 0xfc00ffff, 0x2000ff7f, 0 , 0, 18338 0x0 }, /* POOL32Axf_5_group3~*(31) */ 18339 }; 18340 18341 18342 static const Pool POOL32Axf_5[4] = { 18343 { pool , POOL32Axf_5_group0 , 32 , 32, 18344 0xfc00c1ff, 0x2000017f, 0 , 0, 18345 0x0 }, /* POOL32Axf_5_group0 */ 18346 { pool , POOL32Axf_5_group1 , 32 , 32, 18347 0xfc00c1ff, 0x2000417f, 0 , 0, 18348 0x0 }, /* POOL32Axf_5_group1 */ 18349 { reserved_block , 0 , 0 , 32, 18350 0xfc00c1ff, 0x2000817f, 0 , 0, 18351 0x0 }, /* POOL32Axf_5~*(2) */ 18352 { pool , POOL32Axf_5_group3 , 32 , 32, 18353 0xfc00c1ff, 0x2000c17f, 0 , 0, 18354 0x0 }, /* POOL32Axf_5_group3 */ 18355 }; 18356 18357 18358 static const Pool SHRA__R__QB[2] = { 18359 { instruction , 0 , 0 , 32, 18360 0xfc001fff, 0x200001ff, &SHRA_QB , 0, 18361 DSP_ }, /* SHRA.QB */ 18362 { instruction , 0 , 0 , 32, 18363 0xfc001fff, 0x200011ff, &SHRA_R_QB , 0, 18364 DSP_ }, /* SHRA_R.QB */ 18365 }; 18366 18367 18368 static const Pool POOL32Axf_7[8] = { 18369 { pool , SHRA__R__QB , 2 , 32, 18370 0xfc000fff, 0x200001ff, 0 , 0, 18371 0x0 }, /* SHRA[_R].QB */ 18372 { instruction , 0 , 0 , 32, 18373 0xfc000fff, 0x200003ff, &SHRL_PH , 0, 18374 DSP_ }, /* SHRL.PH */ 18375 { instruction , 0 , 0 , 32, 18376 0xfc000fff, 0x200005ff, &REPL_QB , 0, 18377 DSP_ }, /* REPL.QB */ 18378 { reserved_block , 0 , 0 , 32, 18379 0xfc000fff, 0x200007ff, 0 , 0, 18380 0x0 }, /* POOL32Axf_7~*(3) */ 18381 { reserved_block , 0 , 0 , 32, 18382 0xfc000fff, 0x200009ff, 0 , 0, 18383 0x0 }, /* POOL32Axf_7~*(4) */ 18384 { reserved_block , 0 , 0 , 32, 18385 0xfc000fff, 0x20000bff, 0 , 0, 18386 0x0 }, /* POOL32Axf_7~*(5) */ 18387 { reserved_block , 0 , 0 , 32, 18388 0xfc000fff, 0x20000dff, 0 , 0, 18389 0x0 }, /* POOL32Axf_7~*(6) */ 18390 { reserved_block , 0 , 0 , 32, 18391 0xfc000fff, 0x20000fff, 0 , 0, 18392 0x0 }, /* POOL32Axf_7~*(7) */ 18393 }; 18394 18395 18396 static const Pool POOL32Axf[8] = { 18397 { reserved_block , 0 , 0 , 32, 18398 0xfc0001ff, 0x2000003f, 0 , 0, 18399 0x0 }, /* POOL32Axf~*(0) */ 18400 { pool , POOL32Axf_1 , 8 , 32, 18401 0xfc0001ff, 0x2000007f, 0 , 0, 18402 0x0 }, /* POOL32Axf_1 */ 18403 { pool , POOL32Axf_2 , 4 , 32, 18404 0xfc0001ff, 0x200000bf, 0 , 0, 18405 0x0 }, /* POOL32Axf_2 */ 18406 { reserved_block , 0 , 0 , 32, 18407 0xfc0001ff, 0x200000ff, 0 , 0, 18408 0x0 }, /* POOL32Axf~*(3) */ 18409 { pool , POOL32Axf_4 , 128 , 32, 18410 0xfc0001ff, 0x2000013f, 0 , 0, 18411 0x0 }, /* POOL32Axf_4 */ 18412 { pool , POOL32Axf_5 , 4 , 32, 18413 0xfc0001ff, 0x2000017f, 0 , 0, 18414 0x0 }, /* POOL32Axf_5 */ 18415 { reserved_block , 0 , 0 , 32, 18416 0xfc0001ff, 0x200001bf, 0 , 0, 18417 0x0 }, /* POOL32Axf~*(6) */ 18418 { pool , POOL32Axf_7 , 8 , 32, 18419 0xfc0001ff, 0x200001ff, 0 , 0, 18420 0x0 }, /* POOL32Axf_7 */ 18421 }; 18422 18423 18424 static const Pool _POOL32A7[8] = { 18425 { pool , P_LSX , 2 , 32, 18426 0xfc00003f, 0x20000007, 0 , 0, 18427 0x0 }, /* P.LSX */ 18428 { instruction , 0 , 0 , 32, 18429 0xfc00003f, 0x2000000f, &LSA , 0, 18430 0x0 }, /* LSA */ 18431 { reserved_block , 0 , 0 , 32, 18432 0xfc00003f, 0x20000017, 0 , 0, 18433 0x0 }, /* _POOL32A7~*(2) */ 18434 { instruction , 0 , 0 , 32, 18435 0xfc00003f, 0x2000001f, &EXTW , 0, 18436 0x0 }, /* EXTW */ 18437 { reserved_block , 0 , 0 , 32, 18438 0xfc00003f, 0x20000027, 0 , 0, 18439 0x0 }, /* _POOL32A7~*(4) */ 18440 { reserved_block , 0 , 0 , 32, 18441 0xfc00003f, 0x2000002f, 0 , 0, 18442 0x0 }, /* _POOL32A7~*(5) */ 18443 { reserved_block , 0 , 0 , 32, 18444 0xfc00003f, 0x20000037, 0 , 0, 18445 0x0 }, /* _POOL32A7~*(6) */ 18446 { pool , POOL32Axf , 8 , 32, 18447 0xfc00003f, 0x2000003f, 0 , 0, 18448 0x0 }, /* POOL32Axf */ 18449 }; 18450 18451 18452 static const Pool P32A[8] = { 18453 { pool , _POOL32A0 , 128 , 32, 18454 0xfc000007, 0x20000000, 0 , 0, 18455 0x0 }, /* _POOL32A0 */ 18456 { instruction , 0 , 0 , 32, 18457 0xfc000007, 0x20000001, &SPECIAL2 , 0, 18458 UDI_ }, /* SPECIAL2 */ 18459 { instruction , 0 , 0 , 32, 18460 0xfc000007, 0x20000002, &COP2_1 , 0, 18461 CP2_ }, /* COP2_1 */ 18462 { instruction , 0 , 0 , 32, 18463 0xfc000007, 0x20000003, &UDI , 0, 18464 UDI_ }, /* UDI */ 18465 { reserved_block , 0 , 0 , 32, 18466 0xfc000007, 0x20000004, 0 , 0, 18467 0x0 }, /* P32A~*(4) */ 18468 { pool , _POOL32A5 , 128 , 32, 18469 0xfc000007, 0x20000005, 0 , 0, 18470 0x0 }, /* _POOL32A5 */ 18471 { reserved_block , 0 , 0 , 32, 18472 0xfc000007, 0x20000006, 0 , 0, 18473 0x0 }, /* P32A~*(6) */ 18474 { pool , _POOL32A7 , 8 , 32, 18475 0xfc000007, 0x20000007, 0 , 0, 18476 0x0 }, /* _POOL32A7 */ 18477 }; 18478 18479 18480 static const Pool P_GP_D[2] = { 18481 { instruction , 0 , 0 , 32, 18482 0xfc000007, 0x40000001, &LD_GP_ , 0, 18483 MIPS64_ }, /* LD[GP] */ 18484 { instruction , 0 , 0 , 32, 18485 0xfc000007, 0x40000005, &SD_GP_ , 0, 18486 MIPS64_ }, /* SD[GP] */ 18487 }; 18488 18489 18490 static const Pool P_GP_W[4] = { 18491 { instruction , 0 , 0 , 32, 18492 0xfc000003, 0x40000000, &ADDIU_GP_W_ , 0, 18493 0x0 }, /* ADDIU[GP.W] */ 18494 { pool , P_GP_D , 2 , 32, 18495 0xfc000003, 0x40000001, 0 , 0, 18496 0x0 }, /* P.GP.D */ 18497 { instruction , 0 , 0 , 32, 18498 0xfc000003, 0x40000002, &LW_GP_ , 0, 18499 0x0 }, /* LW[GP] */ 18500 { instruction , 0 , 0 , 32, 18501 0xfc000003, 0x40000003, &SW_GP_ , 0, 18502 0x0 }, /* SW[GP] */ 18503 }; 18504 18505 18506 static const Pool POOL48I[32] = { 18507 { instruction , 0 , 0 , 48, 18508 0xfc1f00000000ull, 0x600000000000ull, &LI_48_ , 0, 18509 XMMS_ }, /* LI[48] */ 18510 { instruction , 0 , 0 , 48, 18511 0xfc1f00000000ull, 0x600100000000ull, &ADDIU_48_ , 0, 18512 XMMS_ }, /* ADDIU[48] */ 18513 { instruction , 0 , 0 , 48, 18514 0xfc1f00000000ull, 0x600200000000ull, &ADDIU_GP48_ , 0, 18515 XMMS_ }, /* ADDIU[GP48] */ 18516 { instruction , 0 , 0 , 48, 18517 0xfc1f00000000ull, 0x600300000000ull, &ADDIUPC_48_ , 0, 18518 XMMS_ }, /* ADDIUPC[48] */ 18519 { reserved_block , 0 , 0 , 48, 18520 0xfc1f00000000ull, 0x600400000000ull, 0 , 0, 18521 0x0 }, /* POOL48I~*(4) */ 18522 { reserved_block , 0 , 0 , 48, 18523 0xfc1f00000000ull, 0x600500000000ull, 0 , 0, 18524 0x0 }, /* POOL48I~*(5) */ 18525 { reserved_block , 0 , 0 , 48, 18526 0xfc1f00000000ull, 0x600600000000ull, 0 , 0, 18527 0x0 }, /* POOL48I~*(6) */ 18528 { reserved_block , 0 , 0 , 48, 18529 0xfc1f00000000ull, 0x600700000000ull, 0 , 0, 18530 0x0 }, /* POOL48I~*(7) */ 18531 { reserved_block , 0 , 0 , 48, 18532 0xfc1f00000000ull, 0x600800000000ull, 0 , 0, 18533 0x0 }, /* POOL48I~*(8) */ 18534 { reserved_block , 0 , 0 , 48, 18535 0xfc1f00000000ull, 0x600900000000ull, 0 , 0, 18536 0x0 }, /* POOL48I~*(9) */ 18537 { reserved_block , 0 , 0 , 48, 18538 0xfc1f00000000ull, 0x600a00000000ull, 0 , 0, 18539 0x0 }, /* POOL48I~*(10) */ 18540 { instruction , 0 , 0 , 48, 18541 0xfc1f00000000ull, 0x600b00000000ull, &LWPC_48_ , 0, 18542 XMMS_ }, /* LWPC[48] */ 18543 { reserved_block , 0 , 0 , 48, 18544 0xfc1f00000000ull, 0x600c00000000ull, 0 , 0, 18545 0x0 }, /* POOL48I~*(12) */ 18546 { reserved_block , 0 , 0 , 48, 18547 0xfc1f00000000ull, 0x600d00000000ull, 0 , 0, 18548 0x0 }, /* POOL48I~*(13) */ 18549 { reserved_block , 0 , 0 , 48, 18550 0xfc1f00000000ull, 0x600e00000000ull, 0 , 0, 18551 0x0 }, /* POOL48I~*(14) */ 18552 { instruction , 0 , 0 , 48, 18553 0xfc1f00000000ull, 0x600f00000000ull, &SWPC_48_ , 0, 18554 XMMS_ }, /* SWPC[48] */ 18555 { reserved_block , 0 , 0 , 48, 18556 0xfc1f00000000ull, 0x601000000000ull, 0 , 0, 18557 0x0 }, /* POOL48I~*(16) */ 18558 { instruction , 0 , 0 , 48, 18559 0xfc1f00000000ull, 0x601100000000ull, &DADDIU_48_ , 0, 18560 MIPS64_ }, /* DADDIU[48] */ 18561 { reserved_block , 0 , 0 , 48, 18562 0xfc1f00000000ull, 0x601200000000ull, 0 , 0, 18563 0x0 }, /* POOL48I~*(18) */ 18564 { reserved_block , 0 , 0 , 48, 18565 0xfc1f00000000ull, 0x601300000000ull, 0 , 0, 18566 0x0 }, /* POOL48I~*(19) */ 18567 { instruction , 0 , 0 , 48, 18568 0xfc1f00000000ull, 0x601400000000ull, &DLUI_48_ , 0, 18569 MIPS64_ }, /* DLUI[48] */ 18570 { reserved_block , 0 , 0 , 48, 18571 0xfc1f00000000ull, 0x601500000000ull, 0 , 0, 18572 0x0 }, /* POOL48I~*(21) */ 18573 { reserved_block , 0 , 0 , 48, 18574 0xfc1f00000000ull, 0x601600000000ull, 0 , 0, 18575 0x0 }, /* POOL48I~*(22) */ 18576 { reserved_block , 0 , 0 , 48, 18577 0xfc1f00000000ull, 0x601700000000ull, 0 , 0, 18578 0x0 }, /* POOL48I~*(23) */ 18579 { reserved_block , 0 , 0 , 48, 18580 0xfc1f00000000ull, 0x601800000000ull, 0 , 0, 18581 0x0 }, /* POOL48I~*(24) */ 18582 { reserved_block , 0 , 0 , 48, 18583 0xfc1f00000000ull, 0x601900000000ull, 0 , 0, 18584 0x0 }, /* POOL48I~*(25) */ 18585 { reserved_block , 0 , 0 , 48, 18586 0xfc1f00000000ull, 0x601a00000000ull, 0 , 0, 18587 0x0 }, /* POOL48I~*(26) */ 18588 { instruction , 0 , 0 , 48, 18589 0xfc1f00000000ull, 0x601b00000000ull, &LDPC_48_ , 0, 18590 MIPS64_ }, /* LDPC[48] */ 18591 { reserved_block , 0 , 0 , 48, 18592 0xfc1f00000000ull, 0x601c00000000ull, 0 , 0, 18593 0x0 }, /* POOL48I~*(28) */ 18594 { reserved_block , 0 , 0 , 48, 18595 0xfc1f00000000ull, 0x601d00000000ull, 0 , 0, 18596 0x0 }, /* POOL48I~*(29) */ 18597 { reserved_block , 0 , 0 , 48, 18598 0xfc1f00000000ull, 0x601e00000000ull, 0 , 0, 18599 0x0 }, /* POOL48I~*(30) */ 18600 { instruction , 0 , 0 , 48, 18601 0xfc1f00000000ull, 0x601f00000000ull, &SDPC_48_ , 0, 18602 MIPS64_ }, /* SDPC[48] */ 18603 }; 18604 18605 18606 static const Pool PP_SR[4] = { 18607 { instruction , 0 , 0 , 32, 18608 0xfc10f003, 0x80003000, &SAVE_32_ , 0, 18609 0x0 }, /* SAVE[32] */ 18610 { reserved_block , 0 , 0 , 32, 18611 0xfc10f003, 0x80003001, 0 , 0, 18612 0x0 }, /* PP.SR~*(1) */ 18613 { instruction , 0 , 0 , 32, 18614 0xfc10f003, 0x80003002, &RESTORE_32_ , 0, 18615 0x0 }, /* RESTORE[32] */ 18616 { return_instruction , 0 , 0 , 32, 18617 0xfc10f003, 0x80003003, &RESTORE_JRC_32_ , 0, 18618 0x0 }, /* RESTORE.JRC[32] */ 18619 }; 18620 18621 18622 static const Pool P_SR_F[8] = { 18623 { instruction , 0 , 0 , 32, 18624 0xfc10f007, 0x80103000, &SAVEF , 0, 18625 CP1_ }, /* SAVEF */ 18626 { instruction , 0 , 0 , 32, 18627 0xfc10f007, 0x80103001, &RESTOREF , 0, 18628 CP1_ }, /* RESTOREF */ 18629 { reserved_block , 0 , 0 , 32, 18630 0xfc10f007, 0x80103002, 0 , 0, 18631 0x0 }, /* P.SR.F~*(2) */ 18632 { reserved_block , 0 , 0 , 32, 18633 0xfc10f007, 0x80103003, 0 , 0, 18634 0x0 }, /* P.SR.F~*(3) */ 18635 { reserved_block , 0 , 0 , 32, 18636 0xfc10f007, 0x80103004, 0 , 0, 18637 0x0 }, /* P.SR.F~*(4) */ 18638 { reserved_block , 0 , 0 , 32, 18639 0xfc10f007, 0x80103005, 0 , 0, 18640 0x0 }, /* P.SR.F~*(5) */ 18641 { reserved_block , 0 , 0 , 32, 18642 0xfc10f007, 0x80103006, 0 , 0, 18643 0x0 }, /* P.SR.F~*(6) */ 18644 { reserved_block , 0 , 0 , 32, 18645 0xfc10f007, 0x80103007, 0 , 0, 18646 0x0 }, /* P.SR.F~*(7) */ 18647 }; 18648 18649 18650 static const Pool P_SR[2] = { 18651 { pool , PP_SR , 4 , 32, 18652 0xfc10f000, 0x80003000, 0 , 0, 18653 0x0 }, /* PP.SR */ 18654 { pool , P_SR_F , 8 , 32, 18655 0xfc10f000, 0x80103000, 0 , 0, 18656 0x0 }, /* P.SR.F */ 18657 }; 18658 18659 18660 static const Pool P_SLL[5] = { 18661 { instruction , 0 , 0 , 32, 18662 0xffe0f1ff, 0x8000c000, &NOP_32_ , 0, 18663 0x0 }, /* NOP[32] */ 18664 { instruction , 0 , 0 , 32, 18665 0xffe0f1ff, 0x8000c003, &EHB , 0, 18666 0x0 }, /* EHB */ 18667 { instruction , 0 , 0 , 32, 18668 0xffe0f1ff, 0x8000c005, &PAUSE , 0, 18669 0x0 }, /* PAUSE */ 18670 { instruction , 0 , 0 , 32, 18671 0xffe0f1ff, 0x8000c006, &SYNC , 0, 18672 0x0 }, /* SYNC */ 18673 { instruction , 0 , 0 , 32, 18674 0xfc00f1e0, 0x8000c000, &SLL_32_ , 0, 18675 0x0 }, /* SLL[32] */ 18676 }; 18677 18678 18679 static const Pool P_SHIFT[16] = { 18680 { pool , P_SLL , 5 , 32, 18681 0xfc00f1e0, 0x8000c000, 0 , 0, 18682 0x0 }, /* P.SLL */ 18683 { reserved_block , 0 , 0 , 32, 18684 0xfc00f1e0, 0x8000c020, 0 , 0, 18685 0x0 }, /* P.SHIFT~*(1) */ 18686 { instruction , 0 , 0 , 32, 18687 0xfc00f1e0, 0x8000c040, &SRL_32_ , 0, 18688 0x0 }, /* SRL[32] */ 18689 { reserved_block , 0 , 0 , 32, 18690 0xfc00f1e0, 0x8000c060, 0 , 0, 18691 0x0 }, /* P.SHIFT~*(3) */ 18692 { instruction , 0 , 0 , 32, 18693 0xfc00f1e0, 0x8000c080, &SRA , 0, 18694 0x0 }, /* SRA */ 18695 { reserved_block , 0 , 0 , 32, 18696 0xfc00f1e0, 0x8000c0a0, 0 , 0, 18697 0x0 }, /* P.SHIFT~*(5) */ 18698 { instruction , 0 , 0 , 32, 18699 0xfc00f1e0, 0x8000c0c0, &ROTR , 0, 18700 0x0 }, /* ROTR */ 18701 { reserved_block , 0 , 0 , 32, 18702 0xfc00f1e0, 0x8000c0e0, 0 , 0, 18703 0x0 }, /* P.SHIFT~*(7) */ 18704 { instruction , 0 , 0 , 32, 18705 0xfc00f1e0, 0x8000c100, &DSLL , 0, 18706 MIPS64_ }, /* DSLL */ 18707 { instruction , 0 , 0 , 32, 18708 0xfc00f1e0, 0x8000c120, &DSLL32 , 0, 18709 MIPS64_ }, /* DSLL32 */ 18710 { instruction , 0 , 0 , 32, 18711 0xfc00f1e0, 0x8000c140, &DSRL , 0, 18712 MIPS64_ }, /* DSRL */ 18713 { instruction , 0 , 0 , 32, 18714 0xfc00f1e0, 0x8000c160, &DSRL32 , 0, 18715 MIPS64_ }, /* DSRL32 */ 18716 { instruction , 0 , 0 , 32, 18717 0xfc00f1e0, 0x8000c180, &DSRA , 0, 18718 MIPS64_ }, /* DSRA */ 18719 { instruction , 0 , 0 , 32, 18720 0xfc00f1e0, 0x8000c1a0, &DSRA32 , 0, 18721 MIPS64_ }, /* DSRA32 */ 18722 { instruction , 0 , 0 , 32, 18723 0xfc00f1e0, 0x8000c1c0, &DROTR , 0, 18724 MIPS64_ }, /* DROTR */ 18725 { instruction , 0 , 0 , 32, 18726 0xfc00f1e0, 0x8000c1e0, &DROTR32 , 0, 18727 MIPS64_ }, /* DROTR32 */ 18728 }; 18729 18730 18731 static const Pool P_ROTX[4] = { 18732 { instruction , 0 , 0 , 32, 18733 0xfc00f820, 0x8000d000, &ROTX , 0, 18734 XMMS_ }, /* ROTX */ 18735 { reserved_block , 0 , 0 , 32, 18736 0xfc00f820, 0x8000d020, 0 , 0, 18737 0x0 }, /* P.ROTX~*(1) */ 18738 { reserved_block , 0 , 0 , 32, 18739 0xfc00f820, 0x8000d800, 0 , 0, 18740 0x0 }, /* P.ROTX~*(2) */ 18741 { reserved_block , 0 , 0 , 32, 18742 0xfc00f820, 0x8000d820, 0 , 0, 18743 0x0 }, /* P.ROTX~*(3) */ 18744 }; 18745 18746 18747 static const Pool P_INS[4] = { 18748 { instruction , 0 , 0 , 32, 18749 0xfc00f820, 0x8000e000, &INS , 0, 18750 XMMS_ }, /* INS */ 18751 { instruction , 0 , 0 , 32, 18752 0xfc00f820, 0x8000e020, &DINSU , 0, 18753 MIPS64_ }, /* DINSU */ 18754 { instruction , 0 , 0 , 32, 18755 0xfc00f820, 0x8000e800, &DINSM , 0, 18756 MIPS64_ }, /* DINSM */ 18757 { instruction , 0 , 0 , 32, 18758 0xfc00f820, 0x8000e820, &DINS , 0, 18759 MIPS64_ }, /* DINS */ 18760 }; 18761 18762 18763 static const Pool P_EXT[4] = { 18764 { instruction , 0 , 0 , 32, 18765 0xfc00f820, 0x8000f000, &EXT , 0, 18766 XMMS_ }, /* EXT */ 18767 { instruction , 0 , 0 , 32, 18768 0xfc00f820, 0x8000f020, &DEXTU , 0, 18769 MIPS64_ }, /* DEXTU */ 18770 { instruction , 0 , 0 , 32, 18771 0xfc00f820, 0x8000f800, &DEXTM , 0, 18772 MIPS64_ }, /* DEXTM */ 18773 { instruction , 0 , 0 , 32, 18774 0xfc00f820, 0x8000f820, &DEXT , 0, 18775 MIPS64_ }, /* DEXT */ 18776 }; 18777 18778 18779 static const Pool P_U12[16] = { 18780 { instruction , 0 , 0 , 32, 18781 0xfc00f000, 0x80000000, &ORI , 0, 18782 0x0 }, /* ORI */ 18783 { instruction , 0 , 0 , 32, 18784 0xfc00f000, 0x80001000, &XORI , 0, 18785 0x0 }, /* XORI */ 18786 { instruction , 0 , 0 , 32, 18787 0xfc00f000, 0x80002000, &ANDI_32_ , 0, 18788 0x0 }, /* ANDI[32] */ 18789 { pool , P_SR , 2 , 32, 18790 0xfc00f000, 0x80003000, 0 , 0, 18791 0x0 }, /* P.SR */ 18792 { instruction , 0 , 0 , 32, 18793 0xfc00f000, 0x80004000, &SLTI , 0, 18794 0x0 }, /* SLTI */ 18795 { instruction , 0 , 0 , 32, 18796 0xfc00f000, 0x80005000, &SLTIU , 0, 18797 0x0 }, /* SLTIU */ 18798 { instruction , 0 , 0 , 32, 18799 0xfc00f000, 0x80006000, &SEQI , 0, 18800 0x0 }, /* SEQI */ 18801 { reserved_block , 0 , 0 , 32, 18802 0xfc00f000, 0x80007000, 0 , 0, 18803 0x0 }, /* P.U12~*(7) */ 18804 { instruction , 0 , 0 , 32, 18805 0xfc00f000, 0x80008000, &ADDIU_NEG_ , 0, 18806 0x0 }, /* ADDIU[NEG] */ 18807 { instruction , 0 , 0 , 32, 18808 0xfc00f000, 0x80009000, &DADDIU_U12_ , 0, 18809 MIPS64_ }, /* DADDIU[U12] */ 18810 { instruction , 0 , 0 , 32, 18811 0xfc00f000, 0x8000a000, &DADDIU_NEG_ , 0, 18812 MIPS64_ }, /* DADDIU[NEG] */ 18813 { instruction , 0 , 0 , 32, 18814 0xfc00f000, 0x8000b000, &DROTX , 0, 18815 MIPS64_ }, /* DROTX */ 18816 { pool , P_SHIFT , 16 , 32, 18817 0xfc00f000, 0x8000c000, 0 , 0, 18818 0x0 }, /* P.SHIFT */ 18819 { pool , P_ROTX , 4 , 32, 18820 0xfc00f000, 0x8000d000, 0 , 0, 18821 0x0 }, /* P.ROTX */ 18822 { pool , P_INS , 4 , 32, 18823 0xfc00f000, 0x8000e000, 0 , 0, 18824 0x0 }, /* P.INS */ 18825 { pool , P_EXT , 4 , 32, 18826 0xfc00f000, 0x8000f000, 0 , 0, 18827 0x0 }, /* P.EXT */ 18828 }; 18829 18830 18831 static const Pool RINT_fmt[2] = { 18832 { instruction , 0 , 0 , 32, 18833 0xfc0003ff, 0xa0000020, &RINT_S , 0, 18834 CP1_ }, /* RINT.S */ 18835 { instruction , 0 , 0 , 32, 18836 0xfc0003ff, 0xa0000220, &RINT_D , 0, 18837 CP1_ }, /* RINT.D */ 18838 }; 18839 18840 18841 static const Pool ADD_fmt0[2] = { 18842 { instruction , 0 , 0 , 32, 18843 0xfc0003ff, 0xa0000030, &ADD_S , 0, 18844 CP1_ }, /* ADD.S */ 18845 { reserved_block , 0 , 0 , 32, 18846 0xfc0003ff, 0xa0000230, 0 , 0, 18847 CP1_ }, /* ADD.fmt0~*(1) */ 18848 }; 18849 18850 18851 static const Pool SELEQZ_fmt[2] = { 18852 { instruction , 0 , 0 , 32, 18853 0xfc0003ff, 0xa0000038, &SELEQZ_S , 0, 18854 CP1_ }, /* SELEQZ.S */ 18855 { instruction , 0 , 0 , 32, 18856 0xfc0003ff, 0xa0000238, &SELEQZ_D , 0, 18857 CP1_ }, /* SELEQZ.D */ 18858 }; 18859 18860 18861 static const Pool CLASS_fmt[2] = { 18862 { instruction , 0 , 0 , 32, 18863 0xfc0003ff, 0xa0000060, &CLASS_S , 0, 18864 CP1_ }, /* CLASS.S */ 18865 { instruction , 0 , 0 , 32, 18866 0xfc0003ff, 0xa0000260, &CLASS_D , 0, 18867 CP1_ }, /* CLASS.D */ 18868 }; 18869 18870 18871 static const Pool SUB_fmt0[2] = { 18872 { instruction , 0 , 0 , 32, 18873 0xfc0003ff, 0xa0000070, &SUB_S , 0, 18874 CP1_ }, /* SUB.S */ 18875 { reserved_block , 0 , 0 , 32, 18876 0xfc0003ff, 0xa0000270, 0 , 0, 18877 CP1_ }, /* SUB.fmt0~*(1) */ 18878 }; 18879 18880 18881 static const Pool SELNEZ_fmt[2] = { 18882 { instruction , 0 , 0 , 32, 18883 0xfc0003ff, 0xa0000078, &SELNEZ_S , 0, 18884 CP1_ }, /* SELNEZ.S */ 18885 { instruction , 0 , 0 , 32, 18886 0xfc0003ff, 0xa0000278, &SELNEZ_D , 0, 18887 CP1_ }, /* SELNEZ.D */ 18888 }; 18889 18890 18891 static const Pool MUL_fmt0[2] = { 18892 { instruction , 0 , 0 , 32, 18893 0xfc0003ff, 0xa00000b0, &MUL_S , 0, 18894 CP1_ }, /* MUL.S */ 18895 { reserved_block , 0 , 0 , 32, 18896 0xfc0003ff, 0xa00002b0, 0 , 0, 18897 CP1_ }, /* MUL.fmt0~*(1) */ 18898 }; 18899 18900 18901 static const Pool SEL_fmt[2] = { 18902 { instruction , 0 , 0 , 32, 18903 0xfc0003ff, 0xa00000b8, &SEL_S , 0, 18904 CP1_ }, /* SEL.S */ 18905 { instruction , 0 , 0 , 32, 18906 0xfc0003ff, 0xa00002b8, &SEL_D , 0, 18907 CP1_ }, /* SEL.D */ 18908 }; 18909 18910 18911 static const Pool DIV_fmt0[2] = { 18912 { instruction , 0 , 0 , 32, 18913 0xfc0003ff, 0xa00000f0, &DIV_S , 0, 18914 CP1_ }, /* DIV.S */ 18915 { reserved_block , 0 , 0 , 32, 18916 0xfc0003ff, 0xa00002f0, 0 , 0, 18917 CP1_ }, /* DIV.fmt0~*(1) */ 18918 }; 18919 18920 18921 static const Pool ADD_fmt1[2] = { 18922 { instruction , 0 , 0 , 32, 18923 0xfc0003ff, 0xa0000130, &ADD_D , 0, 18924 CP1_ }, /* ADD.D */ 18925 { reserved_block , 0 , 0 , 32, 18926 0xfc0003ff, 0xa0000330, 0 , 0, 18927 CP1_ }, /* ADD.fmt1~*(1) */ 18928 }; 18929 18930 18931 static const Pool SUB_fmt1[2] = { 18932 { instruction , 0 , 0 , 32, 18933 0xfc0003ff, 0xa0000170, &SUB_D , 0, 18934 CP1_ }, /* SUB.D */ 18935 { reserved_block , 0 , 0 , 32, 18936 0xfc0003ff, 0xa0000370, 0 , 0, 18937 CP1_ }, /* SUB.fmt1~*(1) */ 18938 }; 18939 18940 18941 static const Pool MUL_fmt1[2] = { 18942 { instruction , 0 , 0 , 32, 18943 0xfc0003ff, 0xa00001b0, &MUL_D , 0, 18944 CP1_ }, /* MUL.D */ 18945 { reserved_block , 0 , 0 , 32, 18946 0xfc0003ff, 0xa00003b0, 0 , 0, 18947 CP1_ }, /* MUL.fmt1~*(1) */ 18948 }; 18949 18950 18951 static const Pool MADDF_fmt[2] = { 18952 { instruction , 0 , 0 , 32, 18953 0xfc0003ff, 0xa00001b8, &MADDF_S , 0, 18954 CP1_ }, /* MADDF.S */ 18955 { instruction , 0 , 0 , 32, 18956 0xfc0003ff, 0xa00003b8, &MADDF_D , 0, 18957 CP1_ }, /* MADDF.D */ 18958 }; 18959 18960 18961 static const Pool DIV_fmt1[2] = { 18962 { instruction , 0 , 0 , 32, 18963 0xfc0003ff, 0xa00001f0, &DIV_D , 0, 18964 CP1_ }, /* DIV.D */ 18965 { reserved_block , 0 , 0 , 32, 18966 0xfc0003ff, 0xa00003f0, 0 , 0, 18967 CP1_ }, /* DIV.fmt1~*(1) */ 18968 }; 18969 18970 18971 static const Pool MSUBF_fmt[2] = { 18972 { instruction , 0 , 0 , 32, 18973 0xfc0003ff, 0xa00001f8, &MSUBF_S , 0, 18974 CP1_ }, /* MSUBF.S */ 18975 { instruction , 0 , 0 , 32, 18976 0xfc0003ff, 0xa00003f8, &MSUBF_D , 0, 18977 CP1_ }, /* MSUBF.D */ 18978 }; 18979 18980 18981 static const Pool POOL32F_0[64] = { 18982 { reserved_block , 0 , 0 , 32, 18983 0xfc0001ff, 0xa0000000, 0 , 0, 18984 CP1_ }, /* POOL32F_0~*(0) */ 18985 { reserved_block , 0 , 0 , 32, 18986 0xfc0001ff, 0xa0000008, 0 , 0, 18987 CP1_ }, /* POOL32F_0~*(1) */ 18988 { reserved_block , 0 , 0 , 32, 18989 0xfc0001ff, 0xa0000010, 0 , 0, 18990 CP1_ }, /* POOL32F_0~*(2) */ 18991 { reserved_block , 0 , 0 , 32, 18992 0xfc0001ff, 0xa0000018, 0 , 0, 18993 CP1_ }, /* POOL32F_0~*(3) */ 18994 { pool , RINT_fmt , 2 , 32, 18995 0xfc0001ff, 0xa0000020, 0 , 0, 18996 CP1_ }, /* RINT.fmt */ 18997 { reserved_block , 0 , 0 , 32, 18998 0xfc0001ff, 0xa0000028, 0 , 0, 18999 CP1_ }, /* POOL32F_0~*(5) */ 19000 { pool , ADD_fmt0 , 2 , 32, 19001 0xfc0001ff, 0xa0000030, 0 , 0, 19002 CP1_ }, /* ADD.fmt0 */ 19003 { pool , SELEQZ_fmt , 2 , 32, 19004 0xfc0001ff, 0xa0000038, 0 , 0, 19005 CP1_ }, /* SELEQZ.fmt */ 19006 { reserved_block , 0 , 0 , 32, 19007 0xfc0001ff, 0xa0000040, 0 , 0, 19008 CP1_ }, /* POOL32F_0~*(8) */ 19009 { reserved_block , 0 , 0 , 32, 19010 0xfc0001ff, 0xa0000048, 0 , 0, 19011 CP1_ }, /* POOL32F_0~*(9) */ 19012 { reserved_block , 0 , 0 , 32, 19013 0xfc0001ff, 0xa0000050, 0 , 0, 19014 CP1_ }, /* POOL32F_0~*(10) */ 19015 { reserved_block , 0 , 0 , 32, 19016 0xfc0001ff, 0xa0000058, 0 , 0, 19017 CP1_ }, /* POOL32F_0~*(11) */ 19018 { pool , CLASS_fmt , 2 , 32, 19019 0xfc0001ff, 0xa0000060, 0 , 0, 19020 CP1_ }, /* CLASS.fmt */ 19021 { reserved_block , 0 , 0 , 32, 19022 0xfc0001ff, 0xa0000068, 0 , 0, 19023 CP1_ }, /* POOL32F_0~*(13) */ 19024 { pool , SUB_fmt0 , 2 , 32, 19025 0xfc0001ff, 0xa0000070, 0 , 0, 19026 CP1_ }, /* SUB.fmt0 */ 19027 { pool , SELNEZ_fmt , 2 , 32, 19028 0xfc0001ff, 0xa0000078, 0 , 0, 19029 CP1_ }, /* SELNEZ.fmt */ 19030 { reserved_block , 0 , 0 , 32, 19031 0xfc0001ff, 0xa0000080, 0 , 0, 19032 CP1_ }, /* POOL32F_0~*(16) */ 19033 { reserved_block , 0 , 0 , 32, 19034 0xfc0001ff, 0xa0000088, 0 , 0, 19035 CP1_ }, /* POOL32F_0~*(17) */ 19036 { reserved_block , 0 , 0 , 32, 19037 0xfc0001ff, 0xa0000090, 0 , 0, 19038 CP1_ }, /* POOL32F_0~*(18) */ 19039 { reserved_block , 0 , 0 , 32, 19040 0xfc0001ff, 0xa0000098, 0 , 0, 19041 CP1_ }, /* POOL32F_0~*(19) */ 19042 { reserved_block , 0 , 0 , 32, 19043 0xfc0001ff, 0xa00000a0, 0 , 0, 19044 CP1_ }, /* POOL32F_0~*(20) */ 19045 { reserved_block , 0 , 0 , 32, 19046 0xfc0001ff, 0xa00000a8, 0 , 0, 19047 CP1_ }, /* POOL32F_0~*(21) */ 19048 { pool , MUL_fmt0 , 2 , 32, 19049 0xfc0001ff, 0xa00000b0, 0 , 0, 19050 CP1_ }, /* MUL.fmt0 */ 19051 { pool , SEL_fmt , 2 , 32, 19052 0xfc0001ff, 0xa00000b8, 0 , 0, 19053 CP1_ }, /* SEL.fmt */ 19054 { reserved_block , 0 , 0 , 32, 19055 0xfc0001ff, 0xa00000c0, 0 , 0, 19056 CP1_ }, /* POOL32F_0~*(24) */ 19057 { reserved_block , 0 , 0 , 32, 19058 0xfc0001ff, 0xa00000c8, 0 , 0, 19059 CP1_ }, /* POOL32F_0~*(25) */ 19060 { reserved_block , 0 , 0 , 32, 19061 0xfc0001ff, 0xa00000d0, 0 , 0, 19062 CP1_ }, /* POOL32F_0~*(26) */ 19063 { reserved_block , 0 , 0 , 32, 19064 0xfc0001ff, 0xa00000d8, 0 , 0, 19065 CP1_ }, /* POOL32F_0~*(27) */ 19066 { reserved_block , 0 , 0 , 32, 19067 0xfc0001ff, 0xa00000e0, 0 , 0, 19068 CP1_ }, /* POOL32F_0~*(28) */ 19069 { reserved_block , 0 , 0 , 32, 19070 0xfc0001ff, 0xa00000e8, 0 , 0, 19071 CP1_ }, /* POOL32F_0~*(29) */ 19072 { pool , DIV_fmt0 , 2 , 32, 19073 0xfc0001ff, 0xa00000f0, 0 , 0, 19074 CP1_ }, /* DIV.fmt0 */ 19075 { reserved_block , 0 , 0 , 32, 19076 0xfc0001ff, 0xa00000f8, 0 , 0, 19077 CP1_ }, /* POOL32F_0~*(31) */ 19078 { reserved_block , 0 , 0 , 32, 19079 0xfc0001ff, 0xa0000100, 0 , 0, 19080 CP1_ }, /* POOL32F_0~*(32) */ 19081 { reserved_block , 0 , 0 , 32, 19082 0xfc0001ff, 0xa0000108, 0 , 0, 19083 CP1_ }, /* POOL32F_0~*(33) */ 19084 { reserved_block , 0 , 0 , 32, 19085 0xfc0001ff, 0xa0000110, 0 , 0, 19086 CP1_ }, /* POOL32F_0~*(34) */ 19087 { reserved_block , 0 , 0 , 32, 19088 0xfc0001ff, 0xa0000118, 0 , 0, 19089 CP1_ }, /* POOL32F_0~*(35) */ 19090 { reserved_block , 0 , 0 , 32, 19091 0xfc0001ff, 0xa0000120, 0 , 0, 19092 CP1_ }, /* POOL32F_0~*(36) */ 19093 { reserved_block , 0 , 0 , 32, 19094 0xfc0001ff, 0xa0000128, 0 , 0, 19095 CP1_ }, /* POOL32F_0~*(37) */ 19096 { pool , ADD_fmt1 , 2 , 32, 19097 0xfc0001ff, 0xa0000130, 0 , 0, 19098 CP1_ }, /* ADD.fmt1 */ 19099 { reserved_block , 0 , 0 , 32, 19100 0xfc0001ff, 0xa0000138, 0 , 0, 19101 CP1_ }, /* POOL32F_0~*(39) */ 19102 { reserved_block , 0 , 0 , 32, 19103 0xfc0001ff, 0xa0000140, 0 , 0, 19104 CP1_ }, /* POOL32F_0~*(40) */ 19105 { reserved_block , 0 , 0 , 32, 19106 0xfc0001ff, 0xa0000148, 0 , 0, 19107 CP1_ }, /* POOL32F_0~*(41) */ 19108 { reserved_block , 0 , 0 , 32, 19109 0xfc0001ff, 0xa0000150, 0 , 0, 19110 CP1_ }, /* POOL32F_0~*(42) */ 19111 { reserved_block , 0 , 0 , 32, 19112 0xfc0001ff, 0xa0000158, 0 , 0, 19113 CP1_ }, /* POOL32F_0~*(43) */ 19114 { reserved_block , 0 , 0 , 32, 19115 0xfc0001ff, 0xa0000160, 0 , 0, 19116 CP1_ }, /* POOL32F_0~*(44) */ 19117 { reserved_block , 0 , 0 , 32, 19118 0xfc0001ff, 0xa0000168, 0 , 0, 19119 CP1_ }, /* POOL32F_0~*(45) */ 19120 { pool , SUB_fmt1 , 2 , 32, 19121 0xfc0001ff, 0xa0000170, 0 , 0, 19122 CP1_ }, /* SUB.fmt1 */ 19123 { reserved_block , 0 , 0 , 32, 19124 0xfc0001ff, 0xa0000178, 0 , 0, 19125 CP1_ }, /* POOL32F_0~*(47) */ 19126 { reserved_block , 0 , 0 , 32, 19127 0xfc0001ff, 0xa0000180, 0 , 0, 19128 CP1_ }, /* POOL32F_0~*(48) */ 19129 { reserved_block , 0 , 0 , 32, 19130 0xfc0001ff, 0xa0000188, 0 , 0, 19131 CP1_ }, /* POOL32F_0~*(49) */ 19132 { reserved_block , 0 , 0 , 32, 19133 0xfc0001ff, 0xa0000190, 0 , 0, 19134 CP1_ }, /* POOL32F_0~*(50) */ 19135 { reserved_block , 0 , 0 , 32, 19136 0xfc0001ff, 0xa0000198, 0 , 0, 19137 CP1_ }, /* POOL32F_0~*(51) */ 19138 { reserved_block , 0 , 0 , 32, 19139 0xfc0001ff, 0xa00001a0, 0 , 0, 19140 CP1_ }, /* POOL32F_0~*(52) */ 19141 { reserved_block , 0 , 0 , 32, 19142 0xfc0001ff, 0xa00001a8, 0 , 0, 19143 CP1_ }, /* POOL32F_0~*(53) */ 19144 { pool , MUL_fmt1 , 2 , 32, 19145 0xfc0001ff, 0xa00001b0, 0 , 0, 19146 CP1_ }, /* MUL.fmt1 */ 19147 { pool , MADDF_fmt , 2 , 32, 19148 0xfc0001ff, 0xa00001b8, 0 , 0, 19149 CP1_ }, /* MADDF.fmt */ 19150 { reserved_block , 0 , 0 , 32, 19151 0xfc0001ff, 0xa00001c0, 0 , 0, 19152 CP1_ }, /* POOL32F_0~*(56) */ 19153 { reserved_block , 0 , 0 , 32, 19154 0xfc0001ff, 0xa00001c8, 0 , 0, 19155 CP1_ }, /* POOL32F_0~*(57) */ 19156 { reserved_block , 0 , 0 , 32, 19157 0xfc0001ff, 0xa00001d0, 0 , 0, 19158 CP1_ }, /* POOL32F_0~*(58) */ 19159 { reserved_block , 0 , 0 , 32, 19160 0xfc0001ff, 0xa00001d8, 0 , 0, 19161 CP1_ }, /* POOL32F_0~*(59) */ 19162 { reserved_block , 0 , 0 , 32, 19163 0xfc0001ff, 0xa00001e0, 0 , 0, 19164 CP1_ }, /* POOL32F_0~*(60) */ 19165 { reserved_block , 0 , 0 , 32, 19166 0xfc0001ff, 0xa00001e8, 0 , 0, 19167 CP1_ }, /* POOL32F_0~*(61) */ 19168 { pool , DIV_fmt1 , 2 , 32, 19169 0xfc0001ff, 0xa00001f0, 0 , 0, 19170 CP1_ }, /* DIV.fmt1 */ 19171 { pool , MSUBF_fmt , 2 , 32, 19172 0xfc0001ff, 0xa00001f8, 0 , 0, 19173 CP1_ }, /* MSUBF.fmt */ 19174 }; 19175 19176 19177 static const Pool MIN_fmt[2] = { 19178 { instruction , 0 , 0 , 32, 19179 0xfc00023f, 0xa0000003, &MIN_S , 0, 19180 CP1_ }, /* MIN.S */ 19181 { instruction , 0 , 0 , 32, 19182 0xfc00023f, 0xa0000203, &MIN_D , 0, 19183 CP1_ }, /* MIN.D */ 19184 }; 19185 19186 19187 static const Pool MAX_fmt[2] = { 19188 { instruction , 0 , 0 , 32, 19189 0xfc00023f, 0xa000000b, &MAX_S , 0, 19190 CP1_ }, /* MAX.S */ 19191 { instruction , 0 , 0 , 32, 19192 0xfc00023f, 0xa000020b, &MAX_D , 0, 19193 CP1_ }, /* MAX.D */ 19194 }; 19195 19196 19197 static const Pool MINA_fmt[2] = { 19198 { instruction , 0 , 0 , 32, 19199 0xfc00023f, 0xa0000023, &MINA_S , 0, 19200 CP1_ }, /* MINA.S */ 19201 { instruction , 0 , 0 , 32, 19202 0xfc00023f, 0xa0000223, &MINA_D , 0, 19203 CP1_ }, /* MINA.D */ 19204 }; 19205 19206 19207 static const Pool MAXA_fmt[2] = { 19208 { instruction , 0 , 0 , 32, 19209 0xfc00023f, 0xa000002b, &MAXA_S , 0, 19210 CP1_ }, /* MAXA.S */ 19211 { instruction , 0 , 0 , 32, 19212 0xfc00023f, 0xa000022b, &MAXA_D , 0, 19213 CP1_ }, /* MAXA.D */ 19214 }; 19215 19216 19217 static const Pool CVT_L_fmt[2] = { 19218 { instruction , 0 , 0 , 32, 19219 0xfc007fff, 0xa000013b, &CVT_L_S , 0, 19220 CP1_ }, /* CVT.L.S */ 19221 { instruction , 0 , 0 , 32, 19222 0xfc007fff, 0xa000413b, &CVT_L_D , 0, 19223 CP1_ }, /* CVT.L.D */ 19224 }; 19225 19226 19227 static const Pool RSQRT_fmt[2] = { 19228 { instruction , 0 , 0 , 32, 19229 0xfc007fff, 0xa000023b, &RSQRT_S , 0, 19230 CP1_ }, /* RSQRT.S */ 19231 { instruction , 0 , 0 , 32, 19232 0xfc007fff, 0xa000423b, &RSQRT_D , 0, 19233 CP1_ }, /* RSQRT.D */ 19234 }; 19235 19236 19237 static const Pool FLOOR_L_fmt[2] = { 19238 { instruction , 0 , 0 , 32, 19239 0xfc007fff, 0xa000033b, &FLOOR_L_S , 0, 19240 CP1_ }, /* FLOOR.L.S */ 19241 { instruction , 0 , 0 , 32, 19242 0xfc007fff, 0xa000433b, &FLOOR_L_D , 0, 19243 CP1_ }, /* FLOOR.L.D */ 19244 }; 19245 19246 19247 static const Pool CVT_W_fmt[2] = { 19248 { instruction , 0 , 0 , 32, 19249 0xfc007fff, 0xa000093b, &CVT_W_S , 0, 19250 CP1_ }, /* CVT.W.S */ 19251 { instruction , 0 , 0 , 32, 19252 0xfc007fff, 0xa000493b, &CVT_W_D , 0, 19253 CP1_ }, /* CVT.W.D */ 19254 }; 19255 19256 19257 static const Pool SQRT_fmt[2] = { 19258 { instruction , 0 , 0 , 32, 19259 0xfc007fff, 0xa0000a3b, &SQRT_S , 0, 19260 CP1_ }, /* SQRT.S */ 19261 { instruction , 0 , 0 , 32, 19262 0xfc007fff, 0xa0004a3b, &SQRT_D , 0, 19263 CP1_ }, /* SQRT.D */ 19264 }; 19265 19266 19267 static const Pool FLOOR_W_fmt[2] = { 19268 { instruction , 0 , 0 , 32, 19269 0xfc007fff, 0xa0000b3b, &FLOOR_W_S , 0, 19270 CP1_ }, /* FLOOR.W.S */ 19271 { instruction , 0 , 0 , 32, 19272 0xfc007fff, 0xa0004b3b, &FLOOR_W_D , 0, 19273 CP1_ }, /* FLOOR.W.D */ 19274 }; 19275 19276 19277 static const Pool RECIP_fmt[2] = { 19278 { instruction , 0 , 0 , 32, 19279 0xfc007fff, 0xa000123b, &RECIP_S , 0, 19280 CP1_ }, /* RECIP.S */ 19281 { instruction , 0 , 0 , 32, 19282 0xfc007fff, 0xa000523b, &RECIP_D , 0, 19283 CP1_ }, /* RECIP.D */ 19284 }; 19285 19286 19287 static const Pool CEIL_L_fmt[2] = { 19288 { instruction , 0 , 0 , 32, 19289 0xfc007fff, 0xa000133b, &CEIL_L_S , 0, 19290 CP1_ }, /* CEIL.L.S */ 19291 { instruction , 0 , 0 , 32, 19292 0xfc007fff, 0xa000533b, &CEIL_L_D , 0, 19293 CP1_ }, /* CEIL.L.D */ 19294 }; 19295 19296 19297 static const Pool CEIL_W_fmt[2] = { 19298 { instruction , 0 , 0 , 32, 19299 0xfc007fff, 0xa0001b3b, &CEIL_W_S , 0, 19300 CP1_ }, /* CEIL.W.S */ 19301 { instruction , 0 , 0 , 32, 19302 0xfc007fff, 0xa0005b3b, &CEIL_W_D , 0, 19303 CP1_ }, /* CEIL.W.D */ 19304 }; 19305 19306 19307 static const Pool TRUNC_L_fmt[2] = { 19308 { instruction , 0 , 0 , 32, 19309 0xfc007fff, 0xa000233b, &TRUNC_L_S , 0, 19310 CP1_ }, /* TRUNC.L.S */ 19311 { instruction , 0 , 0 , 32, 19312 0xfc007fff, 0xa000633b, &TRUNC_L_D , 0, 19313 CP1_ }, /* TRUNC.L.D */ 19314 }; 19315 19316 19317 static const Pool TRUNC_W_fmt[2] = { 19318 { instruction , 0 , 0 , 32, 19319 0xfc007fff, 0xa0002b3b, &TRUNC_W_S , 0, 19320 CP1_ }, /* TRUNC.W.S */ 19321 { instruction , 0 , 0 , 32, 19322 0xfc007fff, 0xa0006b3b, &TRUNC_W_D , 0, 19323 CP1_ }, /* TRUNC.W.D */ 19324 }; 19325 19326 19327 static const Pool ROUND_L_fmt[2] = { 19328 { instruction , 0 , 0 , 32, 19329 0xfc007fff, 0xa000333b, &ROUND_L_S , 0, 19330 CP1_ }, /* ROUND.L.S */ 19331 { instruction , 0 , 0 , 32, 19332 0xfc007fff, 0xa000733b, &ROUND_L_D , 0, 19333 CP1_ }, /* ROUND.L.D */ 19334 }; 19335 19336 19337 static const Pool ROUND_W_fmt[2] = { 19338 { instruction , 0 , 0 , 32, 19339 0xfc007fff, 0xa0003b3b, &ROUND_W_S , 0, 19340 CP1_ }, /* ROUND.W.S */ 19341 { instruction , 0 , 0 , 32, 19342 0xfc007fff, 0xa0007b3b, &ROUND_W_D , 0, 19343 CP1_ }, /* ROUND.W.D */ 19344 }; 19345 19346 19347 static const Pool POOL32Fxf_0[64] = { 19348 { reserved_block , 0 , 0 , 32, 19349 0xfc003fff, 0xa000003b, 0 , 0, 19350 CP1_ }, /* POOL32Fxf_0~*(0) */ 19351 { pool , CVT_L_fmt , 2 , 32, 19352 0xfc003fff, 0xa000013b, 0 , 0, 19353 CP1_ }, /* CVT.L.fmt */ 19354 { pool , RSQRT_fmt , 2 , 32, 19355 0xfc003fff, 0xa000023b, 0 , 0, 19356 CP1_ }, /* RSQRT.fmt */ 19357 { pool , FLOOR_L_fmt , 2 , 32, 19358 0xfc003fff, 0xa000033b, 0 , 0, 19359 CP1_ }, /* FLOOR.L.fmt */ 19360 { reserved_block , 0 , 0 , 32, 19361 0xfc003fff, 0xa000043b, 0 , 0, 19362 CP1_ }, /* POOL32Fxf_0~*(4) */ 19363 { reserved_block , 0 , 0 , 32, 19364 0xfc003fff, 0xa000053b, 0 , 0, 19365 CP1_ }, /* POOL32Fxf_0~*(5) */ 19366 { reserved_block , 0 , 0 , 32, 19367 0xfc003fff, 0xa000063b, 0 , 0, 19368 CP1_ }, /* POOL32Fxf_0~*(6) */ 19369 { reserved_block , 0 , 0 , 32, 19370 0xfc003fff, 0xa000073b, 0 , 0, 19371 CP1_ }, /* POOL32Fxf_0~*(7) */ 19372 { reserved_block , 0 , 0 , 32, 19373 0xfc003fff, 0xa000083b, 0 , 0, 19374 CP1_ }, /* POOL32Fxf_0~*(8) */ 19375 { pool , CVT_W_fmt , 2 , 32, 19376 0xfc003fff, 0xa000093b, 0 , 0, 19377 CP1_ }, /* CVT.W.fmt */ 19378 { pool , SQRT_fmt , 2 , 32, 19379 0xfc003fff, 0xa0000a3b, 0 , 0, 19380 CP1_ }, /* SQRT.fmt */ 19381 { pool , FLOOR_W_fmt , 2 , 32, 19382 0xfc003fff, 0xa0000b3b, 0 , 0, 19383 CP1_ }, /* FLOOR.W.fmt */ 19384 { reserved_block , 0 , 0 , 32, 19385 0xfc003fff, 0xa0000c3b, 0 , 0, 19386 CP1_ }, /* POOL32Fxf_0~*(12) */ 19387 { reserved_block , 0 , 0 , 32, 19388 0xfc003fff, 0xa0000d3b, 0 , 0, 19389 CP1_ }, /* POOL32Fxf_0~*(13) */ 19390 { reserved_block , 0 , 0 , 32, 19391 0xfc003fff, 0xa0000e3b, 0 , 0, 19392 CP1_ }, /* POOL32Fxf_0~*(14) */ 19393 { reserved_block , 0 , 0 , 32, 19394 0xfc003fff, 0xa0000f3b, 0 , 0, 19395 CP1_ }, /* POOL32Fxf_0~*(15) */ 19396 { instruction , 0 , 0 , 32, 19397 0xfc003fff, 0xa000103b, &CFC1 , 0, 19398 CP1_ }, /* CFC1 */ 19399 { reserved_block , 0 , 0 , 32, 19400 0xfc003fff, 0xa000113b, 0 , 0, 19401 CP1_ }, /* POOL32Fxf_0~*(17) */ 19402 { pool , RECIP_fmt , 2 , 32, 19403 0xfc003fff, 0xa000123b, 0 , 0, 19404 CP1_ }, /* RECIP.fmt */ 19405 { pool , CEIL_L_fmt , 2 , 32, 19406 0xfc003fff, 0xa000133b, 0 , 0, 19407 CP1_ }, /* CEIL.L.fmt */ 19408 { reserved_block , 0 , 0 , 32, 19409 0xfc003fff, 0xa000143b, 0 , 0, 19410 CP1_ }, /* POOL32Fxf_0~*(20) */ 19411 { reserved_block , 0 , 0 , 32, 19412 0xfc003fff, 0xa000153b, 0 , 0, 19413 CP1_ }, /* POOL32Fxf_0~*(21) */ 19414 { reserved_block , 0 , 0 , 32, 19415 0xfc003fff, 0xa000163b, 0 , 0, 19416 CP1_ }, /* POOL32Fxf_0~*(22) */ 19417 { reserved_block , 0 , 0 , 32, 19418 0xfc003fff, 0xa000173b, 0 , 0, 19419 CP1_ }, /* POOL32Fxf_0~*(23) */ 19420 { instruction , 0 , 0 , 32, 19421 0xfc003fff, 0xa000183b, &CTC1 , 0, 19422 CP1_ }, /* CTC1 */ 19423 { reserved_block , 0 , 0 , 32, 19424 0xfc003fff, 0xa000193b, 0 , 0, 19425 CP1_ }, /* POOL32Fxf_0~*(25) */ 19426 { reserved_block , 0 , 0 , 32, 19427 0xfc003fff, 0xa0001a3b, 0 , 0, 19428 CP1_ }, /* POOL32Fxf_0~*(26) */ 19429 { pool , CEIL_W_fmt , 2 , 32, 19430 0xfc003fff, 0xa0001b3b, 0 , 0, 19431 CP1_ }, /* CEIL.W.fmt */ 19432 { reserved_block , 0 , 0 , 32, 19433 0xfc003fff, 0xa0001c3b, 0 , 0, 19434 CP1_ }, /* POOL32Fxf_0~*(28) */ 19435 { reserved_block , 0 , 0 , 32, 19436 0xfc003fff, 0xa0001d3b, 0 , 0, 19437 CP1_ }, /* POOL32Fxf_0~*(29) */ 19438 { reserved_block , 0 , 0 , 32, 19439 0xfc003fff, 0xa0001e3b, 0 , 0, 19440 CP1_ }, /* POOL32Fxf_0~*(30) */ 19441 { reserved_block , 0 , 0 , 32, 19442 0xfc003fff, 0xa0001f3b, 0 , 0, 19443 CP1_ }, /* POOL32Fxf_0~*(31) */ 19444 { instruction , 0 , 0 , 32, 19445 0xfc003fff, 0xa000203b, &MFC1 , 0, 19446 CP1_ }, /* MFC1 */ 19447 { instruction , 0 , 0 , 32, 19448 0xfc003fff, 0xa000213b, &CVT_S_PL , 0, 19449 CP1_ }, /* CVT.S.PL */ 19450 { reserved_block , 0 , 0 , 32, 19451 0xfc003fff, 0xa000223b, 0 , 0, 19452 CP1_ }, /* POOL32Fxf_0~*(34) */ 19453 { pool , TRUNC_L_fmt , 2 , 32, 19454 0xfc003fff, 0xa000233b, 0 , 0, 19455 CP1_ }, /* TRUNC.L.fmt */ 19456 { instruction , 0 , 0 , 32, 19457 0xfc003fff, 0xa000243b, &DMFC1 , 0, 19458 CP1_ | MIPS64_ }, /* DMFC1 */ 19459 { reserved_block , 0 , 0 , 32, 19460 0xfc003fff, 0xa000253b, 0 , 0, 19461 CP1_ }, /* POOL32Fxf_0~*(37) */ 19462 { reserved_block , 0 , 0 , 32, 19463 0xfc003fff, 0xa000263b, 0 , 0, 19464 CP1_ }, /* POOL32Fxf_0~*(38) */ 19465 { reserved_block , 0 , 0 , 32, 19466 0xfc003fff, 0xa000273b, 0 , 0, 19467 CP1_ }, /* POOL32Fxf_0~*(39) */ 19468 { instruction , 0 , 0 , 32, 19469 0xfc003fff, 0xa000283b, &MTC1 , 0, 19470 CP1_ }, /* MTC1 */ 19471 { instruction , 0 , 0 , 32, 19472 0xfc003fff, 0xa000293b, &CVT_S_PU , 0, 19473 CP1_ }, /* CVT.S.PU */ 19474 { reserved_block , 0 , 0 , 32, 19475 0xfc003fff, 0xa0002a3b, 0 , 0, 19476 CP1_ }, /* POOL32Fxf_0~*(42) */ 19477 { pool , TRUNC_W_fmt , 2 , 32, 19478 0xfc003fff, 0xa0002b3b, 0 , 0, 19479 CP1_ }, /* TRUNC.W.fmt */ 19480 { instruction , 0 , 0 , 32, 19481 0xfc003fff, 0xa0002c3b, &DMTC1 , 0, 19482 CP1_ | MIPS64_ }, /* DMTC1 */ 19483 { reserved_block , 0 , 0 , 32, 19484 0xfc003fff, 0xa0002d3b, 0 , 0, 19485 CP1_ }, /* POOL32Fxf_0~*(45) */ 19486 { reserved_block , 0 , 0 , 32, 19487 0xfc003fff, 0xa0002e3b, 0 , 0, 19488 CP1_ }, /* POOL32Fxf_0~*(46) */ 19489 { reserved_block , 0 , 0 , 32, 19490 0xfc003fff, 0xa0002f3b, 0 , 0, 19491 CP1_ }, /* POOL32Fxf_0~*(47) */ 19492 { instruction , 0 , 0 , 32, 19493 0xfc003fff, 0xa000303b, &MFHC1 , 0, 19494 CP1_ }, /* MFHC1 */ 19495 { reserved_block , 0 , 0 , 32, 19496 0xfc003fff, 0xa000313b, 0 , 0, 19497 CP1_ }, /* POOL32Fxf_0~*(49) */ 19498 { reserved_block , 0 , 0 , 32, 19499 0xfc003fff, 0xa000323b, 0 , 0, 19500 CP1_ }, /* POOL32Fxf_0~*(50) */ 19501 { pool , ROUND_L_fmt , 2 , 32, 19502 0xfc003fff, 0xa000333b, 0 , 0, 19503 CP1_ }, /* ROUND.L.fmt */ 19504 { reserved_block , 0 , 0 , 32, 19505 0xfc003fff, 0xa000343b, 0 , 0, 19506 CP1_ }, /* POOL32Fxf_0~*(52) */ 19507 { reserved_block , 0 , 0 , 32, 19508 0xfc003fff, 0xa000353b, 0 , 0, 19509 CP1_ }, /* POOL32Fxf_0~*(53) */ 19510 { reserved_block , 0 , 0 , 32, 19511 0xfc003fff, 0xa000363b, 0 , 0, 19512 CP1_ }, /* POOL32Fxf_0~*(54) */ 19513 { reserved_block , 0 , 0 , 32, 19514 0xfc003fff, 0xa000373b, 0 , 0, 19515 CP1_ }, /* POOL32Fxf_0~*(55) */ 19516 { instruction , 0 , 0 , 32, 19517 0xfc003fff, 0xa000383b, &MTHC1 , 0, 19518 CP1_ }, /* MTHC1 */ 19519 { reserved_block , 0 , 0 , 32, 19520 0xfc003fff, 0xa000393b, 0 , 0, 19521 CP1_ }, /* POOL32Fxf_0~*(57) */ 19522 { reserved_block , 0 , 0 , 32, 19523 0xfc003fff, 0xa0003a3b, 0 , 0, 19524 CP1_ }, /* POOL32Fxf_0~*(58) */ 19525 { pool , ROUND_W_fmt , 2 , 32, 19526 0xfc003fff, 0xa0003b3b, 0 , 0, 19527 CP1_ }, /* ROUND.W.fmt */ 19528 { reserved_block , 0 , 0 , 32, 19529 0xfc003fff, 0xa0003c3b, 0 , 0, 19530 CP1_ }, /* POOL32Fxf_0~*(60) */ 19531 { reserved_block , 0 , 0 , 32, 19532 0xfc003fff, 0xa0003d3b, 0 , 0, 19533 CP1_ }, /* POOL32Fxf_0~*(61) */ 19534 { reserved_block , 0 , 0 , 32, 19535 0xfc003fff, 0xa0003e3b, 0 , 0, 19536 CP1_ }, /* POOL32Fxf_0~*(62) */ 19537 { reserved_block , 0 , 0 , 32, 19538 0xfc003fff, 0xa0003f3b, 0 , 0, 19539 CP1_ }, /* POOL32Fxf_0~*(63) */ 19540 }; 19541 19542 19543 static const Pool MOV_fmt[4] = { 19544 { instruction , 0 , 0 , 32, 19545 0xfc007fff, 0xa000007b, &MOV_S , 0, 19546 CP1_ }, /* MOV.S */ 19547 { instruction , 0 , 0 , 32, 19548 0xfc007fff, 0xa000207b, &MOV_D , 0, 19549 CP1_ }, /* MOV.D */ 19550 { reserved_block , 0 , 0 , 32, 19551 0xfc007fff, 0xa000407b, 0 , 0, 19552 CP1_ }, /* MOV.fmt~*(2) */ 19553 { reserved_block , 0 , 0 , 32, 19554 0xfc007fff, 0xa000607b, 0 , 0, 19555 CP1_ }, /* MOV.fmt~*(3) */ 19556 }; 19557 19558 19559 static const Pool ABS_fmt[4] = { 19560 { instruction , 0 , 0 , 32, 19561 0xfc007fff, 0xa000037b, &ABS_S , 0, 19562 CP1_ }, /* ABS.S */ 19563 { instruction , 0 , 0 , 32, 19564 0xfc007fff, 0xa000237b, &ABS_D , 0, 19565 CP1_ }, /* ABS.D */ 19566 { reserved_block , 0 , 0 , 32, 19567 0xfc007fff, 0xa000437b, 0 , 0, 19568 CP1_ }, /* ABS.fmt~*(2) */ 19569 { reserved_block , 0 , 0 , 32, 19570 0xfc007fff, 0xa000637b, 0 , 0, 19571 CP1_ }, /* ABS.fmt~*(3) */ 19572 }; 19573 19574 19575 static const Pool NEG_fmt[4] = { 19576 { instruction , 0 , 0 , 32, 19577 0xfc007fff, 0xa0000b7b, &NEG_S , 0, 19578 CP1_ }, /* NEG.S */ 19579 { instruction , 0 , 0 , 32, 19580 0xfc007fff, 0xa0002b7b, &NEG_D , 0, 19581 CP1_ }, /* NEG.D */ 19582 { reserved_block , 0 , 0 , 32, 19583 0xfc007fff, 0xa0004b7b, 0 , 0, 19584 CP1_ }, /* NEG.fmt~*(2) */ 19585 { reserved_block , 0 , 0 , 32, 19586 0xfc007fff, 0xa0006b7b, 0 , 0, 19587 CP1_ }, /* NEG.fmt~*(3) */ 19588 }; 19589 19590 19591 static const Pool CVT_D_fmt[4] = { 19592 { instruction , 0 , 0 , 32, 19593 0xfc007fff, 0xa000137b, &CVT_D_S , 0, 19594 CP1_ }, /* CVT.D.S */ 19595 { instruction , 0 , 0 , 32, 19596 0xfc007fff, 0xa000337b, &CVT_D_W , 0, 19597 CP1_ }, /* CVT.D.W */ 19598 { instruction , 0 , 0 , 32, 19599 0xfc007fff, 0xa000537b, &CVT_D_L , 0, 19600 CP1_ }, /* CVT.D.L */ 19601 { reserved_block , 0 , 0 , 32, 19602 0xfc007fff, 0xa000737b, 0 , 0, 19603 CP1_ }, /* CVT.D.fmt~*(3) */ 19604 }; 19605 19606 19607 static const Pool CVT_S_fmt[4] = { 19608 { instruction , 0 , 0 , 32, 19609 0xfc007fff, 0xa0001b7b, &CVT_S_D , 0, 19610 CP1_ }, /* CVT.S.D */ 19611 { instruction , 0 , 0 , 32, 19612 0xfc007fff, 0xa0003b7b, &CVT_S_W , 0, 19613 CP1_ }, /* CVT.S.W */ 19614 { instruction , 0 , 0 , 32, 19615 0xfc007fff, 0xa0005b7b, &CVT_S_L , 0, 19616 CP1_ }, /* CVT.S.L */ 19617 { reserved_block , 0 , 0 , 32, 19618 0xfc007fff, 0xa0007b7b, 0 , 0, 19619 CP1_ }, /* CVT.S.fmt~*(3) */ 19620 }; 19621 19622 19623 static const Pool POOL32Fxf_1[32] = { 19624 { pool , MOV_fmt , 4 , 32, 19625 0xfc001fff, 0xa000007b, 0 , 0, 19626 CP1_ }, /* MOV.fmt */ 19627 { reserved_block , 0 , 0 , 32, 19628 0xfc001fff, 0xa000017b, 0 , 0, 19629 CP1_ }, /* POOL32Fxf_1~*(1) */ 19630 { reserved_block , 0 , 0 , 32, 19631 0xfc001fff, 0xa000027b, 0 , 0, 19632 CP1_ }, /* POOL32Fxf_1~*(2) */ 19633 { pool , ABS_fmt , 4 , 32, 19634 0xfc001fff, 0xa000037b, 0 , 0, 19635 CP1_ }, /* ABS.fmt */ 19636 { reserved_block , 0 , 0 , 32, 19637 0xfc001fff, 0xa000047b, 0 , 0, 19638 CP1_ }, /* POOL32Fxf_1~*(4) */ 19639 { reserved_block , 0 , 0 , 32, 19640 0xfc001fff, 0xa000057b, 0 , 0, 19641 CP1_ }, /* POOL32Fxf_1~*(5) */ 19642 { reserved_block , 0 , 0 , 32, 19643 0xfc001fff, 0xa000067b, 0 , 0, 19644 CP1_ }, /* POOL32Fxf_1~*(6) */ 19645 { reserved_block , 0 , 0 , 32, 19646 0xfc001fff, 0xa000077b, 0 , 0, 19647 CP1_ }, /* POOL32Fxf_1~*(7) */ 19648 { reserved_block , 0 , 0 , 32, 19649 0xfc001fff, 0xa000087b, 0 , 0, 19650 CP1_ }, /* POOL32Fxf_1~*(8) */ 19651 { reserved_block , 0 , 0 , 32, 19652 0xfc001fff, 0xa000097b, 0 , 0, 19653 CP1_ }, /* POOL32Fxf_1~*(9) */ 19654 { reserved_block , 0 , 0 , 32, 19655 0xfc001fff, 0xa0000a7b, 0 , 0, 19656 CP1_ }, /* POOL32Fxf_1~*(10) */ 19657 { pool , NEG_fmt , 4 , 32, 19658 0xfc001fff, 0xa0000b7b, 0 , 0, 19659 CP1_ }, /* NEG.fmt */ 19660 { reserved_block , 0 , 0 , 32, 19661 0xfc001fff, 0xa0000c7b, 0 , 0, 19662 CP1_ }, /* POOL32Fxf_1~*(12) */ 19663 { reserved_block , 0 , 0 , 32, 19664 0xfc001fff, 0xa0000d7b, 0 , 0, 19665 CP1_ }, /* POOL32Fxf_1~*(13) */ 19666 { reserved_block , 0 , 0 , 32, 19667 0xfc001fff, 0xa0000e7b, 0 , 0, 19668 CP1_ }, /* POOL32Fxf_1~*(14) */ 19669 { reserved_block , 0 , 0 , 32, 19670 0xfc001fff, 0xa0000f7b, 0 , 0, 19671 CP1_ }, /* POOL32Fxf_1~*(15) */ 19672 { reserved_block , 0 , 0 , 32, 19673 0xfc001fff, 0xa000107b, 0 , 0, 19674 CP1_ }, /* POOL32Fxf_1~*(16) */ 19675 { reserved_block , 0 , 0 , 32, 19676 0xfc001fff, 0xa000117b, 0 , 0, 19677 CP1_ }, /* POOL32Fxf_1~*(17) */ 19678 { reserved_block , 0 , 0 , 32, 19679 0xfc001fff, 0xa000127b, 0 , 0, 19680 CP1_ }, /* POOL32Fxf_1~*(18) */ 19681 { pool , CVT_D_fmt , 4 , 32, 19682 0xfc001fff, 0xa000137b, 0 , 0, 19683 CP1_ }, /* CVT.D.fmt */ 19684 { reserved_block , 0 , 0 , 32, 19685 0xfc001fff, 0xa000147b, 0 , 0, 19686 CP1_ }, /* POOL32Fxf_1~*(20) */ 19687 { reserved_block , 0 , 0 , 32, 19688 0xfc001fff, 0xa000157b, 0 , 0, 19689 CP1_ }, /* POOL32Fxf_1~*(21) */ 19690 { reserved_block , 0 , 0 , 32, 19691 0xfc001fff, 0xa000167b, 0 , 0, 19692 CP1_ }, /* POOL32Fxf_1~*(22) */ 19693 { reserved_block , 0 , 0 , 32, 19694 0xfc001fff, 0xa000177b, 0 , 0, 19695 CP1_ }, /* POOL32Fxf_1~*(23) */ 19696 { reserved_block , 0 , 0 , 32, 19697 0xfc001fff, 0xa000187b, 0 , 0, 19698 CP1_ }, /* POOL32Fxf_1~*(24) */ 19699 { reserved_block , 0 , 0 , 32, 19700 0xfc001fff, 0xa000197b, 0 , 0, 19701 CP1_ }, /* POOL32Fxf_1~*(25) */ 19702 { reserved_block , 0 , 0 , 32, 19703 0xfc001fff, 0xa0001a7b, 0 , 0, 19704 CP1_ }, /* POOL32Fxf_1~*(26) */ 19705 { pool , CVT_S_fmt , 4 , 32, 19706 0xfc001fff, 0xa0001b7b, 0 , 0, 19707 CP1_ }, /* CVT.S.fmt */ 19708 { reserved_block , 0 , 0 , 32, 19709 0xfc001fff, 0xa0001c7b, 0 , 0, 19710 CP1_ }, /* POOL32Fxf_1~*(28) */ 19711 { reserved_block , 0 , 0 , 32, 19712 0xfc001fff, 0xa0001d7b, 0 , 0, 19713 CP1_ }, /* POOL32Fxf_1~*(29) */ 19714 { reserved_block , 0 , 0 , 32, 19715 0xfc001fff, 0xa0001e7b, 0 , 0, 19716 CP1_ }, /* POOL32Fxf_1~*(30) */ 19717 { reserved_block , 0 , 0 , 32, 19718 0xfc001fff, 0xa0001f7b, 0 , 0, 19719 CP1_ }, /* POOL32Fxf_1~*(31) */ 19720 }; 19721 19722 19723 static const Pool POOL32Fxf[4] = { 19724 { pool , POOL32Fxf_0 , 64 , 32, 19725 0xfc0000ff, 0xa000003b, 0 , 0, 19726 CP1_ }, /* POOL32Fxf_0 */ 19727 { pool , POOL32Fxf_1 , 32 , 32, 19728 0xfc0000ff, 0xa000007b, 0 , 0, 19729 CP1_ }, /* POOL32Fxf_1 */ 19730 { reserved_block , 0 , 0 , 32, 19731 0xfc0000ff, 0xa00000bb, 0 , 0, 19732 CP1_ }, /* POOL32Fxf~*(2) */ 19733 { reserved_block , 0 , 0 , 32, 19734 0xfc0000ff, 0xa00000fb, 0 , 0, 19735 CP1_ }, /* POOL32Fxf~*(3) */ 19736 }; 19737 19738 19739 static const Pool POOL32F_3[8] = { 19740 { pool , MIN_fmt , 2 , 32, 19741 0xfc00003f, 0xa0000003, 0 , 0, 19742 CP1_ }, /* MIN.fmt */ 19743 { pool , MAX_fmt , 2 , 32, 19744 0xfc00003f, 0xa000000b, 0 , 0, 19745 CP1_ }, /* MAX.fmt */ 19746 { reserved_block , 0 , 0 , 32, 19747 0xfc00003f, 0xa0000013, 0 , 0, 19748 CP1_ }, /* POOL32F_3~*(2) */ 19749 { reserved_block , 0 , 0 , 32, 19750 0xfc00003f, 0xa000001b, 0 , 0, 19751 CP1_ }, /* POOL32F_3~*(3) */ 19752 { pool , MINA_fmt , 2 , 32, 19753 0xfc00003f, 0xa0000023, 0 , 0, 19754 CP1_ }, /* MINA.fmt */ 19755 { pool , MAXA_fmt , 2 , 32, 19756 0xfc00003f, 0xa000002b, 0 , 0, 19757 CP1_ }, /* MAXA.fmt */ 19758 { reserved_block , 0 , 0 , 32, 19759 0xfc00003f, 0xa0000033, 0 , 0, 19760 CP1_ }, /* POOL32F_3~*(6) */ 19761 { pool , POOL32Fxf , 4 , 32, 19762 0xfc00003f, 0xa000003b, 0 , 0, 19763 CP1_ }, /* POOL32Fxf */ 19764 }; 19765 19766 19767 static const Pool CMP_condn_S[32] = { 19768 { instruction , 0 , 0 , 32, 19769 0xfc0007ff, 0xa0000005, &CMP_AF_S , 0, 19770 CP1_ }, /* CMP.AF.S */ 19771 { instruction , 0 , 0 , 32, 19772 0xfc0007ff, 0xa0000045, &CMP_UN_S , 0, 19773 CP1_ }, /* CMP.UN.S */ 19774 { instruction , 0 , 0 , 32, 19775 0xfc0007ff, 0xa0000085, &CMP_EQ_S , 0, 19776 CP1_ }, /* CMP.EQ.S */ 19777 { instruction , 0 , 0 , 32, 19778 0xfc0007ff, 0xa00000c5, &CMP_UEQ_S , 0, 19779 CP1_ }, /* CMP.UEQ.S */ 19780 { instruction , 0 , 0 , 32, 19781 0xfc0007ff, 0xa0000105, &CMP_LT_S , 0, 19782 CP1_ }, /* CMP.LT.S */ 19783 { instruction , 0 , 0 , 32, 19784 0xfc0007ff, 0xa0000145, &CMP_ULT_S , 0, 19785 CP1_ }, /* CMP.ULT.S */ 19786 { instruction , 0 , 0 , 32, 19787 0xfc0007ff, 0xa0000185, &CMP_LE_S , 0, 19788 CP1_ }, /* CMP.LE.S */ 19789 { instruction , 0 , 0 , 32, 19790 0xfc0007ff, 0xa00001c5, &CMP_ULE_S , 0, 19791 CP1_ }, /* CMP.ULE.S */ 19792 { instruction , 0 , 0 , 32, 19793 0xfc0007ff, 0xa0000205, &CMP_SAF_S , 0, 19794 CP1_ }, /* CMP.SAF.S */ 19795 { instruction , 0 , 0 , 32, 19796 0xfc0007ff, 0xa0000245, &CMP_SUN_S , 0, 19797 CP1_ }, /* CMP.SUN.S */ 19798 { instruction , 0 , 0 , 32, 19799 0xfc0007ff, 0xa0000285, &CMP_SEQ_S , 0, 19800 CP1_ }, /* CMP.SEQ.S */ 19801 { instruction , 0 , 0 , 32, 19802 0xfc0007ff, 0xa00002c5, &CMP_SUEQ_S , 0, 19803 CP1_ }, /* CMP.SUEQ.S */ 19804 { instruction , 0 , 0 , 32, 19805 0xfc0007ff, 0xa0000305, &CMP_SLT_S , 0, 19806 CP1_ }, /* CMP.SLT.S */ 19807 { instruction , 0 , 0 , 32, 19808 0xfc0007ff, 0xa0000345, &CMP_SULT_S , 0, 19809 CP1_ }, /* CMP.SULT.S */ 19810 { instruction , 0 , 0 , 32, 19811 0xfc0007ff, 0xa0000385, &CMP_SLE_S , 0, 19812 CP1_ }, /* CMP.SLE.S */ 19813 { instruction , 0 , 0 , 32, 19814 0xfc0007ff, 0xa00003c5, &CMP_SULE_S , 0, 19815 CP1_ }, /* CMP.SULE.S */ 19816 { reserved_block , 0 , 0 , 32, 19817 0xfc0007ff, 0xa0000405, 0 , 0, 19818 CP1_ }, /* CMP.condn.S~*(16) */ 19819 { instruction , 0 , 0 , 32, 19820 0xfc0007ff, 0xa0000445, &CMP_OR_S , 0, 19821 CP1_ }, /* CMP.OR.S */ 19822 { instruction , 0 , 0 , 32, 19823 0xfc0007ff, 0xa0000485, &CMP_UNE_S , 0, 19824 CP1_ }, /* CMP.UNE.S */ 19825 { instruction , 0 , 0 , 32, 19826 0xfc0007ff, 0xa00004c5, &CMP_NE_S , 0, 19827 CP1_ }, /* CMP.NE.S */ 19828 { reserved_block , 0 , 0 , 32, 19829 0xfc0007ff, 0xa0000505, 0 , 0, 19830 CP1_ }, /* CMP.condn.S~*(20) */ 19831 { reserved_block , 0 , 0 , 32, 19832 0xfc0007ff, 0xa0000545, 0 , 0, 19833 CP1_ }, /* CMP.condn.S~*(21) */ 19834 { reserved_block , 0 , 0 , 32, 19835 0xfc0007ff, 0xa0000585, 0 , 0, 19836 CP1_ }, /* CMP.condn.S~*(22) */ 19837 { reserved_block , 0 , 0 , 32, 19838 0xfc0007ff, 0xa00005c5, 0 , 0, 19839 CP1_ }, /* CMP.condn.S~*(23) */ 19840 { reserved_block , 0 , 0 , 32, 19841 0xfc0007ff, 0xa0000605, 0 , 0, 19842 CP1_ }, /* CMP.condn.S~*(24) */ 19843 { instruction , 0 , 0 , 32, 19844 0xfc0007ff, 0xa0000645, &CMP_SOR_S , 0, 19845 CP1_ }, /* CMP.SOR.S */ 19846 { instruction , 0 , 0 , 32, 19847 0xfc0007ff, 0xa0000685, &CMP_SUNE_S , 0, 19848 CP1_ }, /* CMP.SUNE.S */ 19849 { instruction , 0 , 0 , 32, 19850 0xfc0007ff, 0xa00006c5, &CMP_SNE_S , 0, 19851 CP1_ }, /* CMP.SNE.S */ 19852 { reserved_block , 0 , 0 , 32, 19853 0xfc0007ff, 0xa0000705, 0 , 0, 19854 CP1_ }, /* CMP.condn.S~*(28) */ 19855 { reserved_block , 0 , 0 , 32, 19856 0xfc0007ff, 0xa0000745, 0 , 0, 19857 CP1_ }, /* CMP.condn.S~*(29) */ 19858 { reserved_block , 0 , 0 , 32, 19859 0xfc0007ff, 0xa0000785, 0 , 0, 19860 CP1_ }, /* CMP.condn.S~*(30) */ 19861 { reserved_block , 0 , 0 , 32, 19862 0xfc0007ff, 0xa00007c5, 0 , 0, 19863 CP1_ }, /* CMP.condn.S~*(31) */ 19864 }; 19865 19866 19867 static const Pool CMP_condn_D[32] = { 19868 { instruction , 0 , 0 , 32, 19869 0xfc0007ff, 0xa0000015, &CMP_AF_D , 0, 19870 CP1_ }, /* CMP.AF.D */ 19871 { instruction , 0 , 0 , 32, 19872 0xfc0007ff, 0xa0000055, &CMP_UN_D , 0, 19873 CP1_ }, /* CMP.UN.D */ 19874 { instruction , 0 , 0 , 32, 19875 0xfc0007ff, 0xa0000095, &CMP_EQ_D , 0, 19876 CP1_ }, /* CMP.EQ.D */ 19877 { instruction , 0 , 0 , 32, 19878 0xfc0007ff, 0xa00000d5, &CMP_UEQ_D , 0, 19879 CP1_ }, /* CMP.UEQ.D */ 19880 { instruction , 0 , 0 , 32, 19881 0xfc0007ff, 0xa0000115, &CMP_LT_D , 0, 19882 CP1_ }, /* CMP.LT.D */ 19883 { instruction , 0 , 0 , 32, 19884 0xfc0007ff, 0xa0000155, &CMP_ULT_D , 0, 19885 CP1_ }, /* CMP.ULT.D */ 19886 { instruction , 0 , 0 , 32, 19887 0xfc0007ff, 0xa0000195, &CMP_LE_D , 0, 19888 CP1_ }, /* CMP.LE.D */ 19889 { instruction , 0 , 0 , 32, 19890 0xfc0007ff, 0xa00001d5, &CMP_ULE_D , 0, 19891 CP1_ }, /* CMP.ULE.D */ 19892 { instruction , 0 , 0 , 32, 19893 0xfc0007ff, 0xa0000215, &CMP_SAF_D , 0, 19894 CP1_ }, /* CMP.SAF.D */ 19895 { instruction , 0 , 0 , 32, 19896 0xfc0007ff, 0xa0000255, &CMP_SUN_D , 0, 19897 CP1_ }, /* CMP.SUN.D */ 19898 { instruction , 0 , 0 , 32, 19899 0xfc0007ff, 0xa0000295, &CMP_SEQ_D , 0, 19900 CP1_ }, /* CMP.SEQ.D */ 19901 { instruction , 0 , 0 , 32, 19902 0xfc0007ff, 0xa00002d5, &CMP_SUEQ_D , 0, 19903 CP1_ }, /* CMP.SUEQ.D */ 19904 { instruction , 0 , 0 , 32, 19905 0xfc0007ff, 0xa0000315, &CMP_SLT_D , 0, 19906 CP1_ }, /* CMP.SLT.D */ 19907 { instruction , 0 , 0 , 32, 19908 0xfc0007ff, 0xa0000355, &CMP_SULT_D , 0, 19909 CP1_ }, /* CMP.SULT.D */ 19910 { instruction , 0 , 0 , 32, 19911 0xfc0007ff, 0xa0000395, &CMP_SLE_D , 0, 19912 CP1_ }, /* CMP.SLE.D */ 19913 { instruction , 0 , 0 , 32, 19914 0xfc0007ff, 0xa00003d5, &CMP_SULE_D , 0, 19915 CP1_ }, /* CMP.SULE.D */ 19916 { reserved_block , 0 , 0 , 32, 19917 0xfc0007ff, 0xa0000415, 0 , 0, 19918 CP1_ }, /* CMP.condn.D~*(16) */ 19919 { instruction , 0 , 0 , 32, 19920 0xfc0007ff, 0xa0000455, &CMP_OR_D , 0, 19921 CP1_ }, /* CMP.OR.D */ 19922 { instruction , 0 , 0 , 32, 19923 0xfc0007ff, 0xa0000495, &CMP_UNE_D , 0, 19924 CP1_ }, /* CMP.UNE.D */ 19925 { instruction , 0 , 0 , 32, 19926 0xfc0007ff, 0xa00004d5, &CMP_NE_D , 0, 19927 CP1_ }, /* CMP.NE.D */ 19928 { reserved_block , 0 , 0 , 32, 19929 0xfc0007ff, 0xa0000515, 0 , 0, 19930 CP1_ }, /* CMP.condn.D~*(20) */ 19931 { reserved_block , 0 , 0 , 32, 19932 0xfc0007ff, 0xa0000555, 0 , 0, 19933 CP1_ }, /* CMP.condn.D~*(21) */ 19934 { reserved_block , 0 , 0 , 32, 19935 0xfc0007ff, 0xa0000595, 0 , 0, 19936 CP1_ }, /* CMP.condn.D~*(22) */ 19937 { reserved_block , 0 , 0 , 32, 19938 0xfc0007ff, 0xa00005d5, 0 , 0, 19939 CP1_ }, /* CMP.condn.D~*(23) */ 19940 { reserved_block , 0 , 0 , 32, 19941 0xfc0007ff, 0xa0000615, 0 , 0, 19942 CP1_ }, /* CMP.condn.D~*(24) */ 19943 { instruction , 0 , 0 , 32, 19944 0xfc0007ff, 0xa0000655, &CMP_SOR_D , 0, 19945 CP1_ }, /* CMP.SOR.D */ 19946 { instruction , 0 , 0 , 32, 19947 0xfc0007ff, 0xa0000695, &CMP_SUNE_D , 0, 19948 CP1_ }, /* CMP.SUNE.D */ 19949 { instruction , 0 , 0 , 32, 19950 0xfc0007ff, 0xa00006d5, &CMP_SNE_D , 0, 19951 CP1_ }, /* CMP.SNE.D */ 19952 { reserved_block , 0 , 0 , 32, 19953 0xfc0007ff, 0xa0000715, 0 , 0, 19954 CP1_ }, /* CMP.condn.D~*(28) */ 19955 { reserved_block , 0 , 0 , 32, 19956 0xfc0007ff, 0xa0000755, 0 , 0, 19957 CP1_ }, /* CMP.condn.D~*(29) */ 19958 { reserved_block , 0 , 0 , 32, 19959 0xfc0007ff, 0xa0000795, 0 , 0, 19960 CP1_ }, /* CMP.condn.D~*(30) */ 19961 { reserved_block , 0 , 0 , 32, 19962 0xfc0007ff, 0xa00007d5, 0 , 0, 19963 CP1_ }, /* CMP.condn.D~*(31) */ 19964 }; 19965 19966 19967 static const Pool POOL32F_5[8] = { 19968 { pool , CMP_condn_S , 32 , 32, 19969 0xfc00003f, 0xa0000005, 0 , 0, 19970 CP1_ }, /* CMP.condn.S */ 19971 { reserved_block , 0 , 0 , 32, 19972 0xfc00003f, 0xa000000d, 0 , 0, 19973 CP1_ }, /* POOL32F_5~*(1) */ 19974 { pool , CMP_condn_D , 32 , 32, 19975 0xfc00003f, 0xa0000015, 0 , 0, 19976 CP1_ }, /* CMP.condn.D */ 19977 { reserved_block , 0 , 0 , 32, 19978 0xfc00003f, 0xa000001d, 0 , 0, 19979 CP1_ }, /* POOL32F_5~*(3) */ 19980 { reserved_block , 0 , 0 , 32, 19981 0xfc00003f, 0xa0000025, 0 , 0, 19982 CP1_ }, /* POOL32F_5~*(4) */ 19983 { reserved_block , 0 , 0 , 32, 19984 0xfc00003f, 0xa000002d, 0 , 0, 19985 CP1_ }, /* POOL32F_5~*(5) */ 19986 { reserved_block , 0 , 0 , 32, 19987 0xfc00003f, 0xa0000035, 0 , 0, 19988 CP1_ }, /* POOL32F_5~*(6) */ 19989 { reserved_block , 0 , 0 , 32, 19990 0xfc00003f, 0xa000003d, 0 , 0, 19991 CP1_ }, /* POOL32F_5~*(7) */ 19992 }; 19993 19994 19995 static const Pool POOL32F[8] = { 19996 { pool , POOL32F_0 , 64 , 32, 19997 0xfc000007, 0xa0000000, 0 , 0, 19998 CP1_ }, /* POOL32F_0 */ 19999 { reserved_block , 0 , 0 , 32, 20000 0xfc000007, 0xa0000001, 0 , 0, 20001 CP1_ }, /* POOL32F~*(1) */ 20002 { reserved_block , 0 , 0 , 32, 20003 0xfc000007, 0xa0000002, 0 , 0, 20004 CP1_ }, /* POOL32F~*(2) */ 20005 { pool , POOL32F_3 , 8 , 32, 20006 0xfc000007, 0xa0000003, 0 , 0, 20007 CP1_ }, /* POOL32F_3 */ 20008 { reserved_block , 0 , 0 , 32, 20009 0xfc000007, 0xa0000004, 0 , 0, 20010 CP1_ }, /* POOL32F~*(4) */ 20011 { pool , POOL32F_5 , 8 , 32, 20012 0xfc000007, 0xa0000005, 0 , 0, 20013 CP1_ }, /* POOL32F_5 */ 20014 { reserved_block , 0 , 0 , 32, 20015 0xfc000007, 0xa0000006, 0 , 0, 20016 CP1_ }, /* POOL32F~*(6) */ 20017 { reserved_block , 0 , 0 , 32, 20018 0xfc000007, 0xa0000007, 0 , 0, 20019 CP1_ }, /* POOL32F~*(7) */ 20020 }; 20021 20022 20023 static const Pool POOL32S_0[64] = { 20024 { reserved_block , 0 , 0 , 32, 20025 0xfc0001ff, 0xc0000000, 0 , 0, 20026 0x0 }, /* POOL32S_0~*(0) */ 20027 { instruction , 0 , 0 , 32, 20028 0xfc0001ff, 0xc0000008, &DLSA , 0, 20029 MIPS64_ }, /* DLSA */ 20030 { instruction , 0 , 0 , 32, 20031 0xfc0001ff, 0xc0000010, &DSLLV , 0, 20032 MIPS64_ }, /* DSLLV */ 20033 { instruction , 0 , 0 , 32, 20034 0xfc0001ff, 0xc0000018, &DMUL , 0, 20035 MIPS64_ }, /* DMUL */ 20036 { reserved_block , 0 , 0 , 32, 20037 0xfc0001ff, 0xc0000020, 0 , 0, 20038 0x0 }, /* POOL32S_0~*(4) */ 20039 { reserved_block , 0 , 0 , 32, 20040 0xfc0001ff, 0xc0000028, 0 , 0, 20041 0x0 }, /* POOL32S_0~*(5) */ 20042 { reserved_block , 0 , 0 , 32, 20043 0xfc0001ff, 0xc0000030, 0 , 0, 20044 0x0 }, /* POOL32S_0~*(6) */ 20045 { reserved_block , 0 , 0 , 32, 20046 0xfc0001ff, 0xc0000038, 0 , 0, 20047 0x0 }, /* POOL32S_0~*(7) */ 20048 { reserved_block , 0 , 0 , 32, 20049 0xfc0001ff, 0xc0000040, 0 , 0, 20050 0x0 }, /* POOL32S_0~*(8) */ 20051 { reserved_block , 0 , 0 , 32, 20052 0xfc0001ff, 0xc0000048, 0 , 0, 20053 0x0 }, /* POOL32S_0~*(9) */ 20054 { instruction , 0 , 0 , 32, 20055 0xfc0001ff, 0xc0000050, &DSRLV , 0, 20056 MIPS64_ }, /* DSRLV */ 20057 { instruction , 0 , 0 , 32, 20058 0xfc0001ff, 0xc0000058, &DMUH , 0, 20059 MIPS64_ }, /* DMUH */ 20060 { reserved_block , 0 , 0 , 32, 20061 0xfc0001ff, 0xc0000060, 0 , 0, 20062 0x0 }, /* POOL32S_0~*(12) */ 20063 { reserved_block , 0 , 0 , 32, 20064 0xfc0001ff, 0xc0000068, 0 , 0, 20065 0x0 }, /* POOL32S_0~*(13) */ 20066 { reserved_block , 0 , 0 , 32, 20067 0xfc0001ff, 0xc0000070, 0 , 0, 20068 0x0 }, /* POOL32S_0~*(14) */ 20069 { reserved_block , 0 , 0 , 32, 20070 0xfc0001ff, 0xc0000078, 0 , 0, 20071 0x0 }, /* POOL32S_0~*(15) */ 20072 { reserved_block , 0 , 0 , 32, 20073 0xfc0001ff, 0xc0000080, 0 , 0, 20074 0x0 }, /* POOL32S_0~*(16) */ 20075 { reserved_block , 0 , 0 , 32, 20076 0xfc0001ff, 0xc0000088, 0 , 0, 20077 0x0 }, /* POOL32S_0~*(17) */ 20078 { instruction , 0 , 0 , 32, 20079 0xfc0001ff, 0xc0000090, &DSRAV , 0, 20080 MIPS64_ }, /* DSRAV */ 20081 { instruction , 0 , 0 , 32, 20082 0xfc0001ff, 0xc0000098, &DMULU , 0, 20083 MIPS64_ }, /* DMULU */ 20084 { reserved_block , 0 , 0 , 32, 20085 0xfc0001ff, 0xc00000a0, 0 , 0, 20086 0x0 }, /* POOL32S_0~*(20) */ 20087 { reserved_block , 0 , 0 , 32, 20088 0xfc0001ff, 0xc00000a8, 0 , 0, 20089 0x0 }, /* POOL32S_0~*(21) */ 20090 { reserved_block , 0 , 0 , 32, 20091 0xfc0001ff, 0xc00000b0, 0 , 0, 20092 0x0 }, /* POOL32S_0~*(22) */ 20093 { reserved_block , 0 , 0 , 32, 20094 0xfc0001ff, 0xc00000b8, 0 , 0, 20095 0x0 }, /* POOL32S_0~*(23) */ 20096 { reserved_block , 0 , 0 , 32, 20097 0xfc0001ff, 0xc00000c0, 0 , 0, 20098 0x0 }, /* POOL32S_0~*(24) */ 20099 { reserved_block , 0 , 0 , 32, 20100 0xfc0001ff, 0xc00000c8, 0 , 0, 20101 0x0 }, /* POOL32S_0~*(25) */ 20102 { instruction , 0 , 0 , 32, 20103 0xfc0001ff, 0xc00000d0, &DROTRV , 0, 20104 MIPS64_ }, /* DROTRV */ 20105 { instruction , 0 , 0 , 32, 20106 0xfc0001ff, 0xc00000d8, &DMUHU , 0, 20107 MIPS64_ }, /* DMUHU */ 20108 { reserved_block , 0 , 0 , 32, 20109 0xfc0001ff, 0xc00000e0, 0 , 0, 20110 0x0 }, /* POOL32S_0~*(28) */ 20111 { reserved_block , 0 , 0 , 32, 20112 0xfc0001ff, 0xc00000e8, 0 , 0, 20113 0x0 }, /* POOL32S_0~*(29) */ 20114 { reserved_block , 0 , 0 , 32, 20115 0xfc0001ff, 0xc00000f0, 0 , 0, 20116 0x0 }, /* POOL32S_0~*(30) */ 20117 { reserved_block , 0 , 0 , 32, 20118 0xfc0001ff, 0xc00000f8, 0 , 0, 20119 0x0 }, /* POOL32S_0~*(31) */ 20120 { reserved_block , 0 , 0 , 32, 20121 0xfc0001ff, 0xc0000100, 0 , 0, 20122 0x0 }, /* POOL32S_0~*(32) */ 20123 { reserved_block , 0 , 0 , 32, 20124 0xfc0001ff, 0xc0000108, 0 , 0, 20125 0x0 }, /* POOL32S_0~*(33) */ 20126 { instruction , 0 , 0 , 32, 20127 0xfc0001ff, 0xc0000110, &DADD , 0, 20128 MIPS64_ }, /* DADD */ 20129 { instruction , 0 , 0 , 32, 20130 0xfc0001ff, 0xc0000118, &DDIV , 0, 20131 MIPS64_ }, /* DDIV */ 20132 { reserved_block , 0 , 0 , 32, 20133 0xfc0001ff, 0xc0000120, 0 , 0, 20134 0x0 }, /* POOL32S_0~*(36) */ 20135 { reserved_block , 0 , 0 , 32, 20136 0xfc0001ff, 0xc0000128, 0 , 0, 20137 0x0 }, /* POOL32S_0~*(37) */ 20138 { reserved_block , 0 , 0 , 32, 20139 0xfc0001ff, 0xc0000130, 0 , 0, 20140 0x0 }, /* POOL32S_0~*(38) */ 20141 { reserved_block , 0 , 0 , 32, 20142 0xfc0001ff, 0xc0000138, 0 , 0, 20143 0x0 }, /* POOL32S_0~*(39) */ 20144 { reserved_block , 0 , 0 , 32, 20145 0xfc0001ff, 0xc0000140, 0 , 0, 20146 0x0 }, /* POOL32S_0~*(40) */ 20147 { reserved_block , 0 , 0 , 32, 20148 0xfc0001ff, 0xc0000148, 0 , 0, 20149 0x0 }, /* POOL32S_0~*(41) */ 20150 { instruction , 0 , 0 , 32, 20151 0xfc0001ff, 0xc0000150, &DADDU , 0, 20152 MIPS64_ }, /* DADDU */ 20153 { instruction , 0 , 0 , 32, 20154 0xfc0001ff, 0xc0000158, &DMOD , 0, 20155 MIPS64_ }, /* DMOD */ 20156 { reserved_block , 0 , 0 , 32, 20157 0xfc0001ff, 0xc0000160, 0 , 0, 20158 0x0 }, /* POOL32S_0~*(44) */ 20159 { reserved_block , 0 , 0 , 32, 20160 0xfc0001ff, 0xc0000168, 0 , 0, 20161 0x0 }, /* POOL32S_0~*(45) */ 20162 { reserved_block , 0 , 0 , 32, 20163 0xfc0001ff, 0xc0000170, 0 , 0, 20164 0x0 }, /* POOL32S_0~*(46) */ 20165 { reserved_block , 0 , 0 , 32, 20166 0xfc0001ff, 0xc0000178, 0 , 0, 20167 0x0 }, /* POOL32S_0~*(47) */ 20168 { reserved_block , 0 , 0 , 32, 20169 0xfc0001ff, 0xc0000180, 0 , 0, 20170 0x0 }, /* POOL32S_0~*(48) */ 20171 { reserved_block , 0 , 0 , 32, 20172 0xfc0001ff, 0xc0000188, 0 , 0, 20173 0x0 }, /* POOL32S_0~*(49) */ 20174 { instruction , 0 , 0 , 32, 20175 0xfc0001ff, 0xc0000190, &DSUB , 0, 20176 MIPS64_ }, /* DSUB */ 20177 { instruction , 0 , 0 , 32, 20178 0xfc0001ff, 0xc0000198, &DDIVU , 0, 20179 MIPS64_ }, /* DDIVU */ 20180 { reserved_block , 0 , 0 , 32, 20181 0xfc0001ff, 0xc00001a0, 0 , 0, 20182 0x0 }, /* POOL32S_0~*(52) */ 20183 { reserved_block , 0 , 0 , 32, 20184 0xfc0001ff, 0xc00001a8, 0 , 0, 20185 0x0 }, /* POOL32S_0~*(53) */ 20186 { reserved_block , 0 , 0 , 32, 20187 0xfc0001ff, 0xc00001b0, 0 , 0, 20188 0x0 }, /* POOL32S_0~*(54) */ 20189 { reserved_block , 0 , 0 , 32, 20190 0xfc0001ff, 0xc00001b8, 0 , 0, 20191 0x0 }, /* POOL32S_0~*(55) */ 20192 { reserved_block , 0 , 0 , 32, 20193 0xfc0001ff, 0xc00001c0, 0 , 0, 20194 0x0 }, /* POOL32S_0~*(56) */ 20195 { reserved_block , 0 , 0 , 32, 20196 0xfc0001ff, 0xc00001c8, 0 , 0, 20197 0x0 }, /* POOL32S_0~*(57) */ 20198 { instruction , 0 , 0 , 32, 20199 0xfc0001ff, 0xc00001d0, &DSUBU , 0, 20200 MIPS64_ }, /* DSUBU */ 20201 { instruction , 0 , 0 , 32, 20202 0xfc0001ff, 0xc00001d8, &DMODU , 0, 20203 MIPS64_ }, /* DMODU */ 20204 { reserved_block , 0 , 0 , 32, 20205 0xfc0001ff, 0xc00001e0, 0 , 0, 20206 0x0 }, /* POOL32S_0~*(60) */ 20207 { reserved_block , 0 , 0 , 32, 20208 0xfc0001ff, 0xc00001e8, 0 , 0, 20209 0x0 }, /* POOL32S_0~*(61) */ 20210 { reserved_block , 0 , 0 , 32, 20211 0xfc0001ff, 0xc00001f0, 0 , 0, 20212 0x0 }, /* POOL32S_0~*(62) */ 20213 { reserved_block , 0 , 0 , 32, 20214 0xfc0001ff, 0xc00001f8, 0 , 0, 20215 0x0 }, /* POOL32S_0~*(63) */ 20216 }; 20217 20218 20219 static const Pool POOL32Sxf_4[128] = { 20220 { reserved_block , 0 , 0 , 32, 20221 0xfc00ffff, 0xc000013c, 0 , 0, 20222 0x0 }, /* POOL32Sxf_4~*(0) */ 20223 { reserved_block , 0 , 0 , 32, 20224 0xfc00ffff, 0xc000033c, 0 , 0, 20225 0x0 }, /* POOL32Sxf_4~*(1) */ 20226 { reserved_block , 0 , 0 , 32, 20227 0xfc00ffff, 0xc000053c, 0 , 0, 20228 0x0 }, /* POOL32Sxf_4~*(2) */ 20229 { reserved_block , 0 , 0 , 32, 20230 0xfc00ffff, 0xc000073c, 0 , 0, 20231 0x0 }, /* POOL32Sxf_4~*(3) */ 20232 { reserved_block , 0 , 0 , 32, 20233 0xfc00ffff, 0xc000093c, 0 , 0, 20234 0x0 }, /* POOL32Sxf_4~*(4) */ 20235 { reserved_block , 0 , 0 , 32, 20236 0xfc00ffff, 0xc0000b3c, 0 , 0, 20237 0x0 }, /* POOL32Sxf_4~*(5) */ 20238 { reserved_block , 0 , 0 , 32, 20239 0xfc00ffff, 0xc0000d3c, 0 , 0, 20240 0x0 }, /* POOL32Sxf_4~*(6) */ 20241 { reserved_block , 0 , 0 , 32, 20242 0xfc00ffff, 0xc0000f3c, 0 , 0, 20243 0x0 }, /* POOL32Sxf_4~*(7) */ 20244 { reserved_block , 0 , 0 , 32, 20245 0xfc00ffff, 0xc000113c, 0 , 0, 20246 0x0 }, /* POOL32Sxf_4~*(8) */ 20247 { reserved_block , 0 , 0 , 32, 20248 0xfc00ffff, 0xc000133c, 0 , 0, 20249 0x0 }, /* POOL32Sxf_4~*(9) */ 20250 { reserved_block , 0 , 0 , 32, 20251 0xfc00ffff, 0xc000153c, 0 , 0, 20252 0x0 }, /* POOL32Sxf_4~*(10) */ 20253 { reserved_block , 0 , 0 , 32, 20254 0xfc00ffff, 0xc000173c, 0 , 0, 20255 0x0 }, /* POOL32Sxf_4~*(11) */ 20256 { reserved_block , 0 , 0 , 32, 20257 0xfc00ffff, 0xc000193c, 0 , 0, 20258 0x0 }, /* POOL32Sxf_4~*(12) */ 20259 { reserved_block , 0 , 0 , 32, 20260 0xfc00ffff, 0xc0001b3c, 0 , 0, 20261 0x0 }, /* POOL32Sxf_4~*(13) */ 20262 { reserved_block , 0 , 0 , 32, 20263 0xfc00ffff, 0xc0001d3c, 0 , 0, 20264 0x0 }, /* POOL32Sxf_4~*(14) */ 20265 { reserved_block , 0 , 0 , 32, 20266 0xfc00ffff, 0xc0001f3c, 0 , 0, 20267 0x0 }, /* POOL32Sxf_4~*(15) */ 20268 { reserved_block , 0 , 0 , 32, 20269 0xfc00ffff, 0xc000213c, 0 , 0, 20270 0x0 }, /* POOL32Sxf_4~*(16) */ 20271 { reserved_block , 0 , 0 , 32, 20272 0xfc00ffff, 0xc000233c, 0 , 0, 20273 0x0 }, /* POOL32Sxf_4~*(17) */ 20274 { reserved_block , 0 , 0 , 32, 20275 0xfc00ffff, 0xc000253c, 0 , 0, 20276 0x0 }, /* POOL32Sxf_4~*(18) */ 20277 { reserved_block , 0 , 0 , 32, 20278 0xfc00ffff, 0xc000273c, 0 , 0, 20279 0x0 }, /* POOL32Sxf_4~*(19) */ 20280 { reserved_block , 0 , 0 , 32, 20281 0xfc00ffff, 0xc000293c, 0 , 0, 20282 0x0 }, /* POOL32Sxf_4~*(20) */ 20283 { reserved_block , 0 , 0 , 32, 20284 0xfc00ffff, 0xc0002b3c, 0 , 0, 20285 0x0 }, /* POOL32Sxf_4~*(21) */ 20286 { reserved_block , 0 , 0 , 32, 20287 0xfc00ffff, 0xc0002d3c, 0 , 0, 20288 0x0 }, /* POOL32Sxf_4~*(22) */ 20289 { reserved_block , 0 , 0 , 32, 20290 0xfc00ffff, 0xc0002f3c, 0 , 0, 20291 0x0 }, /* POOL32Sxf_4~*(23) */ 20292 { reserved_block , 0 , 0 , 32, 20293 0xfc00ffff, 0xc000313c, 0 , 0, 20294 0x0 }, /* POOL32Sxf_4~*(24) */ 20295 { reserved_block , 0 , 0 , 32, 20296 0xfc00ffff, 0xc000333c, 0 , 0, 20297 0x0 }, /* POOL32Sxf_4~*(25) */ 20298 { reserved_block , 0 , 0 , 32, 20299 0xfc00ffff, 0xc000353c, 0 , 0, 20300 0x0 }, /* POOL32Sxf_4~*(26) */ 20301 { reserved_block , 0 , 0 , 32, 20302 0xfc00ffff, 0xc000373c, 0 , 0, 20303 0x0 }, /* POOL32Sxf_4~*(27) */ 20304 { reserved_block , 0 , 0 , 32, 20305 0xfc00ffff, 0xc000393c, 0 , 0, 20306 0x0 }, /* POOL32Sxf_4~*(28) */ 20307 { reserved_block , 0 , 0 , 32, 20308 0xfc00ffff, 0xc0003b3c, 0 , 0, 20309 0x0 }, /* POOL32Sxf_4~*(29) */ 20310 { reserved_block , 0 , 0 , 32, 20311 0xfc00ffff, 0xc0003d3c, 0 , 0, 20312 0x0 }, /* POOL32Sxf_4~*(30) */ 20313 { reserved_block , 0 , 0 , 32, 20314 0xfc00ffff, 0xc0003f3c, 0 , 0, 20315 0x0 }, /* POOL32Sxf_4~*(31) */ 20316 { reserved_block , 0 , 0 , 32, 20317 0xfc00ffff, 0xc000413c, 0 , 0, 20318 0x0 }, /* POOL32Sxf_4~*(32) */ 20319 { reserved_block , 0 , 0 , 32, 20320 0xfc00ffff, 0xc000433c, 0 , 0, 20321 0x0 }, /* POOL32Sxf_4~*(33) */ 20322 { reserved_block , 0 , 0 , 32, 20323 0xfc00ffff, 0xc000453c, 0 , 0, 20324 0x0 }, /* POOL32Sxf_4~*(34) */ 20325 { reserved_block , 0 , 0 , 32, 20326 0xfc00ffff, 0xc000473c, 0 , 0, 20327 0x0 }, /* POOL32Sxf_4~*(35) */ 20328 { reserved_block , 0 , 0 , 32, 20329 0xfc00ffff, 0xc000493c, 0 , 0, 20330 0x0 }, /* POOL32Sxf_4~*(36) */ 20331 { instruction , 0 , 0 , 32, 20332 0xfc00ffff, 0xc0004b3c, &DCLO , 0, 20333 MIPS64_ }, /* DCLO */ 20334 { reserved_block , 0 , 0 , 32, 20335 0xfc00ffff, 0xc0004d3c, 0 , 0, 20336 0x0 }, /* POOL32Sxf_4~*(38) */ 20337 { reserved_block , 0 , 0 , 32, 20338 0xfc00ffff, 0xc0004f3c, 0 , 0, 20339 0x0 }, /* POOL32Sxf_4~*(39) */ 20340 { reserved_block , 0 , 0 , 32, 20341 0xfc00ffff, 0xc000513c, 0 , 0, 20342 0x0 }, /* POOL32Sxf_4~*(40) */ 20343 { reserved_block , 0 , 0 , 32, 20344 0xfc00ffff, 0xc000533c, 0 , 0, 20345 0x0 }, /* POOL32Sxf_4~*(41) */ 20346 { reserved_block , 0 , 0 , 32, 20347 0xfc00ffff, 0xc000553c, 0 , 0, 20348 0x0 }, /* POOL32Sxf_4~*(42) */ 20349 { reserved_block , 0 , 0 , 32, 20350 0xfc00ffff, 0xc000573c, 0 , 0, 20351 0x0 }, /* POOL32Sxf_4~*(43) */ 20352 { reserved_block , 0 , 0 , 32, 20353 0xfc00ffff, 0xc000593c, 0 , 0, 20354 0x0 }, /* POOL32Sxf_4~*(44) */ 20355 { instruction , 0 , 0 , 32, 20356 0xfc00ffff, 0xc0005b3c, &DCLZ , 0, 20357 MIPS64_ }, /* DCLZ */ 20358 { reserved_block , 0 , 0 , 32, 20359 0xfc00ffff, 0xc0005d3c, 0 , 0, 20360 0x0 }, /* POOL32Sxf_4~*(46) */ 20361 { reserved_block , 0 , 0 , 32, 20362 0xfc00ffff, 0xc0005f3c, 0 , 0, 20363 0x0 }, /* POOL32Sxf_4~*(47) */ 20364 { reserved_block , 0 , 0 , 32, 20365 0xfc00ffff, 0xc000613c, 0 , 0, 20366 0x0 }, /* POOL32Sxf_4~*(48) */ 20367 { reserved_block , 0 , 0 , 32, 20368 0xfc00ffff, 0xc000633c, 0 , 0, 20369 0x0 }, /* POOL32Sxf_4~*(49) */ 20370 { reserved_block , 0 , 0 , 32, 20371 0xfc00ffff, 0xc000653c, 0 , 0, 20372 0x0 }, /* POOL32Sxf_4~*(50) */ 20373 { reserved_block , 0 , 0 , 32, 20374 0xfc00ffff, 0xc000673c, 0 , 0, 20375 0x0 }, /* POOL32Sxf_4~*(51) */ 20376 { reserved_block , 0 , 0 , 32, 20377 0xfc00ffff, 0xc000693c, 0 , 0, 20378 0x0 }, /* POOL32Sxf_4~*(52) */ 20379 { reserved_block , 0 , 0 , 32, 20380 0xfc00ffff, 0xc0006b3c, 0 , 0, 20381 0x0 }, /* POOL32Sxf_4~*(53) */ 20382 { reserved_block , 0 , 0 , 32, 20383 0xfc00ffff, 0xc0006d3c, 0 , 0, 20384 0x0 }, /* POOL32Sxf_4~*(54) */ 20385 { reserved_block , 0 , 0 , 32, 20386 0xfc00ffff, 0xc0006f3c, 0 , 0, 20387 0x0 }, /* POOL32Sxf_4~*(55) */ 20388 { reserved_block , 0 , 0 , 32, 20389 0xfc00ffff, 0xc000713c, 0 , 0, 20390 0x0 }, /* POOL32Sxf_4~*(56) */ 20391 { reserved_block , 0 , 0 , 32, 20392 0xfc00ffff, 0xc000733c, 0 , 0, 20393 0x0 }, /* POOL32Sxf_4~*(57) */ 20394 { reserved_block , 0 , 0 , 32, 20395 0xfc00ffff, 0xc000753c, 0 , 0, 20396 0x0 }, /* POOL32Sxf_4~*(58) */ 20397 { reserved_block , 0 , 0 , 32, 20398 0xfc00ffff, 0xc000773c, 0 , 0, 20399 0x0 }, /* POOL32Sxf_4~*(59) */ 20400 { reserved_block , 0 , 0 , 32, 20401 0xfc00ffff, 0xc000793c, 0 , 0, 20402 0x0 }, /* POOL32Sxf_4~*(60) */ 20403 { reserved_block , 0 , 0 , 32, 20404 0xfc00ffff, 0xc0007b3c, 0 , 0, 20405 0x0 }, /* POOL32Sxf_4~*(61) */ 20406 { reserved_block , 0 , 0 , 32, 20407 0xfc00ffff, 0xc0007d3c, 0 , 0, 20408 0x0 }, /* POOL32Sxf_4~*(62) */ 20409 { reserved_block , 0 , 0 , 32, 20410 0xfc00ffff, 0xc0007f3c, 0 , 0, 20411 0x0 }, /* POOL32Sxf_4~*(63) */ 20412 { reserved_block , 0 , 0 , 32, 20413 0xfc00ffff, 0xc000813c, 0 , 0, 20414 0x0 }, /* POOL32Sxf_4~*(64) */ 20415 { reserved_block , 0 , 0 , 32, 20416 0xfc00ffff, 0xc000833c, 0 , 0, 20417 0x0 }, /* POOL32Sxf_4~*(65) */ 20418 { reserved_block , 0 , 0 , 32, 20419 0xfc00ffff, 0xc000853c, 0 , 0, 20420 0x0 }, /* POOL32Sxf_4~*(66) */ 20421 { reserved_block , 0 , 0 , 32, 20422 0xfc00ffff, 0xc000873c, 0 , 0, 20423 0x0 }, /* POOL32Sxf_4~*(67) */ 20424 { reserved_block , 0 , 0 , 32, 20425 0xfc00ffff, 0xc000893c, 0 , 0, 20426 0x0 }, /* POOL32Sxf_4~*(68) */ 20427 { reserved_block , 0 , 0 , 32, 20428 0xfc00ffff, 0xc0008b3c, 0 , 0, 20429 0x0 }, /* POOL32Sxf_4~*(69) */ 20430 { reserved_block , 0 , 0 , 32, 20431 0xfc00ffff, 0xc0008d3c, 0 , 0, 20432 0x0 }, /* POOL32Sxf_4~*(70) */ 20433 { reserved_block , 0 , 0 , 32, 20434 0xfc00ffff, 0xc0008f3c, 0 , 0, 20435 0x0 }, /* POOL32Sxf_4~*(71) */ 20436 { reserved_block , 0 , 0 , 32, 20437 0xfc00ffff, 0xc000913c, 0 , 0, 20438 0x0 }, /* POOL32Sxf_4~*(72) */ 20439 { reserved_block , 0 , 0 , 32, 20440 0xfc00ffff, 0xc000933c, 0 , 0, 20441 0x0 }, /* POOL32Sxf_4~*(73) */ 20442 { reserved_block , 0 , 0 , 32, 20443 0xfc00ffff, 0xc000953c, 0 , 0, 20444 0x0 }, /* POOL32Sxf_4~*(74) */ 20445 { reserved_block , 0 , 0 , 32, 20446 0xfc00ffff, 0xc000973c, 0 , 0, 20447 0x0 }, /* POOL32Sxf_4~*(75) */ 20448 { reserved_block , 0 , 0 , 32, 20449 0xfc00ffff, 0xc000993c, 0 , 0, 20450 0x0 }, /* POOL32Sxf_4~*(76) */ 20451 { reserved_block , 0 , 0 , 32, 20452 0xfc00ffff, 0xc0009b3c, 0 , 0, 20453 0x0 }, /* POOL32Sxf_4~*(77) */ 20454 { reserved_block , 0 , 0 , 32, 20455 0xfc00ffff, 0xc0009d3c, 0 , 0, 20456 0x0 }, /* POOL32Sxf_4~*(78) */ 20457 { reserved_block , 0 , 0 , 32, 20458 0xfc00ffff, 0xc0009f3c, 0 , 0, 20459 0x0 }, /* POOL32Sxf_4~*(79) */ 20460 { reserved_block , 0 , 0 , 32, 20461 0xfc00ffff, 0xc000a13c, 0 , 0, 20462 0x0 }, /* POOL32Sxf_4~*(80) */ 20463 { reserved_block , 0 , 0 , 32, 20464 0xfc00ffff, 0xc000a33c, 0 , 0, 20465 0x0 }, /* POOL32Sxf_4~*(81) */ 20466 { reserved_block , 0 , 0 , 32, 20467 0xfc00ffff, 0xc000a53c, 0 , 0, 20468 0x0 }, /* POOL32Sxf_4~*(82) */ 20469 { reserved_block , 0 , 0 , 32, 20470 0xfc00ffff, 0xc000a73c, 0 , 0, 20471 0x0 }, /* POOL32Sxf_4~*(83) */ 20472 { reserved_block , 0 , 0 , 32, 20473 0xfc00ffff, 0xc000a93c, 0 , 0, 20474 0x0 }, /* POOL32Sxf_4~*(84) */ 20475 { reserved_block , 0 , 0 , 32, 20476 0xfc00ffff, 0xc000ab3c, 0 , 0, 20477 0x0 }, /* POOL32Sxf_4~*(85) */ 20478 { reserved_block , 0 , 0 , 32, 20479 0xfc00ffff, 0xc000ad3c, 0 , 0, 20480 0x0 }, /* POOL32Sxf_4~*(86) */ 20481 { reserved_block , 0 , 0 , 32, 20482 0xfc00ffff, 0xc000af3c, 0 , 0, 20483 0x0 }, /* POOL32Sxf_4~*(87) */ 20484 { reserved_block , 0 , 0 , 32, 20485 0xfc00ffff, 0xc000b13c, 0 , 0, 20486 0x0 }, /* POOL32Sxf_4~*(88) */ 20487 { reserved_block , 0 , 0 , 32, 20488 0xfc00ffff, 0xc000b33c, 0 , 0, 20489 0x0 }, /* POOL32Sxf_4~*(89) */ 20490 { reserved_block , 0 , 0 , 32, 20491 0xfc00ffff, 0xc000b53c, 0 , 0, 20492 0x0 }, /* POOL32Sxf_4~*(90) */ 20493 { reserved_block , 0 , 0 , 32, 20494 0xfc00ffff, 0xc000b73c, 0 , 0, 20495 0x0 }, /* POOL32Sxf_4~*(91) */ 20496 { reserved_block , 0 , 0 , 32, 20497 0xfc00ffff, 0xc000b93c, 0 , 0, 20498 0x0 }, /* POOL32Sxf_4~*(92) */ 20499 { reserved_block , 0 , 0 , 32, 20500 0xfc00ffff, 0xc000bb3c, 0 , 0, 20501 0x0 }, /* POOL32Sxf_4~*(93) */ 20502 { reserved_block , 0 , 0 , 32, 20503 0xfc00ffff, 0xc000bd3c, 0 , 0, 20504 0x0 }, /* POOL32Sxf_4~*(94) */ 20505 { reserved_block , 0 , 0 , 32, 20506 0xfc00ffff, 0xc000bf3c, 0 , 0, 20507 0x0 }, /* POOL32Sxf_4~*(95) */ 20508 { reserved_block , 0 , 0 , 32, 20509 0xfc00ffff, 0xc000c13c, 0 , 0, 20510 0x0 }, /* POOL32Sxf_4~*(96) */ 20511 { reserved_block , 0 , 0 , 32, 20512 0xfc00ffff, 0xc000c33c, 0 , 0, 20513 0x0 }, /* POOL32Sxf_4~*(97) */ 20514 { reserved_block , 0 , 0 , 32, 20515 0xfc00ffff, 0xc000c53c, 0 , 0, 20516 0x0 }, /* POOL32Sxf_4~*(98) */ 20517 { reserved_block , 0 , 0 , 32, 20518 0xfc00ffff, 0xc000c73c, 0 , 0, 20519 0x0 }, /* POOL32Sxf_4~*(99) */ 20520 { reserved_block , 0 , 0 , 32, 20521 0xfc00ffff, 0xc000c93c, 0 , 0, 20522 0x0 }, /* POOL32Sxf_4~*(100) */ 20523 { reserved_block , 0 , 0 , 32, 20524 0xfc00ffff, 0xc000cb3c, 0 , 0, 20525 0x0 }, /* POOL32Sxf_4~*(101) */ 20526 { reserved_block , 0 , 0 , 32, 20527 0xfc00ffff, 0xc000cd3c, 0 , 0, 20528 0x0 }, /* POOL32Sxf_4~*(102) */ 20529 { reserved_block , 0 , 0 , 32, 20530 0xfc00ffff, 0xc000cf3c, 0 , 0, 20531 0x0 }, /* POOL32Sxf_4~*(103) */ 20532 { reserved_block , 0 , 0 , 32, 20533 0xfc00ffff, 0xc000d13c, 0 , 0, 20534 0x0 }, /* POOL32Sxf_4~*(104) */ 20535 { reserved_block , 0 , 0 , 32, 20536 0xfc00ffff, 0xc000d33c, 0 , 0, 20537 0x0 }, /* POOL32Sxf_4~*(105) */ 20538 { reserved_block , 0 , 0 , 32, 20539 0xfc00ffff, 0xc000d53c, 0 , 0, 20540 0x0 }, /* POOL32Sxf_4~*(106) */ 20541 { reserved_block , 0 , 0 , 32, 20542 0xfc00ffff, 0xc000d73c, 0 , 0, 20543 0x0 }, /* POOL32Sxf_4~*(107) */ 20544 { reserved_block , 0 , 0 , 32, 20545 0xfc00ffff, 0xc000d93c, 0 , 0, 20546 0x0 }, /* POOL32Sxf_4~*(108) */ 20547 { reserved_block , 0 , 0 , 32, 20548 0xfc00ffff, 0xc000db3c, 0 , 0, 20549 0x0 }, /* POOL32Sxf_4~*(109) */ 20550 { reserved_block , 0 , 0 , 32, 20551 0xfc00ffff, 0xc000dd3c, 0 , 0, 20552 0x0 }, /* POOL32Sxf_4~*(110) */ 20553 { reserved_block , 0 , 0 , 32, 20554 0xfc00ffff, 0xc000df3c, 0 , 0, 20555 0x0 }, /* POOL32Sxf_4~*(111) */ 20556 { reserved_block , 0 , 0 , 32, 20557 0xfc00ffff, 0xc000e13c, 0 , 0, 20558 0x0 }, /* POOL32Sxf_4~*(112) */ 20559 { reserved_block , 0 , 0 , 32, 20560 0xfc00ffff, 0xc000e33c, 0 , 0, 20561 0x0 }, /* POOL32Sxf_4~*(113) */ 20562 { reserved_block , 0 , 0 , 32, 20563 0xfc00ffff, 0xc000e53c, 0 , 0, 20564 0x0 }, /* POOL32Sxf_4~*(114) */ 20565 { reserved_block , 0 , 0 , 32, 20566 0xfc00ffff, 0xc000e73c, 0 , 0, 20567 0x0 }, /* POOL32Sxf_4~*(115) */ 20568 { reserved_block , 0 , 0 , 32, 20569 0xfc00ffff, 0xc000e93c, 0 , 0, 20570 0x0 }, /* POOL32Sxf_4~*(116) */ 20571 { reserved_block , 0 , 0 , 32, 20572 0xfc00ffff, 0xc000eb3c, 0 , 0, 20573 0x0 }, /* POOL32Sxf_4~*(117) */ 20574 { reserved_block , 0 , 0 , 32, 20575 0xfc00ffff, 0xc000ed3c, 0 , 0, 20576 0x0 }, /* POOL32Sxf_4~*(118) */ 20577 { reserved_block , 0 , 0 , 32, 20578 0xfc00ffff, 0xc000ef3c, 0 , 0, 20579 0x0 }, /* POOL32Sxf_4~*(119) */ 20580 { reserved_block , 0 , 0 , 32, 20581 0xfc00ffff, 0xc000f13c, 0 , 0, 20582 0x0 }, /* POOL32Sxf_4~*(120) */ 20583 { reserved_block , 0 , 0 , 32, 20584 0xfc00ffff, 0xc000f33c, 0 , 0, 20585 0x0 }, /* POOL32Sxf_4~*(121) */ 20586 { reserved_block , 0 , 0 , 32, 20587 0xfc00ffff, 0xc000f53c, 0 , 0, 20588 0x0 }, /* POOL32Sxf_4~*(122) */ 20589 { reserved_block , 0 , 0 , 32, 20590 0xfc00ffff, 0xc000f73c, 0 , 0, 20591 0x0 }, /* POOL32Sxf_4~*(123) */ 20592 { reserved_block , 0 , 0 , 32, 20593 0xfc00ffff, 0xc000f93c, 0 , 0, 20594 0x0 }, /* POOL32Sxf_4~*(124) */ 20595 { reserved_block , 0 , 0 , 32, 20596 0xfc00ffff, 0xc000fb3c, 0 , 0, 20597 0x0 }, /* POOL32Sxf_4~*(125) */ 20598 { reserved_block , 0 , 0 , 32, 20599 0xfc00ffff, 0xc000fd3c, 0 , 0, 20600 0x0 }, /* POOL32Sxf_4~*(126) */ 20601 { reserved_block , 0 , 0 , 32, 20602 0xfc00ffff, 0xc000ff3c, 0 , 0, 20603 0x0 }, /* POOL32Sxf_4~*(127) */ 20604 }; 20605 20606 20607 static const Pool POOL32Sxf[8] = { 20608 { reserved_block , 0 , 0 , 32, 20609 0xfc0001ff, 0xc000003c, 0 , 0, 20610 0x0 }, /* POOL32Sxf~*(0) */ 20611 { reserved_block , 0 , 0 , 32, 20612 0xfc0001ff, 0xc000007c, 0 , 0, 20613 0x0 }, /* POOL32Sxf~*(1) */ 20614 { reserved_block , 0 , 0 , 32, 20615 0xfc0001ff, 0xc00000bc, 0 , 0, 20616 0x0 }, /* POOL32Sxf~*(2) */ 20617 { reserved_block , 0 , 0 , 32, 20618 0xfc0001ff, 0xc00000fc, 0 , 0, 20619 0x0 }, /* POOL32Sxf~*(3) */ 20620 { pool , POOL32Sxf_4 , 128 , 32, 20621 0xfc0001ff, 0xc000013c, 0 , 0, 20622 0x0 }, /* POOL32Sxf_4 */ 20623 { reserved_block , 0 , 0 , 32, 20624 0xfc0001ff, 0xc000017c, 0 , 0, 20625 0x0 }, /* POOL32Sxf~*(5) */ 20626 { reserved_block , 0 , 0 , 32, 20627 0xfc0001ff, 0xc00001bc, 0 , 0, 20628 0x0 }, /* POOL32Sxf~*(6) */ 20629 { reserved_block , 0 , 0 , 32, 20630 0xfc0001ff, 0xc00001fc, 0 , 0, 20631 0x0 }, /* POOL32Sxf~*(7) */ 20632 }; 20633 20634 20635 static const Pool POOL32S_4[8] = { 20636 { instruction , 0 , 0 , 32, 20637 0xfc00003f, 0xc0000004, &EXTD , 0, 20638 MIPS64_ }, /* EXTD */ 20639 { instruction , 0 , 0 , 32, 20640 0xfc00003f, 0xc000000c, &EXTD32 , 0, 20641 MIPS64_ }, /* EXTD32 */ 20642 { reserved_block , 0 , 0 , 32, 20643 0xfc00003f, 0xc0000014, 0 , 0, 20644 0x0 }, /* POOL32S_4~*(2) */ 20645 { reserved_block , 0 , 0 , 32, 20646 0xfc00003f, 0xc000001c, 0 , 0, 20647 0x0 }, /* POOL32S_4~*(3) */ 20648 { reserved_block , 0 , 0 , 32, 20649 0xfc00003f, 0xc0000024, 0 , 0, 20650 0x0 }, /* POOL32S_4~*(4) */ 20651 { reserved_block , 0 , 0 , 32, 20652 0xfc00003f, 0xc000002c, 0 , 0, 20653 0x0 }, /* POOL32S_4~*(5) */ 20654 { reserved_block , 0 , 0 , 32, 20655 0xfc00003f, 0xc0000034, 0 , 0, 20656 0x0 }, /* POOL32S_4~*(6) */ 20657 { pool , POOL32Sxf , 8 , 32, 20658 0xfc00003f, 0xc000003c, 0 , 0, 20659 0x0 }, /* POOL32Sxf */ 20660 }; 20661 20662 20663 static const Pool POOL32S[8] = { 20664 { pool , POOL32S_0 , 64 , 32, 20665 0xfc000007, 0xc0000000, 0 , 0, 20666 0x0 }, /* POOL32S_0 */ 20667 { reserved_block , 0 , 0 , 32, 20668 0xfc000007, 0xc0000001, 0 , 0, 20669 0x0 }, /* POOL32S~*(1) */ 20670 { reserved_block , 0 , 0 , 32, 20671 0xfc000007, 0xc0000002, 0 , 0, 20672 0x0 }, /* POOL32S~*(2) */ 20673 { reserved_block , 0 , 0 , 32, 20674 0xfc000007, 0xc0000003, 0 , 0, 20675 0x0 }, /* POOL32S~*(3) */ 20676 { pool , POOL32S_4 , 8 , 32, 20677 0xfc000007, 0xc0000004, 0 , 0, 20678 0x0 }, /* POOL32S_4 */ 20679 { reserved_block , 0 , 0 , 32, 20680 0xfc000007, 0xc0000005, 0 , 0, 20681 0x0 }, /* POOL32S~*(5) */ 20682 { reserved_block , 0 , 0 , 32, 20683 0xfc000007, 0xc0000006, 0 , 0, 20684 0x0 }, /* POOL32S~*(6) */ 20685 { reserved_block , 0 , 0 , 32, 20686 0xfc000007, 0xc0000007, 0 , 0, 20687 0x0 }, /* POOL32S~*(7) */ 20688 }; 20689 20690 20691 static const Pool P_LUI[2] = { 20692 { instruction , 0 , 0 , 32, 20693 0xfc000002, 0xe0000000, &LUI , 0, 20694 0x0 }, /* LUI */ 20695 { instruction , 0 , 0 , 32, 20696 0xfc000002, 0xe0000002, &ALUIPC , 0, 20697 0x0 }, /* ALUIPC */ 20698 }; 20699 20700 20701 static const Pool P_GP_LH[2] = { 20702 { instruction , 0 , 0 , 32, 20703 0xfc1c0001, 0x44100000, &LH_GP_ , 0, 20704 0x0 }, /* LH[GP] */ 20705 { instruction , 0 , 0 , 32, 20706 0xfc1c0001, 0x44100001, &LHU_GP_ , 0, 20707 0x0 }, /* LHU[GP] */ 20708 }; 20709 20710 20711 static const Pool P_GP_SH[2] = { 20712 { instruction , 0 , 0 , 32, 20713 0xfc1c0001, 0x44140000, &SH_GP_ , 0, 20714 0x0 }, /* SH[GP] */ 20715 { reserved_block , 0 , 0 , 32, 20716 0xfc1c0001, 0x44140001, 0 , 0, 20717 0x0 }, /* P.GP.SH~*(1) */ 20718 }; 20719 20720 20721 static const Pool P_GP_CP1[4] = { 20722 { instruction , 0 , 0 , 32, 20723 0xfc1c0003, 0x44180000, &LWC1_GP_ , 0, 20724 CP1_ }, /* LWC1[GP] */ 20725 { instruction , 0 , 0 , 32, 20726 0xfc1c0003, 0x44180001, &SWC1_GP_ , 0, 20727 CP1_ }, /* SWC1[GP] */ 20728 { instruction , 0 , 0 , 32, 20729 0xfc1c0003, 0x44180002, &LDC1_GP_ , 0, 20730 CP1_ }, /* LDC1[GP] */ 20731 { instruction , 0 , 0 , 32, 20732 0xfc1c0003, 0x44180003, &SDC1_GP_ , 0, 20733 CP1_ }, /* SDC1[GP] */ 20734 }; 20735 20736 20737 static const Pool P_GP_M64[4] = { 20738 { instruction , 0 , 0 , 32, 20739 0xfc1c0003, 0x441c0000, &LWU_GP_ , 0, 20740 MIPS64_ }, /* LWU[GP] */ 20741 { reserved_block , 0 , 0 , 32, 20742 0xfc1c0003, 0x441c0001, 0 , 0, 20743 0x0 }, /* P.GP.M64~*(1) */ 20744 { reserved_block , 0 , 0 , 32, 20745 0xfc1c0003, 0x441c0002, 0 , 0, 20746 0x0 }, /* P.GP.M64~*(2) */ 20747 { reserved_block , 0 , 0 , 32, 20748 0xfc1c0003, 0x441c0003, 0 , 0, 20749 0x0 }, /* P.GP.M64~*(3) */ 20750 }; 20751 20752 20753 static const Pool P_GP_BH[8] = { 20754 { instruction , 0 , 0 , 32, 20755 0xfc1c0000, 0x44000000, &LB_GP_ , 0, 20756 0x0 }, /* LB[GP] */ 20757 { instruction , 0 , 0 , 32, 20758 0xfc1c0000, 0x44040000, &SB_GP_ , 0, 20759 0x0 }, /* SB[GP] */ 20760 { instruction , 0 , 0 , 32, 20761 0xfc1c0000, 0x44080000, &LBU_GP_ , 0, 20762 0x0 }, /* LBU[GP] */ 20763 { instruction , 0 , 0 , 32, 20764 0xfc1c0000, 0x440c0000, &ADDIU_GP_B_ , 0, 20765 0x0 }, /* ADDIU[GP.B] */ 20766 { pool , P_GP_LH , 2 , 32, 20767 0xfc1c0000, 0x44100000, 0 , 0, 20768 0x0 }, /* P.GP.LH */ 20769 { pool , P_GP_SH , 2 , 32, 20770 0xfc1c0000, 0x44140000, 0 , 0, 20771 0x0 }, /* P.GP.SH */ 20772 { pool , P_GP_CP1 , 4 , 32, 20773 0xfc1c0000, 0x44180000, 0 , 0, 20774 0x0 }, /* P.GP.CP1 */ 20775 { pool , P_GP_M64 , 4 , 32, 20776 0xfc1c0000, 0x441c0000, 0 , 0, 20777 0x0 }, /* P.GP.M64 */ 20778 }; 20779 20780 20781 static const Pool P_LS_U12[16] = { 20782 { instruction , 0 , 0 , 32, 20783 0xfc00f000, 0x84000000, &LB_U12_ , 0, 20784 0x0 }, /* LB[U12] */ 20785 { instruction , 0 , 0 , 32, 20786 0xfc00f000, 0x84001000, &SB_U12_ , 0, 20787 0x0 }, /* SB[U12] */ 20788 { instruction , 0 , 0 , 32, 20789 0xfc00f000, 0x84002000, &LBU_U12_ , 0, 20790 0x0 }, /* LBU[U12] */ 20791 { instruction , 0 , 0 , 32, 20792 0xfc00f000, 0x84003000, &PREF_U12_ , 0, 20793 0x0 }, /* PREF[U12] */ 20794 { instruction , 0 , 0 , 32, 20795 0xfc00f000, 0x84004000, &LH_U12_ , 0, 20796 0x0 }, /* LH[U12] */ 20797 { instruction , 0 , 0 , 32, 20798 0xfc00f000, 0x84005000, &SH_U12_ , 0, 20799 0x0 }, /* SH[U12] */ 20800 { instruction , 0 , 0 , 32, 20801 0xfc00f000, 0x84006000, &LHU_U12_ , 0, 20802 0x0 }, /* LHU[U12] */ 20803 { instruction , 0 , 0 , 32, 20804 0xfc00f000, 0x84007000, &LWU_U12_ , 0, 20805 MIPS64_ }, /* LWU[U12] */ 20806 { instruction , 0 , 0 , 32, 20807 0xfc00f000, 0x84008000, &LW_U12_ , 0, 20808 0x0 }, /* LW[U12] */ 20809 { instruction , 0 , 0 , 32, 20810 0xfc00f000, 0x84009000, &SW_U12_ , 0, 20811 0x0 }, /* SW[U12] */ 20812 { instruction , 0 , 0 , 32, 20813 0xfc00f000, 0x8400a000, &LWC1_U12_ , 0, 20814 CP1_ }, /* LWC1[U12] */ 20815 { instruction , 0 , 0 , 32, 20816 0xfc00f000, 0x8400b000, &SWC1_U12_ , 0, 20817 CP1_ }, /* SWC1[U12] */ 20818 { instruction , 0 , 0 , 32, 20819 0xfc00f000, 0x8400c000, &LD_U12_ , 0, 20820 MIPS64_ }, /* LD[U12] */ 20821 { instruction , 0 , 0 , 32, 20822 0xfc00f000, 0x8400d000, &SD_U12_ , 0, 20823 MIPS64_ }, /* SD[U12] */ 20824 { instruction , 0 , 0 , 32, 20825 0xfc00f000, 0x8400e000, &LDC1_U12_ , 0, 20826 CP1_ }, /* LDC1[U12] */ 20827 { instruction , 0 , 0 , 32, 20828 0xfc00f000, 0x8400f000, &SDC1_U12_ , 0, 20829 CP1_ }, /* SDC1[U12] */ 20830 }; 20831 20832 20833 static const Pool P_PREF_S9_[2] = { 20834 { instruction , 0 , 0 , 32, 20835 0xffe07f00, 0xa7e01800, &SYNCI , 0, 20836 0x0 }, /* SYNCI */ 20837 { instruction , 0 , 0 , 32, 20838 0xfc007f00, 0xa4001800, &PREF_S9_ , &PREF_S9__cond , 20839 0x0 }, /* PREF[S9] */ 20840 }; 20841 20842 20843 static const Pool P_LS_S0[16] = { 20844 { instruction , 0 , 0 , 32, 20845 0xfc007f00, 0xa4000000, &LB_S9_ , 0, 20846 0x0 }, /* LB[S9] */ 20847 { instruction , 0 , 0 , 32, 20848 0xfc007f00, 0xa4000800, &SB_S9_ , 0, 20849 0x0 }, /* SB[S9] */ 20850 { instruction , 0 , 0 , 32, 20851 0xfc007f00, 0xa4001000, &LBU_S9_ , 0, 20852 0x0 }, /* LBU[S9] */ 20853 { pool , P_PREF_S9_ , 2 , 32, 20854 0xfc007f00, 0xa4001800, 0 , 0, 20855 0x0 }, /* P.PREF[S9] */ 20856 { instruction , 0 , 0 , 32, 20857 0xfc007f00, 0xa4002000, &LH_S9_ , 0, 20858 0x0 }, /* LH[S9] */ 20859 { instruction , 0 , 0 , 32, 20860 0xfc007f00, 0xa4002800, &SH_S9_ , 0, 20861 0x0 }, /* SH[S9] */ 20862 { instruction , 0 , 0 , 32, 20863 0xfc007f00, 0xa4003000, &LHU_S9_ , 0, 20864 0x0 }, /* LHU[S9] */ 20865 { instruction , 0 , 0 , 32, 20866 0xfc007f00, 0xa4003800, &LWU_S9_ , 0, 20867 MIPS64_ }, /* LWU[S9] */ 20868 { instruction , 0 , 0 , 32, 20869 0xfc007f00, 0xa4004000, &LW_S9_ , 0, 20870 0x0 }, /* LW[S9] */ 20871 { instruction , 0 , 0 , 32, 20872 0xfc007f00, 0xa4004800, &SW_S9_ , 0, 20873 0x0 }, /* SW[S9] */ 20874 { instruction , 0 , 0 , 32, 20875 0xfc007f00, 0xa4005000, &LWC1_S9_ , 0, 20876 CP1_ }, /* LWC1[S9] */ 20877 { instruction , 0 , 0 , 32, 20878 0xfc007f00, 0xa4005800, &SWC1_S9_ , 0, 20879 CP1_ }, /* SWC1[S9] */ 20880 { instruction , 0 , 0 , 32, 20881 0xfc007f00, 0xa4006000, &LD_S9_ , 0, 20882 MIPS64_ }, /* LD[S9] */ 20883 { instruction , 0 , 0 , 32, 20884 0xfc007f00, 0xa4006800, &SD_S9_ , 0, 20885 MIPS64_ }, /* SD[S9] */ 20886 { instruction , 0 , 0 , 32, 20887 0xfc007f00, 0xa4007000, &LDC1_S9_ , 0, 20888 CP1_ }, /* LDC1[S9] */ 20889 { instruction , 0 , 0 , 32, 20890 0xfc007f00, 0xa4007800, &SDC1_S9_ , 0, 20891 CP1_ }, /* SDC1[S9] */ 20892 }; 20893 20894 20895 static const Pool ASET_ACLR[2] = { 20896 { instruction , 0 , 0 , 32, 20897 0xfe007f00, 0xa4001100, &ASET , 0, 20898 MCU_ }, /* ASET */ 20899 { instruction , 0 , 0 , 32, 20900 0xfe007f00, 0xa6001100, &ACLR , 0, 20901 MCU_ }, /* ACLR */ 20902 }; 20903 20904 20905 static const Pool P_LL[4] = { 20906 { instruction , 0 , 0 , 32, 20907 0xfc007f03, 0xa4005100, &LL , 0, 20908 0x0 }, /* LL */ 20909 { instruction , 0 , 0 , 32, 20910 0xfc007f03, 0xa4005101, &LLWP , 0, 20911 XNP_ }, /* LLWP */ 20912 { reserved_block , 0 , 0 , 32, 20913 0xfc007f03, 0xa4005102, 0 , 0, 20914 0x0 }, /* P.LL~*(2) */ 20915 { reserved_block , 0 , 0 , 32, 20916 0xfc007f03, 0xa4005103, 0 , 0, 20917 0x0 }, /* P.LL~*(3) */ 20918 }; 20919 20920 20921 static const Pool P_SC[4] = { 20922 { instruction , 0 , 0 , 32, 20923 0xfc007f03, 0xa4005900, &SC , 0, 20924 0x0 }, /* SC */ 20925 { instruction , 0 , 0 , 32, 20926 0xfc007f03, 0xa4005901, &SCWP , 0, 20927 XNP_ }, /* SCWP */ 20928 { reserved_block , 0 , 0 , 32, 20929 0xfc007f03, 0xa4005902, 0 , 0, 20930 0x0 }, /* P.SC~*(2) */ 20931 { reserved_block , 0 , 0 , 32, 20932 0xfc007f03, 0xa4005903, 0 , 0, 20933 0x0 }, /* P.SC~*(3) */ 20934 }; 20935 20936 20937 static const Pool P_LLD[8] = { 20938 { instruction , 0 , 0 , 32, 20939 0xfc007f07, 0xa4007100, &LLD , 0, 20940 MIPS64_ }, /* LLD */ 20941 { instruction , 0 , 0 , 32, 20942 0xfc007f07, 0xa4007101, &LLDP , 0, 20943 MIPS64_ }, /* LLDP */ 20944 { reserved_block , 0 , 0 , 32, 20945 0xfc007f07, 0xa4007102, 0 , 0, 20946 0x0 }, /* P.LLD~*(2) */ 20947 { reserved_block , 0 , 0 , 32, 20948 0xfc007f07, 0xa4007103, 0 , 0, 20949 0x0 }, /* P.LLD~*(3) */ 20950 { reserved_block , 0 , 0 , 32, 20951 0xfc007f07, 0xa4007104, 0 , 0, 20952 0x0 }, /* P.LLD~*(4) */ 20953 { reserved_block , 0 , 0 , 32, 20954 0xfc007f07, 0xa4007105, 0 , 0, 20955 0x0 }, /* P.LLD~*(5) */ 20956 { reserved_block , 0 , 0 , 32, 20957 0xfc007f07, 0xa4007106, 0 , 0, 20958 0x0 }, /* P.LLD~*(6) */ 20959 { reserved_block , 0 , 0 , 32, 20960 0xfc007f07, 0xa4007107, 0 , 0, 20961 0x0 }, /* P.LLD~*(7) */ 20962 }; 20963 20964 20965 static const Pool P_SCD[8] = { 20966 { instruction , 0 , 0 , 32, 20967 0xfc007f07, 0xa4007900, &SCD , 0, 20968 MIPS64_ }, /* SCD */ 20969 { instruction , 0 , 0 , 32, 20970 0xfc007f07, 0xa4007901, &SCDP , 0, 20971 MIPS64_ }, /* SCDP */ 20972 { reserved_block , 0 , 0 , 32, 20973 0xfc007f07, 0xa4007902, 0 , 0, 20974 0x0 }, /* P.SCD~*(2) */ 20975 { reserved_block , 0 , 0 , 32, 20976 0xfc007f07, 0xa4007903, 0 , 0, 20977 0x0 }, /* P.SCD~*(3) */ 20978 { reserved_block , 0 , 0 , 32, 20979 0xfc007f07, 0xa4007904, 0 , 0, 20980 0x0 }, /* P.SCD~*(4) */ 20981 { reserved_block , 0 , 0 , 32, 20982 0xfc007f07, 0xa4007905, 0 , 0, 20983 0x0 }, /* P.SCD~*(5) */ 20984 { reserved_block , 0 , 0 , 32, 20985 0xfc007f07, 0xa4007906, 0 , 0, 20986 0x0 }, /* P.SCD~*(6) */ 20987 { reserved_block , 0 , 0 , 32, 20988 0xfc007f07, 0xa4007907, 0 , 0, 20989 0x0 }, /* P.SCD~*(7) */ 20990 }; 20991 20992 20993 static const Pool P_LS_S1[16] = { 20994 { reserved_block , 0 , 0 , 32, 20995 0xfc007f00, 0xa4000100, 0 , 0, 20996 0x0 }, /* P.LS.S1~*(0) */ 20997 { reserved_block , 0 , 0 , 32, 20998 0xfc007f00, 0xa4000900, 0 , 0, 20999 0x0 }, /* P.LS.S1~*(1) */ 21000 { pool , ASET_ACLR , 2 , 32, 21001 0xfc007f00, 0xa4001100, 0 , 0, 21002 0x0 }, /* ASET_ACLR */ 21003 { reserved_block , 0 , 0 , 32, 21004 0xfc007f00, 0xa4001900, 0 , 0, 21005 0x0 }, /* P.LS.S1~*(3) */ 21006 { instruction , 0 , 0 , 32, 21007 0xfc007f00, 0xa4002100, &UALH , 0, 21008 XMMS_ }, /* UALH */ 21009 { instruction , 0 , 0 , 32, 21010 0xfc007f00, 0xa4002900, &UASH , 0, 21011 XMMS_ }, /* UASH */ 21012 { reserved_block , 0 , 0 , 32, 21013 0xfc007f00, 0xa4003100, 0 , 0, 21014 0x0 }, /* P.LS.S1~*(6) */ 21015 { instruction , 0 , 0 , 32, 21016 0xfc007f00, 0xa4003900, &CACHE , 0, 21017 CP0_ }, /* CACHE */ 21018 { instruction , 0 , 0 , 32, 21019 0xfc007f00, 0xa4004100, &LWC2 , 0, 21020 CP2_ }, /* LWC2 */ 21021 { instruction , 0 , 0 , 32, 21022 0xfc007f00, 0xa4004900, &SWC2 , 0, 21023 CP2_ }, /* SWC2 */ 21024 { pool , P_LL , 4 , 32, 21025 0xfc007f00, 0xa4005100, 0 , 0, 21026 0x0 }, /* P.LL */ 21027 { pool , P_SC , 4 , 32, 21028 0xfc007f00, 0xa4005900, 0 , 0, 21029 0x0 }, /* P.SC */ 21030 { instruction , 0 , 0 , 32, 21031 0xfc007f00, 0xa4006100, &LDC2 , 0, 21032 CP2_ }, /* LDC2 */ 21033 { instruction , 0 , 0 , 32, 21034 0xfc007f00, 0xa4006900, &SDC2 , 0, 21035 CP2_ }, /* SDC2 */ 21036 { pool , P_LLD , 8 , 32, 21037 0xfc007f00, 0xa4007100, 0 , 0, 21038 0x0 }, /* P.LLD */ 21039 { pool , P_SCD , 8 , 32, 21040 0xfc007f00, 0xa4007900, 0 , 0, 21041 0x0 }, /* P.SCD */ 21042 }; 21043 21044 21045 static const Pool P_PREFE[2] = { 21046 { instruction , 0 , 0 , 32, 21047 0xffe07f00, 0xa7e01a00, &SYNCIE , 0, 21048 CP0_ | EVA_ }, /* SYNCIE */ 21049 { instruction , 0 , 0 , 32, 21050 0xfc007f00, 0xa4001a00, &PREFE , &PREFE_cond , 21051 CP0_ | EVA_ }, /* PREFE */ 21052 }; 21053 21054 21055 static const Pool P_LLE[4] = { 21056 { instruction , 0 , 0 , 32, 21057 0xfc007f03, 0xa4005200, &LLE , 0, 21058 CP0_ | EVA_ }, /* LLE */ 21059 { instruction , 0 , 0 , 32, 21060 0xfc007f03, 0xa4005201, &LLWPE , 0, 21061 CP0_ | EVA_ }, /* LLWPE */ 21062 { reserved_block , 0 , 0 , 32, 21063 0xfc007f03, 0xa4005202, 0 , 0, 21064 0x0 }, /* P.LLE~*(2) */ 21065 { reserved_block , 0 , 0 , 32, 21066 0xfc007f03, 0xa4005203, 0 , 0, 21067 0x0 }, /* P.LLE~*(3) */ 21068 }; 21069 21070 21071 static const Pool P_SCE[4] = { 21072 { instruction , 0 , 0 , 32, 21073 0xfc007f03, 0xa4005a00, &SCE , 0, 21074 CP0_ | EVA_ }, /* SCE */ 21075 { instruction , 0 , 0 , 32, 21076 0xfc007f03, 0xa4005a01, &SCWPE , 0, 21077 CP0_ | EVA_ }, /* SCWPE */ 21078 { reserved_block , 0 , 0 , 32, 21079 0xfc007f03, 0xa4005a02, 0 , 0, 21080 0x0 }, /* P.SCE~*(2) */ 21081 { reserved_block , 0 , 0 , 32, 21082 0xfc007f03, 0xa4005a03, 0 , 0, 21083 0x0 }, /* P.SCE~*(3) */ 21084 }; 21085 21086 21087 static const Pool P_LS_E0[16] = { 21088 { instruction , 0 , 0 , 32, 21089 0xfc007f00, 0xa4000200, &LBE , 0, 21090 CP0_ | EVA_ }, /* LBE */ 21091 { instruction , 0 , 0 , 32, 21092 0xfc007f00, 0xa4000a00, &SBE , 0, 21093 CP0_ | EVA_ }, /* SBE */ 21094 { instruction , 0 , 0 , 32, 21095 0xfc007f00, 0xa4001200, &LBUE , 0, 21096 CP0_ | EVA_ }, /* LBUE */ 21097 { pool , P_PREFE , 2 , 32, 21098 0xfc007f00, 0xa4001a00, 0 , 0, 21099 0x0 }, /* P.PREFE */ 21100 { instruction , 0 , 0 , 32, 21101 0xfc007f00, 0xa4002200, &LHE , 0, 21102 CP0_ | EVA_ }, /* LHE */ 21103 { instruction , 0 , 0 , 32, 21104 0xfc007f00, 0xa4002a00, &SHE , 0, 21105 CP0_ | EVA_ }, /* SHE */ 21106 { instruction , 0 , 0 , 32, 21107 0xfc007f00, 0xa4003200, &LHUE , 0, 21108 CP0_ | EVA_ }, /* LHUE */ 21109 { instruction , 0 , 0 , 32, 21110 0xfc007f00, 0xa4003a00, &CACHEE , 0, 21111 CP0_ | EVA_ }, /* CACHEE */ 21112 { instruction , 0 , 0 , 32, 21113 0xfc007f00, 0xa4004200, &LWE , 0, 21114 CP0_ | EVA_ }, /* LWE */ 21115 { instruction , 0 , 0 , 32, 21116 0xfc007f00, 0xa4004a00, &SWE , 0, 21117 CP0_ | EVA_ }, /* SWE */ 21118 { pool , P_LLE , 4 , 32, 21119 0xfc007f00, 0xa4005200, 0 , 0, 21120 0x0 }, /* P.LLE */ 21121 { pool , P_SCE , 4 , 32, 21122 0xfc007f00, 0xa4005a00, 0 , 0, 21123 0x0 }, /* P.SCE */ 21124 { reserved_block , 0 , 0 , 32, 21125 0xfc007f00, 0xa4006200, 0 , 0, 21126 0x0 }, /* P.LS.E0~*(12) */ 21127 { reserved_block , 0 , 0 , 32, 21128 0xfc007f00, 0xa4006a00, 0 , 0, 21129 0x0 }, /* P.LS.E0~*(13) */ 21130 { reserved_block , 0 , 0 , 32, 21131 0xfc007f00, 0xa4007200, 0 , 0, 21132 0x0 }, /* P.LS.E0~*(14) */ 21133 { reserved_block , 0 , 0 , 32, 21134 0xfc007f00, 0xa4007a00, 0 , 0, 21135 0x0 }, /* P.LS.E0~*(15) */ 21136 }; 21137 21138 21139 static const Pool P_LS_WM[2] = { 21140 { instruction , 0 , 0 , 32, 21141 0xfc000f00, 0xa4000400, &LWM , 0, 21142 XMMS_ }, /* LWM */ 21143 { instruction , 0 , 0 , 32, 21144 0xfc000f00, 0xa4000c00, &SWM , 0, 21145 XMMS_ }, /* SWM */ 21146 }; 21147 21148 21149 static const Pool P_LS_UAWM[2] = { 21150 { instruction , 0 , 0 , 32, 21151 0xfc000f00, 0xa4000500, &UALWM , 0, 21152 XMMS_ }, /* UALWM */ 21153 { instruction , 0 , 0 , 32, 21154 0xfc000f00, 0xa4000d00, &UASWM , 0, 21155 XMMS_ }, /* UASWM */ 21156 }; 21157 21158 21159 static const Pool P_LS_DM[2] = { 21160 { instruction , 0 , 0 , 32, 21161 0xfc000f00, 0xa4000600, &LDM , 0, 21162 MIPS64_ }, /* LDM */ 21163 { instruction , 0 , 0 , 32, 21164 0xfc000f00, 0xa4000e00, &SDM , 0, 21165 MIPS64_ }, /* SDM */ 21166 }; 21167 21168 21169 static const Pool P_LS_UADM[2] = { 21170 { instruction , 0 , 0 , 32, 21171 0xfc000f00, 0xa4000700, &UALDM , 0, 21172 MIPS64_ }, /* UALDM */ 21173 { instruction , 0 , 0 , 32, 21174 0xfc000f00, 0xa4000f00, &UASDM , 0, 21175 MIPS64_ }, /* UASDM */ 21176 }; 21177 21178 21179 static const Pool P_LS_S9[8] = { 21180 { pool , P_LS_S0 , 16 , 32, 21181 0xfc000700, 0xa4000000, 0 , 0, 21182 0x0 }, /* P.LS.S0 */ 21183 { pool , P_LS_S1 , 16 , 32, 21184 0xfc000700, 0xa4000100, 0 , 0, 21185 0x0 }, /* P.LS.S1 */ 21186 { pool , P_LS_E0 , 16 , 32, 21187 0xfc000700, 0xa4000200, 0 , 0, 21188 0x0 }, /* P.LS.E0 */ 21189 { reserved_block , 0 , 0 , 32, 21190 0xfc000700, 0xa4000300, 0 , 0, 21191 0x0 }, /* P.LS.S9~*(3) */ 21192 { pool , P_LS_WM , 2 , 32, 21193 0xfc000700, 0xa4000400, 0 , 0, 21194 0x0 }, /* P.LS.WM */ 21195 { pool , P_LS_UAWM , 2 , 32, 21196 0xfc000700, 0xa4000500, 0 , 0, 21197 0x0 }, /* P.LS.UAWM */ 21198 { pool , P_LS_DM , 2 , 32, 21199 0xfc000700, 0xa4000600, 0 , 0, 21200 0x0 }, /* P.LS.DM */ 21201 { pool , P_LS_UADM , 2 , 32, 21202 0xfc000700, 0xa4000700, 0 , 0, 21203 0x0 }, /* P.LS.UADM */ 21204 }; 21205 21206 21207 static const Pool P_BAL[2] = { 21208 { branch_instruction , 0 , 0 , 32, 21209 0xfe000000, 0x28000000, &BC_32_ , 0, 21210 0x0 }, /* BC[32] */ 21211 { call_instruction , 0 , 0 , 32, 21212 0xfe000000, 0x2a000000, &BALC_32_ , 0, 21213 0x0 }, /* BALC[32] */ 21214 }; 21215 21216 21217 static const Pool P_BALRSC[2] = { 21218 { branch_instruction , 0 , 0 , 32, 21219 0xffe0f000, 0x48008000, &BRSC , 0, 21220 0x0 }, /* BRSC */ 21221 { call_instruction , 0 , 0 , 32, 21222 0xfc00f000, 0x48008000, &BALRSC , &BALRSC_cond , 21223 0x0 }, /* BALRSC */ 21224 }; 21225 21226 21227 static const Pool P_J[16] = { 21228 { call_instruction , 0 , 0 , 32, 21229 0xfc00f000, 0x48000000, &JALRC_32_ , 0, 21230 0x0 }, /* JALRC[32] */ 21231 { call_instruction , 0 , 0 , 32, 21232 0xfc00f000, 0x48001000, &JALRC_HB , 0, 21233 0x0 }, /* JALRC.HB */ 21234 { reserved_block , 0 , 0 , 32, 21235 0xfc00f000, 0x48002000, 0 , 0, 21236 0x0 }, /* P.J~*(2) */ 21237 { reserved_block , 0 , 0 , 32, 21238 0xfc00f000, 0x48003000, 0 , 0, 21239 0x0 }, /* P.J~*(3) */ 21240 { reserved_block , 0 , 0 , 32, 21241 0xfc00f000, 0x48004000, 0 , 0, 21242 0x0 }, /* P.J~*(4) */ 21243 { reserved_block , 0 , 0 , 32, 21244 0xfc00f000, 0x48005000, 0 , 0, 21245 0x0 }, /* P.J~*(5) */ 21246 { reserved_block , 0 , 0 , 32, 21247 0xfc00f000, 0x48006000, 0 , 0, 21248 0x0 }, /* P.J~*(6) */ 21249 { reserved_block , 0 , 0 , 32, 21250 0xfc00f000, 0x48007000, 0 , 0, 21251 0x0 }, /* P.J~*(7) */ 21252 { pool , P_BALRSC , 2 , 32, 21253 0xfc00f000, 0x48008000, 0 , 0, 21254 0x0 }, /* P.BALRSC */ 21255 { reserved_block , 0 , 0 , 32, 21256 0xfc00f000, 0x48009000, 0 , 0, 21257 0x0 }, /* P.J~*(9) */ 21258 { reserved_block , 0 , 0 , 32, 21259 0xfc00f000, 0x4800a000, 0 , 0, 21260 0x0 }, /* P.J~*(10) */ 21261 { reserved_block , 0 , 0 , 32, 21262 0xfc00f000, 0x4800b000, 0 , 0, 21263 0x0 }, /* P.J~*(11) */ 21264 { reserved_block , 0 , 0 , 32, 21265 0xfc00f000, 0x4800c000, 0 , 0, 21266 0x0 }, /* P.J~*(12) */ 21267 { reserved_block , 0 , 0 , 32, 21268 0xfc00f000, 0x4800d000, 0 , 0, 21269 0x0 }, /* P.J~*(13) */ 21270 { reserved_block , 0 , 0 , 32, 21271 0xfc00f000, 0x4800e000, 0 , 0, 21272 0x0 }, /* P.J~*(14) */ 21273 { reserved_block , 0 , 0 , 32, 21274 0xfc00f000, 0x4800f000, 0 , 0, 21275 0x0 }, /* P.J~*(15) */ 21276 }; 21277 21278 21279 static const Pool P_BR3A[32] = { 21280 { branch_instruction , 0 , 0 , 32, 21281 0xfc1fc000, 0x88004000, &BC1EQZC , 0, 21282 CP1_ }, /* BC1EQZC */ 21283 { branch_instruction , 0 , 0 , 32, 21284 0xfc1fc000, 0x88014000, &BC1NEZC , 0, 21285 CP1_ }, /* BC1NEZC */ 21286 { branch_instruction , 0 , 0 , 32, 21287 0xfc1fc000, 0x88024000, &BC2EQZC , 0, 21288 CP2_ }, /* BC2EQZC */ 21289 { branch_instruction , 0 , 0 , 32, 21290 0xfc1fc000, 0x88034000, &BC2NEZC , 0, 21291 CP2_ }, /* BC2NEZC */ 21292 { branch_instruction , 0 , 0 , 32, 21293 0xfc1fc000, 0x88044000, &BPOSGE32C , 0, 21294 DSP_ }, /* BPOSGE32C */ 21295 { reserved_block , 0 , 0 , 32, 21296 0xfc1fc000, 0x88054000, 0 , 0, 21297 0x0 }, /* P.BR3A~*(5) */ 21298 { reserved_block , 0 , 0 , 32, 21299 0xfc1fc000, 0x88064000, 0 , 0, 21300 0x0 }, /* P.BR3A~*(6) */ 21301 { reserved_block , 0 , 0 , 32, 21302 0xfc1fc000, 0x88074000, 0 , 0, 21303 0x0 }, /* P.BR3A~*(7) */ 21304 { reserved_block , 0 , 0 , 32, 21305 0xfc1fc000, 0x88084000, 0 , 0, 21306 0x0 }, /* P.BR3A~*(8) */ 21307 { reserved_block , 0 , 0 , 32, 21308 0xfc1fc000, 0x88094000, 0 , 0, 21309 0x0 }, /* P.BR3A~*(9) */ 21310 { reserved_block , 0 , 0 , 32, 21311 0xfc1fc000, 0x880a4000, 0 , 0, 21312 0x0 }, /* P.BR3A~*(10) */ 21313 { reserved_block , 0 , 0 , 32, 21314 0xfc1fc000, 0x880b4000, 0 , 0, 21315 0x0 }, /* P.BR3A~*(11) */ 21316 { reserved_block , 0 , 0 , 32, 21317 0xfc1fc000, 0x880c4000, 0 , 0, 21318 0x0 }, /* P.BR3A~*(12) */ 21319 { reserved_block , 0 , 0 , 32, 21320 0xfc1fc000, 0x880d4000, 0 , 0, 21321 0x0 }, /* P.BR3A~*(13) */ 21322 { reserved_block , 0 , 0 , 32, 21323 0xfc1fc000, 0x880e4000, 0 , 0, 21324 0x0 }, /* P.BR3A~*(14) */ 21325 { reserved_block , 0 , 0 , 32, 21326 0xfc1fc000, 0x880f4000, 0 , 0, 21327 0x0 }, /* P.BR3A~*(15) */ 21328 { reserved_block , 0 , 0 , 32, 21329 0xfc1fc000, 0x88104000, 0 , 0, 21330 0x0 }, /* P.BR3A~*(16) */ 21331 { reserved_block , 0 , 0 , 32, 21332 0xfc1fc000, 0x88114000, 0 , 0, 21333 0x0 }, /* P.BR3A~*(17) */ 21334 { reserved_block , 0 , 0 , 32, 21335 0xfc1fc000, 0x88124000, 0 , 0, 21336 0x0 }, /* P.BR3A~*(18) */ 21337 { reserved_block , 0 , 0 , 32, 21338 0xfc1fc000, 0x88134000, 0 , 0, 21339 0x0 }, /* P.BR3A~*(19) */ 21340 { reserved_block , 0 , 0 , 32, 21341 0xfc1fc000, 0x88144000, 0 , 0, 21342 0x0 }, /* P.BR3A~*(20) */ 21343 { reserved_block , 0 , 0 , 32, 21344 0xfc1fc000, 0x88154000, 0 , 0, 21345 0x0 }, /* P.BR3A~*(21) */ 21346 { reserved_block , 0 , 0 , 32, 21347 0xfc1fc000, 0x88164000, 0 , 0, 21348 0x0 }, /* P.BR3A~*(22) */ 21349 { reserved_block , 0 , 0 , 32, 21350 0xfc1fc000, 0x88174000, 0 , 0, 21351 0x0 }, /* P.BR3A~*(23) */ 21352 { reserved_block , 0 , 0 , 32, 21353 0xfc1fc000, 0x88184000, 0 , 0, 21354 0x0 }, /* P.BR3A~*(24) */ 21355 { reserved_block , 0 , 0 , 32, 21356 0xfc1fc000, 0x88194000, 0 , 0, 21357 0x0 }, /* P.BR3A~*(25) */ 21358 { reserved_block , 0 , 0 , 32, 21359 0xfc1fc000, 0x881a4000, 0 , 0, 21360 0x0 }, /* P.BR3A~*(26) */ 21361 { reserved_block , 0 , 0 , 32, 21362 0xfc1fc000, 0x881b4000, 0 , 0, 21363 0x0 }, /* P.BR3A~*(27) */ 21364 { reserved_block , 0 , 0 , 32, 21365 0xfc1fc000, 0x881c4000, 0 , 0, 21366 0x0 }, /* P.BR3A~*(28) */ 21367 { reserved_block , 0 , 0 , 32, 21368 0xfc1fc000, 0x881d4000, 0 , 0, 21369 0x0 }, /* P.BR3A~*(29) */ 21370 { reserved_block , 0 , 0 , 32, 21371 0xfc1fc000, 0x881e4000, 0 , 0, 21372 0x0 }, /* P.BR3A~*(30) */ 21373 { reserved_block , 0 , 0 , 32, 21374 0xfc1fc000, 0x881f4000, 0 , 0, 21375 0x0 }, /* P.BR3A~*(31) */ 21376 }; 21377 21378 21379 static const Pool P_BR1[4] = { 21380 { branch_instruction , 0 , 0 , 32, 21381 0xfc00c000, 0x88000000, &BEQC_32_ , 0, 21382 0x0 }, /* BEQC[32] */ 21383 { pool , P_BR3A , 32 , 32, 21384 0xfc00c000, 0x88004000, 0 , 0, 21385 0x0 }, /* P.BR3A */ 21386 { branch_instruction , 0 , 0 , 32, 21387 0xfc00c000, 0x88008000, &BGEC , 0, 21388 0x0 }, /* BGEC */ 21389 { branch_instruction , 0 , 0 , 32, 21390 0xfc00c000, 0x8800c000, &BGEUC , 0, 21391 0x0 }, /* BGEUC */ 21392 }; 21393 21394 21395 static const Pool P_BR2[4] = { 21396 { branch_instruction , 0 , 0 , 32, 21397 0xfc00c000, 0xa8000000, &BNEC_32_ , 0, 21398 0x0 }, /* BNEC[32] */ 21399 { reserved_block , 0 , 0 , 32, 21400 0xfc00c000, 0xa8004000, 0 , 0, 21401 0x0 }, /* P.BR2~*(1) */ 21402 { branch_instruction , 0 , 0 , 32, 21403 0xfc00c000, 0xa8008000, &BLTC , 0, 21404 0x0 }, /* BLTC */ 21405 { branch_instruction , 0 , 0 , 32, 21406 0xfc00c000, 0xa800c000, &BLTUC , 0, 21407 0x0 }, /* BLTUC */ 21408 }; 21409 21410 21411 static const Pool P_BRI[8] = { 21412 { branch_instruction , 0 , 0 , 32, 21413 0xfc1c0000, 0xc8000000, &BEQIC , 0, 21414 0x0 }, /* BEQIC */ 21415 { branch_instruction , 0 , 0 , 32, 21416 0xfc1c0000, 0xc8040000, &BBEQZC , 0, 21417 XMMS_ }, /* BBEQZC */ 21418 { branch_instruction , 0 , 0 , 32, 21419 0xfc1c0000, 0xc8080000, &BGEIC , 0, 21420 0x0 }, /* BGEIC */ 21421 { branch_instruction , 0 , 0 , 32, 21422 0xfc1c0000, 0xc80c0000, &BGEIUC , 0, 21423 0x0 }, /* BGEIUC */ 21424 { branch_instruction , 0 , 0 , 32, 21425 0xfc1c0000, 0xc8100000, &BNEIC , 0, 21426 0x0 }, /* BNEIC */ 21427 { branch_instruction , 0 , 0 , 32, 21428 0xfc1c0000, 0xc8140000, &BBNEZC , 0, 21429 XMMS_ }, /* BBNEZC */ 21430 { branch_instruction , 0 , 0 , 32, 21431 0xfc1c0000, 0xc8180000, &BLTIC , 0, 21432 0x0 }, /* BLTIC */ 21433 { branch_instruction , 0 , 0 , 32, 21434 0xfc1c0000, 0xc81c0000, &BLTIUC , 0, 21435 0x0 }, /* BLTIUC */ 21436 }; 21437 21438 21439 static const Pool P32[32] = { 21440 { pool , P_ADDIU , 2 , 32, 21441 0xfc000000, 0x00000000, 0 , 0, 21442 0x0 }, /* P.ADDIU */ 21443 { pool , P32A , 8 , 32, 21444 0xfc000000, 0x20000000, 0 , 0, 21445 0x0 }, /* P32A */ 21446 { pool , P_GP_W , 4 , 32, 21447 0xfc000000, 0x40000000, 0 , 0, 21448 0x0 }, /* P.GP.W */ 21449 { pool , POOL48I , 32 , 48, 21450 0xfc0000000000ull, 0x600000000000ull, 0 , 0, 21451 0x0 }, /* POOL48I */ 21452 { pool , P_U12 , 16 , 32, 21453 0xfc000000, 0x80000000, 0 , 0, 21454 0x0 }, /* P.U12 */ 21455 { pool , POOL32F , 8 , 32, 21456 0xfc000000, 0xa0000000, 0 , 0, 21457 CP1_ }, /* POOL32F */ 21458 { pool , POOL32S , 8 , 32, 21459 0xfc000000, 0xc0000000, 0 , 0, 21460 0x0 }, /* POOL32S */ 21461 { pool , P_LUI , 2 , 32, 21462 0xfc000000, 0xe0000000, 0 , 0, 21463 0x0 }, /* P.LUI */ 21464 { instruction , 0 , 0 , 32, 21465 0xfc000000, 0x04000000, &ADDIUPC_32_ , 0, 21466 0x0 }, /* ADDIUPC[32] */ 21467 { reserved_block , 0 , 0 , 32, 21468 0xfc000000, 0x24000000, 0 , 0, 21469 0x0 }, /* P32~*(5) */ 21470 { pool , P_GP_BH , 8 , 32, 21471 0xfc000000, 0x44000000, 0 , 0, 21472 0x0 }, /* P.GP.BH */ 21473 { reserved_block , 0 , 0 , 32, 21474 0xfc000000, 0x64000000, 0 , 0, 21475 0x0 }, /* P32~*(13) */ 21476 { pool , P_LS_U12 , 16 , 32, 21477 0xfc000000, 0x84000000, 0 , 0, 21478 0x0 }, /* P.LS.U12 */ 21479 { pool , P_LS_S9 , 8 , 32, 21480 0xfc000000, 0xa4000000, 0 , 0, 21481 0x0 }, /* P.LS.S9 */ 21482 { reserved_block , 0 , 0 , 32, 21483 0xfc000000, 0xc4000000, 0 , 0, 21484 0x0 }, /* P32~*(25) */ 21485 { reserved_block , 0 , 0 , 32, 21486 0xfc000000, 0xe4000000, 0 , 0, 21487 0x0 }, /* P32~*(29) */ 21488 { call_instruction , 0 , 0 , 32, 21489 0xfc000000, 0x08000000, &MOVE_BALC , 0, 21490 XMMS_ }, /* MOVE.BALC */ 21491 { pool , P_BAL , 2 , 32, 21492 0xfc000000, 0x28000000, 0 , 0, 21493 0x0 }, /* P.BAL */ 21494 { pool , P_J , 16 , 32, 21495 0xfc000000, 0x48000000, 0 , 0, 21496 0x0 }, /* P.J */ 21497 { reserved_block , 0 , 0 , 32, 21498 0xfc000000, 0x68000000, 0 , 0, 21499 0x0 }, /* P32~*(14) */ 21500 { pool , P_BR1 , 4 , 32, 21501 0xfc000000, 0x88000000, 0 , 0, 21502 0x0 }, /* P.BR1 */ 21503 { pool , P_BR2 , 4 , 32, 21504 0xfc000000, 0xa8000000, 0 , 0, 21505 0x0 }, /* P.BR2 */ 21506 { pool , P_BRI , 8 , 32, 21507 0xfc000000, 0xc8000000, 0 , 0, 21508 0x0 }, /* P.BRI */ 21509 { reserved_block , 0 , 0 , 32, 21510 0xfc000000, 0xe8000000, 0 , 0, 21511 0x0 }, /* P32~*(30) */ 21512 { reserved_block , 0 , 0 , 32, 21513 0xfc000000, 0x0c000000, 0 , 0, 21514 0x0 }, /* P32~*(3) */ 21515 { reserved_block , 0 , 0 , 32, 21516 0xfc000000, 0x2c000000, 0 , 0, 21517 0x0 }, /* P32~*(7) */ 21518 { reserved_block , 0 , 0 , 32, 21519 0xfc000000, 0x4c000000, 0 , 0, 21520 0x0 }, /* P32~*(11) */ 21521 { reserved_block , 0 , 0 , 32, 21522 0xfc000000, 0x6c000000, 0 , 0, 21523 0x0 }, /* P32~*(15) */ 21524 { reserved_block , 0 , 0 , 32, 21525 0xfc000000, 0x8c000000, 0 , 0, 21526 0x0 }, /* P32~*(19) */ 21527 { reserved_block , 0 , 0 , 32, 21528 0xfc000000, 0xac000000, 0 , 0, 21529 0x0 }, /* P32~*(23) */ 21530 { reserved_block , 0 , 0 , 32, 21531 0xfc000000, 0xcc000000, 0 , 0, 21532 0x0 }, /* P32~*(27) */ 21533 { reserved_block , 0 , 0 , 32, 21534 0xfc000000, 0xec000000, 0 , 0, 21535 0x0 }, /* P32~*(31) */ 21536 }; 21537 21538 21539 static const Pool P16_SYSCALL[2] = { 21540 { instruction , 0 , 0 , 16, 21541 0xfffc , 0x1008 , &SYSCALL_16_ , 0, 21542 0x0 }, /* SYSCALL[16] */ 21543 { instruction , 0 , 0 , 16, 21544 0xfffc , 0x100c , &HYPCALL_16_ , 0, 21545 CP0_ | VZ_ }, /* HYPCALL[16] */ 21546 }; 21547 21548 21549 static const Pool P16_RI[4] = { 21550 { reserved_block , 0 , 0 , 16, 21551 0xfff8 , 0x1000 , 0 , 0, 21552 0x0 }, /* P16.RI~*(0) */ 21553 { pool , P16_SYSCALL , 2 , 16, 21554 0xfff8 , 0x1008 , 0 , 0, 21555 0x0 }, /* P16.SYSCALL */ 21556 { instruction , 0 , 0 , 16, 21557 0xfff8 , 0x1010 , &BREAK_16_ , 0, 21558 0x0 }, /* BREAK[16] */ 21559 { instruction , 0 , 0 , 16, 21560 0xfff8 , 0x1018 , &SDBBP_16_ , 0, 21561 EJTAG_ }, /* SDBBP[16] */ 21562 }; 21563 21564 21565 static const Pool P16_MV[2] = { 21566 { pool , P16_RI , 4 , 16, 21567 0xffe0 , 0x1000 , 0 , 0, 21568 0x0 }, /* P16.RI */ 21569 { instruction , 0 , 0 , 16, 21570 0xfc00 , 0x1000 , &MOVE , &MOVE_cond , 21571 0x0 }, /* MOVE */ 21572 }; 21573 21574 21575 static const Pool P16_SHIFT[2] = { 21576 { instruction , 0 , 0 , 16, 21577 0xfc08 , 0x3000 , &SLL_16_ , 0, 21578 0x0 }, /* SLL[16] */ 21579 { instruction , 0 , 0 , 16, 21580 0xfc08 , 0x3008 , &SRL_16_ , 0, 21581 0x0 }, /* SRL[16] */ 21582 }; 21583 21584 21585 static const Pool POOL16C_00[4] = { 21586 { instruction , 0 , 0 , 16, 21587 0xfc0f , 0x5000 , &NOT_16_ , 0, 21588 0x0 }, /* NOT[16] */ 21589 { instruction , 0 , 0 , 16, 21590 0xfc0f , 0x5004 , &XOR_16_ , 0, 21591 0x0 }, /* XOR[16] */ 21592 { instruction , 0 , 0 , 16, 21593 0xfc0f , 0x5008 , &AND_16_ , 0, 21594 0x0 }, /* AND[16] */ 21595 { instruction , 0 , 0 , 16, 21596 0xfc0f , 0x500c , &OR_16_ , 0, 21597 0x0 }, /* OR[16] */ 21598 }; 21599 21600 21601 static const Pool POOL16C_0[2] = { 21602 { pool , POOL16C_00 , 4 , 16, 21603 0xfc03 , 0x5000 , 0 , 0, 21604 0x0 }, /* POOL16C_00 */ 21605 { reserved_block , 0 , 0 , 16, 21606 0xfc03 , 0x5002 , 0 , 0, 21607 0x0 }, /* POOL16C_0~*(1) */ 21608 }; 21609 21610 21611 static const Pool P16C[2] = { 21612 { pool , POOL16C_0 , 2 , 16, 21613 0xfc01 , 0x5000 , 0 , 0, 21614 0x0 }, /* POOL16C_0 */ 21615 { instruction , 0 , 0 , 16, 21616 0xfc01 , 0x5001 , &LWXS_16_ , 0, 21617 0x0 }, /* LWXS[16] */ 21618 }; 21619 21620 21621 static const Pool P16_A1[2] = { 21622 { reserved_block , 0 , 0 , 16, 21623 0xfc40 , 0x7000 , 0 , 0, 21624 0x0 }, /* P16.A1~*(0) */ 21625 { instruction , 0 , 0 , 16, 21626 0xfc40 , 0x7040 , &ADDIU_R1_SP_ , 0, 21627 0x0 }, /* ADDIU[R1.SP] */ 21628 }; 21629 21630 21631 static const Pool P_ADDIU_RS5_[2] = { 21632 { instruction , 0 , 0 , 16, 21633 0xffe8 , 0x9008 , &NOP_16_ , 0, 21634 0x0 }, /* NOP[16] */ 21635 { instruction , 0 , 0 , 16, 21636 0xfc08 , 0x9008 , &ADDIU_RS5_ , &ADDIU_RS5__cond , 21637 0x0 }, /* ADDIU[RS5] */ 21638 }; 21639 21640 21641 static const Pool P16_A2[2] = { 21642 { instruction , 0 , 0 , 16, 21643 0xfc08 , 0x9000 , &ADDIU_R2_ , 0, 21644 0x0 }, /* ADDIU[R2] */ 21645 { pool , P_ADDIU_RS5_ , 2 , 16, 21646 0xfc08 , 0x9008 , 0 , 0, 21647 0x0 }, /* P.ADDIU[RS5] */ 21648 }; 21649 21650 21651 static const Pool P16_ADDU[2] = { 21652 { instruction , 0 , 0 , 16, 21653 0xfc01 , 0xb000 , &ADDU_16_ , 0, 21654 0x0 }, /* ADDU[16] */ 21655 { instruction , 0 , 0 , 16, 21656 0xfc01 , 0xb001 , &SUBU_16_ , 0, 21657 0x0 }, /* SUBU[16] */ 21658 }; 21659 21660 21661 static const Pool P16_JRC[2] = { 21662 { branch_instruction , 0 , 0 , 16, 21663 0xfc1f , 0xd800 , &JRC , 0, 21664 0x0 }, /* JRC */ 21665 { call_instruction , 0 , 0 , 16, 21666 0xfc1f , 0xd810 , &JALRC_16_ , 0, 21667 0x0 }, /* JALRC[16] */ 21668 }; 21669 21670 21671 static const Pool P16_BR1[2] = { 21672 { branch_instruction , 0 , 0 , 16, 21673 0xfc00 , 0xd800 , &BEQC_16_ , &BEQC_16__cond , 21674 XMMS_ }, /* BEQC[16] */ 21675 { branch_instruction , 0 , 0 , 16, 21676 0xfc00 , 0xd800 , &BNEC_16_ , &BNEC_16__cond , 21677 XMMS_ }, /* BNEC[16] */ 21678 }; 21679 21680 21681 static const Pool P16_BR[2] = { 21682 { pool , P16_JRC , 2 , 16, 21683 0xfc0f , 0xd800 , 0 , 0, 21684 0x0 }, /* P16.JRC */ 21685 { pool , P16_BR1 , 2 , 16, 21686 0xfc00 , 0xd800 , 0 , &P16_BR1_cond , 21687 0x0 }, /* P16.BR1 */ 21688 }; 21689 21690 21691 static const Pool P16_SR[2] = { 21692 { instruction , 0 , 0 , 16, 21693 0xfd00 , 0x1c00 , &SAVE_16_ , 0, 21694 0x0 }, /* SAVE[16] */ 21695 { return_instruction , 0 , 0 , 16, 21696 0xfd00 , 0x1d00 , &RESTORE_JRC_16_ , 0, 21697 0x0 }, /* RESTORE.JRC[16] */ 21698 }; 21699 21700 21701 static const Pool P16_4X4[4] = { 21702 { instruction , 0 , 0 , 16, 21703 0xfd08 , 0x3c00 , &ADDU_4X4_ , 0, 21704 XMMS_ }, /* ADDU[4X4] */ 21705 { instruction , 0 , 0 , 16, 21706 0xfd08 , 0x3c08 , &MUL_4X4_ , 0, 21707 XMMS_ }, /* MUL[4X4] */ 21708 { reserved_block , 0 , 0 , 16, 21709 0xfd08 , 0x3d00 , 0 , 0, 21710 0x0 }, /* P16.4X4~*(2) */ 21711 { reserved_block , 0 , 0 , 16, 21712 0xfd08 , 0x3d08 , 0 , 0, 21713 0x0 }, /* P16.4X4~*(3) */ 21714 }; 21715 21716 21717 static const Pool P16_LB[4] = { 21718 { instruction , 0 , 0 , 16, 21719 0xfc0c , 0x5c00 , &LB_16_ , 0, 21720 0x0 }, /* LB[16] */ 21721 { instruction , 0 , 0 , 16, 21722 0xfc0c , 0x5c04 , &SB_16_ , 0, 21723 0x0 }, /* SB[16] */ 21724 { instruction , 0 , 0 , 16, 21725 0xfc0c , 0x5c08 , &LBU_16_ , 0, 21726 0x0 }, /* LBU[16] */ 21727 { reserved_block , 0 , 0 , 16, 21728 0xfc0c , 0x5c0c , 0 , 0, 21729 0x0 }, /* P16.LB~*(3) */ 21730 }; 21731 21732 21733 static const Pool P16_LH[4] = { 21734 { instruction , 0 , 0 , 16, 21735 0xfc09 , 0x7c00 , &LH_16_ , 0, 21736 0x0 }, /* LH[16] */ 21737 { instruction , 0 , 0 , 16, 21738 0xfc09 , 0x7c01 , &SH_16_ , 0, 21739 0x0 }, /* SH[16] */ 21740 { instruction , 0 , 0 , 16, 21741 0xfc09 , 0x7c08 , &LHU_16_ , 0, 21742 0x0 }, /* LHU[16] */ 21743 { reserved_block , 0 , 0 , 16, 21744 0xfc09 , 0x7c09 , 0 , 0, 21745 0x0 }, /* P16.LH~*(3) */ 21746 }; 21747 21748 21749 static const Pool P16[32] = { 21750 { pool , P16_MV , 2 , 16, 21751 0xfc00 , 0x1000 , 0 , 0, 21752 0x0 }, /* P16.MV */ 21753 { pool , P16_SHIFT , 2 , 16, 21754 0xfc00 , 0x3000 , 0 , 0, 21755 0x0 }, /* P16.SHIFT */ 21756 { pool , P16C , 2 , 16, 21757 0xfc00 , 0x5000 , 0 , 0, 21758 0x0 }, /* P16C */ 21759 { pool , P16_A1 , 2 , 16, 21760 0xfc00 , 0x7000 , 0 , 0, 21761 0x0 }, /* P16.A1 */ 21762 { pool , P16_A2 , 2 , 16, 21763 0xfc00 , 0x9000 , 0 , 0, 21764 0x0 }, /* P16.A2 */ 21765 { pool , P16_ADDU , 2 , 16, 21766 0xfc00 , 0xb000 , 0 , 0, 21767 0x0 }, /* P16.ADDU */ 21768 { instruction , 0 , 0 , 16, 21769 0xfc00 , 0xd000 , &LI_16_ , 0, 21770 0x0 }, /* LI[16] */ 21771 { instruction , 0 , 0 , 16, 21772 0xfc00 , 0xf000 , &ANDI_16_ , 0, 21773 0x0 }, /* ANDI[16] */ 21774 { instruction , 0 , 0 , 16, 21775 0xfc00 , 0x1400 , &LW_16_ , 0, 21776 0x0 }, /* LW[16] */ 21777 { instruction , 0 , 0 , 16, 21778 0xfc00 , 0x3400 , &LW_SP_ , 0, 21779 0x0 }, /* LW[SP] */ 21780 { instruction , 0 , 0 , 16, 21781 0xfc00 , 0x5400 , &LW_GP16_ , 0, 21782 0x0 }, /* LW[GP16] */ 21783 { instruction , 0 , 0 , 16, 21784 0xfc00 , 0x7400 , &LW_4X4_ , 0, 21785 XMMS_ }, /* LW[4X4] */ 21786 { instruction , 0 , 0 , 16, 21787 0xfc00 , 0x9400 , &SW_16_ , 0, 21788 0x0 }, /* SW[16] */ 21789 { instruction , 0 , 0 , 16, 21790 0xfc00 , 0xb400 , &SW_SP_ , 0, 21791 0x0 }, /* SW[SP] */ 21792 { instruction , 0 , 0 , 16, 21793 0xfc00 , 0xd400 , &SW_GP16_ , 0, 21794 0x0 }, /* SW[GP16] */ 21795 { instruction , 0 , 0 , 16, 21796 0xfc00 , 0xf400 , &SW_4X4_ , 0, 21797 XMMS_ }, /* SW[4X4] */ 21798 { branch_instruction , 0 , 0 , 16, 21799 0xfc00 , 0x1800 , &BC_16_ , 0, 21800 0x0 }, /* BC[16] */ 21801 { call_instruction , 0 , 0 , 16, 21802 0xfc00 , 0x3800 , &BALC_16_ , 0, 21803 0x0 }, /* BALC[16] */ 21804 { reserved_block , 0 , 0 , 16, 21805 0xfc00 , 0x5800 , 0 , 0, 21806 0x0 }, /* P16~*(10) */ 21807 { reserved_block , 0 , 0 , 16, 21808 0xfc00 , 0x7800 , 0 , 0, 21809 0x0 }, /* P16~*(14) */ 21810 { branch_instruction , 0 , 0 , 16, 21811 0xfc00 , 0x9800 , &BEQZC_16_ , 0, 21812 0x0 }, /* BEQZC[16] */ 21813 { branch_instruction , 0 , 0 , 16, 21814 0xfc00 , 0xb800 , &BNEZC_16_ , 0, 21815 0x0 }, /* BNEZC[16] */ 21816 { pool , P16_BR , 2 , 16, 21817 0xfc00 , 0xd800 , 0 , 0, 21818 0x0 }, /* P16.BR */ 21819 { reserved_block , 0 , 0 , 16, 21820 0xfc00 , 0xf800 , 0 , 0, 21821 0x0 }, /* P16~*(30) */ 21822 { pool , P16_SR , 2 , 16, 21823 0xfc00 , 0x1c00 , 0 , 0, 21824 0x0 }, /* P16.SR */ 21825 { pool , P16_4X4 , 4 , 16, 21826 0xfc00 , 0x3c00 , 0 , 0, 21827 0x0 }, /* P16.4X4 */ 21828 { pool , P16_LB , 4 , 16, 21829 0xfc00 , 0x5c00 , 0 , 0, 21830 0x0 }, /* P16.LB */ 21831 { pool , P16_LH , 4 , 16, 21832 0xfc00 , 0x7c00 , 0 , 0, 21833 0x0 }, /* P16.LH */ 21834 { reserved_block , 0 , 0 , 16, 21835 0xfc00 , 0x9c00 , 0 , 0, 21836 0x0 }, /* P16~*(19) */ 21837 { instruction , 0 , 0 , 16, 21838 0xfc00 , 0xbc00 , &MOVEP , 0, 21839 XMMS_ }, /* MOVEP */ 21840 { reserved_block , 0 , 0 , 16, 21841 0xfc00 , 0xdc00 , 0 , 0, 21842 0x0 }, /* P16~*(27) */ 21843 { instruction , 0 , 0 , 16, 21844 0xfc00 , 0xfc00 , &MOVEP_REV_ , 0, 21845 XMMS_ }, /* MOVEP[REV] */ 21846 }; 21847 21848 21849 static const Pool MAJOR[2] = { 21850 { pool , P32 , 32 , 32, 21851 0x10000000, 0x00000000, 0 , 0, 21852 0x0 }, /* P32 */ 21853 { pool , P16 , 32 , 16, 21854 0x1000 , 0x1000 , 0 , 0, 21855 0x0 }, /* P16 */ 21856 }; 21857 21858 /* 21859 * Recurse through tables until the instruction is found then return 21860 * the string and size 21861 * 21862 * inputs: 21863 * pointer to a word stream, 21864 * disassember table and size 21865 * returns: 21866 * instruction size - negative is error 21867 * disassembly string - on error will constain error string 21868 */ 21869 static int Disassemble(const uint16 *data, char **dis, 21870 TABLE_ENTRY_TYPE *type, const Pool *table, 21871 int table_size, Dis_info *info) 21872 { 21873 for (int i = 0; i < table_size; i++) { 21874 uint64 op_code = extract_op_code_value(data, 21875 table[i].instructions_size); 21876 if ((op_code & table[i].mask) == table[i].value) { 21877 /* possible match */ 21878 conditional_function cond = table[i].condition; 21879 if ((cond == NULL) || cond(op_code)) { 21880 if (table[i].type == pool) { 21881 return Disassemble(data, dis, type, 21882 table[i].next_table, 21883 table[i].next_table_size, 21884 info); 21885 } else if ((table[i].type == instruction) || 21886 (table[i].type == call_instruction) || 21887 (table[i].type == branch_instruction) || 21888 (table[i].type == return_instruction)) { 21889 disassembly_function dis_fn = table[i].disassembly; 21890 if (dis_fn == 0) { 21891 *dis = g_strdup( 21892 "disassembler failure - bad table entry"); 21893 return -6; 21894 } 21895 *type = table[i].type; 21896 *dis = dis_fn(op_code, info); 21897 return table[i].instructions_size; 21898 } else { 21899 *dis = g_strdup("reserved instruction"); 21900 return -2; 21901 } 21902 } 21903 } 21904 } 21905 *dis = g_strdup("failed to disassemble"); 21906 return -1; /* failed to disassemble */ 21907 } 21908 21909 21910 static bool nanomips_dis(const uint16_t *data, char **buf, Dis_info *info) 21911 { 21912 TABLE_ENTRY_TYPE type; 21913 21914 /* Handle runtime errors. */ 21915 if (unlikely(sigsetjmp(info->buf, 0) != 0)) { 21916 return false; 21917 } 21918 return Disassemble(data, buf, &type, MAJOR, ARRAY_SIZE(MAJOR), info) >= 0; 21919 } 21920 21921 static bool read_u16(uint16_t *ret, bfd_vma memaddr, 21922 struct disassemble_info *info) 21923 { 21924 int status = (*info->read_memory_func)(memaddr, (bfd_byte *)ret, 2, info); 21925 if (status != 0) { 21926 (*info->memory_error_func)(status, memaddr, info); 21927 return false; 21928 } 21929 21930 if ((info->endian == BFD_ENDIAN_BIG) != HOST_BIG_ENDIAN) { 21931 bswap16s(ret); 21932 } 21933 return true; 21934 } 21935 21936 int print_insn_nanomips(bfd_vma memaddr, struct disassemble_info *info) 21937 { 21938 int length; 21939 uint16_t words[3] = { }; 21940 g_autofree char *buf = NULL; 21941 21942 info->bytes_per_chunk = 2; 21943 info->display_endian = info->endian; 21944 info->insn_info_valid = 1; 21945 info->branch_delay_insns = 0; 21946 info->data_size = 0; 21947 info->insn_type = dis_nonbranch; 21948 info->target = 0; 21949 info->target2 = 0; 21950 21951 Dis_info disassm_info; 21952 disassm_info.m_pc = memaddr; 21953 disassm_info.fprintf_func = info->fprintf_func; 21954 disassm_info.stream = info->stream; 21955 21956 if (!read_u16(&words[0], memaddr, info)) { 21957 return -1; 21958 } 21959 length = 2; 21960 21961 /* Handle 32-bit opcodes. */ 21962 if ((words[0] & 0x1000) == 0) { 21963 if (!read_u16(&words[1], memaddr + 2, info)) { 21964 return -1; 21965 } 21966 length = 4; 21967 21968 /* Handle 48-bit opcodes. */ 21969 if ((words[0] >> 10) == 0x18) { 21970 if (!read_u16(&words[1], memaddr + 4, info)) { 21971 return -1; 21972 } 21973 length = 6; 21974 } 21975 } 21976 21977 for (int i = 0; i < ARRAY_SIZE(words); i++) { 21978 if (i * 2 < length) { 21979 (*info->fprintf_func)(info->stream, "%04x ", words[i]); 21980 } else { 21981 (*info->fprintf_func)(info->stream, " "); 21982 } 21983 } 21984 21985 if (nanomips_dis(words, &buf, &disassm_info)) { 21986 (*info->fprintf_func) (info->stream, "%s", buf); 21987 } 21988 21989 return length; 21990 } 21991