1 /* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003 4 Free Software Foundation, Inc. 5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). 6 7 This file is part of GDB, GAS, and the GNU binutils. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "qemu/osdep.h" 23 #include "disas/dis-asm.h" 24 25 /* mips.h. Mips opcode list for GDB, the GNU debugger. 26 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 27 Free Software Foundation, Inc. 28 Contributed by Ralph Campbell and OSF 29 Commented and modified by Ian Lance Taylor, Cygnus Support 30 31 This file is part of GDB, GAS, and the GNU binutils. 32 33 GDB, GAS, and the GNU binutils are free software; you can redistribute 34 them and/or modify them under the terms of the GNU General Public 35 License as published by the Free Software Foundation; either version 36 1, or (at your option) any later version. 37 38 GDB, GAS, and the GNU binutils are distributed in the hope that they 39 will be useful, but WITHOUT ANY WARRANTY; without even the implied 40 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 41 the GNU General Public License for more details. 42 43 You should have received a copy of the GNU General Public License 44 along with this file; see the file COPYING. If not, 45 see <http://www.gnu.org/licenses/>. */ 46 47 /* These are bit masks and shift counts to use to access the various 48 fields of an instruction. To retrieve the X field of an 49 instruction, use the expression 50 (i >> OP_SH_X) & OP_MASK_X 51 To set the same field (to j), use 52 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 53 54 Make sure you use fields that are appropriate for the instruction, 55 of course. 56 57 The 'i' format uses OP, RS, RT and IMMEDIATE. 58 59 The 'j' format uses OP and TARGET. 60 61 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 62 63 The 'b' format uses OP, RS, RT and DELTA. 64 65 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 66 67 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 68 69 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 70 breakpoint instruction are not defined; Kane says the breakpoint 71 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 72 only use ten bits). An optional two-operand form of break/sdbbp 73 allows the lower ten bits to be set too, and MIPS32 and later 74 architectures allow 20 bits to be set with a signal operand 75 (using CODE20). 76 77 The syscall instruction uses CODE20. 78 79 The general coprocessor instructions use COPZ. */ 80 81 #define OP_MASK_OP 0x3f 82 #define OP_SH_OP 26 83 #define OP_MASK_RS 0x1f 84 #define OP_SH_RS 21 85 #define OP_MASK_FR 0x1f 86 #define OP_SH_FR 21 87 #define OP_MASK_FMT 0x1f 88 #define OP_SH_FMT 21 89 #define OP_MASK_BCC 0x7 90 #define OP_SH_BCC 18 91 #define OP_MASK_CODE 0x3ff 92 #define OP_SH_CODE 16 93 #define OP_MASK_CODE2 0x3ff 94 #define OP_SH_CODE2 6 95 #define OP_MASK_RT 0x1f 96 #define OP_SH_RT 16 97 #define OP_MASK_FT 0x1f 98 #define OP_SH_FT 16 99 #define OP_MASK_CACHE 0x1f 100 #define OP_SH_CACHE 16 101 #define OP_MASK_RD 0x1f 102 #define OP_SH_RD 11 103 #define OP_MASK_FS 0x1f 104 #define OP_SH_FS 11 105 #define OP_MASK_PREFX 0x1f 106 #define OP_SH_PREFX 11 107 #define OP_MASK_CCC 0x7 108 #define OP_SH_CCC 8 109 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 110 #define OP_SH_CODE20 6 111 #define OP_MASK_SHAMT 0x1f 112 #define OP_SH_SHAMT 6 113 #define OP_MASK_FD 0x1f 114 #define OP_SH_FD 6 115 #define OP_MASK_TARGET 0x3ffffff 116 #define OP_SH_TARGET 0 117 #define OP_MASK_COPZ 0x1ffffff 118 #define OP_SH_COPZ 0 119 #define OP_MASK_IMMEDIATE 0xffff 120 #define OP_SH_IMMEDIATE 0 121 #define OP_MASK_DELTA 0xffff 122 #define OP_SH_DELTA 0 123 #define OP_MASK_DELTA_R6 0x1ff 124 #define OP_SH_DELTA_R6 7 125 #define OP_MASK_FUNCT 0x3f 126 #define OP_SH_FUNCT 0 127 #define OP_MASK_SPEC 0x3f 128 #define OP_SH_SPEC 0 129 #define OP_SH_LOCC 8 /* FP condition code. */ 130 #define OP_SH_HICC 18 /* FP condition code. */ 131 #define OP_MASK_CC 0x7 132 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 133 #define OP_MASK_COP1NORM 0x1 /* a single bit. */ 134 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 135 #define OP_MASK_COP1SPEC 0xf 136 #define OP_MASK_COP1SCLR 0x4 137 #define OP_MASK_COP1CMP 0x3 138 #define OP_SH_COP1CMP 4 139 #define OP_SH_FORMAT 21 /* FP short format field. */ 140 #define OP_MASK_FORMAT 0x7 141 #define OP_SH_TRUE 16 142 #define OP_MASK_TRUE 0x1 143 #define OP_SH_GE 17 144 #define OP_MASK_GE 0x01 145 #define OP_SH_UNSIGNED 16 146 #define OP_MASK_UNSIGNED 0x1 147 #define OP_SH_HINT 16 148 #define OP_MASK_HINT 0x1f 149 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 150 #define OP_MASK_MMI 0x3f 151 #define OP_SH_MMISUB 6 152 #define OP_MASK_MMISUB 0x1f 153 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 154 #define OP_SH_PERFREG 1 155 #define OP_SH_SEL 0 /* Coprocessor select field. */ 156 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 157 #define OP_SH_CODE19 6 /* 19 bit wait code. */ 158 #define OP_MASK_CODE19 0x7ffff 159 #define OP_SH_ALN 21 160 #define OP_MASK_ALN 0x7 161 #define OP_SH_VSEL 21 162 #define OP_MASK_VSEL 0x1f 163 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 164 but 0x8-0xf don't select bytes. */ 165 #define OP_SH_VECBYTE 22 166 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 167 #define OP_SH_VECALIGN 21 168 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 169 #define OP_SH_INSMSB 11 170 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 171 #define OP_SH_EXTMSBD 11 172 173 #define OP_OP_COP0 0x10 174 #define OP_OP_COP1 0x11 175 #define OP_OP_COP2 0x12 176 #define OP_OP_COP3 0x13 177 #define OP_OP_LWC1 0x31 178 #define OP_OP_LWC2 0x32 179 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 180 #define OP_OP_LDC1 0x35 181 #define OP_OP_LDC2 0x36 182 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 183 #define OP_OP_SWC1 0x39 184 #define OP_OP_SWC2 0x3a 185 #define OP_OP_SWC3 0x3b 186 #define OP_OP_SDC1 0x3d 187 #define OP_OP_SDC2 0x3e 188 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 189 190 /* MIPS DSP ASE */ 191 #define OP_SH_DSPACC 11 192 #define OP_MASK_DSPACC 0x3 193 #define OP_SH_DSPACC_S 21 194 #define OP_MASK_DSPACC_S 0x3 195 #define OP_SH_DSPSFT 20 196 #define OP_MASK_DSPSFT 0x3f 197 #define OP_SH_DSPSFT_7 19 198 #define OP_MASK_DSPSFT_7 0x7f 199 #define OP_SH_SA3 21 200 #define OP_MASK_SA3 0x7 201 #define OP_SH_SA4 21 202 #define OP_MASK_SA4 0xf 203 #define OP_SH_IMM8 16 204 #define OP_MASK_IMM8 0xff 205 #define OP_SH_IMM10 16 206 #define OP_MASK_IMM10 0x3ff 207 #define OP_SH_WRDSP 11 208 #define OP_MASK_WRDSP 0x3f 209 #define OP_SH_RDDSP 16 210 #define OP_MASK_RDDSP 0x3f 211 #define OP_SH_BP 11 212 #define OP_MASK_BP 0x3 213 214 /* MIPS MT ASE */ 215 #define OP_SH_MT_U 5 216 #define OP_MASK_MT_U 0x1 217 #define OP_SH_MT_H 4 218 #define OP_MASK_MT_H 0x1 219 #define OP_SH_MTACC_T 18 220 #define OP_MASK_MTACC_T 0x3 221 #define OP_SH_MTACC_D 13 222 #define OP_MASK_MTACC_D 0x3 223 224 /* MSA */ 225 #define OP_MASK_1BIT 0x1 226 #define OP_SH_1BIT 16 227 #define OP_MASK_2BIT 0x3 228 #define OP_SH_2BIT 16 229 #define OP_MASK_3BIT 0x7 230 #define OP_SH_3BIT 16 231 #define OP_MASK_4BIT 0xf 232 #define OP_SH_4BIT 16 233 #define OP_MASK_5BIT 0x1f 234 #define OP_SH_5BIT 16 235 #define OP_MASK_10BIT 0x3ff 236 #define OP_SH_10BIT 11 237 #define OP_MASK_MSACR11 0x1f 238 #define OP_SH_MSACR11 11 239 #define OP_MASK_MSACR6 0x1f 240 #define OP_SH_MSACR6 6 241 #define OP_MASK_GPR 0x1f 242 #define OP_SH_GPR 6 243 #define OP_MASK_1_TO_4 0x3 244 #define OP_SH_1_TO_4 6 245 246 #define OP_OP_COP0 0x10 247 #define OP_OP_COP1 0x11 248 #define OP_OP_COP2 0x12 249 #define OP_OP_COP3 0x13 250 #define OP_OP_LWC1 0x31 251 #define OP_OP_LWC2 0x32 252 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 253 #define OP_OP_LDC1 0x35 254 #define OP_OP_LDC2 0x36 255 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 256 #define OP_OP_SWC1 0x39 257 #define OP_OP_SWC2 0x3a 258 #define OP_OP_SWC3 0x3b 259 #define OP_OP_SDC1 0x3d 260 #define OP_OP_SDC2 0x3e 261 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 262 263 /* Values in the 'VSEL' field. */ 264 #define MDMX_FMTSEL_IMM_QH 0x1d 265 #define MDMX_FMTSEL_IMM_OB 0x1e 266 #define MDMX_FMTSEL_VEC_QH 0x15 267 #define MDMX_FMTSEL_VEC_OB 0x16 268 269 /* UDI */ 270 #define OP_SH_UDI1 6 271 #define OP_MASK_UDI1 0x1f 272 #define OP_SH_UDI2 6 273 #define OP_MASK_UDI2 0x3ff 274 #define OP_SH_UDI3 6 275 #define OP_MASK_UDI3 0x7fff 276 #define OP_SH_UDI4 6 277 #define OP_MASK_UDI4 0xfffff 278 /* This structure holds information for a particular instruction. */ 279 280 struct mips_opcode 281 { 282 /* The name of the instruction. */ 283 const char *name; 284 /* A string describing the arguments for this instruction. */ 285 const char *args; 286 /* The basic opcode for the instruction. When assembling, this 287 opcode is modified by the arguments to produce the actual opcode 288 that is used. If pinfo is INSN_MACRO, then this is 0. */ 289 unsigned long match; 290 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 291 relevant portions of the opcode when disassembling. If the 292 actual opcode anded with the match field equals the opcode field, 293 then we have found the correct instruction. If pinfo is 294 INSN_MACRO, then this field is the macro identifier. */ 295 unsigned long mask; 296 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 297 of bits describing the instruction, notably any relevant hazard 298 information. */ 299 unsigned long pinfo; 300 /* A collection of additional bits describing the instruction. */ 301 unsigned long pinfo2; 302 /* A collection of bits describing the instruction sets of which this 303 instruction or macro is a member. */ 304 unsigned long membership; 305 }; 306 307 /* These are the characters which may appear in the args field of an 308 instruction. They appear in the order in which the fields appear 309 when the instruction is used. Commas and parentheses in the args 310 string are ignored when assembling, and written into the output 311 when disassembling. 312 313 Each of these characters corresponds to a mask field defined above. 314 315 "<" 5 bit shift amount (OP_*_SHAMT) 316 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 317 "a" 26 bit target address (OP_*_TARGET) 318 "b" 5 bit base register (OP_*_RS) 319 "c" 10 bit breakpoint code (OP_*_CODE) 320 "d" 5 bit destination register specifier (OP_*_RD) 321 "h" 5 bit prefx hint (OP_*_PREFX) 322 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 323 "j" 16 bit signed immediate (OP_*_DELTA) 324 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 325 Also used for immediate operands in vr5400 vector insns. 326 "o" 16 bit signed offset (OP_*_DELTA) 327 "p" 16 bit PC relative branch target address (OP_*_DELTA) 328 "q" 10 bit extra breakpoint code (OP_*_CODE2) 329 "r" 5 bit same register used as both source and target (OP_*_RS) 330 "s" 5 bit source register specifier (OP_*_RS) 331 "t" 5 bit target register (OP_*_RT) 332 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 333 "v" 5 bit same register used as both source and destination (OP_*_RS) 334 "w" 5 bit same register used as both target and destination (OP_*_RT) 335 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 336 (used by clo and clz) 337 "C" 25 bit coprocessor function code (OP_*_COPZ) 338 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 339 "J" 19 bit wait function code (OP_*_CODE19) 340 "x" accept and ignore register name 341 "z" must be zero register 342 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 343 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 344 LSB (OP_*_SHAMT). 345 Enforces: 0 <= pos < 32. 346 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 347 Requires that "+A" or "+E" occur first to set position. 348 Enforces: 0 < (pos+size) <= 32. 349 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 350 Requires that "+A" or "+E" occur first to set position. 351 Enforces: 0 < (pos+size) <= 32. 352 (Also used by "dext" w/ different limits, but limits for 353 that are checked by the M_DEXT macro.) 354 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 355 Enforces: 32 <= pos < 64. 356 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 357 Requires that "+A" or "+E" occur first to set position. 358 Enforces: 32 < (pos+size) <= 64. 359 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 360 Requires that "+A" or "+E" occur first to set position. 361 Enforces: 32 < (pos+size) <= 64. 362 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 363 Requires that "+A" or "+E" occur first to set position. 364 Enforces: 32 < (pos+size) <= 64. 365 366 Floating point instructions: 367 "D" 5 bit destination register (OP_*_FD) 368 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 369 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 370 "S" 5 bit fs source 1 register (OP_*_FS) 371 "T" 5 bit ft source 2 register (OP_*_FT) 372 "R" 5 bit fr source 3 register (OP_*_FR) 373 "V" 5 bit same register used as floating source and destination (OP_*_FS) 374 "W" 5 bit same register used as floating target and destination (OP_*_FT) 375 376 Coprocessor instructions: 377 "E" 5 bit target register (OP_*_RT) 378 "G" 5 bit destination register (OP_*_RD) 379 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 380 "P" 5 bit performance-monitor register (OP_*_PERFREG) 381 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 382 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 383 see also "k" above 384 "+D" Combined destination register ("G") and sel ("H") for CP0 ops, 385 for pretty-printing in disassembly only. 386 387 Macro instructions: 388 "A" General 32 bit expression 389 "I" 32 bit immediate (value placed in imm_expr). 390 "+I" 32 bit immediate (value placed in imm2_expr). 391 "F" 64 bit floating point constant in .rdata 392 "L" 64 bit floating point constant in .lit8 393 "f" 32 bit floating point constant 394 "l" 32 bit floating point constant in .lit4 395 396 MDMX instruction operands (note that while these use the FP register 397 fields, they accept both $fN and $vN names for the registers): 398 "O" MDMX alignment offset (OP_*_ALN) 399 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 400 "X" MDMX destination register (OP_*_FD) 401 "Y" MDMX source register (OP_*_FS) 402 "Z" MDMX source register (OP_*_FT) 403 404 DSP ASE usage: 405 "2" 2 bit unsigned immediate for byte align (OP_*_BP) 406 "3" 3 bit unsigned immediate (OP_*_SA3) 407 "4" 4 bit unsigned immediate (OP_*_SA4) 408 "5" 8 bit unsigned immediate (OP_*_IMM8) 409 "6" 5 bit unsigned immediate (OP_*_RS) 410 "7" 2 bit dsp accumulator register (OP_*_DSPACC) 411 "8" 6 bit unsigned immediate (OP_*_WRDSP) 412 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 413 "0" 6 bit signed immediate (OP_*_DSPSFT) 414 ":" 7 bit signed immediate (OP_*_DSPSFT_7) 415 "'" 6 bit unsigned immediate (OP_*_RDDSP) 416 "@" 10 bit signed immediate (OP_*_IMM10) 417 418 MT ASE usage: 419 "!" 1 bit usermode flag (OP_*_MT_U) 420 "$" 1 bit load high flag (OP_*_MT_H) 421 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 422 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 423 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) 424 "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 425 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only 426 427 UDI immediates: 428 "+1" UDI immediate bits 6-10 429 "+2" UDI immediate bits 6-15 430 "+3" UDI immediate bits 6-20 431 "+4" UDI immediate bits 6-25 432 433 R6 immediates/displacements : 434 (adding suffix to 'o' to avoid adding new characters) 435 "+o" 9 bits immediate/displacement (shift = 7) 436 "+o1" 18 bits immediate/displacement (shift = 0) 437 "+o2" 19 bits immediate/displacement (shift = 0) 438 439 Other: 440 "()" parens surrounding optional value 441 "," separates operands 442 "[]" brackets around index for vector-op scalar operand specifier (vr5400) 443 "+" Start of extension sequence. 444 445 Characters used so far, for quick reference when adding more: 446 "234567890" 447 "%[]<>(),+:'@!$*&" 448 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 449 "abcdefghijklopqrstuvwxz" 450 451 Extension character sequences used so far ("+" followed by the 452 following), for quick reference when adding more: 453 "1234" 454 "ABCDEFGHIT" 455 "t" 456 */ 457 458 /* These are the bits which may be set in the pinfo field of an 459 instructions, if it is not equal to INSN_MACRO. */ 460 461 /* Modifies the general purpose register in OP_*_RD. */ 462 #define INSN_WRITE_GPR_D 0x00000001 463 /* Modifies the general purpose register in OP_*_RT. */ 464 #define INSN_WRITE_GPR_T 0x00000002 465 /* Modifies general purpose register 31. */ 466 #define INSN_WRITE_GPR_31 0x00000004 467 /* Modifies the floating point register in OP_*_FD. */ 468 #define INSN_WRITE_FPR_D 0x00000008 469 /* Modifies the floating point register in OP_*_FS. */ 470 #define INSN_WRITE_FPR_S 0x00000010 471 /* Modifies the floating point register in OP_*_FT. */ 472 #define INSN_WRITE_FPR_T 0x00000020 473 /* Reads the general purpose register in OP_*_RS. */ 474 #define INSN_READ_GPR_S 0x00000040 475 /* Reads the general purpose register in OP_*_RT. */ 476 #define INSN_READ_GPR_T 0x00000080 477 /* Reads the floating point register in OP_*_FS. */ 478 #define INSN_READ_FPR_S 0x00000100 479 /* Reads the floating point register in OP_*_FT. */ 480 #define INSN_READ_FPR_T 0x00000200 481 /* Reads the floating point register in OP_*_FR. */ 482 #define INSN_READ_FPR_R 0x00000400 483 /* Modifies coprocessor condition code. */ 484 #define INSN_WRITE_COND_CODE 0x00000800 485 /* Reads coprocessor condition code. */ 486 #define INSN_READ_COND_CODE 0x00001000 487 /* TLB operation. */ 488 #define INSN_TLB 0x00002000 489 /* Reads coprocessor register other than floating point register. */ 490 #define INSN_COP 0x00004000 491 /* Instruction loads value from memory, requiring delay. */ 492 #define INSN_LOAD_MEMORY_DELAY 0x00008000 493 /* Instruction loads value from coprocessor, requiring delay. */ 494 #define INSN_LOAD_COPROC_DELAY 0x00010000 495 /* Instruction has unconditional branch delay slot. */ 496 #define INSN_UNCOND_BRANCH_DELAY 0x00020000 497 /* Instruction has conditional branch delay slot. */ 498 #define INSN_COND_BRANCH_DELAY 0x00040000 499 /* Conditional branch likely: if branch not taken, insn nullified. */ 500 #define INSN_COND_BRANCH_LIKELY 0x00080000 501 /* Moves to coprocessor register, requiring delay. */ 502 #define INSN_COPROC_MOVE_DELAY 0x00100000 503 /* Loads coprocessor register from memory, requiring delay. */ 504 #define INSN_COPROC_MEMORY_DELAY 0x00200000 505 /* Reads the HI register. */ 506 #define INSN_READ_HI 0x00400000 507 /* Reads the LO register. */ 508 #define INSN_READ_LO 0x00800000 509 /* Modifies the HI register. */ 510 #define INSN_WRITE_HI 0x01000000 511 /* Modifies the LO register. */ 512 #define INSN_WRITE_LO 0x02000000 513 /* Takes a trap (easier to keep out of delay slot). */ 514 #define INSN_TRAP 0x04000000 515 /* Instruction stores value into memory. */ 516 #define INSN_STORE_MEMORY 0x08000000 517 /* Instruction uses single precision floating point. */ 518 #define FP_S 0x10000000 519 /* Instruction uses double precision floating point. */ 520 #define FP_D 0x20000000 521 /* Instruction is part of the tx39's integer multiply family. */ 522 #define INSN_MULT 0x40000000 523 /* Instruction synchronize shared memory. */ 524 #define INSN_SYNC 0x80000000 525 526 /* These are the bits which may be set in the pinfo2 field of an 527 instruction. */ 528 529 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 530 #define INSN2_ALIAS 0x00000001 531 /* Instruction reads MDMX accumulator. */ 532 #define INSN2_READ_MDMX_ACC 0x00000002 533 /* Instruction writes MDMX accumulator. */ 534 #define INSN2_WRITE_MDMX_ACC 0x00000004 535 536 /* Reads the general purpose register in OP_*_RD. */ 537 #define INSN2_READ_GPR_D 0x00000200 538 539 /* Instruction is actually a macro. It should be ignored by the 540 disassembler, and requires special treatment by the assembler. */ 541 #define INSN_MACRO 0xffffffff 542 543 /* Masks used to mark instructions to indicate which MIPS ISA level 544 they were introduced in. ISAs, as defined below, are logical 545 ORs of these bits, indicating that they support the instructions 546 defined at the given level. */ 547 548 #define INSN_ISA_MASK 0x00000fff 549 #define INSN_ISA1 0x00000001 550 #define INSN_ISA2 0x00000002 551 #define INSN_ISA3 0x00000004 552 #define INSN_ISA4 0x00000008 553 #define INSN_ISA5 0x00000010 554 #define INSN_ISA32 0x00000020 555 #define INSN_ISA64 0x00000040 556 #define INSN_ISA32R2 0x00000080 557 #define INSN_ISA64R2 0x00000100 558 #define INSN_ISA32R6 0x00000200 559 #define INSN_ISA64R6 0x00000400 560 561 /* Masks used for MIPS-defined ASEs. */ 562 #define INSN_ASE_MASK 0x0000f000 563 564 /* DSP ASE */ 565 #define INSN_DSP 0x00001000 566 #define INSN_DSP64 0x00002000 567 /* MIPS 16 ASE */ 568 #define INSN_MIPS16 0x00004000 569 /* MIPS-3D ASE */ 570 #define INSN_MIPS3D 0x00008000 571 572 /* Chip specific instructions. These are bitmasks. */ 573 574 /* MIPS R4650 instruction. */ 575 #define INSN_4650 0x00010000 576 /* LSI R4010 instruction. */ 577 #define INSN_4010 0x00020000 578 /* NEC VR4100 instruction. */ 579 #define INSN_4100 0x00040000 580 /* Toshiba R3900 instruction. */ 581 #define INSN_3900 0x00080000 582 /* MIPS R10000 instruction. */ 583 #define INSN_10000 0x00100000 584 /* Broadcom SB-1 instruction. */ 585 #define INSN_SB1 0x00200000 586 /* NEC VR4111/VR4181 instruction. */ 587 #define INSN_4111 0x00400000 588 /* NEC VR4120 instruction. */ 589 #define INSN_4120 0x00800000 590 /* NEC VR5400 instruction. */ 591 #define INSN_5400 0x01000000 592 /* NEC VR5500 instruction. */ 593 #define INSN_5500 0x02000000 594 595 /* MDMX ASE */ 596 #define INSN_MDMX 0x00000000 /* Deprecated */ 597 598 /* MIPS MSA Extension */ 599 #define INSN_MSA 0x04000000 600 #define INSN_MSA64 0x04000000 601 602 /* MT ASE */ 603 #define INSN_MT 0x08000000 604 /* SmartMIPS ASE */ 605 #define INSN_SMARTMIPS 0x10000000 606 /* DSP R2 ASE */ 607 #define INSN_DSPR2 0x20000000 608 609 /* ST Microelectronics Loongson 2E. */ 610 #define INSN_LOONGSON_2E 0x40000000 611 /* ST Microelectronics Loongson 2F. */ 612 #define INSN_LOONGSON_2F 0x80000000 613 614 /* MIPS ISA defines, use instead of hardcoding ISA level. */ 615 616 #define ISA_UNKNOWN 0 /* Gas internal use. */ 617 #define ISA_MIPS1 (INSN_ISA1) 618 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) 619 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) 620 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) 621 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) 622 623 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) 624 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) 625 626 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) 627 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) 628 629 #define ISA_MIPS32R6 (ISA_MIPS32R2 | INSN_ISA32R6) 630 #define ISA_MIPS64R6 (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6) 631 632 /* CPU defines, use instead of hardcoding processor number. Keep this 633 in sync with bfd/archures.c in order for machine selection to work. */ 634 #define CPU_UNKNOWN 0 /* Gas internal use. */ 635 #define CPU_R3000 3000 636 #define CPU_R3900 3900 637 #define CPU_R4000 4000 638 #define CPU_R4010 4010 639 #define CPU_VR4100 4100 640 #define CPU_R4111 4111 641 #define CPU_VR4120 4120 642 #define CPU_R4300 4300 643 #define CPU_R4400 4400 644 #define CPU_R4600 4600 645 #define CPU_R4650 4650 646 #define CPU_R5000 5000 647 #define CPU_VR5400 5400 648 #define CPU_VR5500 5500 649 #define CPU_R6000 6000 650 #define CPU_RM7000 7000 651 #define CPU_R8000 8000 652 #define CPU_R10000 10000 653 #define CPU_R12000 12000 654 #define CPU_MIPS16 16 655 #define CPU_MIPS32 32 656 #define CPU_MIPS32R2 33 657 #define CPU_MIPS5 5 658 #define CPU_MIPS64 64 659 #define CPU_MIPS64R2 65 660 #define CPU_SB1 12310201 /* octal 'SB', 01. */ 661 662 /* Test for membership in an ISA including chip specific ISAs. INSN 663 is pointer to an element of the opcode table; ISA is the specified 664 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 665 test, or zero if no CPU specific ISA test is desired. */ 666 667 #if 0 668 #define OPCODE_IS_MEMBER(insn, isa, cpu) \ 669 (((insn)->membership & isa) != 0 \ 670 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ 671 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ 672 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ 673 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ 674 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ 675 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ 676 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ 677 && ((insn)->membership & INSN_10000) != 0) \ 678 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ 679 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ 680 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ 681 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ 682 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ 683 || 0) /* Please keep this term for easier source merging. */ 684 #else 685 #define OPCODE_IS_MEMBER(insn, isa, cpu) \ 686 (1 != 0) 687 #endif 688 689 /* This is a list of macro expanded instructions. 690 691 _I appended means immediate 692 _A appended means address 693 _AB appended means address with base register 694 _D appended means 64 bit floating point constant 695 _S appended means 32 bit floating point constant. */ 696 697 enum 698 { 699 M_ABS, 700 M_ADD_I, 701 M_ADDU_I, 702 M_AND_I, 703 M_BALIGN, 704 M_BEQ, 705 M_BEQ_I, 706 M_BEQL_I, 707 M_BGE, 708 M_BGEL, 709 M_BGE_I, 710 M_BGEL_I, 711 M_BGEU, 712 M_BGEUL, 713 M_BGEU_I, 714 M_BGEUL_I, 715 M_BGT, 716 M_BGTL, 717 M_BGT_I, 718 M_BGTL_I, 719 M_BGTU, 720 M_BGTUL, 721 M_BGTU_I, 722 M_BGTUL_I, 723 M_BLE, 724 M_BLEL, 725 M_BLE_I, 726 M_BLEL_I, 727 M_BLEU, 728 M_BLEUL, 729 M_BLEU_I, 730 M_BLEUL_I, 731 M_BLT, 732 M_BLTL, 733 M_BLT_I, 734 M_BLTL_I, 735 M_BLTU, 736 M_BLTUL, 737 M_BLTU_I, 738 M_BLTUL_I, 739 M_BNE, 740 M_BNE_I, 741 M_BNEL_I, 742 M_CACHE_AB, 743 M_DABS, 744 M_DADD_I, 745 M_DADDU_I, 746 M_DDIV_3, 747 M_DDIV_3I, 748 M_DDIVU_3, 749 M_DDIVU_3I, 750 M_DEXT, 751 M_DINS, 752 M_DIV_3, 753 M_DIV_3I, 754 M_DIVU_3, 755 M_DIVU_3I, 756 M_DLA_AB, 757 M_DLCA_AB, 758 M_DLI, 759 M_DMUL, 760 M_DMUL_I, 761 M_DMULO, 762 M_DMULO_I, 763 M_DMULOU, 764 M_DMULOU_I, 765 M_DREM_3, 766 M_DREM_3I, 767 M_DREMU_3, 768 M_DREMU_3I, 769 M_DSUB_I, 770 M_DSUBU_I, 771 M_DSUBU_I_2, 772 M_J_A, 773 M_JAL_1, 774 M_JAL_2, 775 M_JAL_A, 776 M_L_DOB, 777 M_L_DAB, 778 M_LA_AB, 779 M_LB_A, 780 M_LB_AB, 781 M_LBU_A, 782 M_LBU_AB, 783 M_LCA_AB, 784 M_LD_A, 785 M_LD_OB, 786 M_LD_AB, 787 M_LDC1_AB, 788 M_LDC2_AB, 789 M_LDC3_AB, 790 M_LDL_AB, 791 M_LDR_AB, 792 M_LH_A, 793 M_LH_AB, 794 M_LHU_A, 795 M_LHU_AB, 796 M_LI, 797 M_LI_D, 798 M_LI_DD, 799 M_LI_S, 800 M_LI_SS, 801 M_LL_AB, 802 M_LLD_AB, 803 M_LS_A, 804 M_LW_A, 805 M_LW_AB, 806 M_LWC0_A, 807 M_LWC0_AB, 808 M_LWC1_A, 809 M_LWC1_AB, 810 M_LWC2_A, 811 M_LWC2_AB, 812 M_LWC3_A, 813 M_LWC3_AB, 814 M_LWL_A, 815 M_LWL_AB, 816 M_LWR_A, 817 M_LWR_AB, 818 M_LWU_AB, 819 M_MOVE, 820 M_MUL, 821 M_MUL_I, 822 M_MULO, 823 M_MULO_I, 824 M_MULOU, 825 M_MULOU_I, 826 M_NOR_I, 827 M_OR_I, 828 M_REM_3, 829 M_REM_3I, 830 M_REMU_3, 831 M_REMU_3I, 832 M_DROL, 833 M_ROL, 834 M_DROL_I, 835 M_ROL_I, 836 M_DROR, 837 M_ROR, 838 M_DROR_I, 839 M_ROR_I, 840 M_S_DA, 841 M_S_DOB, 842 M_S_DAB, 843 M_S_S, 844 M_SC_AB, 845 M_SCD_AB, 846 M_SD_A, 847 M_SD_OB, 848 M_SD_AB, 849 M_SDC1_AB, 850 M_SDC2_AB, 851 M_SDC3_AB, 852 M_SDL_AB, 853 M_SDR_AB, 854 M_SEQ, 855 M_SEQ_I, 856 M_SGE, 857 M_SGE_I, 858 M_SGEU, 859 M_SGEU_I, 860 M_SGT, 861 M_SGT_I, 862 M_SGTU, 863 M_SGTU_I, 864 M_SLE, 865 M_SLE_I, 866 M_SLEU, 867 M_SLEU_I, 868 M_SLT_I, 869 M_SLTU_I, 870 M_SNE, 871 M_SNE_I, 872 M_SB_A, 873 M_SB_AB, 874 M_SH_A, 875 M_SH_AB, 876 M_SW_A, 877 M_SW_AB, 878 M_SWC0_A, 879 M_SWC0_AB, 880 M_SWC1_A, 881 M_SWC1_AB, 882 M_SWC2_A, 883 M_SWC2_AB, 884 M_SWC3_A, 885 M_SWC3_AB, 886 M_SWL_A, 887 M_SWL_AB, 888 M_SWR_A, 889 M_SWR_AB, 890 M_SUB_I, 891 M_SUBU_I, 892 M_SUBU_I_2, 893 M_TEQ_I, 894 M_TGE_I, 895 M_TGEU_I, 896 M_TLT_I, 897 M_TLTU_I, 898 M_TNE_I, 899 M_TRUNCWD, 900 M_TRUNCWS, 901 M_ULD, 902 M_ULD_A, 903 M_ULH, 904 M_ULH_A, 905 M_ULHU, 906 M_ULHU_A, 907 M_ULW, 908 M_ULW_A, 909 M_USH, 910 M_USH_A, 911 M_USW, 912 M_USW_A, 913 M_USD, 914 M_USD_A, 915 M_XOR_I, 916 M_COP0, 917 M_COP1, 918 M_COP2, 919 M_COP3, 920 M_NUM_MACROS 921 }; 922 923 924 /* The order of overloaded instructions matters. Label arguments and 925 register arguments look the same. Instructions that can have either 926 for arguments must apear in the correct order in this table for the 927 assembler to pick the right one. In other words, entries with 928 immediate operands must apear after the same instruction with 929 registers. 930 931 Many instructions are short hand for other instructions (i.e., The 932 jal <register> instruction is short for jalr <register>). */ 933 934 extern const struct mips_opcode mips_builtin_opcodes[]; 935 extern const int bfd_mips_num_builtin_opcodes; 936 extern struct mips_opcode *mips_opcodes; 937 extern int bfd_mips_num_opcodes; 938 #define NUMOPCODES bfd_mips_num_opcodes 939 940 941 /* The rest of this file adds definitions for the mips16 TinyRISC 942 processor. */ 943 944 /* These are the bitmasks and shift counts used for the different 945 fields in the instruction formats. Other than OP, no masks are 946 provided for the fixed portions of an instruction, since they are 947 not needed. 948 949 The I format uses IMM11. 950 951 The RI format uses RX and IMM8. 952 953 The RR format uses RX, and RY. 954 955 The RRI format uses RX, RY, and IMM5. 956 957 The RRR format uses RX, RY, and RZ. 958 959 The RRI_A format uses RX, RY, and IMM4. 960 961 The SHIFT format uses RX, RY, and SHAMT. 962 963 The I8 format uses IMM8. 964 965 The I8_MOVR32 format uses RY and REGR32. 966 967 The IR_MOV32R format uses REG32R and MOV32Z. 968 969 The I64 format uses IMM8. 970 971 The RI64 format uses RY and IMM5. 972 */ 973 974 #define MIPS16OP_MASK_OP 0x1f 975 #define MIPS16OP_SH_OP 11 976 #define MIPS16OP_MASK_IMM11 0x7ff 977 #define MIPS16OP_SH_IMM11 0 978 #define MIPS16OP_MASK_RX 0x7 979 #define MIPS16OP_SH_RX 8 980 #define MIPS16OP_MASK_IMM8 0xff 981 #define MIPS16OP_SH_IMM8 0 982 #define MIPS16OP_MASK_RY 0x7 983 #define MIPS16OP_SH_RY 5 984 #define MIPS16OP_MASK_IMM5 0x1f 985 #define MIPS16OP_SH_IMM5 0 986 #define MIPS16OP_MASK_RZ 0x7 987 #define MIPS16OP_SH_RZ 2 988 #define MIPS16OP_MASK_IMM4 0xf 989 #define MIPS16OP_SH_IMM4 0 990 #define MIPS16OP_MASK_REGR32 0x1f 991 #define MIPS16OP_SH_REGR32 0 992 #define MIPS16OP_MASK_REG32R 0x1f 993 #define MIPS16OP_SH_REG32R 3 994 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 995 #define MIPS16OP_MASK_MOVE32Z 0x7 996 #define MIPS16OP_SH_MOVE32Z 0 997 #define MIPS16OP_MASK_IMM6 0x3f 998 #define MIPS16OP_SH_IMM6 5 999 1000 /* These are the characters which may appears in the args field of an 1001 instruction. They appear in the order in which the fields appear 1002 when the instruction is used. Commas and parentheses in the args 1003 string are ignored when assembling, and written into the output 1004 when disassembling. 1005 1006 "y" 3 bit register (MIPS16OP_*_RY) 1007 "x" 3 bit register (MIPS16OP_*_RX) 1008 "z" 3 bit register (MIPS16OP_*_RZ) 1009 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 1010 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 1011 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 1012 "0" zero register ($0) 1013 "S" stack pointer ($sp or $29) 1014 "P" program counter 1015 "R" return address register ($ra or $31) 1016 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 1017 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 1018 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 1019 "a" 26 bit jump address 1020 "e" 11 bit extension value 1021 "l" register list for entry instruction 1022 "L" register list for exit instruction 1023 1024 The remaining codes may be extended. Except as otherwise noted, 1025 the full extended operand is a 16 bit signed value. 1026 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 1027 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 1028 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 1029 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 1030 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 1031 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 1032 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 1033 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 1034 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 1035 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 1036 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 1037 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 1038 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 1039 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 1040 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 1041 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 1042 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 1043 "q" 11 bit branch address (MIPS16OP_*_IMM11) 1044 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 1045 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 1046 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 1047 */ 1048 1049 /* Save/restore encoding for the args field when all 4 registers are 1050 either saved as arguments or saved/restored as statics. */ 1051 #define MIPS16_ALL_ARGS 0xe 1052 #define MIPS16_ALL_STATICS 0xb 1053 1054 /* For the mips16, we use the same opcode table format and a few of 1055 the same flags. However, most of the flags are different. */ 1056 1057 /* Modifies the register in MIPS16OP_*_RX. */ 1058 #define MIPS16_INSN_WRITE_X 0x00000001 1059 /* Modifies the register in MIPS16OP_*_RY. */ 1060 #define MIPS16_INSN_WRITE_Y 0x00000002 1061 /* Modifies the register in MIPS16OP_*_RZ. */ 1062 #define MIPS16_INSN_WRITE_Z 0x00000004 1063 /* Modifies the T ($24) register. */ 1064 #define MIPS16_INSN_WRITE_T 0x00000008 1065 /* Modifies the SP ($29) register. */ 1066 #define MIPS16_INSN_WRITE_SP 0x00000010 1067 /* Modifies the RA ($31) register. */ 1068 #define MIPS16_INSN_WRITE_31 0x00000020 1069 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ 1070 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 1071 /* Reads the register in MIPS16OP_*_RX. */ 1072 #define MIPS16_INSN_READ_X 0x00000080 1073 /* Reads the register in MIPS16OP_*_RY. */ 1074 #define MIPS16_INSN_READ_Y 0x00000100 1075 /* Reads the register in MIPS16OP_*_MOVE32Z. */ 1076 #define MIPS16_INSN_READ_Z 0x00000200 1077 /* Reads the T ($24) register. */ 1078 #define MIPS16_INSN_READ_T 0x00000400 1079 /* Reads the SP ($29) register. */ 1080 #define MIPS16_INSN_READ_SP 0x00000800 1081 /* Reads the RA ($31) register. */ 1082 #define MIPS16_INSN_READ_31 0x00001000 1083 /* Reads the program counter. */ 1084 #define MIPS16_INSN_READ_PC 0x00002000 1085 /* Reads the general purpose register in MIPS16OP_*_REGR32. */ 1086 #define MIPS16_INSN_READ_GPR_X 0x00004000 1087 /* Is a branch insn. */ 1088 #define MIPS16_INSN_BRANCH 0x00010000 1089 1090 /* The following flags have the same value for the mips16 opcode 1091 table: 1092 INSN_UNCOND_BRANCH_DELAY 1093 INSN_COND_BRANCH_DELAY 1094 INSN_COND_BRANCH_LIKELY (never used) 1095 INSN_READ_HI 1096 INSN_READ_LO 1097 INSN_WRITE_HI 1098 INSN_WRITE_LO 1099 INSN_TRAP 1100 INSN_ISA3 1101 */ 1102 1103 extern const struct mips_opcode mips16_opcodes[]; 1104 extern const int bfd_mips16_num_opcodes; 1105 1106 /* Short hand so the lines aren't too long. */ 1107 1108 #define LDD INSN_LOAD_MEMORY_DELAY 1109 #define LCD INSN_LOAD_COPROC_DELAY 1110 #define UBD INSN_UNCOND_BRANCH_DELAY 1111 #define CBD INSN_COND_BRANCH_DELAY 1112 #define COD INSN_COPROC_MOVE_DELAY 1113 #define CLD INSN_COPROC_MEMORY_DELAY 1114 #define CBL INSN_COND_BRANCH_LIKELY 1115 #define TRAP INSN_TRAP 1116 #define SM INSN_STORE_MEMORY 1117 1118 #define WR_d INSN_WRITE_GPR_D 1119 #define WR_t INSN_WRITE_GPR_T 1120 #define WR_31 INSN_WRITE_GPR_31 1121 #define WR_D INSN_WRITE_FPR_D 1122 #define WR_T INSN_WRITE_FPR_T 1123 #define WR_S INSN_WRITE_FPR_S 1124 #define RD_s INSN_READ_GPR_S 1125 #define RD_b INSN_READ_GPR_S 1126 #define RD_t INSN_READ_GPR_T 1127 #define RD_S INSN_READ_FPR_S 1128 #define RD_T INSN_READ_FPR_T 1129 #define RD_R INSN_READ_FPR_R 1130 #define WR_CC INSN_WRITE_COND_CODE 1131 #define RD_CC INSN_READ_COND_CODE 1132 #define RD_C0 INSN_COP 1133 #define RD_C1 INSN_COP 1134 #define RD_C2 INSN_COP 1135 #define RD_C3 INSN_COP 1136 #define WR_C0 INSN_COP 1137 #define WR_C1 INSN_COP 1138 #define WR_C2 INSN_COP 1139 #define WR_C3 INSN_COP 1140 1141 #define WR_HI INSN_WRITE_HI 1142 #define RD_HI INSN_READ_HI 1143 #define MOD_HI WR_HI|RD_HI 1144 1145 #define WR_LO INSN_WRITE_LO 1146 #define RD_LO INSN_READ_LO 1147 #define MOD_LO WR_LO|RD_LO 1148 1149 #define WR_HILO WR_HI|WR_LO 1150 #define RD_HILO RD_HI|RD_LO 1151 #define MOD_HILO WR_HILO|RD_HILO 1152 1153 #define IS_M INSN_MULT 1154 1155 #define WR_MACC INSN2_WRITE_MDMX_ACC 1156 #define RD_MACC INSN2_READ_MDMX_ACC 1157 1158 #define I1 INSN_ISA1 1159 #define I2 INSN_ISA2 1160 #define I3 INSN_ISA3 1161 #define I4 INSN_ISA4 1162 #define I5 INSN_ISA5 1163 #define I32 INSN_ISA32 1164 #define I64 INSN_ISA64 1165 #define I33 INSN_ISA32R2 1166 #define I65 INSN_ISA64R2 1167 #define I32R6 INSN_ISA32R6 1168 #define I64R6 INSN_ISA64R6 1169 1170 /* MIPS64 MIPS-3D ASE support. */ 1171 #define I16 INSN_MIPS16 1172 1173 /* MIPS32 SmartMIPS ASE support. */ 1174 #define SMT INSN_SMARTMIPS 1175 1176 /* MIPS64 MIPS-3D ASE support. */ 1177 #define M3D INSN_MIPS3D 1178 1179 /* MIPS64 MDMX ASE support. */ 1180 #define MX INSN_MDMX 1181 1182 #define IL2E (INSN_LOONGSON_2E) 1183 #define IL2F (INSN_LOONGSON_2F) 1184 1185 #define P3 INSN_4650 1186 #define L1 INSN_4010 1187 #define V1 (INSN_4100 | INSN_4111 | INSN_4120) 1188 #define T3 INSN_3900 1189 #define M1 INSN_10000 1190 #define SB1 INSN_SB1 1191 #define N411 INSN_4111 1192 #define N412 INSN_4120 1193 #define N5 (INSN_5400 | INSN_5500) 1194 #define N54 INSN_5400 1195 #define N55 INSN_5500 1196 1197 #define G1 (T3 \ 1198 ) 1199 1200 #define G2 (T3 \ 1201 ) 1202 1203 #define G3 (I4 \ 1204 ) 1205 1206 /* MIPS DSP ASE support. 1207 NOTE: 1208 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair 1209 of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have 1210 the same structure as $ac0 (HI + LO). For DSP instructions that write or 1211 read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a 1212 (RD_HILO) attributes, such that HILO dependencies are maintained 1213 conservatively. 1214 1215 2. For some mul. instructions that use integer registers as destinations 1216 but destroy HI+LO as side-effect, we add WR_HILO to their attributes. 1217 1218 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields 1219 (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write 1220 certain fields of the DSP control register. For simplicity, we decide not 1221 to track dependencies of these fields. 1222 However, "bposge32" is a branch instruction that depends on the "pos" 1223 field. In order to make sure that GAS does not reorder DSP instructions 1224 that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP) 1225 attribute to those instructions that write the "pos" field. */ 1226 1227 #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ 1228 #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ 1229 #define MOD_a WR_a|RD_a 1230 #define DSP_VOLA INSN_TRAP 1231 #define D32 INSN_DSP 1232 #define D33 INSN_DSPR2 1233 #define D64 INSN_DSP64 1234 1235 /* MIPS MT ASE support. */ 1236 #define MT32 INSN_MT 1237 1238 /* MSA */ 1239 #define MSA INSN_MSA 1240 #define MSA64 INSN_MSA64 1241 #define WR_VD INSN_WRITE_FPR_D /* Reuse INSN_WRITE_FPR_D */ 1242 #define RD_VD WR_VD /* Reuse WR_VD */ 1243 #define RD_VT INSN_READ_FPR_T /* Reuse INSN_READ_FPR_T */ 1244 #define RD_VS INSN_READ_FPR_S /* Reuse INSN_READ_FPR_S */ 1245 #define RD_d INSN2_READ_GPR_D /* Reuse INSN2_READ_GPR_D */ 1246 1247 #define RD_rd6 0 1248 1249 /* The order of overloaded instructions matters. Label arguments and 1250 register arguments look the same. Instructions that can have either 1251 for arguments must apear in the correct order in this table for the 1252 assembler to pick the right one. In other words, entries with 1253 immediate operands must apear after the same instruction with 1254 registers. 1255 1256 Because of the lookup algorithm used, entries with the same opcode 1257 name must be contiguous. 1258 1259 Many instructions are short hand for other instructions (i.e., The 1260 jal <register> instruction is short for jalr <register>). */ 1261 1262 const struct mips_opcode mips_builtin_opcodes[] = 1263 { 1264 /* These instructions appear first so that the disassembler will find 1265 them first. The assemblers uses a hash table based on the 1266 instruction name anyhow. */ 1267 /* name, args, match, mask, pinfo, membership */ 1268 {"lwpc", "s,+o2", 0xec080000, 0xfc180000, WR_d, 0, I32R6}, 1269 {"lwupc", "s,+o2", 0xec100000, 0xfc180000, WR_d, 0, I64R6}, 1270 {"ldpc", "s,+o1", 0xec180000, 0xfc1c0000, WR_d, 0, I64R6}, 1271 {"addiupc", "s,+o2", 0xec000000, 0xfc180000, WR_d, 0, I32R6}, 1272 {"auipc", "s,u", 0xec1e0000, 0xfc1f0000, WR_d, 0, I32R6}, 1273 {"aluipc", "s,u", 0xec1f0000, 0xfc1f0000, WR_d, 0, I32R6}, 1274 {"daui", "s,t,u", 0x74000000, 0xfc000000, RD_s|WR_t, 0, I64R6}, 1275 {"dahi", "s,u", 0x04060000, 0xfc1f0000, RD_s, 0, I64R6}, 1276 {"dati", "s,u", 0x041e0000, 0xfc1f0000, RD_s, 0, I64R6}, 1277 {"lsa", "d,s,t", 0x00000005, 0xfc00073f, WR_d|RD_s|RD_t, 0, I32R6}, 1278 {"dlsa", "d,s,t", 0x00000015, 0xfc00073f, WR_d|RD_s|RD_t, 0, I64R6}, 1279 {"clz", "U,s", 0x00000050, 0xfc1f07ff, WR_d|RD_s, 0, I32R6}, 1280 {"clo", "U,s", 0x00000051, 0xfc1f07ff, WR_d|RD_s, 0, I32R6}, 1281 {"dclz", "U,s", 0x00000052, 0xfc1f07ff, WR_d|RD_s, 0, I64R6}, 1282 {"dclo", "U,s", 0x00000053, 0xfc1f07ff, WR_d|RD_s, 0, I64R6}, 1283 {"sdbbp", "B", 0x0000000e, 0xfc00003f, TRAP, 0, I32R6}, 1284 {"mul", "d,s,t", 0x00000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, 1285 {"muh", "d,s,t", 0x000000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, 1286 {"mulu", "d,s,t", 0x00000099, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, 1287 {"muhu", "d,s,t", 0x000000d9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, 1288 {"div", "d,s,t", 0x0000009a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, 1289 {"mod", "d,s,t", 0x000000da, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, 1290 {"divu", "d,s,t", 0x0000009b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, 1291 {"modu", "d,s,t", 0x000000db, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, 1292 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, 1293 {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, 1294 {"dmulu", "d,s,t", 0x0000009d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, 1295 {"dmuhu", "d,s,t", 0x000000dd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, 1296 {"ddiv", "d,s,t", 0x0000009e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, 1297 {"dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, 1298 {"ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, 1299 {"dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, 1300 {"ll", "t,+o(b)", 0x7c000036, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6}, 1301 {"sc", "t,+o(b)", 0x7c000026, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6}, 1302 {"lld", "t,+o(b)", 0x7c000037, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6}, 1303 {"scd", "t,+o(b)", 0x7c000027, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6}, 1304 {"pref", "h,+o(b)", 0x7c000035, 0xfc00007f, RD_b, 0, I32R6}, 1305 {"cache", "k,+o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6}, 1306 {"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, 1307 {"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, 1308 {"maddf.s", "D,S,T", 0x46000018, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6}, 1309 {"maddf.d", "D,S,T", 0x46200018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6}, 1310 {"msubf.s", "D,S,T", 0x46000019, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6}, 1311 {"msubf.d", "D,S,T", 0x46200019, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6}, 1312 {"max.s", "D,S,T", 0x4600001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6}, 1313 {"max.d", "D,S,T", 0x4620001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6}, 1314 {"maxa.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6}, 1315 {"maxa.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6}, 1316 {"rint.s", "D,S", 0x4600001a, 0xffff003f, WR_D|RD_S|FP_S, 0, I32R6}, 1317 {"rint.d", "D,S", 0x4620001a, 0xffff003f, WR_D|RD_S|FP_D, 0, I32R6}, 1318 {"class.s", "D,S", 0x4600001b, 0xffff003f, WR_D|RD_S|FP_S, 0, I32R6}, 1319 {"class.d", "D,S", 0x4620001b, 0xffff003f, WR_D|RD_S|FP_D, 0, I32R6}, 1320 {"min.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6}, 1321 {"min.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6}, 1322 {"mina.s", "D,S,T", 0x4600001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6}, 1323 {"mina.d", "D,S,T", 0x4620001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6}, 1324 {"sel.s", "D,S,T", 0x46000010, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6}, 1325 {"sel.d", "D,S,T", 0x46200010, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6}, 1326 {"seleqz.s", "D,S,T", 0x46000014, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6}, 1327 {"seleqz.d", "D,S,T", 0x46200014, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6}, 1328 {"selnez.s", "D,S,T", 0x46000017, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6}, 1329 {"selnez.d", "D,S,T", 0x46200017, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I32R6}, 1330 {"align", "d,v,t", 0x7c000220, 0xfc00073f, WR_d|RD_s|RD_t, 0, I32R6}, 1331 {"dalign", "d,v,t", 0x7c000224, 0xfc00063f, WR_d|RD_s|RD_t, 0, I64R6}, 1332 {"bitswap", "d,w", 0x7c000020, 0xffe007ff, WR_d|RD_t, 0, I32R6}, 1333 {"dbitswap","d,w", 0x7c000024, 0xffe007ff, WR_d|RD_t, 0, I64R6}, 1334 {"balc", "+p", 0xe8000000, 0xfc000000, UBD|WR_31, 0, I32R6}, 1335 {"bc", "+p", 0xc8000000, 0xfc000000, UBD|WR_31, 0, I32R6}, 1336 {"jic", "t,o", 0xd8000000, 0xffe00000, UBD|RD_t, 0, I32R6}, 1337 {"beqzc", "s,+p", 0xd8000000, 0xfc000000, CBD|RD_s, 0, I32R6}, 1338 {"jialc", "t,o", 0xf8000000, 0xffe00000, UBD|RD_t, 0, I32R6}, 1339 {"bnezc", "s,+p", 0xf8000000, 0xfc000000, CBD|RD_s, 0, I32R6}, 1340 {"beqzalc", "s,t,p", 0x20000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6}, 1341 {"bovc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1342 {"beqc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1343 {"bnezalc", "s,t,p", 0x60000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6}, 1344 {"bnvc", "s,t,p", 0x60000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1345 {"bnec", "s,t,p", 0x60000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1346 {"blezc", "s,t,p", 0x58000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6}, 1347 {"bgezc", "s,t,p", 0x58000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1348 {"bgec", "s,t,p", 0x58000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1349 {"bgtzc", "s,t,p", 0x5c000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6}, 1350 {"bltzc", "s,t,p", 0x5c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1351 {"bltc", "s,t,p", 0x5c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1352 {"blezalc", "s,t,p", 0x18000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6}, 1353 {"bgezalc", "s,t,p", 0x18000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1354 {"bgeuc", "s,t,p", 0x18000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1355 {"bgtzalc", "s,t,p", 0x1c000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6}, 1356 {"bltzalc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1357 {"bltuc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6}, 1358 {"nal", "p", 0x04100000, 0xffff0000, WR_31, 0, I32R6}, 1359 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, 0, I32R6}, 1360 {"bc1eqz", "T,p", 0x45200000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6}, 1361 {"bc1nez", "T,p", 0x45a00000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6}, 1362 {"bc2eqz", "E,p", 0x49200000, 0xffe00000, CBD|RD_C2, 0, I32R6}, 1363 {"bc2nez", "E,p", 0x49a00000, 0xffe00000, CBD|RD_C2, 0, I32R6}, 1364 {"cmp.af.s", "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1365 {"cmp.un.s", "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1366 {"cmp.eq.s", "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1367 {"cmp.ueq.s", "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1368 {"cmp.lt.s", "D,S,T", 0x46800004, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1369 {"cmp.ult.s", "D,S,T", 0x46800005, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1370 {"cmp.le.s", "D,S,T", 0x46800006, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1371 {"cmp.ule.s", "D,S,T", 0x46800007, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1372 {"cmp.saf.s", "D,S,T", 0x46800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1373 {"cmp.sun.s", "D,S,T", 0x46800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1374 {"cmp.seq.s", "D,S,T", 0x4680000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1375 {"cmp.sueq.s", "D,S,T", 0x4680000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1376 {"cmp.slt.s", "D,S,T", 0x4680000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1377 {"cmp.sult.s", "D,S,T", 0x4680000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1378 {"cmp.sle.s", "D,S,T", 0x4680000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1379 {"cmp.sule.s", "D,S,T", 0x4680000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1380 {"cmp.or.s", "D,S,T", 0x46800011, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1381 {"cmp.une.s", "D,S,T", 0x46800012, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1382 {"cmp.ne.s", "D,S,T", 0x46800013, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1383 {"cmp.sor.s", "D,S,T", 0x46800019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1384 {"cmp.sune.s", "D,S,T", 0x4680001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1385 {"cmp.sne.s", "D,S,T", 0x4680001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, I32R6}, 1386 {"cmp.af.d", "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1387 {"cmp.un.d", "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1388 {"cmp.eq.d", "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1389 {"cmp.ueq.d", "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1390 {"cmp.lt.d", "D,S,T", 0x46a00004, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1391 {"cmp.ult.d", "D,S,T", 0x46a00005, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1392 {"cmp.le.d", "D,S,T", 0x46a00006, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1393 {"cmp.ule.d", "D,S,T", 0x46a00007, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1394 {"cmp.saf.d", "D,S,T", 0x46a00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1395 {"cmp.sun.d", "D,S,T", 0x46a00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1396 {"cmp.seq.d", "D,S,T", 0x46a0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1397 {"cmp.sueq.d", "D,S,T", 0x46a0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1398 {"cmp.slt.d", "D,S,T", 0x46a0000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1399 {"cmp.sult.d", "D,S,T", 0x46a0000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1400 {"cmp.sle.d", "D,S,T", 0x46a0000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1401 {"cmp.sule.d", "D,S,T", 0x46a0000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1402 {"cmp.or.d", "D,S,T", 0x46a00011, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1403 {"cmp.une.d", "D,S,T", 0x46a00012, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1404 {"cmp.ne.d", "D,S,T", 0x46a00013, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1405 {"cmp.sor.d", "D,S,T", 0x46a00019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1406 {"cmp.sune.d", "D,S,T", 0x46a0001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1407 {"cmp.sne.d", "D,S,T", 0x46a0001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, I32R6}, 1408 {"dvp", "", 0x41600024, 0xffffffff, TRAP, 0, I32R6}, 1409 {"dvp", "t", 0x41600024, 0xffe0ffff, TRAP|WR_t, 0, I32R6}, 1410 {"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I32R6}, 1411 {"evp", "t", 0x41600004, 0xffe0ffff, TRAP|WR_t, 0, I32R6}, 1412 {"ginvi", "v", 0x7c00003d, 0xfc1ffcff, TRAP | INSN_TLB, 0, I32R6}, 1413 {"ginvt", "v", 0x7c0000bd, 0xfc1ffcff, TRAP | INSN_TLB, 0, I32R6}, 1414 {"crc32b", "t,v,t", 0x7c00000f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, 1415 {"crc32h", "t,v,t", 0x7c00004f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, 1416 {"crc32w", "t,v,t", 0x7c00008f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, 1417 {"crc32d", "t,v,t", 0x7c0000cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I64R6}, 1418 {"crc32cb", "t,v,t", 0x7c00010f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, 1419 {"crc32ch", "t,v,t", 0x7c00014f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, 1420 {"crc32cw", "t,v,t", 0x7c00018f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I32R6}, 1421 {"crc32cd", "t,v,t", 0x7c0001cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I64R6}, 1422 1423 /* MSA */ 1424 {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1425 {"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1426 {"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1427 {"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1428 {"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1429 {"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1430 {"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1431 {"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1432 {"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1433 {"sra.h", "+d,+e,+f", 0x78a0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1434 {"sra.w", "+d,+e,+f", 0x78c0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1435 {"sra.d", "+d,+e,+f", 0x78e0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1436 {"srai.b", "+d,+e,+7", 0x78f00009, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1437 {"srai.h", "+d,+e,+8", 0x78e00009, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1438 {"srai.w", "+d,+e,+9", 0x78c00009, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1439 {"srai.d", "+d,+e,'", 0x78800009, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1440 {"srl.b", "+d,+e,+f", 0x7900000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1441 {"srl.h", "+d,+e,+f", 0x7920000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1442 {"srl.w", "+d,+e,+f", 0x7940000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1443 {"srl.d", "+d,+e,+f", 0x7960000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1444 {"srli.b", "+d,+e,+7", 0x79700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1445 {"srli.h", "+d,+e,+8", 0x79600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1446 {"srli.w", "+d,+e,+9", 0x79400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1447 {"srli.d", "+d,+e,'", 0x79000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1448 {"bclr.b", "+d,+e,+f", 0x7980000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1449 {"bclr.h", "+d,+e,+f", 0x79a0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1450 {"bclr.w", "+d,+e,+f", 0x79c0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1451 {"bclr.d", "+d,+e,+f", 0x79e0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1452 {"bclri.b", "+d,+e,+7", 0x79f00009, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1453 {"bclri.h", "+d,+e,+8", 0x79e00009, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1454 {"bclri.w", "+d,+e,+9", 0x79c00009, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1455 {"bclri.d", "+d,+e,'", 0x79800009, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1456 {"bset.b", "+d,+e,+f", 0x7a00000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1457 {"bset.h", "+d,+e,+f", 0x7a20000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1458 {"bset.w", "+d,+e,+f", 0x7a40000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1459 {"bset.d", "+d,+e,+f", 0x7a60000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1460 {"bseti.b", "+d,+e,+7", 0x7a700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1461 {"bseti.h", "+d,+e,+8", 0x7a600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1462 {"bseti.w", "+d,+e,+9", 0x7a400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1463 {"bseti.d", "+d,+e,'", 0x7a000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1464 {"bneg.b", "+d,+e,+f", 0x7a80000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1465 {"bneg.h", "+d,+e,+f", 0x7aa0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1466 {"bneg.w", "+d,+e,+f", 0x7ac0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1467 {"bneg.d", "+d,+e,+f", 0x7ae0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1468 {"bnegi.b", "+d,+e,+7", 0x7af00009, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1469 {"bnegi.h", "+d,+e,+8", 0x7ae00009, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1470 {"bnegi.w", "+d,+e,+9", 0x7ac00009, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1471 {"bnegi.d", "+d,+e,'", 0x7a800009, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1472 {"binsl.b", "+d,+e,+f", 0x7b00000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1473 {"binsl.h", "+d,+e,+f", 0x7b20000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1474 {"binsl.w", "+d,+e,+f", 0x7b40000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1475 {"binsl.d", "+d,+e,+f", 0x7b60000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1476 {"binsli.b", "+d,+e,+7", 0x7b700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1477 {"binsli.h", "+d,+e,+8", 0x7b600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1478 {"binsli.w", "+d,+e,+9", 0x7b400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1479 {"binsli.d", "+d,+e,'", 0x7b000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1480 {"binsr.b", "+d,+e,+f", 0x7b80000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1481 {"binsr.h", "+d,+e,+f", 0x7ba0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1482 {"binsr.w", "+d,+e,+f", 0x7bc0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1483 {"binsr.d", "+d,+e,+f", 0x7be0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1484 {"binsri.b", "+d,+e,+7", 0x7bf00009, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1485 {"binsri.h", "+d,+e,+8", 0x7be00009, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1486 {"binsri.w", "+d,+e,+9", 0x7bc00009, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1487 {"binsri.d", "+d,+e,'", 0x7b800009, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1488 {"addv.b", "+d,+e,+f", 0x7800000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1489 {"addv.h", "+d,+e,+f", 0x7820000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1490 {"addv.w", "+d,+e,+f", 0x7840000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1491 {"addv.d", "+d,+e,+f", 0x7860000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1492 {"addvi.b", "+d,+e,k", 0x78000006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1493 {"addvi.h", "+d,+e,k", 0x78200006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1494 {"addvi.w", "+d,+e,k", 0x78400006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1495 {"addvi.d", "+d,+e,k", 0x78600006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1496 {"subv.b", "+d,+e,+f", 0x7880000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1497 {"subv.h", "+d,+e,+f", 0x78a0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1498 {"subv.w", "+d,+e,+f", 0x78c0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1499 {"subv.d", "+d,+e,+f", 0x78e0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1500 {"subvi.b", "+d,+e,k", 0x78800006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1501 {"subvi.h", "+d,+e,k", 0x78a00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1502 {"subvi.w", "+d,+e,k", 0x78c00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1503 {"subvi.d", "+d,+e,k", 0x78e00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1504 {"max_s.b", "+d,+e,+f", 0x7900000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1505 {"max_s.h", "+d,+e,+f", 0x7920000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1506 {"max_s.w", "+d,+e,+f", 0x7940000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1507 {"max_s.d", "+d,+e,+f", 0x7960000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1508 {"maxi_s.b", "+d,+e,+5", 0x79000006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1509 {"maxi_s.h", "+d,+e,+5", 0x79200006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1510 {"maxi_s.w", "+d,+e,+5", 0x79400006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1511 {"maxi_s.d", "+d,+e,+5", 0x79600006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1512 {"max_u.b", "+d,+e,+f", 0x7980000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1513 {"max_u.h", "+d,+e,+f", 0x79a0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1514 {"max_u.w", "+d,+e,+f", 0x79c0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1515 {"max_u.d", "+d,+e,+f", 0x79e0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1516 {"maxi_u.b", "+d,+e,k", 0x79800006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1517 {"maxi_u.h", "+d,+e,k", 0x79a00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1518 {"maxi_u.w", "+d,+e,k", 0x79c00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1519 {"maxi_u.d", "+d,+e,k", 0x79e00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1520 {"min_s.b", "+d,+e,+f", 0x7a00000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1521 {"min_s.h", "+d,+e,+f", 0x7a20000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1522 {"min_s.w", "+d,+e,+f", 0x7a40000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1523 {"min_s.d", "+d,+e,+f", 0x7a60000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1524 {"mini_s.b", "+d,+e,+5", 0x7a000006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1525 {"mini_s.h", "+d,+e,+5", 0x7a200006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1526 {"mini_s.w", "+d,+e,+5", 0x7a400006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1527 {"mini_s.d", "+d,+e,+5", 0x7a600006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1528 {"min_u.b", "+d,+e,+f", 0x7a80000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1529 {"min_u.h", "+d,+e,+f", 0x7aa0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1530 {"min_u.w", "+d,+e,+f", 0x7ac0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1531 {"min_u.d", "+d,+e,+f", 0x7ae0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1532 {"mini_u.b", "+d,+e,k", 0x7a800006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1533 {"mini_u.h", "+d,+e,k", 0x7aa00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1534 {"mini_u.w", "+d,+e,k", 0x7ac00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1535 {"mini_u.d", "+d,+e,k", 0x7ae00006, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1536 {"max_a.b", "+d,+e,+f", 0x7b00000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1537 {"max_a.h", "+d,+e,+f", 0x7b20000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1538 {"max_a.w", "+d,+e,+f", 0x7b40000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1539 {"max_a.d", "+d,+e,+f", 0x7b60000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1540 {"min_a.b", "+d,+e,+f", 0x7b80000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1541 {"min_a.h", "+d,+e,+f", 0x7ba0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1542 {"min_a.w", "+d,+e,+f", 0x7bc0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1543 {"min_a.d", "+d,+e,+f", 0x7be0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1544 {"ceq.b", "+d,+e,+f", 0x7800000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1545 {"ceq.h", "+d,+e,+f", 0x7820000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1546 {"ceq.w", "+d,+e,+f", 0x7840000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1547 {"ceq.d", "+d,+e,+f", 0x7860000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1548 {"ceqi.b", "+d,+e,+5", 0x78000007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1549 {"ceqi.h", "+d,+e,+5", 0x78200007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1550 {"ceqi.w", "+d,+e,+5", 0x78400007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1551 {"ceqi.d", "+d,+e,+5", 0x78600007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1552 {"clt_s.b", "+d,+e,+f", 0x7900000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1553 {"clt_s.h", "+d,+e,+f", 0x7920000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1554 {"clt_s.w", "+d,+e,+f", 0x7940000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1555 {"clt_s.d", "+d,+e,+f", 0x7960000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1556 {"clti_s.b", "+d,+e,+5", 0x79000007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1557 {"clti_s.h", "+d,+e,+5", 0x79200007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1558 {"clti_s.w", "+d,+e,+5", 0x79400007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1559 {"clti_s.d", "+d,+e,+5", 0x79600007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1560 {"clt_u.b", "+d,+e,+f", 0x7980000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1561 {"clt_u.h", "+d,+e,+f", 0x79a0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1562 {"clt_u.w", "+d,+e,+f", 0x79c0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1563 {"clt_u.d", "+d,+e,+f", 0x79e0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1564 {"clti_u.b", "+d,+e,k", 0x79800007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1565 {"clti_u.h", "+d,+e,k", 0x79a00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1566 {"clti_u.w", "+d,+e,k", 0x79c00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1567 {"clti_u.d", "+d,+e,k", 0x79e00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1568 {"cle_s.b", "+d,+e,+f", 0x7a00000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1569 {"cle_s.h", "+d,+e,+f", 0x7a20000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1570 {"cle_s.w", "+d,+e,+f", 0x7a40000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1571 {"cle_s.d", "+d,+e,+f", 0x7a60000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1572 {"clei_s.b", "+d,+e,+5", 0x7a000007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1573 {"clei_s.h", "+d,+e,+5", 0x7a200007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1574 {"clei_s.w", "+d,+e,+5", 0x7a400007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1575 {"clei_s.d", "+d,+e,+5", 0x7a600007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1576 {"cle_u.b", "+d,+e,+f", 0x7a80000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1577 {"cle_u.h", "+d,+e,+f", 0x7aa0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1578 {"cle_u.w", "+d,+e,+f", 0x7ac0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1579 {"cle_u.d", "+d,+e,+f", 0x7ae0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1580 {"clei_u.b", "+d,+e,k", 0x7a800007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1581 {"clei_u.h", "+d,+e,k", 0x7aa00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1582 {"clei_u.w", "+d,+e,k", 0x7ac00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1583 {"clei_u.d", "+d,+e,k", 0x7ae00007, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1584 {"ld.b", "+d,+^(d)", 0x78000020, 0xfc00003f, WR_VD|LDD, RD_d, MSA}, 1585 {"ld.h", "+d,+#(d)", 0x78000021, 0xfc00003f, WR_VD|LDD, RD_d, MSA}, 1586 {"ld.w", "+d,+$(d)", 0x78000022, 0xfc00003f, WR_VD|LDD, RD_d, MSA}, 1587 {"ld.d", "+d,+%(d)", 0x78000023, 0xfc00003f, WR_VD|LDD, RD_d, MSA}, 1588 {"st.b", "+d,+^(d)", 0x78000024, 0xfc00003f, RD_VD|SM, RD_d, MSA}, 1589 {"st.h", "+d,+#(d)", 0x78000025, 0xfc00003f, RD_VD|SM, RD_d, MSA}, 1590 {"st.w", "+d,+$(d)", 0x78000026, 0xfc00003f, RD_VD|SM, RD_d, MSA}, 1591 {"st.d", "+d,+%(d)", 0x78000027, 0xfc00003f, RD_VD|SM, RD_d, MSA}, 1592 {"sat_s.b", "+d,+e,+7", 0x7870000a, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1593 {"sat_s.h", "+d,+e,+8", 0x7860000a, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1594 {"sat_s.w", "+d,+e,+9", 0x7840000a, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1595 {"sat_s.d", "+d,+e,'", 0x7800000a, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1596 {"sat_u.b", "+d,+e,+7", 0x78f0000a, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1597 {"sat_u.h", "+d,+e,+8", 0x78e0000a, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1598 {"sat_u.w", "+d,+e,+9", 0x78c0000a, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1599 {"sat_u.d", "+d,+e,'", 0x7880000a, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1600 {"add_a.b", "+d,+e,+f", 0x78000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1601 {"add_a.h", "+d,+e,+f", 0x78200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1602 {"add_a.w", "+d,+e,+f", 0x78400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1603 {"add_a.d", "+d,+e,+f", 0x78600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1604 {"adds_a.b", "+d,+e,+f", 0x78800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1605 {"adds_a.h", "+d,+e,+f", 0x78a00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1606 {"adds_a.w", "+d,+e,+f", 0x78c00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1607 {"adds_a.d", "+d,+e,+f", 0x78e00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1608 {"adds_s.b", "+d,+e,+f", 0x79000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1609 {"adds_s.h", "+d,+e,+f", 0x79200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1610 {"adds_s.w", "+d,+e,+f", 0x79400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1611 {"adds_s.d", "+d,+e,+f", 0x79600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1612 {"adds_u.b", "+d,+e,+f", 0x79800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1613 {"adds_u.h", "+d,+e,+f", 0x79a00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1614 {"adds_u.w", "+d,+e,+f", 0x79c00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1615 {"adds_u.d", "+d,+e,+f", 0x79e00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1616 {"ave_s.b", "+d,+e,+f", 0x7a000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1617 {"ave_s.h", "+d,+e,+f", 0x7a200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1618 {"ave_s.w", "+d,+e,+f", 0x7a400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1619 {"ave_s.d", "+d,+e,+f", 0x7a600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1620 {"ave_u.b", "+d,+e,+f", 0x7a800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1621 {"ave_u.h", "+d,+e,+f", 0x7aa00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1622 {"ave_u.w", "+d,+e,+f", 0x7ac00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1623 {"ave_u.d", "+d,+e,+f", 0x7ae00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1624 {"aver_s.b", "+d,+e,+f", 0x7b000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1625 {"aver_s.h", "+d,+e,+f", 0x7b200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1626 {"aver_s.w", "+d,+e,+f", 0x7b400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1627 {"aver_s.d", "+d,+e,+f", 0x7b600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1628 {"aver_u.b", "+d,+e,+f", 0x7b800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1629 {"aver_u.h", "+d,+e,+f", 0x7ba00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1630 {"aver_u.w", "+d,+e,+f", 0x7bc00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1631 {"aver_u.d", "+d,+e,+f", 0x7be00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1632 {"subs_s.b", "+d,+e,+f", 0x78000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1633 {"subs_s.h", "+d,+e,+f", 0x78200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1634 {"subs_s.w", "+d,+e,+f", 0x78400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1635 {"subs_s.d", "+d,+e,+f", 0x78600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1636 {"subs_u.b", "+d,+e,+f", 0x78800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1637 {"subs_u.h", "+d,+e,+f", 0x78a00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1638 {"subs_u.w", "+d,+e,+f", 0x78c00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1639 {"subs_u.d", "+d,+e,+f", 0x78e00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1640 {"subsus_u.b", "+d,+e,+f", 0x79000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1641 {"subsus_u.h", "+d,+e,+f", 0x79200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1642 {"subsus_u.w", "+d,+e,+f", 0x79400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1643 {"subsus_u.d", "+d,+e,+f", 0x79600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1644 {"subsuu_s.b", "+d,+e,+f", 0x79800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1645 {"subsuu_s.h", "+d,+e,+f", 0x79a00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1646 {"subsuu_s.w", "+d,+e,+f", 0x79c00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1647 {"subsuu_s.d", "+d,+e,+f", 0x79e00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1648 {"asub_s.b", "+d,+e,+f", 0x7a000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1649 {"asub_s.h", "+d,+e,+f", 0x7a200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1650 {"asub_s.w", "+d,+e,+f", 0x7a400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1651 {"asub_s.d", "+d,+e,+f", 0x7a600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1652 {"asub_u.b", "+d,+e,+f", 0x7a800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1653 {"asub_u.h", "+d,+e,+f", 0x7aa00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1654 {"asub_u.w", "+d,+e,+f", 0x7ac00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1655 {"asub_u.d", "+d,+e,+f", 0x7ae00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1656 {"mulv.b", "+d,+e,+f", 0x78000012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1657 {"mulv.h", "+d,+e,+f", 0x78200012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1658 {"mulv.w", "+d,+e,+f", 0x78400012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1659 {"mulv.d", "+d,+e,+f", 0x78600012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1660 {"maddv.b", "+d,+e,+f", 0x78800012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1661 {"maddv.h", "+d,+e,+f", 0x78a00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1662 {"maddv.w", "+d,+e,+f", 0x78c00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1663 {"maddv.d", "+d,+e,+f", 0x78e00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1664 {"msubv.b", "+d,+e,+f", 0x79000012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1665 {"msubv.h", "+d,+e,+f", 0x79200012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1666 {"msubv.w", "+d,+e,+f", 0x79400012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1667 {"msubv.d", "+d,+e,+f", 0x79600012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1668 {"div_s.b", "+d,+e,+f", 0x7a000012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1669 {"div_s.h", "+d,+e,+f", 0x7a200012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1670 {"div_s.w", "+d,+e,+f", 0x7a400012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1671 {"div_s.d", "+d,+e,+f", 0x7a600012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1672 {"div_u.b", "+d,+e,+f", 0x7a800012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1673 {"div_u.h", "+d,+e,+f", 0x7aa00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1674 {"div_u.w", "+d,+e,+f", 0x7ac00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1675 {"div_u.d", "+d,+e,+f", 0x7ae00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1676 {"mod_s.b", "+d,+e,+f", 0x7b000012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1677 {"mod_s.h", "+d,+e,+f", 0x7b200012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1678 {"mod_s.w", "+d,+e,+f", 0x7b400012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1679 {"mod_s.d", "+d,+e,+f", 0x7b600012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1680 {"mod_u.b", "+d,+e,+f", 0x7b800012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1681 {"mod_u.h", "+d,+e,+f", 0x7ba00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1682 {"mod_u.w", "+d,+e,+f", 0x7bc00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1683 {"mod_u.d", "+d,+e,+f", 0x7be00012, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1684 {"dotp_s.h", "+d,+e,+f", 0x78200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1685 {"dotp_s.w", "+d,+e,+f", 0x78400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1686 {"dotp_s.d", "+d,+e,+f", 0x78600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1687 {"dotp_u.h", "+d,+e,+f", 0x78a00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1688 {"dotp_u.w", "+d,+e,+f", 0x78c00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1689 {"dotp_u.d", "+d,+e,+f", 0x78e00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1690 {"dpadd_s.h", "+d,+e,+f", 0x79200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1691 {"dpadd_s.w", "+d,+e,+f", 0x79400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1692 {"dpadd_s.d", "+d,+e,+f", 0x79600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1693 {"dpadd_u.h", "+d,+e,+f", 0x79a00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1694 {"dpadd_u.w", "+d,+e,+f", 0x79c00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1695 {"dpadd_u.d", "+d,+e,+f", 0x79e00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1696 {"dpsub_s.h", "+d,+e,+f", 0x7a200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1697 {"dpsub_s.w", "+d,+e,+f", 0x7a400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1698 {"dpsub_s.d", "+d,+e,+f", 0x7a600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1699 {"dpsub_u.h", "+d,+e,+f", 0x7aa00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1700 {"dpsub_u.w", "+d,+e,+f", 0x7ac00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1701 {"dpsub_u.d", "+d,+e,+f", 0x7ae00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1702 {"sld.b", "+d,+e[t]", 0x78000014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA}, 1703 {"sld.h", "+d,+e[t]", 0x78200014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA}, 1704 {"sld.w", "+d,+e[t]", 0x78400014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA}, 1705 {"sld.d", "+d,+e[t]", 0x78600014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA}, 1706 {"sldi.b", "+d,+e[+9]", 0x78000019, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1707 {"sldi.h", "+d,+e[+8]", 0x78200019, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1708 {"sldi.w", "+d,+e[+7]", 0x78300019, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1709 {"sldi.d", "+d,+e[+6]", 0x78380019, 0xfffc003f, WR_VD|RD_VS, 0, MSA}, 1710 {"splat.b", "+d,+e[t]", 0x78800014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA}, 1711 {"splat.h", "+d,+e[t]", 0x78a00014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA}, 1712 {"splat.w", "+d,+e[t]", 0x78c00014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA}, 1713 {"splat.d", "+d,+e[t]", 0x78e00014, 0xffe0003f, WR_VD|RD_VS|RD_t, 0, MSA}, 1714 {"splati.b", "+d,+e[+9]", 0x78400019, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1715 {"splati.h", "+d,+e[+8]", 0x78600019, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1716 {"splati.w", "+d,+e[+7]", 0x78700019, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1717 {"splati.d", "+d,+e[+6]", 0x78780019, 0xfffc003f, WR_VD|RD_VS, 0, MSA}, 1718 {"pckev.b", "+d,+e,+f", 0x79000014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1719 {"pckev.h", "+d,+e,+f", 0x79200014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1720 {"pckev.w", "+d,+e,+f", 0x79400014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1721 {"pckev.d", "+d,+e,+f", 0x79600014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1722 {"pckod.b", "+d,+e,+f", 0x79800014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1723 {"pckod.h", "+d,+e,+f", 0x79a00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1724 {"pckod.w", "+d,+e,+f", 0x79c00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1725 {"pckod.d", "+d,+e,+f", 0x79e00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1726 {"ilvl.b", "+d,+e,+f", 0x7a000014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1727 {"ilvl.h", "+d,+e,+f", 0x7a200014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1728 {"ilvl.w", "+d,+e,+f", 0x7a400014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1729 {"ilvl.d", "+d,+e,+f", 0x7a600014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1730 {"ilvr.b", "+d,+e,+f", 0x7a800014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1731 {"ilvr.h", "+d,+e,+f", 0x7aa00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1732 {"ilvr.w", "+d,+e,+f", 0x7ac00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1733 {"ilvr.d", "+d,+e,+f", 0x7ae00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1734 {"ilvev.b", "+d,+e,+f", 0x7b000014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1735 {"ilvev.h", "+d,+e,+f", 0x7b200014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1736 {"ilvev.w", "+d,+e,+f", 0x7b400014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1737 {"ilvev.d", "+d,+e,+f", 0x7b600014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1738 {"ilvod.b", "+d,+e,+f", 0x7b800014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1739 {"ilvod.h", "+d,+e,+f", 0x7ba00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1740 {"ilvod.w", "+d,+e,+f", 0x7bc00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1741 {"ilvod.d", "+d,+e,+f", 0x7be00014, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1742 {"vshf.b", "+d,+e,+f", 0x78000015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1743 {"vshf.h", "+d,+e,+f", 0x78200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1744 {"vshf.w", "+d,+e,+f", 0x78400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1745 {"vshf.d", "+d,+e,+f", 0x78600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1746 {"srar.b", "+d,+e,+f", 0x78800015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1747 {"srar.h", "+d,+e,+f", 0x78a00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1748 {"srar.w", "+d,+e,+f", 0x78c00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1749 {"srar.d", "+d,+e,+f", 0x78e00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1750 {"srari.b", "+d,+e,+7", 0x7970000a, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1751 {"srari.h", "+d,+e,+8", 0x7960000a, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1752 {"srari.w", "+d,+e,+9", 0x7940000a, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1753 {"srari.d", "+d,+e,'", 0x7900000a, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1754 {"srlr.b", "+d,+e,+f", 0x79000015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1755 {"srlr.h", "+d,+e,+f", 0x79200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1756 {"srlr.w", "+d,+e,+f", 0x79400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1757 {"srlr.d", "+d,+e,+f", 0x79600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1758 {"srlri.b", "+d,+e,+7", 0x79f0000a, 0xfff8003f, WR_VD|RD_VS, 0, MSA}, 1759 {"srlri.h", "+d,+e,+8", 0x79e0000a, 0xfff0003f, WR_VD|RD_VS, 0, MSA}, 1760 {"srlri.w", "+d,+e,+9", 0x79c0000a, 0xffe0003f, WR_VD|RD_VS, 0, MSA}, 1761 {"srlri.d", "+d,+e,'", 0x7980000a, 0xffc0003f, WR_VD|RD_VS, 0, MSA}, 1762 {"hadd_s.h", "+d,+e,+f", 0x7a200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1763 {"hadd_s.w", "+d,+e,+f", 0x7a400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1764 {"hadd_s.d", "+d,+e,+f", 0x7a600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1765 {"hadd_u.h", "+d,+e,+f", 0x7aa00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1766 {"hadd_u.w", "+d,+e,+f", 0x7ac00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1767 {"hadd_u.d", "+d,+e,+f", 0x7ae00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1768 {"hsub_s.h", "+d,+e,+f", 0x7b200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1769 {"hsub_s.w", "+d,+e,+f", 0x7b400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1770 {"hsub_s.d", "+d,+e,+f", 0x7b600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1771 {"hsub_u.h", "+d,+e,+f", 0x7ba00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1772 {"hsub_u.w", "+d,+e,+f", 0x7bc00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1773 {"hsub_u.d", "+d,+e,+f", 0x7be00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1774 {"and.v", "+d,+e,+f", 0x7800001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1775 {"andi.b", "+d,+e,5", 0x78000000, 0xff00003f, WR_VD|RD_VS, 0, MSA}, 1776 {"or.v", "+d,+e,+f", 0x7820001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1777 {"ori.b", "+d,+e,5", 0x79000000, 0xff00003f, WR_VD|RD_VS, 0, MSA}, 1778 {"nor.v", "+d,+e,+f", 0x7840001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1779 {"nori.b", "+d,+e,5", 0x7a000000, 0xff00003f, WR_VD|RD_VS, 0, MSA}, 1780 {"xor.v", "+d,+e,+f", 0x7860001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1781 {"xori.b", "+d,+e,5", 0x7b000000, 0xff00003f, WR_VD|RD_VS, 0, MSA}, 1782 {"bmnz.v", "+d,+e,+f", 0x7880001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1783 {"bmnzi.b", "+d,+e,5", 0x78000001, 0xff00003f, WR_VD|RD_VS, 0, MSA}, 1784 {"bmz.v", "+d,+e,+f", 0x78a0001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1785 {"bmzi.b", "+d,+e,5", 0x79000001, 0xff00003f, WR_VD|RD_VS, 0, MSA}, 1786 {"bsel.v", "+d,+e,+f", 0x78c0001e, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1787 {"bseli.b", "+d,+e,5", 0x7a000001, 0xff00003f, WR_VD|RD_VS, 0, MSA}, 1788 {"shf.b", "+d,+e,5", 0x78000002, 0xff00003f, WR_VD|RD_VS, 0, MSA}, 1789 {"shf.h", "+d,+e,5", 0x79000002, 0xff00003f, WR_VD|RD_VS, 0, MSA}, 1790 {"shf.w", "+d,+e,5", 0x7a000002, 0xff00003f, WR_VD|RD_VS, 0, MSA}, 1791 {"bnz.v", "+f,p", 0x45e00000, 0xffe00000, CBD|RD_VT, 0, MSA}, 1792 {"bz.v", "+f,p", 0x45600000, 0xffe00000, CBD|RD_VT, 0, MSA}, 1793 {"fill.b", "+d,d", 0x7b00001e, 0xffff003f, WR_VD, RD_d, MSA}, 1794 {"fill.h", "+d,d", 0x7b01001e, 0xffff003f, WR_VD, RD_d, MSA}, 1795 {"fill.w", "+d,d", 0x7b02001e, 0xffff003f, WR_VD, RD_d, MSA}, 1796 {"fill.d", "+d,d", 0x7b03001e, 0xffff003f, WR_VD, RD_d, MSA64}, 1797 {"pcnt.b", "+d,+e", 0x7b04001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1798 {"pcnt.h", "+d,+e", 0x7b05001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1799 {"pcnt.w", "+d,+e", 0x7b06001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1800 {"pcnt.d", "+d,+e", 0x7b07001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1801 {"nloc.b", "+d,+e", 0x7b08001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1802 {"nloc.h", "+d,+e", 0x7b09001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1803 {"nloc.w", "+d,+e", 0x7b0a001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1804 {"nloc.d", "+d,+e", 0x7b0b001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1805 {"nlzc.b", "+d,+e", 0x7b0c001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1806 {"nlzc.h", "+d,+e", 0x7b0d001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1807 {"nlzc.w", "+d,+e", 0x7b0e001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1808 {"nlzc.d", "+d,+e", 0x7b0f001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1809 {"copy_s.b", "+i,+e[+9]", 0x78800019, 0xffe0003f, RD_VS, RD_rd6, MSA}, 1810 {"copy_s.h", "+i,+e[+8]", 0x78a00019, 0xfff0003f, RD_VS, RD_rd6, MSA}, 1811 {"copy_s.w", "+i,+e[+7]", 0x78b00019, 0xfff8003f, RD_VS, RD_rd6, MSA}, 1812 {"copy_s.d", "+i,+e[+6]", 0x78b80019, 0xfffc003f, RD_VS, RD_rd6, MSA64}, 1813 {"copy_u.b", "+i,+e[+9]", 0x78c00019, 0xffe0003f, RD_VS, RD_rd6, MSA}, 1814 {"copy_u.h", "+i,+e[+8]", 0x78e00019, 0xfff0003f, RD_VS, RD_rd6, MSA}, 1815 {"copy_u.w", "+i,+e[+7]", 0x78f00019, 0xfff8003f, RD_VS, RD_rd6, MSA}, 1816 {"copy_u.d", "+i,+e[+6]", 0x78f80019, 0xfffc003f, RD_VS, RD_rd6, MSA64}, 1817 {"insert.b", "+d[+9],d", 0x79000019, 0xffe0003f, WR_VD|RD_VD, RD_d, MSA}, 1818 {"insert.h", "+d[+8],d", 0x79200019, 0xfff0003f, WR_VD|RD_VD, RD_d, MSA}, 1819 {"insert.w", "+d[+7],d", 0x79300019, 0xfff8003f, WR_VD|RD_VD, RD_d, MSA}, 1820 {"insert.d", "+d[+6],d", 0x79380019, 0xfffc003f, WR_VD|RD_VD, RD_d, MSA64}, 1821 {"insve.b", "+d[+9],+e[+~]", 0x79400019, 0xffe0003f, WR_VD|RD_VD|RD_VS, 0, MSA}, 1822 {"insve.h", "+d[+8],+e[+~]", 0x79600019, 0xfff0003f, WR_VD|RD_VD|RD_VS, 0, MSA}, 1823 {"insve.w", "+d[+7],+e[+~]", 0x79700019, 0xfff8003f, WR_VD|RD_VD|RD_VS, 0, MSA}, 1824 {"insve.d", "+d[+6],+e[+~]", 0x79780019, 0xfffc003f, WR_VD|RD_VD|RD_VS, 0, MSA}, 1825 {"bnz.b", "+f,p", 0x47800000, 0xffe00000, CBD|RD_VT, 0, MSA}, 1826 {"bnz.h", "+f,p", 0x47a00000, 0xffe00000, CBD|RD_VT, 0, MSA}, 1827 {"bnz.w", "+f,p", 0x47c00000, 0xffe00000, CBD|RD_VT, 0, MSA}, 1828 {"bnz.d", "+f,p", 0x47e00000, 0xffe00000, CBD|RD_VT, 0, MSA}, 1829 {"bz.b", "+f,p", 0x47000000, 0xffe00000, CBD|RD_VT, 0, MSA}, 1830 {"bz.h", "+f,p", 0x47200000, 0xffe00000, CBD|RD_VT, 0, MSA}, 1831 {"bz.w", "+f,p", 0x47400000, 0xffe00000, CBD|RD_VT, 0, MSA}, 1832 {"bz.d", "+f,p", 0x47600000, 0xffe00000, CBD|RD_VT, 0, MSA}, 1833 {"ldi.b", "+d,+0", 0x7b000007, 0xffe0003f, WR_VD, 0, MSA}, 1834 {"ldi.h", "+d,+0", 0x7b200007, 0xffe0003f, WR_VD, 0, MSA}, 1835 {"ldi.w", "+d,+0", 0x7b400007, 0xffe0003f, WR_VD, 0, MSA}, 1836 {"ldi.d", "+d,+0", 0x7b600007, 0xffe0003f, WR_VD, 0, MSA}, 1837 {"fcaf.w", "+d,+e,+f", 0x7800001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1838 {"fcaf.d", "+d,+e,+f", 0x7820001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1839 {"fcun.w", "+d,+e,+f", 0x7840001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1840 {"fcun.d", "+d,+e,+f", 0x7860001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1841 {"fceq.w", "+d,+e,+f", 0x7880001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1842 {"fceq.d", "+d,+e,+f", 0x78a0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1843 {"fcueq.w", "+d,+e,+f", 0x78c0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1844 {"fcueq.d", "+d,+e,+f", 0x78e0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1845 {"fclt.w", "+d,+e,+f", 0x7900001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1846 {"fclt.d", "+d,+e,+f", 0x7920001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1847 {"fcult.w", "+d,+e,+f", 0x7940001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1848 {"fcult.d", "+d,+e,+f", 0x7960001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1849 {"fcle.w", "+d,+e,+f", 0x7980001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1850 {"fcle.d", "+d,+e,+f", 0x79a0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1851 {"fcule.w", "+d,+e,+f", 0x79c0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1852 {"fcule.d", "+d,+e,+f", 0x79e0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1853 {"fsaf.w", "+d,+e,+f", 0x7a00001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1854 {"fsaf.d", "+d,+e,+f", 0x7a20001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1855 {"fsun.w", "+d,+e,+f", 0x7a40001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1856 {"fsun.d", "+d,+e,+f", 0x7a60001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1857 {"fseq.w", "+d,+e,+f", 0x7a80001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1858 {"fseq.d", "+d,+e,+f", 0x7aa0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1859 {"fsueq.w", "+d,+e,+f", 0x7ac0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1860 {"fsueq.d", "+d,+e,+f", 0x7ae0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1861 {"fslt.w", "+d,+e,+f", 0x7b00001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1862 {"fslt.d", "+d,+e,+f", 0x7b20001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1863 {"fsult.w", "+d,+e,+f", 0x7b40001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1864 {"fsult.d", "+d,+e,+f", 0x7b60001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1865 {"fsle.w", "+d,+e,+f", 0x7b80001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1866 {"fsle.d", "+d,+e,+f", 0x7ba0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1867 {"fsule.w", "+d,+e,+f", 0x7bc0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1868 {"fsule.d", "+d,+e,+f", 0x7be0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1869 {"fadd.w", "+d,+e,+f", 0x7800001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1870 {"fadd.d", "+d,+e,+f", 0x7820001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1871 {"fsub.w", "+d,+e,+f", 0x7840001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1872 {"fsub.d", "+d,+e,+f", 0x7860001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1873 {"fmul.w", "+d,+e,+f", 0x7880001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1874 {"fmul.d", "+d,+e,+f", 0x78a0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1875 {"fdiv.w", "+d,+e,+f", 0x78c0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1876 {"fdiv.d", "+d,+e,+f", 0x78e0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1877 {"fmadd.w", "+d,+e,+f", 0x7900001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1878 {"fmadd.d", "+d,+e,+f", 0x7920001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1879 {"fmsub.w", "+d,+e,+f", 0x7940001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1880 {"fmsub.d", "+d,+e,+f", 0x7960001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1881 {"fexp2.w", "+d,+e,+f", 0x79c0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1882 {"fexp2.d", "+d,+e,+f", 0x79e0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1883 {"fexdo.h", "+d,+e,+f", 0x7a00001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1884 {"fexdo.w", "+d,+e,+f", 0x7a20001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1885 {"ftq.h", "+d,+e,+f", 0x7a80001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1886 {"ftq.w", "+d,+e,+f", 0x7aa0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1887 {"fmin.w", "+d,+e,+f", 0x7b00001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1888 {"fmin.d", "+d,+e,+f", 0x7b20001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1889 {"fmin_a.w", "+d,+e,+f", 0x7b40001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1890 {"fmin_a.d", "+d,+e,+f", 0x7b60001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1891 {"fmax.w", "+d,+e,+f", 0x7b80001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1892 {"fmax.d", "+d,+e,+f", 0x7ba0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1893 {"fmax_a.w", "+d,+e,+f", 0x7bc0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1894 {"fmax_a.d", "+d,+e,+f", 0x7be0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1895 {"fcor.w", "+d,+e,+f", 0x7840001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1896 {"fcor.d", "+d,+e,+f", 0x7860001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1897 {"fcune.w", "+d,+e,+f", 0x7880001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1898 {"fcune.d", "+d,+e,+f", 0x78a0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1899 {"fcne.w", "+d,+e,+f", 0x78c0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1900 {"fcne.d", "+d,+e,+f", 0x78e0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1901 {"mul_q.h", "+d,+e,+f", 0x7900001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1902 {"mul_q.w", "+d,+e,+f", 0x7920001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1903 {"madd_q.h", "+d,+e,+f", 0x7940001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1904 {"madd_q.w", "+d,+e,+f", 0x7960001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1905 {"msub_q.h", "+d,+e,+f", 0x7980001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1906 {"msub_q.w", "+d,+e,+f", 0x79a0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1907 {"fsor.w", "+d,+e,+f", 0x7a40001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1908 {"fsor.d", "+d,+e,+f", 0x7a60001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1909 {"fsune.w", "+d,+e,+f", 0x7a80001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1910 {"fsune.d", "+d,+e,+f", 0x7aa0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1911 {"fsne.w", "+d,+e,+f", 0x7ac0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1912 {"fsne.d", "+d,+e,+f", 0x7ae0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1913 {"mulr_q.h", "+d,+e,+f", 0x7b00001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1914 {"mulr_q.w", "+d,+e,+f", 0x7b20001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1915 {"maddr_q.h", "+d,+e,+f", 0x7b40001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1916 {"maddr_q.w", "+d,+e,+f", 0x7b60001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1917 {"msubr_q.h", "+d,+e,+f", 0x7b80001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1918 {"msubr_q.w", "+d,+e,+f", 0x7ba0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA}, 1919 {"fclass.w", "+d,+e", 0x7b20001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1920 {"fclass.d", "+d,+e", 0x7b21001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1921 {"fsqrt.w", "+d,+e", 0x7b26001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1922 {"fsqrt.d", "+d,+e", 0x7b27001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1923 {"frsqrt.w", "+d,+e", 0x7b28001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1924 {"frsqrt.d", "+d,+e", 0x7b29001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1925 {"frcp.w", "+d,+e", 0x7b2a001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1926 {"frcp.d", "+d,+e", 0x7b2b001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1927 {"frint.w", "+d,+e", 0x7b2c001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1928 {"frint.d", "+d,+e", 0x7b2d001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1929 {"flog2.w", "+d,+e", 0x7b2e001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1930 {"flog2.d", "+d,+e", 0x7b2f001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1931 {"fexupl.w", "+d,+e", 0x7b30001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1932 {"fexupl.d", "+d,+e", 0x7b31001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1933 {"fexupr.w", "+d,+e", 0x7b32001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1934 {"fexupr.d", "+d,+e", 0x7b33001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1935 {"ffql.w", "+d,+e", 0x7b34001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1936 {"ffql.d", "+d,+e", 0x7b35001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1937 {"ffqr.w", "+d,+e", 0x7b36001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1938 {"ffqr.d", "+d,+e", 0x7b37001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1939 {"ftint_s.w", "+d,+e", 0x7b38001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1940 {"ftint_s.d", "+d,+e", 0x7b39001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1941 {"ftint_u.w", "+d,+e", 0x7b3a001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1942 {"ftint_u.d", "+d,+e", 0x7b3b001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1943 {"ffint_s.w", "+d,+e", 0x7b3c001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1944 {"ffint_s.d", "+d,+e", 0x7b3d001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1945 {"ffint_u.w", "+d,+e", 0x7b3e001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1946 {"ffint_u.d", "+d,+e", 0x7b3f001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1947 {"ftrunc_s.w", "+d,+e", 0x7b40001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1948 {"ftrunc_s.d", "+d,+e", 0x7b41001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1949 {"ftrunc_u.w", "+d,+e", 0x7b42001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1950 {"ftrunc_u.d", "+d,+e", 0x7b43001e, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1951 {"ctcmsa", "+h,d", 0x783e0019, 0xffff003f, COD, RD_d, MSA}, 1952 {"cfcmsa", "+i,+g", 0x787e0019, 0xffff003f, COD, 0, MSA}, 1953 {"move.v", "+d,+e", 0x78be0019, 0xffff003f, WR_VD|RD_VS, 0, MSA}, 1954 {"lsa", "d,v,t,+@", 0x00000005, 0xfc00073f, WR_d|RD_s|RD_t, 0, MSA}, 1955 {"dlsa", "d,v,t,+@", 0x00000015, 0xfc00073f, WR_d|RD_s|RD_t, 0, MSA64}, 1956 1957 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 }, 1958 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 }, 1959 {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ 1960 {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */ 1961 {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */ 1962 {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */ 1963 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */ 1964 {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 }, 1965 {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 }, 1966 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */ 1967 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */ 1968 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */ 1969 {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */ 1970 {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */ 1971 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/ 1972 1973 {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, 1974 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 1975 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 1976 {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 1977 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1978 {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, 1979 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 1980 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 1981 {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1982 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1983 {"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 1984 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 1985 {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 1986 {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1987 {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1988 {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1989 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 1990 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 1991 {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 1992 {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 1993 {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 1994 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 1995 {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 }, 1996 {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 1997 {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 }, 1998 {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 1999 {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2000 {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 }, 2001 {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX }, 2002 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2003 {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 }, 2004 {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2005 {"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2006 {"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2007 {"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2008 {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2009 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2010 /* b is at the top of the table. */ 2011 /* bal is at the top of the table. */ 2012 /* bc0[tf]l? are at the bottom of the table. */ 2013 {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 2014 {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 2015 {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 2016 {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D }, 2017 {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, 2018 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, 2019 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, 2020 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, 2021 {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 }, 2022 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 }, 2023 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, 2024 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, 2025 /* bc2* are at the bottom of the table. */ 2026 /* bc3* are at the bottom of the table. */ 2027 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 2028 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 2029 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, 2030 {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, 2031 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, 2032 {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 }, 2033 {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, 2034 {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, 2035 {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 }, 2036 {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 }, 2037 {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, 2038 {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, 2039 {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 }, 2040 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 }, 2041 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 2042 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 2043 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, 2044 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, 2045 {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, 2046 {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, 2047 {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 }, 2048 {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 }, 2049 {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, 2050 {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, 2051 {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 }, 2052 {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 }, 2053 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 2054 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 2055 {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, 2056 {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, 2057 {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 }, 2058 {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 }, 2059 {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, 2060 {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, 2061 {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 }, 2062 {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 }, 2063 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 2064 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 2065 {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, 2066 {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, 2067 {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 }, 2068 {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 }, 2069 {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, 2070 {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, 2071 {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 }, 2072 {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 }, 2073 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 2074 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 2075 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 }, 2076 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 }, 2077 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, 2078 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 2079 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, 2080 {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, 2081 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, 2082 {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 }, 2083 {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 }, 2084 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 }, 2085 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 }, 2086 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2087 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2088 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2089 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2090 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2091 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2092 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2093 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2094 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2095 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2096 {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2097 {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2098 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2099 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2100 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2101 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2102 {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2103 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2104 {"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2105 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2106 {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2107 {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2108 {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 2109 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2110 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2111 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2112 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2113 {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2114 {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2115 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2116 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2117 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2118 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2119 {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2120 {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2121 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2122 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2123 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2124 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2125 {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2126 {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2127 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2128 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2129 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2130 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2131 {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2132 {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2133 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2134 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2135 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2136 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2137 {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2138 {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2139 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2140 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2141 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2142 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2143 {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2144 {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2145 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2146 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2147 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2148 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2149 {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2150 {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2151 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2152 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2153 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2154 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2155 {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2156 {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2157 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2158 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2159 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2160 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2161 {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2162 {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2163 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2164 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2165 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2166 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2167 {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2168 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2169 {"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2170 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2171 {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2172 {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2173 {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 2174 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2175 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2176 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2177 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2178 {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2179 {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2180 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2181 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2182 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2183 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2184 {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2185 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2186 {"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2187 {"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2188 {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2189 {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2190 {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, 2191 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, 2192 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, 2193 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, 2194 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, 2195 {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2196 {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, 2197 {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2198 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2199 {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2200 {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2201 {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2202 {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2203 {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2204 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2205 {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2206 {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2207 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2208 {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2209 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2210 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2211 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2212 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2213 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2214 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2215 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2216 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2217 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2218 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2219 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2220 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2221 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2222 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2223 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2224 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2225 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2226 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2227 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2228 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2229 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2230 {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2231 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2232 {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2233 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2234 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2235 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2236 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2237 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2238 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2239 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2240 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2241 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2242 {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2243 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, 2244 {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, 2245 /* CW4010 instructions which are aliases for the cache instruction. */ 2246 {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, 2247 {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, 2248 {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, 2249 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, 2250 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3}, 2251 {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3}, 2252 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 2253 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 2254 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2255 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2256 {"mfhc0", "t,G,H", 0x40400000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I33}, 2257 {"mthc0", "t,G,H", 0x40c00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I33}, 2258 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, 2259 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, 2260 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, 2261 /* cfc2 is at the bottom of the table. */ 2262 /* cfc3 is at the bottom of the table. */ 2263 {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, 2264 {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, 2265 {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 2266 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, 2267 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 }, 2268 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 2269 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, 2270 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, 2271 /* ctc2 is at the bottom of the table. */ 2272 /* ctc3 is at the bottom of the table. */ 2273 {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, 2274 {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, 2275 {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 }, 2276 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 2277 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 2278 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 2279 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 2280 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 2281 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 2282 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 2283 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 2284 {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, 2285 {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, 2286 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, 2287 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 2288 {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, 2289 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 }, 2290 {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, 2291 {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, 2292 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 2293 {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 }, 2294 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 }, 2295 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 }, 2296 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 2297 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 }, 2298 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 }, 2299 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, 2300 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 }, 2301 /* dctr and dctw are used on the r5000. */ 2302 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 }, 2303 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 }, 2304 {"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 }, 2305 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 }, 2306 {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 }, 2307 {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 }, 2308 {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 }, 2309 /* For ddiv, see the comments about div. */ 2310 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 2311 {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 }, 2312 {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 }, 2313 /* For ddivu, see the comments about div. */ 2314 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 2315 {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 }, 2316 {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 }, 2317 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2318 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2319 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 }, 2320 {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 }, 2321 {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 }, 2322 {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 }, 2323 /* The MIPS assembler treats the div opcode with two operands as 2324 though the first operand appeared twice (the first operand is both 2325 a source and a destination). To get the div machine instruction, 2326 you must use an explicit destination of $0. */ 2327 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2328 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2329 {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, 2330 {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 }, 2331 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 2332 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 2333 {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 2334 /* For divu, see the comments about div. */ 2335 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2336 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2337 {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, 2338 {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 }, 2339 {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 }, 2340 {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 }, 2341 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */ 2342 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */ 2343 {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 }, 2344 {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 2345 {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 2346 {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 2347 {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 2348 {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 2349 {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 2350 {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 2351 {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 }, 2352 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 }, 2353 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 }, 2354 {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, 2355 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 }, 2356 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 }, 2357 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2358 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 }, 2359 {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, 2360 {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 }, 2361 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, 2362 {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 }, 2363 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, 2364 {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, 2365 /* dmfc2 is at the bottom of the table. */ 2366 /* dmtc2 is at the bottom of the table. */ 2367 /* dmfc3 is at the bottom of the table. */ 2368 /* dmtc3 is at the bottom of the table. */ 2369 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, 2370 {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, 2371 {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 }, 2372 {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 }, 2373 {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 }, 2374 {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 }, 2375 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 2376 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 2377 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */ 2378 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/ 2379 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 2380 {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 }, 2381 {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 }, 2382 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 }, 2383 {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 }, 2384 {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 }, 2385 {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 }, 2386 {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 }, 2387 {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 }, 2388 {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 }, 2389 {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 }, 2390 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, 2391 {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 }, 2392 {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 }, 2393 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 }, 2394 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 }, 2395 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 }, 2396 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 }, 2397 {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 }, 2398 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 }, 2399 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 }, 2400 {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 }, 2401 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 2402 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, 2403 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */ 2404 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */ 2405 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 }, 2406 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 2407 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, 2408 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */ 2409 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */ 2410 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 }, 2411 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, 2412 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, 2413 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */ 2414 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */ 2415 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 }, 2416 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 2417 {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 }, 2418 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, 2419 {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 }, 2420 {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 }, 2421 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2422 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 }, 2423 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 }, 2424 {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 }, 2425 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2426 {"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 }, 2427 {"eretnc", "", 0x42000058, 0xffffffff, 0, 0, I33}, 2428 {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 }, 2429 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 }, 2430 {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 }, 2431 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 2432 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 2433 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2434 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2435 {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, 2436 {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, 2437 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, 2438 {"jr", "s", 0x00000009, 0xfc1fffff, UBD|RD_s, 0, I32R6 }, /* jalr */ 2439 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with 2440 the same hazard barrier effect. */ 2441 {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, 2442 {"jr.hb", "s", 0x00000409, 0xfc1fffff, UBD|RD_s, 0, I32R6 }, /* jalr.hb */ 2443 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ 2444 /* SVR4 PIC code requires special handling for j, so it must be a 2445 macro. */ 2446 {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 }, 2447 /* This form of j is used by the disassembler and internally by the 2448 assembler, but will never match user input (because the line above 2449 will match first). */ 2450 {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, 2451 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, 2452 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, 2453 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr 2454 with the same hazard barrier effect. */ 2455 {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 }, 2456 {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 }, 2457 /* SVR4 PIC code requires special handling for jal, so it must be a 2458 macro. */ 2459 {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, 2460 {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 }, 2461 {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 }, 2462 /* This form of jal is used by the disassembler and internally by the 2463 assembler, but will never match user input (because the line above 2464 will match first). */ 2465 {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, 2466 {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 }, 2467 {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, 2468 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 2469 {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, 2470 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 2471 {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 }, 2472 {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, 2473 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, 2474 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, 2475 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, 2476 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, 2477 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, 2478 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, 2479 {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 }, 2480 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */ 2481 {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 }, 2482 {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 }, 2483 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, 2484 {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 }, 2485 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 }, 2486 {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 }, 2487 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, 2488 {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 }, 2489 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 }, 2490 {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 }, 2491 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, 2492 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 2493 {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 }, 2494 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 2495 {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 }, 2496 /* li is at the start of the table. */ 2497 {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 }, 2498 {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 }, 2499 {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 }, 2500 {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 }, 2501 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, 2502 {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 }, 2503 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, 2504 {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 }, 2505 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, 2506 {"aui", "s,t,u", 0x3c000000, 0xfc000000, RD_s|WR_t, 0, I32R6}, 2507 {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55}, 2508 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 2509 {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, 2510 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 2511 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 }, 2512 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, 2513 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, 2514 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 2515 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 2516 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */ 2517 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 }, 2518 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 2519 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 }, 2520 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, 2521 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 }, 2522 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 2523 {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 }, 2524 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ 2525 {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */ 2526 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, 2527 {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 }, 2528 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */ 2529 {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */ 2530 {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 }, 2531 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, 2532 {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, 2533 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, 2534 {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT }, 2535 {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 2536 {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2537 {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 2538 {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 2539 {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2540 {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 2541 {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 2542 {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2543 {"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 2544 {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 2545 {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2546 {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, 2547 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, 2548 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, 2549 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 2550 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 2551 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 2552 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 2553 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 2554 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, 2555 {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2556 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 2557 {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, 2558 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 2559 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 2560 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, 2561 {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2562 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 2563 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, 2564 {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2565 {"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2566 {"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2567 {"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2568 {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2569 {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, 2570 {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 }, 2571 {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 2572 {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 2573 {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 2574 {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 2575 {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 }, 2576 {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, 2577 {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 }, 2578 {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 2579 {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 }, 2580 {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, 2581 {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, 2582 {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 }, 2583 {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, 2584 {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 2585 {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 2586 {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 }, 2587 {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 }, 2588 {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 }, 2589 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 }, 2590 {"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, 2591 {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 }, 2592 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, 2593 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 }, 2594 {"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, 2595 {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, 2596 /* mfc2 is at the bottom of the table. */ 2597 /* mfhc2 is at the bottom of the table. */ 2598 /* mfc3 is at the bottom of the table. */ 2599 {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, 2600 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, 2601 {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, 2602 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, 2603 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, 2604 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, 2605 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2606 {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2607 {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2608 {"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2609 {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2610 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 2611 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 2612 {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 2613 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, 2614 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, 2615 {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 2616 {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 2617 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, 2618 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, 2619 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, 2620 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, 2621 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, 2622 {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 2623 {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 2624 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, 2625 {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, 2626 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, 2627 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, 2628 {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 2629 {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, 2630 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, 2631 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, 2632 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, 2633 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, 2634 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, 2635 {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 2636 {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, 2637 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, 2638 {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, 2639 {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2640 {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2641 {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2642 {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2643 /* move is at the top of the table. */ 2644 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2645 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 2646 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 2647 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 2648 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 2649 {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 2650 {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2651 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, 2652 {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, 2653 {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 2654 {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, 2655 {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, 2656 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, 2657 {"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, 2658 {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 }, 2659 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, 2660 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 }, 2661 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, 2662 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, 2663 /* mtc2 is at the bottom of the table. */ 2664 /* mthc2 is at the bottom of the table. */ 2665 /* mtc3 is at the bottom of the table. */ 2666 {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, 2667 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, 2668 {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, 2669 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, 2670 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, 2671 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, 2672 {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 2673 {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 2674 {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 }, 2675 {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, 2676 {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 }, 2677 {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, 2678 {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 2679 {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 2680 {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 }, 2681 {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 }, 2682 {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, 2683 {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 }, 2684 {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 }, 2685 {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 2686 {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 2687 {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 }, 2688 {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 }, 2689 {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 }, 2690 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 2691 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 2692 {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2693 {"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2694 {"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2695 {"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2696 {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2697 {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2698 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55}, 2699 {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 }, 2700 {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, 2701 {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 }, 2702 {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2703 {"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2704 {"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2705 {"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2706 {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2707 {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2708 {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2709 {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2710 {"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2711 {"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2712 {"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2713 {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2714 {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 }, 2715 {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 }, 2716 {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 }, 2717 {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 }, 2718 {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 2719 {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2720 {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2721 {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2722 {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2723 {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2724 {"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2725 {"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2726 {"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2727 {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2728 {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2729 {"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2730 {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2731 {"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, 2732 {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2733 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, 2734 {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, 2735 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 2736 {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, 2737 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, 2738 {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, 2739 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, 2740 {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, 2741 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ 2742 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ 2743 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, 2744 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, 2745 {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, 2746 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 2747 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 2748 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 2749 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, 2750 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, 2751 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, 2752 /* nop is at the start of the table. */ 2753 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2754 {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, 2755 {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2756 {"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2757 {"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2758 {"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2759 {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2760 {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/ 2761 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2762 {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 }, 2763 {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2764 {"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2765 {"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2766 {"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2767 {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2768 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2769 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 2770 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 }, 2771 {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 }, 2772 {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2773 {"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2774 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2775 {"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2776 {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2777 {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2778 {"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2779 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2780 {"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2781 {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2782 {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2783 {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2784 /* pref and prefx are at the start of the table. */ 2785 {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2786 {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2787 {"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT }, 2788 {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2789 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2790 {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2791 {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2792 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2793 {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2794 {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, 2795 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 2796 {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, 2797 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, 2798 {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2799 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, 2800 {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, 2801 {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2802 {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2803 {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 2804 {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2805 {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2806 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2807 {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, 2808 {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 }, 2809 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 }, 2810 {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, 2811 {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 }, 2812 {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 }, 2813 {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 }, 2814 {"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 }, 2815 {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2816 {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2817 {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2818 {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2819 {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2820 {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2821 {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 }, 2822 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, 2823 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, 2824 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, 2825 {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, 2826 {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, 2827 {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, 2828 {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, 2829 {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, 2830 {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, 2831 {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, 2832 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 2833 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 2834 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 2835 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2836 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, 2837 {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2838 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 }, 2839 {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D }, 2840 {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2841 {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D }, 2842 {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D }, 2843 {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2844 {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D }, 2845 {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2846 {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 }, 2847 {"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 }, 2848 {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX }, 2849 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2850 {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 }, 2851 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 }, 2852 {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 }, 2853 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 }, 2854 {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 }, 2855 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2856 {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, 2857 {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, 2858 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 }, 2859 {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 }, 2860 {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, 2861 {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 }, 2862 {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 }, 2863 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2864 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2865 {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, 2866 {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 }, 2867 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 }, 2868 {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 }, 2869 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 }, 2870 {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 }, 2871 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 }, 2872 {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 }, 2873 {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 }, 2874 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2875 {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, 2876 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, 2877 {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 }, 2878 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 }, 2879 {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 }, 2880 {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 }, 2881 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, 2882 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 }, 2883 {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 }, 2884 {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 }, 2885 {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 }, 2886 {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 }, 2887 {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 }, 2888 {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 }, 2889 {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 }, 2890 {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 }, 2891 {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 }, 2892 {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 }, 2893 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2894 {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 }, 2895 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2896 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2897 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2898 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2899 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2900 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2901 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2902 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2903 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2904 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2905 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2906 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2907 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2908 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2909 {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 }, 2910 {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 }, 2911 {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 }, 2912 {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 }, 2913 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2914 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */ 2915 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2916 {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2917 {"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2918 {"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2919 {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2920 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2921 {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 }, 2922 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2923 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 2924 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2925 {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 }, 2926 {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 }, 2927 {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 }, 2928 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 }, 2929 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 2930 {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 }, 2931 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2932 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */ 2933 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2934 {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2935 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, 2936 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */ 2937 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 }, 2938 {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2939 {"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2940 {"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2941 {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2942 /* ssnop is at the start of the table. */ 2943 {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 }, 2944 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2945 {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 }, 2946 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 }, 2947 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, 2948 {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 2949 {"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2950 {"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 2951 {"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 2952 {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, 2953 {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 2954 {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2955 {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2956 {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 2957 {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 2958 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 2959 {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, 2960 {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 }, 2961 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55}, 2962 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2963 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, 2964 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 }, 2965 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 }, 2966 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, 2967 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, 2968 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2969 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2970 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */ 2971 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 }, 2972 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 }, 2973 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 }, 2974 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 }, 2975 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 }, 2976 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2977 {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 }, 2978 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ 2979 {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */ 2980 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, 2981 {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 }, 2982 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */ 2983 {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */ 2984 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 }, 2985 {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 }, 2986 {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 }, 2987 {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 }, 2988 {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 }, 2989 {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 }, 2990 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 }, 2991 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2992 {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2993 {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2994 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */ 2995 {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 }, 2996 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 2997 {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 2998 {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 2999 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */ 3000 {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 }, 3001 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 3002 {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 3003 {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 3004 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ 3005 {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, 3006 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, 3007 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, 3008 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, 3009 {"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, I32 }, 3010 {"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, I32 }, 3011 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 }, 3012 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 3013 {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 3014 {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 3015 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */ 3016 {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 }, 3017 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 3018 {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 3019 {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 3020 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */ 3021 {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 }, 3022 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, 3023 {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 }, 3024 {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, 3025 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */ 3026 {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 }, 3027 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, 3028 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, 3029 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 3030 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, 3031 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 }, 3032 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 3033 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, 3034 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 }, 3035 {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, 3036 {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, 3037 {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, 3038 {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, 3039 {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, 3040 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, 3041 {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, 3042 {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, 3043 {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, 3044 {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, 3045 {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, 3046 {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, 3047 {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, 3048 {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, 3049 {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 }, 3050 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, 3051 {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX }, 3052 {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, 3053 {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 }, 3054 {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, 3055 {"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 }, 3056 {"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 }, 3057 {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, 3058 {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, 3059 {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, 3060 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, 3061 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, 3062 {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, 3063 {"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 3064 {"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, 3065 {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, 3066 {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, 3067 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 }, 3068 {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 }, 3069 {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 }, 3070 3071 /* User Defined Instruction. */ 3072 {"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3073 {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3074 {"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3075 {"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3076 {"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3077 {"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3078 {"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3079 {"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3080 {"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3081 {"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3082 {"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3083 {"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3084 {"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3085 {"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3086 {"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3087 {"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3088 {"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3089 {"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3090 {"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3091 {"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3092 {"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3093 {"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3094 {"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3095 {"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3096 {"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3097 {"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3098 {"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3099 {"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3100 {"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3101 {"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3102 {"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3103 {"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3104 {"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3105 {"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3106 {"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3107 {"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3108 {"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3109 {"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3110 {"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3111 {"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3112 {"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3113 {"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3114 {"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3115 {"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3116 {"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3117 {"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3118 {"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3119 {"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3120 {"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3121 {"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3122 {"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3123 {"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3124 {"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3125 {"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3126 {"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3127 {"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3128 {"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3129 {"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3130 {"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3131 {"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3132 {"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3133 {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3134 {"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3135 {"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, 3136 3137 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format 3138 instructions so they are here for the latters to take precedence. */ 3139 {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 3140 {"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 }, 3141 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 3142 {"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 }, 3143 {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 3144 {"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 }, 3145 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 3146 {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, 3147 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, 3148 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 3149 {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 }, 3150 {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 }, 3151 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 }, 3152 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, 3153 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, 3154 {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, 3155 {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, 3156 {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 }, 3157 {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 }, 3158 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 }, 3159 {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, 3160 {"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 3161 {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 3162 {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, 3163 3164 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 3165 instructions, so they are here for the latters to take precedence. */ 3166 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 3167 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 3168 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 3169 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 3170 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, 3171 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, 3172 {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, 3173 {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, 3174 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, 3175 {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, 3176 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, 3177 {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, 3178 3179 /* No hazard protection on coprocessor instructions--they shouldn't 3180 change the state of the processor and if they do it's up to the 3181 user to put in nops as necessary. These are at the end so that the 3182 disassembler recognizes more specific versions first. */ 3183 {"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 }, 3184 {"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 }, 3185 {"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 }, 3186 {"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 }, 3187 {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 }, 3188 {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 }, 3189 {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, 3190 {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }, 3191 /* Conflicts with the 4650's "mul" instruction. Nobody's using the 3192 4010 any more, so move this insn out of the way. If the object 3193 format gave us more info, we could do this right. */ 3194 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 }, 3195 /* MIPS DSP ASE */ 3196 {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3197 {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3198 {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3199 {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3200 {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3201 {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3202 {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3203 {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3204 {"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3205 {"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3206 {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3207 {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3208 {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3209 {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3210 {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3211 {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3212 {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3213 {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3214 {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 }, 3215 {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 }, 3216 {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 3217 {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 3218 {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 3219 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3220 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3221 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3222 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3223 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3224 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3225 {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 3226 {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 3227 {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 3228 {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 3229 {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 3230 {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 3231 {"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 3232 {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 3233 {"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 3234 {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 3235 {"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 }, 3236 {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 }, 3237 {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 }, 3238 {"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 }, 3239 {"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 3240 {"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 3241 {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 3242 {"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 3243 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 3244 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 3245 {"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 3246 {"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 3247 {"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 3248 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 3249 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 3250 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 3251 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 3252 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 3253 {"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, 3254 {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, 3255 {"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 }, 3256 {"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3257 {"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3258 {"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3259 {"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3260 {"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 }, 3261 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3262 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3263 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3264 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3265 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3266 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3267 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3268 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3269 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3270 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3271 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3272 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3273 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3274 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3275 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3276 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3277 {"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 }, 3278 {"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 }, 3279 {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 }, 3280 {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, 3281 {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 3282 {"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 3283 {"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 3284 {"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 3285 {"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 3286 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 3287 {"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 3288 {"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 3289 {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 }, 3290 {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, 3291 {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, 3292 {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 3293 {"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 }, 3294 {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 3295 {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, 3296 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3297 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3298 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3299 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3300 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3301 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3302 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3303 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3304 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3305 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3306 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3307 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3308 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3309 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3310 {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3311 {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, 3312 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 3313 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 3314 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 3315 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 3316 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 3317 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 3318 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 3319 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 3320 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, 3321 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, 3322 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3323 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, 3324 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, 3325 {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3326 {"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3327 {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3328 {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3329 {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3330 {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3331 {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3332 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3333 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3334 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3335 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3336 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3337 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3338 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3339 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3340 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3341 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3342 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3343 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3344 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3345 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3346 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3347 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3348 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3349 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3350 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3351 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3352 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3353 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3354 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3355 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3356 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3357 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3358 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3359 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3360 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3361 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3362 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3363 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3364 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3365 {"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 }, 3366 {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 }, 3367 {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 }, 3368 {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 }, 3369 {"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 }, 3370 {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 }, 3371 {"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 }, 3372 {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 }, 3373 {"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 }, 3374 {"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3375 {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3376 {"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3377 {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, 3378 {"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, 3379 {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 }, 3380 {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 }, 3381 {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 }, 3382 {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 3383 {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 3384 {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 }, 3385 {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 3386 {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 3387 {"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 3388 {"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 3389 {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 }, 3390 {"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3391 {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3392 {"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3393 {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3394 {"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3395 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3396 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3397 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3398 {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3399 {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 3400 {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 3401 {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 3402 {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 }, 3403 {"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 }, 3404 {"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 }, 3405 {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 }, 3406 {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3407 {"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3408 {"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3409 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3410 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3411 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3412 {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3413 {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 }, 3414 {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 }, 3415 {"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3416 {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3417 {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3418 {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3419 {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3420 {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3421 {"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3422 {"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3423 {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3424 {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3425 {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3426 {"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, 3427 {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, 3428 {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 }, 3429 {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, 3430 /* MIPS DSP ASE Rev2 */ 3431 {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, 3432 {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3433 {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3434 {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3435 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3436 {"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 3437 {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, 3438 {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, 3439 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3440 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3441 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3442 {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 3443 {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 3444 {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 3445 {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 3446 {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 3447 {"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 3448 {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, 3449 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 3450 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3451 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 3452 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 3453 {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, 3454 {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, 3455 {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, 3456 {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3457 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3458 {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, 3459 {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3460 {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3461 {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3462 {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3463 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3464 {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3465 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3466 {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3467 {"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3468 {"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3469 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3470 {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3471 {"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, 3472 {"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 3473 {"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 3474 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 3475 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 3476 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 3477 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, 3478 /* Move bc0* after mftr and mttr to avoid opcode collision. */ 3479 {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 }, 3480 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 3481 {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 }, 3482 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, 3483 /* ST Microelectronics Loongson-2E and -2F. */ 3484 {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3485 {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3486 {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3487 {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3488 {"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3489 {"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3490 {"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3491 {"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3492 {"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3493 {"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3494 {"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3495 {"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3496 {"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3497 {"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3498 {"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3499 {"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3500 {"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3501 {"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3502 {"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3503 {"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3504 {"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3505 {"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3506 {"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E }, 3507 {"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F }, 3508 }; 3509 3510 #define MIPS_NUM_OPCODES \ 3511 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) 3512 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; 3513 3514 /* const removed from the following to allow for dynamic extensions to the 3515 * built-in instruction set. */ 3516 struct mips_opcode *mips_opcodes = 3517 (struct mips_opcode *) mips_builtin_opcodes; 3518 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; 3519 #undef MIPS_NUM_OPCODES 3520 3521 /* Mips instructions are at maximum this many bytes long. */ 3522 #define INSNLEN 4 3523 3524 3525 /* FIXME: These should be shared with gdb somehow. */ 3526 3527 struct mips_cp0sel_name 3528 { 3529 unsigned int cp0reg; 3530 unsigned int sel; 3531 const char * const name; 3532 }; 3533 3534 #if 0 3535 /* The mips16 registers. */ 3536 static const unsigned int mips16_to_32_reg_map[] = 3537 { 3538 16, 17, 2, 3, 4, 5, 6, 7 3539 }; 3540 3541 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] 3542 #endif 3543 3544 static const char * const mips_gpr_names_numeric[32] = 3545 { 3546 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 3547 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3548 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3549 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 3550 }; 3551 3552 static const char * const mips_gpr_names_oldabi[32] = 3553 { 3554 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 3555 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 3556 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3557 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 3558 }; 3559 3560 static const char * const mips_gpr_names_newabi[32] = 3561 { 3562 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 3563 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 3564 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3565 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 3566 }; 3567 3568 static const char * const mips_fpr_names_numeric[32] = 3569 { 3570 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 3571 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 3572 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 3573 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 3574 }; 3575 3576 static const char * const mips_fpr_names_32[32] = 3577 { 3578 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 3579 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 3580 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 3581 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 3582 }; 3583 3584 static const char * const mips_fpr_names_n32[32] = 3585 { 3586 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 3587 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 3588 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 3589 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 3590 }; 3591 3592 static const char * const mips_fpr_names_64[32] = 3593 { 3594 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 3595 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 3596 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 3597 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 3598 }; 3599 3600 static const char * const mips_wr_names[32] = { 3601 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3602 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3603 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3604 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "w31" 3605 }; 3606 3607 static const char * const mips_cp0_names_numeric[32] = 3608 { 3609 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 3610 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3611 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3612 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 3613 }; 3614 3615 static const char * const mips_cp0_names_mips3264[32] = 3616 { 3617 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 3618 "c0_context", "c0_pagemask", "c0_wired", "$7", 3619 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 3620 "c0_status", "c0_cause", "c0_epc", "c0_prid", 3621 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 3622 "c0_xcontext", "$21", "$22", "c0_debug", 3623 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 3624 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 3625 }; 3626 3627 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 3628 { 3629 { 4, 1, "c0_contextconfig" }, 3630 { 0, 1, "c0_mvpcontrol" }, 3631 { 0, 2, "c0_mvpconf0" }, 3632 { 0, 3, "c0_mvpconf1" }, 3633 { 1, 1, "c0_vpecontrol" }, 3634 { 1, 2, "c0_vpeconf0" }, 3635 { 1, 3, "c0_vpeconf1" }, 3636 { 1, 4, "c0_yqmask" }, 3637 { 1, 5, "c0_vpeschedule" }, 3638 { 1, 6, "c0_vpeschefback" }, 3639 { 2, 1, "c0_tcstatus" }, 3640 { 2, 2, "c0_tcbind" }, 3641 { 2, 3, "c0_tcrestart" }, 3642 { 2, 4, "c0_tchalt" }, 3643 { 2, 5, "c0_tccontext" }, 3644 { 2, 6, "c0_tcschedule" }, 3645 { 2, 7, "c0_tcschefback" }, 3646 { 5, 1, "c0_pagegrain" }, 3647 { 6, 1, "c0_srsconf0" }, 3648 { 6, 2, "c0_srsconf1" }, 3649 { 6, 3, "c0_srsconf2" }, 3650 { 6, 4, "c0_srsconf3" }, 3651 { 6, 5, "c0_srsconf4" }, 3652 { 12, 1, "c0_intctl" }, 3653 { 12, 2, "c0_srsctl" }, 3654 { 12, 3, "c0_srsmap" }, 3655 { 15, 1, "c0_ebase" }, 3656 { 16, 1, "c0_config1" }, 3657 { 16, 2, "c0_config2" }, 3658 { 16, 3, "c0_config3" }, 3659 { 18, 1, "c0_watchlo,1" }, 3660 { 18, 2, "c0_watchlo,2" }, 3661 { 18, 3, "c0_watchlo,3" }, 3662 { 18, 4, "c0_watchlo,4" }, 3663 { 18, 5, "c0_watchlo,5" }, 3664 { 18, 6, "c0_watchlo,6" }, 3665 { 18, 7, "c0_watchlo,7" }, 3666 { 19, 1, "c0_watchhi,1" }, 3667 { 19, 2, "c0_watchhi,2" }, 3668 { 19, 3, "c0_watchhi,3" }, 3669 { 19, 4, "c0_watchhi,4" }, 3670 { 19, 5, "c0_watchhi,5" }, 3671 { 19, 6, "c0_watchhi,6" }, 3672 { 19, 7, "c0_watchhi,7" }, 3673 { 23, 1, "c0_tracecontrol" }, 3674 { 23, 2, "c0_tracecontrol2" }, 3675 { 23, 3, "c0_usertracedata" }, 3676 { 23, 4, "c0_tracebpc" }, 3677 { 25, 1, "c0_perfcnt,1" }, 3678 { 25, 2, "c0_perfcnt,2" }, 3679 { 25, 3, "c0_perfcnt,3" }, 3680 { 25, 4, "c0_perfcnt,4" }, 3681 { 25, 5, "c0_perfcnt,5" }, 3682 { 25, 6, "c0_perfcnt,6" }, 3683 { 25, 7, "c0_perfcnt,7" }, 3684 { 27, 1, "c0_cacheerr,1" }, 3685 { 27, 2, "c0_cacheerr,2" }, 3686 { 27, 3, "c0_cacheerr,3" }, 3687 { 28, 1, "c0_datalo" }, 3688 { 28, 2, "c0_taglo1" }, 3689 { 28, 3, "c0_datalo1" }, 3690 { 28, 4, "c0_taglo2" }, 3691 { 28, 5, "c0_datalo2" }, 3692 { 28, 6, "c0_taglo3" }, 3693 { 28, 7, "c0_datalo3" }, 3694 { 29, 1, "c0_datahi" }, 3695 { 29, 2, "c0_taghi1" }, 3696 { 29, 3, "c0_datahi1" }, 3697 { 29, 4, "c0_taghi2" }, 3698 { 29, 5, "c0_datahi2" }, 3699 { 29, 6, "c0_taghi3" }, 3700 { 29, 7, "c0_datahi3" }, 3701 }; 3702 3703 static const char * const mips_cp0_names_mips3264r2[32] = 3704 { 3705 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 3706 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 3707 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 3708 "c0_status", "c0_cause", "c0_epc", "c0_prid", 3709 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 3710 "c0_xcontext", "$21", "$22", "c0_debug", 3711 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 3712 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 3713 }; 3714 3715 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 3716 { 3717 { 4, 1, "c0_contextconfig" }, 3718 { 5, 1, "c0_pagegrain" }, 3719 { 12, 1, "c0_intctl" }, 3720 { 12, 2, "c0_srsctl" }, 3721 { 12, 3, "c0_srsmap" }, 3722 { 15, 1, "c0_ebase" }, 3723 { 16, 1, "c0_config1" }, 3724 { 16, 2, "c0_config2" }, 3725 { 16, 3, "c0_config3" }, 3726 { 18, 1, "c0_watchlo,1" }, 3727 { 18, 2, "c0_watchlo,2" }, 3728 { 18, 3, "c0_watchlo,3" }, 3729 { 18, 4, "c0_watchlo,4" }, 3730 { 18, 5, "c0_watchlo,5" }, 3731 { 18, 6, "c0_watchlo,6" }, 3732 { 18, 7, "c0_watchlo,7" }, 3733 { 19, 1, "c0_watchhi,1" }, 3734 { 19, 2, "c0_watchhi,2" }, 3735 { 19, 3, "c0_watchhi,3" }, 3736 { 19, 4, "c0_watchhi,4" }, 3737 { 19, 5, "c0_watchhi,5" }, 3738 { 19, 6, "c0_watchhi,6" }, 3739 { 19, 7, "c0_watchhi,7" }, 3740 { 23, 1, "c0_tracecontrol" }, 3741 { 23, 2, "c0_tracecontrol2" }, 3742 { 23, 3, "c0_usertracedata" }, 3743 { 23, 4, "c0_tracebpc" }, 3744 { 25, 1, "c0_perfcnt,1" }, 3745 { 25, 2, "c0_perfcnt,2" }, 3746 { 25, 3, "c0_perfcnt,3" }, 3747 { 25, 4, "c0_perfcnt,4" }, 3748 { 25, 5, "c0_perfcnt,5" }, 3749 { 25, 6, "c0_perfcnt,6" }, 3750 { 25, 7, "c0_perfcnt,7" }, 3751 { 27, 1, "c0_cacheerr,1" }, 3752 { 27, 2, "c0_cacheerr,2" }, 3753 { 27, 3, "c0_cacheerr,3" }, 3754 { 28, 1, "c0_datalo" }, 3755 { 28, 2, "c0_taglo1" }, 3756 { 28, 3, "c0_datalo1" }, 3757 { 28, 4, "c0_taglo2" }, 3758 { 28, 5, "c0_datalo2" }, 3759 { 28, 6, "c0_taglo3" }, 3760 { 28, 7, "c0_datalo3" }, 3761 { 29, 1, "c0_datahi" }, 3762 { 29, 2, "c0_taghi1" }, 3763 { 29, 3, "c0_datahi1" }, 3764 { 29, 4, "c0_taghi2" }, 3765 { 29, 5, "c0_datahi2" }, 3766 { 29, 6, "c0_taghi3" }, 3767 { 29, 7, "c0_datahi3" }, 3768 }; 3769 3770 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 3771 static const char * const mips_cp0_names_sb1[32] = 3772 { 3773 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 3774 "c0_context", "c0_pagemask", "c0_wired", "$7", 3775 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 3776 "c0_status", "c0_cause", "c0_epc", "c0_prid", 3777 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 3778 "c0_xcontext", "$21", "$22", "c0_debug", 3779 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 3780 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 3781 }; 3782 3783 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 3784 { 3785 { 16, 1, "c0_config1" }, 3786 { 18, 1, "c0_watchlo,1" }, 3787 { 19, 1, "c0_watchhi,1" }, 3788 { 22, 0, "c0_perftrace" }, 3789 { 23, 3, "c0_edebug" }, 3790 { 25, 1, "c0_perfcnt,1" }, 3791 { 25, 2, "c0_perfcnt,2" }, 3792 { 25, 3, "c0_perfcnt,3" }, 3793 { 25, 4, "c0_perfcnt,4" }, 3794 { 25, 5, "c0_perfcnt,5" }, 3795 { 25, 6, "c0_perfcnt,6" }, 3796 { 25, 7, "c0_perfcnt,7" }, 3797 { 26, 1, "c0_buserr_pa" }, 3798 { 27, 1, "c0_cacheerr_d" }, 3799 { 27, 3, "c0_cacheerr_d_pa" }, 3800 { 28, 1, "c0_datalo_i" }, 3801 { 28, 2, "c0_taglo_d" }, 3802 { 28, 3, "c0_datalo_d" }, 3803 { 29, 1, "c0_datahi_i" }, 3804 { 29, 2, "c0_taghi_d" }, 3805 { 29, 3, "c0_datahi_d" }, 3806 }; 3807 3808 static const char * const mips_hwr_names_numeric[32] = 3809 { 3810 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 3811 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3812 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3813 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 3814 }; 3815 3816 static const char * const mips_hwr_names_mips3264r2[32] = 3817 { 3818 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 3819 "$4", "$5", "$6", "$7", 3820 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3821 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3822 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 3823 }; 3824 3825 static const char * const mips_msa_control_names_mips3264r2[32] = { 3826 "MSAIR", "MSACSR", "$2", "$3", "$4", "$5", "$6", "$7", 3827 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3828 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3829 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 3830 }; 3831 3832 struct mips_abi_choice 3833 { 3834 const char *name; 3835 const char * const *gpr_names; 3836 const char * const *fpr_names; 3837 }; 3838 3839 static struct mips_abi_choice mips_abi_choices[] = 3840 { 3841 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 3842 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 3843 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 3844 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 3845 }; 3846 3847 struct mips_arch_choice 3848 { 3849 const char *name; 3850 int bfd_mach_valid; 3851 unsigned long bfd_mach; 3852 int processor; 3853 int isa; 3854 const char * const *cp0_names; 3855 const struct mips_cp0sel_name *cp0sel_names; 3856 unsigned int cp0sel_names_len; 3857 const char * const *hwr_names; 3858 }; 3859 3860 #define bfd_mach_mips3000 3000 3861 #define bfd_mach_mips3900 3900 3862 #define bfd_mach_mips4000 4000 3863 #define bfd_mach_mips4010 4010 3864 #define bfd_mach_mips4100 4100 3865 #define bfd_mach_mips4111 4111 3866 #define bfd_mach_mips4120 4120 3867 #define bfd_mach_mips4300 4300 3868 #define bfd_mach_mips4400 4400 3869 #define bfd_mach_mips4600 4600 3870 #define bfd_mach_mips4650 4650 3871 #define bfd_mach_mips5000 5000 3872 #define bfd_mach_mips5400 5400 3873 #define bfd_mach_mips5500 5500 3874 #define bfd_mach_mips6000 6000 3875 #define bfd_mach_mips7000 7000 3876 #define bfd_mach_mips8000 8000 3877 #define bfd_mach_mips9000 9000 3878 #define bfd_mach_mips10000 10000 3879 #define bfd_mach_mips12000 12000 3880 #define bfd_mach_mips16 16 3881 #define bfd_mach_mips5 5 3882 #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */ 3883 #define bfd_mach_mipsisa32 32 3884 #define bfd_mach_mipsisa32r2 33 3885 #define bfd_mach_mipsisa64 64 3886 #define bfd_mach_mipsisa64r2 65 3887 3888 static const struct mips_arch_choice mips_arch_choices[] = 3889 { 3890 { "numeric", 0, 0, 0, 0, 3891 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3892 3893 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 3894 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3895 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 3896 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3897 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 3898 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3899 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 3900 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3901 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 3902 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3903 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 3904 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3905 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 3906 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3907 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 3908 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3909 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 3910 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3911 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 3912 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3913 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 3914 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3915 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 3916 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3917 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 3918 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3919 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 3920 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3921 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 3922 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3923 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 3924 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3925 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 3926 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3927 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 3928 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3929 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 3930 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3931 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 3932 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3933 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 3934 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3935 3936 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 3937 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 3938 _MIPS32 Architecture For Programmers Volume I: Introduction to the 3939 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 3940 page 1. */ 3941 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 3942 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, 3943 mips_cp0_names_mips3264, 3944 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 3945 mips_hwr_names_numeric }, 3946 3947 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 3948 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 3949 | INSN_MIPS3D | INSN_MT | INSN_MSA), 3950 mips_cp0_names_mips3264r2, 3951 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 3952 mips_hwr_names_mips3264r2 }, 3953 3954 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 3955 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 3956 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, 3957 mips_cp0_names_mips3264, 3958 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 3959 mips_hwr_names_numeric }, 3960 3961 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 3962 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 3963 | INSN_DSP64 | INSN_MT | INSN_MDMX), 3964 mips_cp0_names_mips3264r2, 3965 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 3966 mips_hwr_names_mips3264r2 }, 3967 3968 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 3969 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, 3970 mips_cp0_names_sb1, 3971 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 3972 mips_hwr_names_numeric }, 3973 3974 /* This entry, mips16, is here only for ISA/processor selection; do 3975 not print its name. */ 3976 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, 3977 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 3978 }; 3979 3980 /* ISA and processor type to disassemble for, and register names to use. 3981 set_default_mips_dis_options and parse_mips_dis_options fill in these 3982 values. */ 3983 static int mips_processor; 3984 static int mips_isa; 3985 static const char * const *mips_gpr_names; 3986 static const char * const *mips_fpr_names; 3987 static const char * const *mips_cp0_names; 3988 static const struct mips_cp0sel_name *mips_cp0sel_names; 3989 static int mips_cp0sel_names_len; 3990 static const char * const *mips_hwr_names; 3991 3992 /* Other options */ 3993 static int no_aliases; /* If set disassemble as most general inst. */ 3994 3995 static const struct mips_abi_choice * 3996 choose_abi_by_name (const char *name, unsigned int namelen) 3997 { 3998 const struct mips_abi_choice *c; 3999 unsigned int i; 4000 4001 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 4002 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 4003 && strlen (mips_abi_choices[i].name) == namelen) 4004 c = &mips_abi_choices[i]; 4005 4006 return c; 4007 } 4008 4009 static const struct mips_arch_choice * 4010 choose_arch_by_name (const char *name, unsigned int namelen) 4011 { 4012 const struct mips_arch_choice *c = NULL; 4013 unsigned int i; 4014 4015 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 4016 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 4017 && strlen (mips_arch_choices[i].name) == namelen) 4018 c = &mips_arch_choices[i]; 4019 4020 return c; 4021 } 4022 4023 static const struct mips_arch_choice * 4024 choose_arch_by_number (unsigned long mach) 4025 { 4026 static unsigned long hint_bfd_mach; 4027 static const struct mips_arch_choice *hint_arch_choice; 4028 const struct mips_arch_choice *c; 4029 unsigned int i; 4030 4031 /* We optimize this because even if the user specifies no 4032 flags, this will be done for every instruction! */ 4033 if (hint_bfd_mach == mach 4034 && hint_arch_choice != NULL 4035 && hint_arch_choice->bfd_mach == hint_bfd_mach) 4036 return hint_arch_choice; 4037 4038 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 4039 { 4040 if (mips_arch_choices[i].bfd_mach_valid 4041 && mips_arch_choices[i].bfd_mach == mach) 4042 { 4043 c = &mips_arch_choices[i]; 4044 hint_bfd_mach = mach; 4045 hint_arch_choice = c; 4046 } 4047 } 4048 return c; 4049 } 4050 4051 static void 4052 set_default_mips_dis_options (struct disassemble_info *info) 4053 { 4054 const struct mips_arch_choice *chosen_arch; 4055 4056 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, 4057 and numeric FPR, CP0 register, and HWR names. */ 4058 mips_isa = ISA_MIPS3; 4059 mips_processor = CPU_R3000; 4060 mips_gpr_names = mips_gpr_names_oldabi; 4061 mips_fpr_names = mips_fpr_names_numeric; 4062 mips_cp0_names = mips_cp0_names_numeric; 4063 mips_cp0sel_names = NULL; 4064 mips_cp0sel_names_len = 0; 4065 mips_hwr_names = mips_hwr_names_numeric; 4066 no_aliases = 0; 4067 4068 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 4069 #if 0 4070 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 4071 { 4072 Elf_Internal_Ehdr *header; 4073 4074 header = elf_elfheader (info->section->owner); 4075 if (is_newabi (header)) 4076 mips_gpr_names = mips_gpr_names_newabi; 4077 } 4078 #endif 4079 4080 /* Set ISA, architecture, and cp0 register names as best we can. */ 4081 #if !defined(SYMTAB_AVAILABLE) && 0 4082 /* This is running out on a target machine, not in a host tool. 4083 FIXME: Where does mips_target_info come from? */ 4084 target_processor = mips_target_info.processor; 4085 mips_isa = mips_target_info.isa; 4086 #else 4087 chosen_arch = choose_arch_by_number (info->mach); 4088 if (chosen_arch != NULL) 4089 { 4090 mips_processor = chosen_arch->processor; 4091 mips_isa = chosen_arch->isa; 4092 mips_cp0_names = chosen_arch->cp0_names; 4093 mips_cp0sel_names = chosen_arch->cp0sel_names; 4094 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 4095 mips_hwr_names = chosen_arch->hwr_names; 4096 } 4097 #endif 4098 } 4099 4100 static void 4101 parse_mips_dis_option (const char *option, unsigned int len) 4102 { 4103 unsigned int i, optionlen, vallen; 4104 const char *val; 4105 const struct mips_abi_choice *chosen_abi; 4106 const struct mips_arch_choice *chosen_arch; 4107 4108 /* Look for the = that delimits the end of the option name. */ 4109 for (i = 0; i < len; i++) 4110 { 4111 if (option[i] == '=') 4112 break; 4113 } 4114 if (i == 0) /* Invalid option: no name before '='. */ 4115 return; 4116 if (i == len) /* Invalid option: no '='. */ 4117 return; 4118 if (i == (len - 1)) /* Invalid option: no value after '='. */ 4119 return; 4120 4121 optionlen = i; 4122 val = option + (optionlen + 1); 4123 vallen = len - (optionlen + 1); 4124 4125 if (strncmp("gpr-names", option, optionlen) == 0 4126 && strlen("gpr-names") == optionlen) 4127 { 4128 chosen_abi = choose_abi_by_name (val, vallen); 4129 if (chosen_abi != NULL) 4130 mips_gpr_names = chosen_abi->gpr_names; 4131 return; 4132 } 4133 4134 if (strncmp("fpr-names", option, optionlen) == 0 4135 && strlen("fpr-names") == optionlen) 4136 { 4137 chosen_abi = choose_abi_by_name (val, vallen); 4138 if (chosen_abi != NULL) 4139 mips_fpr_names = chosen_abi->fpr_names; 4140 return; 4141 } 4142 4143 if (strncmp("cp0-names", option, optionlen) == 0 4144 && strlen("cp0-names") == optionlen) 4145 { 4146 chosen_arch = choose_arch_by_name (val, vallen); 4147 if (chosen_arch != NULL) 4148 { 4149 mips_cp0_names = chosen_arch->cp0_names; 4150 mips_cp0sel_names = chosen_arch->cp0sel_names; 4151 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 4152 } 4153 return; 4154 } 4155 4156 if (strncmp("hwr-names", option, optionlen) == 0 4157 && strlen("hwr-names") == optionlen) 4158 { 4159 chosen_arch = choose_arch_by_name (val, vallen); 4160 if (chosen_arch != NULL) 4161 mips_hwr_names = chosen_arch->hwr_names; 4162 return; 4163 } 4164 4165 if (strncmp("reg-names", option, optionlen) == 0 4166 && strlen("reg-names") == optionlen) 4167 { 4168 /* We check both ABI and ARCH here unconditionally, so 4169 that "numeric" will do the desirable thing: select 4170 numeric register names for all registers. Other than 4171 that, a given name probably won't match both. */ 4172 chosen_abi = choose_abi_by_name (val, vallen); 4173 if (chosen_abi != NULL) 4174 { 4175 mips_gpr_names = chosen_abi->gpr_names; 4176 mips_fpr_names = chosen_abi->fpr_names; 4177 } 4178 chosen_arch = choose_arch_by_name (val, vallen); 4179 if (chosen_arch != NULL) 4180 { 4181 mips_cp0_names = chosen_arch->cp0_names; 4182 mips_cp0sel_names = chosen_arch->cp0sel_names; 4183 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 4184 mips_hwr_names = chosen_arch->hwr_names; 4185 } 4186 return; 4187 } 4188 4189 /* Invalid option. */ 4190 } 4191 4192 static void 4193 parse_mips_dis_options (const char *options) 4194 { 4195 const char *option_end; 4196 4197 if (options == NULL) 4198 return; 4199 4200 while (*options != '\0') 4201 { 4202 /* Skip empty options. */ 4203 if (*options == ',') 4204 { 4205 options++; 4206 continue; 4207 } 4208 4209 /* We know that *options is neither NUL or a comma. */ 4210 option_end = options + 1; 4211 while (*option_end != ',' && *option_end != '\0') 4212 option_end++; 4213 4214 parse_mips_dis_option (options, option_end - options); 4215 4216 /* Go on to the next one. If option_end points to a comma, it 4217 will be skipped above. */ 4218 options = option_end; 4219 } 4220 } 4221 4222 static const struct mips_cp0sel_name * 4223 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 4224 unsigned int len, 4225 unsigned int cp0reg, 4226 unsigned int sel) 4227 { 4228 unsigned int i; 4229 4230 for (i = 0; i < len; i++) 4231 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 4232 return &names[i]; 4233 return NULL; 4234 } 4235 4236 /* Print insn arguments for 32/64-bit code. */ 4237 4238 static void 4239 print_insn_args (const char *d, 4240 register unsigned long int l, 4241 bfd_vma pc, 4242 struct disassemble_info *info, 4243 const struct mips_opcode *opp) 4244 { 4245 int op, delta; 4246 unsigned int lsb, msb, msbd; 4247 4248 lsb = 0; 4249 4250 for (; *d != '\0'; d++) 4251 { 4252 switch (*d) 4253 { 4254 case ',': 4255 case '(': 4256 case ')': 4257 case '[': 4258 case ']': 4259 (*info->fprintf_func) (info->stream, "%c", *d); 4260 break; 4261 4262 case '+': 4263 /* Extension character; switch for second char. */ 4264 d++; 4265 switch (*d) 4266 { 4267 case '\0': 4268 /* xgettext:c-format */ 4269 (*info->fprintf_func) (info->stream, 4270 "# internal error, incomplete extension sequence (+)"); 4271 return; 4272 4273 case 'A': 4274 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; 4275 (*info->fprintf_func) (info->stream, "0x%x", lsb); 4276 break; 4277 4278 case 'B': 4279 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; 4280 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 4281 break; 4282 4283 case '1': 4284 (*info->fprintf_func) (info->stream, "0x%lx", 4285 (l >> OP_SH_UDI1) & OP_MASK_UDI1); 4286 break; 4287 4288 case '2': 4289 (*info->fprintf_func) (info->stream, "0x%lx", 4290 (l >> OP_SH_UDI2) & OP_MASK_UDI2); 4291 break; 4292 4293 case '3': 4294 (*info->fprintf_func) (info->stream, "0x%lx", 4295 (l >> OP_SH_UDI3) & OP_MASK_UDI3); 4296 break; 4297 4298 case '4': 4299 (*info->fprintf_func) (info->stream, "0x%lx", 4300 (l >> OP_SH_UDI4) & OP_MASK_UDI4); 4301 break; 4302 4303 case '5': /* 5-bit signed immediate in bit 16 */ 4304 delta = ((l >> OP_SH_RT) & OP_MASK_RT); 4305 if (delta & 0x10) { /* test sign bit */ 4306 delta |= ~OP_MASK_RT; 4307 } 4308 (*info->fprintf_func) (info->stream, "%d", delta); 4309 break; 4310 4311 case '6': 4312 (*info->fprintf_func) (info->stream, "0x%lx", 4313 (l >> OP_SH_2BIT) & OP_MASK_2BIT); 4314 break; 4315 4316 case '7': 4317 (*info->fprintf_func) (info->stream, "0x%lx", 4318 (l >> OP_SH_3BIT) & OP_MASK_3BIT); 4319 break; 4320 4321 case '8': 4322 (*info->fprintf_func) (info->stream, "0x%lx", 4323 (l >> OP_SH_4BIT) & OP_MASK_4BIT); 4324 break; 4325 4326 case '9': 4327 (*info->fprintf_func) (info->stream, "0x%lx", 4328 (l >> OP_SH_5BIT) & OP_MASK_5BIT); 4329 break; 4330 4331 case ':': 4332 (*info->fprintf_func) (info->stream, "0x%lx", 4333 (l >> OP_SH_1BIT) & OP_MASK_1BIT); 4334 break; 4335 4336 case '!': /* 10-bit pc-relative target in bit 11 */ 4337 delta = ((l >> OP_SH_10BIT) & OP_MASK_10BIT); 4338 if (delta & 0x200) { /* test sign bit */ 4339 delta |= ~OP_MASK_10BIT; 4340 } 4341 info->target = (delta << 2) + pc + INSNLEN; 4342 (*info->print_address_func) (info->target, info); 4343 break; 4344 4345 case '~': 4346 (*info->fprintf_func) (info->stream, "0"); 4347 break; 4348 4349 case '@': 4350 (*info->fprintf_func) (info->stream, "0x%lx", 4351 ((l >> OP_SH_1_TO_4) & OP_MASK_1_TO_4)+1); 4352 break; 4353 4354 case '^': /* 10-bit signed immediate << 0 in bit 16 */ 4355 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); 4356 if (delta & 0x200) { /* test sign bit */ 4357 delta |= ~OP_MASK_IMM10; 4358 } 4359 (*info->fprintf_func) (info->stream, "%d", delta); 4360 break; 4361 4362 case '#': /* 10-bit signed immediate << 1 in bit 16 */ 4363 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); 4364 if (delta & 0x200) { /* test sign bit */ 4365 delta |= ~OP_MASK_IMM10; 4366 } 4367 (*info->fprintf_func) (info->stream, "%d", delta << 1); 4368 break; 4369 4370 case '$': /* 10-bit signed immediate << 2 in bit 16 */ 4371 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); 4372 if (delta & 0x200) { /* test sign bit */ 4373 delta |= ~OP_MASK_IMM10; 4374 } 4375 (*info->fprintf_func) (info->stream, "%d", delta << 2); 4376 break; 4377 4378 case '%': /* 10-bit signed immediate << 3 in bit 16 */ 4379 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); 4380 if (delta & 0x200) { /* test sign bit */ 4381 delta |= ~OP_MASK_IMM10; 4382 } 4383 (*info->fprintf_func) (info->stream, "%d", delta << 3); 4384 break; 4385 4386 case 'C': 4387 case 'H': 4388 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; 4389 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 4390 break; 4391 4392 case 'D': 4393 { 4394 const struct mips_cp0sel_name *n; 4395 unsigned int cp0reg, sel; 4396 4397 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; 4398 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 4399 4400 /* CP0 register including 'sel' code for mtcN (et al.), to be 4401 printed textually if known. If not known, print both 4402 CP0 register name and sel numerically since CP0 register 4403 with sel 0 may have a name unrelated to register being 4404 printed. */ 4405 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 4406 mips_cp0sel_names_len, cp0reg, sel); 4407 if (n != NULL) 4408 (*info->fprintf_func) (info->stream, "%s", n->name); 4409 else 4410 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 4411 break; 4412 } 4413 4414 case 'E': 4415 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; 4416 (*info->fprintf_func) (info->stream, "0x%x", lsb); 4417 break; 4418 4419 case 'F': 4420 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; 4421 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 4422 break; 4423 4424 case 'G': 4425 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; 4426 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 4427 break; 4428 4429 case 'o': 4430 switch (*(d+1)) { 4431 case '1': 4432 d++; 4433 delta = l & ((1 << 18) - 1); 4434 if (delta & 0x20000) { 4435 delta |= ~0x1ffff; 4436 } 4437 break; 4438 case '2': 4439 d++; 4440 delta = l & ((1 << 19) - 1); 4441 if (delta & 0x40000) { 4442 delta |= ~0x3ffff; 4443 } 4444 break; 4445 default: 4446 delta = (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6; 4447 if (delta & 0x8000) { 4448 delta |= ~0xffff; 4449 } 4450 } 4451 4452 (*info->fprintf_func) (info->stream, "%d", delta); 4453 break; 4454 4455 case 'p': 4456 /* Sign extend the displacement with 26 bits. */ 4457 delta = (l >> OP_SH_DELTA) & OP_MASK_TARGET; 4458 if (delta & 0x2000000) { 4459 delta |= ~0x3FFFFFF; 4460 } 4461 info->target = (delta << 2) + pc + INSNLEN; 4462 (*info->print_address_func) (info->target, info); 4463 break; 4464 4465 case 't': /* Coprocessor 0 reg name */ 4466 (*info->fprintf_func) (info->stream, "%s", 4467 mips_cp0_names[(l >> OP_SH_RT) & 4468 OP_MASK_RT]); 4469 break; 4470 4471 case 'T': /* Coprocessor 0 reg name */ 4472 { 4473 const struct mips_cp0sel_name *n; 4474 unsigned int cp0reg, sel; 4475 4476 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; 4477 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 4478 4479 /* CP0 register including 'sel' code for mftc0, to be 4480 printed textually if known. If not known, print both 4481 CP0 register name and sel numerically since CP0 register 4482 with sel 0 may have a name unrelated to register being 4483 printed. */ 4484 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 4485 mips_cp0sel_names_len, cp0reg, sel); 4486 if (n != NULL) 4487 (*info->fprintf_func) (info->stream, "%s", n->name); 4488 else 4489 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 4490 break; 4491 } 4492 4493 case 'd': 4494 (*info->fprintf_func) (info->stream, "%s", 4495 mips_wr_names[(l >> OP_SH_FD) & OP_MASK_FD]); 4496 break; 4497 4498 case 'e': 4499 (*info->fprintf_func) (info->stream, "%s", 4500 mips_wr_names[(l >> OP_SH_FS) & OP_MASK_FS]); 4501 break; 4502 4503 case 'f': 4504 (*info->fprintf_func) (info->stream, "%s", 4505 mips_wr_names[(l >> OP_SH_FT) & OP_MASK_FT]); 4506 break; 4507 4508 case 'g': 4509 (*info->fprintf_func) (info->stream, "%s", 4510 mips_msa_control_names_mips3264r2[(l >> OP_SH_MSACR11) 4511 & OP_MASK_MSACR11]); 4512 break; 4513 4514 case 'h': 4515 (*info->fprintf_func) (info->stream, "%s", 4516 mips_msa_control_names_mips3264r2[(l >> OP_SH_MSACR6) 4517 & OP_MASK_MSACR6]); 4518 break; 4519 4520 case 'i': 4521 (*info->fprintf_func) (info->stream, "%s", 4522 mips_gpr_names[(l >> OP_SH_GPR) & OP_MASK_GPR]); 4523 break; 4524 4525 default: 4526 /* xgettext:c-format */ 4527 (*info->fprintf_func) (info->stream, 4528 "# internal error, undefined extension sequence (+%c)", 4529 *d); 4530 return; 4531 } 4532 break; 4533 4534 case '2': 4535 (*info->fprintf_func) (info->stream, "0x%lx", 4536 (l >> OP_SH_BP) & OP_MASK_BP); 4537 break; 4538 4539 case '3': 4540 (*info->fprintf_func) (info->stream, "0x%lx", 4541 (l >> OP_SH_SA3) & OP_MASK_SA3); 4542 break; 4543 4544 case '4': 4545 (*info->fprintf_func) (info->stream, "0x%lx", 4546 (l >> OP_SH_SA4) & OP_MASK_SA4); 4547 break; 4548 4549 case '5': 4550 (*info->fprintf_func) (info->stream, "0x%lx", 4551 (l >> OP_SH_IMM8) & OP_MASK_IMM8); 4552 break; 4553 4554 case '6': 4555 (*info->fprintf_func) (info->stream, "0x%lx", 4556 (l >> OP_SH_RS) & OP_MASK_RS); 4557 break; 4558 4559 case '7': 4560 (*info->fprintf_func) (info->stream, "$ac%ld", 4561 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); 4562 break; 4563 4564 case '8': 4565 (*info->fprintf_func) (info->stream, "0x%lx", 4566 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); 4567 break; 4568 4569 case '9': 4570 (*info->fprintf_func) (info->stream, "$ac%ld", 4571 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); 4572 break; 4573 4574 case '0': /* dsp 6-bit signed immediate in bit 20 */ 4575 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); 4576 if (delta & 0x20) /* test sign bit */ 4577 delta |= ~OP_MASK_DSPSFT; 4578 (*info->fprintf_func) (info->stream, "%d", delta); 4579 break; 4580 4581 case ':': /* dsp 7-bit signed immediate in bit 19 */ 4582 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); 4583 if (delta & 0x40) /* test sign bit */ 4584 delta |= ~OP_MASK_DSPSFT_7; 4585 (*info->fprintf_func) (info->stream, "%d", delta); 4586 break; 4587 4588 case '\'': 4589 (*info->fprintf_func) (info->stream, "0x%lx", 4590 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); 4591 break; 4592 4593 case '@': /* dsp 10-bit signed immediate in bit 16 */ 4594 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); 4595 if (delta & 0x200) /* test sign bit */ 4596 delta |= ~OP_MASK_IMM10; 4597 (*info->fprintf_func) (info->stream, "%d", delta); 4598 break; 4599 4600 case '!': 4601 (*info->fprintf_func) (info->stream, "%ld", 4602 (l >> OP_SH_MT_U) & OP_MASK_MT_U); 4603 break; 4604 4605 case '$': 4606 (*info->fprintf_func) (info->stream, "%ld", 4607 (l >> OP_SH_MT_H) & OP_MASK_MT_H); 4608 break; 4609 4610 case '*': 4611 (*info->fprintf_func) (info->stream, "$ac%ld", 4612 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); 4613 break; 4614 4615 case '&': 4616 (*info->fprintf_func) (info->stream, "$ac%ld", 4617 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); 4618 break; 4619 4620 case 'g': 4621 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ 4622 (*info->fprintf_func) (info->stream, "$%ld", 4623 (l >> OP_SH_RD) & OP_MASK_RD); 4624 break; 4625 4626 case 's': 4627 case 'b': 4628 case 'r': 4629 case 'v': 4630 (*info->fprintf_func) (info->stream, "%s", 4631 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); 4632 break; 4633 4634 case 't': 4635 case 'w': 4636 (*info->fprintf_func) (info->stream, "%s", 4637 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 4638 break; 4639 4640 case 'i': 4641 case 'u': 4642 (*info->fprintf_func) (info->stream, "0x%lx", 4643 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); 4644 break; 4645 4646 case 'j': /* Same as i, but sign-extended. */ 4647 case 'o': 4648 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 4649 4650 if (delta & 0x8000) 4651 delta |= ~0xffff; 4652 (*info->fprintf_func) (info->stream, "%d", 4653 delta); 4654 break; 4655 4656 case 'h': 4657 (*info->fprintf_func) (info->stream, "0x%x", 4658 (unsigned int) ((l >> OP_SH_PREFX) 4659 & OP_MASK_PREFX)); 4660 break; 4661 4662 case 'k': 4663 (*info->fprintf_func) (info->stream, "0x%x", 4664 (unsigned int) ((l >> OP_SH_CACHE) 4665 & OP_MASK_CACHE)); 4666 break; 4667 4668 case 'a': 4669 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) 4670 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); 4671 /* For gdb disassembler, force odd address on jalx. */ 4672 if (info->flavour == bfd_target_unknown_flavour 4673 && strcmp (opp->name, "jalx") == 0) 4674 info->target |= 1; 4675 (*info->print_address_func) (info->target, info); 4676 break; 4677 4678 case 'p': 4679 /* Sign extend the displacement. */ 4680 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 4681 if (delta & 0x8000) 4682 delta |= ~0xffff; 4683 info->target = (delta << 2) + pc + INSNLEN; 4684 (*info->print_address_func) (info->target, info); 4685 break; 4686 4687 case 'd': 4688 (*info->fprintf_func) (info->stream, "%s", 4689 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 4690 break; 4691 4692 case 'U': 4693 { 4694 /* First check for both rd and rt being equal. */ 4695 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; 4696 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) 4697 (*info->fprintf_func) (info->stream, "%s", 4698 mips_gpr_names[reg]); 4699 else 4700 { 4701 /* If one is zero use the other. */ 4702 if (reg == 0) 4703 (*info->fprintf_func) (info->stream, "%s", 4704 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 4705 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) 4706 (*info->fprintf_func) (info->stream, "%s", 4707 mips_gpr_names[reg]); 4708 else /* Bogus, result depends on processor. */ 4709 (*info->fprintf_func) (info->stream, "%s or %s", 4710 mips_gpr_names[reg], 4711 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 4712 } 4713 } 4714 break; 4715 4716 case 'z': 4717 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 4718 break; 4719 4720 case '<': 4721 (*info->fprintf_func) (info->stream, "0x%lx", 4722 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); 4723 break; 4724 4725 case 'c': 4726 (*info->fprintf_func) (info->stream, "0x%lx", 4727 (l >> OP_SH_CODE) & OP_MASK_CODE); 4728 break; 4729 4730 case 'q': 4731 (*info->fprintf_func) (info->stream, "0x%lx", 4732 (l >> OP_SH_CODE2) & OP_MASK_CODE2); 4733 break; 4734 4735 case 'C': 4736 (*info->fprintf_func) (info->stream, "0x%lx", 4737 (l >> OP_SH_COPZ) & OP_MASK_COPZ); 4738 break; 4739 4740 case 'B': 4741 (*info->fprintf_func) (info->stream, "0x%lx", 4742 4743 (l >> OP_SH_CODE20) & OP_MASK_CODE20); 4744 break; 4745 4746 case 'J': 4747 (*info->fprintf_func) (info->stream, "0x%lx", 4748 (l >> OP_SH_CODE19) & OP_MASK_CODE19); 4749 break; 4750 4751 case 'S': 4752 case 'V': 4753 (*info->fprintf_func) (info->stream, "%s", 4754 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); 4755 break; 4756 4757 case 'T': 4758 case 'W': 4759 (*info->fprintf_func) (info->stream, "%s", 4760 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); 4761 break; 4762 4763 case 'D': 4764 (*info->fprintf_func) (info->stream, "%s", 4765 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); 4766 break; 4767 4768 case 'R': 4769 (*info->fprintf_func) (info->stream, "%s", 4770 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); 4771 break; 4772 4773 case 'E': 4774 /* Coprocessor register for lwcN instructions, et al. 4775 4776 Note that there is no load/store cp0 instructions, and 4777 that FPU (cp1) instructions disassemble this field using 4778 'T' format. Therefore, until we gain understanding of 4779 cp2 register names, we can simply print the register 4780 numbers. */ 4781 (*info->fprintf_func) (info->stream, "$%ld", 4782 (l >> OP_SH_RT) & OP_MASK_RT); 4783 break; 4784 4785 case 'G': 4786 /* Coprocessor register for mtcN instructions, et al. Note 4787 that FPU (cp1) instructions disassemble this field using 4788 'S' format. Therefore, we only need to worry about cp0, 4789 cp2, and cp3. */ 4790 op = (l >> OP_SH_OP) & OP_MASK_OP; 4791 if (op == OP_OP_COP0) 4792 (*info->fprintf_func) (info->stream, "%s", 4793 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); 4794 else 4795 (*info->fprintf_func) (info->stream, "$%ld", 4796 (l >> OP_SH_RD) & OP_MASK_RD); 4797 break; 4798 4799 case 'K': 4800 (*info->fprintf_func) (info->stream, "%s", 4801 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 4802 break; 4803 4804 case 'N': 4805 (*info->fprintf_func) (info->stream, 4806 ((opp->pinfo & (FP_D | FP_S)) != 0 4807 ? "$fcc%ld" : "$cc%ld"), 4808 (l >> OP_SH_BCC) & OP_MASK_BCC); 4809 break; 4810 4811 case 'M': 4812 (*info->fprintf_func) (info->stream, "$fcc%ld", 4813 (l >> OP_SH_CCC) & OP_MASK_CCC); 4814 break; 4815 4816 case 'P': 4817 (*info->fprintf_func) (info->stream, "%ld", 4818 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); 4819 break; 4820 4821 case 'e': 4822 (*info->fprintf_func) (info->stream, "%ld", 4823 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); 4824 break; 4825 4826 case '%': 4827 (*info->fprintf_func) (info->stream, "%ld", 4828 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); 4829 break; 4830 4831 case 'H': 4832 (*info->fprintf_func) (info->stream, "%ld", 4833 (l >> OP_SH_SEL) & OP_MASK_SEL); 4834 break; 4835 4836 case 'O': 4837 (*info->fprintf_func) (info->stream, "%ld", 4838 (l >> OP_SH_ALN) & OP_MASK_ALN); 4839 break; 4840 4841 case 'Q': 4842 { 4843 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; 4844 4845 if ((vsel & 0x10) == 0) 4846 { 4847 int fmt; 4848 4849 vsel &= 0x0f; 4850 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 4851 if ((vsel & 1) == 0) 4852 break; 4853 (*info->fprintf_func) (info->stream, "$v%ld[%d]", 4854 (l >> OP_SH_FT) & OP_MASK_FT, 4855 vsel >> 1); 4856 } 4857 else if ((vsel & 0x08) == 0) 4858 { 4859 (*info->fprintf_func) (info->stream, "$v%ld", 4860 (l >> OP_SH_FT) & OP_MASK_FT); 4861 } 4862 else 4863 { 4864 (*info->fprintf_func) (info->stream, "0x%lx", 4865 (l >> OP_SH_FT) & OP_MASK_FT); 4866 } 4867 } 4868 break; 4869 4870 case 'X': 4871 (*info->fprintf_func) (info->stream, "$v%ld", 4872 (l >> OP_SH_FD) & OP_MASK_FD); 4873 break; 4874 4875 case 'Y': 4876 (*info->fprintf_func) (info->stream, "$v%ld", 4877 (l >> OP_SH_FS) & OP_MASK_FS); 4878 break; 4879 4880 case 'Z': 4881 (*info->fprintf_func) (info->stream, "$v%ld", 4882 (l >> OP_SH_FT) & OP_MASK_FT); 4883 break; 4884 4885 default: 4886 /* xgettext:c-format */ 4887 (*info->fprintf_func) (info->stream, 4888 "# internal error, undefined modifier(%c)", 4889 *d); 4890 return; 4891 } 4892 } 4893 } 4894 4895 /* Check if the object uses NewABI conventions. */ 4896 #if 0 4897 static int 4898 is_newabi (header) 4899 Elf_Internal_Ehdr *header; 4900 { 4901 /* There are no old-style ABIs which use 64-bit ELF. */ 4902 if (header->e_ident[EI_CLASS] == ELFCLASS64) 4903 return 1; 4904 4905 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 4906 if ((header->e_flags & EF_MIPS_ABI2) != 0) 4907 return 1; 4908 4909 return 0; 4910 } 4911 #endif 4912 4913 /* Print the mips instruction at address MEMADDR in debugged memory, 4914 on using INFO. Returns length of the instruction, in bytes, which is 4915 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 4916 this is little-endian code. */ 4917 4918 static int 4919 print_insn_mips (bfd_vma memaddr, 4920 unsigned long int word, 4921 struct disassemble_info *info) 4922 { 4923 const struct mips_opcode *op; 4924 static bfd_boolean init = 0; 4925 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 4926 4927 /* Build a hash table to shorten the search time. */ 4928 if (! init) 4929 { 4930 unsigned int i; 4931 4932 for (i = 0; i <= OP_MASK_OP; i++) 4933 { 4934 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 4935 { 4936 if (op->pinfo == INSN_MACRO 4937 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 4938 continue; 4939 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) 4940 { 4941 mips_hash[i] = op; 4942 break; 4943 } 4944 } 4945 } 4946 4947 init = 1; 4948 } 4949 4950 info->bytes_per_chunk = INSNLEN; 4951 info->display_endian = info->endian; 4952 info->insn_info_valid = 1; 4953 info->branch_delay_insns = 0; 4954 info->data_size = 0; 4955 info->insn_type = dis_nonbranch; 4956 info->target = 0; 4957 info->target2 = 0; 4958 4959 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; 4960 if (op != NULL) 4961 { 4962 for (; op < &mips_opcodes[NUMOPCODES]; op++) 4963 { 4964 if (op->pinfo != INSN_MACRO 4965 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 4966 && (word & op->mask) == op->match) 4967 { 4968 const char *d; 4969 4970 /* We always allow to disassemble the jalx instruction. */ 4971 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) 4972 && strcmp (op->name, "jalx")) 4973 continue; 4974 4975 if (strcmp(op->name, "bovc") == 0 4976 || strcmp(op->name, "bnvc") == 0) { 4977 if (((word >> OP_SH_RS) & OP_MASK_RS) < 4978 ((word >> OP_SH_RT) & OP_MASK_RT)) { 4979 continue; 4980 } 4981 } 4982 if (strcmp(op->name, "bgezc") == 0 4983 || strcmp(op->name, "bltzc") == 0 4984 || strcmp(op->name, "bgezalc") == 0 4985 || strcmp(op->name, "bltzalc") == 0) { 4986 if (((word >> OP_SH_RS) & OP_MASK_RS) != 4987 ((word >> OP_SH_RT) & OP_MASK_RT)) { 4988 continue; 4989 } 4990 } 4991 4992 /* Figure out instruction type and branch delay information. */ 4993 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 4994 { 4995 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 4996 info->insn_type = dis_jsr; 4997 else 4998 info->insn_type = dis_branch; 4999 info->branch_delay_insns = 1; 5000 } 5001 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 5002 | INSN_COND_BRANCH_LIKELY)) != 0) 5003 { 5004 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 5005 info->insn_type = dis_condjsr; 5006 else 5007 info->insn_type = dis_condbranch; 5008 info->branch_delay_insns = 1; 5009 } 5010 else if ((op->pinfo & (INSN_STORE_MEMORY 5011 | INSN_LOAD_MEMORY_DELAY)) != 0) 5012 info->insn_type = dis_dref; 5013 5014 (*info->fprintf_func) (info->stream, "%s", op->name); 5015 5016 d = op->args; 5017 if (d != NULL && *d != '\0') 5018 { 5019 (*info->fprintf_func) (info->stream, "\t"); 5020 print_insn_args (d, word, memaddr, info, op); 5021 } 5022 5023 return INSNLEN; 5024 } 5025 } 5026 } 5027 5028 /* Handle undefined instructions. */ 5029 info->insn_type = dis_noninsn; 5030 (*info->fprintf_func) (info->stream, "0x%lx", word); 5031 return INSNLEN; 5032 } 5033 5034 /* In an environment where we do not know the symbol type of the 5035 instruction we are forced to assume that the low order bit of the 5036 instructions' address may mark it as a mips16 instruction. If we 5037 are single stepping, or the pc is within the disassembled function, 5038 this works. Otherwise, we need a clue. Sometimes. */ 5039 5040 static int 5041 _print_insn_mips (bfd_vma memaddr, 5042 struct disassemble_info *info, 5043 enum bfd_endian endianness) 5044 { 5045 bfd_byte buffer[INSNLEN]; 5046 int status; 5047 5048 set_default_mips_dis_options (info); 5049 parse_mips_dis_options (info->disassembler_options); 5050 5051 #if 0 5052 #if 1 5053 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ 5054 /* Only a few tools will work this way. */ 5055 if (memaddr & 0x01) 5056 return print_insn_mips16 (memaddr, info); 5057 #endif 5058 5059 #if SYMTAB_AVAILABLE 5060 if (info->mach == bfd_mach_mips16 5061 || (info->flavour == bfd_target_elf_flavour 5062 && info->symbols != NULL 5063 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other 5064 == STO_MIPS16))) 5065 return print_insn_mips16 (memaddr, info); 5066 #endif 5067 #endif 5068 5069 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 5070 if (status == 0) 5071 { 5072 unsigned long insn; 5073 5074 if (endianness == BFD_ENDIAN_BIG) 5075 insn = (unsigned long) bfd_getb32 (buffer); 5076 else 5077 insn = (unsigned long) bfd_getl32 (buffer); 5078 5079 return print_insn_mips (memaddr, insn, info); 5080 } 5081 else 5082 { 5083 (*info->memory_error_func) (status, memaddr, info); 5084 return -1; 5085 } 5086 } 5087 5088 int 5089 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 5090 { 5091 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 5092 } 5093 5094 int 5095 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 5096 { 5097 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 5098 } 5099 5100 /* Disassemble mips16 instructions. */ 5101 #if 0 5102 static int 5103 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 5104 { 5105 int status; 5106 bfd_byte buffer[2]; 5107 int length; 5108 int insn; 5109 bfd_boolean use_extend; 5110 int extend = 0; 5111 const struct mips_opcode *op, *opend; 5112 5113 info->bytes_per_chunk = 2; 5114 info->display_endian = info->endian; 5115 info->insn_info_valid = 1; 5116 info->branch_delay_insns = 0; 5117 info->data_size = 0; 5118 info->insn_type = dis_nonbranch; 5119 info->target = 0; 5120 info->target2 = 0; 5121 5122 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 5123 if (status != 0) 5124 { 5125 (*info->memory_error_func) (status, memaddr, info); 5126 return -1; 5127 } 5128 5129 length = 2; 5130 5131 if (info->endian == BFD_ENDIAN_BIG) 5132 insn = bfd_getb16 (buffer); 5133 else 5134 insn = bfd_getl16 (buffer); 5135 5136 /* Handle the extend opcode specially. */ 5137 use_extend = FALSE; 5138 if ((insn & 0xf800) == 0xf000) 5139 { 5140 use_extend = TRUE; 5141 extend = insn & 0x7ff; 5142 5143 memaddr += 2; 5144 5145 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 5146 if (status != 0) 5147 { 5148 (*info->fprintf_func) (info->stream, "extend 0x%x", 5149 (unsigned int) extend); 5150 (*info->memory_error_func) (status, memaddr, info); 5151 return -1; 5152 } 5153 5154 if (info->endian == BFD_ENDIAN_BIG) 5155 insn = bfd_getb16 (buffer); 5156 else 5157 insn = bfd_getl16 (buffer); 5158 5159 /* Check for an extend opcode followed by an extend opcode. */ 5160 if ((insn & 0xf800) == 0xf000) 5161 { 5162 (*info->fprintf_func) (info->stream, "extend 0x%x", 5163 (unsigned int) extend); 5164 info->insn_type = dis_noninsn; 5165 return length; 5166 } 5167 5168 length += 2; 5169 } 5170 5171 /* FIXME: Should probably use a hash table on the major opcode here. */ 5172 5173 opend = mips16_opcodes + bfd_mips16_num_opcodes; 5174 for (op = mips16_opcodes; op < opend; op++) 5175 { 5176 if (op->pinfo != INSN_MACRO 5177 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 5178 && (insn & op->mask) == op->match) 5179 { 5180 const char *s; 5181 5182 if (strchr (op->args, 'a') != NULL) 5183 { 5184 if (use_extend) 5185 { 5186 (*info->fprintf_func) (info->stream, "extend 0x%x", 5187 (unsigned int) extend); 5188 info->insn_type = dis_noninsn; 5189 return length - 2; 5190 } 5191 5192 use_extend = FALSE; 5193 5194 memaddr += 2; 5195 5196 status = (*info->read_memory_func) (memaddr, buffer, 2, 5197 info); 5198 if (status == 0) 5199 { 5200 use_extend = TRUE; 5201 if (info->endian == BFD_ENDIAN_BIG) 5202 extend = bfd_getb16 (buffer); 5203 else 5204 extend = bfd_getl16 (buffer); 5205 length += 2; 5206 } 5207 } 5208 5209 (*info->fprintf_func) (info->stream, "%s", op->name); 5210 if (op->args[0] != '\0') 5211 (*info->fprintf_func) (info->stream, "\t"); 5212 5213 for (s = op->args; *s != '\0'; s++) 5214 { 5215 if (*s == ',' 5216 && s[1] == 'w' 5217 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) 5218 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) 5219 { 5220 /* Skip the register and the comma. */ 5221 ++s; 5222 continue; 5223 } 5224 if (*s == ',' 5225 && s[1] == 'v' 5226 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) 5227 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) 5228 { 5229 /* Skip the register and the comma. */ 5230 ++s; 5231 continue; 5232 } 5233 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, 5234 info); 5235 } 5236 5237 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 5238 { 5239 info->branch_delay_insns = 1; 5240 if (info->insn_type != dis_jsr) 5241 info->insn_type = dis_branch; 5242 } 5243 5244 return length; 5245 } 5246 } 5247 5248 if (use_extend) 5249 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); 5250 (*info->fprintf_func) (info->stream, "0x%x", insn); 5251 info->insn_type = dis_noninsn; 5252 5253 return length; 5254 } 5255 5256 /* Disassemble an operand for a mips16 instruction. */ 5257 5258 static void 5259 print_mips16_insn_arg (char type, 5260 const struct mips_opcode *op, 5261 int l, 5262 bfd_boolean use_extend, 5263 int extend, 5264 bfd_vma memaddr, 5265 struct disassemble_info *info) 5266 { 5267 switch (type) 5268 { 5269 case ',': 5270 case '(': 5271 case ')': 5272 (*info->fprintf_func) (info->stream, "%c", type); 5273 break; 5274 5275 case 'y': 5276 case 'w': 5277 (*info->fprintf_func) (info->stream, "%s", 5278 mips16_reg_names(((l >> MIPS16OP_SH_RY) 5279 & MIPS16OP_MASK_RY))); 5280 break; 5281 5282 case 'x': 5283 case 'v': 5284 (*info->fprintf_func) (info->stream, "%s", 5285 mips16_reg_names(((l >> MIPS16OP_SH_RX) 5286 & MIPS16OP_MASK_RX))); 5287 break; 5288 5289 case 'z': 5290 (*info->fprintf_func) (info->stream, "%s", 5291 mips16_reg_names(((l >> MIPS16OP_SH_RZ) 5292 & MIPS16OP_MASK_RZ))); 5293 break; 5294 5295 case 'Z': 5296 (*info->fprintf_func) (info->stream, "%s", 5297 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) 5298 & MIPS16OP_MASK_MOVE32Z))); 5299 break; 5300 5301 case '0': 5302 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 5303 break; 5304 5305 case 'S': 5306 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); 5307 break; 5308 5309 case 'P': 5310 (*info->fprintf_func) (info->stream, "$pc"); 5311 break; 5312 5313 case 'R': 5314 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); 5315 break; 5316 5317 case 'X': 5318 (*info->fprintf_func) (info->stream, "%s", 5319 mips_gpr_names[((l >> MIPS16OP_SH_REGR32) 5320 & MIPS16OP_MASK_REGR32)]); 5321 break; 5322 5323 case 'Y': 5324 (*info->fprintf_func) (info->stream, "%s", 5325 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); 5326 break; 5327 5328 case '<': 5329 case '>': 5330 case '[': 5331 case ']': 5332 case '4': 5333 case '5': 5334 case 'H': 5335 case 'W': 5336 case 'D': 5337 case 'j': 5338 case '6': 5339 case '8': 5340 case 'V': 5341 case 'C': 5342 case 'U': 5343 case 'k': 5344 case 'K': 5345 case 'p': 5346 case 'q': 5347 case 'A': 5348 case 'B': 5349 case 'E': 5350 { 5351 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; 5352 5353 shift = 0; 5354 signedp = 0; 5355 extbits = 16; 5356 pcrel = 0; 5357 extu = 0; 5358 branch = 0; 5359 switch (type) 5360 { 5361 case '<': 5362 nbits = 3; 5363 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 5364 extbits = 5; 5365 extu = 1; 5366 break; 5367 case '>': 5368 nbits = 3; 5369 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 5370 extbits = 5; 5371 extu = 1; 5372 break; 5373 case '[': 5374 nbits = 3; 5375 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 5376 extbits = 6; 5377 extu = 1; 5378 break; 5379 case ']': 5380 nbits = 3; 5381 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 5382 extbits = 6; 5383 extu = 1; 5384 break; 5385 case '4': 5386 nbits = 4; 5387 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; 5388 signedp = 1; 5389 extbits = 15; 5390 break; 5391 case '5': 5392 nbits = 5; 5393 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 5394 info->insn_type = dis_dref; 5395 info->data_size = 1; 5396 break; 5397 case 'H': 5398 nbits = 5; 5399 shift = 1; 5400 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 5401 info->insn_type = dis_dref; 5402 info->data_size = 2; 5403 break; 5404 case 'W': 5405 nbits = 5; 5406 shift = 2; 5407 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 5408 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 5409 && (op->pinfo & MIPS16_INSN_READ_SP) == 0) 5410 { 5411 info->insn_type = dis_dref; 5412 info->data_size = 4; 5413 } 5414 break; 5415 case 'D': 5416 nbits = 5; 5417 shift = 3; 5418 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 5419 info->insn_type = dis_dref; 5420 info->data_size = 8; 5421 break; 5422 case 'j': 5423 nbits = 5; 5424 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 5425 signedp = 1; 5426 break; 5427 case '6': 5428 nbits = 6; 5429 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 5430 break; 5431 case '8': 5432 nbits = 8; 5433 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 5434 break; 5435 case 'V': 5436 nbits = 8; 5437 shift = 2; 5438 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 5439 /* FIXME: This might be lw, or it might be addiu to $sp or 5440 $pc. We assume it's load. */ 5441 info->insn_type = dis_dref; 5442 info->data_size = 4; 5443 break; 5444 case 'C': 5445 nbits = 8; 5446 shift = 3; 5447 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 5448 info->insn_type = dis_dref; 5449 info->data_size = 8; 5450 break; 5451 case 'U': 5452 nbits = 8; 5453 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 5454 extu = 1; 5455 break; 5456 case 'k': 5457 nbits = 8; 5458 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 5459 signedp = 1; 5460 break; 5461 case 'K': 5462 nbits = 8; 5463 shift = 3; 5464 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 5465 signedp = 1; 5466 break; 5467 case 'p': 5468 nbits = 8; 5469 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 5470 signedp = 1; 5471 pcrel = 1; 5472 branch = 1; 5473 info->insn_type = dis_condbranch; 5474 break; 5475 case 'q': 5476 nbits = 11; 5477 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; 5478 signedp = 1; 5479 pcrel = 1; 5480 branch = 1; 5481 info->insn_type = dis_branch; 5482 break; 5483 case 'A': 5484 nbits = 8; 5485 shift = 2; 5486 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 5487 pcrel = 1; 5488 /* FIXME: This can be lw or la. We assume it is lw. */ 5489 info->insn_type = dis_dref; 5490 info->data_size = 4; 5491 break; 5492 case 'B': 5493 nbits = 5; 5494 shift = 3; 5495 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 5496 pcrel = 1; 5497 info->insn_type = dis_dref; 5498 info->data_size = 8; 5499 break; 5500 case 'E': 5501 nbits = 5; 5502 shift = 2; 5503 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 5504 pcrel = 1; 5505 break; 5506 default: 5507 abort (); 5508 } 5509 5510 if (! use_extend) 5511 { 5512 if (signedp && immed >= (1 << (nbits - 1))) 5513 immed -= 1 << nbits; 5514 immed <<= shift; 5515 if ((type == '<' || type == '>' || type == '[' || type == ']') 5516 && immed == 0) 5517 immed = 8; 5518 } 5519 else 5520 { 5521 if (extbits == 16) 5522 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); 5523 else if (extbits == 15) 5524 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); 5525 else 5526 immed = ((extend >> 6) & 0x1f) | (extend & 0x20); 5527 immed &= (1 << extbits) - 1; 5528 if (! extu && immed >= (1 << (extbits - 1))) 5529 immed -= 1 << extbits; 5530 } 5531 5532 if (! pcrel) 5533 (*info->fprintf_func) (info->stream, "%d", immed); 5534 else 5535 { 5536 bfd_vma baseaddr; 5537 5538 if (branch) 5539 { 5540 immed *= 2; 5541 baseaddr = memaddr + 2; 5542 } 5543 else if (use_extend) 5544 baseaddr = memaddr - 2; 5545 else 5546 { 5547 int status; 5548 bfd_byte buffer[2]; 5549 5550 baseaddr = memaddr; 5551 5552 /* If this instruction is in the delay slot of a jr 5553 instruction, the base address is the address of the 5554 jr instruction. If it is in the delay slot of jalr 5555 instruction, the base address is the address of the 5556 jalr instruction. This test is unreliable: we have 5557 no way of knowing whether the previous word is 5558 instruction or data. */ 5559 status = (*info->read_memory_func) (memaddr - 4, buffer, 2, 5560 info); 5561 if (status == 0 5562 && (((info->endian == BFD_ENDIAN_BIG 5563 ? bfd_getb16 (buffer) 5564 : bfd_getl16 (buffer)) 5565 & 0xf800) == 0x1800)) 5566 baseaddr = memaddr - 4; 5567 else 5568 { 5569 status = (*info->read_memory_func) (memaddr - 2, buffer, 5570 2, info); 5571 if (status == 0 5572 && (((info->endian == BFD_ENDIAN_BIG 5573 ? bfd_getb16 (buffer) 5574 : bfd_getl16 (buffer)) 5575 & 0xf81f) == 0xe800)) 5576 baseaddr = memaddr - 2; 5577 } 5578 } 5579 info->target = (baseaddr & ~((1 << shift) - 1)) + immed; 5580 if (pcrel && branch 5581 && info->flavour == bfd_target_unknown_flavour) 5582 /* For gdb disassembler, maintain odd address. */ 5583 info->target |= 1; 5584 (*info->print_address_func) (info->target, info); 5585 } 5586 } 5587 break; 5588 5589 case 'a': 5590 { 5591 int jalx = l & 0x400; 5592 5593 if (! use_extend) 5594 extend = 0; 5595 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); 5596 if (!jalx && info->flavour == bfd_target_unknown_flavour) 5597 /* For gdb disassembler, maintain odd address. */ 5598 l |= 1; 5599 } 5600 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; 5601 (*info->print_address_func) (info->target, info); 5602 info->insn_type = dis_jsr; 5603 info->branch_delay_insns = 1; 5604 break; 5605 5606 case 'l': 5607 case 'L': 5608 { 5609 int need_comma, amask, smask; 5610 5611 need_comma = 0; 5612 5613 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 5614 5615 amask = (l >> 3) & 7; 5616 5617 if (amask > 0 && amask < 5) 5618 { 5619 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 5620 if (amask > 1) 5621 (*info->fprintf_func) (info->stream, "-%s", 5622 mips_gpr_names[amask + 3]); 5623 need_comma = 1; 5624 } 5625 5626 smask = (l >> 1) & 3; 5627 if (smask == 3) 5628 { 5629 (*info->fprintf_func) (info->stream, "%s??", 5630 need_comma ? "," : ""); 5631 need_comma = 1; 5632 } 5633 else if (smask > 0) 5634 { 5635 (*info->fprintf_func) (info->stream, "%s%s", 5636 need_comma ? "," : "", 5637 mips_gpr_names[16]); 5638 if (smask > 1) 5639 (*info->fprintf_func) (info->stream, "-%s", 5640 mips_gpr_names[smask + 15]); 5641 need_comma = 1; 5642 } 5643 5644 if (l & 1) 5645 { 5646 (*info->fprintf_func) (info->stream, "%s%s", 5647 need_comma ? "," : "", 5648 mips_gpr_names[31]); 5649 need_comma = 1; 5650 } 5651 5652 if (amask == 5 || amask == 6) 5653 { 5654 (*info->fprintf_func) (info->stream, "%s$f0", 5655 need_comma ? "," : ""); 5656 if (amask == 6) 5657 (*info->fprintf_func) (info->stream, "-$f1"); 5658 } 5659 } 5660 break; 5661 5662 case 'm': 5663 case 'M': 5664 /* MIPS16e save/restore. */ 5665 { 5666 int need_comma = 0; 5667 int amask, args, statics; 5668 int nsreg, smask; 5669 int framesz; 5670 int i, j; 5671 5672 l = l & 0x7f; 5673 if (use_extend) 5674 l |= extend << 16; 5675 5676 amask = (l >> 16) & 0xf; 5677 if (amask == MIPS16_ALL_ARGS) 5678 { 5679 args = 4; 5680 statics = 0; 5681 } 5682 else if (amask == MIPS16_ALL_STATICS) 5683 { 5684 args = 0; 5685 statics = 4; 5686 } 5687 else 5688 { 5689 args = amask >> 2; 5690 statics = amask & 3; 5691 } 5692 5693 if (args > 0) { 5694 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 5695 if (args > 1) 5696 (*info->fprintf_func) (info->stream, "-%s", 5697 mips_gpr_names[4 + args - 1]); 5698 need_comma = 1; 5699 } 5700 5701 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; 5702 if (framesz == 0 && !use_extend) 5703 framesz = 128; 5704 5705 (*info->fprintf_func) (info->stream, "%s%d", 5706 need_comma ? "," : "", 5707 framesz); 5708 5709 if (l & 0x40) /* $ra */ 5710 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); 5711 5712 nsreg = (l >> 24) & 0x7; 5713 smask = 0; 5714 if (l & 0x20) /* $s0 */ 5715 smask |= 1 << 0; 5716 if (l & 0x10) /* $s1 */ 5717 smask |= 1 << 1; 5718 if (nsreg > 0) /* $s2-$s8 */ 5719 smask |= ((1 << nsreg) - 1) << 2; 5720 5721 /* Find first set static reg bit. */ 5722 for (i = 0; i < 9; i++) 5723 { 5724 if (smask & (1 << i)) 5725 { 5726 (*info->fprintf_func) (info->stream, ",%s", 5727 mips_gpr_names[i == 8 ? 30 : (16 + i)]); 5728 /* Skip over string of set bits. */ 5729 for (j = i; smask & (2 << j); j++) 5730 continue; 5731 if (j > i) 5732 (*info->fprintf_func) (info->stream, "-%s", 5733 mips_gpr_names[j == 8 ? 30 : (16 + j)]); 5734 i = j + 1; 5735 } 5736 } 5737 5738 /* Statics $ax - $a3. */ 5739 if (statics == 1) 5740 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); 5741 else if (statics > 0) 5742 (*info->fprintf_func) (info->stream, ",%s-%s", 5743 mips_gpr_names[7 - statics + 1], 5744 mips_gpr_names[7]); 5745 } 5746 break; 5747 5748 default: 5749 /* xgettext:c-format */ 5750 (*info->fprintf_func) 5751 (info->stream, 5752 "# internal disassembler error, unrecognised modifier (%c)", 5753 type); 5754 abort (); 5755 } 5756 } 5757 5758 void 5759 print_mips_disassembler_options (FILE *stream) 5760 { 5761 unsigned int i; 5762 5763 fprintf (stream, "\n\ 5764 The following MIPS specific disassembler options are supported for use\n\ 5765 with the -M switch (multiple options should be separated by commas):\n"); 5766 5767 fprintf (stream, "\n\ 5768 gpr-names=ABI Print GPR names according to specified ABI.\n\ 5769 Default: based on binary being disassembled.\n"); 5770 5771 fprintf (stream, "\n\ 5772 fpr-names=ABI Print FPR names according to specified ABI.\n\ 5773 Default: numeric.\n"); 5774 5775 fprintf (stream, "\n\ 5776 cp0-names=ARCH Print CP0 register names according to\n\ 5777 specified architecture.\n\ 5778 Default: based on binary being disassembled.\n"); 5779 5780 fprintf (stream, "\n\ 5781 hwr-names=ARCH Print HWR names according to specified\n\ 5782 architecture.\n\ 5783 Default: based on binary being disassembled.\n"); 5784 5785 fprintf (stream, "\n\ 5786 reg-names=ABI Print GPR and FPR names according to\n\ 5787 specified ABI.\n"); 5788 5789 fprintf (stream, "\n\ 5790 reg-names=ARCH Print CP0 register and HWR names according to\n\ 5791 specified architecture.\n"); 5792 5793 fprintf (stream, "\n\ 5794 For the options above, the following values are supported for \"ABI\":\n\ 5795 "); 5796 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 5797 fprintf (stream, " %s", mips_abi_choices[i].name); 5798 fprintf (stream, "\n"); 5799 5800 fprintf (stream, "\n\ 5801 For the options above, The following values are supported for \"ARCH\":\n\ 5802 "); 5803 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 5804 if (*mips_arch_choices[i].name != '\0') 5805 fprintf (stream, " %s", mips_arch_choices[i].name); 5806 fprintf (stream, "\n"); 5807 5808 fprintf (stream, "\n"); 5809 } 5810 #endif 5811