1 /* This file is composed of several different files from the upstream 2 sourceware.org CVS. Original file boundaries marked with **** */ 3 4 #include "qemu/osdep.h" 5 #include <math.h> 6 7 #include "disas/dis-asm.h" 8 9 /* **** floatformat.h from sourceware.org CVS 2005-08-14. */ 10 /* IEEE floating point support declarations, for GDB, the GNU Debugger. 11 Copyright 1991, 1994, 1995, 1997, 2000, 2003 Free Software Foundation, Inc. 12 13 This file is part of GDB. 14 15 This program is free software; you can redistribute it and/or modify 16 it under the terms of the GNU General Public License as published by 17 the Free Software Foundation; either version 2 of the License, or 18 (at your option) any later version. 19 20 This program is distributed in the hope that it will be useful, 21 but WITHOUT ANY WARRANTY; without even the implied warranty of 22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 GNU General Public License for more details. 24 25 You should have received a copy of the GNU General Public License 26 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 27 28 #if !defined (FLOATFORMAT_H) 29 #define FLOATFORMAT_H 1 30 31 /*#include "ansidecl.h" */ 32 33 /* A floatformat consists of a sign bit, an exponent and a mantissa. Once the 34 bytes are concatenated according to the byteorder flag, then each of those 35 fields is contiguous. We number the bits with 0 being the most significant 36 (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field 37 contains with the *_start and *_len fields. */ 38 39 /* What is the order of the bytes. */ 40 41 enum floatformat_byteorders { 42 43 /* Standard little endian byte order. 44 EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */ 45 46 floatformat_little, 47 48 /* Standard big endian byte order. 49 EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */ 50 51 floatformat_big, 52 53 /* Little endian byte order but big endian word order. 54 EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */ 55 56 floatformat_littlebyte_bigword 57 58 }; 59 60 enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no }; 61 62 struct floatformat 63 { 64 enum floatformat_byteorders byteorder; 65 unsigned int totalsize; /* Total size of number in bits */ 66 67 /* Sign bit is always one bit long. 1 means negative, 0 means positive. */ 68 unsigned int sign_start; 69 70 unsigned int exp_start; 71 unsigned int exp_len; 72 /* Bias added to a "true" exponent to form the biased exponent. It 73 is intentionally signed as, otherwise, -exp_bias can turn into a 74 very large number (e.g., given the exp_bias of 0x3fff and a 64 75 bit long, the equation (long)(1 - exp_bias) evaluates to 76 4294950914) instead of -16382). */ 77 int exp_bias; 78 /* Exponent value which indicates NaN. This is the actual value stored in 79 the float, not adjusted by the exp_bias. This usually consists of all 80 one bits. */ 81 unsigned int exp_nan; 82 83 unsigned int man_start; 84 unsigned int man_len; 85 86 /* Is the integer bit explicit or implicit? */ 87 enum floatformat_intbit intbit; 88 89 /* Internal name for debugging. */ 90 const char *name; 91 92 /* Validator method. */ 93 int (*is_valid) (const struct floatformat *fmt, const char *from); 94 }; 95 96 /* floatformats for IEEE single and double, big and little endian. */ 97 98 extern const struct floatformat floatformat_ieee_single_big; 99 extern const struct floatformat floatformat_ieee_single_little; 100 extern const struct floatformat floatformat_ieee_double_big; 101 extern const struct floatformat floatformat_ieee_double_little; 102 103 /* floatformat for ARM IEEE double, little endian bytes and big endian words */ 104 105 extern const struct floatformat floatformat_ieee_double_littlebyte_bigword; 106 107 /* floatformats for various extendeds. */ 108 109 extern const struct floatformat floatformat_i387_ext; 110 extern const struct floatformat floatformat_m68881_ext; 111 extern const struct floatformat floatformat_i960_ext; 112 extern const struct floatformat floatformat_m88110_ext; 113 extern const struct floatformat floatformat_m88110_harris_ext; 114 extern const struct floatformat floatformat_arm_ext_big; 115 extern const struct floatformat floatformat_arm_ext_littlebyte_bigword; 116 /* IA-64 Floating Point register spilt into memory. */ 117 extern const struct floatformat floatformat_ia64_spill_big; 118 extern const struct floatformat floatformat_ia64_spill_little; 119 extern const struct floatformat floatformat_ia64_quad_big; 120 extern const struct floatformat floatformat_ia64_quad_little; 121 122 /* Convert from FMT to a double. 123 FROM is the address of the extended float. 124 Store the double in *TO. */ 125 126 extern void 127 floatformat_to_double (const struct floatformat *, const char *, double *); 128 129 /* The converse: convert the double *FROM to FMT 130 and store where TO points. */ 131 132 extern void 133 floatformat_from_double (const struct floatformat *, const double *, char *); 134 135 /* Return non-zero iff the data at FROM is a valid number in format FMT. */ 136 137 extern int 138 floatformat_is_valid (const struct floatformat *fmt, const char *from); 139 140 #endif /* defined (FLOATFORMAT_H) */ 141 /* **** End of floatformat.h */ 142 /* **** m68k-dis.h from sourceware.org CVS 2005-08-14. */ 143 /* Opcode table header for m680[01234]0/m6888[12]/m68851. 144 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, 145 2003, 2004 Free Software Foundation, Inc. 146 147 This file is part of GDB, GAS, and the GNU binutils. 148 149 GDB, GAS, and the GNU binutils are free software; you can redistribute 150 them and/or modify them under the terms of the GNU General Public 151 License as published by the Free Software Foundation; either version 152 1, or (at your option) any later version. 153 154 GDB, GAS, and the GNU binutils are distributed in the hope that they 155 will be useful, but WITHOUT ANY WARRANTY; without even the implied 156 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 157 the GNU General Public License for more details. 158 159 You should have received a copy of the GNU General Public License 160 along with this file; see the file COPYING. If not, 161 see <http://www.gnu.org/licenses/>. */ 162 163 /* These are used as bit flags for the arch field in the m68k_opcode 164 structure. */ 165 #define _m68k_undef 0 166 #define m68000 0x001 167 #define m68008 m68000 /* Synonym for -m68000. otherwise unused. */ 168 #define m68010 0x002 169 #define m68020 0x004 170 #define m68030 0x008 171 #define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences; 172 gas will deal with the few differences. */ 173 #define m68040 0x010 174 /* There is no 68050. */ 175 #define m68060 0x020 176 #define m68881 0x040 177 #define m68882 m68881 /* Synonym for -m68881. otherwise unused. */ 178 #define m68851 0x080 179 #define cpu32 0x100 /* e.g., 68332 */ 180 181 #define mcfmac 0x200 /* ColdFire MAC. */ 182 #define mcfemac 0x400 /* ColdFire EMAC. */ 183 #define cfloat 0x800 /* ColdFire FPU. */ 184 #define mcfhwdiv 0x1000 /* ColdFire hardware divide. */ 185 186 #define mcfisa_a 0x2000 /* ColdFire ISA_A. */ 187 #define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */ 188 #define mcfisa_b 0x8000 /* ColdFire ISA_B. */ 189 #define mcfusp 0x10000 /* ColdFire USP instructions. */ 190 191 #define mcf5200 0x20000 192 #define mcf5206e 0x40000 193 #define mcf521x 0x80000 194 #define mcf5249 0x100000 195 #define mcf528x 0x200000 196 #define mcf5307 0x400000 197 #define mcf5407 0x800000 198 #define mcf5470 0x1000000 199 #define mcf5480 0x2000000 200 201 /* Handy aliases. */ 202 #define m68040up (m68040 | m68060) 203 #define m68030up (m68030 | m68040up) 204 #define m68020up (m68020 | m68030up) 205 #define m68010up (m68010 | cpu32 | m68020up) 206 #define m68000up (m68000 | m68010up) 207 208 #define mfloat (m68881 | m68882 | m68040 | m68060) 209 #define mmmu (m68851 | m68030 | m68040 | m68060) 210 211 /* The structure used to hold information for an opcode. */ 212 213 struct m68k_opcode 214 { 215 /* The opcode name. */ 216 const char *name; 217 /* The pseudo-size of the instruction(in bytes). Used to determine 218 number of bytes necessary to disassemble the instruction. */ 219 unsigned int size; 220 /* The opcode itself. */ 221 unsigned long opcode; 222 /* The mask used by the disassembler. */ 223 unsigned long match; 224 /* The arguments. */ 225 const char *args; 226 /* The architectures which support this opcode. */ 227 unsigned int arch; 228 }; 229 230 /* The structure used to hold information for an opcode alias. */ 231 232 struct m68k_opcode_alias 233 { 234 /* The alias name. */ 235 const char *alias; 236 /* The instruction for which this is an alias. */ 237 const char *primary; 238 }; 239 240 /* We store four bytes of opcode for all opcodes because that is the 241 most any of them need. The actual length of an instruction is 242 always at least 2 bytes, and is as much longer as necessary to hold 243 the operands it has. 244 245 The match field is a mask saying which bits must match particular 246 opcode in order for an instruction to be an instance of that 247 opcode. 248 249 The args field is a string containing two characters for each 250 operand of the instruction. The first specifies the kind of 251 operand; the second, the place it is stored. */ 252 253 /* Kinds of operands: 254 Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+- 255 256 D data register only. Stored as 3 bits. 257 A address register only. Stored as 3 bits. 258 a address register indirect only. Stored as 3 bits. 259 R either kind of register. Stored as 4 bits. 260 r either kind of register indirect only. Stored as 4 bits. 261 At the moment, used only for cas2 instruction. 262 F floating point coprocessor register only. Stored as 3 bits. 263 O an offset (or width): immediate data 0-31 or data register. 264 Stored as 6 bits in special format for BF... insns. 265 + autoincrement only. Stored as 3 bits (number of the address register). 266 - autodecrement only. Stored as 3 bits (number of the address register). 267 Q quick immediate data. Stored as 3 bits. 268 This matches an immediate operand only when value is in range 1 .. 8. 269 M moveq immediate data. Stored as 8 bits. 270 This matches an immediate operand only when value is in range -128..127 271 T trap vector immediate data. Stored as 4 bits. 272 273 k K-factor for fmove.p instruction. Stored as a 7-bit constant or 274 a three bit register offset, depending on the field type. 275 276 # immediate data. Stored in special places (b, w or l) 277 which say how many bits to store. 278 ^ immediate data for floating point instructions. Special places 279 are offset by 2 bytes from '#'... 280 B pc-relative address, converted to an offset 281 that is treated as immediate data. 282 d displacement and register. Stores the register as 3 bits 283 and stores the displacement in the entire second word. 284 285 C the CCR. No need to store it; this is just for filtering validity. 286 S the SR. No need to store, just as with CCR. 287 U the USP. No need to store, just as with CCR. 288 E the MAC ACC. No need to store, just as with CCR. 289 e the EMAC ACC[0123]. 290 G the MAC/EMAC MACSR. No need to store, just as with CCR. 291 g the EMAC ACCEXT{01,23}. 292 H the MASK. No need to store, just as with CCR. 293 i the MAC/EMAC scale factor. 294 295 I Coprocessor ID. Not printed if 1. The Coprocessor ID is always 296 extracted from the 'd' field of word one, which means that an extended 297 coprocessor opcode can be skipped using the 'i' place, if needed. 298 299 s System Control register for the floating point coprocessor. 300 301 J Misc register for movec instruction, stored in 'j' format. 302 Possible values: 303 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10] 304 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10] 305 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf] 306 0x003 TC MMU Translation Control [60, 40] 307 0x004 ITT0 Instruction Transparent 308 Translation reg 0 [60, 40] 309 0x005 ITT1 Instruction Transparent 310 Translation reg 1 [60, 40] 311 0x006 DTT0 Data Transparent 312 Translation reg 0 [60, 40] 313 0x007 DTT1 Data Transparent 314 Translation reg 1 [60, 40] 315 0x008 BUSCR Bus Control Register [60] 316 0x800 USP User Stack Pointer [60, 40, 30, 20, 10] 317 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf] 318 0x802 CAAR Cache Address Register [ 30, 20] 319 0x803 MSP Master Stack Pointer [ 40, 30, 20] 320 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20] 321 0x805 MMUSR MMU Status reg [ 40] 322 0x806 URP User Root Pointer [60, 40] 323 0x807 SRP Supervisor Root Pointer [60, 40] 324 0x808 PCR Processor Configuration reg [60] 325 0xC00 ROMBAR ROM Base Address Register [520X] 326 0xC04 RAMBAR0 RAM Base Address Register 0 [520X] 327 0xC05 RAMBAR1 RAM Base Address Register 0 [520X] 328 0xC0F MBAR0 RAM Base Address Register 0 [520X] 329 0xC04 FLASHBAR FLASH Base Address Register [mcf528x] 330 0xC05 RAMBAR Static RAM Base Address Register [mcf528x] 331 332 L Register list of the type d0-d7/a0-a7 etc. 333 (New! Improved! Can also hold fp0-fp7, as well!) 334 The assembler tries to see if the registers match the insn by 335 looking at where the insn wants them stored. 336 337 l Register list like L, but with all the bits reversed. 338 Used for going the other way. . . 339 340 c cache identifier which may be "nc" for no cache, "ic" 341 for instruction cache, "dc" for data cache, or "bc" 342 for both caches. Used in cinv and cpush. Always 343 stored in position "d". 344 345 u Any register, with ``upper'' or ``lower'' specification. Used 346 in the mac instructions with size word. 347 348 The remainder are all stored as 6 bits using an address mode and a 349 register number; they differ in which addressing modes they match. 350 351 * all (modes 0-6,7.0-4) 352 ~ alterable memory (modes 2-6,7.0,7.1) 353 (not 0,1,7.2-4) 354 % alterable (modes 0-6,7.0,7.1) 355 (not 7.2-4) 356 ; data (modes 0,2-6,7.0-4) 357 (not 1) 358 @ data, but not immediate (modes 0,2-6,7.0-3) 359 (not 1,7.4) 360 ! control (modes 2,5,6,7.0-3) 361 (not 0,1,3,4,7.4) 362 & alterable control (modes 2,5,6,7.0,7.1) 363 (not 0,1,3,4,7.2-4) 364 $ alterable data (modes 0,2-6,7.0,7.1) 365 (not 1,7.2-4) 366 ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) 367 (not 1,3,4,7.2-4) 368 / control, or data register (modes 0,2,5,6,7.0-3) 369 (not 1,3,4,7.4) 370 > *save operands (modes 2,4,5,6,7.0,7.1) 371 (not 0,1,3,7.2-4) 372 < *restore operands (modes 2,3,5,6,7.0-3) 373 (not 0,1,4,7.4) 374 375 coldfire move operands: 376 m (modes 0-4) 377 n (modes 5,7.2) 378 o (modes 6,7.0,7.1,7.3,7.4) 379 p (modes 0-5) 380 381 coldfire bset/bclr/btst/mulsl/mulul operands: 382 q (modes 0,2-5) 383 v (modes 0,2-5,7.0,7.1) 384 b (modes 0,2-5,7.2) 385 w (modes 2-5,7.2) 386 y (modes 2,5) 387 z (modes 2,5,7.2) 388 x mov3q immediate operand. 389 4 (modes 2,3,4,5) 390 */ 391 392 /* For the 68851: */ 393 /* I didn't use much imagination in choosing the 394 following codes, so many of them aren't very 395 mnemonic. -rab 396 397 0 32 bit pmmu register 398 Possible values: 399 000 TC Translation Control Register (68030, 68851) 400 401 1 16 bit pmmu register 402 111 AC Access Control (68851) 403 404 2 8 bit pmmu register 405 100 CAL Current Access Level (68851) 406 101 VAL Validate Access Level (68851) 407 110 SCC Stack Change Control (68851) 408 409 3 68030-only pmmu registers (32 bit) 410 010 TT0 Transparent Translation reg 0 411 (aka Access Control reg 0 -- AC0 -- on 68ec030) 412 011 TT1 Transparent Translation reg 1 413 (aka Access Control reg 1 -- AC1 -- on 68ec030) 414 415 W wide pmmu registers 416 Possible values: 417 001 DRP Dma Root Pointer (68851) 418 010 SRP Supervisor Root Pointer (68030, 68851) 419 011 CRP Cpu Root Pointer (68030, 68851) 420 421 f function code register (68030, 68851) 422 0 SFC 423 1 DFC 424 425 V VAL register only (68851) 426 427 X BADx, BACx (16 bit) 428 100 BAD Breakpoint Acknowledge Data (68851) 429 101 BAC Breakpoint Acknowledge Control (68851) 430 431 Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030) 432 Z PCSR (68851) 433 434 | memory (modes 2-6, 7.*) 435 436 t address test level (68030 only) 437 Stored as 3 bits, range 0-7. 438 Also used for breakpoint instruction now. 439 440 */ 441 442 /* Places to put an operand, for non-general operands: 443 Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/ 444 445 s source, low bits of first word. 446 d dest, shifted 9 in first word 447 1 second word, shifted 12 448 2 second word, shifted 6 449 3 second word, shifted 0 450 4 third word, shifted 12 451 5 third word, shifted 6 452 6 third word, shifted 0 453 7 second word, shifted 7 454 8 second word, shifted 10 455 9 second word, shifted 5 456 D store in both place 1 and place 3; for divul and divsl. 457 B first word, low byte, for branch displacements 458 W second word (entire), for branch displacements 459 L second and third words (entire), for branch displacements 460 (also overloaded for move16) 461 b second word, low byte 462 w second word (entire) [variable word/long branch offset for dbra] 463 W second word (entire) (must be signed 16 bit value) 464 l second and third word (entire) 465 g variable branch offset for bra and similar instructions. 466 The place to store depends on the magnitude of offset. 467 t store in both place 7 and place 8; for floating point operations 468 c branch offset for cpBcc operations. 469 The place to store is word two if bit six of word one is zero, 470 and words two and three if bit six of word one is one. 471 i Increment by two, to skip over coprocessor extended operands. Only 472 works with the 'I' format. 473 k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number. 474 Also used for dynamic fmovem instruction. 475 C floating point coprocessor constant - 7 bits. Also used for static 476 K-factors... 477 j Movec register #, stored in 12 low bits of second word. 478 m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word 479 and remaining 3 bits of register shifted 9 bits in first word. 480 Indicate upper/lower in 1 bit shifted 7 bits in second word. 481 Use with `R' or `u' format. 482 n `m' without upper/lower indication. (For M[S]ACx; 4 bits split 483 with MSB shifted 6 bits in first word and remaining 3 bits of 484 register shifted 9 bits in first word. No upper/lower 485 indication is done.) Use with `R' or `u' format. 486 o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). 487 Indicate upper/lower in 1 bit shifted 7 bits in second word. 488 Use with `R' or `u' format. 489 M For M[S]ACw; 4 bits in low bits of first word. Indicate 490 upper/lower in 1 bit shifted 6 bits in second word. Use with 491 `R' or `u' format. 492 N For M[S]ACw; 4 bits in low bits of second word. Indicate 493 upper/lower in 1 bit shifted 6 bits in second word. Use with 494 `R' or `u' format. 495 h shift indicator (scale factor), 1 bit shifted 10 in second word 496 497 Places to put operand, for general operands: 498 d destination, shifted 6 bits in first word 499 b source, at low bit of first word, and immediate uses one byte 500 w source, at low bit of first word, and immediate uses two bytes 501 l source, at low bit of first word, and immediate uses four bytes 502 s source, at low bit of first word. 503 Used sometimes in contexts where immediate is not allowed anyway. 504 f single precision float, low bit of 1st word, immediate uses 4 bytes 505 F double precision float, low bit of 1st word, immediate uses 8 bytes 506 x extended precision float, low bit of 1st word, immediate uses 12 bytes 507 p packed float, low bit of 1st word, immediate uses 12 bytes 508 G EMAC accumulator, load (bit 4 2nd word, !bit8 first word) 509 H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word) 510 F EMAC ACCx 511 f EMAC ACCy 512 I MAC/EMAC scale factor 513 / Like 's', but set 2nd word, bit 5 if trailing_ampersand set 514 ] first word, bit 10 515 */ 516 517 extern const struct m68k_opcode m68k_opcodes[]; 518 extern const struct m68k_opcode_alias m68k_opcode_aliases[]; 519 520 extern const int m68k_numopcodes, m68k_numaliases; 521 522 /* **** End of m68k-opcode.h */ 523 /* **** m68k-dis.c from sourceware.org CVS 2005-08-14. */ 524 /* Print Motorola 68k instructions. 525 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 526 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 527 Free Software Foundation, Inc. 528 529 This file is free software; you can redistribute it and/or modify 530 it under the terms of the GNU General Public License as published by 531 the Free Software Foundation; either version 2 of the License, or 532 (at your option) any later version. 533 534 This program is distributed in the hope that it will be useful, 535 but WITHOUT ANY WARRANTY; without even the implied warranty of 536 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 537 GNU General Public License for more details. 538 539 You should have received a copy of the GNU General Public License 540 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 541 542 /* Local function prototypes. */ 543 544 static const char * const fpcr_names[] = 545 { 546 "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr", 547 "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr" 548 }; 549 550 static const char *const reg_names[] = 551 { 552 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", 553 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", 554 "%ps", "%pc" 555 }; 556 557 /* Name of register halves for MAC/EMAC. 558 Separate from reg_names since 'spu', 'fpl' look weird. */ 559 static const char *const reg_half_names[] = 560 { 561 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", 562 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7", 563 "%ps", "%pc" 564 }; 565 566 /* Sign-extend an (unsigned char). */ 567 #if __STDC__ == 1 568 #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch)) 569 #else 570 #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128) 571 #endif 572 573 /* Get a 1 byte signed integer. */ 574 #define NEXTBYTE(p) (p += 2, fetch_data(info, p), COERCE_SIGNED_CHAR(p[-1])) 575 576 /* Get a 2 byte signed integer. */ 577 #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000)) 578 #define NEXTWORD(p) \ 579 (p += 2, fetch_data(info, p), \ 580 COERCE16 ((p[-2] << 8) + p[-1])) 581 582 /* Get a 4 byte signed integer. */ 583 #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000) 584 #define NEXTLONG(p) \ 585 (p += 4, fetch_data(info, p), \ 586 (COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]))) 587 588 /* Get a 4 byte unsigned integer. */ 589 #define NEXTULONG(p) \ 590 (p += 4, fetch_data(info, p), \ 591 (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])) 592 593 /* Get a single precision float. */ 594 #define NEXTSINGLE(val, p) \ 595 (p += 4, fetch_data(info, p), \ 596 floatformat_to_double (&floatformat_ieee_single_big, (char *) p - 4, &val)) 597 598 /* Get a double precision float. */ 599 #define NEXTDOUBLE(val, p) \ 600 (p += 8, fetch_data(info, p), \ 601 floatformat_to_double (&floatformat_ieee_double_big, (char *) p - 8, &val)) 602 603 /* Get an extended precision float. */ 604 #define NEXTEXTEND(val, p) \ 605 (p += 12, fetch_data(info, p), \ 606 floatformat_to_double (&floatformat_m68881_ext, (char *) p - 12, &val)) 607 608 /* Need a function to convert from packed to double 609 precision. Actually, it's easier to print a 610 packed number than a double anyway, so maybe 611 there should be a special case to handle this... */ 612 #define NEXTPACKED(p) \ 613 (p += 12, fetch_data(info, p), 0.0) 614 615 /* Maximum length of an instruction. */ 616 #define MAXLEN 22 617 618 struct private 619 { 620 /* Points to first byte not fetched. */ 621 bfd_byte *max_fetched; 622 bfd_byte the_buffer[MAXLEN]; 623 bfd_vma insn_start; 624 sigjmp_buf bailout; 625 }; 626 627 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) 628 to ADDR (exclusive) are valid. Returns 1 for success, longjmps 629 on error. */ 630 static int 631 fetch_data2(struct disassemble_info *info, bfd_byte *addr) 632 { 633 int status; 634 struct private *priv = (struct private *)info->private_data; 635 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); 636 637 status = (*info->read_memory_func) (start, 638 priv->max_fetched, 639 addr - priv->max_fetched, 640 info); 641 if (status != 0) 642 { 643 (*info->memory_error_func) (status, start, info); 644 siglongjmp(priv->bailout, 1); 645 } 646 else 647 priv->max_fetched = addr; 648 return 1; 649 } 650 651 static int 652 fetch_data(struct disassemble_info *info, bfd_byte *addr) 653 { 654 if (addr <= ((struct private *) (info->private_data))->max_fetched) { 655 return 1; 656 } else { 657 return fetch_data2(info, addr); 658 } 659 } 660 661 /* This function is used to print to the bit-bucket. */ 662 static int 663 dummy_printer (FILE *file ATTRIBUTE_UNUSED, 664 const char *format ATTRIBUTE_UNUSED, 665 ...) 666 { 667 return 0; 668 } 669 670 static void 671 dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED, 672 struct disassemble_info *info ATTRIBUTE_UNUSED) 673 { 674 } 675 676 /* Fetch BITS bits from a position in the instruction specified by CODE. 677 CODE is a "place to put an argument", or 'x' for a destination 678 that is a general address (mode and register). 679 BUFFER contains the instruction. */ 680 681 static int 682 fetch_arg (unsigned char *buffer, 683 int code, 684 int bits, 685 disassemble_info *info) 686 { 687 int val = 0; 688 689 switch (code) 690 { 691 case '/': /* MAC/EMAC mask bit. */ 692 val = buffer[3] >> 5; 693 break; 694 695 case 'G': /* EMAC ACC load. */ 696 val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1); 697 break; 698 699 case 'H': /* EMAC ACC !load. */ 700 val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1); 701 break; 702 703 case ']': /* EMAC ACCEXT bit. */ 704 val = buffer[0] >> 2; 705 break; 706 707 case 'I': /* MAC/EMAC scale factor. */ 708 val = buffer[2] >> 1; 709 break; 710 711 case 'F': /* EMAC ACCx. */ 712 val = buffer[0] >> 1; 713 break; 714 715 case 'f': 716 val = buffer[1]; 717 break; 718 719 case 's': 720 val = buffer[1]; 721 break; 722 723 case 'd': /* Destination, for register or quick. */ 724 val = (buffer[0] << 8) + buffer[1]; 725 val >>= 9; 726 break; 727 728 case 'x': /* Destination, for general arg. */ 729 val = (buffer[0] << 8) + buffer[1]; 730 val >>= 6; 731 break; 732 733 case 'k': 734 fetch_data(info, buffer + 3); 735 val = (buffer[3] >> 4); 736 break; 737 738 case 'C': 739 fetch_data(info, buffer + 3); 740 val = buffer[3]; 741 break; 742 743 case '1': 744 fetch_data(info, buffer + 3); 745 val = (buffer[2] << 8) + buffer[3]; 746 val >>= 12; 747 break; 748 749 case '2': 750 fetch_data(info, buffer + 3); 751 val = (buffer[2] << 8) + buffer[3]; 752 val >>= 6; 753 break; 754 755 case '3': 756 case 'j': 757 fetch_data(info, buffer + 3); 758 val = (buffer[2] << 8) + buffer[3]; 759 break; 760 761 case '4': 762 fetch_data(info, buffer + 5); 763 val = (buffer[4] << 8) + buffer[5]; 764 val >>= 12; 765 break; 766 767 case '5': 768 fetch_data(info, buffer + 5); 769 val = (buffer[4] << 8) + buffer[5]; 770 val >>= 6; 771 break; 772 773 case '6': 774 fetch_data(info, buffer + 5); 775 val = (buffer[4] << 8) + buffer[5]; 776 break; 777 778 case '7': 779 fetch_data(info, buffer + 3); 780 val = (buffer[2] << 8) + buffer[3]; 781 val >>= 7; 782 break; 783 784 case '8': 785 fetch_data(info, buffer + 3); 786 val = (buffer[2] << 8) + buffer[3]; 787 val >>= 10; 788 break; 789 790 case '9': 791 fetch_data(info, buffer + 3); 792 val = (buffer[2] << 8) + buffer[3]; 793 val >>= 5; 794 break; 795 796 case 'e': 797 val = (buffer[1] >> 6); 798 break; 799 800 case 'm': 801 val = (buffer[1] & 0x40 ? 0x8 : 0) 802 | ((buffer[0] >> 1) & 0x7) 803 | (buffer[3] & 0x80 ? 0x10 : 0); 804 break; 805 806 case 'n': 807 val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7); 808 break; 809 810 case 'o': 811 val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0); 812 break; 813 814 case 'M': 815 val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); 816 break; 817 818 case 'N': 819 val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); 820 break; 821 822 case 'h': 823 val = buffer[2] >> 2; 824 break; 825 826 default: 827 abort (); 828 } 829 830 switch (bits) 831 { 832 case 1: 833 return val & 1; 834 case 2: 835 return val & 3; 836 case 3: 837 return val & 7; 838 case 4: 839 return val & 017; 840 case 5: 841 return val & 037; 842 case 6: 843 return val & 077; 844 case 7: 845 return val & 0177; 846 case 8: 847 return val & 0377; 848 case 12: 849 return val & 07777; 850 default: 851 abort (); 852 } 853 } 854 855 /* Check if an EA is valid for a particular code. This is required 856 for the EMAC instructions since the type of source address determines 857 if it is a EMAC-load instruction if the EA is mode 2-5, otherwise it 858 is a non-load EMAC instruction and the bits mean register Ry. 859 A similar case exists for the movem instructions where the register 860 mask is interpreted differently for different EAs. */ 861 862 static bfd_boolean 863 m68k_valid_ea (char code, int val) 864 { 865 int mode, mask; 866 #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \ 867 (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \ 868 | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11) 869 870 switch (code) 871 { 872 case '*': 873 mask = M (1,1,1,1,1,1,1,1,1,1,1,1); 874 break; 875 case '~': 876 mask = M (0,0,1,1,1,1,1,1,1,0,0,0); 877 break; 878 case '%': 879 mask = M (1,1,1,1,1,1,1,1,1,0,0,0); 880 break; 881 case ';': 882 mask = M (1,0,1,1,1,1,1,1,1,1,1,1); 883 break; 884 case '@': 885 mask = M (1,0,1,1,1,1,1,1,1,1,1,0); 886 break; 887 case '!': 888 mask = M (0,0,1,0,0,1,1,1,1,1,1,0); 889 break; 890 case '&': 891 mask = M (0,0,1,0,0,1,1,1,1,0,0,0); 892 break; 893 case '$': 894 mask = M (1,0,1,1,1,1,1,1,1,0,0,0); 895 break; 896 case '?': 897 mask = M (1,0,1,0,0,1,1,1,1,0,0,0); 898 break; 899 case '/': 900 mask = M (1,0,1,0,0,1,1,1,1,1,1,0); 901 break; 902 case '|': 903 mask = M (0,0,1,0,0,1,1,1,1,1,1,0); 904 break; 905 case '>': 906 mask = M (0,0,1,0,1,1,1,1,1,0,0,0); 907 break; 908 case '<': 909 mask = M (0,0,1,1,0,1,1,1,1,1,1,0); 910 break; 911 case 'm': 912 mask = M (1,1,1,1,1,0,0,0,0,0,0,0); 913 break; 914 case 'n': 915 mask = M (0,0,0,0,0,1,0,0,0,1,0,0); 916 break; 917 case 'o': 918 mask = M (0,0,0,0,0,0,1,1,1,0,1,1); 919 break; 920 case 'p': 921 mask = M (1,1,1,1,1,1,0,0,0,0,0,0); 922 break; 923 case 'q': 924 mask = M (1,0,1,1,1,1,0,0,0,0,0,0); 925 break; 926 case 'v': 927 mask = M (1,0,1,1,1,1,0,1,1,0,0,0); 928 break; 929 case 'b': 930 mask = M (1,0,1,1,1,1,0,0,0,1,0,0); 931 break; 932 case 'w': 933 mask = M (0,0,1,1,1,1,0,0,0,1,0,0); 934 break; 935 case 'y': 936 mask = M (0,0,1,0,0,1,0,0,0,0,0,0); 937 break; 938 case 'z': 939 mask = M (0,0,1,0,0,1,0,0,0,1,0,0); 940 break; 941 case '4': 942 mask = M (0,0,1,1,1,1,0,0,0,0,0,0); 943 break; 944 default: 945 abort (); 946 } 947 #undef M 948 949 mode = (val >> 3) & 7; 950 if (mode == 7) 951 mode += val & 7; 952 return (mask & (1 << mode)) != 0; 953 } 954 955 /* Print a base register REGNO and displacement DISP, on INFO->STREAM. 956 REGNO = -1 for pc, -2 for none (suppressed). */ 957 958 static void 959 print_base (int regno, bfd_vma disp, disassemble_info *info) 960 { 961 if (regno == -1) 962 { 963 (*info->fprintf_func) (info->stream, "%%pc@("); 964 (*info->print_address_func) (disp, info); 965 } 966 else 967 { 968 char buf[50]; 969 970 if (regno == -2) 971 (*info->fprintf_func) (info->stream, "@("); 972 else if (regno == -3) 973 (*info->fprintf_func) (info->stream, "%%zpc@("); 974 else 975 (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]); 976 977 sprintf_vma (buf, disp); 978 (*info->fprintf_func) (info->stream, "%s", buf); 979 } 980 } 981 982 /* Print an indexed argument. The base register is BASEREG (-1 for pc). 983 P points to extension word, in buffer. 984 ADDR is the nominal core address of that extension word. */ 985 986 static unsigned char * 987 print_indexed (int basereg, 988 unsigned char *p, 989 bfd_vma addr, 990 disassemble_info *info) 991 { 992 int word; 993 static const char *const scales[] = { "", ":2", ":4", ":8" }; 994 bfd_vma base_disp; 995 bfd_vma outer_disp; 996 char buf[40]; 997 char vmabuf[50]; 998 999 word = NEXTWORD (p); 1000 1001 /* Generate the text for the index register. 1002 Where this will be output is not yet determined. */ 1003 snprintf(buf, sizeof(buf), "%s:%c%s", 1004 reg_names[(word >> 12) & 0xf], 1005 (word & 0x800) ? 'l' : 'w', 1006 scales[(word >> 9) & 3]); 1007 1008 /* Handle the 68000 style of indexing. */ 1009 1010 if ((word & 0x100) == 0) 1011 { 1012 base_disp = word & 0xff; 1013 if ((base_disp & 0x80) != 0) 1014 base_disp -= 0x100; 1015 if (basereg == -1) 1016 base_disp += addr; 1017 print_base (basereg, base_disp, info); 1018 (*info->fprintf_func) (info->stream, ",%s)", buf); 1019 return p; 1020 } 1021 1022 /* Handle the generalized kind. */ 1023 /* First, compute the displacement to add to the base register. */ 1024 if (word & 0200) 1025 { 1026 if (basereg == -1) 1027 basereg = -3; 1028 else 1029 basereg = -2; 1030 } 1031 if (word & 0100) 1032 buf[0] = '\0'; 1033 base_disp = 0; 1034 switch ((word >> 4) & 3) 1035 { 1036 case 2: 1037 base_disp = NEXTWORD (p); 1038 break; 1039 case 3: 1040 base_disp = NEXTLONG (p); 1041 } 1042 if (basereg == -1) 1043 base_disp += addr; 1044 1045 /* Handle single-level case (not indirect). */ 1046 if ((word & 7) == 0) 1047 { 1048 print_base (basereg, base_disp, info); 1049 if (buf[0] != '\0') 1050 (*info->fprintf_func) (info->stream, ",%s", buf); 1051 (*info->fprintf_func) (info->stream, ")"); 1052 return p; 1053 } 1054 1055 /* Two level. Compute displacement to add after indirection. */ 1056 outer_disp = 0; 1057 switch (word & 3) 1058 { 1059 case 2: 1060 outer_disp = NEXTWORD (p); 1061 break; 1062 case 3: 1063 outer_disp = NEXTLONG (p); 1064 } 1065 1066 print_base (basereg, base_disp, info); 1067 if ((word & 4) == 0 && buf[0] != '\0') 1068 { 1069 (*info->fprintf_func) (info->stream, ",%s", buf); 1070 buf[0] = '\0'; 1071 } 1072 sprintf_vma (vmabuf, outer_disp); 1073 (*info->fprintf_func) (info->stream, ")@(%s", vmabuf); 1074 if (buf[0] != '\0') 1075 (*info->fprintf_func) (info->stream, ",%s", buf); 1076 (*info->fprintf_func) (info->stream, ")"); 1077 1078 return p; 1079 } 1080 1081 /* Returns number of bytes "eaten" by the operand, or 1082 return -1 if an invalid operand was found, or -2 if 1083 an opcode table error was found. 1084 ADDR is the pc for this arg to be relative to. */ 1085 1086 static int 1087 print_insn_arg (const char *d, 1088 unsigned char *buffer, 1089 unsigned char *p0, 1090 bfd_vma addr, 1091 disassemble_info *info) 1092 { 1093 int val = 0; 1094 int place = d[1]; 1095 unsigned char *p = p0; 1096 int regno; 1097 const char *regname; 1098 unsigned char *p1; 1099 double flval; 1100 int flt_p; 1101 bfd_signed_vma disp; 1102 unsigned int uval; 1103 1104 switch (*d) 1105 { 1106 case 'c': /* Cache identifier. */ 1107 { 1108 static const char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" }; 1109 val = fetch_arg (buffer, place, 2, info); 1110 (*info->fprintf_func) (info->stream, "%s", cacheFieldName[val]); 1111 break; 1112 } 1113 1114 case 'a': /* Address register indirect only. Cf. case '+'. */ 1115 { 1116 (*info->fprintf_func) 1117 (info->stream, 1118 "%s@", 1119 reg_names[fetch_arg (buffer, place, 3, info) + 8]); 1120 break; 1121 } 1122 1123 case '_': /* 32-bit absolute address for move16. */ 1124 { 1125 uval = NEXTULONG (p); 1126 (*info->print_address_func) (uval, info); 1127 break; 1128 } 1129 1130 case 'C': 1131 (*info->fprintf_func) (info->stream, "%%ccr"); 1132 break; 1133 1134 case 'S': 1135 (*info->fprintf_func) (info->stream, "%%sr"); 1136 break; 1137 1138 case 'U': 1139 (*info->fprintf_func) (info->stream, "%%usp"); 1140 break; 1141 1142 case 'E': 1143 (*info->fprintf_func) (info->stream, "%%acc"); 1144 break; 1145 1146 case 'G': 1147 (*info->fprintf_func) (info->stream, "%%macsr"); 1148 break; 1149 1150 case 'H': 1151 (*info->fprintf_func) (info->stream, "%%mask"); 1152 break; 1153 1154 case 'J': 1155 { 1156 /* FIXME: There's a problem here, different m68k processors call the 1157 same address different names. This table can't get it right 1158 because it doesn't know which processor it's disassembling for. */ 1159 static const struct { const char *name; int value; } names[] 1160 = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002}, 1161 {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005}, 1162 {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008}, 1163 {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802}, 1164 {"%msp", 0x803}, {"%isp", 0x804}, 1165 {"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */ 1166 1167 /* Should we be calling this psr like we do in case 'Y'? */ 1168 {"%mmusr",0x805}, 1169 1170 {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}}; 1171 1172 val = fetch_arg (buffer, place, 12, info); 1173 for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--) 1174 if (names[regno].value == val) 1175 { 1176 (*info->fprintf_func) (info->stream, "%s", names[regno].name); 1177 break; 1178 } 1179 if (regno < 0) 1180 (*info->fprintf_func) (info->stream, "%d", val); 1181 } 1182 break; 1183 1184 case 'Q': 1185 val = fetch_arg (buffer, place, 3, info); 1186 /* 0 means 8, except for the bkpt instruction... */ 1187 if (val == 0 && d[1] != 's') 1188 val = 8; 1189 (*info->fprintf_func) (info->stream, "#%d", val); 1190 break; 1191 1192 case 'x': 1193 val = fetch_arg (buffer, place, 3, info); 1194 /* 0 means -1. */ 1195 if (val == 0) 1196 val = -1; 1197 (*info->fprintf_func) (info->stream, "#%d", val); 1198 break; 1199 1200 case 'M': 1201 if (place == 'h') 1202 { 1203 static const char *const scalefactor_name[] = { "<<", ">>" }; 1204 val = fetch_arg (buffer, place, 1, info); 1205 (*info->fprintf_func) (info->stream, "%s", scalefactor_name[val]); 1206 } 1207 else 1208 { 1209 val = fetch_arg (buffer, place, 8, info); 1210 if (val & 0x80) 1211 val = val - 0x100; 1212 (*info->fprintf_func) (info->stream, "#%d", val); 1213 } 1214 break; 1215 1216 case 'T': 1217 val = fetch_arg (buffer, place, 4, info); 1218 (*info->fprintf_func) (info->stream, "#%d", val); 1219 break; 1220 1221 case 'D': 1222 (*info->fprintf_func) (info->stream, "%s", 1223 reg_names[fetch_arg (buffer, place, 3, info)]); 1224 break; 1225 1226 case 'A': 1227 (*info->fprintf_func) 1228 (info->stream, "%s", 1229 reg_names[fetch_arg (buffer, place, 3, info) + 010]); 1230 break; 1231 1232 case 'R': 1233 (*info->fprintf_func) 1234 (info->stream, "%s", 1235 reg_names[fetch_arg (buffer, place, 4, info)]); 1236 break; 1237 1238 case 'r': 1239 regno = fetch_arg (buffer, place, 4, info); 1240 if (regno > 7) 1241 (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]); 1242 else 1243 (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]); 1244 break; 1245 1246 case 'F': 1247 (*info->fprintf_func) 1248 (info->stream, "%%fp%d", 1249 fetch_arg (buffer, place, 3, info)); 1250 break; 1251 1252 case 'O': 1253 val = fetch_arg (buffer, place, 6, info); 1254 if (val & 0x20) 1255 (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]); 1256 else 1257 (*info->fprintf_func) (info->stream, "%d", val); 1258 break; 1259 1260 case '+': 1261 (*info->fprintf_func) 1262 (info->stream, "%s@+", 1263 reg_names[fetch_arg (buffer, place, 3, info) + 8]); 1264 break; 1265 1266 case '-': 1267 (*info->fprintf_func) 1268 (info->stream, "%s@-", 1269 reg_names[fetch_arg (buffer, place, 3, info) + 8]); 1270 break; 1271 1272 case 'k': 1273 if (place == 'k') 1274 (*info->fprintf_func) 1275 (info->stream, "{%s}", 1276 reg_names[fetch_arg (buffer, place, 3, info)]); 1277 else if (place == 'C') 1278 { 1279 val = fetch_arg (buffer, place, 7, info); 1280 if (val > 63) /* This is a signed constant. */ 1281 val -= 128; 1282 (*info->fprintf_func) (info->stream, "{#%d}", val); 1283 } 1284 else 1285 return -2; 1286 break; 1287 1288 case '#': 1289 case '^': 1290 p1 = buffer + (*d == '#' ? 2 : 4); 1291 if (place == 's') 1292 val = fetch_arg (buffer, place, 4, info); 1293 else if (place == 'C') 1294 val = fetch_arg (buffer, place, 7, info); 1295 else if (place == '8') 1296 val = fetch_arg (buffer, place, 3, info); 1297 else if (place == '3') 1298 val = fetch_arg (buffer, place, 8, info); 1299 else if (place == 'b') 1300 val = NEXTBYTE (p1); 1301 else if (place == 'w' || place == 'W') 1302 val = NEXTWORD (p1); 1303 else if (place == 'l') 1304 val = NEXTLONG (p1); 1305 else 1306 return -2; 1307 (*info->fprintf_func) (info->stream, "#%d", val); 1308 break; 1309 1310 case 'B': 1311 if (place == 'b') 1312 disp = NEXTBYTE (p); 1313 else if (place == 'B') 1314 disp = COERCE_SIGNED_CHAR (buffer[1]); 1315 else if (place == 'w' || place == 'W') 1316 disp = NEXTWORD (p); 1317 else if (place == 'l' || place == 'L' || place == 'C') 1318 disp = NEXTLONG (p); 1319 else if (place == 'g') 1320 { 1321 disp = NEXTBYTE (buffer); 1322 if (disp == 0) 1323 disp = NEXTWORD (p); 1324 else if (disp == -1) 1325 disp = NEXTLONG (p); 1326 } 1327 else if (place == 'c') 1328 { 1329 if (buffer[1] & 0x40) /* If bit six is one, long offset. */ 1330 disp = NEXTLONG (p); 1331 else 1332 disp = NEXTWORD (p); 1333 } 1334 else 1335 return -2; 1336 1337 (*info->print_address_func) (addr + disp, info); 1338 break; 1339 1340 case 'd': 1341 val = NEXTWORD (p); 1342 (*info->fprintf_func) 1343 (info->stream, "%s@(%d)", 1344 reg_names[fetch_arg (buffer, place, 3, info) + 8], val); 1345 break; 1346 1347 case 's': 1348 (*info->fprintf_func) (info->stream, "%s", 1349 fpcr_names[fetch_arg (buffer, place, 3, info)]); 1350 break; 1351 1352 case 'e': 1353 val = fetch_arg(buffer, place, 2, info); 1354 (*info->fprintf_func) (info->stream, "%%acc%d", val); 1355 break; 1356 1357 case 'g': 1358 val = fetch_arg(buffer, place, 1, info); 1359 (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23"); 1360 break; 1361 1362 case 'i': 1363 val = fetch_arg(buffer, place, 2, info); 1364 if (val == 1) 1365 (*info->fprintf_func) (info->stream, "<<"); 1366 else if (val == 3) 1367 (*info->fprintf_func) (info->stream, ">>"); 1368 else 1369 return -1; 1370 break; 1371 1372 case 'I': 1373 /* Get coprocessor ID... */ 1374 val = fetch_arg (buffer, 'd', 3, info); 1375 1376 if (val != 1) /* Unusual coprocessor ID? */ 1377 (*info->fprintf_func) (info->stream, "(cpid=%d) ", val); 1378 break; 1379 1380 case '4': 1381 case '*': 1382 case '~': 1383 case '%': 1384 case ';': 1385 case '@': 1386 case '!': 1387 case '$': 1388 case '?': 1389 case '/': 1390 case '&': 1391 case '|': 1392 case '<': 1393 case '>': 1394 case 'm': 1395 case 'n': 1396 case 'o': 1397 case 'p': 1398 case 'q': 1399 case 'v': 1400 case 'b': 1401 case 'w': 1402 case 'y': 1403 case 'z': 1404 if (place == 'd') 1405 { 1406 val = fetch_arg (buffer, 'x', 6, info); 1407 val = ((val & 7) << 3) + ((val >> 3) & 7); 1408 } 1409 else 1410 val = fetch_arg (buffer, 's', 6, info); 1411 1412 /* If the <ea> is invalid for *d, then reject this match. */ 1413 if (!m68k_valid_ea (*d, val)) 1414 return -1; 1415 1416 /* Get register number assuming address register. */ 1417 regno = (val & 7) + 8; 1418 regname = reg_names[regno]; 1419 switch (val >> 3) 1420 { 1421 case 0: 1422 (*info->fprintf_func) (info->stream, "%s", reg_names[val]); 1423 break; 1424 1425 case 1: 1426 (*info->fprintf_func) (info->stream, "%s", regname); 1427 break; 1428 1429 case 2: 1430 (*info->fprintf_func) (info->stream, "%s@", regname); 1431 break; 1432 1433 case 3: 1434 (*info->fprintf_func) (info->stream, "%s@+", regname); 1435 break; 1436 1437 case 4: 1438 (*info->fprintf_func) (info->stream, "%s@-", regname); 1439 break; 1440 1441 case 5: 1442 val = NEXTWORD (p); 1443 (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val); 1444 break; 1445 1446 case 6: 1447 p = print_indexed (regno, p, addr, info); 1448 break; 1449 1450 case 7: 1451 switch (val & 7) 1452 { 1453 case 0: 1454 val = NEXTWORD (p); 1455 (*info->print_address_func) (val, info); 1456 break; 1457 1458 case 1: 1459 uval = NEXTULONG (p); 1460 (*info->print_address_func) (uval, info); 1461 break; 1462 1463 case 2: 1464 val = NEXTWORD (p); 1465 (*info->fprintf_func) (info->stream, "%%pc@("); 1466 (*info->print_address_func) (addr + val, info); 1467 (*info->fprintf_func) (info->stream, ")"); 1468 break; 1469 1470 case 3: 1471 p = print_indexed (-1, p, addr, info); 1472 break; 1473 1474 case 4: 1475 flt_p = 1; /* Assume it's a float... */ 1476 switch (place) 1477 { 1478 case 'b': 1479 val = NEXTBYTE (p); 1480 flt_p = 0; 1481 break; 1482 1483 case 'w': 1484 val = NEXTWORD (p); 1485 flt_p = 0; 1486 break; 1487 1488 case 'l': 1489 val = NEXTLONG (p); 1490 flt_p = 0; 1491 break; 1492 1493 case 'f': 1494 NEXTSINGLE (flval, p); 1495 break; 1496 1497 case 'F': 1498 NEXTDOUBLE (flval, p); 1499 break; 1500 1501 case 'x': 1502 NEXTEXTEND (flval, p); 1503 break; 1504 1505 case 'p': 1506 flval = NEXTPACKED (p); 1507 break; 1508 1509 default: 1510 return -1; 1511 } 1512 if (flt_p) /* Print a float? */ 1513 (*info->fprintf_func) (info->stream, "#%g", flval); 1514 else 1515 (*info->fprintf_func) (info->stream, "#%d", val); 1516 break; 1517 1518 default: 1519 return -1; 1520 } 1521 } 1522 1523 /* If place is '/', then this is the case of the mask bit for 1524 mac/emac loads. Now that the arg has been printed, grab the 1525 mask bit and if set, add a '&' to the arg. */ 1526 if (place == '/') 1527 { 1528 val = fetch_arg (buffer, place, 1, info); 1529 if (val) 1530 info->fprintf_func (info->stream, "&"); 1531 } 1532 break; 1533 1534 case 'L': 1535 case 'l': 1536 if (place == 'w') 1537 { 1538 char doneany; 1539 p1 = buffer + 2; 1540 val = NEXTWORD (p1); 1541 /* Move the pointer ahead if this point is farther ahead 1542 than the last. */ 1543 p = p1 > p ? p1 : p; 1544 if (val == 0) 1545 { 1546 (*info->fprintf_func) (info->stream, "#0"); 1547 break; 1548 } 1549 if (*d == 'l') 1550 { 1551 int newval = 0; 1552 1553 for (regno = 0; regno < 16; ++regno) 1554 if (val & (0x8000 >> regno)) 1555 newval |= 1 << regno; 1556 val = newval; 1557 } 1558 val &= 0xffff; 1559 doneany = 0; 1560 for (regno = 0; regno < 16; ++regno) 1561 if (val & (1 << regno)) 1562 { 1563 int first_regno; 1564 1565 if (doneany) 1566 (*info->fprintf_func) (info->stream, "/"); 1567 doneany = 1; 1568 (*info->fprintf_func) (info->stream, "%s", reg_names[regno]); 1569 first_regno = regno; 1570 while (val & (1 << (regno + 1))) 1571 ++regno; 1572 if (regno > first_regno) 1573 (*info->fprintf_func) (info->stream, "-%s", 1574 reg_names[regno]); 1575 } 1576 } 1577 else if (place == '3') 1578 { 1579 /* `fmovem' insn. */ 1580 char doneany; 1581 val = fetch_arg (buffer, place, 8, info); 1582 if (val == 0) 1583 { 1584 (*info->fprintf_func) (info->stream, "#0"); 1585 break; 1586 } 1587 if (*d == 'l') 1588 { 1589 int newval = 0; 1590 1591 for (regno = 0; regno < 8; ++regno) 1592 if (val & (0x80 >> regno)) 1593 newval |= 1 << regno; 1594 val = newval; 1595 } 1596 val &= 0xff; 1597 doneany = 0; 1598 for (regno = 0; regno < 8; ++regno) 1599 if (val & (1 << regno)) 1600 { 1601 int first_regno; 1602 if (doneany) 1603 (*info->fprintf_func) (info->stream, "/"); 1604 doneany = 1; 1605 (*info->fprintf_func) (info->stream, "%%fp%d", regno); 1606 first_regno = regno; 1607 while (val & (1 << (regno + 1))) 1608 ++regno; 1609 if (regno > first_regno) 1610 (*info->fprintf_func) (info->stream, "-%%fp%d", regno); 1611 } 1612 } 1613 else if (place == '8') 1614 { 1615 /* fmoveml for FP status registers. */ 1616 (*info->fprintf_func) (info->stream, "%s", 1617 fpcr_names[fetch_arg (buffer, place, 3, 1618 info)]); 1619 } 1620 else 1621 return -2; 1622 break; 1623 1624 case 'X': 1625 place = '8'; 1626 /* fall through */ 1627 case 'Y': 1628 case 'Z': 1629 case 'W': 1630 case '0': 1631 case '1': 1632 case '2': 1633 case '3': 1634 { 1635 int reg = fetch_arg (buffer, place, 5, info); 1636 const char *name = 0; 1637 1638 switch (reg) 1639 { 1640 case 2: name = "%tt0"; break; 1641 case 3: name = "%tt1"; break; 1642 case 0x10: name = "%tc"; break; 1643 case 0x11: name = "%drp"; break; 1644 case 0x12: name = "%srp"; break; 1645 case 0x13: name = "%crp"; break; 1646 case 0x14: name = "%cal"; break; 1647 case 0x15: name = "%val"; break; 1648 case 0x16: name = "%scc"; break; 1649 case 0x17: name = "%ac"; break; 1650 case 0x18: name = "%psr"; break; 1651 case 0x19: name = "%pcsr"; break; 1652 case 0x1c: 1653 case 0x1d: 1654 { 1655 int break_reg = ((buffer[3] >> 2) & 7); 1656 1657 (*info->fprintf_func) 1658 (info->stream, reg == 0x1c ? "%%bad%d" : "%%bac%d", 1659 break_reg); 1660 } 1661 break; 1662 default: 1663 (*info->fprintf_func) (info->stream, "<mmu register %d>", reg); 1664 } 1665 if (name) 1666 (*info->fprintf_func) (info->stream, "%s", name); 1667 } 1668 break; 1669 1670 case 'f': 1671 { 1672 int fc = fetch_arg (buffer, place, 5, info); 1673 1674 if (fc == 1) 1675 (*info->fprintf_func) (info->stream, "%%dfc"); 1676 else if (fc == 0) 1677 (*info->fprintf_func) (info->stream, "%%sfc"); 1678 else 1679 /* xgettext:c-format */ 1680 (*info->fprintf_func) (info->stream, "<function code %d>", fc); 1681 } 1682 break; 1683 1684 case 'V': 1685 (*info->fprintf_func) (info->stream, "%%val"); 1686 break; 1687 1688 case 't': 1689 { 1690 int level = fetch_arg (buffer, place, 3, info); 1691 1692 (*info->fprintf_func) (info->stream, "%d", level); 1693 } 1694 break; 1695 1696 case 'u': 1697 { 1698 short is_upper = 0; 1699 int reg = fetch_arg (buffer, place, 5, info); 1700 1701 if (reg & 0x10) 1702 { 1703 is_upper = 1; 1704 reg &= 0xf; 1705 } 1706 (*info->fprintf_func) (info->stream, "%s%s", 1707 reg_half_names[reg], 1708 is_upper ? "u" : "l"); 1709 } 1710 break; 1711 1712 default: 1713 return -2; 1714 } 1715 1716 return p - p0; 1717 } 1718 1719 /* Try to match the current instruction to best and if so, return the 1720 number of bytes consumed from the instruction stream, else zero. */ 1721 1722 static int 1723 match_insn_m68k (bfd_vma memaddr, 1724 disassemble_info * info, 1725 const struct m68k_opcode * best, 1726 struct private * priv) 1727 { 1728 unsigned char *save_p; 1729 unsigned char *p; 1730 const char *d; 1731 1732 bfd_byte *buffer = priv->the_buffer; 1733 fprintf_function save_printer = info->fprintf_func; 1734 void (* save_print_address) (bfd_vma, struct disassemble_info *) 1735 = info->print_address_func; 1736 1737 /* Point at first word of argument data, 1738 and at descriptor for first argument. */ 1739 p = buffer + 2; 1740 1741 /* Figure out how long the fixed-size portion of the instruction is. 1742 The only place this is stored in the opcode table is 1743 in the arguments--look for arguments which specify fields in the 2nd 1744 or 3rd words of the instruction. */ 1745 for (d = best->args; *d; d += 2) 1746 { 1747 /* I don't think it is necessary to be checking d[0] here; 1748 I suspect all this could be moved to the case statement below. */ 1749 if (d[0] == '#') 1750 { 1751 if (d[1] == 'l' && p - buffer < 6) 1752 p = buffer + 6; 1753 else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8') 1754 p = buffer + 4; 1755 } 1756 1757 if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4) 1758 p = buffer + 4; 1759 1760 switch (d[1]) 1761 { 1762 case '1': 1763 case '2': 1764 case '3': 1765 case '7': 1766 case '8': 1767 case '9': 1768 case 'i': 1769 if (p - buffer < 4) 1770 p = buffer + 4; 1771 break; 1772 case '4': 1773 case '5': 1774 case '6': 1775 if (p - buffer < 6) 1776 p = buffer + 6; 1777 break; 1778 default: 1779 break; 1780 } 1781 } 1782 1783 /* pflusha is an exceptions. It takes no arguments but is two words 1784 long. Recognize it by looking at the lower 16 bits of the mask. */ 1785 if (p - buffer < 4 && (best->match & 0xFFFF) != 0) 1786 p = buffer + 4; 1787 1788 /* lpstop is another exception. It takes a one word argument but is 1789 three words long. */ 1790 if (p - buffer < 6 1791 && (best->match & 0xffff) == 0xffff 1792 && best->args[0] == '#' 1793 && best->args[1] == 'w') 1794 { 1795 /* Copy the one word argument into the usual location for a one 1796 word argument, to simplify printing it. We can get away with 1797 this because we know exactly what the second word is, and we 1798 aren't going to print anything based on it. */ 1799 p = buffer + 6; 1800 fetch_data(info, p); 1801 buffer[2] = buffer[4]; 1802 buffer[3] = buffer[5]; 1803 } 1804 1805 fetch_data(info, p); 1806 1807 d = best->args; 1808 1809 save_p = p; 1810 info->print_address_func = dummy_print_address; 1811 info->fprintf_func = dummy_printer; 1812 1813 /* We scan the operands twice. The first time we don't print anything, 1814 but look for errors. */ 1815 for (; *d; d += 2) 1816 { 1817 int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); 1818 1819 if (eaten >= 0) 1820 p += eaten; 1821 else if (eaten == -1) 1822 { 1823 info->fprintf_func = save_printer; 1824 info->print_address_func = save_print_address; 1825 return 0; 1826 } 1827 else 1828 { 1829 info->fprintf_func (info->stream, 1830 /* xgettext:c-format */ 1831 "<internal error in opcode table: %s %s>\n", 1832 best->name, best->args); 1833 info->fprintf_func = save_printer; 1834 info->print_address_func = save_print_address; 1835 return 2; 1836 } 1837 } 1838 1839 p = save_p; 1840 info->fprintf_func = save_printer; 1841 info->print_address_func = save_print_address; 1842 1843 d = best->args; 1844 1845 info->fprintf_func (info->stream, "%s", best->name); 1846 1847 if (*d) 1848 info->fprintf_func (info->stream, " "); 1849 1850 while (*d) 1851 { 1852 p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); 1853 d += 2; 1854 1855 if (*d && *(d - 2) != 'I' && *d != 'k') 1856 info->fprintf_func (info->stream, ","); 1857 } 1858 1859 return p - buffer; 1860 } 1861 1862 /* Print the m68k instruction at address MEMADDR in debugged memory, 1863 on INFO->STREAM. Returns length of the instruction, in bytes. */ 1864 1865 int 1866 print_insn_m68k (bfd_vma memaddr, disassemble_info *info) 1867 { 1868 int i; 1869 const char *d; 1870 unsigned int arch_mask; 1871 struct private priv; 1872 bfd_byte *buffer = priv.the_buffer; 1873 int major_opcode; 1874 static int numopcodes[16]; 1875 static const struct m68k_opcode **opcodes[16]; 1876 int val; 1877 1878 if (!opcodes[0]) 1879 { 1880 /* Speed up the matching by sorting the opcode 1881 table on the upper four bits of the opcode. */ 1882 const struct m68k_opcode **opc_pointer[16]; 1883 1884 /* First count how many opcodes are in each of the sixteen buckets. */ 1885 for (i = 0; i < m68k_numopcodes; i++) 1886 numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++; 1887 1888 /* Then create a sorted table of pointers 1889 that point into the unsorted table. */ 1890 opc_pointer[0] = malloc (sizeof (struct m68k_opcode *) 1891 * m68k_numopcodes); 1892 opcodes[0] = opc_pointer[0]; 1893 1894 for (i = 1; i < 16; i++) 1895 { 1896 opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1]; 1897 opcodes[i] = opc_pointer[i]; 1898 } 1899 1900 for (i = 0; i < m68k_numopcodes; i++) 1901 *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i]; 1902 } 1903 1904 info->private_data = (PTR) &priv; 1905 /* Tell objdump to use two bytes per chunk 1906 and six bytes per line for displaying raw data. */ 1907 info->bytes_per_chunk = 2; 1908 info->bytes_per_line = 6; 1909 info->display_endian = BFD_ENDIAN_BIG; 1910 priv.max_fetched = priv.the_buffer; 1911 priv.insn_start = memaddr; 1912 1913 if (sigsetjmp(priv.bailout, 0) != 0) { 1914 /* Error return. */ 1915 return -1; 1916 } 1917 1918 switch (info->mach) 1919 { 1920 default: 1921 case 0: 1922 arch_mask = (unsigned int) -1; 1923 break; 1924 case bfd_mach_m68000: 1925 arch_mask = m68000|m68881|m68851; 1926 break; 1927 case bfd_mach_m68008: 1928 arch_mask = m68008|m68881|m68851; 1929 break; 1930 case bfd_mach_m68010: 1931 arch_mask = m68010|m68881|m68851; 1932 break; 1933 case bfd_mach_m68020: 1934 arch_mask = m68020|m68881|m68851; 1935 break; 1936 case bfd_mach_m68030: 1937 arch_mask = m68030|m68881|m68851; 1938 break; 1939 case bfd_mach_m68040: 1940 arch_mask = m68040|m68881|m68851; 1941 break; 1942 case bfd_mach_m68060: 1943 arch_mask = m68060|m68881|m68851; 1944 break; 1945 case bfd_mach_mcf5200: 1946 arch_mask = mcfisa_a; 1947 break; 1948 case bfd_mach_mcf521x: 1949 case bfd_mach_mcf528x: 1950 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac; 1951 break; 1952 case bfd_mach_mcf5206e: 1953 arch_mask = mcfisa_a|mcfhwdiv|mcfmac; 1954 break; 1955 case bfd_mach_mcf5249: 1956 arch_mask = mcfisa_a|mcfhwdiv|mcfemac; 1957 break; 1958 case bfd_mach_mcf5307: 1959 arch_mask = mcfisa_a|mcfhwdiv|mcfmac; 1960 break; 1961 case bfd_mach_mcf5407: 1962 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac; 1963 break; 1964 case bfd_mach_mcf547x: 1965 case bfd_mach_mcf548x: 1966 case bfd_mach_mcfv4e: 1967 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac; 1968 break; 1969 } 1970 1971 fetch_data(info, buffer + 2); 1972 major_opcode = (buffer[0] >> 4) & 15; 1973 1974 for (i = 0; i < numopcodes[major_opcode]; i++) 1975 { 1976 const struct m68k_opcode *opc = opcodes[major_opcode][i]; 1977 unsigned long opcode = opc->opcode; 1978 unsigned long match = opc->match; 1979 1980 if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24))) 1981 && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16))) 1982 /* Only fetch the next two bytes if we need to. */ 1983 && (((0xffff & match) == 0) 1984 || 1985 (fetch_data(info, buffer + 4) 1986 && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8))) 1987 && ((0xff & buffer[3] & match) == (0xff & opcode))) 1988 ) 1989 && (opc->arch & arch_mask) != 0) 1990 { 1991 /* Don't use for printout the variants of divul and divsl 1992 that have the same register number in two places. 1993 The more general variants will match instead. */ 1994 for (d = opc->args; *d; d += 2) 1995 if (d[1] == 'D') 1996 break; 1997 1998 /* Don't use for printout the variants of most floating 1999 point coprocessor instructions which use the same 2000 register number in two places, as above. */ 2001 if (*d == '\0') 2002 for (d = opc->args; *d; d += 2) 2003 if (d[1] == 't') 2004 break; 2005 2006 /* Don't match fmovel with more than one register; 2007 wait for fmoveml. */ 2008 if (*d == '\0') 2009 { 2010 for (d = opc->args; *d; d += 2) 2011 { 2012 if (d[0] == 's' && d[1] == '8') 2013 { 2014 val = fetch_arg (buffer, d[1], 3, info); 2015 if ((val & (val - 1)) != 0) 2016 break; 2017 } 2018 } 2019 } 2020 2021 /* Don't match FPU insns with non-default coprocessor ID. */ 2022 if (*d == '\0') 2023 { 2024 for (d = opc->args; *d; d += 2) 2025 { 2026 if (d[0] == 'I') 2027 { 2028 val = fetch_arg (buffer, 'd', 3, info); 2029 if (val != 1) 2030 break; 2031 } 2032 } 2033 } 2034 2035 if (*d == '\0') 2036 if ((val = match_insn_m68k (memaddr, info, opc, & priv))) 2037 return val; 2038 } 2039 } 2040 2041 /* Handle undefined instructions. */ 2042 info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]); 2043 return 2; 2044 } 2045 /* **** End of m68k-dis.c */ 2046 /* **** m68k-opc.h from sourceware.org CVS 2005-08-14. */ 2047 /* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200. 2048 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2049 2000, 2001, 2003, 2004, 2005 2050 Free Software Foundation, Inc. 2051 2052 This file is part of GDB, GAS, and the GNU binutils. 2053 2054 GDB, GAS, and the GNU binutils are free software; you can redistribute 2055 them and/or modify them under the terms of the GNU General Public 2056 License as published by the Free Software Foundation; either version 2057 1, or (at your option) any later version. 2058 2059 GDB, GAS, and the GNU binutils are distributed in the hope that they 2060 will be useful, but WITHOUT ANY WARRANTY; without even the implied 2061 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 2062 the GNU General Public License for more details. 2063 2064 You should have received a copy of the GNU General Public License 2065 along with this file; see the file COPYING. If not, 2066 see <http://www.gnu.org/licenses/>. */ 2067 2068 #define one(x) ((unsigned int) (x) << 16) 2069 #define two(x, y) (((unsigned int) (x) << 16) + (y)) 2070 2071 /* The assembler requires that all instances of the same mnemonic must 2072 be consecutive. If they aren't, the assembler will bomb at 2073 runtime. */ 2074 2075 const struct m68k_opcode m68k_opcodes[] = 2076 { 2077 {"abcd", 2, one(0140400), one(0170770), "DsDd", m68000up }, 2078 {"abcd", 2, one(0140410), one(0170770), "-s-d", m68000up }, 2079 2080 {"addaw", 2, one(0150300), one(0170700), "*wAd", m68000up }, 2081 {"addal", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, 2082 2083 {"addib", 4, one(0003000), one(0177700), "#b$s", m68000up }, 2084 {"addiw", 4, one(0003100), one(0177700), "#w$s", m68000up }, 2085 {"addil", 6, one(0003200), one(0177700), "#l$s", m68000up }, 2086 {"addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, 2087 2088 {"addqb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, 2089 {"addqw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, 2090 {"addql", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, 2091 2092 /* The add opcode can generate the adda, addi, and addq instructions. */ 2093 {"addb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, 2094 {"addb", 4, one(0003000), one(0177700), "#b$s", m68000up }, 2095 {"addb", 2, one(0150000), one(0170700), ";bDd", m68000up }, 2096 {"addb", 2, one(0150400), one(0170700), "Dd~b", m68000up }, 2097 {"addw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, 2098 {"addw", 2, one(0150300), one(0170700), "*wAd", m68000up }, 2099 {"addw", 4, one(0003100), one(0177700), "#w$s", m68000up }, 2100 {"addw", 2, one(0150100), one(0170700), "*wDd", m68000up }, 2101 {"addw", 2, one(0150500), one(0170700), "Dd~w", m68000up }, 2102 {"addl", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, 2103 {"addl", 6, one(0003200), one(0177700), "#l$s", m68000up }, 2104 {"addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, 2105 {"addl", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, 2106 {"addl", 2, one(0150200), one(0170700), "*lDd", m68000up | mcfisa_a }, 2107 {"addl", 2, one(0150600), one(0170700), "Dd~l", m68000up | mcfisa_a }, 2108 2109 {"addxb", 2, one(0150400), one(0170770), "DsDd", m68000up }, 2110 {"addxb", 2, one(0150410), one(0170770), "-s-d", m68000up }, 2111 {"addxw", 2, one(0150500), one(0170770), "DsDd", m68000up }, 2112 {"addxw", 2, one(0150510), one(0170770), "-s-d", m68000up }, 2113 {"addxl", 2, one(0150600), one(0170770), "DsDd", m68000up | mcfisa_a }, 2114 {"addxl", 2, one(0150610), one(0170770), "-s-d", m68000up }, 2115 2116 {"andib", 4, one(0001000), one(0177700), "#b$s", m68000up }, 2117 {"andib", 4, one(0001074), one(0177777), "#bCs", m68000up }, 2118 {"andiw", 4, one(0001100), one(0177700), "#w$s", m68000up }, 2119 {"andiw", 4, one(0001174), one(0177777), "#wSs", m68000up }, 2120 {"andil", 6, one(0001200), one(0177700), "#l$s", m68000up }, 2121 {"andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, 2122 {"andi", 4, one(0001100), one(0177700), "#w$s", m68000up }, 2123 {"andi", 4, one(0001074), one(0177777), "#bCs", m68000up }, 2124 {"andi", 4, one(0001174), one(0177777), "#wSs", m68000up }, 2125 2126 /* The and opcode can generate the andi instruction. */ 2127 {"andb", 4, one(0001000), one(0177700), "#b$s", m68000up }, 2128 {"andb", 4, one(0001074), one(0177777), "#bCs", m68000up }, 2129 {"andb", 2, one(0140000), one(0170700), ";bDd", m68000up }, 2130 {"andb", 2, one(0140400), one(0170700), "Dd~b", m68000up }, 2131 {"andw", 4, one(0001100), one(0177700), "#w$s", m68000up }, 2132 {"andw", 4, one(0001174), one(0177777), "#wSs", m68000up }, 2133 {"andw", 2, one(0140100), one(0170700), ";wDd", m68000up }, 2134 {"andw", 2, one(0140500), one(0170700), "Dd~w", m68000up }, 2135 {"andl", 6, one(0001200), one(0177700), "#l$s", m68000up }, 2136 {"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, 2137 {"andl", 2, one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a }, 2138 {"andl", 2, one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a }, 2139 {"and", 4, one(0001100), one(0177700), "#w$w", m68000up }, 2140 {"and", 4, one(0001074), one(0177777), "#bCs", m68000up }, 2141 {"and", 4, one(0001174), one(0177777), "#wSs", m68000up }, 2142 {"and", 2, one(0140100), one(0170700), ";wDd", m68000up }, 2143 {"and", 2, one(0140500), one(0170700), "Dd~w", m68000up }, 2144 2145 {"aslb", 2, one(0160400), one(0170770), "QdDs", m68000up }, 2146 {"aslb", 2, one(0160440), one(0170770), "DdDs", m68000up }, 2147 {"aslw", 2, one(0160500), one(0170770), "QdDs", m68000up }, 2148 {"aslw", 2, one(0160540), one(0170770), "DdDs", m68000up }, 2149 {"aslw", 2, one(0160700), one(0177700), "~s", m68000up }, 2150 {"asll", 2, one(0160600), one(0170770), "QdDs", m68000up | mcfisa_a }, 2151 {"asll", 2, one(0160640), one(0170770), "DdDs", m68000up | mcfisa_a }, 2152 2153 {"asrb", 2, one(0160000), one(0170770), "QdDs", m68000up }, 2154 {"asrb", 2, one(0160040), one(0170770), "DdDs", m68000up }, 2155 {"asrw", 2, one(0160100), one(0170770), "QdDs", m68000up }, 2156 {"asrw", 2, one(0160140), one(0170770), "DdDs", m68000up }, 2157 {"asrw", 2, one(0160300), one(0177700), "~s", m68000up }, 2158 {"asrl", 2, one(0160200), one(0170770), "QdDs", m68000up | mcfisa_a }, 2159 {"asrl", 2, one(0160240), one(0170770), "DdDs", m68000up | mcfisa_a }, 2160 2161 {"bhiw", 2, one(0061000), one(0177777), "BW", m68000up | mcfisa_a }, 2162 {"blsw", 2, one(0061400), one(0177777), "BW", m68000up | mcfisa_a }, 2163 {"bccw", 2, one(0062000), one(0177777), "BW", m68000up | mcfisa_a }, 2164 {"bcsw", 2, one(0062400), one(0177777), "BW", m68000up | mcfisa_a }, 2165 {"bnew", 2, one(0063000), one(0177777), "BW", m68000up | mcfisa_a }, 2166 {"beqw", 2, one(0063400), one(0177777), "BW", m68000up | mcfisa_a }, 2167 {"bvcw", 2, one(0064000), one(0177777), "BW", m68000up | mcfisa_a }, 2168 {"bvsw", 2, one(0064400), one(0177777), "BW", m68000up | mcfisa_a }, 2169 {"bplw", 2, one(0065000), one(0177777), "BW", m68000up | mcfisa_a }, 2170 {"bmiw", 2, one(0065400), one(0177777), "BW", m68000up | mcfisa_a }, 2171 {"bgew", 2, one(0066000), one(0177777), "BW", m68000up | mcfisa_a }, 2172 {"bltw", 2, one(0066400), one(0177777), "BW", m68000up | mcfisa_a }, 2173 {"bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a }, 2174 {"blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a }, 2175 2176 {"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2177 {"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2178 {"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2179 {"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2180 {"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2181 {"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2182 {"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2183 {"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2184 {"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2185 {"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2186 {"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2187 {"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2188 {"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2189 {"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2190 2191 {"bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a }, 2192 {"blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a }, 2193 {"bccs", 2, one(0062000), one(0177400), "BB", m68000up | mcfisa_a }, 2194 {"bcss", 2, one(0062400), one(0177400), "BB", m68000up | mcfisa_a }, 2195 {"bnes", 2, one(0063000), one(0177400), "BB", m68000up | mcfisa_a }, 2196 {"beqs", 2, one(0063400), one(0177400), "BB", m68000up | mcfisa_a }, 2197 {"bvcs", 2, one(0064000), one(0177400), "BB", m68000up | mcfisa_a }, 2198 {"bvss", 2, one(0064400), one(0177400), "BB", m68000up | mcfisa_a }, 2199 {"bpls", 2, one(0065000), one(0177400), "BB", m68000up | mcfisa_a }, 2200 {"bmis", 2, one(0065400), one(0177400), "BB", m68000up | mcfisa_a }, 2201 {"bges", 2, one(0066000), one(0177400), "BB", m68000up | mcfisa_a }, 2202 {"blts", 2, one(0066400), one(0177400), "BB", m68000up | mcfisa_a }, 2203 {"bgts", 2, one(0067000), one(0177400), "BB", m68000up | mcfisa_a }, 2204 {"bles", 2, one(0067400), one(0177400), "BB", m68000up | mcfisa_a }, 2205 2206 {"jhi", 2, one(0061000), one(0177400), "Bg", m68000up | mcfisa_a }, 2207 {"jls", 2, one(0061400), one(0177400), "Bg", m68000up | mcfisa_a }, 2208 {"jcc", 2, one(0062000), one(0177400), "Bg", m68000up | mcfisa_a }, 2209 {"jcs", 2, one(0062400), one(0177400), "Bg", m68000up | mcfisa_a }, 2210 {"jne", 2, one(0063000), one(0177400), "Bg", m68000up | mcfisa_a }, 2211 {"jeq", 2, one(0063400), one(0177400), "Bg", m68000up | mcfisa_a }, 2212 {"jvc", 2, one(0064000), one(0177400), "Bg", m68000up | mcfisa_a }, 2213 {"jvs", 2, one(0064400), one(0177400), "Bg", m68000up | mcfisa_a }, 2214 {"jpl", 2, one(0065000), one(0177400), "Bg", m68000up | mcfisa_a }, 2215 {"jmi", 2, one(0065400), one(0177400), "Bg", m68000up | mcfisa_a }, 2216 {"jge", 2, one(0066000), one(0177400), "Bg", m68000up | mcfisa_a }, 2217 {"jlt", 2, one(0066400), one(0177400), "Bg", m68000up | mcfisa_a }, 2218 {"jgt", 2, one(0067000), one(0177400), "Bg", m68000up | mcfisa_a }, 2219 {"jle", 2, one(0067400), one(0177400), "Bg", m68000up | mcfisa_a }, 2220 2221 {"bchg", 2, one(0000500), one(0170700), "Dd$s", m68000up | mcfisa_a }, 2222 {"bchg", 4, one(0004100), one(0177700), "#b$s", m68000up }, 2223 {"bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a }, 2224 2225 {"bclr", 2, one(0000600), one(0170700), "Dd$s", m68000up | mcfisa_a }, 2226 {"bclr", 4, one(0004200), one(0177700), "#b$s", m68000up }, 2227 {"bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a }, 2228 2229 {"bfchg", 4, two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, 2230 {"bfclr", 4, two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, 2231 {"bfexts", 4, two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, 2232 {"bfextu", 4, two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, 2233 {"bfffo", 4, two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, 2234 {"bfins", 4, two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up }, 2235 {"bfset", 4, two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, 2236 {"bftst", 4, two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up }, 2237 2238 {"bgnd", 2, one(0045372), one(0177777), "", cpu32 }, 2239 2240 {"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa}, 2241 2242 {"bkpt", 2, one(0044110), one(0177770), "ts", m68010up }, 2243 2244 {"braw", 2, one(0060000), one(0177777), "BW", m68000up | mcfisa_a }, 2245 {"bral", 2, one(0060377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2246 {"bras", 2, one(0060000), one(0177400), "BB", m68000up | mcfisa_a }, 2247 2248 {"bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a }, 2249 {"bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a }, 2250 {"bset", 4, one(0004300), one(0177700), "#b$s", m68000up }, 2251 {"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a }, 2252 2253 {"bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a }, 2254 {"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, 2255 {"bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a }, 2256 2257 {"btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a }, 2258 {"btst", 4, one(0004000), one(0177700), "#b@s", m68000up }, 2259 {"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a }, 2260 2261 {"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa}, 2262 2263 {"callm", 4, one(0003300), one(0177700), "#b!s", m68020 }, 2264 2265 {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, 2266 {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, 2267 {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, 2268 {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, 2269 2270 {"casb", 4, two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, 2271 {"casw", 4, two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, 2272 {"casl", 4, two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, 2273 2274 {"chk2b", 4, two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, 2275 {"chk2w", 4, two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, 2276 {"chk2l", 4, two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, 2277 2278 {"chkl", 2, one(0040400), one(0170700), ";lDd", m68000up }, 2279 {"chkw", 2, one(0040600), one(0170700), ";wDd", m68000up }, 2280 2281 #define SCOPE_LINE (0x1 << 3) 2282 #define SCOPE_PAGE (0x2 << 3) 2283 #define SCOPE_ALL (0x3 << 3) 2284 2285 {"cinva", 2, one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up }, 2286 {"cinvl", 2, one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up }, 2287 {"cinvp", 2, one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, 2288 2289 {"cpusha", 2, one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up }, 2290 {"cpushl", 2, one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcfisa_a }, 2291 {"cpushp", 2, one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, 2292 2293 #undef SCOPE_LINE 2294 #undef SCOPE_PAGE 2295 #undef SCOPE_ALL 2296 2297 {"clrb", 2, one(0041000), one(0177700), "$s", m68000up | mcfisa_a }, 2298 {"clrw", 2, one(0041100), one(0177700), "$s", m68000up | mcfisa_a }, 2299 {"clrl", 2, one(0041200), one(0177700), "$s", m68000up | mcfisa_a }, 2300 2301 {"cmp2b", 4, two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, 2302 {"cmp2w", 4, two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, 2303 {"cmp2l", 4, two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, 2304 2305 {"cmpaw", 2, one(0130300), one(0170700), "*wAd", m68000up }, 2306 {"cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, 2307 2308 {"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up }, 2309 {"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b }, 2310 {"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up }, 2311 {"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b }, 2312 {"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up }, 2313 {"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, 2314 2315 {"cmpmb", 2, one(0130410), one(0170770), "+s+d", m68000up }, 2316 {"cmpmw", 2, one(0130510), one(0170770), "+s+d", m68000up }, 2317 {"cmpml", 2, one(0130610), one(0170770), "+s+d", m68000up }, 2318 2319 /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */ 2320 {"cmpb", 4, one(0006000), one(0177700), "#b@s", m68000up }, 2321 {"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b }, 2322 {"cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up }, 2323 {"cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up }, 2324 {"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b }, 2325 {"cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up }, 2326 {"cmpw", 4, one(0006100), one(0177700), "#w@s", m68000up }, 2327 {"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b }, 2328 {"cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up }, 2329 {"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b }, 2330 {"cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, 2331 {"cmpl", 6, one(0006200), one(0177700), "#l@s", m68000up }, 2332 {"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, 2333 {"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up }, 2334 {"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a }, 2335 2336 {"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up }, 2337 {"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up }, 2338 {"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up }, 2339 {"dbf", 2, one(0050710), one(0177770), "DsBw", m68000up }, 2340 {"dbge", 2, one(0056310), one(0177770), "DsBw", m68000up }, 2341 {"dbgt", 2, one(0057310), one(0177770), "DsBw", m68000up }, 2342 {"dbhi", 2, one(0051310), one(0177770), "DsBw", m68000up }, 2343 {"dble", 2, one(0057710), one(0177770), "DsBw", m68000up }, 2344 {"dbls", 2, one(0051710), one(0177770), "DsBw", m68000up }, 2345 {"dblt", 2, one(0056710), one(0177770), "DsBw", m68000up }, 2346 {"dbmi", 2, one(0055710), one(0177770), "DsBw", m68000up }, 2347 {"dbne", 2, one(0053310), one(0177770), "DsBw", m68000up }, 2348 {"dbpl", 2, one(0055310), one(0177770), "DsBw", m68000up }, 2349 {"dbt", 2, one(0050310), one(0177770), "DsBw", m68000up }, 2350 {"dbvc", 2, one(0054310), one(0177770), "DsBw", m68000up }, 2351 {"dbvs", 2, one(0054710), one(0177770), "DsBw", m68000up }, 2352 2353 {"divsw", 2, one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv }, 2354 2355 {"divsl", 4, two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, 2356 {"divsl", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, 2357 {"divsl", 4, two(0046100,0004000),two(0177700,0107770),"qsDD", mcfhwdiv }, 2358 2359 {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, 2360 {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, 2361 2362 {"divuw", 2, one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv }, 2363 2364 {"divul", 4, two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, 2365 {"divul", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, 2366 {"divul", 4, two(0046100,0000000),two(0177700,0107770),"qsDD", mcfhwdiv }, 2367 2368 {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, 2369 {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, 2370 2371 {"eorib", 4, one(0005000), one(0177700), "#b$s", m68000up }, 2372 {"eorib", 4, one(0005074), one(0177777), "#bCs", m68000up }, 2373 {"eoriw", 4, one(0005100), one(0177700), "#w$s", m68000up }, 2374 {"eoriw", 4, one(0005174), one(0177777), "#wSs", m68000up }, 2375 {"eoril", 6, one(0005200), one(0177700), "#l$s", m68000up }, 2376 {"eoril", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, 2377 {"eori", 4, one(0005074), one(0177777), "#bCs", m68000up }, 2378 {"eori", 4, one(0005174), one(0177777), "#wSs", m68000up }, 2379 {"eori", 4, one(0005100), one(0177700), "#w$s", m68000up }, 2380 2381 /* The eor opcode can generate the eori instruction. */ 2382 {"eorb", 4, one(0005000), one(0177700), "#b$s", m68000up }, 2383 {"eorb", 4, one(0005074), one(0177777), "#bCs", m68000up }, 2384 {"eorb", 2, one(0130400), one(0170700), "Dd$s", m68000up }, 2385 {"eorw", 4, one(0005100), one(0177700), "#w$s", m68000up }, 2386 {"eorw", 4, one(0005174), one(0177777), "#wSs", m68000up }, 2387 {"eorw", 2, one(0130500), one(0170700), "Dd$s", m68000up }, 2388 {"eorl", 6, one(0005200), one(0177700), "#l$s", m68000up }, 2389 {"eorl", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, 2390 {"eorl", 2, one(0130600), one(0170700), "Dd$s", m68000up | mcfisa_a }, 2391 {"eor", 4, one(0005074), one(0177777), "#bCs", m68000up }, 2392 {"eor", 4, one(0005174), one(0177777), "#wSs", m68000up }, 2393 {"eor", 4, one(0005100), one(0177700), "#w$s", m68000up }, 2394 {"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up }, 2395 2396 {"exg", 2, one(0140500), one(0170770), "DdDs", m68000up }, 2397 {"exg", 2, one(0140510), one(0170770), "AdAs", m68000up }, 2398 {"exg", 2, one(0140610), one(0170770), "DdAs", m68000up }, 2399 {"exg", 2, one(0140610), one(0170770), "AsDd", m68000up }, 2400 2401 {"extw", 2, one(0044200), one(0177770), "Ds", m68000up|mcfisa_a }, 2402 {"extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a }, 2403 {"extbl", 2, one(0044700), one(0177770), "Ds", m68020up|cpu32|mcfisa_a }, 2404 2405 {"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa}, 2406 2407 /* float stuff starts here */ 2408 2409 {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2410 {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2411 {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2412 {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", cfloat }, 2413 {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2414 {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2415 {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2416 {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2417 {"fabsp", 4, two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2418 {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", cfloat }, 2419 {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2420 {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2421 {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2422 {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2423 {"fabsx", 4, two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2424 {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2425 2426 {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 2427 {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2428 {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2429 {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", cfloat }, 2430 {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 2431 {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2432 {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 2433 {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2434 {"fsabsp", 4, two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 2435 {"fsabss", 4, two(0xF000, 0x4258), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2436 {"fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 2437 {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 2438 {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2439 {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 2440 {"fsabsx", 4, two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 2441 {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up }, 2442 2443 {"fdabsb", 4, two(0xF000, 0x585C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2444 {"fdabsb", 4, two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up}, 2445 {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2446 {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiFt", cfloat }, 2447 {"fdabsd", 4, two(0xF000, 0x545C), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2448 {"fdabsd", 4, two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up}, 2449 {"fdabsl", 4, two(0xF000, 0x405C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2450 {"fdabsl", 4, two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up}, 2451 {"fdabsp", 4, two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up}, 2452 {"fdabss", 4, two(0xF000, 0x425C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2453 {"fdabss", 4, two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up}, 2454 {"fdabsw", 4, two(0xF000, 0x505C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2455 {"fdabsw", 4, two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up}, 2456 {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up}, 2457 {"fdabsx", 4, two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up}, 2458 {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up}, 2459 2460 {"facosb", 4, two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2461 {"facosd", 4, two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2462 {"facosl", 4, two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2463 {"facosp", 4, two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2464 {"facoss", 4, two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2465 {"facosw", 4, two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2466 {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2467 {"facosx", 4, two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2468 {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2469 2470 {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2471 {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2472 {"faddd", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2473 {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2474 {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2475 {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2476 {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2477 {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2478 {"faddp", 4, two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2479 {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2480 {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2481 {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2482 {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2483 {"faddx", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2484 {"faddx", 4, two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2485 2486 {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 2487 {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2488 {"fsaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2489 {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 2490 {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2491 {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 2492 {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2493 {"fsaddp", 4, two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 2494 {"fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 2495 {"fsadds", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2496 {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 2497 {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2498 {"fsaddx", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 2499 {"fsaddx", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 2500 2501 {"fdaddb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2502 {"fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 2503 {"fdaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2504 {"fdaddd", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2505 {"fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 2506 {"fdaddl", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2507 {"fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 2508 {"fdaddp", 4, two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 2509 {"fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 2510 {"fdadds", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2511 {"fdaddw", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2512 {"fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 2513 {"fdaddx", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 2514 {"fdaddx", 4, two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 2515 2516 {"fasinb", 4, two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2517 {"fasind", 4, two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2518 {"fasinl", 4, two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2519 {"fasinp", 4, two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2520 {"fasins", 4, two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2521 {"fasinw", 4, two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2522 {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2523 {"fasinx", 4, two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2524 {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2525 2526 {"fatanb", 4, two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2527 {"fatand", 4, two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2528 {"fatanl", 4, two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2529 {"fatanp", 4, two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2530 {"fatans", 4, two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2531 {"fatanw", 4, two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2532 {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2533 {"fatanx", 4, two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2534 {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2535 2536 {"fatanhb", 4, two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2537 {"fatanhd", 4, two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2538 {"fatanhl", 4, two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2539 {"fatanhp", 4, two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2540 {"fatanhs", 4, two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2541 {"fatanhw", 4, two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2542 {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2543 {"fatanhx", 4, two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2544 {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2545 2546 {"fbeq", 2, one(0xF081), one(0xF1FF), "IdBW", mfloat | cfloat }, 2547 {"fbf", 2, one(0xF080), one(0xF1FF), "IdBW", mfloat | cfloat }, 2548 {"fbge", 2, one(0xF093), one(0xF1FF), "IdBW", mfloat | cfloat }, 2549 {"fbgl", 2, one(0xF096), one(0xF1FF), "IdBW", mfloat | cfloat }, 2550 {"fbgle", 2, one(0xF097), one(0xF1FF), "IdBW", mfloat | cfloat }, 2551 {"fbgt", 2, one(0xF092), one(0xF1FF), "IdBW", mfloat | cfloat }, 2552 {"fble", 2, one(0xF095), one(0xF1FF), "IdBW", mfloat | cfloat }, 2553 {"fblt", 2, one(0xF094), one(0xF1FF), "IdBW", mfloat | cfloat }, 2554 {"fbne", 2, one(0xF08E), one(0xF1FF), "IdBW", mfloat | cfloat }, 2555 {"fbnge", 2, one(0xF09C), one(0xF1FF), "IdBW", mfloat | cfloat }, 2556 {"fbngl", 2, one(0xF099), one(0xF1FF), "IdBW", mfloat | cfloat }, 2557 {"fbngle", 2, one(0xF098), one(0xF1FF), "IdBW", mfloat | cfloat }, 2558 {"fbngt", 2, one(0xF09D), one(0xF1FF), "IdBW", mfloat | cfloat }, 2559 {"fbnle", 2, one(0xF09A), one(0xF1FF), "IdBW", mfloat | cfloat }, 2560 {"fbnlt", 2, one(0xF09B), one(0xF1FF), "IdBW", mfloat | cfloat }, 2561 {"fboge", 2, one(0xF083), one(0xF1FF), "IdBW", mfloat | cfloat }, 2562 {"fbogl", 2, one(0xF086), one(0xF1FF), "IdBW", mfloat | cfloat }, 2563 {"fbogt", 2, one(0xF082), one(0xF1FF), "IdBW", mfloat | cfloat }, 2564 {"fbole", 2, one(0xF085), one(0xF1FF), "IdBW", mfloat | cfloat }, 2565 {"fbolt", 2, one(0xF084), one(0xF1FF), "IdBW", mfloat | cfloat }, 2566 {"fbor", 2, one(0xF087), one(0xF1FF), "IdBW", mfloat | cfloat }, 2567 {"fbseq", 2, one(0xF091), one(0xF1FF), "IdBW", mfloat | cfloat }, 2568 {"fbsf", 2, one(0xF090), one(0xF1FF), "IdBW", mfloat | cfloat }, 2569 {"fbsne", 2, one(0xF09E), one(0xF1FF), "IdBW", mfloat | cfloat }, 2570 {"fbst", 2, one(0xF09F), one(0xF1FF), "IdBW", mfloat | cfloat }, 2571 {"fbt", 2, one(0xF08F), one(0xF1FF), "IdBW", mfloat | cfloat }, 2572 {"fbueq", 2, one(0xF089), one(0xF1FF), "IdBW", mfloat | cfloat }, 2573 {"fbuge", 2, one(0xF08B), one(0xF1FF), "IdBW", mfloat | cfloat }, 2574 {"fbugt", 2, one(0xF08A), one(0xF1FF), "IdBW", mfloat | cfloat }, 2575 {"fbule", 2, one(0xF08D), one(0xF1FF), "IdBW", mfloat | cfloat }, 2576 {"fbult", 2, one(0xF08C), one(0xF1FF), "IdBW", mfloat | cfloat }, 2577 {"fbun", 2, one(0xF088), one(0xF1FF), "IdBW", mfloat | cfloat }, 2578 2579 {"fbeql", 2, one(0xF0C1), one(0xF1FF), "IdBC", mfloat | cfloat }, 2580 {"fbfl", 2, one(0xF0C0), one(0xF1FF), "IdBC", mfloat | cfloat }, 2581 {"fbgel", 2, one(0xF0D3), one(0xF1FF), "IdBC", mfloat | cfloat }, 2582 {"fbgll", 2, one(0xF0D6), one(0xF1FF), "IdBC", mfloat | cfloat }, 2583 {"fbglel", 2, one(0xF0D7), one(0xF1FF), "IdBC", mfloat | cfloat }, 2584 {"fbgtl", 2, one(0xF0D2), one(0xF1FF), "IdBC", mfloat | cfloat }, 2585 {"fblel", 2, one(0xF0D5), one(0xF1FF), "IdBC", mfloat | cfloat }, 2586 {"fbltl", 2, one(0xF0D4), one(0xF1FF), "IdBC", mfloat | cfloat }, 2587 {"fbnel", 2, one(0xF0CE), one(0xF1FF), "IdBC", mfloat | cfloat }, 2588 {"fbngel", 2, one(0xF0DC), one(0xF1FF), "IdBC", mfloat | cfloat }, 2589 {"fbngll", 2, one(0xF0D9), one(0xF1FF), "IdBC", mfloat | cfloat }, 2590 {"fbnglel", 2, one(0xF0D8), one(0xF1FF), "IdBC", mfloat | cfloat }, 2591 {"fbngtl", 2, one(0xF0DD), one(0xF1FF), "IdBC", mfloat | cfloat }, 2592 {"fbnlel", 2, one(0xF0DA), one(0xF1FF), "IdBC", mfloat | cfloat }, 2593 {"fbnltl", 2, one(0xF0DB), one(0xF1FF), "IdBC", mfloat | cfloat }, 2594 {"fbogel", 2, one(0xF0C3), one(0xF1FF), "IdBC", mfloat | cfloat }, 2595 {"fbogll", 2, one(0xF0C6), one(0xF1FF), "IdBC", mfloat | cfloat }, 2596 {"fbogtl", 2, one(0xF0C2), one(0xF1FF), "IdBC", mfloat | cfloat }, 2597 {"fbolel", 2, one(0xF0C5), one(0xF1FF), "IdBC", mfloat | cfloat }, 2598 {"fboltl", 2, one(0xF0C4), one(0xF1FF), "IdBC", mfloat | cfloat }, 2599 {"fborl", 2, one(0xF0C7), one(0xF1FF), "IdBC", mfloat | cfloat }, 2600 {"fbseql", 2, one(0xF0D1), one(0xF1FF), "IdBC", mfloat | cfloat }, 2601 {"fbsfl", 2, one(0xF0D0), one(0xF1FF), "IdBC", mfloat | cfloat }, 2602 {"fbsnel", 2, one(0xF0DE), one(0xF1FF), "IdBC", mfloat | cfloat }, 2603 {"fbstl", 2, one(0xF0DF), one(0xF1FF), "IdBC", mfloat | cfloat }, 2604 {"fbtl", 2, one(0xF0CF), one(0xF1FF), "IdBC", mfloat | cfloat }, 2605 {"fbueql", 2, one(0xF0C9), one(0xF1FF), "IdBC", mfloat | cfloat }, 2606 {"fbugel", 2, one(0xF0CB), one(0xF1FF), "IdBC", mfloat | cfloat }, 2607 {"fbugtl", 2, one(0xF0CA), one(0xF1FF), "IdBC", mfloat | cfloat }, 2608 {"fbulel", 2, one(0xF0CD), one(0xF1FF), "IdBC", mfloat | cfloat }, 2609 {"fbultl", 2, one(0xF0CC), one(0xF1FF), "IdBC", mfloat | cfloat }, 2610 {"fbunl", 2, one(0xF0C8), one(0xF1FF), "IdBC", mfloat | cfloat }, 2611 2612 {"fjeq", 2, one(0xF081), one(0xF1BF), "IdBc", mfloat | cfloat }, 2613 {"fjf", 2, one(0xF080), one(0xF1BF), "IdBc", mfloat | cfloat }, 2614 {"fjge", 2, one(0xF093), one(0xF1BF), "IdBc", mfloat | cfloat }, 2615 {"fjgl", 2, one(0xF096), one(0xF1BF), "IdBc", mfloat | cfloat }, 2616 {"fjgle", 2, one(0xF097), one(0xF1BF), "IdBc", mfloat | cfloat }, 2617 {"fjgt", 2, one(0xF092), one(0xF1BF), "IdBc", mfloat | cfloat }, 2618 {"fjle", 2, one(0xF095), one(0xF1BF), "IdBc", mfloat | cfloat }, 2619 {"fjlt", 2, one(0xF094), one(0xF1BF), "IdBc", mfloat | cfloat }, 2620 {"fjne", 2, one(0xF08E), one(0xF1BF), "IdBc", mfloat | cfloat }, 2621 {"fjnge", 2, one(0xF09C), one(0xF1BF), "IdBc", mfloat | cfloat }, 2622 {"fjngl", 2, one(0xF099), one(0xF1BF), "IdBc", mfloat | cfloat }, 2623 {"fjngle", 2, one(0xF098), one(0xF1BF), "IdBc", mfloat | cfloat }, 2624 {"fjngt", 2, one(0xF09D), one(0xF1BF), "IdBc", mfloat | cfloat }, 2625 {"fjnle", 2, one(0xF09A), one(0xF1BF), "IdBc", mfloat | cfloat }, 2626 {"fjnlt", 2, one(0xF09B), one(0xF1BF), "IdBc", mfloat | cfloat }, 2627 {"fjoge", 2, one(0xF083), one(0xF1BF), "IdBc", mfloat | cfloat }, 2628 {"fjogl", 2, one(0xF086), one(0xF1BF), "IdBc", mfloat | cfloat }, 2629 {"fjogt", 2, one(0xF082), one(0xF1BF), "IdBc", mfloat | cfloat }, 2630 {"fjole", 2, one(0xF085), one(0xF1BF), "IdBc", mfloat | cfloat }, 2631 {"fjolt", 2, one(0xF084), one(0xF1BF), "IdBc", mfloat | cfloat }, 2632 {"fjor", 2, one(0xF087), one(0xF1BF), "IdBc", mfloat | cfloat }, 2633 {"fjseq", 2, one(0xF091), one(0xF1BF), "IdBc", mfloat | cfloat }, 2634 {"fjsf", 2, one(0xF090), one(0xF1BF), "IdBc", mfloat | cfloat }, 2635 {"fjsne", 2, one(0xF09E), one(0xF1BF), "IdBc", mfloat | cfloat }, 2636 {"fjst", 2, one(0xF09F), one(0xF1BF), "IdBc", mfloat | cfloat }, 2637 {"fjt", 2, one(0xF08F), one(0xF1BF), "IdBc", mfloat | cfloat }, 2638 {"fjueq", 2, one(0xF089), one(0xF1BF), "IdBc", mfloat | cfloat }, 2639 {"fjuge", 2, one(0xF08B), one(0xF1BF), "IdBc", mfloat | cfloat }, 2640 {"fjugt", 2, one(0xF08A), one(0xF1BF), "IdBc", mfloat | cfloat }, 2641 {"fjule", 2, one(0xF08D), one(0xF1BF), "IdBc", mfloat | cfloat }, 2642 {"fjult", 2, one(0xF08C), one(0xF1BF), "IdBc", mfloat | cfloat }, 2643 {"fjun", 2, one(0xF088), one(0xF1BF), "IdBc", mfloat | cfloat }, 2644 2645 {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2646 {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2647 {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2648 {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2649 {"fcmpd", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2650 {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2651 {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2652 {"fcmpp", 4, two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2653 {"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2654 {"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2655 {"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2656 {"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2657 {"fcmpx", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2658 {"fcmpx", 4, two(0xF000, 0x4838), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2659 2660 {"fcosb", 4, two(0xF000, 0x581D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2661 {"fcosd", 4, two(0xF000, 0x541D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2662 {"fcosl", 4, two(0xF000, 0x401D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2663 {"fcosp", 4, two(0xF000, 0x4C1D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2664 {"fcoss", 4, two(0xF000, 0x441D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2665 {"fcosw", 4, two(0xF000, 0x501D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2666 {"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2667 {"fcosx", 4, two(0xF000, 0x481D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2668 {"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2669 2670 {"fcoshb", 4, two(0xF000, 0x5819), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2671 {"fcoshd", 4, two(0xF000, 0x5419), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2672 {"fcoshl", 4, two(0xF000, 0x4019), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2673 {"fcoshp", 4, two(0xF000, 0x4C19), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2674 {"fcoshs", 4, two(0xF000, 0x4419), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2675 {"fcoshw", 4, two(0xF000, 0x5019), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2676 {"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2677 {"fcoshx", 4, two(0xF000, 0x4819), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2678 {"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2679 2680 {"fdbeq", 4, two(0xF048, 0x0001), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2681 {"fdbf", 4, two(0xF048, 0x0000), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2682 {"fdbge", 4, two(0xF048, 0x0013), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2683 {"fdbgl", 4, two(0xF048, 0x0016), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2684 {"fdbgle", 4, two(0xF048, 0x0017), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2685 {"fdbgt", 4, two(0xF048, 0x0012), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2686 {"fdble", 4, two(0xF048, 0x0015), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2687 {"fdblt", 4, two(0xF048, 0x0014), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2688 {"fdbne", 4, two(0xF048, 0x000E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2689 {"fdbnge", 4, two(0xF048, 0x001C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2690 {"fdbngl", 4, two(0xF048, 0x0019), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2691 {"fdbngle", 4, two(0xF048, 0x0018), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2692 {"fdbngt", 4, two(0xF048, 0x001D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2693 {"fdbnle", 4, two(0xF048, 0x001A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2694 {"fdbnlt", 4, two(0xF048, 0x001B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2695 {"fdboge", 4, two(0xF048, 0x0003), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2696 {"fdbogl", 4, two(0xF048, 0x0006), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2697 {"fdbogt", 4, two(0xF048, 0x0002), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2698 {"fdbole", 4, two(0xF048, 0x0005), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2699 {"fdbolt", 4, two(0xF048, 0x0004), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2700 {"fdbor", 4, two(0xF048, 0x0007), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2701 {"fdbseq", 4, two(0xF048, 0x0011), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2702 {"fdbsf", 4, two(0xF048, 0x0010), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2703 {"fdbsne", 4, two(0xF048, 0x001E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2704 {"fdbst", 4, two(0xF048, 0x001F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2705 {"fdbt", 4, two(0xF048, 0x000F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2706 {"fdbueq", 4, two(0xF048, 0x0009), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2707 {"fdbuge", 4, two(0xF048, 0x000B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2708 {"fdbugt", 4, two(0xF048, 0x000A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2709 {"fdbule", 4, two(0xF048, 0x000D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2710 {"fdbult", 4, two(0xF048, 0x000C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2711 {"fdbun", 4, two(0xF048, 0x0008), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, 2712 2713 {"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2714 {"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2715 {"fdivd", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2716 {"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2717 {"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2718 {"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2719 {"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2720 {"fdivp", 4, two(0xF000, 0x4C20), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2721 {"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2722 {"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2723 {"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2724 {"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2725 {"fdivx", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2726 {"fdivx", 4, two(0xF000, 0x4820), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2727 2728 {"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 2729 {"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2730 {"fsdivd", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2731 {"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 2732 {"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2733 {"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 2734 {"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2735 {"fsdivp", 4, two(0xF000, 0x4C60), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 2736 {"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 2737 {"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2738 {"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 2739 {"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2740 {"fsdivx", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 2741 {"fsdivx", 4, two(0xF000, 0x4860), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 2742 2743 {"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 2744 {"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2745 {"fddivd", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2746 {"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 2747 {"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2748 {"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 2749 {"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2750 {"fddivp", 4, two(0xF000, 0x4C64), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 2751 {"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 2752 {"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2753 {"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 2754 {"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2755 {"fddivx", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 2756 {"fddivx", 4, two(0xF000, 0x4864), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 2757 2758 {"fetoxb", 4, two(0xF000, 0x5810), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2759 {"fetoxd", 4, two(0xF000, 0x5410), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2760 {"fetoxl", 4, two(0xF000, 0x4010), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2761 {"fetoxp", 4, two(0xF000, 0x4C10), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2762 {"fetoxs", 4, two(0xF000, 0x4410), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2763 {"fetoxw", 4, two(0xF000, 0x5010), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2764 {"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2765 {"fetoxx", 4, two(0xF000, 0x4810), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2766 {"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2767 2768 {"fetoxm1b", 4, two(0xF000, 0x5808), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2769 {"fetoxm1d", 4, two(0xF000, 0x5408), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2770 {"fetoxm1l", 4, two(0xF000, 0x4008), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2771 {"fetoxm1p", 4, two(0xF000, 0x4C08), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2772 {"fetoxm1s", 4, two(0xF000, 0x4408), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2773 {"fetoxm1w", 4, two(0xF000, 0x5008), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2774 {"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2775 {"fetoxm1x", 4, two(0xF000, 0x4808), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2776 {"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2777 2778 {"fgetexpb", 4, two(0xF000, 0x581E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2779 {"fgetexpd", 4, two(0xF000, 0x541E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2780 {"fgetexpl", 4, two(0xF000, 0x401E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2781 {"fgetexpp", 4, two(0xF000, 0x4C1E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2782 {"fgetexps", 4, two(0xF000, 0x441E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2783 {"fgetexpw", 4, two(0xF000, 0x501E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2784 {"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2785 {"fgetexpx", 4, two(0xF000, 0x481E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2786 {"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2787 2788 {"fgetmanb", 4, two(0xF000, 0x581F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2789 {"fgetmand", 4, two(0xF000, 0x541F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2790 {"fgetmanl", 4, two(0xF000, 0x401F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2791 {"fgetmanp", 4, two(0xF000, 0x4C1F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2792 {"fgetmans", 4, two(0xF000, 0x441F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2793 {"fgetmanw", 4, two(0xF000, 0x501F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2794 {"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2795 {"fgetmanx", 4, two(0xF000, 0x481F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2796 {"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2797 2798 {"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2799 {"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2800 {"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2801 {"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", cfloat }, 2802 {"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2803 {"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2804 {"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2805 {"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2806 {"fintp", 4, two(0xF000, 0x4C01), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2807 {"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2808 {"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2809 {"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2810 {"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2811 {"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2812 {"fintx", 4, two(0xF000, 0x4801), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2813 {"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2814 2815 {"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2816 {"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2817 {"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2818 {"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", cfloat }, 2819 {"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2820 {"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2821 {"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2822 {"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2823 {"fintrzp", 4, two(0xF000, 0x4C03), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2824 {"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2825 {"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2826 {"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2827 {"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2828 {"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2829 {"fintrzx", 4, two(0xF000, 0x4803), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2830 {"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2831 2832 {"flog10b", 4, two(0xF000, 0x5815), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2833 {"flog10d", 4, two(0xF000, 0x5415), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2834 {"flog10l", 4, two(0xF000, 0x4015), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2835 {"flog10p", 4, two(0xF000, 0x4C15), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2836 {"flog10s", 4, two(0xF000, 0x4415), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2837 {"flog10w", 4, two(0xF000, 0x5015), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2838 {"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2839 {"flog10x", 4, two(0xF000, 0x4815), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2840 {"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2841 2842 {"flog2b", 4, two(0xF000, 0x5816), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2843 {"flog2d", 4, two(0xF000, 0x5416), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2844 {"flog2l", 4, two(0xF000, 0x4016), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2845 {"flog2p", 4, two(0xF000, 0x4C16), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2846 {"flog2s", 4, two(0xF000, 0x4416), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2847 {"flog2w", 4, two(0xF000, 0x5016), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2848 {"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2849 {"flog2x", 4, two(0xF000, 0x4816), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2850 {"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2851 2852 {"flognb", 4, two(0xF000, 0x5814), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2853 {"flognd", 4, two(0xF000, 0x5414), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2854 {"flognl", 4, two(0xF000, 0x4014), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2855 {"flognp", 4, two(0xF000, 0x4C14), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2856 {"flogns", 4, two(0xF000, 0x4414), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2857 {"flognw", 4, two(0xF000, 0x5014), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2858 {"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2859 {"flognx", 4, two(0xF000, 0x4814), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2860 {"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2861 2862 {"flognp1b", 4, two(0xF000, 0x5806), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2863 {"flognp1d", 4, two(0xF000, 0x5406), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2864 {"flognp1l", 4, two(0xF000, 0x4006), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2865 {"flognp1p", 4, two(0xF000, 0x4C06), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2866 {"flognp1s", 4, two(0xF000, 0x4406), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2867 {"flognp1w", 4, two(0xF000, 0x5006), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2868 {"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2869 {"flognp1x", 4, two(0xF000, 0x4806), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2870 {"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 2871 2872 {"fmodb", 4, two(0xF000, 0x5821), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2873 {"fmodd", 4, two(0xF000, 0x5421), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2874 {"fmodl", 4, two(0xF000, 0x4021), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2875 {"fmodp", 4, two(0xF000, 0x4C21), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2876 {"fmods", 4, two(0xF000, 0x4421), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2877 {"fmodw", 4, two(0xF000, 0x5021), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2878 {"fmodx", 4, two(0xF000, 0x0021), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 2879 {"fmodx", 4, two(0xF000, 0x4821), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2880 2881 {"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2882 {"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, 2883 {"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 2884 {"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7$b", mfloat }, 2885 {"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 2886 {"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7~F", mfloat }, 2887 {"fmoved", 4, two(0xF000, 0x0000), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2888 {"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2889 {"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, 2890 {"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 2891 {"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7$l", mfloat }, 2892 /* FIXME: the next two variants should not permit moving an address 2893 register to anything but the floating point instruction register. */ 2894 {"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, 2895 {"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ls8", mfloat }, 2896 {"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2897 {"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, 2898 /* Move the FP control registers. */ 2899 {"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8ps", cfloat }, 2900 {"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Iibss8", cfloat }, 2901 {"fmovep", 4, two(0xF000, 0x4C00), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 2902 {"fmovep", 4, two(0xF000, 0x6C00), two(0xF1C0, 0xFC00), "IiF7~pkC", mfloat }, 2903 {"fmovep", 4, two(0xF000, 0x7C00), two(0xF1C0, 0xFC0F), "IiF7~pDk", mfloat }, 2904 {"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 2905 {"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7$f", mfloat }, 2906 {"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2907 {"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, 2908 {"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 2909 {"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7$w", mfloat }, 2910 {"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2911 {"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, 2912 {"fmovex", 4, two(0xF000, 0x0000), two(0xF1FF, 0xE07F), "IiF8F7", mfloat }, 2913 {"fmovex", 4, two(0xF000, 0x4800), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 2914 {"fmovex", 4, two(0xF000, 0x6800), two(0xF1C0, 0xFC7F), "IiF7~x", mfloat }, 2915 2916 {"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 2917 {"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2918 {"fsmoveb", 4, two(0xF000, 0x7840), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, 2919 {"fsmoved", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2920 {"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 2921 {"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2922 {"fsmoved", 4, two(0xF000, 0x7440), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, 2923 {"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 2924 {"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2925 {"fsmovel", 4, two(0xF000, 0x6040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, 2926 {"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 2927 {"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2928 {"fsmoves", 4, two(0xF000, 0x6440), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, 2929 {"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 2930 {"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2931 {"fsmovew", 4, two(0xF000, 0x7040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, 2932 {"fsmovex", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 2933 {"fsmovex", 4, two(0xF000, 0x4840), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 2934 {"fsmovep", 4, two(0xF000, 0x4C40), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 2935 2936 {"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 2937 {"fdmoveb", 4, two(0xF000, 0x5844), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2938 {"fdmoveb", 4, two(0xF000, 0x7844), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, 2939 {"fdmoved", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 2940 {"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 2941 {"fdmoved", 4, two(0xF000, 0x5444), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 2942 {"fdmoved", 4, two(0xF000, 0x7444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, 2943 {"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 2944 {"fdmovel", 4, two(0xF000, 0x4044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2945 {"fdmovel", 4, two(0xF000, 0x6044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, 2946 {"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 2947 {"fdmoves", 4, two(0xF000, 0x4444), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2948 {"fdmoves", 4, two(0xF000, 0x6444), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, 2949 {"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 2950 {"fdmovew", 4, two(0xF000, 0x5044), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 2951 {"fdmovew", 4, two(0xF000, 0x7044), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, 2952 {"fdmovex", 4, two(0xF000, 0x0044), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 2953 {"fdmovex", 4, two(0xF000, 0x4844), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 2954 {"fdmovep", 4, two(0xF000, 0x4C44), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 2955 2956 {"fmovecrx", 4, two(0xF000, 0x5C00), two(0xF1FF, 0xFC00), "Ii#CF7", mfloat }, 2957 2958 {"fmovemd", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizsl3", cfloat }, 2959 {"fmovemd", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat }, 2960 {"fmovemd", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat }, 2961 {"fmovemd", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Iil3ys", cfloat }, 2962 2963 {"fmovemx", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, 2964 {"fmovemx", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, 2965 {"fmovemx", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, 2966 {"fmovemx", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, 2967 {"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, 2968 {"fmovemx", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, 2969 {"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, 2970 {"fmovemx", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, 2971 {"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, 2972 {"fmovemx", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, 2973 {"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, 2974 {"fmovemx", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, 2975 2976 {"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, 2977 {"fmoveml", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, 2978 /* FIXME: In the next instruction, we should only permit %dn if the 2979 target is a single register. We should only permit %an if the 2980 target is a single %fpiar. */ 2981 {"fmoveml", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*lL8", mfloat }, 2982 2983 {"fmovem", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "IizsL3", cfloat }, 2984 {"fmovem", 4, two(0xF000, 0xD000), two(0xFFC0, 0xFF00), "Iizs#3", cfloat }, 2985 {"fmovem", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "Ii#3ys", cfloat }, 2986 {"fmovem", 4, two(0xF000, 0xF000), two(0xFFC0, 0xFF00), "IiL3ys", cfloat }, 2987 2988 {"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "IdL3-s", mfloat }, 2989 {"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Idl3&s", mfloat }, 2990 {"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+sl3", mfloat }, 2991 {"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&sl3", mfloat }, 2992 {"fmovem", 4, two(0xF020, 0xE000), two(0xF1F8, 0xFF00), "Id#3-s", mfloat }, 2993 {"fmovem", 4, two(0xF020, 0xE800), two(0xF1F8, 0xFF8F), "IiDk-s", mfloat }, 2994 {"fmovem", 4, two(0xF000, 0xF000), two(0xF1C0, 0xFF00), "Id#3&s", mfloat }, 2995 {"fmovem", 4, two(0xF000, 0xF800), two(0xF1C0, 0xFF8F), "IiDk&s", mfloat }, 2996 {"fmovem", 4, two(0xF018, 0xD000), two(0xF1F8, 0xFF00), "Id+s#3", mfloat }, 2997 {"fmovem", 4, two(0xF018, 0xD800), two(0xF1F8, 0xFF8F), "Ii+sDk", mfloat }, 2998 {"fmovem", 4, two(0xF000, 0xD000), two(0xF1C0, 0xFF00), "Id&s#3", mfloat }, 2999 {"fmovem", 4, two(0xF000, 0xD800), two(0xF1C0, 0xFF8F), "Ii&sDk", mfloat }, 3000 {"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, 3001 {"fmovem", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ss8", mfloat }, 3002 {"fmovem", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "IiL8~s", mfloat }, 3003 {"fmovem", 4, two(0xF000, 0x8000), two(0xF2C0, 0xE3FF), "Ii*sL8", mfloat }, 3004 3005 {"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3006 {"fmulb", 4, two(0xF000, 0x5823), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3007 {"fmuld", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3008 {"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3009 {"fmuld", 4, two(0xF000, 0x5423), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 3010 {"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3011 {"fmull", 4, two(0xF000, 0x4023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3012 {"fmulp", 4, two(0xF000, 0x4C23), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3013 {"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3014 {"fmuls", 4, two(0xF000, 0x4423), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3015 {"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3016 {"fmulw", 4, two(0xF000, 0x5023), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3017 {"fmulx", 4, two(0xF000, 0x0023), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3018 {"fmulx", 4, two(0xF000, 0x4823), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3019 3020 {"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 3021 {"fsmulb", 4, two(0xF000, 0x5863), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3022 {"fsmuld", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3023 {"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 3024 {"fsmuld", 4, two(0xF000, 0x5463), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 3025 {"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 3026 {"fsmull", 4, two(0xF000, 0x4063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3027 {"fsmulp", 4, two(0xF000, 0x4C63), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 3028 {"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 3029 {"fsmuls", 4, two(0xF000, 0x4463), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3030 {"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 3031 {"fsmulw", 4, two(0xF000, 0x5063), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3032 {"fsmulx", 4, two(0xF000, 0x0063), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 3033 {"fsmulx", 4, two(0xF000, 0x4863), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 3034 3035 {"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 3036 {"fdmulb", 4, two(0xF000, 0x5867), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3037 {"fdmuld", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3038 {"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 3039 {"fdmuld", 4, two(0xF000, 0x5467), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 3040 {"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 3041 {"fdmull", 4, two(0xF000, 0x4067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3042 {"fdmulp", 4, two(0xF000, 0x4C67), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 3043 {"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 3044 {"fdmuls", 4, two(0xF000, 0x4467), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3045 {"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 3046 {"fdmulw", 4, two(0xF000, 0x5067), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3047 {"fdmulx", 4, two(0xF000, 0x0067), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 3048 {"fdmulx", 4, two(0xF000, 0x4867), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 3049 3050 {"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3051 {"fnegb", 4, two(0xF000, 0x581A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3052 {"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3053 {"fnegd", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", cfloat }, 3054 {"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3055 {"fnegd", 4, two(0xF000, 0x541A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 3056 {"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3057 {"fnegl", 4, two(0xF000, 0x401A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3058 {"fnegp", 4, two(0xF000, 0x4C1A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3059 {"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3060 {"fnegs", 4, two(0xF000, 0x441A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3061 {"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3062 {"fnegw", 4, two(0xF000, 0x501A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3063 {"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3064 {"fnegx", 4, two(0xF000, 0x481A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3065 {"fnegx", 4, two(0xF000, 0x001A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 3066 3067 {"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 3068 {"fsnegb", 4, two(0xF000, 0x585A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3069 {"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3070 {"fsnegd", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", cfloat }, 3071 {"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 3072 {"fsnegd", 4, two(0xF000, 0x545A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 3073 {"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 3074 {"fsnegl", 4, two(0xF000, 0x405A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3075 {"fsnegp", 4, two(0xF000, 0x4C5A), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 3076 {"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 3077 {"fsnegs", 4, two(0xF000, 0x445A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3078 {"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 3079 {"fsnegw", 4, two(0xF000, 0x505A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3080 {"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 3081 {"fsnegx", 4, two(0xF000, 0x485A), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 3082 {"fsnegx", 4, two(0xF000, 0x005A), two(0xF1C0, 0xE07F), "IiFt", m68040up }, 3083 3084 {"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 3085 {"fdnegb", 4, two(0xF000, 0x585E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3086 {"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3087 {"fdnegd", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", cfloat }, 3088 {"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 3089 {"fdnegd", 4, two(0xF000, 0x545E), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 3090 {"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 3091 {"fdnegl", 4, two(0xF000, 0x405E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3092 {"fdnegp", 4, two(0xF000, 0x4C5E), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 3093 {"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 3094 {"fdnegs", 4, two(0xF000, 0x445E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3095 {"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 3096 {"fdnegw", 4, two(0xF000, 0x505E), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3097 {"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 3098 {"fdnegx", 4, two(0xF000, 0x485E), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 3099 {"fdnegx", 4, two(0xF000, 0x005E), two(0xF1C0, 0xE07F), "IiFt", m68040up }, 3100 3101 {"fnop", 4, two(0xF280, 0x0000), two(0xFFFF, 0xFFFF), "Ii", mfloat | cfloat }, 3102 3103 {"fremb", 4, two(0xF000, 0x5825), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3104 {"fremd", 4, two(0xF000, 0x5425), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3105 {"freml", 4, two(0xF000, 0x4025), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3106 {"fremp", 4, two(0xF000, 0x4C25), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3107 {"frems", 4, two(0xF000, 0x4425), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3108 {"fremw", 4, two(0xF000, 0x5025), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3109 {"fremx", 4, two(0xF000, 0x0025), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3110 {"fremx", 4, two(0xF000, 0x4825), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3111 3112 {"frestore", 2, one(0xF140), one(0xF1C0), "Id<s", mfloat }, 3113 {"frestore", 2, one(0xF140), one(0xF1C0), "Idys", cfloat }, 3114 3115 {"fsave", 2, one(0xF100), one(0xF1C0), "Id>s", mfloat }, 3116 {"fsave", 2, one(0xF100), one(0xF1C0), "Idzs", cfloat }, 3117 3118 {"fscaleb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3119 {"fscaled", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3120 {"fscalel", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3121 {"fscalep", 4, two(0xF000, 0x4C26), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3122 {"fscales", 4, two(0xF000, 0x4426), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3123 {"fscalew", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3124 {"fscalex", 4, two(0xF000, 0x0026), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3125 {"fscalex", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3126 3127 /* $ is necessary to prevent the assembler from using PC-relative. 3128 If @ were used, "label: fseq label" could produce "ftrapeq", 2, 3129 because "label" became "pc@label". */ 3130 {"fseq", 4, two(0xF040, 0x0001), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3131 {"fsf", 4, two(0xF040, 0x0000), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3132 {"fsge", 4, two(0xF040, 0x0013), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3133 {"fsgl", 4, two(0xF040, 0x0016), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3134 {"fsgle", 4, two(0xF040, 0x0017), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3135 {"fsgt", 4, two(0xF040, 0x0012), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3136 {"fsle", 4, two(0xF040, 0x0015), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3137 {"fslt", 4, two(0xF040, 0x0014), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3138 {"fsne", 4, two(0xF040, 0x000E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3139 {"fsnge", 4, two(0xF040, 0x001C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3140 {"fsngl", 4, two(0xF040, 0x0019), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3141 {"fsngle", 4, two(0xF040, 0x0018), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3142 {"fsngt", 4, two(0xF040, 0x001D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3143 {"fsnle", 4, two(0xF040, 0x001A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3144 {"fsnlt", 4, two(0xF040, 0x001B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3145 {"fsoge", 4, two(0xF040, 0x0003), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3146 {"fsogl", 4, two(0xF040, 0x0006), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3147 {"fsogt", 4, two(0xF040, 0x0002), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3148 {"fsole", 4, two(0xF040, 0x0005), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3149 {"fsolt", 4, two(0xF040, 0x0004), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3150 {"fsor", 4, two(0xF040, 0x0007), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3151 {"fsseq", 4, two(0xF040, 0x0011), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3152 {"fssf", 4, two(0xF040, 0x0010), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3153 {"fssne", 4, two(0xF040, 0x001E), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3154 {"fsst", 4, two(0xF040, 0x001F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3155 {"fst", 4, two(0xF040, 0x000F), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3156 {"fsueq", 4, two(0xF040, 0x0009), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3157 {"fsuge", 4, two(0xF040, 0x000B), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3158 {"fsugt", 4, two(0xF040, 0x000A), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3159 {"fsule", 4, two(0xF040, 0x000D), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3160 {"fsult", 4, two(0xF040, 0x000C), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3161 {"fsun", 4, two(0xF040, 0x0008), two(0xF1C0, 0xFFFF), "Ii$s", mfloat }, 3162 3163 {"fsgldivb", 4, two(0xF000, 0x5824), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3164 {"fsgldivd", 4, two(0xF000, 0x5424), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3165 {"fsgldivl", 4, two(0xF000, 0x4024), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3166 {"fsgldivp", 4, two(0xF000, 0x4C24), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3167 {"fsgldivs", 4, two(0xF000, 0x4424), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3168 {"fsgldivw", 4, two(0xF000, 0x5024), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3169 {"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3170 {"fsgldivx", 4, two(0xF000, 0x4824), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3171 {"fsgldivx", 4, two(0xF000, 0x0024), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 3172 3173 {"fsglmulb", 4, two(0xF000, 0x5827), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3174 {"fsglmuld", 4, two(0xF000, 0x5427), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3175 {"fsglmull", 4, two(0xF000, 0x4027), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3176 {"fsglmulp", 4, two(0xF000, 0x4C27), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3177 {"fsglmuls", 4, two(0xF000, 0x4427), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3178 {"fsglmulw", 4, two(0xF000, 0x5027), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3179 {"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3180 {"fsglmulx", 4, two(0xF000, 0x4827), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3181 {"fsglmulx", 4, two(0xF000, 0x0027), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 3182 3183 {"fsinb", 4, two(0xF000, 0x580E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3184 {"fsind", 4, two(0xF000, 0x540E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3185 {"fsinl", 4, two(0xF000, 0x400E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3186 {"fsinp", 4, two(0xF000, 0x4C0E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3187 {"fsins", 4, two(0xF000, 0x440E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3188 {"fsinw", 4, two(0xF000, 0x500E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3189 {"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3190 {"fsinx", 4, two(0xF000, 0x480E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3191 {"fsinx", 4, two(0xF000, 0x000E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 3192 3193 {"fsincosb", 4, two(0xF000, 0x5830), two(0xF1C0, 0xFC78), "Ii;bF3F7", mfloat }, 3194 {"fsincosd", 4, two(0xF000, 0x5430), two(0xF1C0, 0xFC78), "Ii;FF3F7", mfloat }, 3195 {"fsincosl", 4, two(0xF000, 0x4030), two(0xF1C0, 0xFC78), "Ii;lF3F7", mfloat }, 3196 {"fsincosp", 4, two(0xF000, 0x4C30), two(0xF1C0, 0xFC78), "Ii;pF3F7", mfloat }, 3197 {"fsincoss", 4, two(0xF000, 0x4430), two(0xF1C0, 0xFC78), "Ii;fF3F7", mfloat }, 3198 {"fsincosw", 4, two(0xF000, 0x5030), two(0xF1C0, 0xFC78), "Ii;wF3F7", mfloat }, 3199 {"fsincosx", 4, two(0xF000, 0x0030), two(0xF1C0, 0xE078), "IiF8F3F7", mfloat }, 3200 {"fsincosx", 4, two(0xF000, 0x4830), two(0xF1C0, 0xFC78), "Ii;xF3F7", mfloat }, 3201 3202 {"fsinhb", 4, two(0xF000, 0x5802), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3203 {"fsinhd", 4, two(0xF000, 0x5402), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3204 {"fsinhl", 4, two(0xF000, 0x4002), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3205 {"fsinhp", 4, two(0xF000, 0x4C02), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3206 {"fsinhs", 4, two(0xF000, 0x4402), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3207 {"fsinhw", 4, two(0xF000, 0x5002), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3208 {"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3209 {"fsinhx", 4, two(0xF000, 0x4802), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3210 {"fsinhx", 4, two(0xF000, 0x0002), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 3211 3212 {"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3213 {"fsqrtb", 4, two(0xF000, 0x5804), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3214 {"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3215 {"fsqrtd", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", cfloat }, 3216 {"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3217 {"fsqrtd", 4, two(0xF000, 0x5404), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 3218 {"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3219 {"fsqrtl", 4, two(0xF000, 0x4004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3220 {"fsqrtp", 4, two(0xF000, 0x4C04), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3221 {"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3222 {"fsqrts", 4, two(0xF000, 0x4404), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3223 {"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3224 {"fsqrtw", 4, two(0xF000, 0x5004), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3225 {"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3226 {"fsqrtx", 4, two(0xF000, 0x4804), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3227 {"fsqrtx", 4, two(0xF000, 0x0004), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 3228 3229 {"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 3230 {"fssqrtb", 4, two(0xF000, 0x5841), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3231 {"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3232 {"fssqrtd", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", cfloat }, 3233 {"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 3234 {"fssqrtd", 4, two(0xF000, 0x5441), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 3235 {"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 3236 {"fssqrtl", 4, two(0xF000, 0x4041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3237 {"fssqrtp", 4, two(0xF000, 0x4C41), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 3238 {"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 3239 {"fssqrts", 4, two(0xF000, 0x4441), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3240 {"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 3241 {"fssqrtw", 4, two(0xF000, 0x5041), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3242 {"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 3243 {"fssqrtx", 4, two(0xF000, 0x4841), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 3244 {"fssqrtx", 4, two(0xF000, 0x0041), two(0xF1C0, 0xE07F), "IiFt", m68040up }, 3245 3246 {"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 3247 {"fdsqrtb", 4, two(0xF000, 0x5845), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3248 {"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3249 {"fdsqrtd", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", cfloat }, 3250 {"fdsqrtd", 4, two(0xF000, 0x5445), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 3251 {"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 3252 {"fdsqrtl", 4, two(0xF000, 0x4045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3253 {"fdsqrtp", 4, two(0xF000, 0x4C45), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 3254 {"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 3255 {"fdsqrts", 4, two(0xF000, 0x4445), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3256 {"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 3257 {"fdsqrtw", 4, two(0xF000, 0x5045), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3258 {"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 3259 {"fdsqrtx", 4, two(0xF000, 0x4845), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 3260 {"fdsqrtx", 4, two(0xF000, 0x0045), two(0xF1C0, 0xE07F), "IiFt", m68040up }, 3261 3262 {"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3263 {"fsubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3264 {"fsubd", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3265 {"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3266 {"fsubd", 4, two(0xF000, 0x5428), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 3267 {"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3268 {"fsubl", 4, two(0xF000, 0x4028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3269 {"fsubp", 4, two(0xF000, 0x4C28), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3270 {"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3271 {"fsubs", 4, two(0xF000, 0x4428), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3272 {"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3273 {"fsubw", 4, two(0xF000, 0x5028), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3274 {"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3275 {"fsubx", 4, two(0xF000, 0x4828), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3276 {"fsubx", 4, two(0xF000, 0x0028), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 3277 3278 {"fssubb", 4, two(0xF000, 0x5828), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3279 {"fssubb", 4, two(0xF000, 0x5868), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 3280 {"fssubd", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3281 {"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 3282 {"fssubd", 4, two(0xF000, 0x5468), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 3283 {"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 3284 {"fssubl", 4, two(0xF000, 0x4068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3285 {"fssubp", 4, two(0xF000, 0x4C68), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 3286 {"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 3287 {"fssubs", 4, two(0xF000, 0x4468), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3288 {"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 3289 {"fssubw", 4, two(0xF000, 0x5068), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3290 {"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 3291 {"fssubx", 4, two(0xF000, 0x4868), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 3292 {"fssubx", 4, two(0xF000, 0x0068), two(0xF1C0, 0xE07F), "IiFt", m68040up }, 3293 3294 {"fdsubb", 4, two(0xF000, 0x586A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3295 {"fdsubb", 4, two(0xF000, 0x586c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, 3296 {"fdsubd", 4, two(0xF000, 0x006A), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, 3297 {"fdsubd", 4, two(0xF000, 0x546A), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, 3298 {"fdsubd", 4, two(0xF000, 0x546c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, 3299 {"fdsubl", 4, two(0xF000, 0x406A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3300 {"fdsubl", 4, two(0xF000, 0x406c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, 3301 {"fdsubp", 4, two(0xF000, 0x4C6c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, 3302 {"fdsubs", 4, two(0xF000, 0x446A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3303 {"fdsubs", 4, two(0xF000, 0x446c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, 3304 {"fdsubw", 4, two(0xF000, 0x506A), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, 3305 {"fdsubw", 4, two(0xF000, 0x506c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, 3306 {"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, 3307 {"fdsubx", 4, two(0xF000, 0x486c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, 3308 {"fdsubx", 4, two(0xF000, 0x006c), two(0xF1C0, 0xE07F), "IiFt", m68040up }, 3309 3310 {"ftanb", 4, two(0xF000, 0x580F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3311 {"ftand", 4, two(0xF000, 0x540F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3312 {"ftanl", 4, two(0xF000, 0x400F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3313 {"ftanp", 4, two(0xF000, 0x4C0F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3314 {"ftans", 4, two(0xF000, 0x440F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3315 {"ftanw", 4, two(0xF000, 0x500F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3316 {"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3317 {"ftanx", 4, two(0xF000, 0x480F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3318 {"ftanx", 4, two(0xF000, 0x000F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 3319 3320 {"ftanhb", 4, two(0xF000, 0x5809), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3321 {"ftanhd", 4, two(0xF000, 0x5409), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3322 {"ftanhl", 4, two(0xF000, 0x4009), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3323 {"ftanhp", 4, two(0xF000, 0x4C09), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3324 {"ftanhs", 4, two(0xF000, 0x4409), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3325 {"ftanhw", 4, two(0xF000, 0x5009), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3326 {"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3327 {"ftanhx", 4, two(0xF000, 0x4809), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3328 {"ftanhx", 4, two(0xF000, 0x0009), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 3329 3330 {"ftentoxb", 4, two(0xF000, 0x5812), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3331 {"ftentoxd", 4, two(0xF000, 0x5412), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3332 {"ftentoxl", 4, two(0xF000, 0x4012), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3333 {"ftentoxp", 4, two(0xF000, 0x4C12), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3334 {"ftentoxs", 4, two(0xF000, 0x4412), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3335 {"ftentoxw", 4, two(0xF000, 0x5012), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3336 {"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3337 {"ftentoxx", 4, two(0xF000, 0x4812), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3338 {"ftentoxx", 4, two(0xF000, 0x0012), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 3339 3340 {"ftrapeq", 4, two(0xF07C, 0x0001), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3341 {"ftrapf", 4, two(0xF07C, 0x0000), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3342 {"ftrapge", 4, two(0xF07C, 0x0013), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3343 {"ftrapgl", 4, two(0xF07C, 0x0016), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3344 {"ftrapgle", 4, two(0xF07C, 0x0017), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3345 {"ftrapgt", 4, two(0xF07C, 0x0012), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3346 {"ftraple", 4, two(0xF07C, 0x0015), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3347 {"ftraplt", 4, two(0xF07C, 0x0014), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3348 {"ftrapne", 4, two(0xF07C, 0x000E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3349 {"ftrapnge", 4, two(0xF07C, 0x001C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3350 {"ftrapngl", 4, two(0xF07C, 0x0019), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3351 {"ftrapngle", 4,two(0xF07C, 0x0018), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3352 {"ftrapngt", 4, two(0xF07C, 0x001D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3353 {"ftrapnle", 4, two(0xF07C, 0x001A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3354 {"ftrapnlt", 4, two(0xF07C, 0x001B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3355 {"ftrapoge", 4, two(0xF07C, 0x0003), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3356 {"ftrapogl", 4, two(0xF07C, 0x0006), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3357 {"ftrapogt", 4, two(0xF07C, 0x0002), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3358 {"ftrapole", 4, two(0xF07C, 0x0005), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3359 {"ftrapolt", 4, two(0xF07C, 0x0004), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3360 {"ftrapor", 4, two(0xF07C, 0x0007), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3361 {"ftrapseq", 4, two(0xF07C, 0x0011), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3362 {"ftrapsf", 4, two(0xF07C, 0x0010), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3363 {"ftrapsne", 4, two(0xF07C, 0x001E), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3364 {"ftrapst", 4, two(0xF07C, 0x001F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3365 {"ftrapt", 4, two(0xF07C, 0x000F), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3366 {"ftrapueq", 4, two(0xF07C, 0x0009), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3367 {"ftrapuge", 4, two(0xF07C, 0x000B), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3368 {"ftrapugt", 4, two(0xF07C, 0x000A), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3369 {"ftrapule", 4, two(0xF07C, 0x000D), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3370 {"ftrapult", 4, two(0xF07C, 0x000C), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3371 {"ftrapun", 4, two(0xF07C, 0x0008), two(0xF1FF, 0xFFFF), "Ii", mfloat }, 3372 3373 {"ftrapeqw", 4, two(0xF07A, 0x0001), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3374 {"ftrapfw", 4, two(0xF07A, 0x0000), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3375 {"ftrapgew", 4, two(0xF07A, 0x0013), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3376 {"ftrapglw", 4, two(0xF07A, 0x0016), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3377 {"ftrapglew", 4,two(0xF07A, 0x0017), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3378 {"ftrapgtw", 4, two(0xF07A, 0x0012), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3379 {"ftraplew", 4, two(0xF07A, 0x0015), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3380 {"ftrapltw", 4, two(0xF07A, 0x0014), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3381 {"ftrapnew", 4, two(0xF07A, 0x000E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3382 {"ftrapngew", 4,two(0xF07A, 0x001C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3383 {"ftrapnglw", 4,two(0xF07A, 0x0019), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3384 {"ftrapnglew", 4,two(0xF07A, 0x0018), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3385 {"ftrapngtw", 4,two(0xF07A, 0x001D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3386 {"ftrapnlew", 4,two(0xF07A, 0x001A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3387 {"ftrapnltw", 4,two(0xF07A, 0x001B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3388 {"ftrapogew", 4,two(0xF07A, 0x0003), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3389 {"ftrapoglw", 4,two(0xF07A, 0x0006), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3390 {"ftrapogtw", 4,two(0xF07A, 0x0002), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3391 {"ftrapolew", 4,two(0xF07A, 0x0005), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3392 {"ftrapoltw", 4,two(0xF07A, 0x0004), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3393 {"ftraporw", 4, two(0xF07A, 0x0007), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3394 {"ftrapseqw", 4,two(0xF07A, 0x0011), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3395 {"ftrapsfw", 4, two(0xF07A, 0x0010), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3396 {"ftrapsnew", 4,two(0xF07A, 0x001E), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3397 {"ftrapstw", 4, two(0xF07A, 0x001F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3398 {"ftraptw", 4, two(0xF07A, 0x000F), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3399 {"ftrapueqw", 4,two(0xF07A, 0x0009), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3400 {"ftrapugew", 4,two(0xF07A, 0x000B), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3401 {"ftrapugtw", 4,two(0xF07A, 0x000A), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3402 {"ftrapulew", 4,two(0xF07A, 0x000D), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3403 {"ftrapultw", 4,two(0xF07A, 0x000C), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3404 {"ftrapunw", 4, two(0xF07A, 0x0008), two(0xF1FF, 0xFFFF), "Ii^w", mfloat }, 3405 3406 {"ftrapeql", 4, two(0xF07B, 0x0001), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3407 {"ftrapfl", 4, two(0xF07B, 0x0000), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3408 {"ftrapgel", 4, two(0xF07B, 0x0013), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3409 {"ftrapgll", 4, two(0xF07B, 0x0016), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3410 {"ftrapglel", 4,two(0xF07B, 0x0017), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3411 {"ftrapgtl", 4, two(0xF07B, 0x0012), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3412 {"ftraplel", 4, two(0xF07B, 0x0015), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3413 {"ftrapltl", 4, two(0xF07B, 0x0014), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3414 {"ftrapnel", 4, two(0xF07B, 0x000E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3415 {"ftrapngel", 4,two(0xF07B, 0x001C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3416 {"ftrapngll", 4,two(0xF07B, 0x0019), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3417 {"ftrapnglel", 4,two(0xF07B, 0x0018), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3418 {"ftrapngtl", 4,two(0xF07B, 0x001D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3419 {"ftrapnlel", 4,two(0xF07B, 0x001A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3420 {"ftrapnltl", 4,two(0xF07B, 0x001B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3421 {"ftrapogel", 4,two(0xF07B, 0x0003), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3422 {"ftrapogll", 4,two(0xF07B, 0x0006), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3423 {"ftrapogtl", 4,two(0xF07B, 0x0002), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3424 {"ftrapolel", 4,two(0xF07B, 0x0005), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3425 {"ftrapoltl", 4,two(0xF07B, 0x0004), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3426 {"ftraporl", 4, two(0xF07B, 0x0007), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3427 {"ftrapseql", 4,two(0xF07B, 0x0011), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3428 {"ftrapsfl", 4, two(0xF07B, 0x0010), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3429 {"ftrapsnel", 4,two(0xF07B, 0x001E), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3430 {"ftrapstl", 4, two(0xF07B, 0x001F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3431 {"ftraptl", 4, two(0xF07B, 0x000F), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3432 {"ftrapueql", 4,two(0xF07B, 0x0009), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3433 {"ftrapugel", 4,two(0xF07B, 0x000B), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3434 {"ftrapugtl", 4,two(0xF07B, 0x000A), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3435 {"ftrapulel", 4,two(0xF07B, 0x000D), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3436 {"ftrapultl", 4,two(0xF07B, 0x000C), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3437 {"ftrapunl", 4, two(0xF07B, 0x0008), two(0xF1FF, 0xFFFF), "Ii^l", mfloat }, 3438 3439 {"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Ii;b", mfloat }, 3440 {"ftstb", 4, two(0xF000, 0x583A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, 3441 {"ftstd", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", cfloat }, 3442 {"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Ii;F", mfloat }, 3443 {"ftstd", 4, two(0xF000, 0x543A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, 3444 {"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Ii;l", mfloat }, 3445 {"ftstl", 4, two(0xF000, 0x403A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, 3446 {"ftstp", 4, two(0xF000, 0x4C3A), two(0xF1C0, 0xFC7F), "Ii;p", mfloat }, 3447 {"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Ii;f", mfloat }, 3448 {"ftsts", 4, two(0xF000, 0x443A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, 3449 {"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Ii;w", mfloat }, 3450 {"ftstw", 4, two(0xF000, 0x503A), two(0xF1C0, 0xFC7F), "Iibs", cfloat }, 3451 {"ftstx", 4, two(0xF000, 0x003A), two(0xF1C0, 0xE07F), "IiF8", mfloat }, 3452 {"ftstx", 4, two(0xF000, 0x483A), two(0xF1C0, 0xFC7F), "Ii;x", mfloat }, 3453 3454 {"ftwotoxb", 4, two(0xF000, 0x5811), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, 3455 {"ftwotoxd", 4, two(0xF000, 0x5411), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, 3456 {"ftwotoxl", 4, two(0xF000, 0x4011), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, 3457 {"ftwotoxp", 4, two(0xF000, 0x4C11), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, 3458 {"ftwotoxs", 4, two(0xF000, 0x4411), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, 3459 {"ftwotoxw", 4, two(0xF000, 0x5011), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, 3460 {"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, 3461 {"ftwotoxx", 4, two(0xF000, 0x4811), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, 3462 {"ftwotoxx", 4, two(0xF000, 0x0011), two(0xF1C0, 0xE07F), "IiFt", mfloat }, 3463 3464 {"halt", 2, one(0045310), one(0177777), "", m68060 | mcfisa_a }, 3465 3466 {"illegal", 2, one(0045374), one(0177777), "", m68000up | mcfisa_a }, 3467 {"intouch", 2, one(0xf428), one(0xfff8), "As", mcfisa_b }, 3468 3469 {"jmp", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, 3470 3471 {"jra", 2, one(0060000), one(0177400), "Bg", m68000up | mcfisa_a }, 3472 {"jra", 2, one(0047300), one(0177700), "!s", m68000up | mcfisa_a }, 3473 3474 {"jsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, 3475 3476 {"jbsr", 2, one(0060400), one(0177400), "Bg", m68000up | mcfisa_a }, 3477 {"jbsr", 2, one(0047200), one(0177700), "!s", m68000up | mcfisa_a }, 3478 3479 {"lea", 2, one(0040700), one(0170700), "!sAd", m68000up | mcfisa_a }, 3480 3481 {"lpstop", 6, two(0174000,0000700),two(0177777,0177777),"#w", cpu32|m68060 }, 3482 3483 {"linkw", 4, one(0047120), one(0177770), "As#w", m68000up | mcfisa_a }, 3484 {"linkl", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 }, 3485 {"link", 4, one(0047120), one(0177770), "As#W", m68000up | mcfisa_a }, 3486 {"link", 6, one(0044010), one(0177770), "As#l", m68020up | cpu32 }, 3487 3488 {"lslb", 2, one(0160410), one(0170770), "QdDs", m68000up }, 3489 {"lslb", 2, one(0160450), one(0170770), "DdDs", m68000up }, 3490 {"lslw", 2, one(0160510), one(0170770), "QdDs", m68000up }, 3491 {"lslw", 2, one(0160550), one(0170770), "DdDs", m68000up }, 3492 {"lslw", 2, one(0161700), one(0177700), "~s", m68000up }, 3493 {"lsll", 2, one(0160610), one(0170770), "QdDs", m68000up | mcfisa_a }, 3494 {"lsll", 2, one(0160650), one(0170770), "DdDs", m68000up | mcfisa_a }, 3495 3496 {"lsrb", 2, one(0160010), one(0170770), "QdDs", m68000up }, 3497 {"lsrb", 2, one(0160050), one(0170770), "DdDs", m68000up }, 3498 {"lsrw", 2, one(0160110), one(0170770), "QdDs", m68000up }, 3499 {"lsrw", 2, one(0160150), one(0170770), "DdDs", m68000up }, 3500 {"lsrw", 2, one(0161300), one(0177700), "~s", m68000up }, 3501 {"lsrl", 2, one(0160210), one(0170770), "QdDs", m68000up | mcfisa_a }, 3502 {"lsrl", 2, one(0160250), one(0170770), "DdDs", m68000up | mcfisa_a }, 3503 3504 {"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac }, 3505 {"macw", 4, two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac }, 3506 {"macw", 4, two(0xa080, 0x0000), two(0xf180, 0x0f10), "uNuo4/Rn", mcfmac }, 3507 {"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0900), "uMumiI", mcfmac }, 3508 {"macw", 4, two(0xa000, 0x0200), two(0xf1b0, 0x0900), "uMumMh", mcfmac }, 3509 {"macw", 4, two(0xa000, 0x0000), two(0xf1b0, 0x0f00), "uMum", mcfmac }, 3510 3511 {"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0900), "uNuoiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */ 3512 {"macw", 4, two(0xa000, 0x0200), two(0xf100, 0x0900), "uNuoMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */ 3513 {"macw", 4, two(0xa000, 0x0000), two(0xf100, 0x0f00), "uNuo4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */ 3514 {"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */ 3515 {"macw", 4, two(0xa000, 0x0200), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */ 3516 {"macw", 4, two(0xa000, 0x0000), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */ 3517 3518 {"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac }, 3519 {"macl", 4, two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac }, 3520 {"macl", 4, two(0xa080, 0x0800), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac }, 3521 {"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac }, 3522 {"macl", 4, two(0xa000, 0x0a00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac }, 3523 {"macl", 4, two(0xa000, 0x0800), two(0xf1b0, 0x0800), "RMRm", mcfmac }, 3524 3525 {"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac }, 3526 {"macl", 4, two(0xa000, 0x0a00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac }, 3527 {"macl", 4, two(0xa000, 0x0800), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac }, 3528 {"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0900), "RMRmiIeH", mcfemac }, 3529 {"macl", 4, two(0xa000, 0x0a00), two(0xf130, 0x0900), "RMRmMheH", mcfemac }, 3530 {"macl", 4, two(0xa000, 0x0800), two(0xf130, 0x0f00), "RMRmeH", mcfemac }, 3531 3532 /* NOTE: The mcf5200 family programmer's reference manual does not 3533 indicate the byte form of the movea instruction is invalid (as it 3534 is on 68000 family cpus). However, experiments on the 5202 yield 3535 unexpected results. The value is copied, but it is not sign extended 3536 (as is done with movea.w) and the top three bytes in the address 3537 register are not disturbed. I don't know if this is the intended 3538 behavior --- it could be a hole in instruction decoding (Motorola 3539 decided not to trap all invalid instructions for performance reasons) 3540 --- but I suspect that it is not. 3541 3542 I reported this to Motorola ISD Technical Communications Support, 3543 which replied that other coldfire assemblers reject movea.b. For 3544 this reason I've decided to not allow moveab. 3545 3546 jtc@cygnus.com - 97/01/24. */ 3547 3548 {"moveal", 2, one(0020100), one(0170700), "*lAd", m68000up | mcfisa_a }, 3549 {"moveaw", 2, one(0030100), one(0170700), "*wAd", m68000up | mcfisa_a }, 3550 3551 {"movclrl", 2, one(0xA1C0), one(0xf9f0), "eFRs", mcfemac }, 3552 3553 {"movec", 4, one(0047173), one(0177777), "R1Jj", m68010up | mcfisa_a }, 3554 {"movec", 4, one(0047173), one(0177777), "R1#j", m68010up | mcfisa_a }, 3555 {"movec", 4, one(0047172), one(0177777), "JjR1", m68010up }, 3556 {"movec", 4, one(0047172), one(0177777), "#jR1", m68010up }, 3557 3558 {"movemw", 4, one(0044200), one(0177700), "Lw&s", m68000up }, 3559 {"movemw", 4, one(0044240), one(0177770), "lw-s", m68000up }, 3560 {"movemw", 4, one(0044200), one(0177700), "#w>s", m68000up }, 3561 {"movemw", 4, one(0046200), one(0177700), "<sLw", m68000up }, 3562 {"movemw", 4, one(0046200), one(0177700), "<s#w", m68000up }, 3563 {"moveml", 4, one(0044300), one(0177700), "Lw&s", m68000up }, 3564 {"moveml", 4, one(0044340), one(0177770), "lw-s", m68000up }, 3565 {"moveml", 4, one(0044300), one(0177700), "#w>s", m68000up }, 3566 {"moveml", 4, one(0046300), one(0177700), "<sLw", m68000up }, 3567 {"moveml", 4, one(0046300), one(0177700), "<s#w", m68000up }, 3568 /* FIXME: need specifier for mode 2 and 5 to simplify below insn patterns. */ 3569 {"moveml", 4, one(0044320), one(0177770), "Lwas", mcfisa_a }, 3570 {"moveml", 4, one(0044320), one(0177770), "#was", mcfisa_a }, 3571 {"moveml", 4, one(0044350), one(0177770), "Lwds", mcfisa_a }, 3572 {"moveml", 4, one(0044350), one(0177770), "#wds", mcfisa_a }, 3573 {"moveml", 4, one(0046320), one(0177770), "asLw", mcfisa_a }, 3574 {"moveml", 4, one(0046320), one(0177770), "as#w", mcfisa_a }, 3575 {"moveml", 4, one(0046350), one(0177770), "dsLw", mcfisa_a }, 3576 {"moveml", 4, one(0046350), one(0177770), "ds#w", mcfisa_a }, 3577 3578 {"movepw", 2, one(0000410), one(0170770), "dsDd", m68000up }, 3579 {"movepw", 2, one(0000610), one(0170770), "Ddds", m68000up }, 3580 {"movepl", 2, one(0000510), one(0170770), "dsDd", m68000up }, 3581 {"movepl", 2, one(0000710), one(0170770), "Ddds", m68000up }, 3582 3583 {"moveq", 2, one(0070000), one(0170400), "MsDd", m68000up | mcfisa_a }, 3584 {"moveq", 2, one(0070000), one(0170400), "#BDd", m68000up | mcfisa_a }, 3585 3586 /* The move opcode can generate the movea and moveq instructions. */ 3587 {"moveb", 2, one(0010000), one(0170000), ";b$d", m68000up }, 3588 {"moveb", 2, one(0010000), one(0170070), "Ds$d", mcfisa_a }, 3589 {"moveb", 2, one(0010020), one(0170070), "as$d", mcfisa_a }, 3590 {"moveb", 2, one(0010030), one(0170070), "+s$d", mcfisa_a }, 3591 {"moveb", 2, one(0010040), one(0170070), "-s$d", mcfisa_a }, 3592 {"moveb", 2, one(0010000), one(0170000), "nsqd", mcfisa_a }, 3593 {"moveb", 2, one(0010000), one(0170700), "obDd", mcfisa_a }, 3594 {"moveb", 2, one(0010200), one(0170700), "obad", mcfisa_a }, 3595 {"moveb", 2, one(0010300), one(0170700), "ob+d", mcfisa_a }, 3596 {"moveb", 2, one(0010400), one(0170700), "ob-d", mcfisa_a }, 3597 {"moveb", 2, one(0010000), one(0170000), "obnd", mcfisa_b }, 3598 3599 {"movew", 2, one(0030000), one(0170000), "*w%d", m68000up }, 3600 {"movew", 2, one(0030000), one(0170000), "ms%d", mcfisa_a }, 3601 {"movew", 2, one(0030000), one(0170000), "nspd", mcfisa_a }, 3602 {"movew", 2, one(0030000), one(0170000), "owmd", mcfisa_a }, 3603 {"movew", 2, one(0030000), one(0170000), "ownd", mcfisa_b }, 3604 {"movew", 2, one(0040300), one(0177700), "Ss$s", m68000up }, 3605 {"movew", 2, one(0040300), one(0177770), "SsDs", mcfisa_a }, 3606 {"movew", 2, one(0041300), one(0177700), "Cs$s", m68010up }, 3607 {"movew", 2, one(0041300), one(0177770), "CsDs", mcfisa_a }, 3608 {"movew", 2, one(0042300), one(0177700), ";wCd", m68000up }, 3609 {"movew", 2, one(0042300), one(0177700), "DsCd", mcfisa_a }, 3610 {"movew", 4, one(0042374), one(0177777), "#wCd", mcfisa_a }, 3611 {"movew", 2, one(0043300), one(0177700), ";wSd", m68000up }, 3612 {"movew", 2, one(0043300), one(0177700), "DsSd", mcfisa_a }, 3613 {"movew", 4, one(0043374), one(0177777), "#wSd", mcfisa_a }, 3614 3615 {"movel", 2, one(0070000), one(0170400), "MsDd", m68000up | mcfisa_a }, 3616 {"movel", 2, one(0020000), one(0170000), "*l%d", m68000up }, 3617 {"movel", 2, one(0020000), one(0170000), "ms%d", mcfisa_a }, 3618 {"movel", 2, one(0020000), one(0170000), "nspd", mcfisa_a }, 3619 {"movel", 2, one(0020000), one(0170000), "olmd", mcfisa_a }, 3620 {"movel", 2, one(0020000), one(0170000), "olnd", mcfisa_b }, 3621 {"movel", 2, one(0047140), one(0177770), "AsUd", m68000up | mcfusp }, 3622 {"movel", 2, one(0047150), one(0177770), "UdAs", m68000up | mcfusp }, 3623 {"movel", 2, one(0120600), one(0177760), "EsRs", mcfmac }, 3624 {"movel", 2, one(0120400), one(0177760), "RsEs", mcfmac }, 3625 {"movel", 6, one(0120474), one(0177777), "#lEs", mcfmac }, 3626 {"movel", 2, one(0124600), one(0177760), "GsRs", mcfmac }, 3627 {"movel", 2, one(0124400), one(0177760), "RsGs", mcfmac }, 3628 {"movel", 6, one(0124474), one(0177777), "#lGs", mcfmac }, 3629 {"movel", 2, one(0126600), one(0177760), "HsRs", mcfmac }, 3630 {"movel", 2, one(0126400), one(0177760), "RsHs", mcfmac }, 3631 {"movel", 6, one(0126474), one(0177777), "#lHs", mcfmac }, 3632 {"movel", 2, one(0124700), one(0177777), "GsCs", mcfmac }, 3633 3634 {"movel", 2, one(0xa180), one(0xf9f0), "eFRs", mcfemac }, /* ACCx,Rx. */ 3635 {"movel", 2, one(0xab80), one(0xfbf0), "g]Rs", mcfemac }, /* ACCEXTx,Rx. */ 3636 {"movel", 2, one(0xa980), one(0xfff0), "G-Rs", mcfemac }, /* macsr,Rx. */ 3637 {"movel", 2, one(0xad80), one(0xfff0), "H-Rs", mcfemac }, /* mask,Rx. */ 3638 {"movel", 2, one(0xa110), one(0xf9fc), "efeF", mcfemac }, /* ACCy,ACCx. */ 3639 {"movel", 2, one(0xa9c0), one(0xffff), "G-C-", mcfemac }, /* macsr,ccr. */ 3640 {"movel", 2, one(0xa100), one(0xf9f0), "RseF", mcfemac }, /* Rx,ACCx. */ 3641 {"movel", 6, one(0xa13c), one(0xf9ff), "#leF", mcfemac }, /* #,ACCx. */ 3642 {"movel", 2, one(0xab00), one(0xfbc0), "Rsg]", mcfemac }, /* Rx,ACCEXTx. */ 3643 {"movel", 6, one(0xab3c), one(0xfbff), "#lg]", mcfemac }, /* #,ACCEXTx. */ 3644 {"movel", 2, one(0xa900), one(0xffc0), "RsG-", mcfemac }, /* Rx,macsr. */ 3645 {"movel", 6, one(0xa93c), one(0xffff), "#lG-", mcfemac }, /* #,macsr. */ 3646 {"movel", 2, one(0xad00), one(0xffc0), "RsH-", mcfemac }, /* Rx,mask. */ 3647 {"movel", 6, one(0xad3c), one(0xffff), "#lH-", mcfemac }, /* #,mask. */ 3648 3649 {"move", 2, one(0030000), one(0170000), "*w%d", m68000up }, 3650 {"move", 2, one(0030000), one(0170000), "ms%d", mcfisa_a }, 3651 {"move", 2, one(0030000), one(0170000), "nspd", mcfisa_a }, 3652 {"move", 2, one(0030000), one(0170000), "owmd", mcfisa_a }, 3653 {"move", 2, one(0030000), one(0170000), "ownd", mcfisa_b }, 3654 {"move", 2, one(0040300), one(0177700), "Ss$s", m68000up }, 3655 {"move", 2, one(0040300), one(0177770), "SsDs", mcfisa_a }, 3656 {"move", 2, one(0041300), one(0177700), "Cs$s", m68010up }, 3657 {"move", 2, one(0041300), one(0177770), "CsDs", mcfisa_a }, 3658 {"move", 2, one(0042300), one(0177700), ";wCd", m68000up }, 3659 {"move", 2, one(0042300), one(0177700), "DsCd", mcfisa_a }, 3660 {"move", 4, one(0042374), one(0177777), "#wCd", mcfisa_a }, 3661 {"move", 2, one(0043300), one(0177700), ";wSd", m68000up }, 3662 {"move", 2, one(0043300), one(0177700), "DsSd", mcfisa_a }, 3663 {"move", 4, one(0043374), one(0177777), "#wSd", mcfisa_a }, 3664 3665 {"move", 2, one(0047140), one(0177770), "AsUd", m68000up }, 3666 {"move", 2, one(0047150), one(0177770), "UdAs", m68000up }, 3667 3668 {"mov3ql", 2, one(0120500), one(0170700), "xd%s", mcfisa_b }, 3669 {"mvsb", 2, one(0070400), one(0170700), "*bDd", mcfisa_b }, 3670 {"mvsw", 2, one(0070500), one(0170700), "*wDd", mcfisa_b }, 3671 {"mvzb", 2, one(0070600), one(0170700), "*bDd", mcfisa_b }, 3672 {"mvzw", 2, one(0070700), one(0170700), "*wDd", mcfisa_b }, 3673 3674 {"movesb", 4, two(0007000, 0), two(0177700, 07777), "~sR1", m68010up }, 3675 {"movesb", 4, two(0007000, 04000), two(0177700, 07777), "R1~s", m68010up }, 3676 {"movesw", 4, two(0007100, 0), two(0177700, 07777), "~sR1", m68010up }, 3677 {"movesw", 4, two(0007100, 04000), two(0177700, 07777), "R1~s", m68010up }, 3678 {"movesl", 4, two(0007200, 0), two(0177700, 07777), "~sR1", m68010up }, 3679 {"movesl", 4, two(0007200, 04000), two(0177700, 07777), "R1~s", m68010up }, 3680 3681 {"move16", 4, two(0xf620, 0x8000), two(0xfff8, 0x8fff), "+s+1", m68040up }, 3682 {"move16", 2, one(0xf600), one(0xfff8), "+s_L", m68040up }, 3683 {"move16", 2, one(0xf608), one(0xfff8), "_L+s", m68040up }, 3684 {"move16", 2, one(0xf610), one(0xfff8), "as_L", m68040up }, 3685 {"move16", 2, one(0xf618), one(0xfff8), "_Las", m68040up }, 3686 3687 {"msacw", 4, two(0xa080, 0x0100), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac }, 3688 {"msacw", 4, two(0xa080, 0x0300), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac }, 3689 {"msacw", 4, two(0xa080, 0x0100), two(0xf180, 0x0f10), "uNuo4/Rn", mcfmac }, 3690 {"msacw", 4, two(0xa000, 0x0100), two(0xf1b0, 0x0900), "uMumiI", mcfmac }, 3691 {"msacw", 4, two(0xa000, 0x0300), two(0xf1b0, 0x0900), "uMumMh", mcfmac }, 3692 {"msacw", 4, two(0xa000, 0x0100), two(0xf1b0, 0x0f00), "uMum", mcfmac }, 3693 3694 {"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0900), "uMumiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */ 3695 {"msacw", 4, two(0xa000, 0x0300), two(0xf100, 0x0900), "uMumMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */ 3696 {"msacw", 4, two(0xa000, 0x0100), two(0xf100, 0x0f00), "uMum4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */ 3697 {"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */ 3698 {"msacw", 4, two(0xa000, 0x0300), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */ 3699 {"msacw", 4, two(0xa000, 0x0100), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */ 3700 3701 {"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac }, 3702 {"msacl", 4, two(0xa080, 0x0b00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac }, 3703 {"msacl", 4, two(0xa080, 0x0900), two(0xf180, 0x0f10), "RNRo4/Rn", mcfmac }, 3704 {"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac }, 3705 {"msacl", 4, two(0xa000, 0x0b00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac }, 3706 {"msacl", 4, two(0xa000, 0x0900), two(0xf1b0, 0x0800), "RMRm", mcfmac }, 3707 3708 {"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac }, 3709 {"msacl", 4, two(0xa000, 0x0b00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac }, 3710 {"msacl", 4, two(0xa000, 0x0900), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac }, 3711 {"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0900), "RMRmiIeH", mcfemac }, 3712 {"msacl", 4, two(0xa000, 0x0b00), two(0xf130, 0x0900), "RMRmMheH", mcfemac }, 3713 {"msacl", 4, two(0xa000, 0x0900), two(0xf130, 0x0f00), "RMRmeH", mcfemac }, 3714 3715 {"mulsw", 2, one(0140700), one(0170700), ";wDd", m68000up|mcfisa_a }, 3716 {"mulsl", 4, two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 }, 3717 {"mulsl", 4, two(0046000,004000), two(0177700,0107770), "qsD1", mcfisa_a }, 3718 {"mulsl", 4, two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, 3719 3720 {"muluw", 2, one(0140300), one(0170700), ";wDd", m68000up|mcfisa_a }, 3721 {"mulul", 4, two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32 }, 3722 {"mulul", 4, two(0046000,000000), two(0177700,0107770), "qsD1", mcfisa_a }, 3723 {"mulul", 4, two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 }, 3724 3725 {"nbcd", 2, one(0044000), one(0177700), "$s", m68000up }, 3726 3727 {"negb", 2, one(0042000), one(0177700), "$s", m68000up }, 3728 {"negw", 2, one(0042100), one(0177700), "$s", m68000up }, 3729 {"negl", 2, one(0042200), one(0177700), "$s", m68000up }, 3730 {"negl", 2, one(0042200), one(0177700), "Ds", mcfisa_a}, 3731 3732 {"negxb", 2, one(0040000), one(0177700), "$s", m68000up }, 3733 {"negxw", 2, one(0040100), one(0177700), "$s", m68000up }, 3734 {"negxl", 2, one(0040200), one(0177700), "$s", m68000up }, 3735 {"negxl", 2, one(0040200), one(0177700), "Ds", mcfisa_a}, 3736 3737 {"nop", 2, one(0047161), one(0177777), "", m68000up | mcfisa_a}, 3738 3739 {"notb", 2, one(0043000), one(0177700), "$s", m68000up }, 3740 {"notw", 2, one(0043100), one(0177700), "$s", m68000up }, 3741 {"notl", 2, one(0043200), one(0177700), "$s", m68000up }, 3742 {"notl", 2, one(0043200), one(0177700), "Ds", mcfisa_a}, 3743 3744 {"orib", 4, one(0000000), one(0177700), "#b$s", m68000up }, 3745 {"orib", 4, one(0000074), one(0177777), "#bCs", m68000up }, 3746 {"oriw", 4, one(0000100), one(0177700), "#w$s", m68000up }, 3747 {"oriw", 4, one(0000174), one(0177777), "#wSs", m68000up }, 3748 {"oril", 6, one(0000200), one(0177700), "#l$s", m68000up }, 3749 {"oril", 6, one(0000200), one(0177700), "#lDs", mcfisa_a }, 3750 {"ori", 4, one(0000074), one(0177777), "#bCs", m68000up }, 3751 {"ori", 4, one(0000100), one(0177700), "#w$s", m68000up }, 3752 {"ori", 4, one(0000174), one(0177777), "#wSs", m68000up }, 3753 3754 /* The or opcode can generate the ori instruction. */ 3755 {"orb", 4, one(0000000), one(0177700), "#b$s", m68000up }, 3756 {"orb", 4, one(0000074), one(0177777), "#bCs", m68000up }, 3757 {"orb", 2, one(0100000), one(0170700), ";bDd", m68000up }, 3758 {"orb", 2, one(0100400), one(0170700), "Dd~s", m68000up }, 3759 {"orw", 4, one(0000100), one(0177700), "#w$s", m68000up }, 3760 {"orw", 4, one(0000174), one(0177777), "#wSs", m68000up }, 3761 {"orw", 2, one(0100100), one(0170700), ";wDd", m68000up }, 3762 {"orw", 2, one(0100500), one(0170700), "Dd~s", m68000up }, 3763 {"orl", 6, one(0000200), one(0177700), "#l$s", m68000up }, 3764 {"orl", 6, one(0000200), one(0177700), "#lDs", mcfisa_a }, 3765 {"orl", 2, one(0100200), one(0170700), ";lDd", m68000up | mcfisa_a }, 3766 {"orl", 2, one(0100600), one(0170700), "Dd~s", m68000up | mcfisa_a }, 3767 {"or", 4, one(0000074), one(0177777), "#bCs", m68000up }, 3768 {"or", 4, one(0000100), one(0177700), "#w$s", m68000up }, 3769 {"or", 4, one(0000174), one(0177777), "#wSs", m68000up }, 3770 {"or", 2, one(0100100), one(0170700), ";wDd", m68000up }, 3771 {"or", 2, one(0100500), one(0170700), "Dd~s", m68000up }, 3772 3773 {"pack", 4, one(0100500), one(0170770), "DsDd#w", m68020up }, 3774 {"pack", 4, one(0100510), one(0170770), "-s-d#w", m68020up }, 3775 3776 {"pbac", 2, one(0xf087), one(0xffbf), "Bc", m68851 }, 3777 {"pbacw", 2, one(0xf087), one(0xffff), "BW", m68851 }, 3778 {"pbas", 2, one(0xf086), one(0xffbf), "Bc", m68851 }, 3779 {"pbasw", 2, one(0xf086), one(0xffff), "BW", m68851 }, 3780 {"pbbc", 2, one(0xf081), one(0xffbf), "Bc", m68851 }, 3781 {"pbbcw", 2, one(0xf081), one(0xffff), "BW", m68851 }, 3782 {"pbbs", 2, one(0xf080), one(0xffbf), "Bc", m68851 }, 3783 {"pbbsw", 2, one(0xf080), one(0xffff), "BW", m68851 }, 3784 {"pbcc", 2, one(0xf08f), one(0xffbf), "Bc", m68851 }, 3785 {"pbccw", 2, one(0xf08f), one(0xffff), "BW", m68851 }, 3786 {"pbcs", 2, one(0xf08e), one(0xffbf), "Bc", m68851 }, 3787 {"pbcsw", 2, one(0xf08e), one(0xffff), "BW", m68851 }, 3788 {"pbgc", 2, one(0xf08d), one(0xffbf), "Bc", m68851 }, 3789 {"pbgcw", 2, one(0xf08d), one(0xffff), "BW", m68851 }, 3790 {"pbgs", 2, one(0xf08c), one(0xffbf), "Bc", m68851 }, 3791 {"pbgsw", 2, one(0xf08c), one(0xffff), "BW", m68851 }, 3792 {"pbic", 2, one(0xf08b), one(0xffbf), "Bc", m68851 }, 3793 {"pbicw", 2, one(0xf08b), one(0xffff), "BW", m68851 }, 3794 {"pbis", 2, one(0xf08a), one(0xffbf), "Bc", m68851 }, 3795 {"pbisw", 2, one(0xf08a), one(0xffff), "BW", m68851 }, 3796 {"pblc", 2, one(0xf083), one(0xffbf), "Bc", m68851 }, 3797 {"pblcw", 2, one(0xf083), one(0xffff), "BW", m68851 }, 3798 {"pbls", 2, one(0xf082), one(0xffbf), "Bc", m68851 }, 3799 {"pblsw", 2, one(0xf082), one(0xffff), "BW", m68851 }, 3800 {"pbsc", 2, one(0xf085), one(0xffbf), "Bc", m68851 }, 3801 {"pbscw", 2, one(0xf085), one(0xffff), "BW", m68851 }, 3802 {"pbss", 2, one(0xf084), one(0xffbf), "Bc", m68851 }, 3803 {"pbssw", 2, one(0xf084), one(0xffff), "BW", m68851 }, 3804 {"pbwc", 2, one(0xf089), one(0xffbf), "Bc", m68851 }, 3805 {"pbwcw", 2, one(0xf089), one(0xffff), "BW", m68851 }, 3806 {"pbws", 2, one(0xf088), one(0xffbf), "Bc", m68851 }, 3807 {"pbwsw", 2, one(0xf088), one(0xffff), "BW", m68851 }, 3808 3809 {"pdbac", 4, two(0xf048, 0x0007), two(0xfff8, 0xffff), "DsBw", m68851 }, 3810 {"pdbas", 4, two(0xf048, 0x0006), two(0xfff8, 0xffff), "DsBw", m68851 }, 3811 {"pdbbc", 4, two(0xf048, 0x0001), two(0xfff8, 0xffff), "DsBw", m68851 }, 3812 {"pdbbs", 4, two(0xf048, 0x0000), two(0xfff8, 0xffff), "DsBw", m68851 }, 3813 {"pdbcc", 4, two(0xf048, 0x000f), two(0xfff8, 0xffff), "DsBw", m68851 }, 3814 {"pdbcs", 4, two(0xf048, 0x000e), two(0xfff8, 0xffff), "DsBw", m68851 }, 3815 {"pdbgc", 4, two(0xf048, 0x000d), two(0xfff8, 0xffff), "DsBw", m68851 }, 3816 {"pdbgs", 4, two(0xf048, 0x000c), two(0xfff8, 0xffff), "DsBw", m68851 }, 3817 {"pdbic", 4, two(0xf048, 0x000b), two(0xfff8, 0xffff), "DsBw", m68851 }, 3818 {"pdbis", 4, two(0xf048, 0x000a), two(0xfff8, 0xffff), "DsBw", m68851 }, 3819 {"pdblc", 4, two(0xf048, 0x0003), two(0xfff8, 0xffff), "DsBw", m68851 }, 3820 {"pdbls", 4, two(0xf048, 0x0002), two(0xfff8, 0xffff), "DsBw", m68851 }, 3821 {"pdbsc", 4, two(0xf048, 0x0005), two(0xfff8, 0xffff), "DsBw", m68851 }, 3822 {"pdbss", 4, two(0xf048, 0x0004), two(0xfff8, 0xffff), "DsBw", m68851 }, 3823 {"pdbwc", 4, two(0xf048, 0x0009), two(0xfff8, 0xffff), "DsBw", m68851 }, 3824 {"pdbws", 4, two(0xf048, 0x0008), two(0xfff8, 0xffff), "DsBw", m68851 }, 3825 3826 {"pea", 2, one(0044100), one(0177700), "!s", m68000up|mcfisa_a }, 3827 3828 {"pflusha", 2, one(0xf518), one(0xfff8), "", m68040up }, 3829 {"pflusha", 4, two(0xf000,0x2400), two(0xffff,0xffff), "", m68030 | m68851 }, 3830 3831 {"pflush", 4, two(0xf000,0x3010), two(0xffc0,0xfe10), "T3T9", m68030|m68851 }, 3832 {"pflush", 4, two(0xf000,0x3810), two(0xffc0,0xfe10), "T3T9&s", m68030|m68851 }, 3833 {"pflush", 4, two(0xf000,0x3008), two(0xffc0,0xfe18), "D3T9", m68030|m68851 }, 3834 {"pflush", 4, two(0xf000,0x3808), two(0xffc0,0xfe18), "D3T9&s", m68030|m68851 }, 3835 {"pflush", 4, two(0xf000,0x3000), two(0xffc0,0xfe1e), "f3T9", m68030|m68851 }, 3836 {"pflush", 4, two(0xf000,0x3800), two(0xffc0,0xfe1e), "f3T9&s", m68030|m68851 }, 3837 {"pflush", 2, one(0xf508), one(0xfff8), "as", m68040up }, 3838 {"pflush", 2, one(0xf508), one(0xfff8), "As", m68040up }, 3839 3840 {"pflushan", 2, one(0xf510), one(0xfff8), "", m68040up }, 3841 {"pflushn", 2, one(0xf500), one(0xfff8), "as", m68040up }, 3842 {"pflushn", 2, one(0xf500), one(0xfff8), "As", m68040up }, 3843 3844 {"pflushr", 4, two(0xf000, 0xa000), two(0xffc0, 0xffff), "|s", m68851 }, 3845 3846 {"pflushs", 4, two(0xf000, 0x3410), two(0xfff8, 0xfe10), "T3T9", m68851 }, 3847 {"pflushs", 4, two(0xf000, 0x3c10), two(0xfff8, 0xfe10), "T3T9&s", m68851 }, 3848 {"pflushs", 4, two(0xf000, 0x3408), two(0xfff8, 0xfe18), "D3T9", m68851 }, 3849 {"pflushs", 4, two(0xf000, 0x3c08), two(0xfff8, 0xfe18), "D3T9&s", m68851 }, 3850 {"pflushs", 4, two(0xf000, 0x3400), two(0xfff8, 0xfe1e), "f3T9", m68851 }, 3851 {"pflushs", 4, two(0xf000, 0x3c00), two(0xfff8, 0xfe1e), "f3T9&s", m68851 }, 3852 3853 {"ploadr", 4, two(0xf000,0x2210), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, 3854 {"ploadr", 4, two(0xf000,0x2208), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, 3855 {"ploadr", 4, two(0xf000,0x2200), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, 3856 {"ploadw", 4, two(0xf000,0x2010), two(0xffc0,0xfff0), "T3&s", m68030|m68851 }, 3857 {"ploadw", 4, two(0xf000,0x2008), two(0xffc0,0xfff8), "D3&s", m68030|m68851 }, 3858 {"ploadw", 4, two(0xf000,0x2000), two(0xffc0,0xfffe), "f3&s", m68030|m68851 }, 3859 3860 {"plpar", 2, one(0xf5c8), one(0xfff8), "as", m68060 }, 3861 {"plpaw", 2, one(0xf588), one(0xfff8), "as", m68060 }, 3862 3863 {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xffff), "*l08", m68030|m68851 }, 3864 {"pmove", 4, two(0xf000,0x5c00), two(0xffc0,0xffff), "*w18", m68851 }, 3865 {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "*b28", m68851 }, 3866 {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xffff), "08%s", m68030|m68851 }, 3867 {"pmove", 4, two(0xf000,0x5e00), two(0xffc0,0xffff), "18%s", m68851 }, 3868 {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "28%s", m68851 }, 3869 {"pmove", 4, two(0xf000,0x4000), two(0xffc0,0xe3ff), "|sW8", m68030|m68851 }, 3870 {"pmove", 4, two(0xf000,0x4200), two(0xffc0,0xe3ff), "W8~s", m68030|m68851 }, 3871 {"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xe3e3), "*wX3", m68851 }, 3872 {"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xe3e3), "X3%s", m68851 }, 3873 {"pmove", 4, two(0xf000,0x6000), two(0xffc0,0xffff), "*wY8", m68030|m68851 }, 3874 {"pmove", 4, two(0xf000,0x6200), two(0xffc0,0xffff), "Y8%s", m68030|m68851 }, 3875 {"pmove", 4, two(0xf000,0x6600), two(0xffc0,0xffff), "Z8%s", m68851 }, 3876 {"pmove", 4, two(0xf000,0x0800), two(0xffc0,0xfbff), "*l38", m68030 }, 3877 {"pmove", 4, two(0xf000,0x0a00), two(0xffc0,0xfbff), "38%s", m68030 }, 3878 3879 {"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "*l08", m68030 }, 3880 {"pmovefd", 4, two(0xf000, 0x4100), two(0xffc0, 0xe3ff), "|sW8", m68030 }, 3881 {"pmovefd", 4, two(0xf000, 0x0900), two(0xffc0, 0xfbff), "*l38", m68030 }, 3882 3883 {"prestore", 2, one(0xf140), one(0xffc0), "<s", m68851 }, 3884 3885 {"psave", 2, one(0xf100), one(0xffc0), ">s", m68851 }, 3886 3887 {"psac", 4, two(0xf040, 0x0007), two(0xffc0, 0xffff), "$s", m68851 }, 3888 {"psas", 4, two(0xf040, 0x0006), two(0xffc0, 0xffff), "$s", m68851 }, 3889 {"psbc", 4, two(0xf040, 0x0001), two(0xffc0, 0xffff), "$s", m68851 }, 3890 {"psbs", 4, two(0xf040, 0x0000), two(0xffc0, 0xffff), "$s", m68851 }, 3891 {"pscc", 4, two(0xf040, 0x000f), two(0xffc0, 0xffff), "$s", m68851 }, 3892 {"pscs", 4, two(0xf040, 0x000e), two(0xffc0, 0xffff), "$s", m68851 }, 3893 {"psgc", 4, two(0xf040, 0x000d), two(0xffc0, 0xffff), "$s", m68851 }, 3894 {"psgs", 4, two(0xf040, 0x000c), two(0xffc0, 0xffff), "$s", m68851 }, 3895 {"psic", 4, two(0xf040, 0x000b), two(0xffc0, 0xffff), "$s", m68851 }, 3896 {"psis", 4, two(0xf040, 0x000a), two(0xffc0, 0xffff), "$s", m68851 }, 3897 {"pslc", 4, two(0xf040, 0x0003), two(0xffc0, 0xffff), "$s", m68851 }, 3898 {"psls", 4, two(0xf040, 0x0002), two(0xffc0, 0xffff), "$s", m68851 }, 3899 {"pssc", 4, two(0xf040, 0x0005), two(0xffc0, 0xffff), "$s", m68851 }, 3900 {"psss", 4, two(0xf040, 0x0004), two(0xffc0, 0xffff), "$s", m68851 }, 3901 {"pswc", 4, two(0xf040, 0x0009), two(0xffc0, 0xffff), "$s", m68851 }, 3902 {"psws", 4, two(0xf040, 0x0008), two(0xffc0, 0xffff), "$s", m68851 }, 3903 3904 {"ptestr", 4, two(0xf000,0x8210), two(0xffc0, 0xe3f0), "T3&st8", m68030|m68851 }, 3905 {"ptestr", 4, two(0xf000,0x8310), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, 3906 {"ptestr", 4, two(0xf000,0x8208), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, 3907 {"ptestr", 4, two(0xf000,0x8308), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, 3908 {"ptestr", 4, two(0xf000,0x8200), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, 3909 {"ptestr", 4, two(0xf000,0x8300), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, 3910 {"ptestr", 2, one(0xf568), one(0xfff8), "as", m68040 }, 3911 3912 {"ptestw", 4, two(0xf000,0x8010), two(0xffc0,0xe3f0), "T3&st8", m68030|m68851 }, 3913 {"ptestw", 4, two(0xf000,0x8110), two(0xffc0,0xe310), "T3&st8A9", m68030|m68851 }, 3914 {"ptestw", 4, two(0xf000,0x8008), two(0xffc0,0xe3f8), "D3&st8", m68030|m68851 }, 3915 {"ptestw", 4, two(0xf000,0x8108), two(0xffc0,0xe318), "D3&st8A9", m68030|m68851 }, 3916 {"ptestw", 4, two(0xf000,0x8000), two(0xffc0,0xe3fe), "f3&st8", m68030|m68851 }, 3917 {"ptestw", 4, two(0xf000,0x8100), two(0xffc0,0xe31e), "f3&st8A9", m68030|m68851 }, 3918 {"ptestw", 2, one(0xf548), one(0xfff8), "as", m68040 }, 3919 3920 {"ptrapacw", 6, two(0xf07a, 0x0007), two(0xffff, 0xffff), "#w", m68851 }, 3921 {"ptrapacl", 6, two(0xf07b, 0x0007), two(0xffff, 0xffff), "#l", m68851 }, 3922 {"ptrapac", 4, two(0xf07c, 0x0007), two(0xffff, 0xffff), "", m68851 }, 3923 3924 {"ptrapasw", 6, two(0xf07a, 0x0006), two(0xffff, 0xffff), "#w", m68851 }, 3925 {"ptrapasl", 6, two(0xf07b, 0x0006), two(0xffff, 0xffff), "#l", m68851 }, 3926 {"ptrapas", 4, two(0xf07c, 0x0006), two(0xffff, 0xffff), "", m68851 }, 3927 3928 {"ptrapbcw", 6, two(0xf07a, 0x0001), two(0xffff, 0xffff), "#w", m68851 }, 3929 {"ptrapbcl", 6, two(0xf07b, 0x0001), two(0xffff, 0xffff), "#l", m68851 }, 3930 {"ptrapbc", 4, two(0xf07c, 0x0001), two(0xffff, 0xffff), "", m68851 }, 3931 3932 {"ptrapbsw", 6, two(0xf07a, 0x0000), two(0xffff, 0xffff), "#w", m68851 }, 3933 {"ptrapbsl", 6, two(0xf07b, 0x0000), two(0xffff, 0xffff), "#l", m68851 }, 3934 {"ptrapbs", 4, two(0xf07c, 0x0000), two(0xffff, 0xffff), "", m68851 }, 3935 3936 {"ptrapccw", 6, two(0xf07a, 0x000f), two(0xffff, 0xffff), "#w", m68851 }, 3937 {"ptrapccl", 6, two(0xf07b, 0x000f), two(0xffff, 0xffff), "#l", m68851 }, 3938 {"ptrapcc", 4, two(0xf07c, 0x000f), two(0xffff, 0xffff), "", m68851 }, 3939 3940 {"ptrapcsw", 6, two(0xf07a, 0x000e), two(0xffff, 0xffff), "#w", m68851 }, 3941 {"ptrapcsl", 6, two(0xf07b, 0x000e), two(0xffff, 0xffff), "#l", m68851 }, 3942 {"ptrapcs", 4, two(0xf07c, 0x000e), two(0xffff, 0xffff), "", m68851 }, 3943 3944 {"ptrapgcw", 6, two(0xf07a, 0x000d), two(0xffff, 0xffff), "#w", m68851 }, 3945 {"ptrapgcl", 6, two(0xf07b, 0x000d), two(0xffff, 0xffff), "#l", m68851 }, 3946 {"ptrapgc", 4, two(0xf07c, 0x000d), two(0xffff, 0xffff), "", m68851 }, 3947 3948 {"ptrapgsw", 6, two(0xf07a, 0x000c), two(0xffff, 0xffff), "#w", m68851 }, 3949 {"ptrapgsl", 6, two(0xf07b, 0x000c), two(0xffff, 0xffff), "#l", m68851 }, 3950 {"ptrapgs", 4, two(0xf07c, 0x000c), two(0xffff, 0xffff), "", m68851 }, 3951 3952 {"ptrapicw", 6, two(0xf07a, 0x000b), two(0xffff, 0xffff), "#w", m68851 }, 3953 {"ptrapicl", 6, two(0xf07b, 0x000b), two(0xffff, 0xffff), "#l", m68851 }, 3954 {"ptrapic", 4, two(0xf07c, 0x000b), two(0xffff, 0xffff), "", m68851 }, 3955 3956 {"ptrapisw", 6, two(0xf07a, 0x000a), two(0xffff, 0xffff), "#w", m68851 }, 3957 {"ptrapisl", 6, two(0xf07b, 0x000a), two(0xffff, 0xffff), "#l", m68851 }, 3958 {"ptrapis", 4, two(0xf07c, 0x000a), two(0xffff, 0xffff), "", m68851 }, 3959 3960 {"ptraplcw", 6, two(0xf07a, 0x0003), two(0xffff, 0xffff), "#w", m68851 }, 3961 {"ptraplcl", 6, two(0xf07b, 0x0003), two(0xffff, 0xffff), "#l", m68851 }, 3962 {"ptraplc", 4, two(0xf07c, 0x0003), two(0xffff, 0xffff), "", m68851 }, 3963 3964 {"ptraplsw", 6, two(0xf07a, 0x0002), two(0xffff, 0xffff), "#w", m68851 }, 3965 {"ptraplsl", 6, two(0xf07b, 0x0002), two(0xffff, 0xffff), "#l", m68851 }, 3966 {"ptrapls", 4, two(0xf07c, 0x0002), two(0xffff, 0xffff), "", m68851 }, 3967 3968 {"ptrapscw", 6, two(0xf07a, 0x0005), two(0xffff, 0xffff), "#w", m68851 }, 3969 {"ptrapscl", 6, two(0xf07b, 0x0005), two(0xffff, 0xffff), "#l", m68851 }, 3970 {"ptrapsc", 4, two(0xf07c, 0x0005), two(0xffff, 0xffff), "", m68851 }, 3971 3972 {"ptrapssw", 6, two(0xf07a, 0x0004), two(0xffff, 0xffff), "#w", m68851 }, 3973 {"ptrapssl", 6, two(0xf07b, 0x0004), two(0xffff, 0xffff), "#l", m68851 }, 3974 {"ptrapss", 4, two(0xf07c, 0x0004), two(0xffff, 0xffff), "", m68851 }, 3975 3976 {"ptrapwcw", 6, two(0xf07a, 0x0009), two(0xffff, 0xffff), "#w", m68851 }, 3977 {"ptrapwcl", 6, two(0xf07b, 0x0009), two(0xffff, 0xffff), "#l", m68851 }, 3978 {"ptrapwc", 4, two(0xf07c, 0x0009), two(0xffff, 0xffff), "", m68851 }, 3979 3980 {"ptrapwsw", 6, two(0xf07a, 0x0008), two(0xffff, 0xffff), "#w", m68851 }, 3981 {"ptrapwsl", 6, two(0xf07b, 0x0008), two(0xffff, 0xffff), "#l", m68851 }, 3982 {"ptrapws", 4, two(0xf07c, 0x0008), two(0xffff, 0xffff), "", m68851 }, 3983 3984 {"pulse", 2, one(0045314), one(0177777), "", m68060 | mcfisa_a }, 3985 3986 {"pvalid", 4, two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 }, 3987 {"pvalid", 4, two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 }, 3988 3989 /* FIXME: don't allow Dw==Dx. */ 3990 {"remsl", 4, two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv }, 3991 {"remul", 4, two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "qsD3D1", mcfhwdiv }, 3992 3993 {"reset", 2, one(0047160), one(0177777), "", m68000up }, 3994 3995 {"rolb", 2, one(0160430), one(0170770), "QdDs", m68000up }, 3996 {"rolb", 2, one(0160470), one(0170770), "DdDs", m68000up }, 3997 {"rolw", 2, one(0160530), one(0170770), "QdDs", m68000up }, 3998 {"rolw", 2, one(0160570), one(0170770), "DdDs", m68000up }, 3999 {"rolw", 2, one(0163700), one(0177700), "~s", m68000up }, 4000 {"roll", 2, one(0160630), one(0170770), "QdDs", m68000up }, 4001 {"roll", 2, one(0160670), one(0170770), "DdDs", m68000up }, 4002 4003 {"rorb", 2, one(0160030), one(0170770), "QdDs", m68000up }, 4004 {"rorb", 2, one(0160070), one(0170770), "DdDs", m68000up }, 4005 {"rorw", 2, one(0160130), one(0170770), "QdDs", m68000up }, 4006 {"rorw", 2, one(0160170), one(0170770), "DdDs", m68000up }, 4007 {"rorw", 2, one(0163300), one(0177700), "~s", m68000up }, 4008 {"rorl", 2, one(0160230), one(0170770), "QdDs", m68000up }, 4009 {"rorl", 2, one(0160270), one(0170770), "DdDs", m68000up }, 4010 4011 {"roxlb", 2, one(0160420), one(0170770), "QdDs", m68000up }, 4012 {"roxlb", 2, one(0160460), one(0170770), "DdDs", m68000up }, 4013 {"roxlw", 2, one(0160520), one(0170770), "QdDs", m68000up }, 4014 {"roxlw", 2, one(0160560), one(0170770), "DdDs", m68000up }, 4015 {"roxlw", 2, one(0162700), one(0177700), "~s", m68000up }, 4016 {"roxll", 2, one(0160620), one(0170770), "QdDs", m68000up }, 4017 {"roxll", 2, one(0160660), one(0170770), "DdDs", m68000up }, 4018 4019 {"roxrb", 2, one(0160020), one(0170770), "QdDs", m68000up }, 4020 {"roxrb", 2, one(0160060), one(0170770), "DdDs", m68000up }, 4021 {"roxrw", 2, one(0160120), one(0170770), "QdDs", m68000up }, 4022 {"roxrw", 2, one(0160160), one(0170770), "DdDs", m68000up }, 4023 {"roxrw", 2, one(0162300), one(0177700), "~s", m68000up }, 4024 {"roxrl", 2, one(0160220), one(0170770), "QdDs", m68000up }, 4025 {"roxrl", 2, one(0160260), one(0170770), "DdDs", m68000up }, 4026 4027 {"rtd", 4, one(0047164), one(0177777), "#w", m68010up }, 4028 4029 {"rte", 2, one(0047163), one(0177777), "", m68000up | mcfisa_a }, 4030 4031 {"rtm", 2, one(0003300), one(0177760), "Rs", m68020 }, 4032 4033 {"rtr", 2, one(0047167), one(0177777), "", m68000up }, 4034 4035 {"rts", 2, one(0047165), one(0177777), "", m68000up | mcfisa_a }, 4036 4037 {"satsl", 2, one(0046200), one(0177770), "Ds", mcfisa_b }, 4038 4039 {"sbcd", 2, one(0100400), one(0170770), "DsDd", m68000up }, 4040 {"sbcd", 2, one(0100410), one(0170770), "-s-d", m68000up }, 4041 4042 {"scc", 2, one(0052300), one(0177700), "$s", m68000up }, 4043 {"scc", 2, one(0052300), one(0177700), "Ds", mcfisa_a }, 4044 {"scs", 2, one(0052700), one(0177700), "$s", m68000up }, 4045 {"scs", 2, one(0052700), one(0177700), "Ds", mcfisa_a }, 4046 {"seq", 2, one(0053700), one(0177700), "$s", m68000up }, 4047 {"seq", 2, one(0053700), one(0177700), "Ds", mcfisa_a }, 4048 {"sf", 2, one(0050700), one(0177700), "$s", m68000up }, 4049 {"sf", 2, one(0050700), one(0177700), "Ds", mcfisa_a }, 4050 {"sge", 2, one(0056300), one(0177700), "$s", m68000up }, 4051 {"sge", 2, one(0056300), one(0177700), "Ds", mcfisa_a }, 4052 {"sgt", 2, one(0057300), one(0177700), "$s", m68000up }, 4053 {"sgt", 2, one(0057300), one(0177700), "Ds", mcfisa_a }, 4054 {"shi", 2, one(0051300), one(0177700), "$s", m68000up }, 4055 {"shi", 2, one(0051300), one(0177700), "Ds", mcfisa_a }, 4056 {"sle", 2, one(0057700), one(0177700), "$s", m68000up }, 4057 {"sle", 2, one(0057700), one(0177700), "Ds", mcfisa_a }, 4058 {"sls", 2, one(0051700), one(0177700), "$s", m68000up }, 4059 {"sls", 2, one(0051700), one(0177700), "Ds", mcfisa_a }, 4060 {"slt", 2, one(0056700), one(0177700), "$s", m68000up }, 4061 {"slt", 2, one(0056700), one(0177700), "Ds", mcfisa_a }, 4062 {"smi", 2, one(0055700), one(0177700), "$s", m68000up }, 4063 {"smi", 2, one(0055700), one(0177700), "Ds", mcfisa_a }, 4064 {"sne", 2, one(0053300), one(0177700), "$s", m68000up }, 4065 {"sne", 2, one(0053300), one(0177700), "Ds", mcfisa_a }, 4066 {"spl", 2, one(0055300), one(0177700), "$s", m68000up }, 4067 {"spl", 2, one(0055300), one(0177700), "Ds", mcfisa_a }, 4068 {"st", 2, one(0050300), one(0177700), "$s", m68000up }, 4069 {"st", 2, one(0050300), one(0177700), "Ds", mcfisa_a }, 4070 {"svc", 2, one(0054300), one(0177700), "$s", m68000up }, 4071 {"svc", 2, one(0054300), one(0177700), "Ds", mcfisa_a }, 4072 {"svs", 2, one(0054700), one(0177700), "$s", m68000up }, 4073 {"svs", 2, one(0054700), one(0177700), "Ds", mcfisa_a }, 4074 4075 {"stop", 4, one(0047162), one(0177777), "#w", m68000up | mcfisa_a }, 4076 4077 {"strldsr", 4, two(0040347,0043374), two(0177777,0177777), "#w", mcfisa_aa}, 4078 4079 {"subal", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a }, 4080 {"subaw", 2, one(0110300), one(0170700), "*wAd", m68000up }, 4081 4082 {"subib", 4, one(0002000), one(0177700), "#b$s", m68000up }, 4083 {"subiw", 4, one(0002100), one(0177700), "#w$s", m68000up }, 4084 {"subil", 6, one(0002200), one(0177700), "#l$s", m68000up }, 4085 {"subil", 6, one(0002200), one(0177700), "#lDs", mcfisa_a }, 4086 4087 {"subqb", 2, one(0050400), one(0170700), "Qd%s", m68000up }, 4088 {"subqw", 2, one(0050500), one(0170700), "Qd%s", m68000up }, 4089 {"subql", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a }, 4090 4091 /* The sub opcode can generate the suba, subi, and subq instructions. */ 4092 {"subb", 2, one(0050400), one(0170700), "Qd%s", m68000up }, 4093 {"subb", 4, one(0002000), one(0177700), "#b$s", m68000up }, 4094 {"subb", 2, one(0110000), one(0170700), ";bDd", m68000up }, 4095 {"subb", 2, one(0110400), one(0170700), "Dd~s", m68000up }, 4096 {"subw", 2, one(0050500), one(0170700), "Qd%s", m68000up }, 4097 {"subw", 4, one(0002100), one(0177700), "#w$s", m68000up }, 4098 {"subw", 2, one(0110300), one(0170700), "*wAd", m68000up }, 4099 {"subw", 2, one(0110100), one(0170700), "*wDd", m68000up }, 4100 {"subw", 2, one(0110500), one(0170700), "Dd~s", m68000up }, 4101 {"subl", 2, one(0050600), one(0170700), "Qd%s", m68000up | mcfisa_a }, 4102 {"subl", 6, one(0002200), one(0177700), "#l$s", m68000up }, 4103 {"subl", 6, one(0002200), one(0177700), "#lDs", mcfisa_a }, 4104 {"subl", 2, one(0110700), one(0170700), "*lAd", m68000up | mcfisa_a }, 4105 {"subl", 2, one(0110200), one(0170700), "*lDd", m68000up | mcfisa_a }, 4106 {"subl", 2, one(0110600), one(0170700), "Dd~s", m68000up | mcfisa_a }, 4107 4108 {"subxb", 2, one(0110400), one(0170770), "DsDd", m68000up }, 4109 {"subxb", 2, one(0110410), one(0170770), "-s-d", m68000up }, 4110 {"subxw", 2, one(0110500), one(0170770), "DsDd", m68000up }, 4111 {"subxw", 2, one(0110510), one(0170770), "-s-d", m68000up }, 4112 {"subxl", 2, one(0110600), one(0170770), "DsDd", m68000up | mcfisa_a }, 4113 {"subxl", 2, one(0110610), one(0170770), "-s-d", m68000up }, 4114 4115 {"swap", 2, one(0044100), one(0177770), "Ds", m68000up | mcfisa_a }, 4116 4117 /* swbeg and swbegl are magic constants used on sysV68. The compiler 4118 generates them before a switch table. They tell the debugger and 4119 disassembler that a switch table follows. The parameter is the 4120 number of elements in the table. swbeg means that the entries in 4121 the table are word (2 byte) sized, and swbegl means that the 4122 entries in the table are longword (4 byte) sized. */ 4123 {"swbeg", 4, one(0045374), one(0177777), "#w", m68000up | mcfisa_a }, 4124 {"swbegl", 6, one(0045375), one(0177777), "#l", m68000up | mcfisa_a }, 4125 4126 {"tas", 2, one(0045300), one(0177700), "$s", m68000up | mcfisa_b}, 4127 4128 #define TBL1(name,insn_size,signed,round,size) \ 4129 {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)|0000400), \ 4130 two(0177700,0107777), "!sD1", cpu32 }, \ 4131 {name, insn_size, two(0174000, (signed<<11)|(!round<<10)|(size<<6)), \ 4132 two(0177770,0107770), "DsD3D1", cpu32 } 4133 #define TBL(name1, name2, name3, s, r) \ 4134 TBL1(name1, 4, s, r, 0), TBL1(name2, 4, s, r, 1), TBL1(name3, 4, s, r, 2) 4135 TBL("tblsb", "tblsw", "tblsl", 2, 1), 4136 TBL("tblsnb", "tblsnw", "tblsnl", 2, 0), 4137 TBL("tblub", "tbluw", "tblul", 0, 1), 4138 TBL("tblunb", "tblunw", "tblunl", 0, 0), 4139 4140 {"trap", 2, one(0047100), one(0177760), "Ts", m68000up | mcfisa_a }, 4141 4142 {"trapcc", 2, one(0052374), one(0177777), "", m68020up | cpu32 }, 4143 {"trapcs", 2, one(0052774), one(0177777), "", m68020up | cpu32 }, 4144 {"trapeq", 2, one(0053774), one(0177777), "", m68020up | cpu32 }, 4145 {"trapf", 2, one(0050774), one(0177777), "", m68020up | cpu32 | mcfisa_a }, 4146 {"trapge", 2, one(0056374), one(0177777), "", m68020up | cpu32 }, 4147 {"trapgt", 2, one(0057374), one(0177777), "", m68020up | cpu32 }, 4148 {"traphi", 2, one(0051374), one(0177777), "", m68020up | cpu32 }, 4149 {"traple", 2, one(0057774), one(0177777), "", m68020up | cpu32 }, 4150 {"trapls", 2, one(0051774), one(0177777), "", m68020up | cpu32 }, 4151 {"traplt", 2, one(0056774), one(0177777), "", m68020up | cpu32 }, 4152 {"trapmi", 2, one(0055774), one(0177777), "", m68020up | cpu32 }, 4153 {"trapne", 2, one(0053374), one(0177777), "", m68020up | cpu32 }, 4154 {"trappl", 2, one(0055374), one(0177777), "", m68020up | cpu32 }, 4155 {"trapt", 2, one(0050374), one(0177777), "", m68020up | cpu32 }, 4156 {"trapvc", 2, one(0054374), one(0177777), "", m68020up | cpu32 }, 4157 {"trapvs", 2, one(0054774), one(0177777), "", m68020up | cpu32 }, 4158 4159 {"trapccw", 4, one(0052372), one(0177777), "#w", m68020up|cpu32 }, 4160 {"trapcsw", 4, one(0052772), one(0177777), "#w", m68020up|cpu32 }, 4161 {"trapeqw", 4, one(0053772), one(0177777), "#w", m68020up|cpu32 }, 4162 {"trapfw", 4, one(0050772), one(0177777), "#w", m68020up|cpu32|mcfisa_a}, 4163 {"trapgew", 4, one(0056372), one(0177777), "#w", m68020up|cpu32 }, 4164 {"trapgtw", 4, one(0057372), one(0177777), "#w", m68020up|cpu32 }, 4165 {"traphiw", 4, one(0051372), one(0177777), "#w", m68020up|cpu32 }, 4166 {"traplew", 4, one(0057772), one(0177777), "#w", m68020up|cpu32 }, 4167 {"traplsw", 4, one(0051772), one(0177777), "#w", m68020up|cpu32 }, 4168 {"trapltw", 4, one(0056772), one(0177777), "#w", m68020up|cpu32 }, 4169 {"trapmiw", 4, one(0055772), one(0177777), "#w", m68020up|cpu32 }, 4170 {"trapnew", 4, one(0053372), one(0177777), "#w", m68020up|cpu32 }, 4171 {"trapplw", 4, one(0055372), one(0177777), "#w", m68020up|cpu32 }, 4172 {"traptw", 4, one(0050372), one(0177777), "#w", m68020up|cpu32 }, 4173 {"trapvcw", 4, one(0054372), one(0177777), "#w", m68020up|cpu32 }, 4174 {"trapvsw", 4, one(0054772), one(0177777), "#w", m68020up|cpu32 }, 4175 4176 {"trapccl", 6, one(0052373), one(0177777), "#l", m68020up|cpu32 }, 4177 {"trapcsl", 6, one(0052773), one(0177777), "#l", m68020up|cpu32 }, 4178 {"trapeql", 6, one(0053773), one(0177777), "#l", m68020up|cpu32 }, 4179 {"trapfl", 6, one(0050773), one(0177777), "#l", m68020up|cpu32|mcfisa_a}, 4180 {"trapgel", 6, one(0056373), one(0177777), "#l", m68020up|cpu32 }, 4181 {"trapgtl", 6, one(0057373), one(0177777), "#l", m68020up|cpu32 }, 4182 {"traphil", 6, one(0051373), one(0177777), "#l", m68020up|cpu32 }, 4183 {"traplel", 6, one(0057773), one(0177777), "#l", m68020up|cpu32 }, 4184 {"traplsl", 6, one(0051773), one(0177777), "#l", m68020up|cpu32 }, 4185 {"trapltl", 6, one(0056773), one(0177777), "#l", m68020up|cpu32 }, 4186 {"trapmil", 6, one(0055773), one(0177777), "#l", m68020up|cpu32 }, 4187 {"trapnel", 6, one(0053373), one(0177777), "#l", m68020up|cpu32 }, 4188 {"trappll", 6, one(0055373), one(0177777), "#l", m68020up|cpu32 }, 4189 {"traptl", 6, one(0050373), one(0177777), "#l", m68020up|cpu32 }, 4190 {"trapvcl", 6, one(0054373), one(0177777), "#l", m68020up|cpu32 }, 4191 {"trapvsl", 6, one(0054773), one(0177777), "#l", m68020up|cpu32 }, 4192 4193 {"trapv", 2, one(0047166), one(0177777), "", m68000up }, 4194 4195 {"tstb", 2, one(0045000), one(0177700), ";b", m68020up|cpu32|mcfisa_a }, 4196 {"tstb", 2, one(0045000), one(0177700), "$b", m68000up }, 4197 {"tstw", 2, one(0045100), one(0177700), "*w", m68020up|cpu32|mcfisa_a }, 4198 {"tstw", 2, one(0045100), one(0177700), "$w", m68000up }, 4199 {"tstl", 2, one(0045200), one(0177700), "*l", m68020up|cpu32|mcfisa_a }, 4200 {"tstl", 2, one(0045200), one(0177700), "$l", m68000up }, 4201 4202 {"unlk", 2, one(0047130), one(0177770), "As", m68000up | mcfisa_a }, 4203 4204 {"unpk", 4, one(0100600), one(0170770), "DsDd#w", m68020up }, 4205 {"unpk", 4, one(0100610), one(0170770), "-s-d#w", m68020up }, 4206 4207 {"wddatab", 2, one(0175400), one(0177700), "~s", mcfisa_a }, 4208 {"wddataw", 2, one(0175500), one(0177700), "~s", mcfisa_a }, 4209 {"wddatal", 2, one(0175600), one(0177700), "~s", mcfisa_a }, 4210 4211 {"wdebug", 4, two(0175720, 03), two(0177770, 0xffff), "as", mcfisa_a }, 4212 {"wdebug", 4, two(0175750, 03), two(0177770, 0xffff), "ds", mcfisa_a }, 4213 }; 4214 4215 const int m68k_numopcodes = sizeof m68k_opcodes / sizeof m68k_opcodes[0]; 4216 4217 /* These aliases used to be in the above table, each one duplicating 4218 all of the entries for its primary exactly. This table was 4219 constructed by mechanical processing of the opcode table, with a 4220 small number of tweaks done by hand. There are probably a lot more 4221 aliases above that could be moved down here, except for very minor 4222 differences. */ 4223 4224 const struct m68k_opcode_alias m68k_opcode_aliases[] = 4225 { 4226 { "add", "addw", }, 4227 { "adda", "addaw", }, 4228 { "addi", "addiw", }, 4229 { "addq", "addqw", }, 4230 { "addx", "addxw", }, 4231 { "asl", "aslw", }, 4232 { "asr", "asrw", }, 4233 { "bhi", "bhiw", }, 4234 { "bls", "blsw", }, 4235 { "bcc", "bccw", }, 4236 { "bcs", "bcsw", }, 4237 { "bne", "bnew", }, 4238 { "beq", "beqw", }, 4239 { "bvc", "bvcw", }, 4240 { "bvs", "bvsw", }, 4241 { "bpl", "bplw", }, 4242 { "bmi", "bmiw", }, 4243 { "bge", "bgew", }, 4244 { "blt", "bltw", }, 4245 { "bgt", "bgtw", }, 4246 { "ble", "blew", }, 4247 { "bra", "braw", }, 4248 { "bsr", "bsrw", }, 4249 { "bhib", "bhis", }, 4250 { "blsb", "blss", }, 4251 { "bccb", "bccs", }, 4252 { "bcsb", "bcss", }, 4253 { "bneb", "bnes", }, 4254 { "beqb", "beqs", }, 4255 { "bvcb", "bvcs", }, 4256 { "bvsb", "bvss", }, 4257 { "bplb", "bpls", }, 4258 { "bmib", "bmis", }, 4259 { "bgeb", "bges", }, 4260 { "bltb", "blts", }, 4261 { "bgtb", "bgts", }, 4262 { "bleb", "bles", }, 4263 { "brab", "bras", }, 4264 { "bsrb", "bsrs", }, 4265 { "bhs", "bccw" }, 4266 { "bhss", "bccs" }, 4267 { "bhsb", "bccs" }, 4268 { "bhsw", "bccw" }, 4269 { "bhsl", "bccl" }, 4270 { "blo", "bcsw" }, 4271 { "blos", "bcss" }, 4272 { "blob", "bcss" }, 4273 { "blow", "bcsw" }, 4274 { "blol", "bcsl" }, 4275 { "br", "braw", }, 4276 { "brs", "bras", }, 4277 { "brb", "bras", }, 4278 { "brw", "braw", }, 4279 { "brl", "bral", }, 4280 { "jfnlt", "bcc", }, /* Apparently a sun alias. */ 4281 { "jfngt", "ble", }, /* Apparently a sun alias. */ 4282 { "jfeq", "beqs", }, /* Apparently a sun alias. */ 4283 { "bchgb", "bchg", }, 4284 { "bchgl", "bchg", }, 4285 { "bclrb", "bclr", }, 4286 { "bclrl", "bclr", }, 4287 { "bsetb", "bset", }, 4288 { "bsetl", "bset", }, 4289 { "btstb", "btst", }, 4290 { "btstl", "btst", }, 4291 { "cas2", "cas2w", }, 4292 { "cas", "casw", }, 4293 { "chk2", "chk2w", }, 4294 { "chk", "chkw", }, 4295 { "clr", "clrw", }, 4296 { "cmp2", "cmp2w", }, 4297 { "cmpa", "cmpaw", }, 4298 { "cmpi", "cmpiw", }, 4299 { "cmpm", "cmpmw", }, 4300 { "cmp", "cmpw", }, 4301 { "dbccw", "dbcc", }, 4302 { "dbcsw", "dbcs", }, 4303 { "dbeqw", "dbeq", }, 4304 { "dbfw", "dbf", }, 4305 { "dbgew", "dbge", }, 4306 { "dbgtw", "dbgt", }, 4307 { "dbhiw", "dbhi", }, 4308 { "dblew", "dble", }, 4309 { "dblsw", "dbls", }, 4310 { "dbltw", "dblt", }, 4311 { "dbmiw", "dbmi", }, 4312 { "dbnew", "dbne", }, 4313 { "dbplw", "dbpl", }, 4314 { "dbtw", "dbt", }, 4315 { "dbvcw", "dbvc", }, 4316 { "dbvsw", "dbvs", }, 4317 { "dbhs", "dbcc", }, 4318 { "dbhsw", "dbcc", }, 4319 { "dbra", "dbf", }, 4320 { "dbraw", "dbf", }, 4321 { "tdivsl", "divsl", }, 4322 { "divs", "divsw", }, 4323 { "divu", "divuw", }, 4324 { "ext", "extw", }, 4325 { "extbw", "extw", }, 4326 { "extwl", "extl", }, 4327 { "fbneq", "fbne", }, 4328 { "fbsneq", "fbsne", }, 4329 { "fdbneq", "fdbne", }, 4330 { "fdbsneq", "fdbsne", }, 4331 { "fmovecr", "fmovecrx", }, 4332 { "fmovm", "fmovem", }, 4333 { "fsneq", "fsne", }, 4334 { "fssneq", "fssne", }, 4335 { "ftrapneq", "ftrapne", }, 4336 { "ftrapsneq", "ftrapsne", }, 4337 { "fjneq", "fjne", }, 4338 { "fjsneq", "fjsne", }, 4339 { "jmpl", "jmp", }, 4340 { "jmps", "jmp", }, 4341 { "jsrl", "jsr", }, 4342 { "jsrs", "jsr", }, 4343 { "leal", "lea", }, 4344 { "lsl", "lslw", }, 4345 { "lsr", "lsrw", }, 4346 { "mac", "macw" }, 4347 { "movea", "moveaw", }, 4348 { "movem", "movemw", }, 4349 { "movml", "moveml", }, 4350 { "movmw", "movemw", }, 4351 { "movm", "movemw", }, 4352 { "movep", "movepw", }, 4353 { "movpw", "movepw", }, 4354 { "moves", "movesw" }, 4355 { "muls", "mulsw", }, 4356 { "mulu", "muluw", }, 4357 { "msac", "msacw" }, 4358 { "nbcdb", "nbcd" }, 4359 { "neg", "negw", }, 4360 { "negx", "negxw", }, 4361 { "not", "notw", }, 4362 { "peal", "pea", }, 4363 { "rol", "rolw", }, 4364 { "ror", "rorw", }, 4365 { "roxl", "roxlw", }, 4366 { "roxr", "roxrw", }, 4367 { "sats", "satsl", }, 4368 { "sbcdb", "sbcd", }, 4369 { "sccb", "scc", }, 4370 { "scsb", "scs", }, 4371 { "seqb", "seq", }, 4372 { "sfb", "sf", }, 4373 { "sgeb", "sge", }, 4374 { "sgtb", "sgt", }, 4375 { "shib", "shi", }, 4376 { "sleb", "sle", }, 4377 { "slsb", "sls", }, 4378 { "sltb", "slt", }, 4379 { "smib", "smi", }, 4380 { "sneb", "sne", }, 4381 { "splb", "spl", }, 4382 { "stb", "st", }, 4383 { "svcb", "svc", }, 4384 { "svsb", "svs", }, 4385 { "sfge", "sge", }, 4386 { "sfgt", "sgt", }, 4387 { "sfle", "sle", }, 4388 { "sflt", "slt", }, 4389 { "sfneq", "sne", }, 4390 { "suba", "subaw", }, 4391 { "subi", "subiw", }, 4392 { "subq", "subqw", }, 4393 { "sub", "subw", }, 4394 { "subx", "subxw", }, 4395 { "swapw", "swap", }, 4396 { "tasb", "tas", }, 4397 { "tpcc", "trapcc", }, 4398 { "tcc", "trapcc", }, 4399 { "tst", "tstw", }, 4400 { "jbra", "jra", }, 4401 { "jbhi", "jhi", }, 4402 { "jbls", "jls", }, 4403 { "jbcc", "jcc", }, 4404 { "jbcs", "jcs", }, 4405 { "jbne", "jne", }, 4406 { "jbeq", "jeq", }, 4407 { "jbvc", "jvc", }, 4408 { "jbvs", "jvs", }, 4409 { "jbpl", "jpl", }, 4410 { "jbmi", "jmi", }, 4411 { "jbge", "jge", }, 4412 { "jblt", "jlt", }, 4413 { "jbgt", "jgt", }, 4414 { "jble", "jle", }, 4415 { "movql", "moveq", }, 4416 { "moveql", "moveq", }, 4417 { "movl", "movel", }, 4418 { "movq", "moveq", }, 4419 { "moval", "moveal", }, 4420 { "movaw", "moveaw", }, 4421 { "movb", "moveb", }, 4422 { "movc", "movec", }, 4423 { "movecl", "movec", }, 4424 { "movpl", "movepl", }, 4425 { "movw", "movew", }, 4426 { "movsb", "movesb", }, 4427 { "movsl", "movesl", }, 4428 { "movsw", "movesw", }, 4429 { "mov3q", "mov3ql", }, 4430 4431 { "tdivul", "divul", }, /* For m68k-svr4. */ 4432 { "fmovb", "fmoveb", }, 4433 { "fsmovb", "fsmoveb", }, 4434 { "fdmovb", "fdmoveb", }, 4435 { "fmovd", "fmoved", }, 4436 { "fsmovd", "fsmoved", }, 4437 { "fmovl", "fmovel", }, 4438 { "fsmovl", "fsmovel", }, 4439 { "fdmovl", "fdmovel", }, 4440 { "fmovp", "fmovep", }, 4441 { "fsmovp", "fsmovep", }, 4442 { "fdmovp", "fdmovep", }, 4443 { "fmovs", "fmoves", }, 4444 { "fsmovs", "fsmoves", }, 4445 { "fdmovs", "fdmoves", }, 4446 { "fmovw", "fmovew", }, 4447 { "fsmovw", "fsmovew", }, 4448 { "fdmovw", "fdmovew", }, 4449 { "fmovx", "fmovex", }, 4450 { "fsmovx", "fsmovex", }, 4451 { "fdmovx", "fdmovex", }, 4452 { "fmovcr", "fmovecr", }, 4453 { "fmovcrx", "fmovecrx", }, 4454 { "ftestb", "ftstb", }, 4455 { "ftestd", "ftstd", }, 4456 { "ftestl", "ftstl", }, 4457 { "ftestp", "ftstp", }, 4458 { "ftests", "ftsts", }, 4459 { "ftestw", "ftstw", }, 4460 { "ftestx", "ftstx", }, 4461 4462 { "bitrevl", "bitrev", }, 4463 { "byterevl", "byterev", }, 4464 { "ff1l", "ff1", }, 4465 4466 }; 4467 4468 const int m68k_numaliases = 4469 sizeof m68k_opcode_aliases / sizeof m68k_opcode_aliases[0]; 4470 /* **** End of m68k-opc.c */ 4471 /* **** floatformat.c from sourceware.org CVS 2005-08-14. */ 4472 /* IEEE floating point support routines, for GDB, the GNU Debugger. 4473 Copyright (C) 1991, 1994, 1999, 2000, 2003 Free Software Foundation, Inc. 4474 4475 This file is part of GDB. 4476 4477 This program is free software; you can redistribute it and/or modify 4478 it under the terms of the GNU General Public License as published by 4479 the Free Software Foundation; either version 2 of the License, or 4480 (at your option) any later version. 4481 4482 This program is distributed in the hope that it will be useful, 4483 but WITHOUT ANY WARRANTY; without even the implied warranty of 4484 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 4485 GNU General Public License for more details. 4486 4487 You should have received a copy of the GNU General Public License 4488 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 4489 4490 /* This is needed to pick up the NAN macro on some systems. */ 4491 //#define _GNU_SOURCE 4492 4493 #ifndef INFINITY 4494 #ifdef HUGE_VAL 4495 #define INFINITY HUGE_VAL 4496 #else 4497 #define INFINITY (1.0 / 0.0) 4498 #endif 4499 #endif 4500 4501 #ifndef NAN 4502 #define NAN (0.0 / 0.0) 4503 #endif 4504 4505 static unsigned long get_field (const unsigned char *, 4506 enum floatformat_byteorders, 4507 unsigned int, 4508 unsigned int, 4509 unsigned int); 4510 static int floatformat_always_valid (const struct floatformat *fmt, 4511 const char *from); 4512 4513 static int 4514 floatformat_always_valid (const struct floatformat *fmt ATTRIBUTE_UNUSED, 4515 const char *from ATTRIBUTE_UNUSED) 4516 { 4517 return 1; 4518 } 4519 4520 /* The odds that CHAR_BIT will be anything but 8 are low enough that I'm not 4521 going to bother with trying to muck around with whether it is defined in 4522 a system header, what we do if not, etc. */ 4523 #define FLOATFORMAT_CHAR_BIT 8 4524 4525 /* floatformats for IEEE single and double, big and little endian. */ 4526 const struct floatformat floatformat_ieee_single_big = 4527 { 4528 floatformat_big, 32, 0, 1, 8, 127, 255, 9, 23, 4529 floatformat_intbit_no, 4530 "floatformat_ieee_single_big", 4531 floatformat_always_valid 4532 }; 4533 const struct floatformat floatformat_ieee_single_little = 4534 { 4535 floatformat_little, 32, 0, 1, 8, 127, 255, 9, 23, 4536 floatformat_intbit_no, 4537 "floatformat_ieee_single_little", 4538 floatformat_always_valid 4539 }; 4540 const struct floatformat floatformat_ieee_double_big = 4541 { 4542 floatformat_big, 64, 0, 1, 11, 1023, 2047, 12, 52, 4543 floatformat_intbit_no, 4544 "floatformat_ieee_double_big", 4545 floatformat_always_valid 4546 }; 4547 const struct floatformat floatformat_ieee_double_little = 4548 { 4549 floatformat_little, 64, 0, 1, 11, 1023, 2047, 12, 52, 4550 floatformat_intbit_no, 4551 "floatformat_ieee_double_little", 4552 floatformat_always_valid 4553 }; 4554 4555 /* floatformat for IEEE double, little endian byte order, with big endian word 4556 ordering, as on the ARM. */ 4557 4558 const struct floatformat floatformat_ieee_double_littlebyte_bigword = 4559 { 4560 floatformat_littlebyte_bigword, 64, 0, 1, 11, 1023, 2047, 12, 52, 4561 floatformat_intbit_no, 4562 "floatformat_ieee_double_littlebyte_bigword", 4563 floatformat_always_valid 4564 }; 4565 4566 static int floatformat_i387_ext_is_valid (const struct floatformat *fmt, const char *from); 4567 4568 static int 4569 floatformat_i387_ext_is_valid (const struct floatformat *fmt, const char *from) 4570 { 4571 /* In the i387 double-extended format, if the exponent is all ones, 4572 then the integer bit must be set. If the exponent is neither 0 4573 nor ~0, the intbit must also be set. Only if the exponent is 4574 zero can it be zero, and then it must be zero. */ 4575 unsigned long exponent, int_bit; 4576 const unsigned char *ufrom = (const unsigned char *) from; 4577 4578 exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize, 4579 fmt->exp_start, fmt->exp_len); 4580 int_bit = get_field (ufrom, fmt->byteorder, fmt->totalsize, 4581 fmt->man_start, 1); 4582 4583 if ((exponent == 0) != (int_bit == 0)) 4584 return 0; 4585 else 4586 return 1; 4587 } 4588 4589 const struct floatformat floatformat_i387_ext = 4590 { 4591 floatformat_little, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64, 4592 floatformat_intbit_yes, 4593 "floatformat_i387_ext", 4594 floatformat_i387_ext_is_valid 4595 }; 4596 const struct floatformat floatformat_m68881_ext = 4597 { 4598 /* Note that the bits from 16 to 31 are unused. */ 4599 floatformat_big, 96, 0, 1, 15, 0x3fff, 0x7fff, 32, 64, 4600 floatformat_intbit_yes, 4601 "floatformat_m68881_ext", 4602 floatformat_always_valid 4603 }; 4604 const struct floatformat floatformat_i960_ext = 4605 { 4606 /* Note that the bits from 0 to 15 are unused. */ 4607 floatformat_little, 96, 16, 17, 15, 0x3fff, 0x7fff, 32, 64, 4608 floatformat_intbit_yes, 4609 "floatformat_i960_ext", 4610 floatformat_always_valid 4611 }; 4612 const struct floatformat floatformat_m88110_ext = 4613 { 4614 floatformat_big, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64, 4615 floatformat_intbit_yes, 4616 "floatformat_m88110_ext", 4617 floatformat_always_valid 4618 }; 4619 const struct floatformat floatformat_m88110_harris_ext = 4620 { 4621 /* Harris uses raw format 128 bytes long, but the number is just an ieee 4622 double, and the last 64 bits are wasted. */ 4623 floatformat_big,128, 0, 1, 11, 0x3ff, 0x7ff, 12, 52, 4624 floatformat_intbit_no, 4625 "floatformat_m88110_ext_harris", 4626 floatformat_always_valid 4627 }; 4628 const struct floatformat floatformat_arm_ext_big = 4629 { 4630 /* Bits 1 to 16 are unused. */ 4631 floatformat_big, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64, 4632 floatformat_intbit_yes, 4633 "floatformat_arm_ext_big", 4634 floatformat_always_valid 4635 }; 4636 const struct floatformat floatformat_arm_ext_littlebyte_bigword = 4637 { 4638 /* Bits 1 to 16 are unused. */ 4639 floatformat_littlebyte_bigword, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64, 4640 floatformat_intbit_yes, 4641 "floatformat_arm_ext_littlebyte_bigword", 4642 floatformat_always_valid 4643 }; 4644 const struct floatformat floatformat_ia64_spill_big = 4645 { 4646 floatformat_big, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64, 4647 floatformat_intbit_yes, 4648 "floatformat_ia64_spill_big", 4649 floatformat_always_valid 4650 }; 4651 const struct floatformat floatformat_ia64_spill_little = 4652 { 4653 floatformat_little, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64, 4654 floatformat_intbit_yes, 4655 "floatformat_ia64_spill_little", 4656 floatformat_always_valid 4657 }; 4658 const struct floatformat floatformat_ia64_quad_big = 4659 { 4660 floatformat_big, 128, 0, 1, 15, 16383, 0x7fff, 16, 112, 4661 floatformat_intbit_no, 4662 "floatformat_ia64_quad_big", 4663 floatformat_always_valid 4664 }; 4665 const struct floatformat floatformat_ia64_quad_little = 4666 { 4667 floatformat_little, 128, 0, 1, 15, 16383, 0x7fff, 16, 112, 4668 floatformat_intbit_no, 4669 "floatformat_ia64_quad_little", 4670 floatformat_always_valid 4671 }; 4672 4673 /* Extract a field which starts at START and is LEN bits long. DATA and 4674 TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */ 4675 static unsigned long 4676 get_field (const unsigned char *data, enum floatformat_byteorders order, 4677 unsigned int total_len, unsigned int start, unsigned int len) 4678 { 4679 unsigned long result; 4680 unsigned int cur_byte; 4681 int cur_bitshift; 4682 4683 /* Start at the least significant part of the field. */ 4684 cur_byte = (start + len) / FLOATFORMAT_CHAR_BIT; 4685 if (order == floatformat_little) 4686 cur_byte = (total_len / FLOATFORMAT_CHAR_BIT) - cur_byte - 1; 4687 cur_bitshift = 4688 ((start + len) % FLOATFORMAT_CHAR_BIT) - FLOATFORMAT_CHAR_BIT; 4689 result = *(data + cur_byte) >> (-cur_bitshift); 4690 cur_bitshift += FLOATFORMAT_CHAR_BIT; 4691 if (order == floatformat_little) 4692 ++cur_byte; 4693 else 4694 --cur_byte; 4695 4696 /* Move towards the most significant part of the field. */ 4697 while ((unsigned int) cur_bitshift < len) 4698 { 4699 if (len - cur_bitshift < FLOATFORMAT_CHAR_BIT) 4700 /* This is the last byte; zero out the bits which are not part of 4701 this field. */ 4702 result |= 4703 (unsigned long)(*(data + cur_byte) 4704 & ((1 << (len - cur_bitshift)) - 1)) 4705 << cur_bitshift; 4706 else 4707 result |= (unsigned long)*(data + cur_byte) << cur_bitshift; 4708 cur_bitshift += FLOATFORMAT_CHAR_BIT; 4709 if (order == floatformat_little) 4710 ++cur_byte; 4711 else 4712 --cur_byte; 4713 } 4714 return result; 4715 } 4716 4717 /* Convert from FMT to a double. 4718 FROM is the address of the extended float. 4719 Store the double in *TO. */ 4720 4721 void 4722 floatformat_to_double (const struct floatformat *fmt, 4723 const char *from, double *to) 4724 { 4725 const unsigned char *ufrom = (const unsigned char *)from; 4726 double dto; 4727 long exponent; 4728 unsigned long mant; 4729 unsigned int mant_bits, mant_off; 4730 int mant_bits_left; 4731 int special_exponent; /* It's a NaN, denorm or zero */ 4732 4733 exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize, 4734 fmt->exp_start, fmt->exp_len); 4735 4736 /* If the exponent indicates a NaN, we don't have information to 4737 decide what to do. So we handle it like IEEE, except that we 4738 don't try to preserve the type of NaN. FIXME. */ 4739 if ((unsigned long) exponent == fmt->exp_nan) 4740 { 4741 int nan; 4742 4743 mant_off = fmt->man_start; 4744 mant_bits_left = fmt->man_len; 4745 nan = 0; 4746 while (mant_bits_left > 0) 4747 { 4748 mant_bits = MIN(mant_bits_left, 32); 4749 4750 if (get_field (ufrom, fmt->byteorder, fmt->totalsize, 4751 mant_off, mant_bits) != 0) 4752 { 4753 /* This is a NaN. */ 4754 nan = 1; 4755 break; 4756 } 4757 4758 mant_off += mant_bits; 4759 mant_bits_left -= mant_bits; 4760 } 4761 4762 /* On certain systems (such as GNU/Linux), the use of the 4763 INFINITY macro below may generate a warning that can not be 4764 silenced due to a bug in GCC (PR preprocessor/11931). The 4765 preprocessor fails to recognise the __extension__ keyword in 4766 conjunction with the GNU/C99 extension for hexadecimal 4767 floating point constants and will issue a warning when 4768 compiling with -pedantic. */ 4769 if (nan) 4770 dto = NAN; 4771 else 4772 dto = INFINITY; 4773 4774 if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1)) 4775 dto = -dto; 4776 4777 *to = dto; 4778 4779 return; 4780 } 4781 4782 mant_bits_left = fmt->man_len; 4783 mant_off = fmt->man_start; 4784 dto = 0.0; 4785 4786 special_exponent = exponent == 0 || (unsigned long) exponent == fmt->exp_nan; 4787 4788 /* Don't bias zero's, denorms or NaNs. */ 4789 if (!special_exponent) 4790 exponent -= fmt->exp_bias; 4791 4792 /* Build the result algebraically. Might go infinite, underflow, etc; 4793 who cares. */ 4794 4795 /* If this format uses a hidden bit, explicitly add it in now. Otherwise, 4796 increment the exponent by one to account for the integer bit. */ 4797 4798 if (!special_exponent) 4799 { 4800 if (fmt->intbit == floatformat_intbit_no) 4801 dto = ldexp (1.0, exponent); 4802 else 4803 exponent++; 4804 } 4805 4806 while (mant_bits_left > 0) 4807 { 4808 mant_bits = MIN(mant_bits_left, 32); 4809 4810 mant = get_field (ufrom, fmt->byteorder, fmt->totalsize, 4811 mant_off, mant_bits); 4812 4813 /* Handle denormalized numbers. FIXME: What should we do for 4814 non-IEEE formats? */ 4815 if (exponent == 0 && mant != 0) 4816 dto += ldexp ((double)mant, 4817 (- fmt->exp_bias 4818 - mant_bits 4819 - (mant_off - fmt->man_start) 4820 + 1)); 4821 else 4822 dto += ldexp ((double)mant, exponent - mant_bits); 4823 if (exponent != 0) 4824 exponent -= mant_bits; 4825 mant_off += mant_bits; 4826 mant_bits_left -= mant_bits; 4827 } 4828 4829 /* Negate it if negative. */ 4830 if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1)) 4831 dto = -dto; 4832 *to = dto; 4833 } 4834 4835 static void put_field (unsigned char *, enum floatformat_byteorders, 4836 unsigned int, 4837 unsigned int, 4838 unsigned int, 4839 unsigned long); 4840 4841 /* Set a field which starts at START and is LEN bits long. DATA and 4842 TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */ 4843 static void 4844 put_field (unsigned char *data, enum floatformat_byteorders order, 4845 unsigned int total_len, unsigned int start, unsigned int len, 4846 unsigned long stuff_to_put) 4847 { 4848 unsigned int cur_byte; 4849 int cur_bitshift; 4850 4851 /* Start at the least significant part of the field. */ 4852 cur_byte = (start + len) / FLOATFORMAT_CHAR_BIT; 4853 if (order == floatformat_little) 4854 cur_byte = (total_len / FLOATFORMAT_CHAR_BIT) - cur_byte - 1; 4855 cur_bitshift = 4856 ((start + len) % FLOATFORMAT_CHAR_BIT) - FLOATFORMAT_CHAR_BIT; 4857 *(data + cur_byte) &= 4858 ~(((1 << ((start + len) % FLOATFORMAT_CHAR_BIT)) - 1) << (-cur_bitshift)); 4859 *(data + cur_byte) |= 4860 (stuff_to_put & ((1 << FLOATFORMAT_CHAR_BIT) - 1)) << (-cur_bitshift); 4861 cur_bitshift += FLOATFORMAT_CHAR_BIT; 4862 if (order == floatformat_little) 4863 ++cur_byte; 4864 else 4865 --cur_byte; 4866 4867 /* Move towards the most significant part of the field. */ 4868 while ((unsigned int) cur_bitshift < len) 4869 { 4870 if (len - cur_bitshift < FLOATFORMAT_CHAR_BIT) 4871 { 4872 /* This is the last byte. */ 4873 *(data + cur_byte) &= 4874 ~((1 << (len - cur_bitshift)) - 1); 4875 *(data + cur_byte) |= (stuff_to_put >> cur_bitshift); 4876 } 4877 else 4878 *(data + cur_byte) = ((stuff_to_put >> cur_bitshift) 4879 & ((1 << FLOATFORMAT_CHAR_BIT) - 1)); 4880 cur_bitshift += FLOATFORMAT_CHAR_BIT; 4881 if (order == floatformat_little) 4882 ++cur_byte; 4883 else 4884 --cur_byte; 4885 } 4886 } 4887 4888 /* The converse: convert the double *FROM to an extended float 4889 and store where TO points. Neither FROM nor TO have any alignment 4890 restrictions. */ 4891 4892 void 4893 floatformat_from_double (const struct floatformat *fmt, 4894 const double *from, char *to) 4895 { 4896 double dfrom; 4897 int exponent; 4898 double mant; 4899 unsigned int mant_bits, mant_off; 4900 int mant_bits_left; 4901 unsigned char *uto = (unsigned char *)to; 4902 4903 dfrom = *from; 4904 memset (uto, 0, fmt->totalsize / FLOATFORMAT_CHAR_BIT); 4905 4906 /* If negative, set the sign bit. */ 4907 if (dfrom < 0) 4908 { 4909 put_field (uto, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1, 1); 4910 dfrom = -dfrom; 4911 } 4912 4913 if (dfrom == 0) 4914 { 4915 /* 0.0. */ 4916 return; 4917 } 4918 4919 if (dfrom != dfrom) 4920 { 4921 /* NaN. */ 4922 put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, 4923 fmt->exp_len, fmt->exp_nan); 4924 /* Be sure it's not infinity, but NaN value is irrelevant. */ 4925 put_field (uto, fmt->byteorder, fmt->totalsize, fmt->man_start, 4926 32, 1); 4927 return; 4928 } 4929 4930 if (dfrom + dfrom == dfrom) 4931 { 4932 /* This can only happen for an infinite value (or zero, which we 4933 already handled above). */ 4934 put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, 4935 fmt->exp_len, fmt->exp_nan); 4936 return; 4937 } 4938 4939 mant = frexp (dfrom, &exponent); 4940 if (exponent + fmt->exp_bias - 1 > 0) 4941 put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, 4942 fmt->exp_len, exponent + fmt->exp_bias - 1); 4943 else 4944 { 4945 /* Handle a denormalized number. FIXME: What should we do for 4946 non-IEEE formats? */ 4947 put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start, 4948 fmt->exp_len, 0); 4949 mant = ldexp (mant, exponent + fmt->exp_bias - 1); 4950 } 4951 4952 mant_bits_left = fmt->man_len; 4953 mant_off = fmt->man_start; 4954 while (mant_bits_left > 0) 4955 { 4956 unsigned long mant_long; 4957 mant_bits = mant_bits_left < 32 ? mant_bits_left : 32; 4958 4959 mant *= 4294967296.0; 4960 mant_long = (unsigned long)mant; 4961 mant -= mant_long; 4962 4963 /* If the integer bit is implicit, and we are not creating a 4964 denormalized number, then we need to discard it. */ 4965 if ((unsigned int) mant_bits_left == fmt->man_len 4966 && fmt->intbit == floatformat_intbit_no 4967 && exponent + fmt->exp_bias - 1 > 0) 4968 { 4969 mant_long &= 0x7fffffff; 4970 mant_bits -= 1; 4971 } 4972 else if (mant_bits < 32) 4973 { 4974 /* The bits we want are in the most significant MANT_BITS bits of 4975 mant_long. Move them to the least significant. */ 4976 mant_long >>= 32 - mant_bits; 4977 } 4978 4979 put_field (uto, fmt->byteorder, fmt->totalsize, 4980 mant_off, mant_bits, mant_long); 4981 mant_off += mant_bits; 4982 mant_bits_left -= mant_bits; 4983 } 4984 } 4985 4986 /* Return non-zero iff the data at FROM is a valid number in format FMT. */ 4987 4988 int 4989 floatformat_is_valid (const struct floatformat *fmt, const char *from) 4990 { 4991 return fmt->is_valid (fmt, from); 4992 } 4993 4994 4995 #ifdef IEEE_DEBUG 4996 4997 /* This is to be run on a host which uses IEEE floating point. */ 4998 4999 void 5000 ieee_test (double n) 5001 { 5002 double result; 5003 5004 floatformat_to_double (&floatformat_ieee_double_little, (char *) &n, 5005 &result); 5006 if ((n != result && (! isnan (n) || ! isnan (result))) 5007 || (n < 0 && result >= 0) 5008 || (n >= 0 && result < 0)) 5009 printf ("Differ(to): %.20g -> %.20g\n", n, result); 5010 5011 floatformat_from_double (&floatformat_ieee_double_little, &n, 5012 (char *) &result); 5013 if ((n != result && (! isnan (n) || ! isnan (result))) 5014 || (n < 0 && result >= 0) 5015 || (n >= 0 && result < 0)) 5016 printf ("Differ(from): %.20g -> %.20g\n", n, result); 5017 5018 #if 0 5019 { 5020 char exten[16]; 5021 5022 floatformat_from_double (&floatformat_m68881_ext, &n, exten); 5023 floatformat_to_double (&floatformat_m68881_ext, exten, &result); 5024 if (n != result) 5025 printf ("Differ(to+from): %.20g -> %.20g\n", n, result); 5026 } 5027 #endif 5028 5029 #if IEEE_DEBUG > 1 5030 /* This is to be run on a host which uses 68881 format. */ 5031 { 5032 long double ex = *(long double *)exten; 5033 if (ex != n) 5034 printf ("Differ(from vs. extended): %.20g\n", n); 5035 } 5036 #endif 5037 } 5038 5039 int 5040 main (void) 5041 { 5042 ieee_test (0.0); 5043 ieee_test (0.5); 5044 ieee_test (256.0); 5045 ieee_test (0.12345); 5046 ieee_test (234235.78907234); 5047 ieee_test (-512.0); 5048 ieee_test (-0.004321); 5049 ieee_test (1.2E-70); 5050 ieee_test (1.2E-316); 5051 ieee_test (4.9406564584124654E-324); 5052 ieee_test (- 4.9406564584124654E-324); 5053 ieee_test (- 0.0); 5054 ieee_test (- INFINITY); 5055 ieee_test (- NAN); 5056 ieee_test (INFINITY); 5057 ieee_test (NAN); 5058 return 0; 5059 } 5060 #endif 5061 /* **** End of floatformat.c */ 5062