1 /* Disassembler code for CRIS. 2 Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc. 3 Contributed by Axis Communications AB, Lund, Sweden. 4 Written by Hans-Peter Nilsson. 5 6 This file is part of the GNU binutils and GDB, the GNU debugger. 7 8 This program is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published by the 10 Free Software Foundation; either version 2, or (at your option) any later 11 version. 12 13 This program is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 20 21 #include "qemu-common.h" 22 #include "disas/bfd.h" 23 //#include "sysdep.h" 24 #include "target-cris/opcode-cris.h" 25 //#include "libiberty.h" 26 27 #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0) 28 29 /* cris-opc.c -- Table of opcodes for the CRIS processor. 30 Copyright 2000, 2001, 2004 Free Software Foundation, Inc. 31 Contributed by Axis Communications AB, Lund, Sweden. 32 Originally written for GAS 1.38.1 by Mikael Asker. 33 Reorganized by Hans-Peter Nilsson. 34 35 This file is part of GAS, GDB and the GNU binutils. 36 37 GAS, GDB, and GNU binutils is free software; you can redistribute it 38 and/or modify it under the terms of the GNU General Public License as 39 published by the Free Software Foundation; either version 2, or (at your 40 option) any later version. 41 42 GAS, GDB, and GNU binutils are distributed in the hope that they will be 43 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of 44 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 45 GNU General Public License for more details. 46 47 You should have received a copy of the GNU General Public License 48 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 49 50 #ifndef NULL 51 #define NULL (0) 52 #endif 53 54 /* This table isn't used for CRISv32 and the size of immediate operands. */ 55 const struct cris_spec_reg 56 cris_spec_regs[] = 57 { 58 {"bz", 0, 1, cris_ver_v32p, NULL}, 59 {"p0", 0, 1, 0, NULL}, 60 {"vr", 1, 1, 0, NULL}, 61 {"p1", 1, 1, 0, NULL}, 62 {"pid", 2, 1, cris_ver_v32p, NULL}, 63 {"p2", 2, 1, cris_ver_v32p, NULL}, 64 {"p2", 2, 1, cris_ver_warning, NULL}, 65 {"srs", 3, 1, cris_ver_v32p, NULL}, 66 {"p3", 3, 1, cris_ver_v32p, NULL}, 67 {"p3", 3, 1, cris_ver_warning, NULL}, 68 {"wz", 4, 2, cris_ver_v32p, NULL}, 69 {"p4", 4, 2, 0, NULL}, 70 {"ccr", 5, 2, cris_ver_v0_10, NULL}, 71 {"exs", 5, 4, cris_ver_v32p, NULL}, 72 {"p5", 5, 2, cris_ver_v0_10, NULL}, 73 {"p5", 5, 4, cris_ver_v32p, NULL}, 74 {"dcr0",6, 2, cris_ver_v0_3, NULL}, 75 {"eda", 6, 4, cris_ver_v32p, NULL}, 76 {"p6", 6, 2, cris_ver_v0_3, NULL}, 77 {"p6", 6, 4, cris_ver_v32p, NULL}, 78 {"dcr1/mof", 7, 4, cris_ver_v10p, 79 "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"}, 80 {"dcr1/mof", 7, 2, cris_ver_v0_3, 81 "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"}, 82 {"mof", 7, 4, cris_ver_v10p, NULL}, 83 {"dcr1",7, 2, cris_ver_v0_3, NULL}, 84 {"p7", 7, 4, cris_ver_v10p, NULL}, 85 {"p7", 7, 2, cris_ver_v0_3, NULL}, 86 {"dz", 8, 4, cris_ver_v32p, NULL}, 87 {"p8", 8, 4, 0, NULL}, 88 {"ibr", 9, 4, cris_ver_v0_10, NULL}, 89 {"ebp", 9, 4, cris_ver_v32p, NULL}, 90 {"p9", 9, 4, 0, NULL}, 91 {"irp", 10, 4, cris_ver_v0_10, NULL}, 92 {"erp", 10, 4, cris_ver_v32p, NULL}, 93 {"p10", 10, 4, 0, NULL}, 94 {"srp", 11, 4, 0, NULL}, 95 {"p11", 11, 4, 0, NULL}, 96 /* For disassembly use only. Accept at assembly with a warning. */ 97 {"bar/dtp0", 12, 4, cris_ver_warning, 98 "Ambiguous register `bar/dtp0' specified"}, 99 {"nrp", 12, 4, cris_ver_v32p, NULL}, 100 {"bar", 12, 4, cris_ver_v8_10, NULL}, 101 {"dtp0",12, 4, cris_ver_v0_3, NULL}, 102 {"p12", 12, 4, 0, NULL}, 103 /* For disassembly use only. Accept at assembly with a warning. */ 104 {"dccr/dtp1",13, 4, cris_ver_warning, 105 "Ambiguous register `dccr/dtp1' specified"}, 106 {"ccs", 13, 4, cris_ver_v32p, NULL}, 107 {"dccr",13, 4, cris_ver_v8_10, NULL}, 108 {"dtp1",13, 4, cris_ver_v0_3, NULL}, 109 {"p13", 13, 4, 0, NULL}, 110 {"brp", 14, 4, cris_ver_v3_10, NULL}, 111 {"usp", 14, 4, cris_ver_v32p, NULL}, 112 {"p14", 14, 4, cris_ver_v3p, NULL}, 113 {"usp", 15, 4, cris_ver_v10, NULL}, 114 {"spc", 15, 4, cris_ver_v32p, NULL}, 115 {"p15", 15, 4, cris_ver_v10p, NULL}, 116 {NULL, 0, 0, cris_ver_version_all, NULL} 117 }; 118 119 /* Add version specifiers to this table when necessary. 120 The (now) regular coding of register names suggests a simpler 121 implementation. */ 122 const struct cris_support_reg cris_support_regs[] = 123 { 124 {"s0", 0}, 125 {"s1", 1}, 126 {"s2", 2}, 127 {"s3", 3}, 128 {"s4", 4}, 129 {"s5", 5}, 130 {"s6", 6}, 131 {"s7", 7}, 132 {"s8", 8}, 133 {"s9", 9}, 134 {"s10", 10}, 135 {"s11", 11}, 136 {"s12", 12}, 137 {"s13", 13}, 138 {"s14", 14}, 139 {"s15", 15}, 140 {NULL, 0} 141 }; 142 143 /* All CRIS opcodes are 16 bits. 144 145 - The match component is a mask saying which bits must match a 146 particular opcode in order for an instruction to be an instance 147 of that opcode. 148 149 - The args component is a string containing characters symbolically 150 matching the operands of an instruction. Used for both assembly 151 and disassembly. 152 153 Operand-matching characters: 154 [ ] , space 155 Verbatim. 156 A The string "ACR" (case-insensitive). 157 B Not really an operand. It causes a "BDAP -size,SP" prefix to be 158 output for the PUSH alias-instructions and recognizes a push- 159 prefix at disassembly. This letter isn't recognized for v32. 160 Must be followed by a R or P letter. 161 ! Non-match pattern, will not match if there's a prefix insn. 162 b Non-matching operand, used for branches with 16-bit 163 displacement. Only recognized by the disassembler. 164 c 5-bit unsigned immediate in bits <4:0>. 165 C 4-bit unsigned immediate in bits <3:0>. 166 d At assembly, optionally (as in put other cases before this one) 167 ".d" or ".D" at the start of the operands, followed by one space 168 character. At disassembly, nothing. 169 D General register in bits <15:12> and <3:0>. 170 f List of flags in bits <15:12> and <3:0>. 171 i 6-bit signed immediate in bits <5:0>. 172 I 6-bit unsigned immediate in bits <5:0>. 173 M Size modifier (B, W or D) for CLEAR instructions. 174 m Size modifier (B, W or D) in bits <5:4> 175 N A 32-bit dword, like in the difference between s and y. 176 This has no effect on bits in the opcode. Can also be expressed 177 as "[pc+]" in input. 178 n As N, but PC-relative (to the start of the instruction). 179 o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit 180 branch instructions. 181 O [-128..127] offset in bits <7:0>. Also matches a comma and a 182 general register after the expression, in bits <15:12>. Used 183 only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode). 184 P Special register in bits <15:12>. 185 p Indicates that the insn is a prefix insn. Must be first 186 character. 187 Q As O, but don't relax; force an 8-bit offset. 188 R General register in bits <15:12>. 189 r General register in bits <3:0>. 190 S Source operand in bit <10> and a prefix; a 3-operand prefix 191 without side-effect. 192 s Source operand in bits <10> and <3:0>, optionally with a 193 side-effect prefix, except [pc] (the name, not R15 as in ACR) 194 isn't allowed for v32 and higher. 195 T Support register in bits <15:12>. 196 u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>. 197 U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC. 198 Not recognized at disassembly. 199 x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>. 200 y Like 's' but do not allow an integer at assembly. 201 Y The difference s-y; only an integer is allowed. 202 z Size modifier (B or W) in bit <4>. */ 203 204 205 /* Please note the order of the opcodes in this table is significant. 206 The assembler requires that all instances of the same mnemonic must 207 be consecutive. If they aren't, the assembler might not recognize 208 them, or may indicate an internal error. 209 210 The disassembler should not normally care about the order of the 211 opcodes, but will prefer an earlier alternative if the "match-score" 212 (see cris-dis.c) is computed as equal. 213 214 It should not be significant for proper execution that this table is 215 in alphabetical order, but please follow that convention for an easy 216 overview. */ 217 218 const struct cris_opcode 219 cris_opcodes[] = 220 { 221 {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0, 222 cris_abs_op}, 223 224 {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0, 225 cris_reg_mode_add_sub_cmp_and_or_move_op}, 226 227 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0, 228 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 229 230 {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, 231 cris_ver_v0_10, 232 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 233 234 {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, 235 cris_ver_v0_10, 236 cris_three_operand_add_sub_cmp_and_or_op}, 237 238 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 239 cris_ver_v32p, 240 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 241 242 {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32, 243 cris_ver_v32p, 244 cris_not_implemented_op}, 245 246 {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32, 247 cris_ver_v32p, 248 cris_not_implemented_op}, 249 250 {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE, 251 cris_ver_v32p, 252 cris_addi_op}, 253 254 {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0, 255 cris_addi_op}, 256 257 /* This collates after "addo", but we want to disassemble as "addoq", 258 not "addo". */ 259 {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE, 260 cris_ver_v32p, 261 cris_not_implemented_op}, 262 263 {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED, 264 cris_ver_v32p, 265 cris_not_implemented_op}, 266 267 /* This must be located after the insn above, lest we misinterpret 268 "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a 269 parser bug. */ 270 {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE, 271 cris_ver_v32p, 272 cris_not_implemented_op}, 273 274 {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0, 275 cris_quick_mode_add_sub_op}, 276 277 {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0, 278 cris_reg_mode_add_sub_cmp_and_or_move_op}, 279 280 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ 281 {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0, 282 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 283 284 {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, 285 cris_ver_v0_10, 286 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 287 288 {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, 289 cris_ver_v0_10, 290 cris_three_operand_add_sub_cmp_and_or_op}, 291 292 {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0, 293 cris_reg_mode_add_sub_cmp_and_or_move_op}, 294 295 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ 296 {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0, 297 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 298 299 {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, 300 cris_ver_v0_10, 301 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 302 303 {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, 304 cris_ver_v0_10, 305 cris_three_operand_add_sub_cmp_and_or_op}, 306 307 {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0, 308 cris_reg_mode_add_sub_cmp_and_or_move_op}, 309 310 {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0, 311 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 312 313 {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, 314 cris_ver_v0_10, 315 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 316 317 {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, 318 cris_ver_v0_10, 319 cris_three_operand_add_sub_cmp_and_or_op}, 320 321 {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0, 322 cris_quick_mode_and_cmp_move_or_op}, 323 324 {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0, 325 cris_asr_op}, 326 327 {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0, 328 cris_asrq_op}, 329 330 {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0, 331 cris_ax_ei_setf_op}, 332 333 /* FIXME: Should use branch #defines. */ 334 {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0, 335 cris_sixteen_bit_offset_branch_op}, 336 337 {"ba", 338 BA_QUICK_OPCODE, 339 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0, 340 cris_eight_bit_offset_branch_op}, 341 342 /* Needs to come after the usual "ba o", which might be relaxed to 343 this one. */ 344 {"ba", BA_DWORD_OPCODE, 345 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32, 346 cris_ver_v32p, 347 cris_none_reg_mode_jump_op}, 348 349 {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32, 350 cris_ver_v32p, 351 cris_none_reg_mode_jump_op}, 352 353 {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32, 354 cris_ver_v32p, 355 cris_none_reg_mode_jump_op}, 356 357 {"bcc", 358 BRANCH_QUICK_OPCODE+CC_CC*0x1000, 359 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0, 360 cris_eight_bit_offset_branch_op}, 361 362 {"bcs", 363 BRANCH_QUICK_OPCODE+CC_CS*0x1000, 364 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0, 365 cris_eight_bit_offset_branch_op}, 366 367 {"bdap", 368 BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED, 369 cris_ver_v0_10, 370 cris_bdap_prefix}, 371 372 {"bdap", 373 BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, 374 cris_ver_v0_10, 375 cris_quick_mode_bdap_prefix}, 376 377 {"beq", 378 BRANCH_QUICK_OPCODE+CC_EQ*0x1000, 379 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0, 380 cris_eight_bit_offset_branch_op}, 381 382 /* This is deliberately put before "bext" to trump it, even though not 383 in alphabetical order, since we don't do excluding version checks 384 for v0..v10. */ 385 {"bwf", 386 BRANCH_QUICK_OPCODE+CC_EXT*0x1000, 387 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, 388 cris_ver_v10, 389 cris_eight_bit_offset_branch_op}, 390 391 {"bext", 392 BRANCH_QUICK_OPCODE+CC_EXT*0x1000, 393 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, 394 cris_ver_v0_3, 395 cris_eight_bit_offset_branch_op}, 396 397 {"bge", 398 BRANCH_QUICK_OPCODE+CC_GE*0x1000, 399 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0, 400 cris_eight_bit_offset_branch_op}, 401 402 {"bgt", 403 BRANCH_QUICK_OPCODE+CC_GT*0x1000, 404 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0, 405 cris_eight_bit_offset_branch_op}, 406 407 {"bhi", 408 BRANCH_QUICK_OPCODE+CC_HI*0x1000, 409 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0, 410 cris_eight_bit_offset_branch_op}, 411 412 {"bhs", 413 BRANCH_QUICK_OPCODE+CC_HS*0x1000, 414 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0, 415 cris_eight_bit_offset_branch_op}, 416 417 {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, 418 cris_ver_v0_10, 419 cris_biap_prefix}, 420 421 {"ble", 422 BRANCH_QUICK_OPCODE+CC_LE*0x1000, 423 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0, 424 cris_eight_bit_offset_branch_op}, 425 426 {"blo", 427 BRANCH_QUICK_OPCODE+CC_LO*0x1000, 428 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0, 429 cris_eight_bit_offset_branch_op}, 430 431 {"bls", 432 BRANCH_QUICK_OPCODE+CC_LS*0x1000, 433 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0, 434 cris_eight_bit_offset_branch_op}, 435 436 {"blt", 437 BRANCH_QUICK_OPCODE+CC_LT*0x1000, 438 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0, 439 cris_eight_bit_offset_branch_op}, 440 441 {"bmi", 442 BRANCH_QUICK_OPCODE+CC_MI*0x1000, 443 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0, 444 cris_eight_bit_offset_branch_op}, 445 446 {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32, 447 cris_ver_sim_v0_10, 448 cris_not_implemented_op}, 449 450 {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE, 451 cris_ver_sim_v0_10, 452 cris_not_implemented_op}, 453 454 {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE, 455 cris_ver_sim_v0_10, 456 cris_not_implemented_op}, 457 458 {"bne", 459 BRANCH_QUICK_OPCODE+CC_NE*0x1000, 460 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0, 461 cris_eight_bit_offset_branch_op}, 462 463 {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0, 464 cris_two_operand_bound_op}, 465 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ 466 {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, 467 cris_ver_v0_10, 468 cris_two_operand_bound_op}, 469 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ 470 {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0, 471 cris_two_operand_bound_op}, 472 {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, 473 cris_ver_v0_10, 474 cris_two_operand_bound_op}, 475 {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, 476 cris_ver_v0_10, 477 cris_three_operand_bound_op}, 478 479 {"bpl", 480 BRANCH_QUICK_OPCODE+CC_PL*0x1000, 481 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0, 482 cris_eight_bit_offset_branch_op}, 483 484 {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE, 485 cris_ver_v3p, 486 cris_break_op}, 487 488 {"bsb", 489 BRANCH_QUICK_OPCODE+CC_EXT*0x1000, 490 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, 491 cris_ver_v32p, 492 cris_eight_bit_offset_branch_op}, 493 494 {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32, 495 cris_ver_v32p, 496 cris_none_reg_mode_jump_op}, 497 498 {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32, 499 cris_ver_v32p, 500 cris_none_reg_mode_jump_op}, 501 502 {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32, 503 cris_ver_warning, 504 cris_not_implemented_op}, 505 506 {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE, 507 cris_ver_warning, 508 cris_not_implemented_op}, 509 510 {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE, 511 cris_ver_warning, 512 cris_not_implemented_op}, 513 514 {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0, 515 cris_btst_nop_op}, 516 {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0, 517 cris_btst_nop_op}, 518 519 {"bvc", 520 BRANCH_QUICK_OPCODE+CC_VC*0x1000, 521 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0, 522 cris_eight_bit_offset_branch_op}, 523 524 {"bvs", 525 BRANCH_QUICK_OPCODE+CC_VS*0x1000, 526 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0, 527 cris_eight_bit_offset_branch_op}, 528 529 {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0, 530 cris_reg_mode_clear_op}, 531 532 {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0, 533 cris_none_reg_mode_clear_test_op}, 534 535 {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, 536 cris_ver_v0_10, 537 cris_none_reg_mode_clear_test_op}, 538 539 {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0, 540 cris_clearf_di_op}, 541 542 {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0, 543 cris_reg_mode_add_sub_cmp_and_or_move_op}, 544 545 {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0, 546 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 547 548 {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, 549 cris_ver_v0_10, 550 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 551 552 {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0, 553 cris_quick_mode_and_cmp_move_or_op}, 554 555 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ 556 {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0, 557 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 558 559 {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, 560 cris_ver_v0_10, 561 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 562 563 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ 564 {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0, 565 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 566 567 {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, 568 cris_ver_v0_10, 569 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 570 571 {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0, 572 cris_clearf_di_op}, 573 574 {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, 575 cris_ver_v0_10, 576 cris_dip_prefix}, 577 578 {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0, 579 cris_not_implemented_op}, 580 581 {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0, 582 cris_dstep_logshift_mstep_neg_not_op}, 583 584 {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0, 585 cris_ax_ei_setf_op}, 586 587 {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE, 588 cris_ver_v32p, 589 cris_not_implemented_op}, 590 591 {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE, 592 cris_ver_v32p, 593 cris_not_implemented_op}, 594 595 {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE, 596 cris_ver_v32p, 597 cris_not_implemented_op}, 598 599 {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE, 600 cris_ver_v32p, 601 cris_not_implemented_op}, 602 603 {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE, 604 cris_ver_v32p, 605 cris_not_implemented_op}, 606 607 {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE, 608 cris_ver_v32p, 609 cris_reg_mode_jump_op}, 610 611 {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32, 612 cris_ver_v32p, 613 cris_reg_mode_jump_op}, 614 615 {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE, 616 cris_ver_v32p, 617 cris_reg_mode_jump_op}, 618 619 {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32, 620 cris_ver_v32p, 621 cris_reg_mode_jump_op}, 622 623 {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE, 624 cris_ver_v8_10, 625 cris_reg_mode_jump_op}, 626 627 {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32, 628 cris_ver_v8_10, 629 cris_none_reg_mode_jump_op}, 630 631 {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE, 632 cris_ver_v8_10, 633 cris_none_reg_mode_jump_op}, 634 635 {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, 636 cris_ver_v8_10, 637 cris_reg_mode_jump_op}, 638 639 {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, 640 cris_ver_v8_10, 641 cris_none_reg_mode_jump_op}, 642 643 {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, 644 cris_ver_v8_10, 645 cris_none_reg_mode_jump_op}, 646 647 {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE, 648 cris_ver_v8_10, 649 cris_reg_mode_jump_op}, 650 651 {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32, 652 cris_ver_v8_10, 653 cris_none_reg_mode_jump_op}, 654 655 {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE, 656 cris_ver_v8_10, 657 cris_none_reg_mode_jump_op}, 658 659 {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0, 660 cris_reg_mode_jump_op}, 661 662 {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, 663 cris_ver_v0_10, 664 cris_none_reg_mode_jump_op}, 665 666 {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32, 667 cris_ver_v32p, 668 cris_none_reg_mode_jump_op}, 669 670 {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, 671 cris_ver_v0_10, 672 cris_none_reg_mode_jump_op}, 673 674 {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE, 675 cris_ver_v8_10, 676 cris_reg_mode_jump_op}, 677 678 {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32, 679 cris_ver_v8_10, 680 cris_none_reg_mode_jump_op}, 681 682 {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE, 683 cris_ver_v8_10, 684 cris_none_reg_mode_jump_op}, 685 686 {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE, 687 cris_ver_v32p, 688 cris_reg_mode_jump_op}, 689 690 {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32, 691 cris_ver_v32p, 692 cris_reg_mode_jump_op}, 693 694 {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0, 695 cris_reg_mode_jump_op}, 696 697 {"jump", 698 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, 699 cris_ver_v0_10, 700 cris_none_reg_mode_jump_op}, 701 702 {"jump", 703 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, 704 cris_ver_v0_10, 705 cris_none_reg_mode_jump_op}, 706 707 {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE, 708 cris_ver_v32p, 709 cris_none_reg_mode_jump_op}, 710 711 {"jump", 712 JUMP_PC_INCR_OPCODE_V32, 713 (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32, 714 cris_ver_v32p, 715 cris_none_reg_mode_jump_op}, 716 717 {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32, 718 cris_ver_v10, 719 cris_none_reg_mode_jump_op}, 720 721 {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE, 722 cris_ver_v10, 723 cris_none_reg_mode_jump_op}, 724 725 {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE, 726 cris_ver_v32p, 727 cris_not_implemented_op}, 728 729 {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32, 730 cris_ver_v32p, 731 cris_not_implemented_op}, 732 733 {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE, 734 cris_ver_v32p, 735 cris_addi_op}, 736 737 {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0, 738 cris_dstep_logshift_mstep_neg_not_op}, 739 740 {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0, 741 cris_dstep_logshift_mstep_neg_not_op}, 742 743 {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0, 744 cris_dstep_logshift_mstep_neg_not_op}, 745 746 {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0, 747 cris_dstep_logshift_mstep_neg_not_op}, 748 749 {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE, 750 cris_ver_v3p, 751 cris_not_implemented_op}, 752 753 {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE, 754 cris_ver_v32p, 755 cris_not_implemented_op}, 756 757 {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0, 758 cris_reg_mode_add_sub_cmp_and_or_move_op}, 759 760 {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0, 761 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 762 763 {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, 764 cris_ver_v0_10, 765 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 766 767 {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0, 768 cris_move_to_preg_op}, 769 770 {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0, 771 cris_reg_mode_move_from_preg_op}, 772 773 {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0, 774 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 775 776 {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, 777 cris_ver_v0_10, 778 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 779 780 {"move", 781 MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS, 782 "s,P", 0, SIZE_SPEC_REG, 0, 783 cris_move_to_preg_op}, 784 785 {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, 786 cris_ver_v0_10, 787 cris_move_to_preg_op}, 788 789 {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0, 790 cris_none_reg_mode_move_from_preg_op}, 791 792 {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, 793 cris_ver_v0_10, 794 cris_none_reg_mode_move_from_preg_op}, 795 796 {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE, 797 cris_ver_v32p, 798 cris_not_implemented_op}, 799 800 {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE, 801 cris_ver_v32p, 802 cris_not_implemented_op}, 803 804 {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0, 805 cris_move_reg_to_mem_movem_op}, 806 807 {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, 808 cris_ver_v0_10, 809 cris_move_reg_to_mem_movem_op}, 810 811 {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0, 812 cris_move_mem_to_reg_movem_op}, 813 814 {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, 815 cris_ver_v0_10, 816 cris_move_mem_to_reg_movem_op}, 817 818 {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0, 819 cris_quick_mode_and_cmp_move_or_op}, 820 821 {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0, 822 cris_reg_mode_add_sub_cmp_and_or_move_op}, 823 824 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ 825 {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0, 826 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 827 828 {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, 829 cris_ver_v0_10, 830 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 831 832 {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0, 833 cris_reg_mode_add_sub_cmp_and_or_move_op}, 834 835 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ 836 {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0, 837 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 838 839 {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, 840 cris_ver_v0_10, 841 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 842 843 {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, 844 cris_ver_v0_10, 845 cris_dstep_logshift_mstep_neg_not_op}, 846 847 {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE, 848 cris_ver_v10p, 849 cris_muls_op}, 850 851 {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE, 852 cris_ver_v10p, 853 cris_mulu_op}, 854 855 {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0, 856 cris_dstep_logshift_mstep_neg_not_op}, 857 858 {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, 859 cris_ver_v0_10, 860 cris_btst_nop_op}, 861 862 {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE, 863 cris_ver_v32p, 864 cris_btst_nop_op}, 865 866 {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0, 867 cris_dstep_logshift_mstep_neg_not_op}, 868 869 {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0, 870 cris_reg_mode_add_sub_cmp_and_or_move_op}, 871 872 {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0, 873 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 874 875 {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, 876 cris_ver_v0_10, 877 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 878 879 {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, 880 cris_ver_v0_10, 881 cris_three_operand_add_sub_cmp_and_or_op}, 882 883 {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0, 884 cris_quick_mode_and_cmp_move_or_op}, 885 886 {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, 887 cris_ver_v0_10, 888 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 889 890 {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, 891 cris_ver_v0_10, 892 cris_none_reg_mode_move_from_preg_op}, 893 894 {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, 895 cris_ver_v0_10, 896 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 897 898 {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, 899 cris_ver_v0_10, 900 cris_move_to_preg_op}, 901 902 {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE, 903 cris_ver_v10, 904 cris_not_implemented_op}, 905 906 {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE, 907 cris_ver_v10, 908 cris_not_implemented_op}, 909 910 {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE, 911 cris_ver_v32p, 912 cris_not_implemented_op}, 913 914 {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE, 915 cris_ver_v32p, 916 cris_not_implemented_op}, 917 918 {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE, 919 cris_ver_v32p, 920 cris_not_implemented_op}, 921 922 {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, 923 cris_ver_v0_10, 924 cris_reg_mode_move_from_preg_op}, 925 926 {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE, 927 cris_ver_v32p, 928 cris_reg_mode_move_from_preg_op}, 929 930 {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, 931 cris_ver_v0_10, 932 cris_reg_mode_move_from_preg_op}, 933 934 {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE, 935 cris_ver_v32p, 936 cris_reg_mode_move_from_preg_op}, 937 938 {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, 939 cris_ver_v0_10, 940 cris_reg_mode_move_from_preg_op}, 941 942 {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE, 943 cris_ver_v32p, 944 cris_reg_mode_move_from_preg_op}, 945 946 {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE, 947 cris_ver_v10, 948 cris_not_implemented_op}, 949 950 {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE, 951 cris_ver_v10, 952 cris_not_implemented_op}, 953 954 {"sa", 955 0x0530+CC_A*0x1000, 956 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0, 957 cris_scc_op}, 958 959 {"ssb", 960 0x0530+CC_EXT*0x1000, 961 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, 962 cris_ver_v32p, 963 cris_scc_op}, 964 965 {"scc", 966 0x0530+CC_CC*0x1000, 967 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0, 968 cris_scc_op}, 969 970 {"scs", 971 0x0530+CC_CS*0x1000, 972 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0, 973 cris_scc_op}, 974 975 {"seq", 976 0x0530+CC_EQ*0x1000, 977 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0, 978 cris_scc_op}, 979 980 {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0, 981 cris_ax_ei_setf_op}, 982 983 {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE, 984 cris_ver_v32p, 985 cris_not_implemented_op}, 986 987 /* Need to have "swf" in front of "sext" so it is the one displayed in 988 disassembly. */ 989 {"swf", 990 0x0530+CC_EXT*0x1000, 991 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, 992 cris_ver_v10, 993 cris_scc_op}, 994 995 {"sext", 996 0x0530+CC_EXT*0x1000, 997 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, 998 cris_ver_v0_3, 999 cris_scc_op}, 1000 1001 {"sge", 1002 0x0530+CC_GE*0x1000, 1003 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0, 1004 cris_scc_op}, 1005 1006 {"sgt", 1007 0x0530+CC_GT*0x1000, 1008 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0, 1009 cris_scc_op}, 1010 1011 {"shi", 1012 0x0530+CC_HI*0x1000, 1013 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0, 1014 cris_scc_op}, 1015 1016 {"shs", 1017 0x0530+CC_HS*0x1000, 1018 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0, 1019 cris_scc_op}, 1020 1021 {"sle", 1022 0x0530+CC_LE*0x1000, 1023 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0, 1024 cris_scc_op}, 1025 1026 {"slo", 1027 0x0530+CC_LO*0x1000, 1028 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0, 1029 cris_scc_op}, 1030 1031 {"sls", 1032 0x0530+CC_LS*0x1000, 1033 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0, 1034 cris_scc_op}, 1035 1036 {"slt", 1037 0x0530+CC_LT*0x1000, 1038 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0, 1039 cris_scc_op}, 1040 1041 {"smi", 1042 0x0530+CC_MI*0x1000, 1043 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0, 1044 cris_scc_op}, 1045 1046 {"sne", 1047 0x0530+CC_NE*0x1000, 1048 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0, 1049 cris_scc_op}, 1050 1051 {"spl", 1052 0x0530+CC_PL*0x1000, 1053 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0, 1054 cris_scc_op}, 1055 1056 {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0, 1057 cris_reg_mode_add_sub_cmp_and_or_move_op}, 1058 1059 {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0, 1060 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 1061 1062 {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, 1063 cris_ver_v0_10, 1064 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 1065 1066 {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, 1067 cris_ver_v0_10, 1068 cris_three_operand_add_sub_cmp_and_or_op}, 1069 1070 {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0, 1071 cris_quick_mode_add_sub_op}, 1072 1073 {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0, 1074 cris_reg_mode_add_sub_cmp_and_or_move_op}, 1075 1076 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ 1077 {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0, 1078 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 1079 1080 {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, 1081 cris_ver_v0_10, 1082 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 1083 1084 {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, 1085 cris_ver_v0_10, 1086 cris_three_operand_add_sub_cmp_and_or_op}, 1087 1088 {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0, 1089 cris_reg_mode_add_sub_cmp_and_or_move_op}, 1090 1091 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ 1092 {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0, 1093 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 1094 1095 {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, 1096 cris_ver_v0_10, 1097 cris_none_reg_mode_add_sub_cmp_and_or_move_op}, 1098 1099 {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, 1100 cris_ver_v0_10, 1101 cris_three_operand_add_sub_cmp_and_or_op}, 1102 1103 {"svc", 1104 0x0530+CC_VC*0x1000, 1105 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0, 1106 cris_scc_op}, 1107 1108 {"svs", 1109 0x0530+CC_VS*0x1000, 1110 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0, 1111 cris_scc_op}, 1112 1113 /* The insn "swapn" is the same as "not" and will be disassembled as 1114 such, but the swap* family of mnmonics are generally v8-and-higher 1115 only, so count it in. */ 1116 {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE, 1117 cris_ver_v8p, 1118 cris_not_implemented_op}, 1119 1120 {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE, 1121 cris_ver_v8p, 1122 cris_not_implemented_op}, 1123 1124 {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE, 1125 cris_ver_v8p, 1126 cris_not_implemented_op}, 1127 1128 {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE, 1129 cris_ver_v8p, 1130 cris_not_implemented_op}, 1131 1132 {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE, 1133 cris_ver_v8p, 1134 cris_not_implemented_op}, 1135 1136 {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE, 1137 cris_ver_v8p, 1138 cris_not_implemented_op}, 1139 1140 {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE, 1141 cris_ver_v8p, 1142 cris_not_implemented_op}, 1143 1144 {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE, 1145 cris_ver_v8p, 1146 cris_not_implemented_op}, 1147 1148 {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE, 1149 cris_ver_v8p, 1150 cris_not_implemented_op}, 1151 1152 {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE, 1153 cris_ver_v8p, 1154 cris_not_implemented_op}, 1155 1156 {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE, 1157 cris_ver_v8p, 1158 cris_not_implemented_op}, 1159 1160 {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE, 1161 cris_ver_v8p, 1162 cris_not_implemented_op}, 1163 1164 {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE, 1165 cris_ver_v8p, 1166 cris_not_implemented_op}, 1167 1168 {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE, 1169 cris_ver_v8p, 1170 cris_not_implemented_op}, 1171 1172 {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE, 1173 cris_ver_v8p, 1174 cris_not_implemented_op}, 1175 1176 {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, 1177 cris_ver_v0_10, 1178 cris_reg_mode_test_op}, 1179 1180 {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0, 1181 cris_none_reg_mode_clear_test_op}, 1182 1183 {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, 1184 cris_ver_v0_10, 1185 cris_none_reg_mode_clear_test_op}, 1186 1187 {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0, 1188 cris_xor_op}, 1189 1190 {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op} 1191 }; 1192 1193 /* Condition-names, indexed by the CC_* numbers as found in cris.h. */ 1194 const char * const 1195 cris_cc_strings[] = 1196 { 1197 "hs", 1198 "lo", 1199 "ne", 1200 "eq", 1201 "vc", 1202 "vs", 1203 "pl", 1204 "mi", 1205 "ls", 1206 "hi", 1207 "ge", 1208 "lt", 1209 "gt", 1210 "le", 1211 "a", 1212 /* This is a placeholder. In v0, this would be "ext". In v32, this 1213 is "sb". */ 1214 "wf" 1215 }; 1216 1217 /* 1218 * Local variables: 1219 * eval: (c-set-style "gnu") 1220 * indent-tabs-mode: t 1221 * End: 1222 */ 1223 1224 1225 /* No instruction will be disassembled longer than this. In theory, and 1226 in silicon, address prefixes can be cascaded. In practice, cascading 1227 is not used by GCC, and not supported by the assembler. */ 1228 #ifndef MAX_BYTES_PER_CRIS_INSN 1229 #define MAX_BYTES_PER_CRIS_INSN 8 1230 #endif 1231 1232 /* Whether or not to decode prefixes, folding it into the following 1233 instruction. FIXME: Make this optional later. */ 1234 #ifndef PARSE_PREFIX 1235 #define PARSE_PREFIX 1 1236 #endif 1237 1238 /* Sometimes we prefix all registers with this character. */ 1239 #define REGISTER_PREFIX_CHAR '$' 1240 1241 /* Whether or not to trace the following sequence: 1242 sub* X,r%d 1243 bound* Y,r%d 1244 adds.w [pc+r%d.w],pc 1245 1246 This is the assembly form of a switch-statement in C. 1247 The "sub is optional. If there is none, then X will be zero. 1248 X is the value of the first case, 1249 Y is the number of cases (including default). 1250 1251 This results in case offsets printed on the form: 1252 case N: -> case_address 1253 where N is an estimation on the corresponding 'case' operand in C, 1254 and case_address is where execution of that case continues after the 1255 sequence presented above. 1256 1257 The old style of output was to print the offsets as instructions, 1258 which made it hard to follow "case"-constructs in the disassembly, 1259 and caused a lot of annoying warnings about undefined instructions. 1260 1261 FIXME: Make this optional later. */ 1262 #ifndef TRACE_CASE 1263 #define TRACE_CASE (disdata->trace_case) 1264 #endif 1265 1266 enum cris_disass_family 1267 { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 }; 1268 1269 /* Stored in the disasm_info->private_data member. */ 1270 struct cris_disasm_data 1271 { 1272 /* Whether to print something less confusing if we find something 1273 matching a switch-construct. */ 1274 bfd_boolean trace_case; 1275 1276 /* Whether this code is flagged as crisv32. FIXME: Should be an enum 1277 that includes "compatible". */ 1278 enum cris_disass_family distype; 1279 }; 1280 1281 /* Value of first element in switch. */ 1282 static long case_offset = 0; 1283 1284 /* How many more case-offsets to print. */ 1285 static long case_offset_counter = 0; 1286 1287 /* Number of case offsets. */ 1288 static long no_of_case_offsets = 0; 1289 1290 /* Candidate for next case_offset. */ 1291 static long last_immediate = 0; 1292 1293 static int cris_constraint 1294 (const char *, unsigned, unsigned, struct cris_disasm_data *); 1295 1296 /* Parse disassembler options and store state in info. FIXME: For the 1297 time being, we abuse static variables. */ 1298 1299 static bfd_boolean 1300 cris_parse_disassembler_options (disassemble_info *info, 1301 enum cris_disass_family distype) 1302 { 1303 struct cris_disasm_data *disdata; 1304 1305 info->private_data = calloc (1, sizeof (struct cris_disasm_data)); 1306 disdata = (struct cris_disasm_data *) info->private_data; 1307 if (disdata == NULL) 1308 return false; 1309 1310 /* Default true. */ 1311 disdata->trace_case 1312 = (info->disassembler_options == NULL 1313 || (strcmp (info->disassembler_options, "nocase") != 0)); 1314 1315 disdata->distype = distype; 1316 return true; 1317 } 1318 1319 static const struct cris_spec_reg * 1320 spec_reg_info (unsigned int sreg, enum cris_disass_family distype) 1321 { 1322 int i; 1323 1324 for (i = 0; cris_spec_regs[i].name != NULL; i++) 1325 { 1326 if (cris_spec_regs[i].number == sreg) 1327 { 1328 if (distype == cris_dis_v32) 1329 switch (cris_spec_regs[i].applicable_version) 1330 { 1331 case cris_ver_warning: 1332 case cris_ver_version_all: 1333 case cris_ver_v3p: 1334 case cris_ver_v8p: 1335 case cris_ver_v10p: 1336 case cris_ver_v32p: 1337 /* No ambiguous sizes or register names with CRISv32. */ 1338 if (cris_spec_regs[i].warning == NULL) 1339 return &cris_spec_regs[i]; 1340 default: 1341 ; 1342 } 1343 else if (cris_spec_regs[i].applicable_version != cris_ver_v32p) 1344 return &cris_spec_regs[i]; 1345 } 1346 } 1347 1348 return NULL; 1349 } 1350 1351 /* Return the number of bits in the argument. */ 1352 1353 static int 1354 number_of_bits (unsigned int val) 1355 { 1356 int bits; 1357 1358 for (bits = 0; val != 0; val &= val - 1) 1359 bits++; 1360 1361 return bits; 1362 } 1363 1364 /* Get an entry in the opcode-table. */ 1365 1366 static const struct cris_opcode * 1367 get_opcode_entry (unsigned int insn, 1368 unsigned int prefix_insn, 1369 struct cris_disasm_data *disdata) 1370 { 1371 /* For non-prefixed insns, we keep a table of pointers, indexed by the 1372 insn code. Each entry is initialized when found to be NULL. */ 1373 static const struct cris_opcode **opc_table = NULL; 1374 1375 const struct cris_opcode *max_matchedp = NULL; 1376 const struct cris_opcode **prefix_opc_table = NULL; 1377 1378 /* We hold a table for each prefix that need to be handled differently. */ 1379 static const struct cris_opcode **dip_prefixes = NULL; 1380 static const struct cris_opcode **bdapq_m1_prefixes = NULL; 1381 static const struct cris_opcode **bdapq_m2_prefixes = NULL; 1382 static const struct cris_opcode **bdapq_m4_prefixes = NULL; 1383 static const struct cris_opcode **rest_prefixes = NULL; 1384 1385 /* Allocate and clear the opcode-table. */ 1386 if (opc_table == NULL) 1387 { 1388 opc_table = g_new0(const struct cris_opcode *, 65536); 1389 dip_prefixes = g_new0(const struct cris_opcode *, 65536); 1390 bdapq_m1_prefixes = g_new0(const struct cris_opcode *, 65536); 1391 bdapq_m2_prefixes = g_new0(const struct cris_opcode *, 65536); 1392 bdapq_m4_prefixes = g_new0(const struct cris_opcode *, 65536); 1393 rest_prefixes = g_new0(const struct cris_opcode *, 65536); 1394 } 1395 1396 /* Get the right table if this is a prefix. 1397 This code is connected to cris_constraints in that it knows what 1398 prefixes play a role in recognition of patterns; the necessary 1399 state is reflected by which table is used. If constraints 1400 involving match or non-match of prefix insns are changed, then this 1401 probably needs changing too. */ 1402 if (prefix_insn != NO_CRIS_PREFIX) 1403 { 1404 const struct cris_opcode *popcodep 1405 = (opc_table[prefix_insn] != NULL 1406 ? opc_table[prefix_insn] 1407 : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata)); 1408 1409 if (popcodep == NULL) 1410 return NULL; 1411 1412 if (popcodep->match == BDAP_QUICK_OPCODE) 1413 { 1414 /* Since some offsets are recognized with "push" macros, we 1415 have to have different tables for them. */ 1416 int offset = (prefix_insn & 255); 1417 1418 if (offset > 127) 1419 offset -= 256; 1420 1421 switch (offset) 1422 { 1423 case -4: 1424 prefix_opc_table = bdapq_m4_prefixes; 1425 break; 1426 1427 case -2: 1428 prefix_opc_table = bdapq_m2_prefixes; 1429 break; 1430 1431 case -1: 1432 prefix_opc_table = bdapq_m1_prefixes; 1433 break; 1434 1435 default: 1436 prefix_opc_table = rest_prefixes; 1437 break; 1438 } 1439 } 1440 else if (popcodep->match == DIP_OPCODE) 1441 /* We don't allow postincrement when the prefix is DIP, so use a 1442 different table for DIP. */ 1443 prefix_opc_table = dip_prefixes; 1444 else 1445 prefix_opc_table = rest_prefixes; 1446 } 1447 1448 if (prefix_insn != NO_CRIS_PREFIX 1449 && prefix_opc_table[insn] != NULL) 1450 max_matchedp = prefix_opc_table[insn]; 1451 else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL) 1452 max_matchedp = opc_table[insn]; 1453 else 1454 { 1455 const struct cris_opcode *opcodep; 1456 int max_level_of_match = -1; 1457 1458 for (opcodep = cris_opcodes; 1459 opcodep->name != NULL; 1460 opcodep++) 1461 { 1462 int level_of_match; 1463 1464 if (disdata->distype == cris_dis_v32) 1465 { 1466 switch (opcodep->applicable_version) 1467 { 1468 case cris_ver_version_all: 1469 break; 1470 1471 case cris_ver_v0_3: 1472 case cris_ver_v0_10: 1473 case cris_ver_v3_10: 1474 case cris_ver_sim_v0_10: 1475 case cris_ver_v8_10: 1476 case cris_ver_v10: 1477 case cris_ver_warning: 1478 continue; 1479 1480 case cris_ver_v3p: 1481 case cris_ver_v8p: 1482 case cris_ver_v10p: 1483 case cris_ver_v32p: 1484 break; 1485 1486 case cris_ver_v8: 1487 abort (); 1488 default: 1489 abort (); 1490 } 1491 } 1492 else 1493 { 1494 switch (opcodep->applicable_version) 1495 { 1496 case cris_ver_version_all: 1497 case cris_ver_v0_3: 1498 case cris_ver_v3p: 1499 case cris_ver_v0_10: 1500 case cris_ver_v8p: 1501 case cris_ver_v8_10: 1502 case cris_ver_v10: 1503 case cris_ver_sim_v0_10: 1504 case cris_ver_v10p: 1505 case cris_ver_warning: 1506 break; 1507 1508 case cris_ver_v32p: 1509 continue; 1510 1511 case cris_ver_v8: 1512 abort (); 1513 default: 1514 abort (); 1515 } 1516 } 1517 1518 /* We give a double lead for bits matching the template in 1519 cris_opcodes. Not even, because then "move p8,r10" would 1520 be given 2 bits lead over "clear.d r10". When there's a 1521 tie, the first entry in the table wins. This is 1522 deliberate, to avoid a more complicated recognition 1523 formula. */ 1524 if ((opcodep->match & insn) == opcodep->match 1525 && (opcodep->lose & insn) == 0 1526 && ((level_of_match 1527 = cris_constraint (opcodep->args, 1528 insn, 1529 prefix_insn, 1530 disdata)) 1531 >= 0) 1532 && ((level_of_match 1533 += 2 * number_of_bits (opcodep->match 1534 | opcodep->lose)) 1535 > max_level_of_match)) 1536 { 1537 max_matchedp = opcodep; 1538 max_level_of_match = level_of_match; 1539 1540 /* If there was a full match, never mind looking 1541 further. */ 1542 if (level_of_match >= 2 * 16) 1543 break; 1544 } 1545 } 1546 /* Fill in the new entry. 1547 1548 If there are changes to the opcode-table involving prefixes, and 1549 disassembly then does not work correctly, try removing the 1550 else-clause below that fills in the prefix-table. If that 1551 helps, you need to change the prefix_opc_table setting above, or 1552 something related. */ 1553 if (prefix_insn == NO_CRIS_PREFIX) 1554 opc_table[insn] = max_matchedp; 1555 else 1556 prefix_opc_table[insn] = max_matchedp; 1557 } 1558 1559 return max_matchedp; 1560 } 1561 1562 /* Return -1 if the constraints of a bitwise-matched instruction say 1563 that there is no match. Otherwise return a nonnegative number 1564 indicating the confidence in the match (higher is better). */ 1565 1566 static int 1567 cris_constraint (const char *cs, 1568 unsigned int insn, 1569 unsigned int prefix_insn, 1570 struct cris_disasm_data *disdata) 1571 { 1572 int retval = 0; 1573 int tmp; 1574 int prefix_ok = 0; 1575 const char *s; 1576 1577 for (s = cs; *s; s++) 1578 switch (*s) 1579 { 1580 case '!': 1581 /* Do not recognize "pop" if there's a prefix and then only for 1582 v0..v10. */ 1583 if (prefix_insn != NO_CRIS_PREFIX 1584 || disdata->distype != cris_dis_v0_v10) 1585 return -1; 1586 break; 1587 1588 case 'U': 1589 /* Not recognized at disassembly. */ 1590 return -1; 1591 1592 case 'M': 1593 /* Size modifier for "clear", i.e. special register 0, 4 or 8. 1594 Check that it is one of them. Only special register 12 could 1595 be mismatched, but checking for matches is more logical than 1596 checking for mismatches when there are only a few cases. */ 1597 tmp = ((insn >> 12) & 0xf); 1598 if (tmp != 0 && tmp != 4 && tmp != 8) 1599 return -1; 1600 break; 1601 1602 case 'm': 1603 if ((insn & 0x30) == 0x30) 1604 return -1; 1605 break; 1606 1607 case 'S': 1608 /* A prefix operand without side-effect. */ 1609 if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0) 1610 { 1611 prefix_ok = 1; 1612 break; 1613 } 1614 else 1615 return -1; 1616 1617 case 's': 1618 case 'y': 1619 case 'Y': 1620 /* If this is a prefixed insn with postincrement (side-effect), 1621 the prefix must not be DIP. */ 1622 if (prefix_insn != NO_CRIS_PREFIX) 1623 { 1624 if (insn & 0x400) 1625 { 1626 const struct cris_opcode *prefix_opcodep 1627 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); 1628 1629 if (prefix_opcodep->match == DIP_OPCODE) 1630 return -1; 1631 } 1632 1633 prefix_ok = 1; 1634 } 1635 break; 1636 1637 case 'B': 1638 /* If we don't fall through, then the prefix is ok. */ 1639 prefix_ok = 1; 1640 1641 /* A "push" prefix. Check for valid "push" size. 1642 In case of special register, it may be != 4. */ 1643 if (prefix_insn != NO_CRIS_PREFIX) 1644 { 1645 /* Match the prefix insn to BDAPQ. */ 1646 const struct cris_opcode *prefix_opcodep 1647 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); 1648 1649 if (prefix_opcodep->match == BDAP_QUICK_OPCODE) 1650 { 1651 int pushsize = (prefix_insn & 255); 1652 1653 if (pushsize > 127) 1654 pushsize -= 256; 1655 1656 if (s[1] == 'P') 1657 { 1658 unsigned int spec_reg = (insn >> 12) & 15; 1659 const struct cris_spec_reg *sregp 1660 = spec_reg_info (spec_reg, disdata->distype); 1661 1662 /* For a special-register, the "prefix size" must 1663 match the size of the register. */ 1664 if (sregp && sregp->reg_size == (unsigned int) -pushsize) 1665 break; 1666 } 1667 else if (s[1] == 'R') 1668 { 1669 if ((insn & 0x30) == 0x20 && pushsize == -4) 1670 break; 1671 } 1672 /* FIXME: Should abort here; next constraint letter 1673 *must* be 'P' or 'R'. */ 1674 } 1675 } 1676 return -1; 1677 1678 case 'D': 1679 retval = (((insn >> 12) & 15) == (insn & 15)); 1680 if (!retval) 1681 return -1; 1682 else 1683 retval += 4; 1684 break; 1685 1686 case 'P': 1687 { 1688 const struct cris_spec_reg *sregp 1689 = spec_reg_info ((insn >> 12) & 15, disdata->distype); 1690 1691 /* Since we match four bits, we will give a value of 4-1 = 3 1692 in a match. If there is a corresponding exact match of a 1693 special register in another pattern, it will get a value of 1694 4, which will be higher. This should be correct in that an 1695 exact pattern would match better than a general pattern. 1696 1697 Note that there is a reason for not returning zero; the 1698 pattern for "clear" is partly matched in the bit-pattern 1699 (the two lower bits must be zero), while the bit-pattern 1700 for a move from a special register is matched in the 1701 register constraint. */ 1702 1703 if (sregp != NULL) 1704 { 1705 retval += 3; 1706 break; 1707 } 1708 else 1709 return -1; 1710 } 1711 } 1712 1713 if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok) 1714 return -1; 1715 1716 return retval; 1717 } 1718 1719 /* Format number as hex with a leading "0x" into outbuffer. */ 1720 1721 static char * 1722 format_hex (unsigned long number, 1723 char *outbuffer, 1724 struct cris_disasm_data *disdata) 1725 { 1726 /* Truncate negative numbers on >32-bit hosts. */ 1727 number &= 0xffffffff; 1728 1729 sprintf (outbuffer, "0x%lx", number); 1730 1731 /* Save this value for the "case" support. */ 1732 if (TRACE_CASE) 1733 last_immediate = number; 1734 1735 return outbuffer + strlen (outbuffer); 1736 } 1737 1738 /* Format number as decimal into outbuffer. Parameter signedp says 1739 whether the number should be formatted as signed (!= 0) or 1740 unsigned (== 0). */ 1741 1742 static char * 1743 format_dec (long number, char *outbuffer, int signedp) 1744 { 1745 last_immediate = number; 1746 sprintf (outbuffer, signedp ? "%ld" : "%lu", number); 1747 1748 return outbuffer + strlen (outbuffer); 1749 } 1750 1751 /* Format the name of the general register regno into outbuffer. */ 1752 1753 static char * 1754 format_reg (struct cris_disasm_data *disdata, 1755 int regno, 1756 char *outbuffer_start, 1757 bfd_boolean with_reg_prefix) 1758 { 1759 char *outbuffer = outbuffer_start; 1760 1761 if (with_reg_prefix) 1762 *outbuffer++ = REGISTER_PREFIX_CHAR; 1763 1764 switch (regno) 1765 { 1766 case 15: 1767 /* For v32, there is no context in which we output PC. */ 1768 if (disdata->distype == cris_dis_v32) 1769 strcpy (outbuffer, "acr"); 1770 else 1771 strcpy (outbuffer, "pc"); 1772 break; 1773 1774 case 14: 1775 strcpy (outbuffer, "sp"); 1776 break; 1777 1778 default: 1779 sprintf (outbuffer, "r%d", regno); 1780 break; 1781 } 1782 1783 return outbuffer_start + strlen (outbuffer_start); 1784 } 1785 1786 /* Format the name of a support register into outbuffer. */ 1787 1788 static char * 1789 format_sup_reg (unsigned int regno, 1790 char *outbuffer_start, 1791 bfd_boolean with_reg_prefix) 1792 { 1793 char *outbuffer = outbuffer_start; 1794 int i; 1795 1796 if (with_reg_prefix) 1797 *outbuffer++ = REGISTER_PREFIX_CHAR; 1798 1799 for (i = 0; cris_support_regs[i].name != NULL; i++) 1800 if (cris_support_regs[i].number == regno) 1801 { 1802 sprintf (outbuffer, "%s", cris_support_regs[i].name); 1803 return outbuffer_start + strlen (outbuffer_start); 1804 } 1805 1806 /* There's supposed to be register names covering all numbers, though 1807 some may be generic names. */ 1808 sprintf (outbuffer, "format_sup_reg-BUG"); 1809 return outbuffer_start + strlen (outbuffer_start); 1810 } 1811 1812 /* Return the length of an instruction. */ 1813 1814 static unsigned 1815 bytes_to_skip (unsigned int insn, 1816 const struct cris_opcode *matchedp, 1817 enum cris_disass_family distype, 1818 const struct cris_opcode *prefix_matchedp) 1819 { 1820 /* Each insn is a word plus "immediate" operands. */ 1821 unsigned to_skip = 2; 1822 const char *template = matchedp->args; 1823 const char *s; 1824 1825 for (s = template; *s; s++) 1826 if ((*s == 's' || *s == 'N' || *s == 'Y') 1827 && (insn & 0x400) && (insn & 15) == 15 1828 && prefix_matchedp == NULL) 1829 { 1830 /* Immediate via [pc+], so we have to check the size of the 1831 operand. */ 1832 int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3)); 1833 1834 if (matchedp->imm_oprnd_size == SIZE_FIX_32) 1835 to_skip += 4; 1836 else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG) 1837 { 1838 const struct cris_spec_reg *sregp 1839 = spec_reg_info ((insn >> 12) & 15, distype); 1840 1841 /* FIXME: Improve error handling; should have been caught 1842 earlier. */ 1843 if (sregp == NULL) 1844 return 2; 1845 1846 /* PC is incremented by two, not one, for a byte. Except on 1847 CRISv32, where constants are always DWORD-size for 1848 special registers. */ 1849 to_skip += 1850 distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1; 1851 } 1852 else 1853 to_skip += (mode_size + 1) & ~1; 1854 } 1855 else if (*s == 'n') 1856 to_skip += 4; 1857 else if (*s == 'b') 1858 to_skip += 2; 1859 1860 return to_skip; 1861 } 1862 1863 /* Print condition code flags. */ 1864 1865 static char * 1866 print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp) 1867 { 1868 /* Use the v8 (Etrax 100) flag definitions for disassembly. 1869 The differences with v0 (Etrax 1..4) vs. Svinto are: 1870 v0 'd' <=> v8 'm' 1871 v0 'e' <=> v8 'b'. 1872 FIXME: Emit v0..v3 flag names somehow. */ 1873 static const char v8_fnames[] = "cvznxibm"; 1874 static const char v32_fnames[] = "cvznxiup"; 1875 const char *fnames 1876 = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames; 1877 1878 unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15)); 1879 int i; 1880 1881 for (i = 0; i < 8; i++) 1882 if (flagbits & (1 << i)) 1883 *cp++ = fnames[i]; 1884 1885 return cp; 1886 } 1887 1888 /* Print out an insn with its operands, and update the info->insn_type 1889 fields. The prefix_opcodep and the rest hold a prefix insn that is 1890 supposed to be output as an address mode. */ 1891 1892 static void 1893 print_with_operands (const struct cris_opcode *opcodep, 1894 unsigned int insn, 1895 unsigned char *buffer, 1896 bfd_vma addr, 1897 disassemble_info *info, 1898 /* If a prefix insn was before this insn (and is supposed 1899 to be output as an address), here is a description of 1900 it. */ 1901 const struct cris_opcode *prefix_opcodep, 1902 unsigned int prefix_insn, 1903 unsigned char *prefix_buffer, 1904 bfd_boolean with_reg_prefix) 1905 { 1906 /* Get a buffer of somewhat reasonable size where we store 1907 intermediate parts of the insn. */ 1908 char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2]; 1909 char *tp = temp; 1910 static const char mode_char[] = "bwd?"; 1911 const char *s; 1912 const char *cs; 1913 struct cris_disasm_data *disdata 1914 = (struct cris_disasm_data *) info->private_data; 1915 1916 /* Print out the name first thing we do. */ 1917 (*info->fprintf_func) (info->stream, "%s", opcodep->name); 1918 1919 cs = opcodep->args; 1920 s = cs; 1921 1922 /* Ignore any prefix indicator. */ 1923 if (*s == 'p') 1924 s++; 1925 1926 if (*s == 'm' || *s == 'M' || *s == 'z') 1927 { 1928 *tp++ = '.'; 1929 1930 /* Get the size-letter. */ 1931 *tp++ = *s == 'M' 1932 ? (insn & 0x8000 ? 'd' 1933 : insn & 0x4000 ? 'w' : 'b') 1934 : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)]; 1935 1936 /* Ignore the size and the space character that follows. */ 1937 s += 2; 1938 } 1939 1940 /* Add a space if this isn't a long-branch, because for those will add 1941 the condition part of the name later. */ 1942 if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256)) 1943 *tp++ = ' '; 1944 1945 /* Fill in the insn-type if deducible from the name (and there's no 1946 better way). */ 1947 if (opcodep->name[0] == 'j') 1948 { 1949 if (CONST_STRNEQ (opcodep->name, "jsr")) 1950 /* It's "jsr" or "jsrc". */ 1951 info->insn_type = dis_jsr; 1952 else 1953 /* Any other jump-type insn is considered a branch. */ 1954 info->insn_type = dis_branch; 1955 } 1956 1957 /* We might know some more fields right now. */ 1958 info->branch_delay_insns = opcodep->delayed; 1959 1960 /* Handle operands. */ 1961 for (; *s; s++) 1962 { 1963 switch (*s) 1964 { 1965 case 'T': 1966 tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix); 1967 break; 1968 1969 case 'A': 1970 if (with_reg_prefix) 1971 *tp++ = REGISTER_PREFIX_CHAR; 1972 *tp++ = 'a'; 1973 *tp++ = 'c'; 1974 *tp++ = 'r'; 1975 break; 1976 1977 case '[': 1978 case ']': 1979 case ',': 1980 *tp++ = *s; 1981 break; 1982 1983 case '!': 1984 /* Ignore at this point; used at earlier stages to avoid 1985 recognition if there's a prefix at something that in other 1986 ways looks like a "pop". */ 1987 break; 1988 1989 case 'd': 1990 /* Ignore. This is an optional ".d " on the large one of 1991 relaxable insns. */ 1992 break; 1993 1994 case 'B': 1995 /* This was the prefix that made this a "push". We've already 1996 handled it by recognizing it, so signal that the prefix is 1997 handled by setting it to NULL. */ 1998 prefix_opcodep = NULL; 1999 break; 2000 2001 case 'D': 2002 case 'r': 2003 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix); 2004 break; 2005 2006 case 'R': 2007 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); 2008 break; 2009 2010 case 'n': 2011 { 2012 /* Like N but pc-relative to the start of the insn. */ 2013 unsigned long number 2014 = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536 2015 + buffer[5] * 0x1000000 + addr); 2016 2017 /* Finish off and output previous formatted bytes. */ 2018 *tp = 0; 2019 if (temp[0]) 2020 (*info->fprintf_func) (info->stream, "%s", temp); 2021 tp = temp; 2022 2023 (*info->print_address_func) ((bfd_vma) number, info); 2024 } 2025 break; 2026 2027 case 'u': 2028 { 2029 /* Like n but the offset is bits <3:0> in the instruction. */ 2030 unsigned long number = (buffer[0] & 0xf) * 2 + addr; 2031 2032 /* Finish off and output previous formatted bytes. */ 2033 *tp = 0; 2034 if (temp[0]) 2035 (*info->fprintf_func) (info->stream, "%s", temp); 2036 tp = temp; 2037 2038 (*info->print_address_func) ((bfd_vma) number, info); 2039 } 2040 break; 2041 2042 case 'N': 2043 case 'y': 2044 case 'Y': 2045 case 'S': 2046 case 's': 2047 /* Any "normal" memory operand. */ 2048 if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL) 2049 { 2050 /* We're looking at [pc+], i.e. we need to output an immediate 2051 number, where the size can depend on different things. */ 2052 long number; 2053 int signedp 2054 = ((*cs == 'z' && (insn & 0x20)) 2055 || opcodep->match == BDAP_QUICK_OPCODE); 2056 int nbytes; 2057 2058 if (opcodep->imm_oprnd_size == SIZE_FIX_32) 2059 nbytes = 4; 2060 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) 2061 { 2062 const struct cris_spec_reg *sregp 2063 = spec_reg_info ((insn >> 12) & 15, disdata->distype); 2064 2065 /* A NULL return should have been as a non-match earlier, 2066 so catch it as an internal error in the error-case 2067 below. */ 2068 if (sregp == NULL) 2069 /* Whatever non-valid size. */ 2070 nbytes = 42; 2071 else 2072 /* PC is always incremented by a multiple of two. 2073 For CRISv32, immediates are always 4 bytes for 2074 special registers. */ 2075 nbytes = disdata->distype == cris_dis_v32 2076 ? 4 : (sregp->reg_size + 1) & ~1; 2077 } 2078 else 2079 { 2080 int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3)); 2081 2082 if (mode_size == 1) 2083 nbytes = 2; 2084 else 2085 nbytes = mode_size; 2086 } 2087 2088 switch (nbytes) 2089 { 2090 case 1: 2091 number = buffer[2]; 2092 if (signedp && number > 127) 2093 number -= 256; 2094 break; 2095 2096 case 2: 2097 number = buffer[2] + buffer[3] * 256; 2098 if (signedp && number > 32767) 2099 number -= 65536; 2100 break; 2101 2102 case 4: 2103 number 2104 = buffer[2] + buffer[3] * 256 + buffer[4] * 65536 2105 + buffer[5] * 0x1000000; 2106 break; 2107 2108 default: 2109 strcpy (tp, "bug"); 2110 tp += 3; 2111 number = 42; 2112 } 2113 2114 if ((*cs == 'z' && (insn & 0x20)) 2115 || (opcodep->match == BDAP_QUICK_OPCODE 2116 && (nbytes <= 2 || buffer[1 + nbytes] == 0))) 2117 tp = format_dec (number, tp, signedp); 2118 else 2119 { 2120 unsigned int highbyte = (number >> 24) & 0xff; 2121 2122 /* Either output this as an address or as a number. If it's 2123 a dword with the same high-byte as the address of the 2124 insn, assume it's an address, and also if it's a non-zero 2125 non-0xff high-byte. If this is a jsr or a jump, then 2126 it's definitely an address. */ 2127 if (nbytes == 4 2128 && (highbyte == ((addr >> 24) & 0xff) 2129 || (highbyte != 0 && highbyte != 0xff) 2130 || info->insn_type == dis_branch 2131 || info->insn_type == dis_jsr)) 2132 { 2133 /* Finish off and output previous formatted bytes. */ 2134 *tp = 0; 2135 tp = temp; 2136 if (temp[0]) 2137 (*info->fprintf_func) (info->stream, "%s", temp); 2138 2139 (*info->print_address_func) ((bfd_vma) number, info); 2140 2141 info->target = number; 2142 } 2143 else 2144 tp = format_hex (number, tp, disdata); 2145 } 2146 } 2147 else 2148 { 2149 /* Not an immediate number. Then this is a (possibly 2150 prefixed) memory operand. */ 2151 if (info->insn_type != dis_nonbranch) 2152 { 2153 int mode_size 2154 = 1 << ((insn >> 4) 2155 & (opcodep->args[0] == 'z' ? 1 : 3)); 2156 int size; 2157 info->insn_type = dis_dref; 2158 info->flags |= CRIS_DIS_FLAG_MEMREF; 2159 2160 if (opcodep->imm_oprnd_size == SIZE_FIX_32) 2161 size = 4; 2162 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG) 2163 { 2164 const struct cris_spec_reg *sregp 2165 = spec_reg_info ((insn >> 12) & 15, disdata->distype); 2166 2167 /* FIXME: Improve error handling; should have been caught 2168 earlier. */ 2169 if (sregp == NULL) 2170 size = 4; 2171 else 2172 size = sregp->reg_size; 2173 } 2174 else 2175 size = mode_size; 2176 2177 info->data_size = size; 2178 } 2179 2180 *tp++ = '['; 2181 2182 if (prefix_opcodep 2183 /* We don't match dip with a postincremented field 2184 as a side-effect address mode. */ 2185 && ((insn & 0x400) == 0 2186 || prefix_opcodep->match != DIP_OPCODE)) 2187 { 2188 if (insn & 0x400) 2189 { 2190 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix); 2191 *tp++ = '='; 2192 } 2193 2194 2195 /* We mainly ignore the prefix format string when the 2196 address-mode syntax is output. */ 2197 switch (prefix_opcodep->match) 2198 { 2199 case DIP_OPCODE: 2200 /* It's [r], [r+] or [pc+]. */ 2201 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) 2202 { 2203 /* It's [pc+]. This cannot possibly be anything 2204 but an address. */ 2205 unsigned long number 2206 = prefix_buffer[2] + prefix_buffer[3] * 256 2207 + prefix_buffer[4] * 65536 2208 + prefix_buffer[5] * 0x1000000; 2209 2210 info->target = (bfd_vma) number; 2211 2212 /* Finish off and output previous formatted 2213 data. */ 2214 *tp = 0; 2215 tp = temp; 2216 if (temp[0]) 2217 (*info->fprintf_func) (info->stream, "%s", temp); 2218 2219 (*info->print_address_func) ((bfd_vma) number, info); 2220 } 2221 else 2222 { 2223 /* For a memref in an address, we use target2. 2224 In this case, target is zero. */ 2225 info->flags 2226 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG 2227 | CRIS_DIS_FLAG_MEM_TARGET2_MEM); 2228 2229 info->target2 = prefix_insn & 15; 2230 2231 *tp++ = '['; 2232 tp = format_reg (disdata, prefix_insn & 15, tp, 2233 with_reg_prefix); 2234 if (prefix_insn & 0x400) 2235 *tp++ = '+'; 2236 *tp++ = ']'; 2237 } 2238 break; 2239 2240 case BDAP_QUICK_OPCODE: 2241 { 2242 int number; 2243 2244 number = prefix_buffer[0]; 2245 if (number > 127) 2246 number -= 256; 2247 2248 /* Output "reg+num" or, if num < 0, "reg-num". */ 2249 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, 2250 with_reg_prefix); 2251 if (number >= 0) 2252 *tp++ = '+'; 2253 tp = format_dec (number, tp, 1); 2254 2255 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; 2256 info->target = (prefix_insn >> 12) & 15; 2257 info->target2 = (bfd_vma) number; 2258 break; 2259 } 2260 2261 case BIAP_OPCODE: 2262 /* Output "r+R.m". */ 2263 tp = format_reg (disdata, prefix_insn & 15, tp, 2264 with_reg_prefix); 2265 *tp++ = '+'; 2266 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, 2267 with_reg_prefix); 2268 *tp++ = '.'; 2269 *tp++ = mode_char[(prefix_insn >> 4) & 3]; 2270 2271 info->flags 2272 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG 2273 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG 2274 2275 | ((prefix_insn & 0x8000) 2276 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4 2277 : ((prefix_insn & 0x8000) 2278 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0))); 2279 2280 /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */ 2281 if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f) 2282 /* Then start interpreting data as offsets. */ 2283 case_offset_counter = no_of_case_offsets; 2284 break; 2285 2286 case BDAP_INDIR_OPCODE: 2287 /* Output "r+s.m", or, if "s" is [pc+], "r+s" or 2288 "r-s". */ 2289 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp, 2290 with_reg_prefix); 2291 2292 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15) 2293 { 2294 long number; 2295 unsigned int nbytes; 2296 2297 /* It's a value. Get its size. */ 2298 int mode_size = 1 << ((prefix_insn >> 4) & 3); 2299 2300 if (mode_size == 1) 2301 nbytes = 2; 2302 else 2303 nbytes = mode_size; 2304 2305 switch (nbytes) 2306 { 2307 case 1: 2308 number = prefix_buffer[2]; 2309 if (number > 127) 2310 number -= 256; 2311 break; 2312 2313 case 2: 2314 number = prefix_buffer[2] + prefix_buffer[3] * 256; 2315 if (number > 32767) 2316 number -= 65536; 2317 break; 2318 2319 case 4: 2320 number 2321 = prefix_buffer[2] + prefix_buffer[3] * 256 2322 + prefix_buffer[4] * 65536 2323 + prefix_buffer[5] * 0x1000000; 2324 break; 2325 2326 default: 2327 strcpy (tp, "bug"); 2328 tp += 3; 2329 number = 42; 2330 } 2331 2332 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; 2333 info->target2 = (bfd_vma) number; 2334 2335 /* If the size is dword, then assume it's an 2336 address. */ 2337 if (nbytes == 4) 2338 { 2339 /* Finish off and output previous formatted 2340 bytes. */ 2341 *tp++ = '+'; 2342 *tp = 0; 2343 tp = temp; 2344 (*info->fprintf_func) (info->stream, "%s", temp); 2345 2346 (*info->print_address_func) ((bfd_vma) number, info); 2347 } 2348 else 2349 { 2350 if (number >= 0) 2351 *tp++ = '+'; 2352 tp = format_dec (number, tp, 1); 2353 } 2354 } 2355 else 2356 { 2357 /* Output "r+[R].m" or "r+[R+].m". */ 2358 *tp++ = '+'; 2359 *tp++ = '['; 2360 tp = format_reg (disdata, prefix_insn & 15, tp, 2361 with_reg_prefix); 2362 if (prefix_insn & 0x400) 2363 *tp++ = '+'; 2364 *tp++ = ']'; 2365 *tp++ = '.'; 2366 *tp++ = mode_char[(prefix_insn >> 4) & 3]; 2367 2368 info->flags 2369 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG 2370 | CRIS_DIS_FLAG_MEM_TARGET2_MEM 2371 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG 2372 2373 | (((prefix_insn >> 4) == 2) 2374 ? 0 2375 : (((prefix_insn >> 4) & 3) == 1 2376 ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD 2377 : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE))); 2378 } 2379 break; 2380 2381 default: 2382 (*info->fprintf_func) (info->stream, "?prefix-bug"); 2383 } 2384 2385 /* To mark that the prefix is used, reset it. */ 2386 prefix_opcodep = NULL; 2387 } 2388 else 2389 { 2390 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix); 2391 2392 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG; 2393 info->target = insn & 15; 2394 2395 if (insn & 0x400) 2396 *tp++ = '+'; 2397 } 2398 *tp++ = ']'; 2399 } 2400 break; 2401 2402 case 'x': 2403 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); 2404 *tp++ = '.'; 2405 *tp++ = mode_char[(insn >> 4) & 3]; 2406 break; 2407 2408 case 'I': 2409 tp = format_dec (insn & 63, tp, 0); 2410 break; 2411 2412 case 'b': 2413 { 2414 int where = buffer[2] + buffer[3] * 256; 2415 2416 if (where > 32767) 2417 where -= 65536; 2418 2419 where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4); 2420 2421 if (insn == BA_PC_INCR_OPCODE) 2422 info->insn_type = dis_branch; 2423 else 2424 info->insn_type = dis_condbranch; 2425 2426 info->target = (bfd_vma) where; 2427 2428 *tp = 0; 2429 tp = temp; 2430 (*info->fprintf_func) (info->stream, "%s%s ", 2431 temp, cris_cc_strings[insn >> 12]); 2432 2433 (*info->print_address_func) ((bfd_vma) where, info); 2434 } 2435 break; 2436 2437 case 'c': 2438 tp = format_dec (insn & 31, tp, 0); 2439 break; 2440 2441 case 'C': 2442 tp = format_dec (insn & 15, tp, 0); 2443 break; 2444 2445 case 'o': 2446 { 2447 long offset = insn & 0xfe; 2448 bfd_vma target; 2449 2450 if (insn & 1) 2451 offset |= ~0xff; 2452 2453 if (opcodep->match == BA_QUICK_OPCODE) 2454 info->insn_type = dis_branch; 2455 else 2456 info->insn_type = dis_condbranch; 2457 2458 target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset; 2459 info->target = target; 2460 *tp = 0; 2461 tp = temp; 2462 (*info->fprintf_func) (info->stream, "%s", temp); 2463 (*info->print_address_func) (target, info); 2464 } 2465 break; 2466 2467 case 'Q': 2468 case 'O': 2469 { 2470 long number = buffer[0]; 2471 2472 if (number > 127) 2473 number = number - 256; 2474 2475 tp = format_dec (number, tp, 1); 2476 *tp++ = ','; 2477 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); 2478 } 2479 break; 2480 2481 case 'f': 2482 tp = print_flags (disdata, insn, tp); 2483 break; 2484 2485 case 'i': 2486 tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1); 2487 break; 2488 2489 case 'P': 2490 { 2491 const struct cris_spec_reg *sregp 2492 = spec_reg_info ((insn >> 12) & 15, disdata->distype); 2493 2494 if (sregp->name == NULL) 2495 /* Should have been caught as a non-match earlier. */ 2496 *tp++ = '?'; 2497 else 2498 { 2499 if (with_reg_prefix) 2500 *tp++ = REGISTER_PREFIX_CHAR; 2501 strcpy (tp, sregp->name); 2502 tp += strlen (tp); 2503 } 2504 } 2505 break; 2506 2507 default: 2508 strcpy (tp, "???"); 2509 tp += 3; 2510 } 2511 } 2512 2513 *tp = 0; 2514 2515 if (prefix_opcodep) 2516 (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")", 2517 prefix_opcodep->name, prefix_opcodep->args); 2518 2519 (*info->fprintf_func) (info->stream, "%s", temp); 2520 2521 /* Get info for matching case-tables, if we don't have any active. 2522 We assume that the last constant seen is used; either in the insn 2523 itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */ 2524 if (TRACE_CASE && case_offset_counter == 0) 2525 { 2526 if (CONST_STRNEQ (opcodep->name, "sub")) 2527 case_offset = last_immediate; 2528 2529 /* It could also be an "add", if there are negative case-values. */ 2530 else if (CONST_STRNEQ (opcodep->name, "add")) 2531 /* The first case is the negated operand to the add. */ 2532 case_offset = -last_immediate; 2533 2534 /* A bound insn will tell us the number of cases. */ 2535 else if (CONST_STRNEQ (opcodep->name, "bound")) 2536 no_of_case_offsets = last_immediate + 1; 2537 2538 /* A jump or jsr or branch breaks the chain of insns for a 2539 case-table, so assume default first-case again. */ 2540 else if (info->insn_type == dis_jsr 2541 || info->insn_type == dis_branch 2542 || info->insn_type == dis_condbranch) 2543 case_offset = 0; 2544 } 2545 } 2546 2547 2548 /* Print the CRIS instruction at address memaddr on stream. Returns 2549 length of the instruction, in bytes. Prefix register names with `$' if 2550 WITH_REG_PREFIX. */ 2551 2552 static int 2553 print_insn_cris_generic (bfd_vma memaddr, 2554 disassemble_info *info, 2555 bfd_boolean with_reg_prefix) 2556 { 2557 int nbytes; 2558 unsigned int insn; 2559 const struct cris_opcode *matchedp; 2560 int advance = 0; 2561 struct cris_disasm_data *disdata 2562 = (struct cris_disasm_data *) info->private_data; 2563 2564 /* No instruction will be disassembled as longer than this number of 2565 bytes; stacked prefixes will not be expanded. */ 2566 unsigned char buffer[MAX_BYTES_PER_CRIS_INSN]; 2567 unsigned char *bufp; 2568 int status = 0; 2569 bfd_vma addr; 2570 2571 /* There will be an "out of range" error after the last instruction. 2572 Reading pairs of bytes in decreasing number, we hope that we will get 2573 at least the amount that we will consume. 2574 2575 If we can't get any data, or we do not get enough data, we print 2576 the error message. */ 2577 2578 nbytes = info->buffer_length ? info->buffer_length 2579 : MAX_BYTES_PER_CRIS_INSN; 2580 nbytes = MIN(nbytes, MAX_BYTES_PER_CRIS_INSN); 2581 status = (*info->read_memory_func) (memaddr, buffer, nbytes, info); 2582 2583 /* If we did not get all we asked for, then clear the rest. 2584 Hopefully this makes a reproducible result in case of errors. */ 2585 if (nbytes != MAX_BYTES_PER_CRIS_INSN) 2586 memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes); 2587 2588 addr = memaddr; 2589 bufp = buffer; 2590 2591 /* Set some defaults for the insn info. */ 2592 info->insn_info_valid = 1; 2593 info->branch_delay_insns = 0; 2594 info->data_size = 0; 2595 info->insn_type = dis_nonbranch; 2596 info->flags = 0; 2597 info->target = 0; 2598 info->target2 = 0; 2599 2600 /* If we got any data, disassemble it. */ 2601 if (nbytes != 0) 2602 { 2603 matchedp = NULL; 2604 2605 insn = bufp[0] + bufp[1] * 256; 2606 2607 /* If we're in a case-table, don't disassemble the offsets. */ 2608 if (TRACE_CASE && case_offset_counter != 0) 2609 { 2610 info->insn_type = dis_noninsn; 2611 advance += 2; 2612 2613 /* If to print data as offsets, then shortcut here. */ 2614 (*info->fprintf_func) (info->stream, "case %ld%s: -> ", 2615 case_offset + no_of_case_offsets 2616 - case_offset_counter, 2617 case_offset_counter == 1 ? "/default" : 2618 ""); 2619 2620 (*info->print_address_func) ((bfd_vma) 2621 ((short) (insn) 2622 + (long) (addr 2623 - (no_of_case_offsets 2624 - case_offset_counter) 2625 * 2)), info); 2626 case_offset_counter--; 2627 2628 /* The default case start (without a "sub" or "add") must be 2629 zero. */ 2630 if (case_offset_counter == 0) 2631 case_offset = 0; 2632 } 2633 else if (insn == 0) 2634 { 2635 /* We're often called to disassemble zeroes. While this is a 2636 valid "bcc .+2" insn, it is also useless enough and enough 2637 of a nuiscance that we will just output "bcc .+2" for it 2638 and signal it as a noninsn. */ 2639 (*info->fprintf_func) (info->stream, 2640 disdata->distype == cris_dis_v32 2641 ? "bcc ." : "bcc .+2"); 2642 info->insn_type = dis_noninsn; 2643 advance += 2; 2644 } 2645 else 2646 { 2647 const struct cris_opcode *prefix_opcodep = NULL; 2648 unsigned char *prefix_buffer = bufp; 2649 unsigned int prefix_insn = insn; 2650 int prefix_size = 0; 2651 2652 matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata); 2653 2654 /* Check if we're supposed to write out prefixes as address 2655 modes and if this was a prefix. */ 2656 if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p') 2657 { 2658 /* If it's a prefix, put it into the prefix vars and get the 2659 main insn. */ 2660 prefix_size = bytes_to_skip (prefix_insn, matchedp, 2661 disdata->distype, NULL); 2662 prefix_opcodep = matchedp; 2663 2664 insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256; 2665 matchedp = get_opcode_entry (insn, prefix_insn, disdata); 2666 2667 if (matchedp != NULL) 2668 { 2669 addr += prefix_size; 2670 bufp += prefix_size; 2671 advance += prefix_size; 2672 } 2673 else 2674 { 2675 /* The "main" insn wasn't valid, at least not when 2676 prefixed. Put back things enough to output the 2677 prefix insn only, as a normal insn. */ 2678 matchedp = prefix_opcodep; 2679 insn = prefix_insn; 2680 prefix_opcodep = NULL; 2681 } 2682 } 2683 2684 if (matchedp == NULL) 2685 { 2686 (*info->fprintf_func) (info->stream, "??0x%x", insn); 2687 advance += 2; 2688 2689 info->insn_type = dis_noninsn; 2690 } 2691 else 2692 { 2693 advance 2694 += bytes_to_skip (insn, matchedp, disdata->distype, 2695 prefix_opcodep); 2696 2697 /* The info_type and assorted fields will be set according 2698 to the operands. */ 2699 print_with_operands (matchedp, insn, bufp, addr, info, 2700 prefix_opcodep, prefix_insn, 2701 prefix_buffer, with_reg_prefix); 2702 } 2703 } 2704 } 2705 else 2706 info->insn_type = dis_noninsn; 2707 2708 /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error 2709 status when reading that much, and the insn decoding indicated a 2710 length exceeding what we read, there is an error. */ 2711 if (status != 0 && (nbytes == 0 || advance > nbytes)) 2712 { 2713 (*info->memory_error_func) (status, memaddr, info); 2714 return -1; 2715 } 2716 2717 /* Max supported insn size with one folded prefix insn. */ 2718 info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN; 2719 2720 /* I would like to set this to a fixed value larger than the actual 2721 number of bytes to print in order to avoid spaces between bytes, 2722 but objdump.c (2.9.1) does not like that, so we print 16-bit 2723 chunks, which is the next choice. */ 2724 info->bytes_per_chunk = 2; 2725 2726 /* Printing bytes in order of increasing addresses makes sense, 2727 especially on a little-endian target. 2728 This is completely the opposite of what you think; setting this to 2729 BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N 2730 we want. */ 2731 info->display_endian = BFD_ENDIAN_BIG; 2732 2733 return advance; 2734 } 2735 2736 /* Disassemble, prefixing register names with `$'. CRIS v0..v10. */ 2737 static int 2738 print_insn_cris_with_register_prefix (bfd_vma vma, 2739 disassemble_info *info) 2740 { 2741 if (info->private_data == NULL 2742 && !cris_parse_disassembler_options (info, cris_dis_v0_v10)) 2743 return -1; 2744 return print_insn_cris_generic (vma, info, true); 2745 } 2746 /* Disassemble, prefixing register names with `$'. CRIS v32. */ 2747 2748 static int 2749 print_insn_crisv32_with_register_prefix (bfd_vma vma, 2750 disassemble_info *info) 2751 { 2752 if (info->private_data == NULL 2753 && !cris_parse_disassembler_options (info, cris_dis_v32)) 2754 return -1; 2755 return print_insn_cris_generic (vma, info, true); 2756 } 2757 2758 #if 0 2759 /* Disassemble, prefixing register names with `$'. 2760 Common v10 and v32 subset. */ 2761 2762 static int 2763 print_insn_crisv10_v32_with_register_prefix (bfd_vma vma, 2764 disassemble_info *info) 2765 { 2766 if (info->private_data == NULL 2767 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32)) 2768 return -1; 2769 return print_insn_cris_generic (vma, info, true); 2770 } 2771 2772 /* Disassemble, no prefixes on register names. CRIS v0..v10. */ 2773 2774 static int 2775 print_insn_cris_without_register_prefix (bfd_vma vma, 2776 disassemble_info *info) 2777 { 2778 if (info->private_data == NULL 2779 && !cris_parse_disassembler_options (info, cris_dis_v0_v10)) 2780 return -1; 2781 return print_insn_cris_generic (vma, info, false); 2782 } 2783 2784 /* Disassemble, no prefixes on register names. CRIS v32. */ 2785 2786 static int 2787 print_insn_crisv32_without_register_prefix (bfd_vma vma, 2788 disassemble_info *info) 2789 { 2790 if (info->private_data == NULL 2791 && !cris_parse_disassembler_options (info, cris_dis_v32)) 2792 return -1; 2793 return print_insn_cris_generic (vma, info, false); 2794 } 2795 2796 /* Disassemble, no prefixes on register names. 2797 Common v10 and v32 subset. */ 2798 2799 static int 2800 print_insn_crisv10_v32_without_register_prefix (bfd_vma vma, 2801 disassemble_info *info) 2802 { 2803 if (info->private_data == NULL 2804 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32)) 2805 return -1; 2806 return print_insn_cris_generic (vma, info, false); 2807 } 2808 #endif 2809 2810 int 2811 print_insn_crisv10 (bfd_vma vma, 2812 disassemble_info *info) 2813 { 2814 return print_insn_cris_with_register_prefix(vma, info); 2815 } 2816 2817 int 2818 print_insn_crisv32 (bfd_vma vma, 2819 disassemble_info *info) 2820 { 2821 return print_insn_crisv32_with_register_prefix(vma, info); 2822 } 2823 2824 /* Return a disassembler-function that prints registers with a `$' prefix, 2825 or one that prints registers without a prefix. 2826 FIXME: We should improve the solution to avoid the multitude of 2827 functions seen above. */ 2828 #if 0 2829 disassembler_ftype 2830 cris_get_disassembler (bfd *abfd) 2831 { 2832 /* If there's no bfd in sight, we return what is valid as input in all 2833 contexts if fed back to the assembler: disassembly *with* register 2834 prefix. Unfortunately this will be totally wrong for v32. */ 2835 if (abfd == NULL) 2836 return print_insn_cris_with_register_prefix; 2837 2838 if (bfd_get_symbol_leading_char (abfd) == 0) 2839 { 2840 if (bfd_get_mach (abfd) == bfd_mach_cris_v32) 2841 return print_insn_crisv32_with_register_prefix; 2842 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32) 2843 return print_insn_crisv10_v32_with_register_prefix; 2844 2845 /* We default to v10. This may be specifically specified in the 2846 bfd mach, but is also the default setting. */ 2847 return print_insn_cris_with_register_prefix; 2848 } 2849 2850 if (bfd_get_mach (abfd) == bfd_mach_cris_v32) 2851 return print_insn_crisv32_without_register_prefix; 2852 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32) 2853 return print_insn_crisv10_v32_without_register_prefix; 2854 return print_insn_cris_without_register_prefix; 2855 } 2856 #endif 2857 /* Local variables: 2858 eval: (c-set-style "gnu") 2859 indent-tabs-mode: t 2860 End: */ 2861