1 /* alpha-dis.c -- Disassemble Alpha AXP instructions 2 Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. 3 Contributed by Richard Henderson <rth@tamu.edu>, 4 patterned after the PPC opcode handling written by Ian Lance Taylor. 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 11 2, or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, see 20 <http://www.gnu.org/licenses/>. */ 21 22 #include "qemu/osdep.h" 23 #include "disas/dis-asm.h" 24 25 /* MAX is redefined below, so remove any previous definition. */ 26 #undef MAX 27 28 /* The opcode table is an array of struct alpha_opcode. */ 29 30 struct alpha_opcode 31 { 32 /* The opcode name. */ 33 const char *name; 34 35 /* The opcode itself. Those bits which will be filled in with 36 operands are zeroes. */ 37 unsigned opcode; 38 39 /* The opcode mask. This is used by the disassembler. This is a 40 mask containing ones indicating those bits which must match the 41 opcode field, and zeroes indicating those bits which need not 42 match (and are presumably filled in by operands). */ 43 unsigned mask; 44 45 /* One bit flags for the opcode. These are primarily used to 46 indicate specific processors and environments support the 47 instructions. The defined values are listed below. */ 48 unsigned flags; 49 50 /* An array of operand codes. Each code is an index into the 51 operand table. They appear in the order which the operands must 52 appear in assembly code, and are terminated by a zero. */ 53 unsigned char operands[4]; 54 }; 55 56 /* The table itself is sorted by major opcode number, and is otherwise 57 in the order in which the disassembler should consider 58 instructions. */ 59 extern const struct alpha_opcode alpha_opcodes[]; 60 extern const unsigned alpha_num_opcodes; 61 62 /* Values defined for the flags field of a struct alpha_opcode. */ 63 64 /* CPU Availability */ 65 #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ 66 #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ 67 #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ 68 #define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ 69 #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ 70 #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ 71 #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ 72 73 #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) 74 75 /* A macro to extract the major opcode from an instruction. */ 76 #define AXP_OP(i) (((i) >> 26) & 0x3F) 77 78 /* The total number of major opcodes. */ 79 #define AXP_NOPS 0x40 80 81 82 /* The operands table is an array of struct alpha_operand. */ 83 84 struct alpha_operand 85 { 86 /* The number of bits in the operand. */ 87 unsigned int bits : 5; 88 89 /* How far the operand is left shifted in the instruction. */ 90 unsigned int shift : 5; 91 92 /* The default relocation type for this operand. */ 93 signed int default_reloc : 16; 94 95 /* One bit syntax flags. */ 96 unsigned int flags : 16; 97 98 /* Insertion function. This is used by the assembler. To insert an 99 operand value into an instruction, check this field. 100 101 If it is NULL, execute 102 i |= (op & ((1 << o->bits) - 1)) << o->shift; 103 (i is the instruction which we are filling in, o is a pointer to 104 this structure, and op is the opcode value; this assumes twos 105 complement arithmetic). 106 107 If this field is not NULL, then simply call it with the 108 instruction and the operand value. It will return the new value 109 of the instruction. If the ERRMSG argument is not NULL, then if 110 the operand value is illegal, *ERRMSG will be set to a warning 111 string (the operand will be inserted in any case). If the 112 operand value is legal, *ERRMSG will be unchanged (most operands 113 can accept any value). */ 114 unsigned (*insert) (unsigned instruction, int op, 115 const char **errmsg); 116 117 /* Extraction function. This is used by the disassembler. To 118 extract this operand type from an instruction, check this field. 119 120 If it is NULL, compute 121 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 122 if ((o->flags & AXP_OPERAND_SIGNED) != 0 123 && (op & (1 << (o->bits - 1))) != 0) 124 op -= 1 << o->bits; 125 (i is the instruction, o is a pointer to this structure, and op 126 is the result; this assumes twos complement arithmetic). 127 128 If this field is not NULL, then simply call it with the 129 instruction value. It will return the value of the operand. If 130 the INVALID argument is not NULL, *INVALID will be set to 131 non-zero if this operand type can not actually be extracted from 132 this operand (i.e., the instruction does not match). If the 133 operand is valid, *INVALID will not be changed. */ 134 int (*extract) (unsigned instruction, int *invalid); 135 }; 136 137 /* Elements in the table are retrieved by indexing with values from 138 the operands field of the alpha_opcodes table. */ 139 140 extern const struct alpha_operand alpha_operands[]; 141 extern const unsigned alpha_num_operands; 142 143 /* Values defined for the flags field of a struct alpha_operand. */ 144 145 /* Mask for selecting the type for typecheck purposes */ 146 #define AXP_OPERAND_TYPECHECK_MASK \ 147 (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \ 148 AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \ 149 AXP_OPERAND_UNSIGNED) 150 151 /* This operand does not actually exist in the assembler input. This 152 is used to support extended mnemonics, for which two operands fields 153 are identical. The assembler should call the insert function with 154 any op value. The disassembler should call the extract function, 155 ignore the return value, and check the value placed in the invalid 156 argument. */ 157 #define AXP_OPERAND_FAKE 01 158 159 /* The operand should be wrapped in parentheses rather than separated 160 from the previous by a comma. This is used for the load and store 161 instructions which want their operands to look like "Ra,disp(Rb)". */ 162 #define AXP_OPERAND_PARENS 02 163 164 /* Used in combination with PARENS, this suppresses the suppression of 165 the comma. This is used for "jmp Ra,(Rb),hint". */ 166 #define AXP_OPERAND_COMMA 04 167 168 /* This operand names an integer register. */ 169 #define AXP_OPERAND_IR 010 170 171 /* This operand names a floating point register. */ 172 #define AXP_OPERAND_FPR 020 173 174 /* This operand is a relative branch displacement. The disassembler 175 prints these symbolically if possible. */ 176 #define AXP_OPERAND_RELATIVE 040 177 178 /* This operand takes signed values. */ 179 #define AXP_OPERAND_SIGNED 0100 180 181 /* This operand takes unsigned values. This exists primarily so that 182 a flags value of 0 can be treated as end-of-arguments. */ 183 #define AXP_OPERAND_UNSIGNED 0200 184 185 /* Suppress overflow detection on this field. This is used for hints. */ 186 #define AXP_OPERAND_NOOVERFLOW 0400 187 188 /* Mask for optional argument default value. */ 189 #define AXP_OPERAND_OPTIONAL_MASK 07000 190 191 /* This operand defaults to zero. This is used for jump hints. */ 192 #define AXP_OPERAND_DEFAULT_ZERO 01000 193 194 /* This operand should default to the first (real) operand and is used 195 in conjunction with AXP_OPERAND_OPTIONAL. This allows 196 "and $0,3,$0" to be written as "and $0,3", etc. I don't like 197 it, but it's what DEC does. */ 198 #define AXP_OPERAND_DEFAULT_FIRST 02000 199 200 /* Similarly, this operand should default to the second (real) operand. 201 This allows "negl $0" instead of "negl $0,$0". */ 202 #define AXP_OPERAND_DEFAULT_SECOND 04000 203 204 205 /* Register common names */ 206 207 #define AXP_REG_V0 0 208 #define AXP_REG_T0 1 209 #define AXP_REG_T1 2 210 #define AXP_REG_T2 3 211 #define AXP_REG_T3 4 212 #define AXP_REG_T4 5 213 #define AXP_REG_T5 6 214 #define AXP_REG_T6 7 215 #define AXP_REG_T7 8 216 #define AXP_REG_S0 9 217 #define AXP_REG_S1 10 218 #define AXP_REG_S2 11 219 #define AXP_REG_S3 12 220 #define AXP_REG_S4 13 221 #define AXP_REG_S5 14 222 #define AXP_REG_FP 15 223 #define AXP_REG_A0 16 224 #define AXP_REG_A1 17 225 #define AXP_REG_A2 18 226 #define AXP_REG_A3 19 227 #define AXP_REG_A4 20 228 #define AXP_REG_A5 21 229 #define AXP_REG_T8 22 230 #define AXP_REG_T9 23 231 #define AXP_REG_T10 24 232 #define AXP_REG_T11 25 233 #define AXP_REG_RA 26 234 #define AXP_REG_PV 27 235 #define AXP_REG_T12 27 236 #define AXP_REG_AT 28 237 #define AXP_REG_GP 29 238 #define AXP_REG_SP 30 239 #define AXP_REG_ZERO 31 240 241 enum bfd_reloc_code_real { 242 BFD_RELOC_23_PCREL_S2, 243 BFD_RELOC_ALPHA_HINT 244 }; 245 246 /* This file holds the Alpha AXP opcode table. The opcode table includes 247 almost all of the extended instruction mnemonics. This permits the 248 disassembler to use them, and simplifies the assembler logic, at the 249 cost of increasing the table size. The table is strictly constant 250 data, so the compiler should be able to put it in the text segment. 251 252 This file also holds the operand table. All knowledge about inserting 253 and extracting operands from instructions is kept in this file. 254 255 The information for the base instruction set was compiled from the 256 _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE, 257 version 2. 258 259 The information for the post-ev5 architecture extensions BWX, CIX and 260 MAX came from version 3 of this same document, which is also available 261 on-line at http://ftp.digital.com/pub/Digital/info/semiconductor 262 /literature/alphahb2.pdf 263 264 The information for the EV4 PALcode instructions was compiled from 265 _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware 266 Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary 267 revision dated June 1994. 268 269 The information for the EV5 PALcode instructions was compiled from 270 _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital 271 Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */ 272 273 /* Local insertion and extraction functions */ 274 275 static unsigned insert_rba (unsigned, int, const char **); 276 static unsigned insert_rca (unsigned, int, const char **); 277 static unsigned insert_za (unsigned, int, const char **); 278 static unsigned insert_zb (unsigned, int, const char **); 279 static unsigned insert_zc (unsigned, int, const char **); 280 static unsigned insert_bdisp (unsigned, int, const char **); 281 static unsigned insert_jhint (unsigned, int, const char **); 282 static unsigned insert_ev6hwjhint (unsigned, int, const char **); 283 284 static int extract_rba (unsigned, int *); 285 static int extract_rca (unsigned, int *); 286 static int extract_za (unsigned, int *); 287 static int extract_zb (unsigned, int *); 288 static int extract_zc (unsigned, int *); 289 static int extract_bdisp (unsigned, int *); 290 static int extract_jhint (unsigned, int *); 291 static int extract_ev6hwjhint (unsigned, int *); 292 293 294 /* The operands table */ 295 296 const struct alpha_operand alpha_operands[] = 297 { 298 /* The fields are bits, shift, insert, extract, flags */ 299 /* The zero index is used to indicate end-of-list */ 300 #define UNUSED 0 301 { 0, 0, 0, 0, 0, 0 }, 302 303 /* The plain integer register fields */ 304 #define RA (UNUSED + 1) 305 { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, 306 #define RB (RA + 1) 307 { 5, 16, 0, AXP_OPERAND_IR, 0, 0 }, 308 #define RC (RB + 1) 309 { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, 310 311 /* The plain fp register fields */ 312 #define FA (RC + 1) 313 { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, 314 #define FB (FA + 1) 315 { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 }, 316 #define FC (FB + 1) 317 { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, 318 319 /* The integer registers when they are ZERO */ 320 #define ZA (FC + 1) 321 { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, 322 #define ZB (ZA + 1) 323 { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb }, 324 #define ZC (ZB + 1) 325 { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, 326 327 /* The RB field when it needs parentheses */ 328 #define PRB (ZC + 1) 329 { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, 330 331 /* The RB field when it needs parentheses _and_ a preceding comma */ 332 #define CPRB (PRB + 1) 333 { 5, 16, 0, 334 AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, 335 336 /* The RB field when it must be the same as the RA field */ 337 #define RBA (CPRB + 1) 338 { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, 339 340 /* The RC field when it must be the same as the RB field */ 341 #define RCA (RBA + 1) 342 { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, 343 344 /* The RC field when it can *default* to RA */ 345 #define DRC1 (RCA + 1) 346 { 5, 0, 0, 347 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 348 349 /* The RC field when it can *default* to RB */ 350 #define DRC2 (DRC1 + 1) 351 { 5, 0, 0, 352 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 353 354 /* The FC field when it can *default* to RA */ 355 #define DFC1 (DRC2 + 1) 356 { 5, 0, 0, 357 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 358 359 /* The FC field when it can *default* to RB */ 360 #define DFC2 (DFC1 + 1) 361 { 5, 0, 0, 362 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 363 364 /* The unsigned 8-bit literal of Operate format insns */ 365 #define LIT (DFC2 + 1) 366 { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, 367 368 /* The signed 16-bit displacement of Memory format insns. From here 369 we can't tell what relocation should be used, so don't use a default. */ 370 #define MDISP (LIT + 1) 371 { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, 372 373 /* The signed "23-bit" aligned displacement of Branch format insns */ 374 #define BDISP (MDISP + 1) 375 { 21, 0, BFD_RELOC_23_PCREL_S2, 376 AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, 377 378 /* The 26-bit PALcode function */ 379 #define PALFN (BDISP + 1) 380 { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, 381 382 /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */ 383 #define JMPHINT (PALFN + 1) 384 { 14, 0, BFD_RELOC_ALPHA_HINT, 385 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, 386 insert_jhint, extract_jhint }, 387 388 /* The optional hint to RET/JSR_COROUTINE */ 389 #define RETHINT (JMPHINT + 1) 390 { 14, 0, -RETHINT, 391 AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, 392 393 /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */ 394 #define EV4HWDISP (RETHINT + 1) 395 #define EV6HWDISP (EV4HWDISP) 396 { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 397 398 /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */ 399 #define EV4HWINDEX (EV4HWDISP + 1) 400 { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 401 402 /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns 403 that occur in DEC PALcode. */ 404 #define EV4EXTHWINDEX (EV4HWINDEX + 1) 405 { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 406 407 /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */ 408 #define EV5HWDISP (EV4EXTHWINDEX + 1) 409 { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 410 411 /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */ 412 #define EV5HWINDEX (EV5HWDISP + 1) 413 { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 414 415 /* The 16-bit combined index/scoreboard mask for the ev6 416 hw_m[ft]pr (pal19/pal1d) insns */ 417 #define EV6HWINDEX (EV5HWINDEX + 1) 418 { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 419 420 /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */ 421 #define EV6HWJMPHINT (EV6HWINDEX+ 1) 422 { 8, 0, -EV6HWJMPHINT, 423 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, 424 insert_ev6hwjhint, extract_ev6hwjhint } 425 }; 426 427 const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); 428 429 /* The RB field when it is the same as the RA field in the same insn. 430 This operand is marked fake. The insertion function just copies 431 the RA field into the RB field, and the extraction function just 432 checks that the fields are the same. */ 433 434 /*ARGSUSED*/ 435 static unsigned 436 insert_rba(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED) 437 { 438 return insn | (((insn >> 21) & 0x1f) << 16); 439 } 440 441 static int 442 extract_rba(unsigned insn, int *invalid) 443 { 444 if (invalid != (int *) NULL 445 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 446 *invalid = 1; 447 return 0; 448 } 449 450 451 /* The same for the RC field */ 452 453 /*ARGSUSED*/ 454 static unsigned 455 insert_rca(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED) 456 { 457 return insn | ((insn >> 21) & 0x1f); 458 } 459 460 static int 461 extract_rca(unsigned insn, int *invalid) 462 { 463 if (invalid != (int *) NULL 464 && ((insn >> 21) & 0x1f) != (insn & 0x1f)) 465 *invalid = 1; 466 return 0; 467 } 468 469 470 /* Fake arguments in which the registers must be set to ZERO */ 471 472 /*ARGSUSED*/ 473 static unsigned 474 insert_za(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED) 475 { 476 return insn | (31 << 21); 477 } 478 479 static int 480 extract_za(unsigned insn, int *invalid) 481 { 482 if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) 483 *invalid = 1; 484 return 0; 485 } 486 487 /*ARGSUSED*/ 488 static unsigned 489 insert_zb(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED) 490 { 491 return insn | (31 << 16); 492 } 493 494 static int 495 extract_zb(unsigned insn, int *invalid) 496 { 497 if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) 498 *invalid = 1; 499 return 0; 500 } 501 502 /*ARGSUSED*/ 503 static unsigned 504 insert_zc(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED) 505 { 506 return insn | 31; 507 } 508 509 static int 510 extract_zc(unsigned insn, int *invalid) 511 { 512 if (invalid != (int *) NULL && (insn & 0x1f) != 31) 513 *invalid = 1; 514 return 0; 515 } 516 517 518 /* The displacement field of a Branch format insn. */ 519 520 static unsigned 521 insert_bdisp(unsigned insn, int value, const char **errmsg) 522 { 523 if (errmsg != (const char **)NULL && (value & 3)) 524 *errmsg = "branch operand unaligned"; 525 return insn | ((value / 4) & 0x1FFFFF); 526 } 527 528 /*ARGSUSED*/ 529 static int 530 extract_bdisp(unsigned insn, int *invalid ATTRIBUTE_UNUSED) 531 { 532 return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); 533 } 534 535 536 /* The hint field of a JMP/JSR insn. */ 537 538 static unsigned 539 insert_jhint(unsigned insn, int value, const char **errmsg) 540 { 541 if (errmsg != (const char **)NULL && (value & 3)) 542 *errmsg = "jump hint unaligned"; 543 return insn | ((value / 4) & 0x3FFF); 544 } 545 546 /*ARGSUSED*/ 547 static int 548 extract_jhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED) 549 { 550 return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); 551 } 552 553 /* The hint field of an EV6 HW_JMP/JSR insn. */ 554 555 static unsigned 556 insert_ev6hwjhint(unsigned insn, int value, const char **errmsg) 557 { 558 if (errmsg != (const char **)NULL && (value & 3)) 559 *errmsg = "jump hint unaligned"; 560 return insn | ((value / 4) & 0x1FFF); 561 } 562 563 /*ARGSUSED*/ 564 static int 565 extract_ev6hwjhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED) 566 { 567 return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); 568 } 569 570 571 /* Macros used to form opcodes */ 572 573 /* The main opcode */ 574 #define OP(x) (((x) & 0x3F) << 26) 575 #define OP_MASK 0xFC000000 576 577 /* Branch format instructions */ 578 #define BRA_(oo) OP(oo) 579 #define BRA_MASK OP_MASK 580 #define BRA(oo) BRA_(oo), BRA_MASK 581 582 /* Floating point format instructions */ 583 #define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) 584 #define FP_MASK (OP_MASK | 0xFFE0) 585 #define FP(oo,fff) FP_(oo,fff), FP_MASK 586 587 /* Memory format instructions */ 588 #define MEM_(oo) OP(oo) 589 #define MEM_MASK OP_MASK 590 #define MEM(oo) MEM_(oo), MEM_MASK 591 592 /* Memory/Func Code format instructions */ 593 #define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) 594 #define MFC_MASK (OP_MASK | 0xFFFF) 595 #define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK 596 597 /* Memory/Branch format instructions */ 598 #define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) 599 #define MBR_MASK (OP_MASK | 0xC000) 600 #define MBR(oo,h) MBR_(oo,h), MBR_MASK 601 602 /* Operate format instructions. The OPRL variant specifies a 603 literal second argument. */ 604 #define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) 605 #define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) 606 #define OPR_MASK (OP_MASK | 0x1FE0) 607 #define OPR(oo,ff) OPR_(oo,ff), OPR_MASK 608 #define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK 609 610 /* Generic PALcode format instructions */ 611 #define PCD_(oo) OP(oo) 612 #define PCD_MASK OP_MASK 613 #define PCD(oo) PCD_(oo), PCD_MASK 614 615 /* Specific PALcode instructions */ 616 #define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) 617 #define SPCD_MASK 0xFFFFFFFF 618 #define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK 619 620 /* Hardware memory (hw_{ld,st}) instructions */ 621 #define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) 622 #define EV4HWMEM_MASK (OP_MASK | 0xF000) 623 #define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK 624 625 #define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) 626 #define EV5HWMEM_MASK (OP_MASK | 0xF800) 627 #define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK 628 629 #define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) 630 #define EV6HWMEM_MASK (OP_MASK | 0xF000) 631 #define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK 632 633 #define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13)) 634 #define EV6HWMBR_MASK (OP_MASK | 0xE000) 635 #define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK 636 637 /* Abbreviations for instruction subsets. */ 638 #define BASE AXP_OPCODE_BASE 639 #define EV4 AXP_OPCODE_EV4 640 #define EV5 AXP_OPCODE_EV5 641 #define EV6 AXP_OPCODE_EV6 642 #define BWX AXP_OPCODE_BWX 643 #define CIX AXP_OPCODE_CIX 644 #define MAX AXP_OPCODE_MAX 645 646 /* Common combinations of arguments */ 647 #define ARG_NONE { 0 } 648 #define ARG_BRA { RA, BDISP } 649 #define ARG_FBRA { FA, BDISP } 650 #define ARG_FP { FA, FB, DFC1 } 651 #define ARG_FPZ1 { ZA, FB, DFC1 } 652 #define ARG_MEM { RA, MDISP, PRB } 653 #define ARG_FMEM { FA, MDISP, PRB } 654 #define ARG_OPR { RA, RB, DRC1 } 655 #define ARG_OPRL { RA, LIT, DRC1 } 656 #define ARG_OPRZ1 { ZA, RB, DRC1 } 657 #define ARG_OPRLZ1 { ZA, LIT, RC } 658 #define ARG_PCD { PALFN } 659 #define ARG_EV4HWMEM { RA, EV4HWDISP, PRB } 660 #define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX } 661 #define ARG_EV5HWMEM { RA, EV5HWDISP, PRB } 662 #define ARG_EV6HWMEM { RA, EV6HWDISP, PRB } 663 664 /* The opcode table. 665 666 The format of the opcode table is: 667 668 NAME OPCODE MASK { OPERANDS } 669 670 NAME is the name of the instruction. 671 672 OPCODE is the instruction opcode. 673 674 MASK is the opcode mask; this is used to tell the disassembler 675 which bits in the actual opcode must match OPCODE. 676 677 OPERANDS is the list of operands. 678 679 The preceding macros merge the text of the OPCODE and MASK fields. 680 681 The disassembler reads the table in order and prints the first 682 instruction which matches, so this table is sorted to put more 683 specific instructions before more general instructions. 684 685 Otherwise, it is sorted by major opcode and minor function code. 686 687 There are three classes of not-really-instructions in this table: 688 689 ALIAS is another name for another instruction. Some of 690 these come from the Architecture Handbook, some 691 come from the original gas opcode tables. In all 692 cases, the functionality of the opcode is unchanged. 693 694 PSEUDO a stylized code form endorsed by Chapter A.4 of the 695 Architecture Handbook. 696 697 EXTRA a stylized code form found in the original gas tables. 698 699 And two annotations: 700 701 EV56 BUT opcodes that are officially introduced as of the ev56, 702 but with defined results on previous implementations. 703 704 EV56 UNA opcodes that were introduced as of the ev56 with 705 presumably undefined results on previous implementations 706 that were not assigned to a particular extension. 707 */ 708 709 const struct alpha_opcode alpha_opcodes[] = { 710 { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, 711 { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, 712 { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, 713 { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE }, 714 { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, 715 { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, 716 { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, 717 { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE }, 718 { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE }, 719 { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE }, 720 { "call_pal", PCD(0x00), BASE, ARG_PCD }, 721 { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ 722 723 { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */ 724 { "lda", MEM(0x08), BASE, ARG_MEM }, 725 { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */ 726 { "ldah", MEM(0x09), BASE, ARG_MEM }, 727 { "ldbu", MEM(0x0A), BWX, ARG_MEM }, 728 { "unop", MEM_(0x0B) | (30 << 16), 729 MEM_MASK, BASE, { ZA } }, /* pseudo */ 730 { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, 731 { "ldwu", MEM(0x0C), BWX, ARG_MEM }, 732 { "stw", MEM(0x0D), BWX, ARG_MEM }, 733 { "stb", MEM(0x0E), BWX, ARG_MEM }, 734 { "stq_u", MEM(0x0F), BASE, ARG_MEM }, 735 736 { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ 737 { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ 738 { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, 739 { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, 740 { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, 741 { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, 742 { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ 743 { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ 744 { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, 745 { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, 746 { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, 747 { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, 748 { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, 749 { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, 750 { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, 751 { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, 752 { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, 753 { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, 754 { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, 755 { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, 756 { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, 757 { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, 758 { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, 759 { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, 760 { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ 761 { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ 762 { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, 763 { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, 764 { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, 765 { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, 766 { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, 767 { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, 768 { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, 769 { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, 770 { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, 771 { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, 772 { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, 773 { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, 774 { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, 775 { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, 776 { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ 777 { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ 778 { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, 779 { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, 780 { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, 781 { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, 782 { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, 783 { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, 784 { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ 785 { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ 786 { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, 787 { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, 788 { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, 789 { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, 790 791 { "and", OPR(0x11,0x00), BASE, ARG_OPR }, 792 { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, 793 { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ 794 { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ 795 { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, 796 { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, 797 { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, 798 { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, 799 { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, 800 { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, 801 { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ 802 { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ 803 { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ 804 { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ 805 { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ 806 { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ 807 { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ 808 { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, 809 { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, 810 { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, 811 { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, 812 { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, 813 { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, 814 { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ 815 { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ 816 { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, 817 { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, 818 { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, 819 { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, 820 { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, 821 { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, 822 { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, 823 { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, 824 { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, 825 { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, 826 { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ 827 { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ 828 { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ 829 { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ 830 { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, 831 { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, 832 { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, 833 { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, 834 { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), 835 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ 836 837 { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, 838 { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, 839 { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, 840 { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, 841 { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, 842 { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, 843 { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, 844 { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, 845 { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, 846 { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, 847 { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, 848 { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, 849 { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, 850 { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, 851 { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, 852 { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, 853 { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, 854 { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, 855 { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, 856 { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, 857 { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, 858 { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, 859 { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, 860 { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, 861 { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, 862 { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, 863 { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, 864 { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, 865 { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, 866 { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, 867 { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, 868 { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, 869 { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, 870 { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, 871 { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, 872 { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, 873 { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, 874 { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, 875 { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, 876 { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, 877 { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, 878 { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, 879 { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, 880 { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, 881 { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, 882 { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, 883 { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, 884 { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, 885 { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, 886 { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, 887 { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, 888 { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, 889 890 { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, 891 { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, 892 { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, 893 { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, 894 { "umulh", OPR(0x13,0x30), BASE, ARG_OPR }, 895 { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL }, 896 { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR }, 897 { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL }, 898 { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR }, 899 { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL }, 900 901 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, 902 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 }, 903 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 }, 904 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, 905 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, 906 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 }, 907 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 }, 908 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }, 909 { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 }, 910 { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 }, 911 { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 }, 912 { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 }, 913 { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 }, 914 { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 }, 915 { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 }, 916 { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 }, 917 { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 }, 918 { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 }, 919 { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 }, 920 { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 }, 921 { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 }, 922 { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 }, 923 { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 }, 924 { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 }, 925 { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 }, 926 { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 }, 927 { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 }, 928 { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 }, 929 { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 }, 930 { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 }, 931 { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 }, 932 { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 }, 933 { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 }, 934 { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 }, 935 { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 }, 936 { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 }, 937 { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 }, 938 { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 }, 939 { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 }, 940 { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 }, 941 { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 }, 942 { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 }, 943 { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 }, 944 { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 }, 945 { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 }, 946 { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 }, 947 { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 }, 948 { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 }, 949 { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 }, 950 { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 }, 951 { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 }, 952 953 { "addf/c", FP(0x15,0x000), BASE, ARG_FP }, 954 { "subf/c", FP(0x15,0x001), BASE, ARG_FP }, 955 { "mulf/c", FP(0x15,0x002), BASE, ARG_FP }, 956 { "divf/c", FP(0x15,0x003), BASE, ARG_FP }, 957 { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 }, 958 { "addg/c", FP(0x15,0x020), BASE, ARG_FP }, 959 { "subg/c", FP(0x15,0x021), BASE, ARG_FP }, 960 { "mulg/c", FP(0x15,0x022), BASE, ARG_FP }, 961 { "divg/c", FP(0x15,0x023), BASE, ARG_FP }, 962 { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 }, 963 { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 }, 964 { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 }, 965 { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 }, 966 { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 }, 967 { "addf", FP(0x15,0x080), BASE, ARG_FP }, 968 { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 969 { "subf", FP(0x15,0x081), BASE, ARG_FP }, 970 { "mulf", FP(0x15,0x082), BASE, ARG_FP }, 971 { "divf", FP(0x15,0x083), BASE, ARG_FP }, 972 { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 }, 973 { "addg", FP(0x15,0x0A0), BASE, ARG_FP }, 974 { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 975 { "subg", FP(0x15,0x0A1), BASE, ARG_FP }, 976 { "mulg", FP(0x15,0x0A2), BASE, ARG_FP }, 977 { "divg", FP(0x15,0x0A3), BASE, ARG_FP }, 978 { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP }, 979 { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP }, 980 { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP }, 981 { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 }, 982 { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 }, 983 { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 }, 984 { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 }, 985 { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 }, 986 { "addf/uc", FP(0x15,0x100), BASE, ARG_FP }, 987 { "subf/uc", FP(0x15,0x101), BASE, ARG_FP }, 988 { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP }, 989 { "divf/uc", FP(0x15,0x103), BASE, ARG_FP }, 990 { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 }, 991 { "addg/uc", FP(0x15,0x120), BASE, ARG_FP }, 992 { "subg/uc", FP(0x15,0x121), BASE, ARG_FP }, 993 { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP }, 994 { "divg/uc", FP(0x15,0x123), BASE, ARG_FP }, 995 { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 }, 996 { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 }, 997 { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 }, 998 { "addf/u", FP(0x15,0x180), BASE, ARG_FP }, 999 { "subf/u", FP(0x15,0x181), BASE, ARG_FP }, 1000 { "mulf/u", FP(0x15,0x182), BASE, ARG_FP }, 1001 { "divf/u", FP(0x15,0x183), BASE, ARG_FP }, 1002 { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 }, 1003 { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP }, 1004 { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP }, 1005 { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP }, 1006 { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP }, 1007 { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 }, 1008 { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 }, 1009 { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 }, 1010 { "addf/sc", FP(0x15,0x400), BASE, ARG_FP }, 1011 { "subf/sc", FP(0x15,0x401), BASE, ARG_FP }, 1012 { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP }, 1013 { "divf/sc", FP(0x15,0x403), BASE, ARG_FP }, 1014 { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 }, 1015 { "addg/sc", FP(0x15,0x420), BASE, ARG_FP }, 1016 { "subg/sc", FP(0x15,0x421), BASE, ARG_FP }, 1017 { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP }, 1018 { "divg/sc", FP(0x15,0x423), BASE, ARG_FP }, 1019 { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 }, 1020 { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 }, 1021 { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 }, 1022 { "addf/s", FP(0x15,0x480), BASE, ARG_FP }, 1023 { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */ 1024 { "subf/s", FP(0x15,0x481), BASE, ARG_FP }, 1025 { "mulf/s", FP(0x15,0x482), BASE, ARG_FP }, 1026 { "divf/s", FP(0x15,0x483), BASE, ARG_FP }, 1027 { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 }, 1028 { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP }, 1029 { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */ 1030 { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP }, 1031 { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP }, 1032 { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP }, 1033 { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP }, 1034 { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP }, 1035 { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP }, 1036 { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 }, 1037 { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 }, 1038 { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 }, 1039 { "addf/suc", FP(0x15,0x500), BASE, ARG_FP }, 1040 { "subf/suc", FP(0x15,0x501), BASE, ARG_FP }, 1041 { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP }, 1042 { "divf/suc", FP(0x15,0x503), BASE, ARG_FP }, 1043 { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 }, 1044 { "addg/suc", FP(0x15,0x520), BASE, ARG_FP }, 1045 { "subg/suc", FP(0x15,0x521), BASE, ARG_FP }, 1046 { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP }, 1047 { "divg/suc", FP(0x15,0x523), BASE, ARG_FP }, 1048 { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 }, 1049 { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 }, 1050 { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 }, 1051 { "addf/su", FP(0x15,0x580), BASE, ARG_FP }, 1052 { "subf/su", FP(0x15,0x581), BASE, ARG_FP }, 1053 { "mulf/su", FP(0x15,0x582), BASE, ARG_FP }, 1054 { "divf/su", FP(0x15,0x583), BASE, ARG_FP }, 1055 { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 }, 1056 { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP }, 1057 { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP }, 1058 { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP }, 1059 { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP }, 1060 { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 }, 1061 { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 }, 1062 { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 }, 1063 1064 { "adds/c", FP(0x16,0x000), BASE, ARG_FP }, 1065 { "subs/c", FP(0x16,0x001), BASE, ARG_FP }, 1066 { "muls/c", FP(0x16,0x002), BASE, ARG_FP }, 1067 { "divs/c", FP(0x16,0x003), BASE, ARG_FP }, 1068 { "addt/c", FP(0x16,0x020), BASE, ARG_FP }, 1069 { "subt/c", FP(0x16,0x021), BASE, ARG_FP }, 1070 { "mult/c", FP(0x16,0x022), BASE, ARG_FP }, 1071 { "divt/c", FP(0x16,0x023), BASE, ARG_FP }, 1072 { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 }, 1073 { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 }, 1074 { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 }, 1075 { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 }, 1076 { "adds/m", FP(0x16,0x040), BASE, ARG_FP }, 1077 { "subs/m", FP(0x16,0x041), BASE, ARG_FP }, 1078 { "muls/m", FP(0x16,0x042), BASE, ARG_FP }, 1079 { "divs/m", FP(0x16,0x043), BASE, ARG_FP }, 1080 { "addt/m", FP(0x16,0x060), BASE, ARG_FP }, 1081 { "subt/m", FP(0x16,0x061), BASE, ARG_FP }, 1082 { "mult/m", FP(0x16,0x062), BASE, ARG_FP }, 1083 { "divt/m", FP(0x16,0x063), BASE, ARG_FP }, 1084 { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 }, 1085 { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 }, 1086 { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 }, 1087 { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 }, 1088 { "adds", FP(0x16,0x080), BASE, ARG_FP }, 1089 { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 1090 { "subs", FP(0x16,0x081), BASE, ARG_FP }, 1091 { "muls", FP(0x16,0x082), BASE, ARG_FP }, 1092 { "divs", FP(0x16,0x083), BASE, ARG_FP }, 1093 { "addt", FP(0x16,0x0A0), BASE, ARG_FP }, 1094 { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 1095 { "subt", FP(0x16,0x0A1), BASE, ARG_FP }, 1096 { "mult", FP(0x16,0x0A2), BASE, ARG_FP }, 1097 { "divt", FP(0x16,0x0A3), BASE, ARG_FP }, 1098 { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP }, 1099 { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP }, 1100 { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP }, 1101 { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP }, 1102 { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 }, 1103 { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 }, 1104 { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 }, 1105 { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 }, 1106 { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP }, 1107 { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP }, 1108 { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP }, 1109 { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP }, 1110 { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP }, 1111 { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP }, 1112 { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP }, 1113 { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP }, 1114 { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 }, 1115 { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 }, 1116 { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 }, 1117 { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 }, 1118 { "adds/uc", FP(0x16,0x100), BASE, ARG_FP }, 1119 { "subs/uc", FP(0x16,0x101), BASE, ARG_FP }, 1120 { "muls/uc", FP(0x16,0x102), BASE, ARG_FP }, 1121 { "divs/uc", FP(0x16,0x103), BASE, ARG_FP }, 1122 { "addt/uc", FP(0x16,0x120), BASE, ARG_FP }, 1123 { "subt/uc", FP(0x16,0x121), BASE, ARG_FP }, 1124 { "mult/uc", FP(0x16,0x122), BASE, ARG_FP }, 1125 { "divt/uc", FP(0x16,0x123), BASE, ARG_FP }, 1126 { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 }, 1127 { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 }, 1128 { "adds/um", FP(0x16,0x140), BASE, ARG_FP }, 1129 { "subs/um", FP(0x16,0x141), BASE, ARG_FP }, 1130 { "muls/um", FP(0x16,0x142), BASE, ARG_FP }, 1131 { "divs/um", FP(0x16,0x143), BASE, ARG_FP }, 1132 { "addt/um", FP(0x16,0x160), BASE, ARG_FP }, 1133 { "subt/um", FP(0x16,0x161), BASE, ARG_FP }, 1134 { "mult/um", FP(0x16,0x162), BASE, ARG_FP }, 1135 { "divt/um", FP(0x16,0x163), BASE, ARG_FP }, 1136 { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 }, 1137 { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 }, 1138 { "adds/u", FP(0x16,0x180), BASE, ARG_FP }, 1139 { "subs/u", FP(0x16,0x181), BASE, ARG_FP }, 1140 { "muls/u", FP(0x16,0x182), BASE, ARG_FP }, 1141 { "divs/u", FP(0x16,0x183), BASE, ARG_FP }, 1142 { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP }, 1143 { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP }, 1144 { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP }, 1145 { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP }, 1146 { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 }, 1147 { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 }, 1148 { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP }, 1149 { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP }, 1150 { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP }, 1151 { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP }, 1152 { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP }, 1153 { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP }, 1154 { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP }, 1155 { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP }, 1156 { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 }, 1157 { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 }, 1158 { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 }, 1159 { "adds/suc", FP(0x16,0x500), BASE, ARG_FP }, 1160 { "subs/suc", FP(0x16,0x501), BASE, ARG_FP }, 1161 { "muls/suc", FP(0x16,0x502), BASE, ARG_FP }, 1162 { "divs/suc", FP(0x16,0x503), BASE, ARG_FP }, 1163 { "addt/suc", FP(0x16,0x520), BASE, ARG_FP }, 1164 { "subt/suc", FP(0x16,0x521), BASE, ARG_FP }, 1165 { "mult/suc", FP(0x16,0x522), BASE, ARG_FP }, 1166 { "divt/suc", FP(0x16,0x523), BASE, ARG_FP }, 1167 { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 }, 1168 { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 }, 1169 { "adds/sum", FP(0x16,0x540), BASE, ARG_FP }, 1170 { "subs/sum", FP(0x16,0x541), BASE, ARG_FP }, 1171 { "muls/sum", FP(0x16,0x542), BASE, ARG_FP }, 1172 { "divs/sum", FP(0x16,0x543), BASE, ARG_FP }, 1173 { "addt/sum", FP(0x16,0x560), BASE, ARG_FP }, 1174 { "subt/sum", FP(0x16,0x561), BASE, ARG_FP }, 1175 { "mult/sum", FP(0x16,0x562), BASE, ARG_FP }, 1176 { "divt/sum", FP(0x16,0x563), BASE, ARG_FP }, 1177 { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 }, 1178 { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 }, 1179 { "adds/su", FP(0x16,0x580), BASE, ARG_FP }, 1180 { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */ 1181 { "subs/su", FP(0x16,0x581), BASE, ARG_FP }, 1182 { "muls/su", FP(0x16,0x582), BASE, ARG_FP }, 1183 { "divs/su", FP(0x16,0x583), BASE, ARG_FP }, 1184 { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP }, 1185 { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */ 1186 { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP }, 1187 { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP }, 1188 { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP }, 1189 { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP }, 1190 { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP }, 1191 { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP }, 1192 { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP }, 1193 { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 }, 1194 { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 }, 1195 { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP }, 1196 { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP }, 1197 { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP }, 1198 { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP }, 1199 { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP }, 1200 { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP }, 1201 { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP }, 1202 { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP }, 1203 { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 }, 1204 { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 }, 1205 { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 }, 1206 { "adds/suic", FP(0x16,0x700), BASE, ARG_FP }, 1207 { "subs/suic", FP(0x16,0x701), BASE, ARG_FP }, 1208 { "muls/suic", FP(0x16,0x702), BASE, ARG_FP }, 1209 { "divs/suic", FP(0x16,0x703), BASE, ARG_FP }, 1210 { "addt/suic", FP(0x16,0x720), BASE, ARG_FP }, 1211 { "subt/suic", FP(0x16,0x721), BASE, ARG_FP }, 1212 { "mult/suic", FP(0x16,0x722), BASE, ARG_FP }, 1213 { "divt/suic", FP(0x16,0x723), BASE, ARG_FP }, 1214 { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 }, 1215 { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 }, 1216 { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 }, 1217 { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 }, 1218 { "adds/suim", FP(0x16,0x740), BASE, ARG_FP }, 1219 { "subs/suim", FP(0x16,0x741), BASE, ARG_FP }, 1220 { "muls/suim", FP(0x16,0x742), BASE, ARG_FP }, 1221 { "divs/suim", FP(0x16,0x743), BASE, ARG_FP }, 1222 { "addt/suim", FP(0x16,0x760), BASE, ARG_FP }, 1223 { "subt/suim", FP(0x16,0x761), BASE, ARG_FP }, 1224 { "mult/suim", FP(0x16,0x762), BASE, ARG_FP }, 1225 { "divt/suim", FP(0x16,0x763), BASE, ARG_FP }, 1226 { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 }, 1227 { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 }, 1228 { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 }, 1229 { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 }, 1230 { "adds/sui", FP(0x16,0x780), BASE, ARG_FP }, 1231 { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */ 1232 { "subs/sui", FP(0x16,0x781), BASE, ARG_FP }, 1233 { "muls/sui", FP(0x16,0x782), BASE, ARG_FP }, 1234 { "divs/sui", FP(0x16,0x783), BASE, ARG_FP }, 1235 { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP }, 1236 { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */ 1237 { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP }, 1238 { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP }, 1239 { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP }, 1240 { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 }, 1241 { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 }, 1242 { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 }, 1243 { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 }, 1244 { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP }, 1245 { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP }, 1246 { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP }, 1247 { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP }, 1248 { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP }, 1249 { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP }, 1250 { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP }, 1251 { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP }, 1252 { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 }, 1253 { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 }, 1254 { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 }, 1255 { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 }, 1256 1257 { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 }, 1258 { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */ 1259 { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */ 1260 { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */ 1261 { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */ 1262 { "cpys", FP(0x17,0x020), BASE, ARG_FP }, 1263 { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */ 1264 { "cpysn", FP(0x17,0x021), BASE, ARG_FP }, 1265 { "cpyse", FP(0x17,0x022), BASE, ARG_FP }, 1266 { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } }, 1267 { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } }, 1268 { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP }, 1269 { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP }, 1270 { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP }, 1271 { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP }, 1272 { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP }, 1273 { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP }, 1274 { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 }, 1275 { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 }, 1276 { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 }, 1277 1278 { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE }, 1279 { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */ 1280 { "excb", MFC(0x18,0x0400), BASE, ARG_NONE }, 1281 { "mb", MFC(0x18,0x4000), BASE, ARG_NONE }, 1282 { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, 1283 { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } }, 1284 { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } }, 1285 { "rpcc", MFC(0x18,0xC000), BASE, { RA } }, 1286 { "rc", MFC(0x18,0xE000), BASE, { RA } }, 1287 { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */ 1288 { "rs", MFC(0x18,0xF000), BASE, { RA } }, 1289 { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */ 1290 { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */ 1291 1292 { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 1293 { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 1294 { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } }, 1295 { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, 1296 { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, 1297 { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, 1298 { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, 1299 { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, 1300 { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, 1301 { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, 1302 { "pal19", PCD(0x19), BASE, ARG_PCD }, 1303 1304 { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */ 1305 BASE, { ZA, CPRB } }, 1306 { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } }, 1307 { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } }, 1308 { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */ 1309 0xFFFFFFFF, BASE, { 0 } }, 1310 { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } }, 1311 { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */ 1312 { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, 1313 1314 { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 1315 { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 1316 { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM }, 1317 { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 1318 { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 1319 { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM }, 1320 { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 1321 { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 1322 { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 1323 { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 1324 { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 1325 { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 1326 { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 1327 { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 1328 { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 1329 { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 1330 { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 1331 { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM }, 1332 { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 1333 { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 1334 { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 1335 { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 1336 { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 1337 { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 1338 { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 1339 { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 1340 { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 1341 { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 1342 { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 1343 { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 1344 { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 1345 { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 1346 { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 1347 { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 1348 { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 1349 { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 1350 { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 1351 { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 1352 { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM }, 1353 { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 1354 { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 1355 { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM }, 1356 { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM }, 1357 { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 1358 { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 1359 { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 1360 { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 1361 { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 1362 { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 1363 { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 1364 { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 1365 { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 1366 { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM }, 1367 { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 1368 { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 1369 { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 1370 { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 1371 { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 1372 { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 1373 { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 1374 { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 1375 { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 1376 { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 1377 { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 1378 { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 1379 { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM }, 1380 { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 1381 { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 1382 { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM }, 1383 { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 1384 { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 1385 { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 1386 { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 1387 { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 1388 { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 1389 { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 1390 { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 1391 { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 1392 { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 1393 { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 1394 { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM }, 1395 { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 1396 { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 1397 { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 1398 { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 1399 { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 1400 { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 1401 { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 1402 { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 1403 { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 1404 { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 1405 { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 1406 { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 1407 { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 1408 { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 1409 { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 1410 { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 1411 { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 1412 { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 1413 { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 1414 { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 1415 { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM }, 1416 { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 1417 { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 1418 { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM }, 1419 { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM }, 1420 { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 1421 { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 1422 { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 1423 { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 1424 { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 1425 { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 1426 { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 1427 { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 1428 { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 1429 { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM }, 1430 { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 1431 { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 1432 { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 1433 { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 1434 { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 1435 { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 1436 { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 1437 { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 1438 { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 1439 { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 1440 { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 1441 { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 1442 { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 1443 { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 1444 { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 1445 { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 1446 { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 1447 { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 1448 { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 1449 { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 1450 { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 1451 { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 1452 { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 1453 { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 1454 { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 1455 { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 1456 { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 1457 { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 1458 { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 1459 { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 1460 { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 1461 { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 1462 { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 1463 { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 1464 { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 1465 { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 1466 { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 1467 { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 1468 { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 1469 { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 1470 { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 1471 { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 1472 { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 1473 { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 1474 { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 1475 { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 1476 { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 1477 { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 1478 { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 1479 { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 1480 { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 1481 { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 1482 { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 1483 { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 1484 { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 1485 { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 1486 { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 1487 { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 1488 { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 1489 { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 1490 { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 1491 { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 1492 { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 1493 { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 1494 { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 1495 { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 1496 { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 1497 { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 1498 { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 1499 { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 1500 { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 1501 { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 1502 { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 1503 { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 1504 { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 1505 { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 1506 { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 1507 { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 1508 { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 1509 { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 1510 { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 1511 { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 1512 { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 1513 { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 1514 { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 1515 { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 1516 { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 1517 { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 1518 { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 1519 { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 1520 { "pal1b", PCD(0x1B), BASE, ARG_PCD }, 1521 1522 { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 }, 1523 { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 }, 1524 { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 }, 1525 { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR }, 1526 { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 }, 1527 { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 }, 1528 { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 }, 1529 { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 }, 1530 { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 }, 1531 { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 }, 1532 { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR }, 1533 { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL }, 1534 { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR }, 1535 { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL }, 1536 { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR }, 1537 { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL }, 1538 { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR }, 1539 { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL }, 1540 { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR }, 1541 { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL }, 1542 { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR }, 1543 { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL }, 1544 { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR }, 1545 { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL }, 1546 { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR }, 1547 { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL }, 1548 { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } }, 1549 { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } }, 1550 1551 { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 1552 { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 1553 { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } }, 1554 { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, 1555 { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, 1556 { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, 1557 { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, 1558 { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, 1559 { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, 1560 { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, 1561 { "pal1d", PCD(0x1D), BASE, ARG_PCD }, 1562 1563 { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE }, 1564 { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE }, 1565 { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } }, 1566 { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } }, 1567 { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } }, 1568 { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, 1569 { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */ 1570 { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } }, 1571 { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } }, 1572 { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } }, 1573 { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, 1574 { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */ 1575 { "pal1e", PCD(0x1E), BASE, ARG_PCD }, 1576 1577 { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 1578 { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 1579 { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */ 1580 { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 1581 { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 1582 { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM }, 1583 { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 1584 { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 1585 { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 1586 { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 1587 { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 1588 { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 1589 { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 1590 { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM }, 1591 { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 1592 { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 1593 { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 1594 { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 1595 { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 1596 { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 1597 { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 1598 { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 1599 { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 1600 { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 1601 { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 1602 { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 1603 { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 1604 { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 1605 { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 1606 { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 1607 { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM }, 1608 { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 1609 { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 1610 { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 1611 { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 1612 { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 1613 { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 1614 { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */ 1615 { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 1616 { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 1617 { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM }, 1618 { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 1619 { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 1620 { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 1621 { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 1622 { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 1623 { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 1624 { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 1625 { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM }, 1626 { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 1627 { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 1628 { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 1629 { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 1630 { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 1631 { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 1632 { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 1633 { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 1634 { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 1635 { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 1636 { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 1637 { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, 1638 { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 1639 { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 1640 { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 1641 { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 1642 { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 1643 { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 1644 { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM }, 1645 { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 1646 { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 1647 { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 1648 { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 1649 { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 1650 { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 1651 { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 1652 { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 1653 { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 1654 { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 1655 { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 1656 { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 1657 { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 1658 { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 1659 { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 1660 { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 1661 { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 1662 { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 1663 { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 1664 { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 1665 { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 1666 { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 1667 { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 1668 { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 1669 { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 1670 { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 1671 { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 1672 { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 1673 { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 1674 { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 1675 { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 1676 { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 1677 { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 1678 { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 1679 { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 1680 { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 1681 { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 1682 { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 1683 { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 1684 { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 1685 { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 1686 { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 1687 { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 1688 { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 1689 { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 1690 { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 1691 { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 1692 { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 1693 { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 1694 { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 1695 { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 1696 { "pal1f", PCD(0x1F), BASE, ARG_PCD }, 1697 1698 { "ldf", MEM(0x20), BASE, ARG_FMEM }, 1699 { "ldg", MEM(0x21), BASE, ARG_FMEM }, 1700 { "lds", MEM(0x22), BASE, ARG_FMEM }, 1701 { "ldt", MEM(0x23), BASE, ARG_FMEM }, 1702 { "stf", MEM(0x24), BASE, ARG_FMEM }, 1703 { "stg", MEM(0x25), BASE, ARG_FMEM }, 1704 { "sts", MEM(0x26), BASE, ARG_FMEM }, 1705 { "stt", MEM(0x27), BASE, ARG_FMEM }, 1706 1707 { "ldl", MEM(0x28), BASE, ARG_MEM }, 1708 { "ldq", MEM(0x29), BASE, ARG_MEM }, 1709 { "ldl_l", MEM(0x2A), BASE, ARG_MEM }, 1710 { "ldq_l", MEM(0x2B), BASE, ARG_MEM }, 1711 { "stl", MEM(0x2C), BASE, ARG_MEM }, 1712 { "stq", MEM(0x2D), BASE, ARG_MEM }, 1713 { "stl_c", MEM(0x2E), BASE, ARG_MEM }, 1714 { "stq_c", MEM(0x2F), BASE, ARG_MEM }, 1715 1716 { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */ 1717 { "br", BRA(0x30), BASE, ARG_BRA }, 1718 { "fbeq", BRA(0x31), BASE, ARG_FBRA }, 1719 { "fblt", BRA(0x32), BASE, ARG_FBRA }, 1720 { "fble", BRA(0x33), BASE, ARG_FBRA }, 1721 { "bsr", BRA(0x34), BASE, ARG_BRA }, 1722 { "fbne", BRA(0x35), BASE, ARG_FBRA }, 1723 { "fbge", BRA(0x36), BASE, ARG_FBRA }, 1724 { "fbgt", BRA(0x37), BASE, ARG_FBRA }, 1725 { "blbc", BRA(0x38), BASE, ARG_BRA }, 1726 { "beq", BRA(0x39), BASE, ARG_BRA }, 1727 { "blt", BRA(0x3A), BASE, ARG_BRA }, 1728 { "ble", BRA(0x3B), BASE, ARG_BRA }, 1729 { "blbs", BRA(0x3C), BASE, ARG_BRA }, 1730 { "bne", BRA(0x3D), BASE, ARG_BRA }, 1731 { "bge", BRA(0x3E), BASE, ARG_BRA }, 1732 { "bgt", BRA(0x3F), BASE, ARG_BRA }, 1733 }; 1734 1735 const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); 1736 1737 /* OSF register names. */ 1738 1739 static const char * const osf_regnames[64] = { 1740 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", 1741 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", 1742 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", 1743 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", 1744 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 1745 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 1746 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 1747 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 1748 }; 1749 1750 /* VMS register names. */ 1751 1752 static const char * const vms_regnames[64] = { 1753 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", 1754 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", 1755 "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", 1756 "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ", 1757 "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", 1758 "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", 1759 "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", 1760 "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ" 1761 }; 1762 1763 /* Disassemble Alpha instructions. */ 1764 1765 int 1766 print_insn_alpha (bfd_vma memaddr, struct disassemble_info *info) 1767 { 1768 static const struct alpha_opcode *opcode_index[AXP_NOPS+1]; 1769 const char * const * regnames; 1770 const struct alpha_opcode *opcode, *opcode_end; 1771 const unsigned char *opindex; 1772 unsigned insn, op, isa_mask; 1773 int need_comma; 1774 1775 /* Initialize the majorop table the first time through */ 1776 if (!opcode_index[0]) 1777 { 1778 opcode = alpha_opcodes; 1779 opcode_end = opcode + alpha_num_opcodes; 1780 1781 for (op = 0; op < AXP_NOPS; ++op) 1782 { 1783 opcode_index[op] = opcode; 1784 while (opcode < opcode_end && op == AXP_OP (opcode->opcode)) 1785 ++opcode; 1786 } 1787 opcode_index[op] = opcode; 1788 } 1789 1790 if (info->flavour == bfd_target_evax_flavour) 1791 regnames = vms_regnames; 1792 else 1793 regnames = osf_regnames; 1794 1795 isa_mask = AXP_OPCODE_NOPAL; 1796 switch (info->mach) 1797 { 1798 case bfd_mach_alpha_ev4: 1799 isa_mask |= AXP_OPCODE_EV4; 1800 break; 1801 case bfd_mach_alpha_ev5: 1802 isa_mask |= AXP_OPCODE_EV5; 1803 break; 1804 case bfd_mach_alpha_ev6: 1805 isa_mask |= AXP_OPCODE_EV6; 1806 break; 1807 } 1808 1809 /* Read the insn into a host word */ 1810 { 1811 bfd_byte buffer[4]; 1812 int status = (*info->read_memory_func) (memaddr, buffer, 4, info); 1813 if (status != 0) 1814 { 1815 (*info->memory_error_func) (status, memaddr, info); 1816 return -1; 1817 } 1818 insn = bfd_getl32 (buffer); 1819 } 1820 1821 /* Get the major opcode of the instruction. */ 1822 op = AXP_OP (insn); 1823 1824 /* Find the first match in the opcode table. */ 1825 opcode_end = opcode_index[op + 1]; 1826 for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode) 1827 { 1828 if ((insn ^ opcode->opcode) & opcode->mask) 1829 continue; 1830 1831 if (!(opcode->flags & isa_mask)) 1832 continue; 1833 1834 /* Make two passes over the operands. First see if any of them 1835 have extraction functions, and, if they do, make sure the 1836 instruction is valid. */ 1837 { 1838 int invalid = 0; 1839 for (opindex = opcode->operands; *opindex != 0; opindex++) 1840 { 1841 const struct alpha_operand *operand = alpha_operands + *opindex; 1842 if (operand->extract) 1843 (*operand->extract) (insn, &invalid); 1844 } 1845 if (invalid) 1846 continue; 1847 } 1848 1849 /* The instruction is valid. */ 1850 goto found; 1851 } 1852 1853 /* No instruction found */ 1854 (*info->fprintf_func) (info->stream, ".long %#08x", insn); 1855 1856 return 4; 1857 1858 found: 1859 (*info->fprintf_func) (info->stream, "%s", opcode->name); 1860 if (opcode->operands[0] != 0) 1861 (*info->fprintf_func) (info->stream, "\t"); 1862 1863 /* Now extract and print the operands. */ 1864 need_comma = 0; 1865 for (opindex = opcode->operands; *opindex != 0; opindex++) 1866 { 1867 const struct alpha_operand *operand = alpha_operands + *opindex; 1868 int value; 1869 1870 /* Operands that are marked FAKE are simply ignored. We 1871 already made sure that the extract function considered 1872 the instruction to be valid. */ 1873 if ((operand->flags & AXP_OPERAND_FAKE) != 0) 1874 continue; 1875 1876 /* Extract the value from the instruction. */ 1877 if (operand->extract) 1878 value = (*operand->extract) (insn, (int *) NULL); 1879 else 1880 { 1881 value = (insn >> operand->shift) & ((1 << operand->bits) - 1); 1882 if (operand->flags & AXP_OPERAND_SIGNED) 1883 { 1884 int signbit = 1 << (operand->bits - 1); 1885 value = (value ^ signbit) - signbit; 1886 } 1887 } 1888 1889 if (need_comma && 1890 ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA)) 1891 != AXP_OPERAND_PARENS)) 1892 { 1893 (*info->fprintf_func) (info->stream, ","); 1894 } 1895 if (operand->flags & AXP_OPERAND_PARENS) 1896 (*info->fprintf_func) (info->stream, "("); 1897 1898 /* Print the operand as directed by the flags. */ 1899 if (operand->flags & AXP_OPERAND_IR) 1900 (*info->fprintf_func) (info->stream, "%s", regnames[value]); 1901 else if (operand->flags & AXP_OPERAND_FPR) 1902 (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]); 1903 else if (operand->flags & AXP_OPERAND_RELATIVE) 1904 (*info->print_address_func) (memaddr + 4 + value, info); 1905 else if (operand->flags & AXP_OPERAND_SIGNED) 1906 (*info->fprintf_func) (info->stream, "%d", value); 1907 else 1908 (*info->fprintf_func) (info->stream, "%#x", value); 1909 1910 if (operand->flags & AXP_OPERAND_PARENS) 1911 (*info->fprintf_func) (info->stream, ")"); 1912 need_comma = 1; 1913 } 1914 1915 return 4; 1916 } 1917