1 /* 2 * Copyright (C) 2019, Alex Bennée <alex.bennee@linaro.org> 3 * 4 * How vectorised is this code? 5 * 6 * Attempt to measure the amount of vectorisation that has been done 7 * on some code by counting classes of instruction. 8 * 9 * License: GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 #include <inttypes.h> 13 #include <assert.h> 14 #include <stdlib.h> 15 #include <inttypes.h> 16 #include <string.h> 17 #include <unistd.h> 18 #include <stdio.h> 19 #include <glib.h> 20 21 #include <qemu-plugin.h> 22 23 QEMU_PLUGIN_EXPORT int qemu_plugin_version = QEMU_PLUGIN_VERSION; 24 25 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 26 27 typedef enum { 28 COUNT_CLASS, 29 COUNT_INDIVIDUAL, 30 COUNT_NONE 31 } CountType; 32 33 static int limit = 50; 34 static bool do_inline; 35 static bool verbose; 36 37 static GMutex lock; 38 static GHashTable *insns; 39 40 typedef struct { 41 const char *class; 42 const char *opt; 43 uint32_t mask; 44 uint32_t pattern; 45 CountType what; 46 uint64_t count; 47 } InsnClassExecCount; 48 49 typedef struct { 50 char *insn; 51 uint32_t opcode; 52 uint64_t count; 53 InsnClassExecCount *class; 54 } InsnExecCount; 55 56 /* 57 * Matchers for classes of instructions, order is important. 58 * 59 * Your most precise match must be before looser matches. If no match 60 * is found in the table we can create an individual entry. 61 * 62 * 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0 63 */ 64 static InsnClassExecCount aarch64_insn_classes[] = { 65 /* "Reserved"" */ 66 { " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE}, 67 { " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS}, 68 { "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS}, 69 /* Data Processing Immediate */ 70 { " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS}, 71 { " Add/Sub (imm,tags)", "asit", 0x1f800000, 0x11800000, COUNT_CLASS}, 72 { " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS}, 73 { " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS}, 74 { " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS}, 75 { " Bitfield", "bitf", 0x1f800000, 0x13000000, COUNT_CLASS}, 76 { " Extract", "extr", 0x1f800000, 0x13800000, COUNT_CLASS}, 77 { "Data Proc Imm", "dpri", 0x1c000000, 0x10000000, COUNT_CLASS}, 78 /* Branches */ 79 { " Cond Branch (imm)", "cndb", 0xfe000000, 0x54000000, COUNT_CLASS}, 80 { " Exception Gen", "excp", 0xff000000, 0xd4000000, COUNT_CLASS}, 81 { " NOP", "nop", 0xffffffff, 0xd503201f, COUNT_NONE}, 82 { " Hints", "hint", 0xfffff000, 0xd5032000, COUNT_CLASS}, 83 { " Barriers", "barr", 0xfffff000, 0xd5033000, COUNT_CLASS}, 84 { " PSTATE", "psta", 0xfff8f000, 0xd5004000, COUNT_CLASS}, 85 { " System Insn", "sins", 0xffd80000, 0xd5080000, COUNT_CLASS}, 86 { " System Reg", "sreg", 0xffd00000, 0xd5100000, COUNT_CLASS}, 87 { " Branch (reg)", "breg", 0xfe000000, 0xd6000000, COUNT_CLASS}, 88 { " Branch (imm)", "bimm", 0x7c000000, 0x14000000, COUNT_CLASS}, 89 { " Cmp & Branch", "cmpb", 0x7e000000, 0x34000000, COUNT_CLASS}, 90 { " Tst & Branch", "tstb", 0x7e000000, 0x36000000, COUNT_CLASS}, 91 { "Branches", "branch", 0x1c000000, 0x14000000, COUNT_CLASS}, 92 /* Loads and Stores */ 93 { " AdvSimd ldstmult", "advlsm", 0xbfbf0000, 0x0c000000, COUNT_CLASS}, 94 { " AdvSimd ldstmult++", "advlsmp", 0xbfb00000, 0x0c800000, COUNT_CLASS}, 95 { " AdvSimd ldst", "advlss", 0xbf9f0000, 0x0d000000, COUNT_CLASS}, 96 { " AdvSimd ldst++", "advlssp", 0xbf800000, 0x0d800000, COUNT_CLASS}, 97 { " ldst excl", "ldstx", 0x3f000000, 0x08000000, COUNT_CLASS}, 98 { " Prefetch", "prfm", 0xff000000, 0xd8000000, COUNT_CLASS}, 99 { " Load Reg (lit)", "ldlit", 0x1b000000, 0x18000000, COUNT_CLASS}, 100 { " ldst noalloc pair", "ldstnap", 0x3b800000, 0x28000000, COUNT_CLASS}, 101 { " ldst pair", "ldstp", 0x38000000, 0x28000000, COUNT_CLASS}, 102 { " ldst reg", "ldstr", 0x3b200000, 0x38000000, COUNT_CLASS}, 103 { " Atomic ldst", "atomic", 0x3b200c00, 0x38200000, COUNT_CLASS}, 104 { " ldst reg (reg off)", "ldstro", 0x3b200b00, 0x38200800, COUNT_CLASS}, 105 { " ldst reg (pac)", "ldstpa", 0x3b200200, 0x38200800, COUNT_CLASS}, 106 { " ldst reg (imm)", "ldsti", 0x3b000000, 0x39000000, COUNT_CLASS}, 107 { "Loads & Stores", "ldst", 0x0a000000, 0x08000000, COUNT_CLASS}, 108 /* Data Processing Register */ 109 { "Data Proc Reg", "dprr", 0x0e000000, 0x0a000000, COUNT_CLASS}, 110 /* Scalar FP */ 111 { "Scalar FP ", "fpsimd", 0x0e000000, 0x0e000000, COUNT_CLASS}, 112 /* Unclassified */ 113 { "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_CLASS}, 114 }; 115 116 static InsnClassExecCount sparc32_insn_classes[] = { 117 { "Call", "call", 0xc0000000, 0x40000000, COUNT_CLASS}, 118 { "Branch ICond", "bcc", 0xc1c00000, 0x00800000, COUNT_CLASS}, 119 { "Branch Fcond", "fbcc", 0xc1c00000, 0x01800000, COUNT_CLASS}, 120 { "SetHi", "sethi", 0xc1c00000, 0x01000000, COUNT_CLASS}, 121 { "FPU ALU", "fpu", 0xc1f00000, 0x81a00000, COUNT_CLASS}, 122 { "ALU", "alu", 0xc0000000, 0x80000000, COUNT_CLASS}, 123 { "Load/Store", "ldst", 0xc0000000, 0xc0000000, COUNT_CLASS}, 124 /* Unclassified */ 125 { "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_INDIVIDUAL}, 126 }; 127 128 static InsnClassExecCount sparc64_insn_classes[] = { 129 { "SetHi & Branches", "op0", 0xc0000000, 0x00000000, COUNT_CLASS}, 130 { "Call", "op1", 0xc0000000, 0x40000000, COUNT_CLASS}, 131 { "Arith/Logical/Move", "op2", 0xc0000000, 0x80000000, COUNT_CLASS}, 132 { "Arith/Logical/Move", "op3", 0xc0000000, 0xc0000000, COUNT_CLASS}, 133 /* Unclassified */ 134 { "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_INDIVIDUAL}, 135 }; 136 137 /* Default matcher for currently unclassified architectures */ 138 static InsnClassExecCount default_insn_classes[] = { 139 { "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_INDIVIDUAL}, 140 }; 141 142 typedef struct { 143 const char *qemu_target; 144 InsnClassExecCount *table; 145 int table_sz; 146 } ClassSelector; 147 148 static ClassSelector class_tables[] = { 149 { "aarch64", aarch64_insn_classes, ARRAY_SIZE(aarch64_insn_classes) }, 150 { "sparc", sparc32_insn_classes, ARRAY_SIZE(sparc32_insn_classes) }, 151 { "sparc64", sparc64_insn_classes, ARRAY_SIZE(sparc64_insn_classes) }, 152 { NULL, default_insn_classes, ARRAY_SIZE(default_insn_classes) }, 153 }; 154 155 static InsnClassExecCount *class_table; 156 static int class_table_sz; 157 158 static gint cmp_exec_count(gconstpointer a, gconstpointer b) 159 { 160 InsnExecCount *ea = (InsnExecCount *) a; 161 InsnExecCount *eb = (InsnExecCount *) b; 162 return ea->count > eb->count ? -1 : 1; 163 } 164 165 static void free_record(gpointer data) 166 { 167 InsnExecCount *rec = (InsnExecCount *) data; 168 g_free(rec->insn); 169 g_free(rec); 170 } 171 172 static void plugin_exit(qemu_plugin_id_t id, void *p) 173 { 174 g_autoptr(GString) report = g_string_new("Instruction Classes:\n"); 175 int i; 176 GList *counts; 177 InsnClassExecCount *class = NULL; 178 179 for (i = 0; i < class_table_sz; i++) { 180 class = &class_table[i]; 181 switch (class->what) { 182 case COUNT_CLASS: 183 if (class->count || verbose) { 184 g_string_append_printf(report, 185 "Class: %-24s\t(%" PRId64 " hits)\n", 186 class->class, 187 class->count); 188 } 189 break; 190 case COUNT_INDIVIDUAL: 191 g_string_append_printf(report, "Class: %-24s\tcounted individually\n", 192 class->class); 193 break; 194 case COUNT_NONE: 195 g_string_append_printf(report, "Class: %-24s\tnot counted\n", 196 class->class); 197 break; 198 default: 199 break; 200 } 201 } 202 203 counts = g_hash_table_get_values(insns); 204 if (counts && g_list_next(counts)) { 205 g_string_append_printf(report, "Individual Instructions:\n"); 206 counts = g_list_sort(counts, cmp_exec_count); 207 208 for (i = 0; i < limit && g_list_next(counts); 209 i++, counts = g_list_next(counts)) { 210 InsnExecCount *rec = (InsnExecCount *) counts->data; 211 g_string_append_printf(report, 212 "Instr: %-24s\t(%" PRId64 " hits)" 213 "\t(op=0x%08x/%s)\n", 214 rec->insn, 215 rec->count, 216 rec->opcode, 217 rec->class ? 218 rec->class->class : "un-categorised"); 219 } 220 g_list_free(counts); 221 } 222 223 g_hash_table_destroy(insns); 224 225 qemu_plugin_outs(report->str); 226 } 227 228 static void plugin_init(void) 229 { 230 insns = g_hash_table_new_full(NULL, g_direct_equal, NULL, &free_record); 231 } 232 233 static void vcpu_insn_exec_before(unsigned int cpu_index, void *udata) 234 { 235 uint64_t *count = (uint64_t *) udata; 236 (*count)++; 237 } 238 239 static uint64_t *find_counter(struct qemu_plugin_insn *insn) 240 { 241 int i; 242 uint64_t *cnt = NULL; 243 uint32_t opcode; 244 InsnClassExecCount *class = NULL; 245 246 /* 247 * We only match the first 32 bits of the instruction which is 248 * fine for most RISCs but a bit limiting for CISC architectures. 249 * They would probably benefit from a more tailored plugin. 250 * However we can fall back to individual instruction counting. 251 */ 252 opcode = *((uint32_t *)qemu_plugin_insn_data(insn)); 253 254 for (i = 0; !cnt && i < class_table_sz; i++) { 255 class = &class_table[i]; 256 uint32_t masked_bits = opcode & class->mask; 257 if (masked_bits == class->pattern) { 258 break; 259 } 260 } 261 262 g_assert(class); 263 264 switch (class->what) { 265 case COUNT_NONE: 266 return NULL; 267 case COUNT_CLASS: 268 return &class->count; 269 case COUNT_INDIVIDUAL: 270 { 271 InsnExecCount *icount; 272 273 g_mutex_lock(&lock); 274 icount = (InsnExecCount *) g_hash_table_lookup(insns, 275 GUINT_TO_POINTER(opcode)); 276 277 if (!icount) { 278 icount = g_new0(InsnExecCount, 1); 279 icount->opcode = opcode; 280 icount->insn = qemu_plugin_insn_disas(insn); 281 icount->class = class; 282 283 g_hash_table_insert(insns, GUINT_TO_POINTER(opcode), 284 (gpointer) icount); 285 } 286 g_mutex_unlock(&lock); 287 288 return &icount->count; 289 } 290 default: 291 g_assert_not_reached(); 292 } 293 294 return NULL; 295 } 296 297 static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) 298 { 299 size_t n = qemu_plugin_tb_n_insns(tb); 300 size_t i; 301 302 for (i = 0; i < n; i++) { 303 uint64_t *cnt; 304 struct qemu_plugin_insn *insn = qemu_plugin_tb_get_insn(tb, i); 305 cnt = find_counter(insn); 306 307 if (cnt) { 308 if (do_inline) { 309 qemu_plugin_register_vcpu_insn_exec_inline( 310 insn, QEMU_PLUGIN_INLINE_ADD_U64, cnt, 1); 311 } else { 312 qemu_plugin_register_vcpu_insn_exec_cb( 313 insn, vcpu_insn_exec_before, QEMU_PLUGIN_CB_NO_REGS, cnt); 314 } 315 } 316 } 317 } 318 319 QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id, 320 const qemu_info_t *info, 321 int argc, char **argv) 322 { 323 int i; 324 325 /* Select a class table appropriate to the guest architecture */ 326 for (i = 0; i < ARRAY_SIZE(class_tables); i++) { 327 ClassSelector *entry = &class_tables[i]; 328 if (!entry->qemu_target || 329 strcmp(entry->qemu_target, info->target_name) == 0) { 330 class_table = entry->table; 331 class_table_sz = entry->table_sz; 332 break; 333 } 334 } 335 336 for (i = 0; i < argc; i++) { 337 char *p = argv[i]; 338 g_auto(GStrv) tokens = g_strsplit(p, "=", -1); 339 if (g_strcmp0(tokens[0], "inline") == 0) { 340 if (!qemu_plugin_bool_parse(tokens[0], tokens[1], &do_inline)) { 341 fprintf(stderr, "boolean argument parsing failed: %s\n", p); 342 return -1; 343 } 344 } else if (g_strcmp0(tokens[0], "verbose") == 0) { 345 if (!qemu_plugin_bool_parse(tokens[0], tokens[1], &verbose)) { 346 fprintf(stderr, "boolean argument parsing failed: %s\n", p); 347 return -1; 348 } 349 } else if (g_strcmp0(tokens[0], "count") == 0) { 350 char *value = tokens[1]; 351 int j; 352 CountType type = COUNT_INDIVIDUAL; 353 if (*value == '!') { 354 type = COUNT_NONE; 355 value++; 356 } 357 for (j = 0; j < class_table_sz; j++) { 358 if (strcmp(value, class_table[j].opt) == 0) { 359 class_table[j].what = type; 360 break; 361 } 362 } 363 } else { 364 fprintf(stderr, "option parsing failed: %s\n", p); 365 return -1; 366 } 367 } 368 369 plugin_init(); 370 371 qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans); 372 qemu_plugin_register_atexit_cb(id, plugin_exit, NULL); 373 return 0; 374 } 375