xref: /openbmc/qemu/block/nvme.c (revision ae4c2099)
1 /*
2  * NVMe block driver based on vfio
3  *
4  * Copyright 2016 - 2018 Red Hat, Inc.
5  *
6  * Authors:
7  *   Fam Zheng <famz@redhat.com>
8  *   Paolo Bonzini <pbonzini@redhat.com>
9  *
10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
11  * See the COPYING file in the top-level directory.
12  */
13 
14 #include "qemu/osdep.h"
15 #include <linux/vfio.h>
16 #include "qapi/error.h"
17 #include "qapi/qmp/qdict.h"
18 #include "qapi/qmp/qstring.h"
19 #include "qemu/error-report.h"
20 #include "qemu/main-loop.h"
21 #include "qemu/module.h"
22 #include "qemu/cutils.h"
23 #include "qemu/option.h"
24 #include "qemu/vfio-helpers.h"
25 #include "block/block_int.h"
26 #include "sysemu/replay.h"
27 #include "trace.h"
28 
29 #include "block/nvme.h"
30 
31 #define NVME_SQ_ENTRY_BYTES 64
32 #define NVME_CQ_ENTRY_BYTES 16
33 #define NVME_QUEUE_SIZE 128
34 #define NVME_DOORBELL_SIZE 4096
35 
36 /*
37  * We have to leave one slot empty as that is the full queue case where
38  * head == tail + 1.
39  */
40 #define NVME_NUM_REQS (NVME_QUEUE_SIZE - 1)
41 
42 typedef struct BDRVNVMeState BDRVNVMeState;
43 
44 /* Same index is used for queues and IRQs */
45 #define INDEX_ADMIN     0
46 #define INDEX_IO(n)     (1 + n)
47 
48 /* This driver shares a single MSIX IRQ for the admin and I/O queues */
49 enum {
50     MSIX_SHARED_IRQ_IDX = 0,
51     MSIX_IRQ_COUNT = 1
52 };
53 
54 typedef struct {
55     int32_t  head, tail;
56     uint8_t  *queue;
57     uint64_t iova;
58     /* Hardware MMIO register */
59     volatile uint32_t *doorbell;
60 } NVMeQueue;
61 
62 typedef struct {
63     BlockCompletionFunc *cb;
64     void *opaque;
65     int cid;
66     void *prp_list_page;
67     uint64_t prp_list_iova;
68     int free_req_next; /* q->reqs[] index of next free req */
69 } NVMeRequest;
70 
71 typedef struct {
72     QemuMutex   lock;
73 
74     /* Read from I/O code path, initialized under BQL */
75     BDRVNVMeState   *s;
76     int             index;
77 
78     /* Fields protected by BQL */
79     uint8_t     *prp_list_pages;
80 
81     /* Fields protected by @lock */
82     CoQueue     free_req_queue;
83     NVMeQueue   sq, cq;
84     int         cq_phase;
85     int         free_req_head;
86     NVMeRequest reqs[NVME_NUM_REQS];
87     int         need_kick;
88     int         inflight;
89 
90     /* Thread-safe, no lock necessary */
91     QEMUBH      *completion_bh;
92 } NVMeQueuePair;
93 
94 struct BDRVNVMeState {
95     AioContext *aio_context;
96     QEMUVFIOState *vfio;
97     void *bar0_wo_map;
98     /* Memory mapped registers */
99     volatile struct {
100         uint32_t sq_tail;
101         uint32_t cq_head;
102     } *doorbells;
103     /* The submission/completion queue pairs.
104      * [0]: admin queue.
105      * [1..]: io queues.
106      */
107     NVMeQueuePair **queues;
108     unsigned queue_count;
109     size_t page_size;
110     /* How many uint32_t elements does each doorbell entry take. */
111     size_t doorbell_scale;
112     bool write_cache_supported;
113     EventNotifier irq_notifier[MSIX_IRQ_COUNT];
114 
115     uint64_t nsze; /* Namespace size reported by identify command */
116     int nsid;      /* The namespace id to read/write data. */
117     int blkshift;
118 
119     uint64_t max_transfer;
120     bool plugged;
121 
122     bool supports_write_zeroes;
123     bool supports_discard;
124 
125     CoMutex dma_map_lock;
126     CoQueue dma_flush_queue;
127 
128     /* Total size of mapped qiov, accessed under dma_map_lock */
129     int dma_map_count;
130 
131     /* PCI address (required for nvme_refresh_filename()) */
132     char *device;
133 
134     struct {
135         uint64_t completion_errors;
136         uint64_t aligned_accesses;
137         uint64_t unaligned_accesses;
138     } stats;
139 };
140 
141 #define NVME_BLOCK_OPT_DEVICE "device"
142 #define NVME_BLOCK_OPT_NAMESPACE "namespace"
143 
144 static void nvme_process_completion_bh(void *opaque);
145 
146 static QemuOptsList runtime_opts = {
147     .name = "nvme",
148     .head = QTAILQ_HEAD_INITIALIZER(runtime_opts.head),
149     .desc = {
150         {
151             .name = NVME_BLOCK_OPT_DEVICE,
152             .type = QEMU_OPT_STRING,
153             .help = "NVMe PCI device address",
154         },
155         {
156             .name = NVME_BLOCK_OPT_NAMESPACE,
157             .type = QEMU_OPT_NUMBER,
158             .help = "NVMe namespace",
159         },
160         { /* end of list */ }
161     },
162 };
163 
164 /* Returns true on success, false on failure. */
165 static bool nvme_init_queue(BDRVNVMeState *s, NVMeQueue *q,
166                             unsigned nentries, size_t entry_bytes, Error **errp)
167 {
168     size_t bytes;
169     int r;
170 
171     bytes = ROUND_UP(nentries * entry_bytes, qemu_real_host_page_size);
172     q->head = q->tail = 0;
173     q->queue = qemu_try_memalign(qemu_real_host_page_size, bytes);
174     if (!q->queue) {
175         error_setg(errp, "Cannot allocate queue");
176         return false;
177     }
178     memset(q->queue, 0, bytes);
179     r = qemu_vfio_dma_map(s->vfio, q->queue, bytes, false, &q->iova, errp);
180     if (r) {
181         error_prepend(errp, "Cannot map queue: ");
182     }
183     return r == 0;
184 }
185 
186 static void nvme_free_queue(NVMeQueue *q)
187 {
188     qemu_vfree(q->queue);
189 }
190 
191 static void nvme_free_queue_pair(NVMeQueuePair *q)
192 {
193     trace_nvme_free_queue_pair(q->index, q, &q->cq, &q->sq);
194     if (q->completion_bh) {
195         qemu_bh_delete(q->completion_bh);
196     }
197     nvme_free_queue(&q->sq);
198     nvme_free_queue(&q->cq);
199     qemu_vfree(q->prp_list_pages);
200     qemu_mutex_destroy(&q->lock);
201     g_free(q);
202 }
203 
204 static void nvme_free_req_queue_cb(void *opaque)
205 {
206     NVMeQueuePair *q = opaque;
207 
208     qemu_mutex_lock(&q->lock);
209     while (qemu_co_enter_next(&q->free_req_queue, &q->lock)) {
210         /* Retry all pending requests */
211     }
212     qemu_mutex_unlock(&q->lock);
213 }
214 
215 static NVMeQueuePair *nvme_create_queue_pair(BDRVNVMeState *s,
216                                              AioContext *aio_context,
217                                              unsigned idx, size_t size,
218                                              Error **errp)
219 {
220     int i, r;
221     NVMeQueuePair *q;
222     uint64_t prp_list_iova;
223     size_t bytes;
224 
225     q = g_try_new0(NVMeQueuePair, 1);
226     if (!q) {
227         error_setg(errp, "Cannot allocate queue pair");
228         return NULL;
229     }
230     trace_nvme_create_queue_pair(idx, q, size, aio_context,
231                                  event_notifier_get_fd(s->irq_notifier));
232     bytes = QEMU_ALIGN_UP(s->page_size * NVME_NUM_REQS,
233                           qemu_real_host_page_size);
234     q->prp_list_pages = qemu_try_memalign(qemu_real_host_page_size, bytes);
235     if (!q->prp_list_pages) {
236         error_setg(errp, "Cannot allocate PRP page list");
237         goto fail;
238     }
239     memset(q->prp_list_pages, 0, bytes);
240     qemu_mutex_init(&q->lock);
241     q->s = s;
242     q->index = idx;
243     qemu_co_queue_init(&q->free_req_queue);
244     q->completion_bh = aio_bh_new(aio_context, nvme_process_completion_bh, q);
245     r = qemu_vfio_dma_map(s->vfio, q->prp_list_pages, bytes,
246                           false, &prp_list_iova, errp);
247     if (r) {
248         error_prepend(errp, "Cannot map buffer for DMA: ");
249         goto fail;
250     }
251     q->free_req_head = -1;
252     for (i = 0; i < NVME_NUM_REQS; i++) {
253         NVMeRequest *req = &q->reqs[i];
254         req->cid = i + 1;
255         req->free_req_next = q->free_req_head;
256         q->free_req_head = i;
257         req->prp_list_page = q->prp_list_pages + i * s->page_size;
258         req->prp_list_iova = prp_list_iova + i * s->page_size;
259     }
260 
261     if (!nvme_init_queue(s, &q->sq, size, NVME_SQ_ENTRY_BYTES, errp)) {
262         goto fail;
263     }
264     q->sq.doorbell = &s->doorbells[idx * s->doorbell_scale].sq_tail;
265 
266     if (!nvme_init_queue(s, &q->cq, size, NVME_CQ_ENTRY_BYTES, errp)) {
267         goto fail;
268     }
269     q->cq.doorbell = &s->doorbells[idx * s->doorbell_scale].cq_head;
270 
271     return q;
272 fail:
273     nvme_free_queue_pair(q);
274     return NULL;
275 }
276 
277 /* With q->lock */
278 static void nvme_kick(NVMeQueuePair *q)
279 {
280     BDRVNVMeState *s = q->s;
281 
282     if (s->plugged || !q->need_kick) {
283         return;
284     }
285     trace_nvme_kick(s, q->index);
286     assert(!(q->sq.tail & 0xFF00));
287     /* Fence the write to submission queue entry before notifying the device. */
288     smp_wmb();
289     *q->sq.doorbell = cpu_to_le32(q->sq.tail);
290     q->inflight += q->need_kick;
291     q->need_kick = 0;
292 }
293 
294 /* Find a free request element if any, otherwise:
295  * a) if in coroutine context, try to wait for one to become available;
296  * b) if not in coroutine, return NULL;
297  */
298 static NVMeRequest *nvme_get_free_req(NVMeQueuePair *q)
299 {
300     NVMeRequest *req;
301 
302     qemu_mutex_lock(&q->lock);
303 
304     while (q->free_req_head == -1) {
305         if (qemu_in_coroutine()) {
306             trace_nvme_free_req_queue_wait(q->s, q->index);
307             qemu_co_queue_wait(&q->free_req_queue, &q->lock);
308         } else {
309             qemu_mutex_unlock(&q->lock);
310             return NULL;
311         }
312     }
313 
314     req = &q->reqs[q->free_req_head];
315     q->free_req_head = req->free_req_next;
316     req->free_req_next = -1;
317 
318     qemu_mutex_unlock(&q->lock);
319     return req;
320 }
321 
322 /* With q->lock */
323 static void nvme_put_free_req_locked(NVMeQueuePair *q, NVMeRequest *req)
324 {
325     req->free_req_next = q->free_req_head;
326     q->free_req_head = req - q->reqs;
327 }
328 
329 /* With q->lock */
330 static void nvme_wake_free_req_locked(NVMeQueuePair *q)
331 {
332     if (!qemu_co_queue_empty(&q->free_req_queue)) {
333         replay_bh_schedule_oneshot_event(q->s->aio_context,
334                 nvme_free_req_queue_cb, q);
335     }
336 }
337 
338 /* Insert a request in the freelist and wake waiters */
339 static void nvme_put_free_req_and_wake(NVMeQueuePair *q, NVMeRequest *req)
340 {
341     qemu_mutex_lock(&q->lock);
342     nvme_put_free_req_locked(q, req);
343     nvme_wake_free_req_locked(q);
344     qemu_mutex_unlock(&q->lock);
345 }
346 
347 static inline int nvme_translate_error(const NvmeCqe *c)
348 {
349     uint16_t status = (le16_to_cpu(c->status) >> 1) & 0xFF;
350     if (status) {
351         trace_nvme_error(le32_to_cpu(c->result),
352                          le16_to_cpu(c->sq_head),
353                          le16_to_cpu(c->sq_id),
354                          le16_to_cpu(c->cid),
355                          le16_to_cpu(status));
356     }
357     switch (status) {
358     case 0:
359         return 0;
360     case 1:
361         return -ENOSYS;
362     case 2:
363         return -EINVAL;
364     default:
365         return -EIO;
366     }
367 }
368 
369 /* With q->lock */
370 static bool nvme_process_completion(NVMeQueuePair *q)
371 {
372     BDRVNVMeState *s = q->s;
373     bool progress = false;
374     NVMeRequest *preq;
375     NVMeRequest req;
376     NvmeCqe *c;
377 
378     trace_nvme_process_completion(s, q->index, q->inflight);
379     if (s->plugged) {
380         trace_nvme_process_completion_queue_plugged(s, q->index);
381         return false;
382     }
383 
384     /*
385      * Support re-entrancy when a request cb() function invokes aio_poll().
386      * Pending completions must be visible to aio_poll() so that a cb()
387      * function can wait for the completion of another request.
388      *
389      * The aio_poll() loop will execute our BH and we'll resume completion
390      * processing there.
391      */
392     qemu_bh_schedule(q->completion_bh);
393 
394     assert(q->inflight >= 0);
395     while (q->inflight) {
396         int ret;
397         int16_t cid;
398 
399         c = (NvmeCqe *)&q->cq.queue[q->cq.head * NVME_CQ_ENTRY_BYTES];
400         if ((le16_to_cpu(c->status) & 0x1) == q->cq_phase) {
401             break;
402         }
403         ret = nvme_translate_error(c);
404         if (ret) {
405             s->stats.completion_errors++;
406         }
407         q->cq.head = (q->cq.head + 1) % NVME_QUEUE_SIZE;
408         if (!q->cq.head) {
409             q->cq_phase = !q->cq_phase;
410         }
411         cid = le16_to_cpu(c->cid);
412         if (cid == 0 || cid > NVME_QUEUE_SIZE) {
413             warn_report("NVMe: Unexpected CID in completion queue: %"PRIu32", "
414                         "queue size: %u", cid, NVME_QUEUE_SIZE);
415             continue;
416         }
417         trace_nvme_complete_command(s, q->index, cid);
418         preq = &q->reqs[cid - 1];
419         req = *preq;
420         assert(req.cid == cid);
421         assert(req.cb);
422         nvme_put_free_req_locked(q, preq);
423         preq->cb = preq->opaque = NULL;
424         q->inflight--;
425         qemu_mutex_unlock(&q->lock);
426         req.cb(req.opaque, ret);
427         qemu_mutex_lock(&q->lock);
428         progress = true;
429     }
430     if (progress) {
431         /* Notify the device so it can post more completions. */
432         smp_mb_release();
433         *q->cq.doorbell = cpu_to_le32(q->cq.head);
434         nvme_wake_free_req_locked(q);
435     }
436 
437     qemu_bh_cancel(q->completion_bh);
438 
439     return progress;
440 }
441 
442 static void nvme_process_completion_bh(void *opaque)
443 {
444     NVMeQueuePair *q = opaque;
445 
446     /*
447      * We're being invoked because a nvme_process_completion() cb() function
448      * called aio_poll(). The callback may be waiting for further completions
449      * so notify the device that it has space to fill in more completions now.
450      */
451     smp_mb_release();
452     *q->cq.doorbell = cpu_to_le32(q->cq.head);
453     nvme_wake_free_req_locked(q);
454 
455     nvme_process_completion(q);
456 }
457 
458 static void nvme_trace_command(const NvmeCmd *cmd)
459 {
460     int i;
461 
462     if (!trace_event_get_state_backends(TRACE_NVME_SUBMIT_COMMAND_RAW)) {
463         return;
464     }
465     for (i = 0; i < 8; ++i) {
466         uint8_t *cmdp = (uint8_t *)cmd + i * 8;
467         trace_nvme_submit_command_raw(cmdp[0], cmdp[1], cmdp[2], cmdp[3],
468                                       cmdp[4], cmdp[5], cmdp[6], cmdp[7]);
469     }
470 }
471 
472 static void nvme_submit_command(NVMeQueuePair *q, NVMeRequest *req,
473                                 NvmeCmd *cmd, BlockCompletionFunc cb,
474                                 void *opaque)
475 {
476     assert(!req->cb);
477     req->cb = cb;
478     req->opaque = opaque;
479     cmd->cid = cpu_to_le16(req->cid);
480 
481     trace_nvme_submit_command(q->s, q->index, req->cid);
482     nvme_trace_command(cmd);
483     qemu_mutex_lock(&q->lock);
484     memcpy((uint8_t *)q->sq.queue +
485            q->sq.tail * NVME_SQ_ENTRY_BYTES, cmd, sizeof(*cmd));
486     q->sq.tail = (q->sq.tail + 1) % NVME_QUEUE_SIZE;
487     q->need_kick++;
488     nvme_kick(q);
489     nvme_process_completion(q);
490     qemu_mutex_unlock(&q->lock);
491 }
492 
493 static void nvme_admin_cmd_sync_cb(void *opaque, int ret)
494 {
495     int *pret = opaque;
496     *pret = ret;
497     aio_wait_kick();
498 }
499 
500 static int nvme_admin_cmd_sync(BlockDriverState *bs, NvmeCmd *cmd)
501 {
502     BDRVNVMeState *s = bs->opaque;
503     NVMeQueuePair *q = s->queues[INDEX_ADMIN];
504     AioContext *aio_context = bdrv_get_aio_context(bs);
505     NVMeRequest *req;
506     int ret = -EINPROGRESS;
507     req = nvme_get_free_req(q);
508     if (!req) {
509         return -EBUSY;
510     }
511     nvme_submit_command(q, req, cmd, nvme_admin_cmd_sync_cb, &ret);
512 
513     AIO_WAIT_WHILE(aio_context, ret == -EINPROGRESS);
514     return ret;
515 }
516 
517 /* Returns true on success, false on failure. */
518 static bool nvme_identify(BlockDriverState *bs, int namespace, Error **errp)
519 {
520     BDRVNVMeState *s = bs->opaque;
521     bool ret = false;
522     QEMU_AUTO_VFREE union {
523         NvmeIdCtrl ctrl;
524         NvmeIdNs ns;
525     } *id = NULL;
526     NvmeLBAF *lbaf;
527     uint16_t oncs;
528     int r;
529     uint64_t iova;
530     NvmeCmd cmd = {
531         .opcode = NVME_ADM_CMD_IDENTIFY,
532         .cdw10 = cpu_to_le32(0x1),
533     };
534     size_t id_size = QEMU_ALIGN_UP(sizeof(*id), qemu_real_host_page_size);
535 
536     id = qemu_try_memalign(qemu_real_host_page_size, id_size);
537     if (!id) {
538         error_setg(errp, "Cannot allocate buffer for identify response");
539         goto out;
540     }
541     r = qemu_vfio_dma_map(s->vfio, id, id_size, true, &iova, errp);
542     if (r) {
543         error_prepend(errp, "Cannot map buffer for DMA: ");
544         goto out;
545     }
546 
547     memset(id, 0, id_size);
548     cmd.dptr.prp1 = cpu_to_le64(iova);
549     if (nvme_admin_cmd_sync(bs, &cmd)) {
550         error_setg(errp, "Failed to identify controller");
551         goto out;
552     }
553 
554     if (le32_to_cpu(id->ctrl.nn) < namespace) {
555         error_setg(errp, "Invalid namespace");
556         goto out;
557     }
558     s->write_cache_supported = le32_to_cpu(id->ctrl.vwc) & 0x1;
559     s->max_transfer = (id->ctrl.mdts ? 1 << id->ctrl.mdts : 0) * s->page_size;
560     /* For now the page list buffer per command is one page, to hold at most
561      * s->page_size / sizeof(uint64_t) entries. */
562     s->max_transfer = MIN_NON_ZERO(s->max_transfer,
563                           s->page_size / sizeof(uint64_t) * s->page_size);
564 
565     oncs = le16_to_cpu(id->ctrl.oncs);
566     s->supports_write_zeroes = !!(oncs & NVME_ONCS_WRITE_ZEROES);
567     s->supports_discard = !!(oncs & NVME_ONCS_DSM);
568 
569     memset(id, 0, id_size);
570     cmd.cdw10 = 0;
571     cmd.nsid = cpu_to_le32(namespace);
572     if (nvme_admin_cmd_sync(bs, &cmd)) {
573         error_setg(errp, "Failed to identify namespace");
574         goto out;
575     }
576 
577     s->nsze = le64_to_cpu(id->ns.nsze);
578     lbaf = &id->ns.lbaf[NVME_ID_NS_FLBAS_INDEX(id->ns.flbas)];
579 
580     if (NVME_ID_NS_DLFEAT_WRITE_ZEROES(id->ns.dlfeat) &&
581             NVME_ID_NS_DLFEAT_READ_BEHAVIOR(id->ns.dlfeat) ==
582                     NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES) {
583         bs->supported_write_flags |= BDRV_REQ_MAY_UNMAP;
584     }
585 
586     if (lbaf->ms) {
587         error_setg(errp, "Namespaces with metadata are not yet supported");
588         goto out;
589     }
590 
591     if (lbaf->ds < BDRV_SECTOR_BITS || lbaf->ds > 12 ||
592         (1 << lbaf->ds) > s->page_size)
593     {
594         error_setg(errp, "Namespace has unsupported block size (2^%d)",
595                    lbaf->ds);
596         goto out;
597     }
598 
599     ret = true;
600     s->blkshift = lbaf->ds;
601 out:
602     qemu_vfio_dma_unmap(s->vfio, id);
603 
604     return ret;
605 }
606 
607 static bool nvme_poll_queue(NVMeQueuePair *q)
608 {
609     bool progress = false;
610 
611     const size_t cqe_offset = q->cq.head * NVME_CQ_ENTRY_BYTES;
612     NvmeCqe *cqe = (NvmeCqe *)&q->cq.queue[cqe_offset];
613 
614     trace_nvme_poll_queue(q->s, q->index);
615     /*
616      * Do an early check for completions. q->lock isn't needed because
617      * nvme_process_completion() only runs in the event loop thread and
618      * cannot race with itself.
619      */
620     if ((le16_to_cpu(cqe->status) & 0x1) == q->cq_phase) {
621         return false;
622     }
623 
624     qemu_mutex_lock(&q->lock);
625     while (nvme_process_completion(q)) {
626         /* Keep polling */
627         progress = true;
628     }
629     qemu_mutex_unlock(&q->lock);
630 
631     return progress;
632 }
633 
634 static bool nvme_poll_queues(BDRVNVMeState *s)
635 {
636     bool progress = false;
637     int i;
638 
639     for (i = 0; i < s->queue_count; i++) {
640         if (nvme_poll_queue(s->queues[i])) {
641             progress = true;
642         }
643     }
644     return progress;
645 }
646 
647 static void nvme_handle_event(EventNotifier *n)
648 {
649     BDRVNVMeState *s = container_of(n, BDRVNVMeState,
650                                     irq_notifier[MSIX_SHARED_IRQ_IDX]);
651 
652     trace_nvme_handle_event(s);
653     event_notifier_test_and_clear(n);
654     nvme_poll_queues(s);
655 }
656 
657 static bool nvme_add_io_queue(BlockDriverState *bs, Error **errp)
658 {
659     BDRVNVMeState *s = bs->opaque;
660     unsigned n = s->queue_count;
661     NVMeQueuePair *q;
662     NvmeCmd cmd;
663     unsigned queue_size = NVME_QUEUE_SIZE;
664 
665     assert(n <= UINT16_MAX);
666     q = nvme_create_queue_pair(s, bdrv_get_aio_context(bs),
667                                n, queue_size, errp);
668     if (!q) {
669         return false;
670     }
671     cmd = (NvmeCmd) {
672         .opcode = NVME_ADM_CMD_CREATE_CQ,
673         .dptr.prp1 = cpu_to_le64(q->cq.iova),
674         .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n),
675         .cdw11 = cpu_to_le32(NVME_CQ_IEN | NVME_CQ_PC),
676     };
677     if (nvme_admin_cmd_sync(bs, &cmd)) {
678         error_setg(errp, "Failed to create CQ io queue [%u]", n);
679         goto out_error;
680     }
681     cmd = (NvmeCmd) {
682         .opcode = NVME_ADM_CMD_CREATE_SQ,
683         .dptr.prp1 = cpu_to_le64(q->sq.iova),
684         .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n),
685         .cdw11 = cpu_to_le32(NVME_SQ_PC | (n << 16)),
686     };
687     if (nvme_admin_cmd_sync(bs, &cmd)) {
688         error_setg(errp, "Failed to create SQ io queue [%u]", n);
689         goto out_error;
690     }
691     s->queues = g_renew(NVMeQueuePair *, s->queues, n + 1);
692     s->queues[n] = q;
693     s->queue_count++;
694     return true;
695 out_error:
696     nvme_free_queue_pair(q);
697     return false;
698 }
699 
700 static bool nvme_poll_cb(void *opaque)
701 {
702     EventNotifier *e = opaque;
703     BDRVNVMeState *s = container_of(e, BDRVNVMeState,
704                                     irq_notifier[MSIX_SHARED_IRQ_IDX]);
705 
706     return nvme_poll_queues(s);
707 }
708 
709 static int nvme_init(BlockDriverState *bs, const char *device, int namespace,
710                      Error **errp)
711 {
712     BDRVNVMeState *s = bs->opaque;
713     NVMeQueuePair *q;
714     AioContext *aio_context = bdrv_get_aio_context(bs);
715     int ret;
716     uint64_t cap;
717     uint32_t ver;
718     uint64_t timeout_ms;
719     uint64_t deadline, now;
720     volatile NvmeBar *regs = NULL;
721 
722     qemu_co_mutex_init(&s->dma_map_lock);
723     qemu_co_queue_init(&s->dma_flush_queue);
724     s->device = g_strdup(device);
725     s->nsid = namespace;
726     s->aio_context = bdrv_get_aio_context(bs);
727     ret = event_notifier_init(&s->irq_notifier[MSIX_SHARED_IRQ_IDX], 0);
728     if (ret) {
729         error_setg(errp, "Failed to init event notifier");
730         return ret;
731     }
732 
733     s->vfio = qemu_vfio_open_pci(device, errp);
734     if (!s->vfio) {
735         ret = -EINVAL;
736         goto out;
737     }
738 
739     regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, sizeof(NvmeBar),
740                                  PROT_READ | PROT_WRITE, errp);
741     if (!regs) {
742         ret = -EINVAL;
743         goto out;
744     }
745     /* Perform initialize sequence as described in NVMe spec "7.6.1
746      * Initialization". */
747 
748     cap = le64_to_cpu(regs->cap);
749     trace_nvme_controller_capability_raw(cap);
750     trace_nvme_controller_capability("Maximum Queue Entries Supported",
751                                      1 + NVME_CAP_MQES(cap));
752     trace_nvme_controller_capability("Contiguous Queues Required",
753                                      NVME_CAP_CQR(cap));
754     trace_nvme_controller_capability("Doorbell Stride",
755                                      1 << (2 + NVME_CAP_DSTRD(cap)));
756     trace_nvme_controller_capability("Subsystem Reset Supported",
757                                      NVME_CAP_NSSRS(cap));
758     trace_nvme_controller_capability("Memory Page Size Minimum",
759                                      1 << (12 + NVME_CAP_MPSMIN(cap)));
760     trace_nvme_controller_capability("Memory Page Size Maximum",
761                                      1 << (12 + NVME_CAP_MPSMAX(cap)));
762     if (!NVME_CAP_CSS(cap)) {
763         error_setg(errp, "Device doesn't support NVMe command set");
764         ret = -EINVAL;
765         goto out;
766     }
767 
768     s->page_size = 1u << (12 + NVME_CAP_MPSMIN(cap));
769     s->doorbell_scale = (4 << NVME_CAP_DSTRD(cap)) / sizeof(uint32_t);
770     bs->bl.opt_mem_alignment = s->page_size;
771     bs->bl.request_alignment = s->page_size;
772     timeout_ms = MIN(500 * NVME_CAP_TO(cap), 30000);
773 
774     ver = le32_to_cpu(regs->vs);
775     trace_nvme_controller_spec_version(extract32(ver, 16, 16),
776                                        extract32(ver, 8, 8),
777                                        extract32(ver, 0, 8));
778 
779     /* Reset device to get a clean state. */
780     regs->cc = cpu_to_le32(le32_to_cpu(regs->cc) & 0xFE);
781     /* Wait for CSTS.RDY = 0. */
782     deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCALE_MS;
783     while (NVME_CSTS_RDY(le32_to_cpu(regs->csts))) {
784         if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
785             error_setg(errp, "Timeout while waiting for device to reset (%"
786                              PRId64 " ms)",
787                        timeout_ms);
788             ret = -ETIMEDOUT;
789             goto out;
790         }
791     }
792 
793     s->bar0_wo_map = qemu_vfio_pci_map_bar(s->vfio, 0, 0,
794                                            sizeof(NvmeBar) + NVME_DOORBELL_SIZE,
795                                            PROT_WRITE, errp);
796     s->doorbells = (void *)((uintptr_t)s->bar0_wo_map + sizeof(NvmeBar));
797     if (!s->doorbells) {
798         ret = -EINVAL;
799         goto out;
800     }
801 
802     /* Set up admin queue. */
803     s->queues = g_new(NVMeQueuePair *, 1);
804     q = nvme_create_queue_pair(s, aio_context, 0, NVME_QUEUE_SIZE, errp);
805     if (!q) {
806         ret = -EINVAL;
807         goto out;
808     }
809     s->queues[INDEX_ADMIN] = q;
810     s->queue_count = 1;
811     QEMU_BUILD_BUG_ON((NVME_QUEUE_SIZE - 1) & 0xF000);
812     regs->aqa = cpu_to_le32(((NVME_QUEUE_SIZE - 1) << AQA_ACQS_SHIFT) |
813                             ((NVME_QUEUE_SIZE - 1) << AQA_ASQS_SHIFT));
814     regs->asq = cpu_to_le64(q->sq.iova);
815     regs->acq = cpu_to_le64(q->cq.iova);
816 
817     /* After setting up all control registers we can enable device now. */
818     regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << CC_IOCQES_SHIFT) |
819                            (ctz32(NVME_SQ_ENTRY_BYTES) << CC_IOSQES_SHIFT) |
820                            CC_EN_MASK);
821     /* Wait for CSTS.RDY = 1. */
822     now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
823     deadline = now + timeout_ms * SCALE_MS;
824     while (!NVME_CSTS_RDY(le32_to_cpu(regs->csts))) {
825         if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) {
826             error_setg(errp, "Timeout while waiting for device to start (%"
827                              PRId64 " ms)",
828                        timeout_ms);
829             ret = -ETIMEDOUT;
830             goto out;
831         }
832     }
833 
834     ret = qemu_vfio_pci_init_irq(s->vfio, s->irq_notifier,
835                                  VFIO_PCI_MSIX_IRQ_INDEX, errp);
836     if (ret) {
837         goto out;
838     }
839     aio_set_event_notifier(bdrv_get_aio_context(bs),
840                            &s->irq_notifier[MSIX_SHARED_IRQ_IDX],
841                            false, nvme_handle_event, nvme_poll_cb);
842 
843     if (!nvme_identify(bs, namespace, errp)) {
844         ret = -EIO;
845         goto out;
846     }
847 
848     /* Set up command queues. */
849     if (!nvme_add_io_queue(bs, errp)) {
850         ret = -EIO;
851     }
852 out:
853     if (regs) {
854         qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)regs, 0, sizeof(NvmeBar));
855     }
856 
857     /* Cleaning up is done in nvme_file_open() upon error. */
858     return ret;
859 }
860 
861 /* Parse a filename in the format of nvme://XXXX:XX:XX.X/X. Example:
862  *
863  *     nvme://0000:44:00.0/1
864  *
865  * where the "nvme://" is a fixed form of the protocol prefix, the middle part
866  * is the PCI address, and the last part is the namespace number starting from
867  * 1 according to the NVMe spec. */
868 static void nvme_parse_filename(const char *filename, QDict *options,
869                                 Error **errp)
870 {
871     int pref = strlen("nvme://");
872 
873     if (strlen(filename) > pref && !strncmp(filename, "nvme://", pref)) {
874         const char *tmp = filename + pref;
875         char *device;
876         const char *namespace;
877         unsigned long ns;
878         const char *slash = strchr(tmp, '/');
879         if (!slash) {
880             qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, tmp);
881             return;
882         }
883         device = g_strndup(tmp, slash - tmp);
884         qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, device);
885         g_free(device);
886         namespace = slash + 1;
887         if (*namespace && qemu_strtoul(namespace, NULL, 10, &ns)) {
888             error_setg(errp, "Invalid namespace '%s', positive number expected",
889                        namespace);
890             return;
891         }
892         qdict_put_str(options, NVME_BLOCK_OPT_NAMESPACE,
893                       *namespace ? namespace : "1");
894     }
895 }
896 
897 static int nvme_enable_disable_write_cache(BlockDriverState *bs, bool enable,
898                                            Error **errp)
899 {
900     int ret;
901     BDRVNVMeState *s = bs->opaque;
902     NvmeCmd cmd = {
903         .opcode = NVME_ADM_CMD_SET_FEATURES,
904         .nsid = cpu_to_le32(s->nsid),
905         .cdw10 = cpu_to_le32(0x06),
906         .cdw11 = cpu_to_le32(enable ? 0x01 : 0x00),
907     };
908 
909     ret = nvme_admin_cmd_sync(bs, &cmd);
910     if (ret) {
911         error_setg(errp, "Failed to configure NVMe write cache");
912     }
913     return ret;
914 }
915 
916 static void nvme_close(BlockDriverState *bs)
917 {
918     BDRVNVMeState *s = bs->opaque;
919 
920     for (unsigned i = 0; i < s->queue_count; ++i) {
921         nvme_free_queue_pair(s->queues[i]);
922     }
923     g_free(s->queues);
924     aio_set_event_notifier(bdrv_get_aio_context(bs),
925                            &s->irq_notifier[MSIX_SHARED_IRQ_IDX],
926                            false, NULL, NULL);
927     event_notifier_cleanup(&s->irq_notifier[MSIX_SHARED_IRQ_IDX]);
928     qemu_vfio_pci_unmap_bar(s->vfio, 0, s->bar0_wo_map,
929                             0, sizeof(NvmeBar) + NVME_DOORBELL_SIZE);
930     qemu_vfio_close(s->vfio);
931 
932     g_free(s->device);
933 }
934 
935 static int nvme_file_open(BlockDriverState *bs, QDict *options, int flags,
936                           Error **errp)
937 {
938     const char *device;
939     QemuOpts *opts;
940     int namespace;
941     int ret;
942     BDRVNVMeState *s = bs->opaque;
943 
944     bs->supported_write_flags = BDRV_REQ_FUA;
945 
946     opts = qemu_opts_create(&runtime_opts, NULL, 0, &error_abort);
947     qemu_opts_absorb_qdict(opts, options, &error_abort);
948     device = qemu_opt_get(opts, NVME_BLOCK_OPT_DEVICE);
949     if (!device) {
950         error_setg(errp, "'" NVME_BLOCK_OPT_DEVICE "' option is required");
951         qemu_opts_del(opts);
952         return -EINVAL;
953     }
954 
955     namespace = qemu_opt_get_number(opts, NVME_BLOCK_OPT_NAMESPACE, 1);
956     ret = nvme_init(bs, device, namespace, errp);
957     qemu_opts_del(opts);
958     if (ret) {
959         goto fail;
960     }
961     if (flags & BDRV_O_NOCACHE) {
962         if (!s->write_cache_supported) {
963             error_setg(errp,
964                        "NVMe controller doesn't support write cache configuration");
965             ret = -EINVAL;
966         } else {
967             ret = nvme_enable_disable_write_cache(bs, !(flags & BDRV_O_NOCACHE),
968                                                   errp);
969         }
970         if (ret) {
971             goto fail;
972         }
973     }
974     return 0;
975 fail:
976     nvme_close(bs);
977     return ret;
978 }
979 
980 static int64_t nvme_getlength(BlockDriverState *bs)
981 {
982     BDRVNVMeState *s = bs->opaque;
983     return s->nsze << s->blkshift;
984 }
985 
986 static uint32_t nvme_get_blocksize(BlockDriverState *bs)
987 {
988     BDRVNVMeState *s = bs->opaque;
989     assert(s->blkshift >= BDRV_SECTOR_BITS && s->blkshift <= 12);
990     return UINT32_C(1) << s->blkshift;
991 }
992 
993 static int nvme_probe_blocksizes(BlockDriverState *bs, BlockSizes *bsz)
994 {
995     uint32_t blocksize = nvme_get_blocksize(bs);
996     bsz->phys = blocksize;
997     bsz->log = blocksize;
998     return 0;
999 }
1000 
1001 /* Called with s->dma_map_lock */
1002 static coroutine_fn int nvme_cmd_unmap_qiov(BlockDriverState *bs,
1003                                             QEMUIOVector *qiov)
1004 {
1005     int r = 0;
1006     BDRVNVMeState *s = bs->opaque;
1007 
1008     s->dma_map_count -= qiov->size;
1009     if (!s->dma_map_count && !qemu_co_queue_empty(&s->dma_flush_queue)) {
1010         r = qemu_vfio_dma_reset_temporary(s->vfio);
1011         if (!r) {
1012             qemu_co_queue_restart_all(&s->dma_flush_queue);
1013         }
1014     }
1015     return r;
1016 }
1017 
1018 /* Called with s->dma_map_lock */
1019 static coroutine_fn int nvme_cmd_map_qiov(BlockDriverState *bs, NvmeCmd *cmd,
1020                                           NVMeRequest *req, QEMUIOVector *qiov)
1021 {
1022     BDRVNVMeState *s = bs->opaque;
1023     uint64_t *pagelist = req->prp_list_page;
1024     int i, j, r;
1025     int entries = 0;
1026     Error *local_err = NULL, **errp = NULL;
1027 
1028     assert(qiov->size);
1029     assert(QEMU_IS_ALIGNED(qiov->size, s->page_size));
1030     assert(qiov->size / s->page_size <= s->page_size / sizeof(uint64_t));
1031     for (i = 0; i < qiov->niov; ++i) {
1032         bool retry = true;
1033         uint64_t iova;
1034         size_t len = QEMU_ALIGN_UP(qiov->iov[i].iov_len,
1035                                    qemu_real_host_page_size);
1036 try_map:
1037         r = qemu_vfio_dma_map(s->vfio,
1038                               qiov->iov[i].iov_base,
1039                               len, true, &iova, errp);
1040         if (r == -ENOSPC) {
1041             /*
1042              * In addition to the -ENOMEM error, the VFIO_IOMMU_MAP_DMA
1043              * ioctl returns -ENOSPC to signal the user exhausted the DMA
1044              * mappings available for a container since Linux kernel commit
1045              * 492855939bdb ("vfio/type1: Limit DMA mappings per container",
1046              * April 2019, see CVE-2019-3882).
1047              *
1048              * This block driver already handles this error path by checking
1049              * for the -ENOMEM error, so we directly replace -ENOSPC by
1050              * -ENOMEM. Beside, -ENOSPC has a specific meaning for blockdev
1051              * coroutines: it triggers BLOCKDEV_ON_ERROR_ENOSPC and
1052              * BLOCK_ERROR_ACTION_STOP which stops the VM, asking the operator
1053              * to add more storage to the blockdev. Not something we can do
1054              * easily with an IOMMU :)
1055              */
1056             r = -ENOMEM;
1057         }
1058         if (r == -ENOMEM && retry) {
1059             /*
1060              * We exhausted the DMA mappings available for our container:
1061              * recycle the volatile IOVA mappings.
1062              */
1063             retry = false;
1064             trace_nvme_dma_flush_queue_wait(s);
1065             if (s->dma_map_count) {
1066                 trace_nvme_dma_map_flush(s);
1067                 qemu_co_queue_wait(&s->dma_flush_queue, &s->dma_map_lock);
1068             } else {
1069                 r = qemu_vfio_dma_reset_temporary(s->vfio);
1070                 if (r) {
1071                     goto fail;
1072                 }
1073             }
1074             errp = &local_err;
1075 
1076             goto try_map;
1077         }
1078         if (r) {
1079             goto fail;
1080         }
1081 
1082         for (j = 0; j < qiov->iov[i].iov_len / s->page_size; j++) {
1083             pagelist[entries++] = cpu_to_le64(iova + j * s->page_size);
1084         }
1085         trace_nvme_cmd_map_qiov_iov(s, i, qiov->iov[i].iov_base,
1086                                     qiov->iov[i].iov_len / s->page_size);
1087     }
1088 
1089     s->dma_map_count += qiov->size;
1090 
1091     assert(entries <= s->page_size / sizeof(uint64_t));
1092     switch (entries) {
1093     case 0:
1094         abort();
1095     case 1:
1096         cmd->dptr.prp1 = pagelist[0];
1097         cmd->dptr.prp2 = 0;
1098         break;
1099     case 2:
1100         cmd->dptr.prp1 = pagelist[0];
1101         cmd->dptr.prp2 = pagelist[1];
1102         break;
1103     default:
1104         cmd->dptr.prp1 = pagelist[0];
1105         cmd->dptr.prp2 = cpu_to_le64(req->prp_list_iova + sizeof(uint64_t));
1106         break;
1107     }
1108     trace_nvme_cmd_map_qiov(s, cmd, req, qiov, entries);
1109     for (i = 0; i < entries; ++i) {
1110         trace_nvme_cmd_map_qiov_pages(s, i, pagelist[i]);
1111     }
1112     return 0;
1113 fail:
1114     /* No need to unmap [0 - i) iovs even if we've failed, since we don't
1115      * increment s->dma_map_count. This is okay for fixed mapping memory areas
1116      * because they are already mapped before calling this function; for
1117      * temporary mappings, a later nvme_cmd_(un)map_qiov will reclaim by
1118      * calling qemu_vfio_dma_reset_temporary when necessary. */
1119     if (local_err) {
1120         error_reportf_err(local_err, "Cannot map buffer for DMA: ");
1121     }
1122     return r;
1123 }
1124 
1125 typedef struct {
1126     Coroutine *co;
1127     int ret;
1128     AioContext *ctx;
1129 } NVMeCoData;
1130 
1131 static void nvme_rw_cb_bh(void *opaque)
1132 {
1133     NVMeCoData *data = opaque;
1134     qemu_coroutine_enter(data->co);
1135 }
1136 
1137 static void nvme_rw_cb(void *opaque, int ret)
1138 {
1139     NVMeCoData *data = opaque;
1140     data->ret = ret;
1141     if (!data->co) {
1142         /* The rw coroutine hasn't yielded, don't try to enter. */
1143         return;
1144     }
1145     replay_bh_schedule_oneshot_event(data->ctx, nvme_rw_cb_bh, data);
1146 }
1147 
1148 static coroutine_fn int nvme_co_prw_aligned(BlockDriverState *bs,
1149                                             uint64_t offset, uint64_t bytes,
1150                                             QEMUIOVector *qiov,
1151                                             bool is_write,
1152                                             int flags)
1153 {
1154     int r;
1155     BDRVNVMeState *s = bs->opaque;
1156     NVMeQueuePair *ioq = s->queues[INDEX_IO(0)];
1157     NVMeRequest *req;
1158 
1159     uint32_t cdw12 = (((bytes >> s->blkshift) - 1) & 0xFFFF) |
1160                        (flags & BDRV_REQ_FUA ? 1 << 30 : 0);
1161     NvmeCmd cmd = {
1162         .opcode = is_write ? NVME_CMD_WRITE : NVME_CMD_READ,
1163         .nsid = cpu_to_le32(s->nsid),
1164         .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF),
1165         .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF),
1166         .cdw12 = cpu_to_le32(cdw12),
1167     };
1168     NVMeCoData data = {
1169         .ctx = bdrv_get_aio_context(bs),
1170         .ret = -EINPROGRESS,
1171     };
1172 
1173     trace_nvme_prw_aligned(s, is_write, offset, bytes, flags, qiov->niov);
1174     assert(s->queue_count > 1);
1175     req = nvme_get_free_req(ioq);
1176     assert(req);
1177 
1178     qemu_co_mutex_lock(&s->dma_map_lock);
1179     r = nvme_cmd_map_qiov(bs, &cmd, req, qiov);
1180     qemu_co_mutex_unlock(&s->dma_map_lock);
1181     if (r) {
1182         nvme_put_free_req_and_wake(ioq, req);
1183         return r;
1184     }
1185     nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data);
1186 
1187     data.co = qemu_coroutine_self();
1188     while (data.ret == -EINPROGRESS) {
1189         qemu_coroutine_yield();
1190     }
1191 
1192     qemu_co_mutex_lock(&s->dma_map_lock);
1193     r = nvme_cmd_unmap_qiov(bs, qiov);
1194     qemu_co_mutex_unlock(&s->dma_map_lock);
1195     if (r) {
1196         return r;
1197     }
1198 
1199     trace_nvme_rw_done(s, is_write, offset, bytes, data.ret);
1200     return data.ret;
1201 }
1202 
1203 static inline bool nvme_qiov_aligned(BlockDriverState *bs,
1204                                      const QEMUIOVector *qiov)
1205 {
1206     int i;
1207     BDRVNVMeState *s = bs->opaque;
1208 
1209     for (i = 0; i < qiov->niov; ++i) {
1210         if (!QEMU_PTR_IS_ALIGNED(qiov->iov[i].iov_base,
1211                                  qemu_real_host_page_size) ||
1212             !QEMU_IS_ALIGNED(qiov->iov[i].iov_len, qemu_real_host_page_size)) {
1213             trace_nvme_qiov_unaligned(qiov, i, qiov->iov[i].iov_base,
1214                                       qiov->iov[i].iov_len, s->page_size);
1215             return false;
1216         }
1217     }
1218     return true;
1219 }
1220 
1221 static int nvme_co_prw(BlockDriverState *bs, uint64_t offset, uint64_t bytes,
1222                        QEMUIOVector *qiov, bool is_write, int flags)
1223 {
1224     BDRVNVMeState *s = bs->opaque;
1225     int r;
1226     QEMU_AUTO_VFREE uint8_t *buf = NULL;
1227     QEMUIOVector local_qiov;
1228     size_t len = QEMU_ALIGN_UP(bytes, qemu_real_host_page_size);
1229     assert(QEMU_IS_ALIGNED(offset, s->page_size));
1230     assert(QEMU_IS_ALIGNED(bytes, s->page_size));
1231     assert(bytes <= s->max_transfer);
1232     if (nvme_qiov_aligned(bs, qiov)) {
1233         s->stats.aligned_accesses++;
1234         return nvme_co_prw_aligned(bs, offset, bytes, qiov, is_write, flags);
1235     }
1236     s->stats.unaligned_accesses++;
1237     trace_nvme_prw_buffered(s, offset, bytes, qiov->niov, is_write);
1238     buf = qemu_try_memalign(qemu_real_host_page_size, len);
1239 
1240     if (!buf) {
1241         return -ENOMEM;
1242     }
1243     qemu_iovec_init(&local_qiov, 1);
1244     if (is_write) {
1245         qemu_iovec_to_buf(qiov, 0, buf, bytes);
1246     }
1247     qemu_iovec_add(&local_qiov, buf, bytes);
1248     r = nvme_co_prw_aligned(bs, offset, bytes, &local_qiov, is_write, flags);
1249     qemu_iovec_destroy(&local_qiov);
1250     if (!r && !is_write) {
1251         qemu_iovec_from_buf(qiov, 0, buf, bytes);
1252     }
1253     return r;
1254 }
1255 
1256 static coroutine_fn int nvme_co_preadv(BlockDriverState *bs,
1257                                        int64_t offset, int64_t bytes,
1258                                        QEMUIOVector *qiov,
1259                                        BdrvRequestFlags flags)
1260 {
1261     return nvme_co_prw(bs, offset, bytes, qiov, false, flags);
1262 }
1263 
1264 static coroutine_fn int nvme_co_pwritev(BlockDriverState *bs,
1265                                         int64_t offset, int64_t bytes,
1266                                         QEMUIOVector *qiov,
1267                                         BdrvRequestFlags flags)
1268 {
1269     return nvme_co_prw(bs, offset, bytes, qiov, true, flags);
1270 }
1271 
1272 static coroutine_fn int nvme_co_flush(BlockDriverState *bs)
1273 {
1274     BDRVNVMeState *s = bs->opaque;
1275     NVMeQueuePair *ioq = s->queues[INDEX_IO(0)];
1276     NVMeRequest *req;
1277     NvmeCmd cmd = {
1278         .opcode = NVME_CMD_FLUSH,
1279         .nsid = cpu_to_le32(s->nsid),
1280     };
1281     NVMeCoData data = {
1282         .ctx = bdrv_get_aio_context(bs),
1283         .ret = -EINPROGRESS,
1284     };
1285 
1286     assert(s->queue_count > 1);
1287     req = nvme_get_free_req(ioq);
1288     assert(req);
1289     nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data);
1290 
1291     data.co = qemu_coroutine_self();
1292     if (data.ret == -EINPROGRESS) {
1293         qemu_coroutine_yield();
1294     }
1295 
1296     return data.ret;
1297 }
1298 
1299 
1300 static coroutine_fn int nvme_co_pwrite_zeroes(BlockDriverState *bs,
1301                                               int64_t offset,
1302                                               int64_t bytes,
1303                                               BdrvRequestFlags flags)
1304 {
1305     BDRVNVMeState *s = bs->opaque;
1306     NVMeQueuePair *ioq = s->queues[INDEX_IO(0)];
1307     NVMeRequest *req;
1308     uint32_t cdw12;
1309 
1310     if (!s->supports_write_zeroes) {
1311         return -ENOTSUP;
1312     }
1313 
1314     if (bytes == 0) {
1315         return 0;
1316     }
1317 
1318     cdw12 = ((bytes >> s->blkshift) - 1) & 0xFFFF;
1319     /*
1320      * We should not lose information. pwrite_zeroes_alignment and
1321      * max_pwrite_zeroes guarantees it.
1322      */
1323     assert(((cdw12 + 1) << s->blkshift) == bytes);
1324 
1325     NvmeCmd cmd = {
1326         .opcode = NVME_CMD_WRITE_ZEROES,
1327         .nsid = cpu_to_le32(s->nsid),
1328         .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF),
1329         .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF),
1330     };
1331 
1332     NVMeCoData data = {
1333         .ctx = bdrv_get_aio_context(bs),
1334         .ret = -EINPROGRESS,
1335     };
1336 
1337     if (flags & BDRV_REQ_MAY_UNMAP) {
1338         cdw12 |= (1 << 25);
1339     }
1340 
1341     if (flags & BDRV_REQ_FUA) {
1342         cdw12 |= (1 << 30);
1343     }
1344 
1345     cmd.cdw12 = cpu_to_le32(cdw12);
1346 
1347     trace_nvme_write_zeroes(s, offset, bytes, flags);
1348     assert(s->queue_count > 1);
1349     req = nvme_get_free_req(ioq);
1350     assert(req);
1351 
1352     nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data);
1353 
1354     data.co = qemu_coroutine_self();
1355     while (data.ret == -EINPROGRESS) {
1356         qemu_coroutine_yield();
1357     }
1358 
1359     trace_nvme_rw_done(s, true, offset, bytes, data.ret);
1360     return data.ret;
1361 }
1362 
1363 
1364 static int coroutine_fn nvme_co_pdiscard(BlockDriverState *bs,
1365                                          int64_t offset,
1366                                          int64_t bytes)
1367 {
1368     BDRVNVMeState *s = bs->opaque;
1369     NVMeQueuePair *ioq = s->queues[INDEX_IO(0)];
1370     NVMeRequest *req;
1371     QEMU_AUTO_VFREE NvmeDsmRange *buf = NULL;
1372     QEMUIOVector local_qiov;
1373     int ret;
1374 
1375     NvmeCmd cmd = {
1376         .opcode = NVME_CMD_DSM,
1377         .nsid = cpu_to_le32(s->nsid),
1378         .cdw10 = cpu_to_le32(0), /*number of ranges - 0 based*/
1379         .cdw11 = cpu_to_le32(1 << 2), /*deallocate bit*/
1380     };
1381 
1382     NVMeCoData data = {
1383         .ctx = bdrv_get_aio_context(bs),
1384         .ret = -EINPROGRESS,
1385     };
1386 
1387     if (!s->supports_discard) {
1388         return -ENOTSUP;
1389     }
1390 
1391     assert(s->queue_count > 1);
1392 
1393     /*
1394      * Filling the @buf requires @offset and @bytes to satisfy restrictions
1395      * defined in nvme_refresh_limits().
1396      */
1397     assert(QEMU_IS_ALIGNED(bytes, 1UL << s->blkshift));
1398     assert(QEMU_IS_ALIGNED(offset, 1UL << s->blkshift));
1399     assert((bytes >> s->blkshift) <= UINT32_MAX);
1400 
1401     buf = qemu_try_memalign(s->page_size, s->page_size);
1402     if (!buf) {
1403         return -ENOMEM;
1404     }
1405     memset(buf, 0, s->page_size);
1406     buf->nlb = cpu_to_le32(bytes >> s->blkshift);
1407     buf->slba = cpu_to_le64(offset >> s->blkshift);
1408     buf->cattr = 0;
1409 
1410     qemu_iovec_init(&local_qiov, 1);
1411     qemu_iovec_add(&local_qiov, buf, 4096);
1412 
1413     req = nvme_get_free_req(ioq);
1414     assert(req);
1415 
1416     qemu_co_mutex_lock(&s->dma_map_lock);
1417     ret = nvme_cmd_map_qiov(bs, &cmd, req, &local_qiov);
1418     qemu_co_mutex_unlock(&s->dma_map_lock);
1419 
1420     if (ret) {
1421         nvme_put_free_req_and_wake(ioq, req);
1422         goto out;
1423     }
1424 
1425     trace_nvme_dsm(s, offset, bytes);
1426 
1427     nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data);
1428 
1429     data.co = qemu_coroutine_self();
1430     while (data.ret == -EINPROGRESS) {
1431         qemu_coroutine_yield();
1432     }
1433 
1434     qemu_co_mutex_lock(&s->dma_map_lock);
1435     ret = nvme_cmd_unmap_qiov(bs, &local_qiov);
1436     qemu_co_mutex_unlock(&s->dma_map_lock);
1437 
1438     if (ret) {
1439         goto out;
1440     }
1441 
1442     ret = data.ret;
1443     trace_nvme_dsm_done(s, offset, bytes, ret);
1444 out:
1445     qemu_iovec_destroy(&local_qiov);
1446     return ret;
1447 
1448 }
1449 
1450 static int coroutine_fn nvme_co_truncate(BlockDriverState *bs, int64_t offset,
1451                                          bool exact, PreallocMode prealloc,
1452                                          BdrvRequestFlags flags, Error **errp)
1453 {
1454     int64_t cur_length;
1455 
1456     if (prealloc != PREALLOC_MODE_OFF) {
1457         error_setg(errp, "Unsupported preallocation mode '%s'",
1458                    PreallocMode_str(prealloc));
1459         return -ENOTSUP;
1460     }
1461 
1462     cur_length = nvme_getlength(bs);
1463     if (offset != cur_length && exact) {
1464         error_setg(errp, "Cannot resize NVMe devices");
1465         return -ENOTSUP;
1466     } else if (offset > cur_length) {
1467         error_setg(errp, "Cannot grow NVMe devices");
1468         return -EINVAL;
1469     }
1470 
1471     return 0;
1472 }
1473 
1474 static int nvme_reopen_prepare(BDRVReopenState *reopen_state,
1475                                BlockReopenQueue *queue, Error **errp)
1476 {
1477     return 0;
1478 }
1479 
1480 static void nvme_refresh_filename(BlockDriverState *bs)
1481 {
1482     BDRVNVMeState *s = bs->opaque;
1483 
1484     snprintf(bs->exact_filename, sizeof(bs->exact_filename), "nvme://%s/%i",
1485              s->device, s->nsid);
1486 }
1487 
1488 static void nvme_refresh_limits(BlockDriverState *bs, Error **errp)
1489 {
1490     BDRVNVMeState *s = bs->opaque;
1491 
1492     bs->bl.opt_mem_alignment = s->page_size;
1493     bs->bl.request_alignment = s->page_size;
1494     bs->bl.max_transfer = s->max_transfer;
1495 
1496     /*
1497      * Look at nvme_co_pwrite_zeroes: after shift and decrement we should get
1498      * at most 0xFFFF
1499      */
1500     bs->bl.max_pwrite_zeroes = 1ULL << (s->blkshift + 16);
1501     bs->bl.pwrite_zeroes_alignment = MAX(bs->bl.request_alignment,
1502                                          1UL << s->blkshift);
1503 
1504     bs->bl.max_pdiscard = (uint64_t)UINT32_MAX << s->blkshift;
1505     bs->bl.pdiscard_alignment = MAX(bs->bl.request_alignment,
1506                                     1UL << s->blkshift);
1507 }
1508 
1509 static void nvme_detach_aio_context(BlockDriverState *bs)
1510 {
1511     BDRVNVMeState *s = bs->opaque;
1512 
1513     for (unsigned i = 0; i < s->queue_count; i++) {
1514         NVMeQueuePair *q = s->queues[i];
1515 
1516         qemu_bh_delete(q->completion_bh);
1517         q->completion_bh = NULL;
1518     }
1519 
1520     aio_set_event_notifier(bdrv_get_aio_context(bs),
1521                            &s->irq_notifier[MSIX_SHARED_IRQ_IDX],
1522                            false, NULL, NULL);
1523 }
1524 
1525 static void nvme_attach_aio_context(BlockDriverState *bs,
1526                                     AioContext *new_context)
1527 {
1528     BDRVNVMeState *s = bs->opaque;
1529 
1530     s->aio_context = new_context;
1531     aio_set_event_notifier(new_context, &s->irq_notifier[MSIX_SHARED_IRQ_IDX],
1532                            false, nvme_handle_event, nvme_poll_cb);
1533 
1534     for (unsigned i = 0; i < s->queue_count; i++) {
1535         NVMeQueuePair *q = s->queues[i];
1536 
1537         q->completion_bh =
1538             aio_bh_new(new_context, nvme_process_completion_bh, q);
1539     }
1540 }
1541 
1542 static void nvme_aio_plug(BlockDriverState *bs)
1543 {
1544     BDRVNVMeState *s = bs->opaque;
1545     assert(!s->plugged);
1546     s->plugged = true;
1547 }
1548 
1549 static void nvme_aio_unplug(BlockDriverState *bs)
1550 {
1551     BDRVNVMeState *s = bs->opaque;
1552     assert(s->plugged);
1553     s->plugged = false;
1554     for (unsigned i = INDEX_IO(0); i < s->queue_count; i++) {
1555         NVMeQueuePair *q = s->queues[i];
1556         qemu_mutex_lock(&q->lock);
1557         nvme_kick(q);
1558         nvme_process_completion(q);
1559         qemu_mutex_unlock(&q->lock);
1560     }
1561 }
1562 
1563 static void nvme_register_buf(BlockDriverState *bs, void *host, size_t size)
1564 {
1565     int ret;
1566     Error *local_err = NULL;
1567     BDRVNVMeState *s = bs->opaque;
1568 
1569     ret = qemu_vfio_dma_map(s->vfio, host, size, false, NULL, &local_err);
1570     if (ret) {
1571         /* FIXME: we may run out of IOVA addresses after repeated
1572          * bdrv_register_buf/bdrv_unregister_buf, because nvme_vfio_dma_unmap
1573          * doesn't reclaim addresses for fixed mappings. */
1574         error_reportf_err(local_err, "nvme_register_buf failed: ");
1575     }
1576 }
1577 
1578 static void nvme_unregister_buf(BlockDriverState *bs, void *host)
1579 {
1580     BDRVNVMeState *s = bs->opaque;
1581 
1582     qemu_vfio_dma_unmap(s->vfio, host);
1583 }
1584 
1585 static BlockStatsSpecific *nvme_get_specific_stats(BlockDriverState *bs)
1586 {
1587     BlockStatsSpecific *stats = g_new(BlockStatsSpecific, 1);
1588     BDRVNVMeState *s = bs->opaque;
1589 
1590     stats->driver = BLOCKDEV_DRIVER_NVME;
1591     stats->u.nvme = (BlockStatsSpecificNvme) {
1592         .completion_errors = s->stats.completion_errors,
1593         .aligned_accesses = s->stats.aligned_accesses,
1594         .unaligned_accesses = s->stats.unaligned_accesses,
1595     };
1596 
1597     return stats;
1598 }
1599 
1600 static const char *const nvme_strong_runtime_opts[] = {
1601     NVME_BLOCK_OPT_DEVICE,
1602     NVME_BLOCK_OPT_NAMESPACE,
1603 
1604     NULL
1605 };
1606 
1607 static BlockDriver bdrv_nvme = {
1608     .format_name              = "nvme",
1609     .protocol_name            = "nvme",
1610     .instance_size            = sizeof(BDRVNVMeState),
1611 
1612     .bdrv_co_create_opts      = bdrv_co_create_opts_simple,
1613     .create_opts              = &bdrv_create_opts_simple,
1614 
1615     .bdrv_parse_filename      = nvme_parse_filename,
1616     .bdrv_file_open           = nvme_file_open,
1617     .bdrv_close               = nvme_close,
1618     .bdrv_getlength           = nvme_getlength,
1619     .bdrv_probe_blocksizes    = nvme_probe_blocksizes,
1620     .bdrv_co_truncate         = nvme_co_truncate,
1621 
1622     .bdrv_co_preadv           = nvme_co_preadv,
1623     .bdrv_co_pwritev          = nvme_co_pwritev,
1624 
1625     .bdrv_co_pwrite_zeroes    = nvme_co_pwrite_zeroes,
1626     .bdrv_co_pdiscard         = nvme_co_pdiscard,
1627 
1628     .bdrv_co_flush_to_disk    = nvme_co_flush,
1629     .bdrv_reopen_prepare      = nvme_reopen_prepare,
1630 
1631     .bdrv_refresh_filename    = nvme_refresh_filename,
1632     .bdrv_refresh_limits      = nvme_refresh_limits,
1633     .strong_runtime_opts      = nvme_strong_runtime_opts,
1634     .bdrv_get_specific_stats  = nvme_get_specific_stats,
1635 
1636     .bdrv_detach_aio_context  = nvme_detach_aio_context,
1637     .bdrv_attach_aio_context  = nvme_attach_aio_context,
1638 
1639     .bdrv_io_plug             = nvme_aio_plug,
1640     .bdrv_io_unplug           = nvme_aio_unplug,
1641 
1642     .bdrv_register_buf        = nvme_register_buf,
1643     .bdrv_unregister_buf      = nvme_unregister_buf,
1644 };
1645 
1646 static void bdrv_nvme_init(void)
1647 {
1648     bdrv_register(&bdrv_nvme);
1649 }
1650 
1651 block_init(bdrv_nvme_init);
1652