1 /* 2 * NVMe block driver based on vfio 3 * 4 * Copyright 2016 - 2018 Red Hat, Inc. 5 * 6 * Authors: 7 * Fam Zheng <famz@redhat.com> 8 * Paolo Bonzini <pbonzini@redhat.com> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2 or later. 11 * See the COPYING file in the top-level directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include <linux/vfio.h> 16 #include "qapi/error.h" 17 #include "qapi/qmp/qdict.h" 18 #include "qapi/qmp/qstring.h" 19 #include "qemu/error-report.h" 20 #include "qemu/main-loop.h" 21 #include "qemu/module.h" 22 #include "qemu/cutils.h" 23 #include "qemu/option.h" 24 #include "qemu/vfio-helpers.h" 25 #include "block/block_int.h" 26 #include "sysemu/replay.h" 27 #include "trace.h" 28 29 #include "block/nvme.h" 30 31 #define NVME_SQ_ENTRY_BYTES 64 32 #define NVME_CQ_ENTRY_BYTES 16 33 #define NVME_QUEUE_SIZE 128 34 #define NVME_DOORBELL_SIZE 4096 35 36 /* 37 * We have to leave one slot empty as that is the full queue case where 38 * head == tail + 1. 39 */ 40 #define NVME_NUM_REQS (NVME_QUEUE_SIZE - 1) 41 42 typedef struct BDRVNVMeState BDRVNVMeState; 43 44 /* Same index is used for queues and IRQs */ 45 #define INDEX_ADMIN 0 46 #define INDEX_IO(n) (1 + n) 47 48 /* This driver shares a single MSIX IRQ for the admin and I/O queues */ 49 enum { 50 MSIX_SHARED_IRQ_IDX = 0, 51 MSIX_IRQ_COUNT = 1 52 }; 53 54 typedef struct { 55 int32_t head, tail; 56 uint8_t *queue; 57 uint64_t iova; 58 /* Hardware MMIO register */ 59 volatile uint32_t *doorbell; 60 } NVMeQueue; 61 62 typedef struct { 63 BlockCompletionFunc *cb; 64 void *opaque; 65 int cid; 66 void *prp_list_page; 67 uint64_t prp_list_iova; 68 int free_req_next; /* q->reqs[] index of next free req */ 69 } NVMeRequest; 70 71 typedef struct { 72 QemuMutex lock; 73 74 /* Read from I/O code path, initialized under BQL */ 75 BDRVNVMeState *s; 76 int index; 77 78 /* Fields protected by BQL */ 79 uint8_t *prp_list_pages; 80 81 /* Fields protected by @lock */ 82 CoQueue free_req_queue; 83 NVMeQueue sq, cq; 84 int cq_phase; 85 int free_req_head; 86 NVMeRequest reqs[NVME_NUM_REQS]; 87 int need_kick; 88 int inflight; 89 90 /* Thread-safe, no lock necessary */ 91 QEMUBH *completion_bh; 92 } NVMeQueuePair; 93 94 struct BDRVNVMeState { 95 AioContext *aio_context; 96 QEMUVFIOState *vfio; 97 void *bar0_wo_map; 98 /* Memory mapped registers */ 99 volatile struct { 100 uint32_t sq_tail; 101 uint32_t cq_head; 102 } *doorbells; 103 /* The submission/completion queue pairs. 104 * [0]: admin queue. 105 * [1..]: io queues. 106 */ 107 NVMeQueuePair **queues; 108 unsigned queue_count; 109 size_t page_size; 110 /* How many uint32_t elements does each doorbell entry take. */ 111 size_t doorbell_scale; 112 bool write_cache_supported; 113 EventNotifier irq_notifier[MSIX_IRQ_COUNT]; 114 115 uint64_t nsze; /* Namespace size reported by identify command */ 116 int nsid; /* The namespace id to read/write data. */ 117 int blkshift; 118 119 uint64_t max_transfer; 120 bool plugged; 121 122 bool supports_write_zeroes; 123 bool supports_discard; 124 125 CoMutex dma_map_lock; 126 CoQueue dma_flush_queue; 127 128 /* Total size of mapped qiov, accessed under dma_map_lock */ 129 int dma_map_count; 130 131 /* PCI address (required for nvme_refresh_filename()) */ 132 char *device; 133 134 struct { 135 uint64_t completion_errors; 136 uint64_t aligned_accesses; 137 uint64_t unaligned_accesses; 138 } stats; 139 }; 140 141 #define NVME_BLOCK_OPT_DEVICE "device" 142 #define NVME_BLOCK_OPT_NAMESPACE "namespace" 143 144 static void nvme_process_completion_bh(void *opaque); 145 146 static QemuOptsList runtime_opts = { 147 .name = "nvme", 148 .head = QTAILQ_HEAD_INITIALIZER(runtime_opts.head), 149 .desc = { 150 { 151 .name = NVME_BLOCK_OPT_DEVICE, 152 .type = QEMU_OPT_STRING, 153 .help = "NVMe PCI device address", 154 }, 155 { 156 .name = NVME_BLOCK_OPT_NAMESPACE, 157 .type = QEMU_OPT_NUMBER, 158 .help = "NVMe namespace", 159 }, 160 { /* end of list */ } 161 }, 162 }; 163 164 /* Returns true on success, false on failure. */ 165 static bool nvme_init_queue(BDRVNVMeState *s, NVMeQueue *q, 166 unsigned nentries, size_t entry_bytes, Error **errp) 167 { 168 size_t bytes; 169 int r; 170 171 bytes = ROUND_UP(nentries * entry_bytes, qemu_real_host_page_size); 172 q->head = q->tail = 0; 173 q->queue = qemu_try_memalign(qemu_real_host_page_size, bytes); 174 if (!q->queue) { 175 error_setg(errp, "Cannot allocate queue"); 176 return false; 177 } 178 memset(q->queue, 0, bytes); 179 r = qemu_vfio_dma_map(s->vfio, q->queue, bytes, false, &q->iova, errp); 180 if (r) { 181 error_prepend(errp, "Cannot map queue: "); 182 } 183 return r == 0; 184 } 185 186 static void nvme_free_queue_pair(NVMeQueuePair *q) 187 { 188 trace_nvme_free_queue_pair(q->index, q); 189 if (q->completion_bh) { 190 qemu_bh_delete(q->completion_bh); 191 } 192 qemu_vfree(q->prp_list_pages); 193 qemu_vfree(q->sq.queue); 194 qemu_vfree(q->cq.queue); 195 qemu_mutex_destroy(&q->lock); 196 g_free(q); 197 } 198 199 static void nvme_free_req_queue_cb(void *opaque) 200 { 201 NVMeQueuePair *q = opaque; 202 203 qemu_mutex_lock(&q->lock); 204 while (qemu_co_enter_next(&q->free_req_queue, &q->lock)) { 205 /* Retry all pending requests */ 206 } 207 qemu_mutex_unlock(&q->lock); 208 } 209 210 static NVMeQueuePair *nvme_create_queue_pair(BDRVNVMeState *s, 211 AioContext *aio_context, 212 unsigned idx, size_t size, 213 Error **errp) 214 { 215 int i, r; 216 NVMeQueuePair *q; 217 uint64_t prp_list_iova; 218 size_t bytes; 219 220 q = g_try_new0(NVMeQueuePair, 1); 221 if (!q) { 222 error_setg(errp, "Cannot allocate queue pair"); 223 return NULL; 224 } 225 trace_nvme_create_queue_pair(idx, q, size, aio_context, 226 event_notifier_get_fd(s->irq_notifier)); 227 bytes = QEMU_ALIGN_UP(s->page_size * NVME_NUM_REQS, 228 qemu_real_host_page_size); 229 q->prp_list_pages = qemu_try_memalign(qemu_real_host_page_size, bytes); 230 if (!q->prp_list_pages) { 231 error_setg(errp, "Cannot allocate PRP page list"); 232 goto fail; 233 } 234 memset(q->prp_list_pages, 0, bytes); 235 qemu_mutex_init(&q->lock); 236 q->s = s; 237 q->index = idx; 238 qemu_co_queue_init(&q->free_req_queue); 239 q->completion_bh = aio_bh_new(aio_context, nvme_process_completion_bh, q); 240 r = qemu_vfio_dma_map(s->vfio, q->prp_list_pages, bytes, 241 false, &prp_list_iova, errp); 242 if (r) { 243 error_prepend(errp, "Cannot map buffer for DMA: "); 244 goto fail; 245 } 246 q->free_req_head = -1; 247 for (i = 0; i < NVME_NUM_REQS; i++) { 248 NVMeRequest *req = &q->reqs[i]; 249 req->cid = i + 1; 250 req->free_req_next = q->free_req_head; 251 q->free_req_head = i; 252 req->prp_list_page = q->prp_list_pages + i * s->page_size; 253 req->prp_list_iova = prp_list_iova + i * s->page_size; 254 } 255 256 if (!nvme_init_queue(s, &q->sq, size, NVME_SQ_ENTRY_BYTES, errp)) { 257 goto fail; 258 } 259 q->sq.doorbell = &s->doorbells[idx * s->doorbell_scale].sq_tail; 260 261 if (!nvme_init_queue(s, &q->cq, size, NVME_CQ_ENTRY_BYTES, errp)) { 262 goto fail; 263 } 264 q->cq.doorbell = &s->doorbells[idx * s->doorbell_scale].cq_head; 265 266 return q; 267 fail: 268 nvme_free_queue_pair(q); 269 return NULL; 270 } 271 272 /* With q->lock */ 273 static void nvme_kick(NVMeQueuePair *q) 274 { 275 BDRVNVMeState *s = q->s; 276 277 if (s->plugged || !q->need_kick) { 278 return; 279 } 280 trace_nvme_kick(s, q->index); 281 assert(!(q->sq.tail & 0xFF00)); 282 /* Fence the write to submission queue entry before notifying the device. */ 283 smp_wmb(); 284 *q->sq.doorbell = cpu_to_le32(q->sq.tail); 285 q->inflight += q->need_kick; 286 q->need_kick = 0; 287 } 288 289 /* Find a free request element if any, otherwise: 290 * a) if in coroutine context, try to wait for one to become available; 291 * b) if not in coroutine, return NULL; 292 */ 293 static NVMeRequest *nvme_get_free_req(NVMeQueuePair *q) 294 { 295 NVMeRequest *req; 296 297 qemu_mutex_lock(&q->lock); 298 299 while (q->free_req_head == -1) { 300 if (qemu_in_coroutine()) { 301 trace_nvme_free_req_queue_wait(q->s, q->index); 302 qemu_co_queue_wait(&q->free_req_queue, &q->lock); 303 } else { 304 qemu_mutex_unlock(&q->lock); 305 return NULL; 306 } 307 } 308 309 req = &q->reqs[q->free_req_head]; 310 q->free_req_head = req->free_req_next; 311 req->free_req_next = -1; 312 313 qemu_mutex_unlock(&q->lock); 314 return req; 315 } 316 317 /* With q->lock */ 318 static void nvme_put_free_req_locked(NVMeQueuePair *q, NVMeRequest *req) 319 { 320 req->free_req_next = q->free_req_head; 321 q->free_req_head = req - q->reqs; 322 } 323 324 /* With q->lock */ 325 static void nvme_wake_free_req_locked(NVMeQueuePair *q) 326 { 327 if (!qemu_co_queue_empty(&q->free_req_queue)) { 328 replay_bh_schedule_oneshot_event(q->s->aio_context, 329 nvme_free_req_queue_cb, q); 330 } 331 } 332 333 /* Insert a request in the freelist and wake waiters */ 334 static void nvme_put_free_req_and_wake(NVMeQueuePair *q, NVMeRequest *req) 335 { 336 qemu_mutex_lock(&q->lock); 337 nvme_put_free_req_locked(q, req); 338 nvme_wake_free_req_locked(q); 339 qemu_mutex_unlock(&q->lock); 340 } 341 342 static inline int nvme_translate_error(const NvmeCqe *c) 343 { 344 uint16_t status = (le16_to_cpu(c->status) >> 1) & 0xFF; 345 if (status) { 346 trace_nvme_error(le32_to_cpu(c->result), 347 le16_to_cpu(c->sq_head), 348 le16_to_cpu(c->sq_id), 349 le16_to_cpu(c->cid), 350 le16_to_cpu(status)); 351 } 352 switch (status) { 353 case 0: 354 return 0; 355 case 1: 356 return -ENOSYS; 357 case 2: 358 return -EINVAL; 359 default: 360 return -EIO; 361 } 362 } 363 364 /* With q->lock */ 365 static bool nvme_process_completion(NVMeQueuePair *q) 366 { 367 BDRVNVMeState *s = q->s; 368 bool progress = false; 369 NVMeRequest *preq; 370 NVMeRequest req; 371 NvmeCqe *c; 372 373 trace_nvme_process_completion(s, q->index, q->inflight); 374 if (s->plugged) { 375 trace_nvme_process_completion_queue_plugged(s, q->index); 376 return false; 377 } 378 379 /* 380 * Support re-entrancy when a request cb() function invokes aio_poll(). 381 * Pending completions must be visible to aio_poll() so that a cb() 382 * function can wait for the completion of another request. 383 * 384 * The aio_poll() loop will execute our BH and we'll resume completion 385 * processing there. 386 */ 387 qemu_bh_schedule(q->completion_bh); 388 389 assert(q->inflight >= 0); 390 while (q->inflight) { 391 int ret; 392 int16_t cid; 393 394 c = (NvmeCqe *)&q->cq.queue[q->cq.head * NVME_CQ_ENTRY_BYTES]; 395 if ((le16_to_cpu(c->status) & 0x1) == q->cq_phase) { 396 break; 397 } 398 ret = nvme_translate_error(c); 399 if (ret) { 400 s->stats.completion_errors++; 401 } 402 q->cq.head = (q->cq.head + 1) % NVME_QUEUE_SIZE; 403 if (!q->cq.head) { 404 q->cq_phase = !q->cq_phase; 405 } 406 cid = le16_to_cpu(c->cid); 407 if (cid == 0 || cid > NVME_QUEUE_SIZE) { 408 warn_report("NVMe: Unexpected CID in completion queue: %"PRIu32", " 409 "queue size: %u", cid, NVME_QUEUE_SIZE); 410 continue; 411 } 412 trace_nvme_complete_command(s, q->index, cid); 413 preq = &q->reqs[cid - 1]; 414 req = *preq; 415 assert(req.cid == cid); 416 assert(req.cb); 417 nvme_put_free_req_locked(q, preq); 418 preq->cb = preq->opaque = NULL; 419 q->inflight--; 420 qemu_mutex_unlock(&q->lock); 421 req.cb(req.opaque, ret); 422 qemu_mutex_lock(&q->lock); 423 progress = true; 424 } 425 if (progress) { 426 /* Notify the device so it can post more completions. */ 427 smp_mb_release(); 428 *q->cq.doorbell = cpu_to_le32(q->cq.head); 429 nvme_wake_free_req_locked(q); 430 } 431 432 qemu_bh_cancel(q->completion_bh); 433 434 return progress; 435 } 436 437 static void nvme_process_completion_bh(void *opaque) 438 { 439 NVMeQueuePair *q = opaque; 440 441 /* 442 * We're being invoked because a nvme_process_completion() cb() function 443 * called aio_poll(). The callback may be waiting for further completions 444 * so notify the device that it has space to fill in more completions now. 445 */ 446 smp_mb_release(); 447 *q->cq.doorbell = cpu_to_le32(q->cq.head); 448 nvme_wake_free_req_locked(q); 449 450 nvme_process_completion(q); 451 } 452 453 static void nvme_trace_command(const NvmeCmd *cmd) 454 { 455 int i; 456 457 if (!trace_event_get_state_backends(TRACE_NVME_SUBMIT_COMMAND_RAW)) { 458 return; 459 } 460 for (i = 0; i < 8; ++i) { 461 uint8_t *cmdp = (uint8_t *)cmd + i * 8; 462 trace_nvme_submit_command_raw(cmdp[0], cmdp[1], cmdp[2], cmdp[3], 463 cmdp[4], cmdp[5], cmdp[6], cmdp[7]); 464 } 465 } 466 467 static void nvme_submit_command(NVMeQueuePair *q, NVMeRequest *req, 468 NvmeCmd *cmd, BlockCompletionFunc cb, 469 void *opaque) 470 { 471 assert(!req->cb); 472 req->cb = cb; 473 req->opaque = opaque; 474 cmd->cid = cpu_to_le16(req->cid); 475 476 trace_nvme_submit_command(q->s, q->index, req->cid); 477 nvme_trace_command(cmd); 478 qemu_mutex_lock(&q->lock); 479 memcpy((uint8_t *)q->sq.queue + 480 q->sq.tail * NVME_SQ_ENTRY_BYTES, cmd, sizeof(*cmd)); 481 q->sq.tail = (q->sq.tail + 1) % NVME_QUEUE_SIZE; 482 q->need_kick++; 483 nvme_kick(q); 484 nvme_process_completion(q); 485 qemu_mutex_unlock(&q->lock); 486 } 487 488 static void nvme_admin_cmd_sync_cb(void *opaque, int ret) 489 { 490 int *pret = opaque; 491 *pret = ret; 492 aio_wait_kick(); 493 } 494 495 static int nvme_admin_cmd_sync(BlockDriverState *bs, NvmeCmd *cmd) 496 { 497 BDRVNVMeState *s = bs->opaque; 498 NVMeQueuePair *q = s->queues[INDEX_ADMIN]; 499 AioContext *aio_context = bdrv_get_aio_context(bs); 500 NVMeRequest *req; 501 int ret = -EINPROGRESS; 502 req = nvme_get_free_req(q); 503 if (!req) { 504 return -EBUSY; 505 } 506 nvme_submit_command(q, req, cmd, nvme_admin_cmd_sync_cb, &ret); 507 508 AIO_WAIT_WHILE(aio_context, ret == -EINPROGRESS); 509 return ret; 510 } 511 512 /* Returns true on success, false on failure. */ 513 static bool nvme_identify(BlockDriverState *bs, int namespace, Error **errp) 514 { 515 BDRVNVMeState *s = bs->opaque; 516 bool ret = false; 517 union { 518 NvmeIdCtrl ctrl; 519 NvmeIdNs ns; 520 } *id; 521 NvmeLBAF *lbaf; 522 uint16_t oncs; 523 int r; 524 uint64_t iova; 525 NvmeCmd cmd = { 526 .opcode = NVME_ADM_CMD_IDENTIFY, 527 .cdw10 = cpu_to_le32(0x1), 528 }; 529 size_t id_size = QEMU_ALIGN_UP(sizeof(*id), qemu_real_host_page_size); 530 531 id = qemu_try_memalign(qemu_real_host_page_size, id_size); 532 if (!id) { 533 error_setg(errp, "Cannot allocate buffer for identify response"); 534 goto out; 535 } 536 r = qemu_vfio_dma_map(s->vfio, id, id_size, true, &iova, errp); 537 if (r) { 538 error_prepend(errp, "Cannot map buffer for DMA: "); 539 goto out; 540 } 541 542 memset(id, 0, id_size); 543 cmd.dptr.prp1 = cpu_to_le64(iova); 544 if (nvme_admin_cmd_sync(bs, &cmd)) { 545 error_setg(errp, "Failed to identify controller"); 546 goto out; 547 } 548 549 if (le32_to_cpu(id->ctrl.nn) < namespace) { 550 error_setg(errp, "Invalid namespace"); 551 goto out; 552 } 553 s->write_cache_supported = le32_to_cpu(id->ctrl.vwc) & 0x1; 554 s->max_transfer = (id->ctrl.mdts ? 1 << id->ctrl.mdts : 0) * s->page_size; 555 /* For now the page list buffer per command is one page, to hold at most 556 * s->page_size / sizeof(uint64_t) entries. */ 557 s->max_transfer = MIN_NON_ZERO(s->max_transfer, 558 s->page_size / sizeof(uint64_t) * s->page_size); 559 560 oncs = le16_to_cpu(id->ctrl.oncs); 561 s->supports_write_zeroes = !!(oncs & NVME_ONCS_WRITE_ZEROES); 562 s->supports_discard = !!(oncs & NVME_ONCS_DSM); 563 564 memset(id, 0, id_size); 565 cmd.cdw10 = 0; 566 cmd.nsid = cpu_to_le32(namespace); 567 if (nvme_admin_cmd_sync(bs, &cmd)) { 568 error_setg(errp, "Failed to identify namespace"); 569 goto out; 570 } 571 572 s->nsze = le64_to_cpu(id->ns.nsze); 573 lbaf = &id->ns.lbaf[NVME_ID_NS_FLBAS_INDEX(id->ns.flbas)]; 574 575 if (NVME_ID_NS_DLFEAT_WRITE_ZEROES(id->ns.dlfeat) && 576 NVME_ID_NS_DLFEAT_READ_BEHAVIOR(id->ns.dlfeat) == 577 NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES) { 578 bs->supported_write_flags |= BDRV_REQ_MAY_UNMAP; 579 } 580 581 if (lbaf->ms) { 582 error_setg(errp, "Namespaces with metadata are not yet supported"); 583 goto out; 584 } 585 586 if (lbaf->ds < BDRV_SECTOR_BITS || lbaf->ds > 12 || 587 (1 << lbaf->ds) > s->page_size) 588 { 589 error_setg(errp, "Namespace has unsupported block size (2^%d)", 590 lbaf->ds); 591 goto out; 592 } 593 594 ret = true; 595 s->blkshift = lbaf->ds; 596 out: 597 qemu_vfio_dma_unmap(s->vfio, id); 598 qemu_vfree(id); 599 600 return ret; 601 } 602 603 static bool nvme_poll_queue(NVMeQueuePair *q) 604 { 605 bool progress = false; 606 607 const size_t cqe_offset = q->cq.head * NVME_CQ_ENTRY_BYTES; 608 NvmeCqe *cqe = (NvmeCqe *)&q->cq.queue[cqe_offset]; 609 610 trace_nvme_poll_queue(q->s, q->index); 611 /* 612 * Do an early check for completions. q->lock isn't needed because 613 * nvme_process_completion() only runs in the event loop thread and 614 * cannot race with itself. 615 */ 616 if ((le16_to_cpu(cqe->status) & 0x1) == q->cq_phase) { 617 return false; 618 } 619 620 qemu_mutex_lock(&q->lock); 621 while (nvme_process_completion(q)) { 622 /* Keep polling */ 623 progress = true; 624 } 625 qemu_mutex_unlock(&q->lock); 626 627 return progress; 628 } 629 630 static bool nvme_poll_queues(BDRVNVMeState *s) 631 { 632 bool progress = false; 633 int i; 634 635 for (i = 0; i < s->queue_count; i++) { 636 if (nvme_poll_queue(s->queues[i])) { 637 progress = true; 638 } 639 } 640 return progress; 641 } 642 643 static void nvme_handle_event(EventNotifier *n) 644 { 645 BDRVNVMeState *s = container_of(n, BDRVNVMeState, 646 irq_notifier[MSIX_SHARED_IRQ_IDX]); 647 648 trace_nvme_handle_event(s); 649 event_notifier_test_and_clear(n); 650 nvme_poll_queues(s); 651 } 652 653 static bool nvme_add_io_queue(BlockDriverState *bs, Error **errp) 654 { 655 BDRVNVMeState *s = bs->opaque; 656 unsigned n = s->queue_count; 657 NVMeQueuePair *q; 658 NvmeCmd cmd; 659 unsigned queue_size = NVME_QUEUE_SIZE; 660 661 assert(n <= UINT16_MAX); 662 q = nvme_create_queue_pair(s, bdrv_get_aio_context(bs), 663 n, queue_size, errp); 664 if (!q) { 665 return false; 666 } 667 cmd = (NvmeCmd) { 668 .opcode = NVME_ADM_CMD_CREATE_CQ, 669 .dptr.prp1 = cpu_to_le64(q->cq.iova), 670 .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n), 671 .cdw11 = cpu_to_le32(NVME_CQ_IEN | NVME_CQ_PC), 672 }; 673 if (nvme_admin_cmd_sync(bs, &cmd)) { 674 error_setg(errp, "Failed to create CQ io queue [%u]", n); 675 goto out_error; 676 } 677 cmd = (NvmeCmd) { 678 .opcode = NVME_ADM_CMD_CREATE_SQ, 679 .dptr.prp1 = cpu_to_le64(q->sq.iova), 680 .cdw10 = cpu_to_le32(((queue_size - 1) << 16) | n), 681 .cdw11 = cpu_to_le32(NVME_SQ_PC | (n << 16)), 682 }; 683 if (nvme_admin_cmd_sync(bs, &cmd)) { 684 error_setg(errp, "Failed to create SQ io queue [%u]", n); 685 goto out_error; 686 } 687 s->queues = g_renew(NVMeQueuePair *, s->queues, n + 1); 688 s->queues[n] = q; 689 s->queue_count++; 690 return true; 691 out_error: 692 nvme_free_queue_pair(q); 693 return false; 694 } 695 696 static bool nvme_poll_cb(void *opaque) 697 { 698 EventNotifier *e = opaque; 699 BDRVNVMeState *s = container_of(e, BDRVNVMeState, 700 irq_notifier[MSIX_SHARED_IRQ_IDX]); 701 702 return nvme_poll_queues(s); 703 } 704 705 static int nvme_init(BlockDriverState *bs, const char *device, int namespace, 706 Error **errp) 707 { 708 BDRVNVMeState *s = bs->opaque; 709 NVMeQueuePair *q; 710 AioContext *aio_context = bdrv_get_aio_context(bs); 711 int ret; 712 uint64_t cap; 713 uint32_t ver; 714 uint64_t timeout_ms; 715 uint64_t deadline, now; 716 volatile NvmeBar *regs = NULL; 717 718 qemu_co_mutex_init(&s->dma_map_lock); 719 qemu_co_queue_init(&s->dma_flush_queue); 720 s->device = g_strdup(device); 721 s->nsid = namespace; 722 s->aio_context = bdrv_get_aio_context(bs); 723 ret = event_notifier_init(&s->irq_notifier[MSIX_SHARED_IRQ_IDX], 0); 724 if (ret) { 725 error_setg(errp, "Failed to init event notifier"); 726 return ret; 727 } 728 729 s->vfio = qemu_vfio_open_pci(device, errp); 730 if (!s->vfio) { 731 ret = -EINVAL; 732 goto out; 733 } 734 735 regs = qemu_vfio_pci_map_bar(s->vfio, 0, 0, sizeof(NvmeBar), 736 PROT_READ | PROT_WRITE, errp); 737 if (!regs) { 738 ret = -EINVAL; 739 goto out; 740 } 741 /* Perform initialize sequence as described in NVMe spec "7.6.1 742 * Initialization". */ 743 744 cap = le64_to_cpu(regs->cap); 745 trace_nvme_controller_capability_raw(cap); 746 trace_nvme_controller_capability("Maximum Queue Entries Supported", 747 1 + NVME_CAP_MQES(cap)); 748 trace_nvme_controller_capability("Contiguous Queues Required", 749 NVME_CAP_CQR(cap)); 750 trace_nvme_controller_capability("Doorbell Stride", 751 1 << (2 + NVME_CAP_DSTRD(cap))); 752 trace_nvme_controller_capability("Subsystem Reset Supported", 753 NVME_CAP_NSSRS(cap)); 754 trace_nvme_controller_capability("Memory Page Size Minimum", 755 1 << (12 + NVME_CAP_MPSMIN(cap))); 756 trace_nvme_controller_capability("Memory Page Size Maximum", 757 1 << (12 + NVME_CAP_MPSMAX(cap))); 758 if (!NVME_CAP_CSS(cap)) { 759 error_setg(errp, "Device doesn't support NVMe command set"); 760 ret = -EINVAL; 761 goto out; 762 } 763 764 s->page_size = 1u << (12 + NVME_CAP_MPSMIN(cap)); 765 s->doorbell_scale = (4 << NVME_CAP_DSTRD(cap)) / sizeof(uint32_t); 766 bs->bl.opt_mem_alignment = s->page_size; 767 bs->bl.request_alignment = s->page_size; 768 timeout_ms = MIN(500 * NVME_CAP_TO(cap), 30000); 769 770 ver = le32_to_cpu(regs->vs); 771 trace_nvme_controller_spec_version(extract32(ver, 16, 16), 772 extract32(ver, 8, 8), 773 extract32(ver, 0, 8)); 774 775 /* Reset device to get a clean state. */ 776 regs->cc = cpu_to_le32(le32_to_cpu(regs->cc) & 0xFE); 777 /* Wait for CSTS.RDY = 0. */ 778 deadline = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCALE_MS; 779 while (NVME_CSTS_RDY(le32_to_cpu(regs->csts))) { 780 if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 781 error_setg(errp, "Timeout while waiting for device to reset (%" 782 PRId64 " ms)", 783 timeout_ms); 784 ret = -ETIMEDOUT; 785 goto out; 786 } 787 } 788 789 s->bar0_wo_map = qemu_vfio_pci_map_bar(s->vfio, 0, 0, 790 sizeof(NvmeBar) + NVME_DOORBELL_SIZE, 791 PROT_WRITE, errp); 792 s->doorbells = (void *)((uintptr_t)s->bar0_wo_map + sizeof(NvmeBar)); 793 if (!s->doorbells) { 794 ret = -EINVAL; 795 goto out; 796 } 797 798 /* Set up admin queue. */ 799 s->queues = g_new(NVMeQueuePair *, 1); 800 q = nvme_create_queue_pair(s, aio_context, 0, NVME_QUEUE_SIZE, errp); 801 if (!q) { 802 ret = -EINVAL; 803 goto out; 804 } 805 s->queues[INDEX_ADMIN] = q; 806 s->queue_count = 1; 807 QEMU_BUILD_BUG_ON((NVME_QUEUE_SIZE - 1) & 0xF000); 808 regs->aqa = cpu_to_le32(((NVME_QUEUE_SIZE - 1) << AQA_ACQS_SHIFT) | 809 ((NVME_QUEUE_SIZE - 1) << AQA_ASQS_SHIFT)); 810 regs->asq = cpu_to_le64(q->sq.iova); 811 regs->acq = cpu_to_le64(q->cq.iova); 812 813 /* After setting up all control registers we can enable device now. */ 814 regs->cc = cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << CC_IOCQES_SHIFT) | 815 (ctz32(NVME_SQ_ENTRY_BYTES) << CC_IOSQES_SHIFT) | 816 CC_EN_MASK); 817 /* Wait for CSTS.RDY = 1. */ 818 now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 819 deadline = now + timeout_ms * SCALE_MS; 820 while (!NVME_CSTS_RDY(le32_to_cpu(regs->csts))) { 821 if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { 822 error_setg(errp, "Timeout while waiting for device to start (%" 823 PRId64 " ms)", 824 timeout_ms); 825 ret = -ETIMEDOUT; 826 goto out; 827 } 828 } 829 830 ret = qemu_vfio_pci_init_irq(s->vfio, s->irq_notifier, 831 VFIO_PCI_MSIX_IRQ_INDEX, errp); 832 if (ret) { 833 goto out; 834 } 835 aio_set_event_notifier(bdrv_get_aio_context(bs), 836 &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 837 false, nvme_handle_event, nvme_poll_cb); 838 839 if (!nvme_identify(bs, namespace, errp)) { 840 ret = -EIO; 841 goto out; 842 } 843 844 /* Set up command queues. */ 845 if (!nvme_add_io_queue(bs, errp)) { 846 ret = -EIO; 847 } 848 out: 849 if (regs) { 850 qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)regs, 0, sizeof(NvmeBar)); 851 } 852 853 /* Cleaning up is done in nvme_file_open() upon error. */ 854 return ret; 855 } 856 857 /* Parse a filename in the format of nvme://XXXX:XX:XX.X/X. Example: 858 * 859 * nvme://0000:44:00.0/1 860 * 861 * where the "nvme://" is a fixed form of the protocol prefix, the middle part 862 * is the PCI address, and the last part is the namespace number starting from 863 * 1 according to the NVMe spec. */ 864 static void nvme_parse_filename(const char *filename, QDict *options, 865 Error **errp) 866 { 867 int pref = strlen("nvme://"); 868 869 if (strlen(filename) > pref && !strncmp(filename, "nvme://", pref)) { 870 const char *tmp = filename + pref; 871 char *device; 872 const char *namespace; 873 unsigned long ns; 874 const char *slash = strchr(tmp, '/'); 875 if (!slash) { 876 qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, tmp); 877 return; 878 } 879 device = g_strndup(tmp, slash - tmp); 880 qdict_put_str(options, NVME_BLOCK_OPT_DEVICE, device); 881 g_free(device); 882 namespace = slash + 1; 883 if (*namespace && qemu_strtoul(namespace, NULL, 10, &ns)) { 884 error_setg(errp, "Invalid namespace '%s', positive number expected", 885 namespace); 886 return; 887 } 888 qdict_put_str(options, NVME_BLOCK_OPT_NAMESPACE, 889 *namespace ? namespace : "1"); 890 } 891 } 892 893 static int nvme_enable_disable_write_cache(BlockDriverState *bs, bool enable, 894 Error **errp) 895 { 896 int ret; 897 BDRVNVMeState *s = bs->opaque; 898 NvmeCmd cmd = { 899 .opcode = NVME_ADM_CMD_SET_FEATURES, 900 .nsid = cpu_to_le32(s->nsid), 901 .cdw10 = cpu_to_le32(0x06), 902 .cdw11 = cpu_to_le32(enable ? 0x01 : 0x00), 903 }; 904 905 ret = nvme_admin_cmd_sync(bs, &cmd); 906 if (ret) { 907 error_setg(errp, "Failed to configure NVMe write cache"); 908 } 909 return ret; 910 } 911 912 static void nvme_close(BlockDriverState *bs) 913 { 914 BDRVNVMeState *s = bs->opaque; 915 916 for (unsigned i = 0; i < s->queue_count; ++i) { 917 nvme_free_queue_pair(s->queues[i]); 918 } 919 g_free(s->queues); 920 aio_set_event_notifier(bdrv_get_aio_context(bs), 921 &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 922 false, NULL, NULL); 923 event_notifier_cleanup(&s->irq_notifier[MSIX_SHARED_IRQ_IDX]); 924 qemu_vfio_pci_unmap_bar(s->vfio, 0, s->bar0_wo_map, 925 0, sizeof(NvmeBar) + NVME_DOORBELL_SIZE); 926 qemu_vfio_close(s->vfio); 927 928 g_free(s->device); 929 } 930 931 static int nvme_file_open(BlockDriverState *bs, QDict *options, int flags, 932 Error **errp) 933 { 934 const char *device; 935 QemuOpts *opts; 936 int namespace; 937 int ret; 938 BDRVNVMeState *s = bs->opaque; 939 940 bs->supported_write_flags = BDRV_REQ_FUA; 941 942 opts = qemu_opts_create(&runtime_opts, NULL, 0, &error_abort); 943 qemu_opts_absorb_qdict(opts, options, &error_abort); 944 device = qemu_opt_get(opts, NVME_BLOCK_OPT_DEVICE); 945 if (!device) { 946 error_setg(errp, "'" NVME_BLOCK_OPT_DEVICE "' option is required"); 947 qemu_opts_del(opts); 948 return -EINVAL; 949 } 950 951 namespace = qemu_opt_get_number(opts, NVME_BLOCK_OPT_NAMESPACE, 1); 952 ret = nvme_init(bs, device, namespace, errp); 953 qemu_opts_del(opts); 954 if (ret) { 955 goto fail; 956 } 957 if (flags & BDRV_O_NOCACHE) { 958 if (!s->write_cache_supported) { 959 error_setg(errp, 960 "NVMe controller doesn't support write cache configuration"); 961 ret = -EINVAL; 962 } else { 963 ret = nvme_enable_disable_write_cache(bs, !(flags & BDRV_O_NOCACHE), 964 errp); 965 } 966 if (ret) { 967 goto fail; 968 } 969 } 970 return 0; 971 fail: 972 nvme_close(bs); 973 return ret; 974 } 975 976 static int64_t nvme_getlength(BlockDriverState *bs) 977 { 978 BDRVNVMeState *s = bs->opaque; 979 return s->nsze << s->blkshift; 980 } 981 982 static uint32_t nvme_get_blocksize(BlockDriverState *bs) 983 { 984 BDRVNVMeState *s = bs->opaque; 985 assert(s->blkshift >= BDRV_SECTOR_BITS && s->blkshift <= 12); 986 return UINT32_C(1) << s->blkshift; 987 } 988 989 static int nvme_probe_blocksizes(BlockDriverState *bs, BlockSizes *bsz) 990 { 991 uint32_t blocksize = nvme_get_blocksize(bs); 992 bsz->phys = blocksize; 993 bsz->log = blocksize; 994 return 0; 995 } 996 997 /* Called with s->dma_map_lock */ 998 static coroutine_fn int nvme_cmd_unmap_qiov(BlockDriverState *bs, 999 QEMUIOVector *qiov) 1000 { 1001 int r = 0; 1002 BDRVNVMeState *s = bs->opaque; 1003 1004 s->dma_map_count -= qiov->size; 1005 if (!s->dma_map_count && !qemu_co_queue_empty(&s->dma_flush_queue)) { 1006 r = qemu_vfio_dma_reset_temporary(s->vfio); 1007 if (!r) { 1008 qemu_co_queue_restart_all(&s->dma_flush_queue); 1009 } 1010 } 1011 return r; 1012 } 1013 1014 /* Called with s->dma_map_lock */ 1015 static coroutine_fn int nvme_cmd_map_qiov(BlockDriverState *bs, NvmeCmd *cmd, 1016 NVMeRequest *req, QEMUIOVector *qiov) 1017 { 1018 BDRVNVMeState *s = bs->opaque; 1019 uint64_t *pagelist = req->prp_list_page; 1020 int i, j, r; 1021 int entries = 0; 1022 Error *local_err = NULL, **errp = NULL; 1023 1024 assert(qiov->size); 1025 assert(QEMU_IS_ALIGNED(qiov->size, s->page_size)); 1026 assert(qiov->size / s->page_size <= s->page_size / sizeof(uint64_t)); 1027 for (i = 0; i < qiov->niov; ++i) { 1028 bool retry = true; 1029 uint64_t iova; 1030 size_t len = QEMU_ALIGN_UP(qiov->iov[i].iov_len, 1031 qemu_real_host_page_size); 1032 try_map: 1033 r = qemu_vfio_dma_map(s->vfio, 1034 qiov->iov[i].iov_base, 1035 len, true, &iova, errp); 1036 if (r == -ENOSPC) { 1037 /* 1038 * In addition to the -ENOMEM error, the VFIO_IOMMU_MAP_DMA 1039 * ioctl returns -ENOSPC to signal the user exhausted the DMA 1040 * mappings available for a container since Linux kernel commit 1041 * 492855939bdb ("vfio/type1: Limit DMA mappings per container", 1042 * April 2019, see CVE-2019-3882). 1043 * 1044 * This block driver already handles this error path by checking 1045 * for the -ENOMEM error, so we directly replace -ENOSPC by 1046 * -ENOMEM. Beside, -ENOSPC has a specific meaning for blockdev 1047 * coroutines: it triggers BLOCKDEV_ON_ERROR_ENOSPC and 1048 * BLOCK_ERROR_ACTION_STOP which stops the VM, asking the operator 1049 * to add more storage to the blockdev. Not something we can do 1050 * easily with an IOMMU :) 1051 */ 1052 r = -ENOMEM; 1053 } 1054 if (r == -ENOMEM && retry) { 1055 /* 1056 * We exhausted the DMA mappings available for our container: 1057 * recycle the volatile IOVA mappings. 1058 */ 1059 retry = false; 1060 trace_nvme_dma_flush_queue_wait(s); 1061 if (s->dma_map_count) { 1062 trace_nvme_dma_map_flush(s); 1063 qemu_co_queue_wait(&s->dma_flush_queue, &s->dma_map_lock); 1064 } else { 1065 r = qemu_vfio_dma_reset_temporary(s->vfio); 1066 if (r) { 1067 goto fail; 1068 } 1069 } 1070 errp = &local_err; 1071 1072 goto try_map; 1073 } 1074 if (r) { 1075 goto fail; 1076 } 1077 1078 for (j = 0; j < qiov->iov[i].iov_len / s->page_size; j++) { 1079 pagelist[entries++] = cpu_to_le64(iova + j * s->page_size); 1080 } 1081 trace_nvme_cmd_map_qiov_iov(s, i, qiov->iov[i].iov_base, 1082 qiov->iov[i].iov_len / s->page_size); 1083 } 1084 1085 s->dma_map_count += qiov->size; 1086 1087 assert(entries <= s->page_size / sizeof(uint64_t)); 1088 switch (entries) { 1089 case 0: 1090 abort(); 1091 case 1: 1092 cmd->dptr.prp1 = pagelist[0]; 1093 cmd->dptr.prp2 = 0; 1094 break; 1095 case 2: 1096 cmd->dptr.prp1 = pagelist[0]; 1097 cmd->dptr.prp2 = pagelist[1]; 1098 break; 1099 default: 1100 cmd->dptr.prp1 = pagelist[0]; 1101 cmd->dptr.prp2 = cpu_to_le64(req->prp_list_iova + sizeof(uint64_t)); 1102 break; 1103 } 1104 trace_nvme_cmd_map_qiov(s, cmd, req, qiov, entries); 1105 for (i = 0; i < entries; ++i) { 1106 trace_nvme_cmd_map_qiov_pages(s, i, pagelist[i]); 1107 } 1108 return 0; 1109 fail: 1110 /* No need to unmap [0 - i) iovs even if we've failed, since we don't 1111 * increment s->dma_map_count. This is okay for fixed mapping memory areas 1112 * because they are already mapped before calling this function; for 1113 * temporary mappings, a later nvme_cmd_(un)map_qiov will reclaim by 1114 * calling qemu_vfio_dma_reset_temporary when necessary. */ 1115 if (local_err) { 1116 error_reportf_err(local_err, "Cannot map buffer for DMA: "); 1117 } 1118 return r; 1119 } 1120 1121 typedef struct { 1122 Coroutine *co; 1123 int ret; 1124 AioContext *ctx; 1125 } NVMeCoData; 1126 1127 static void nvme_rw_cb_bh(void *opaque) 1128 { 1129 NVMeCoData *data = opaque; 1130 qemu_coroutine_enter(data->co); 1131 } 1132 1133 static void nvme_rw_cb(void *opaque, int ret) 1134 { 1135 NVMeCoData *data = opaque; 1136 data->ret = ret; 1137 if (!data->co) { 1138 /* The rw coroutine hasn't yielded, don't try to enter. */ 1139 return; 1140 } 1141 replay_bh_schedule_oneshot_event(data->ctx, nvme_rw_cb_bh, data); 1142 } 1143 1144 static coroutine_fn int nvme_co_prw_aligned(BlockDriverState *bs, 1145 uint64_t offset, uint64_t bytes, 1146 QEMUIOVector *qiov, 1147 bool is_write, 1148 int flags) 1149 { 1150 int r; 1151 BDRVNVMeState *s = bs->opaque; 1152 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1153 NVMeRequest *req; 1154 1155 uint32_t cdw12 = (((bytes >> s->blkshift) - 1) & 0xFFFF) | 1156 (flags & BDRV_REQ_FUA ? 1 << 30 : 0); 1157 NvmeCmd cmd = { 1158 .opcode = is_write ? NVME_CMD_WRITE : NVME_CMD_READ, 1159 .nsid = cpu_to_le32(s->nsid), 1160 .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF), 1161 .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF), 1162 .cdw12 = cpu_to_le32(cdw12), 1163 }; 1164 NVMeCoData data = { 1165 .ctx = bdrv_get_aio_context(bs), 1166 .ret = -EINPROGRESS, 1167 }; 1168 1169 trace_nvme_prw_aligned(s, is_write, offset, bytes, flags, qiov->niov); 1170 assert(s->queue_count > 1); 1171 req = nvme_get_free_req(ioq); 1172 assert(req); 1173 1174 qemu_co_mutex_lock(&s->dma_map_lock); 1175 r = nvme_cmd_map_qiov(bs, &cmd, req, qiov); 1176 qemu_co_mutex_unlock(&s->dma_map_lock); 1177 if (r) { 1178 nvme_put_free_req_and_wake(ioq, req); 1179 return r; 1180 } 1181 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1182 1183 data.co = qemu_coroutine_self(); 1184 while (data.ret == -EINPROGRESS) { 1185 qemu_coroutine_yield(); 1186 } 1187 1188 qemu_co_mutex_lock(&s->dma_map_lock); 1189 r = nvme_cmd_unmap_qiov(bs, qiov); 1190 qemu_co_mutex_unlock(&s->dma_map_lock); 1191 if (r) { 1192 return r; 1193 } 1194 1195 trace_nvme_rw_done(s, is_write, offset, bytes, data.ret); 1196 return data.ret; 1197 } 1198 1199 static inline bool nvme_qiov_aligned(BlockDriverState *bs, 1200 const QEMUIOVector *qiov) 1201 { 1202 int i; 1203 BDRVNVMeState *s = bs->opaque; 1204 1205 for (i = 0; i < qiov->niov; ++i) { 1206 if (!QEMU_PTR_IS_ALIGNED(qiov->iov[i].iov_base, 1207 qemu_real_host_page_size) || 1208 !QEMU_IS_ALIGNED(qiov->iov[i].iov_len, qemu_real_host_page_size)) { 1209 trace_nvme_qiov_unaligned(qiov, i, qiov->iov[i].iov_base, 1210 qiov->iov[i].iov_len, s->page_size); 1211 return false; 1212 } 1213 } 1214 return true; 1215 } 1216 1217 static int nvme_co_prw(BlockDriverState *bs, uint64_t offset, uint64_t bytes, 1218 QEMUIOVector *qiov, bool is_write, int flags) 1219 { 1220 BDRVNVMeState *s = bs->opaque; 1221 int r; 1222 uint8_t *buf = NULL; 1223 QEMUIOVector local_qiov; 1224 size_t len = QEMU_ALIGN_UP(bytes, qemu_real_host_page_size); 1225 assert(QEMU_IS_ALIGNED(offset, s->page_size)); 1226 assert(QEMU_IS_ALIGNED(bytes, s->page_size)); 1227 assert(bytes <= s->max_transfer); 1228 if (nvme_qiov_aligned(bs, qiov)) { 1229 s->stats.aligned_accesses++; 1230 return nvme_co_prw_aligned(bs, offset, bytes, qiov, is_write, flags); 1231 } 1232 s->stats.unaligned_accesses++; 1233 trace_nvme_prw_buffered(s, offset, bytes, qiov->niov, is_write); 1234 buf = qemu_try_memalign(qemu_real_host_page_size, len); 1235 1236 if (!buf) { 1237 return -ENOMEM; 1238 } 1239 qemu_iovec_init(&local_qiov, 1); 1240 if (is_write) { 1241 qemu_iovec_to_buf(qiov, 0, buf, bytes); 1242 } 1243 qemu_iovec_add(&local_qiov, buf, bytes); 1244 r = nvme_co_prw_aligned(bs, offset, bytes, &local_qiov, is_write, flags); 1245 qemu_iovec_destroy(&local_qiov); 1246 if (!r && !is_write) { 1247 qemu_iovec_from_buf(qiov, 0, buf, bytes); 1248 } 1249 qemu_vfree(buf); 1250 return r; 1251 } 1252 1253 static coroutine_fn int nvme_co_preadv(BlockDriverState *bs, 1254 int64_t offset, int64_t bytes, 1255 QEMUIOVector *qiov, 1256 BdrvRequestFlags flags) 1257 { 1258 return nvme_co_prw(bs, offset, bytes, qiov, false, flags); 1259 } 1260 1261 static coroutine_fn int nvme_co_pwritev(BlockDriverState *bs, 1262 int64_t offset, int64_t bytes, 1263 QEMUIOVector *qiov, 1264 BdrvRequestFlags flags) 1265 { 1266 return nvme_co_prw(bs, offset, bytes, qiov, true, flags); 1267 } 1268 1269 static coroutine_fn int nvme_co_flush(BlockDriverState *bs) 1270 { 1271 BDRVNVMeState *s = bs->opaque; 1272 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1273 NVMeRequest *req; 1274 NvmeCmd cmd = { 1275 .opcode = NVME_CMD_FLUSH, 1276 .nsid = cpu_to_le32(s->nsid), 1277 }; 1278 NVMeCoData data = { 1279 .ctx = bdrv_get_aio_context(bs), 1280 .ret = -EINPROGRESS, 1281 }; 1282 1283 assert(s->queue_count > 1); 1284 req = nvme_get_free_req(ioq); 1285 assert(req); 1286 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1287 1288 data.co = qemu_coroutine_self(); 1289 if (data.ret == -EINPROGRESS) { 1290 qemu_coroutine_yield(); 1291 } 1292 1293 return data.ret; 1294 } 1295 1296 1297 static coroutine_fn int nvme_co_pwrite_zeroes(BlockDriverState *bs, 1298 int64_t offset, 1299 int64_t bytes, 1300 BdrvRequestFlags flags) 1301 { 1302 BDRVNVMeState *s = bs->opaque; 1303 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1304 NVMeRequest *req; 1305 uint32_t cdw12; 1306 1307 if (!s->supports_write_zeroes) { 1308 return -ENOTSUP; 1309 } 1310 1311 if (bytes == 0) { 1312 return 0; 1313 } 1314 1315 cdw12 = ((bytes >> s->blkshift) - 1) & 0xFFFF; 1316 /* 1317 * We should not lose information. pwrite_zeroes_alignment and 1318 * max_pwrite_zeroes guarantees it. 1319 */ 1320 assert(((cdw12 + 1) << s->blkshift) == bytes); 1321 1322 NvmeCmd cmd = { 1323 .opcode = NVME_CMD_WRITE_ZEROES, 1324 .nsid = cpu_to_le32(s->nsid), 1325 .cdw10 = cpu_to_le32((offset >> s->blkshift) & 0xFFFFFFFF), 1326 .cdw11 = cpu_to_le32(((offset >> s->blkshift) >> 32) & 0xFFFFFFFF), 1327 }; 1328 1329 NVMeCoData data = { 1330 .ctx = bdrv_get_aio_context(bs), 1331 .ret = -EINPROGRESS, 1332 }; 1333 1334 if (flags & BDRV_REQ_MAY_UNMAP) { 1335 cdw12 |= (1 << 25); 1336 } 1337 1338 if (flags & BDRV_REQ_FUA) { 1339 cdw12 |= (1 << 30); 1340 } 1341 1342 cmd.cdw12 = cpu_to_le32(cdw12); 1343 1344 trace_nvme_write_zeroes(s, offset, bytes, flags); 1345 assert(s->queue_count > 1); 1346 req = nvme_get_free_req(ioq); 1347 assert(req); 1348 1349 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1350 1351 data.co = qemu_coroutine_self(); 1352 while (data.ret == -EINPROGRESS) { 1353 qemu_coroutine_yield(); 1354 } 1355 1356 trace_nvme_rw_done(s, true, offset, bytes, data.ret); 1357 return data.ret; 1358 } 1359 1360 1361 static int coroutine_fn nvme_co_pdiscard(BlockDriverState *bs, 1362 int64_t offset, 1363 int64_t bytes) 1364 { 1365 BDRVNVMeState *s = bs->opaque; 1366 NVMeQueuePair *ioq = s->queues[INDEX_IO(0)]; 1367 NVMeRequest *req; 1368 NvmeDsmRange *buf; 1369 QEMUIOVector local_qiov; 1370 int ret; 1371 1372 NvmeCmd cmd = { 1373 .opcode = NVME_CMD_DSM, 1374 .nsid = cpu_to_le32(s->nsid), 1375 .cdw10 = cpu_to_le32(0), /*number of ranges - 0 based*/ 1376 .cdw11 = cpu_to_le32(1 << 2), /*deallocate bit*/ 1377 }; 1378 1379 NVMeCoData data = { 1380 .ctx = bdrv_get_aio_context(bs), 1381 .ret = -EINPROGRESS, 1382 }; 1383 1384 if (!s->supports_discard) { 1385 return -ENOTSUP; 1386 } 1387 1388 assert(s->queue_count > 1); 1389 1390 /* 1391 * Filling the @buf requires @offset and @bytes to satisfy restrictions 1392 * defined in nvme_refresh_limits(). 1393 */ 1394 assert(QEMU_IS_ALIGNED(bytes, 1UL << s->blkshift)); 1395 assert(QEMU_IS_ALIGNED(offset, 1UL << s->blkshift)); 1396 assert((bytes >> s->blkshift) <= UINT32_MAX); 1397 1398 buf = qemu_try_memalign(s->page_size, s->page_size); 1399 if (!buf) { 1400 return -ENOMEM; 1401 } 1402 memset(buf, 0, s->page_size); 1403 buf->nlb = cpu_to_le32(bytes >> s->blkshift); 1404 buf->slba = cpu_to_le64(offset >> s->blkshift); 1405 buf->cattr = 0; 1406 1407 qemu_iovec_init(&local_qiov, 1); 1408 qemu_iovec_add(&local_qiov, buf, 4096); 1409 1410 req = nvme_get_free_req(ioq); 1411 assert(req); 1412 1413 qemu_co_mutex_lock(&s->dma_map_lock); 1414 ret = nvme_cmd_map_qiov(bs, &cmd, req, &local_qiov); 1415 qemu_co_mutex_unlock(&s->dma_map_lock); 1416 1417 if (ret) { 1418 nvme_put_free_req_and_wake(ioq, req); 1419 goto out; 1420 } 1421 1422 trace_nvme_dsm(s, offset, bytes); 1423 1424 nvme_submit_command(ioq, req, &cmd, nvme_rw_cb, &data); 1425 1426 data.co = qemu_coroutine_self(); 1427 while (data.ret == -EINPROGRESS) { 1428 qemu_coroutine_yield(); 1429 } 1430 1431 qemu_co_mutex_lock(&s->dma_map_lock); 1432 ret = nvme_cmd_unmap_qiov(bs, &local_qiov); 1433 qemu_co_mutex_unlock(&s->dma_map_lock); 1434 1435 if (ret) { 1436 goto out; 1437 } 1438 1439 ret = data.ret; 1440 trace_nvme_dsm_done(s, offset, bytes, ret); 1441 out: 1442 qemu_iovec_destroy(&local_qiov); 1443 qemu_vfree(buf); 1444 return ret; 1445 1446 } 1447 1448 static int coroutine_fn nvme_co_truncate(BlockDriverState *bs, int64_t offset, 1449 bool exact, PreallocMode prealloc, 1450 BdrvRequestFlags flags, Error **errp) 1451 { 1452 int64_t cur_length; 1453 1454 if (prealloc != PREALLOC_MODE_OFF) { 1455 error_setg(errp, "Unsupported preallocation mode '%s'", 1456 PreallocMode_str(prealloc)); 1457 return -ENOTSUP; 1458 } 1459 1460 cur_length = nvme_getlength(bs); 1461 if (offset != cur_length && exact) { 1462 error_setg(errp, "Cannot resize NVMe devices"); 1463 return -ENOTSUP; 1464 } else if (offset > cur_length) { 1465 error_setg(errp, "Cannot grow NVMe devices"); 1466 return -EINVAL; 1467 } 1468 1469 return 0; 1470 } 1471 1472 static int nvme_reopen_prepare(BDRVReopenState *reopen_state, 1473 BlockReopenQueue *queue, Error **errp) 1474 { 1475 return 0; 1476 } 1477 1478 static void nvme_refresh_filename(BlockDriverState *bs) 1479 { 1480 BDRVNVMeState *s = bs->opaque; 1481 1482 snprintf(bs->exact_filename, sizeof(bs->exact_filename), "nvme://%s/%i", 1483 s->device, s->nsid); 1484 } 1485 1486 static void nvme_refresh_limits(BlockDriverState *bs, Error **errp) 1487 { 1488 BDRVNVMeState *s = bs->opaque; 1489 1490 bs->bl.opt_mem_alignment = s->page_size; 1491 bs->bl.request_alignment = s->page_size; 1492 bs->bl.max_transfer = s->max_transfer; 1493 1494 /* 1495 * Look at nvme_co_pwrite_zeroes: after shift and decrement we should get 1496 * at most 0xFFFF 1497 */ 1498 bs->bl.max_pwrite_zeroes = 1ULL << (s->blkshift + 16); 1499 bs->bl.pwrite_zeroes_alignment = MAX(bs->bl.request_alignment, 1500 1UL << s->blkshift); 1501 1502 bs->bl.max_pdiscard = (uint64_t)UINT32_MAX << s->blkshift; 1503 bs->bl.pdiscard_alignment = MAX(bs->bl.request_alignment, 1504 1UL << s->blkshift); 1505 } 1506 1507 static void nvme_detach_aio_context(BlockDriverState *bs) 1508 { 1509 BDRVNVMeState *s = bs->opaque; 1510 1511 for (unsigned i = 0; i < s->queue_count; i++) { 1512 NVMeQueuePair *q = s->queues[i]; 1513 1514 qemu_bh_delete(q->completion_bh); 1515 q->completion_bh = NULL; 1516 } 1517 1518 aio_set_event_notifier(bdrv_get_aio_context(bs), 1519 &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 1520 false, NULL, NULL); 1521 } 1522 1523 static void nvme_attach_aio_context(BlockDriverState *bs, 1524 AioContext *new_context) 1525 { 1526 BDRVNVMeState *s = bs->opaque; 1527 1528 s->aio_context = new_context; 1529 aio_set_event_notifier(new_context, &s->irq_notifier[MSIX_SHARED_IRQ_IDX], 1530 false, nvme_handle_event, nvme_poll_cb); 1531 1532 for (unsigned i = 0; i < s->queue_count; i++) { 1533 NVMeQueuePair *q = s->queues[i]; 1534 1535 q->completion_bh = 1536 aio_bh_new(new_context, nvme_process_completion_bh, q); 1537 } 1538 } 1539 1540 static void nvme_aio_plug(BlockDriverState *bs) 1541 { 1542 BDRVNVMeState *s = bs->opaque; 1543 assert(!s->plugged); 1544 s->plugged = true; 1545 } 1546 1547 static void nvme_aio_unplug(BlockDriverState *bs) 1548 { 1549 BDRVNVMeState *s = bs->opaque; 1550 assert(s->plugged); 1551 s->plugged = false; 1552 for (unsigned i = INDEX_IO(0); i < s->queue_count; i++) { 1553 NVMeQueuePair *q = s->queues[i]; 1554 qemu_mutex_lock(&q->lock); 1555 nvme_kick(q); 1556 nvme_process_completion(q); 1557 qemu_mutex_unlock(&q->lock); 1558 } 1559 } 1560 1561 static void nvme_register_buf(BlockDriverState *bs, void *host, size_t size) 1562 { 1563 int ret; 1564 Error *local_err = NULL; 1565 BDRVNVMeState *s = bs->opaque; 1566 1567 ret = qemu_vfio_dma_map(s->vfio, host, size, false, NULL, &local_err); 1568 if (ret) { 1569 /* FIXME: we may run out of IOVA addresses after repeated 1570 * bdrv_register_buf/bdrv_unregister_buf, because nvme_vfio_dma_unmap 1571 * doesn't reclaim addresses for fixed mappings. */ 1572 error_reportf_err(local_err, "nvme_register_buf failed: "); 1573 } 1574 } 1575 1576 static void nvme_unregister_buf(BlockDriverState *bs, void *host) 1577 { 1578 BDRVNVMeState *s = bs->opaque; 1579 1580 qemu_vfio_dma_unmap(s->vfio, host); 1581 } 1582 1583 static BlockStatsSpecific *nvme_get_specific_stats(BlockDriverState *bs) 1584 { 1585 BlockStatsSpecific *stats = g_new(BlockStatsSpecific, 1); 1586 BDRVNVMeState *s = bs->opaque; 1587 1588 stats->driver = BLOCKDEV_DRIVER_NVME; 1589 stats->u.nvme = (BlockStatsSpecificNvme) { 1590 .completion_errors = s->stats.completion_errors, 1591 .aligned_accesses = s->stats.aligned_accesses, 1592 .unaligned_accesses = s->stats.unaligned_accesses, 1593 }; 1594 1595 return stats; 1596 } 1597 1598 static const char *const nvme_strong_runtime_opts[] = { 1599 NVME_BLOCK_OPT_DEVICE, 1600 NVME_BLOCK_OPT_NAMESPACE, 1601 1602 NULL 1603 }; 1604 1605 static BlockDriver bdrv_nvme = { 1606 .format_name = "nvme", 1607 .protocol_name = "nvme", 1608 .instance_size = sizeof(BDRVNVMeState), 1609 1610 .bdrv_co_create_opts = bdrv_co_create_opts_simple, 1611 .create_opts = &bdrv_create_opts_simple, 1612 1613 .bdrv_parse_filename = nvme_parse_filename, 1614 .bdrv_file_open = nvme_file_open, 1615 .bdrv_close = nvme_close, 1616 .bdrv_getlength = nvme_getlength, 1617 .bdrv_probe_blocksizes = nvme_probe_blocksizes, 1618 .bdrv_co_truncate = nvme_co_truncate, 1619 1620 .bdrv_co_preadv = nvme_co_preadv, 1621 .bdrv_co_pwritev = nvme_co_pwritev, 1622 1623 .bdrv_co_pwrite_zeroes = nvme_co_pwrite_zeroes, 1624 .bdrv_co_pdiscard = nvme_co_pdiscard, 1625 1626 .bdrv_co_flush_to_disk = nvme_co_flush, 1627 .bdrv_reopen_prepare = nvme_reopen_prepare, 1628 1629 .bdrv_refresh_filename = nvme_refresh_filename, 1630 .bdrv_refresh_limits = nvme_refresh_limits, 1631 .strong_runtime_opts = nvme_strong_runtime_opts, 1632 .bdrv_get_specific_stats = nvme_get_specific_stats, 1633 1634 .bdrv_detach_aio_context = nvme_detach_aio_context, 1635 .bdrv_attach_aio_context = nvme_attach_aio_context, 1636 1637 .bdrv_io_plug = nvme_aio_plug, 1638 .bdrv_io_unplug = nvme_aio_unplug, 1639 1640 .bdrv_register_buf = nvme_register_buf, 1641 .bdrv_unregister_buf = nvme_unregister_buf, 1642 }; 1643 1644 static void bdrv_nvme_init(void) 1645 { 1646 bdrv_register(&bdrv_nvme); 1647 } 1648 1649 block_init(bdrv_nvme_init); 1650