1 /* 2 * User emulator execution 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "disas/disas.h" 22 #include "exec/exec-all.h" 23 #include "tcg.h" 24 #include "qemu/bitops.h" 25 #include "exec/cpu_ldst.h" 26 #include "translate-all.h" 27 #include "exec/helper-proto.h" 28 #include "qemu/atomic128.h" 29 #include "trace-root.h" 30 #include "trace/mem.h" 31 32 #undef EAX 33 #undef ECX 34 #undef EDX 35 #undef EBX 36 #undef ESP 37 #undef EBP 38 #undef ESI 39 #undef EDI 40 #undef EIP 41 #ifdef __linux__ 42 #include <sys/ucontext.h> 43 #endif 44 45 __thread uintptr_t helper_retaddr; 46 47 //#define DEBUG_SIGNAL 48 49 /* exit the current TB from a signal handler. The host registers are 50 restored in a state compatible with the CPU emulator 51 */ 52 static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set) 53 { 54 /* XXX: use siglongjmp ? */ 55 sigprocmask(SIG_SETMASK, old_set, NULL); 56 cpu_loop_exit_noexc(cpu); 57 } 58 59 /* 'pc' is the host PC at which the exception was raised. 'address' is 60 the effective address of the memory exception. 'is_write' is 1 if a 61 write caused the exception and otherwise 0'. 'old_set' is the 62 signal set which should be restored */ 63 static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, 64 int is_write, sigset_t *old_set) 65 { 66 CPUState *cpu = current_cpu; 67 CPUClass *cc; 68 unsigned long address = (unsigned long)info->si_addr; 69 MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; 70 71 switch (helper_retaddr) { 72 default: 73 /* 74 * Fault during host memory operation within a helper function. 75 * The helper's host return address, saved here, gives us a 76 * pointer into the generated code that will unwind to the 77 * correct guest pc. 78 */ 79 pc = helper_retaddr; 80 break; 81 82 case 0: 83 /* 84 * Fault during host memory operation within generated code. 85 * (Or, a unrelated bug within qemu, but we can't tell from here). 86 * 87 * We take the host pc from the signal frame. However, we cannot 88 * use that value directly. Within cpu_restore_state_from_tb, we 89 * assume PC comes from GETPC(), as used by the helper functions, 90 * so we adjust the address by -GETPC_ADJ to form an address that 91 * is within the call insn, so that the address does not accidentially 92 * match the beginning of the next guest insn. However, when the 93 * pc comes from the signal frame it points to the actual faulting 94 * host memory insn and not the return from a call insn. 95 * 96 * Therefore, adjust to compensate for what will be done later 97 * by cpu_restore_state_from_tb. 98 */ 99 pc += GETPC_ADJ; 100 break; 101 102 case 1: 103 /* 104 * Fault during host read for translation, or loosely, "execution". 105 * 106 * The guest pc is already pointing to the start of the TB for which 107 * code is being generated. If the guest translator manages the 108 * page crossings correctly, this is exactly the correct address 109 * (and if the translator doesn't handle page boundaries correctly 110 * there's little we can do about that here). Therefore, do not 111 * trigger the unwinder. 112 * 113 * Like tb_gen_code, release the memory lock before cpu_loop_exit. 114 */ 115 pc = 0; 116 access_type = MMU_INST_FETCH; 117 mmap_unlock(); 118 break; 119 } 120 121 /* For synchronous signals we expect to be coming from the vCPU 122 * thread (so current_cpu should be valid) and either from running 123 * code or during translation which can fault as we cross pages. 124 * 125 * If neither is true then something has gone wrong and we should 126 * abort rather than try and restart the vCPU execution. 127 */ 128 if (!cpu || !cpu->running) { 129 printf("qemu:%s received signal outside vCPU context @ pc=0x%" 130 PRIxPTR "\n", __func__, pc); 131 abort(); 132 } 133 134 #if defined(DEBUG_SIGNAL) 135 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 136 pc, address, is_write, *(unsigned long *)old_set); 137 #endif 138 /* XXX: locking issue */ 139 /* Note that it is important that we don't call page_unprotect() unless 140 * this is really a "write to nonwriteable page" fault, because 141 * page_unprotect() assumes that if it is called for an access to 142 * a page that's writeable this means we had two threads racing and 143 * another thread got there first and already made the page writeable; 144 * so we will retry the access. If we were to call page_unprotect() 145 * for some other kind of fault that should really be passed to the 146 * guest, we'd end up in an infinite loop of retrying the faulting 147 * access. 148 */ 149 if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR && 150 h2g_valid(address)) { 151 switch (page_unprotect(h2g(address), pc)) { 152 case 0: 153 /* Fault not caused by a page marked unwritable to protect 154 * cached translations, must be the guest binary's problem. 155 */ 156 break; 157 case 1: 158 /* Fault caused by protection of cached translation; TBs 159 * invalidated, so resume execution. Retain helper_retaddr 160 * for a possible second fault. 161 */ 162 return 1; 163 case 2: 164 /* Fault caused by protection of cached translation, and the 165 * currently executing TB was modified and must be exited 166 * immediately. Clear helper_retaddr for next execution. 167 */ 168 clear_helper_retaddr(); 169 cpu_exit_tb_from_sighandler(cpu, old_set); 170 /* NORETURN */ 171 172 default: 173 g_assert_not_reached(); 174 } 175 } 176 177 /* Convert forcefully to guest address space, invalid addresses 178 are still valid segv ones */ 179 address = h2g_nocheck(address); 180 181 /* 182 * There is no way the target can handle this other than raising 183 * an exception. Undo signal and retaddr state prior to longjmp. 184 */ 185 sigprocmask(SIG_SETMASK, old_set, NULL); 186 clear_helper_retaddr(); 187 188 cc = CPU_GET_CLASS(cpu); 189 cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); 190 g_assert_not_reached(); 191 } 192 193 void *probe_access(CPUArchState *env, target_ulong addr, int size, 194 MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) 195 { 196 int flags; 197 198 g_assert(-(addr | TARGET_PAGE_MASK) >= size); 199 200 switch (access_type) { 201 case MMU_DATA_STORE: 202 flags = PAGE_WRITE; 203 break; 204 case MMU_DATA_LOAD: 205 flags = PAGE_READ; 206 break; 207 case MMU_INST_FETCH: 208 flags = PAGE_EXEC; 209 break; 210 default: 211 g_assert_not_reached(); 212 } 213 214 if (!guest_addr_valid(addr) || page_check_range(addr, size, flags) < 0) { 215 CPUState *cpu = env_cpu(env); 216 CPUClass *cc = CPU_GET_CLASS(cpu); 217 cc->tlb_fill(cpu, addr, size, access_type, MMU_USER_IDX, false, 218 retaddr); 219 g_assert_not_reached(); 220 } 221 222 return size ? g2h(addr) : NULL; 223 } 224 225 #if defined(__i386__) 226 227 #if defined(__NetBSD__) 228 #include <ucontext.h> 229 230 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) 231 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 232 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 233 #define MASK_sig(context) ((context)->uc_sigmask) 234 #elif defined(__FreeBSD__) || defined(__DragonFly__) 235 #include <ucontext.h> 236 237 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) 238 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 239 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 240 #define MASK_sig(context) ((context)->uc_sigmask) 241 #elif defined(__OpenBSD__) 242 #define EIP_sig(context) ((context)->sc_eip) 243 #define TRAP_sig(context) ((context)->sc_trapno) 244 #define ERROR_sig(context) ((context)->sc_err) 245 #define MASK_sig(context) ((context)->sc_mask) 246 #else 247 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) 248 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 249 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 250 #define MASK_sig(context) ((context)->uc_sigmask) 251 #endif 252 253 int cpu_signal_handler(int host_signum, void *pinfo, 254 void *puc) 255 { 256 siginfo_t *info = pinfo; 257 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 258 ucontext_t *uc = puc; 259 #elif defined(__OpenBSD__) 260 struct sigcontext *uc = puc; 261 #else 262 ucontext_t *uc = puc; 263 #endif 264 unsigned long pc; 265 int trapno; 266 267 #ifndef REG_EIP 268 /* for glibc 2.1 */ 269 #define REG_EIP EIP 270 #define REG_ERR ERR 271 #define REG_TRAPNO TRAPNO 272 #endif 273 pc = EIP_sig(uc); 274 trapno = TRAP_sig(uc); 275 return handle_cpu_signal(pc, info, 276 trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 277 &MASK_sig(uc)); 278 } 279 280 #elif defined(__x86_64__) 281 282 #ifdef __NetBSD__ 283 #define PC_sig(context) _UC_MACHINE_PC(context) 284 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 285 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 286 #define MASK_sig(context) ((context)->uc_sigmask) 287 #elif defined(__OpenBSD__) 288 #define PC_sig(context) ((context)->sc_rip) 289 #define TRAP_sig(context) ((context)->sc_trapno) 290 #define ERROR_sig(context) ((context)->sc_err) 291 #define MASK_sig(context) ((context)->sc_mask) 292 #elif defined(__FreeBSD__) || defined(__DragonFly__) 293 #include <ucontext.h> 294 295 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) 296 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 297 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 298 #define MASK_sig(context) ((context)->uc_sigmask) 299 #else 300 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) 301 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 302 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 303 #define MASK_sig(context) ((context)->uc_sigmask) 304 #endif 305 306 int cpu_signal_handler(int host_signum, void *pinfo, 307 void *puc) 308 { 309 siginfo_t *info = pinfo; 310 unsigned long pc; 311 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 312 ucontext_t *uc = puc; 313 #elif defined(__OpenBSD__) 314 struct sigcontext *uc = puc; 315 #else 316 ucontext_t *uc = puc; 317 #endif 318 319 pc = PC_sig(uc); 320 return handle_cpu_signal(pc, info, 321 TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 322 &MASK_sig(uc)); 323 } 324 325 #elif defined(_ARCH_PPC) 326 327 /*********************************************************************** 328 * signal context platform-specific definitions 329 * From Wine 330 */ 331 #ifdef linux 332 /* All Registers access - only for local access */ 333 #define REG_sig(reg_name, context) \ 334 ((context)->uc_mcontext.regs->reg_name) 335 /* Gpr Registers access */ 336 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) 337 /* Program counter */ 338 #define IAR_sig(context) REG_sig(nip, context) 339 /* Machine State Register (Supervisor) */ 340 #define MSR_sig(context) REG_sig(msr, context) 341 /* Count register */ 342 #define CTR_sig(context) REG_sig(ctr, context) 343 /* User's integer exception register */ 344 #define XER_sig(context) REG_sig(xer, context) 345 /* Link register */ 346 #define LR_sig(context) REG_sig(link, context) 347 /* Condition register */ 348 #define CR_sig(context) REG_sig(ccr, context) 349 350 /* Float Registers access */ 351 #define FLOAT_sig(reg_num, context) \ 352 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) 353 #define FPSCR_sig(context) \ 354 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) 355 /* Exception Registers access */ 356 #define DAR_sig(context) REG_sig(dar, context) 357 #define DSISR_sig(context) REG_sig(dsisr, context) 358 #define TRAP_sig(context) REG_sig(trap, context) 359 #endif /* linux */ 360 361 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 362 #include <ucontext.h> 363 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) 364 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) 365 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) 366 #define XER_sig(context) ((context)->uc_mcontext.mc_xer) 367 #define LR_sig(context) ((context)->uc_mcontext.mc_lr) 368 #define CR_sig(context) ((context)->uc_mcontext.mc_cr) 369 /* Exception Registers access */ 370 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar) 371 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) 372 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) 373 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */ 374 375 int cpu_signal_handler(int host_signum, void *pinfo, 376 void *puc) 377 { 378 siginfo_t *info = pinfo; 379 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 380 ucontext_t *uc = puc; 381 #else 382 ucontext_t *uc = puc; 383 #endif 384 unsigned long pc; 385 int is_write; 386 387 pc = IAR_sig(uc); 388 is_write = 0; 389 #if 0 390 /* ppc 4xx case */ 391 if (DSISR_sig(uc) & 0x00800000) { 392 is_write = 1; 393 } 394 #else 395 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { 396 is_write = 1; 397 } 398 #endif 399 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 400 } 401 402 #elif defined(__alpha__) 403 404 int cpu_signal_handler(int host_signum, void *pinfo, 405 void *puc) 406 { 407 siginfo_t *info = pinfo; 408 ucontext_t *uc = puc; 409 uint32_t *pc = uc->uc_mcontext.sc_pc; 410 uint32_t insn = *pc; 411 int is_write = 0; 412 413 /* XXX: need kernel patch to get write flag faster */ 414 switch (insn >> 26) { 415 case 0x0d: /* stw */ 416 case 0x0e: /* stb */ 417 case 0x0f: /* stq_u */ 418 case 0x24: /* stf */ 419 case 0x25: /* stg */ 420 case 0x26: /* sts */ 421 case 0x27: /* stt */ 422 case 0x2c: /* stl */ 423 case 0x2d: /* stq */ 424 case 0x2e: /* stl_c */ 425 case 0x2f: /* stq_c */ 426 is_write = 1; 427 } 428 429 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 430 } 431 #elif defined(__sparc__) 432 433 int cpu_signal_handler(int host_signum, void *pinfo, 434 void *puc) 435 { 436 siginfo_t *info = pinfo; 437 int is_write; 438 uint32_t insn; 439 #if !defined(__arch64__) || defined(CONFIG_SOLARIS) 440 uint32_t *regs = (uint32_t *)(info + 1); 441 void *sigmask = (regs + 20); 442 /* XXX: is there a standard glibc define ? */ 443 unsigned long pc = regs[1]; 444 #else 445 #ifdef __linux__ 446 struct sigcontext *sc = puc; 447 unsigned long pc = sc->sigc_regs.tpc; 448 void *sigmask = (void *)sc->sigc_mask; 449 #elif defined(__OpenBSD__) 450 struct sigcontext *uc = puc; 451 unsigned long pc = uc->sc_pc; 452 void *sigmask = (void *)(long)uc->sc_mask; 453 #elif defined(__NetBSD__) 454 ucontext_t *uc = puc; 455 unsigned long pc = _UC_MACHINE_PC(uc); 456 void *sigmask = (void *)&uc->uc_sigmask; 457 #endif 458 #endif 459 460 /* XXX: need kernel patch to get write flag faster */ 461 is_write = 0; 462 insn = *(uint32_t *)pc; 463 if ((insn >> 30) == 3) { 464 switch ((insn >> 19) & 0x3f) { 465 case 0x05: /* stb */ 466 case 0x15: /* stba */ 467 case 0x06: /* sth */ 468 case 0x16: /* stha */ 469 case 0x04: /* st */ 470 case 0x14: /* sta */ 471 case 0x07: /* std */ 472 case 0x17: /* stda */ 473 case 0x0e: /* stx */ 474 case 0x1e: /* stxa */ 475 case 0x24: /* stf */ 476 case 0x34: /* stfa */ 477 case 0x27: /* stdf */ 478 case 0x37: /* stdfa */ 479 case 0x26: /* stqf */ 480 case 0x36: /* stqfa */ 481 case 0x25: /* stfsr */ 482 case 0x3c: /* casa */ 483 case 0x3e: /* casxa */ 484 is_write = 1; 485 break; 486 } 487 } 488 return handle_cpu_signal(pc, info, is_write, sigmask); 489 } 490 491 #elif defined(__arm__) 492 493 #if defined(__NetBSD__) 494 #include <ucontext.h> 495 #endif 496 497 int cpu_signal_handler(int host_signum, void *pinfo, 498 void *puc) 499 { 500 siginfo_t *info = pinfo; 501 #if defined(__NetBSD__) 502 ucontext_t *uc = puc; 503 #else 504 ucontext_t *uc = puc; 505 #endif 506 unsigned long pc; 507 int is_write; 508 509 #if defined(__NetBSD__) 510 pc = uc->uc_mcontext.__gregs[_REG_R15]; 511 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) 512 pc = uc->uc_mcontext.gregs[R15]; 513 #else 514 pc = uc->uc_mcontext.arm_pc; 515 #endif 516 517 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or 518 * later processor; on v5 we will always report this as a read). 519 */ 520 is_write = extract32(uc->uc_mcontext.error_code, 11, 1); 521 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 522 } 523 524 #elif defined(__aarch64__) 525 526 #ifndef ESR_MAGIC 527 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ 528 #define ESR_MAGIC 0x45535201 529 struct esr_context { 530 struct _aarch64_ctx head; 531 uint64_t esr; 532 }; 533 #endif 534 535 static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) 536 { 537 return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; 538 } 539 540 static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) 541 { 542 return (struct _aarch64_ctx *)((char *)hdr + hdr->size); 543 } 544 545 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) 546 { 547 siginfo_t *info = pinfo; 548 ucontext_t *uc = puc; 549 uintptr_t pc = uc->uc_mcontext.pc; 550 bool is_write; 551 struct _aarch64_ctx *hdr; 552 struct esr_context const *esrctx = NULL; 553 554 /* Find the esr_context, which has the WnR bit in it */ 555 for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { 556 if (hdr->magic == ESR_MAGIC) { 557 esrctx = (struct esr_context const *)hdr; 558 break; 559 } 560 } 561 562 if (esrctx) { 563 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ 564 uint64_t esr = esrctx->esr; 565 is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; 566 } else { 567 /* 568 * Fall back to parsing instructions; will only be needed 569 * for really ancient (pre-3.16) kernels. 570 */ 571 uint32_t insn = *(uint32_t *)pc; 572 573 is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ 574 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ 575 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ 576 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ 577 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ 578 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ 579 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ 580 /* Ignore bits 10, 11 & 21, controlling indexing. */ 581 || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ 582 || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ 583 /* Ignore bits 23 & 24, controlling indexing. */ 584 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ 585 } 586 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 587 } 588 589 #elif defined(__s390__) 590 591 int cpu_signal_handler(int host_signum, void *pinfo, 592 void *puc) 593 { 594 siginfo_t *info = pinfo; 595 ucontext_t *uc = puc; 596 unsigned long pc; 597 uint16_t *pinsn; 598 int is_write = 0; 599 600 pc = uc->uc_mcontext.psw.addr; 601 602 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead 603 of the normal 2 arguments. The 3rd argument contains the "int_code" 604 from the hardware which does in fact contain the is_write value. 605 The rt signal handler, as far as I can tell, does not give this value 606 at all. Not that we could get to it from here even if it were. */ 607 /* ??? This is not even close to complete, since it ignores all 608 of the read-modify-write instructions. */ 609 pinsn = (uint16_t *)pc; 610 switch (pinsn[0] >> 8) { 611 case 0x50: /* ST */ 612 case 0x42: /* STC */ 613 case 0x40: /* STH */ 614 is_write = 1; 615 break; 616 case 0xc4: /* RIL format insns */ 617 switch (pinsn[0] & 0xf) { 618 case 0xf: /* STRL */ 619 case 0xb: /* STGRL */ 620 case 0x7: /* STHRL */ 621 is_write = 1; 622 } 623 break; 624 case 0xe3: /* RXY format insns */ 625 switch (pinsn[2] & 0xff) { 626 case 0x50: /* STY */ 627 case 0x24: /* STG */ 628 case 0x72: /* STCY */ 629 case 0x70: /* STHY */ 630 case 0x8e: /* STPQ */ 631 case 0x3f: /* STRVH */ 632 case 0x3e: /* STRV */ 633 case 0x2f: /* STRVG */ 634 is_write = 1; 635 } 636 break; 637 } 638 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 639 } 640 641 #elif defined(__mips__) 642 643 int cpu_signal_handler(int host_signum, void *pinfo, 644 void *puc) 645 { 646 siginfo_t *info = pinfo; 647 ucontext_t *uc = puc; 648 greg_t pc = uc->uc_mcontext.pc; 649 int is_write; 650 651 /* XXX: compute is_write */ 652 is_write = 0; 653 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 654 } 655 656 #elif defined(__riscv) 657 658 int cpu_signal_handler(int host_signum, void *pinfo, 659 void *puc) 660 { 661 siginfo_t *info = pinfo; 662 ucontext_t *uc = puc; 663 greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; 664 uint32_t insn = *(uint32_t *)pc; 665 int is_write = 0; 666 667 /* Detect store by reading the instruction at the program 668 counter. Note: we currently only generate 32-bit 669 instructions so we thus only detect 32-bit stores */ 670 switch (((insn >> 0) & 0b11)) { 671 case 3: 672 switch (((insn >> 2) & 0b11111)) { 673 case 8: 674 switch (((insn >> 12) & 0b111)) { 675 case 0: /* sb */ 676 case 1: /* sh */ 677 case 2: /* sw */ 678 case 3: /* sd */ 679 case 4: /* sq */ 680 is_write = 1; 681 break; 682 default: 683 break; 684 } 685 break; 686 case 9: 687 switch (((insn >> 12) & 0b111)) { 688 case 2: /* fsw */ 689 case 3: /* fsd */ 690 case 4: /* fsq */ 691 is_write = 1; 692 break; 693 default: 694 break; 695 } 696 break; 697 default: 698 break; 699 } 700 } 701 702 /* Check for compressed instructions */ 703 switch (((insn >> 13) & 0b111)) { 704 case 7: 705 switch (insn & 0b11) { 706 case 0: /*c.sd */ 707 case 2: /* c.sdsp */ 708 is_write = 1; 709 break; 710 default: 711 break; 712 } 713 break; 714 case 6: 715 switch (insn & 0b11) { 716 case 0: /* c.sw */ 717 case 3: /* c.swsp */ 718 is_write = 1; 719 break; 720 default: 721 break; 722 } 723 break; 724 default: 725 break; 726 } 727 728 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 729 } 730 731 #else 732 733 #error host CPU specific signal handler needed 734 735 #endif 736 737 /* The softmmu versions of these helpers are in cputlb.c. */ 738 739 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) 740 { 741 uint32_t ret; 742 uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, false); 743 744 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 745 ret = ldub_p(g2h(ptr)); 746 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 747 return ret; 748 } 749 750 int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) 751 { 752 int ret; 753 uint16_t meminfo = trace_mem_get_info(MO_SB, MMU_USER_IDX, false); 754 755 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 756 ret = ldsb_p(g2h(ptr)); 757 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 758 return ret; 759 } 760 761 uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr) 762 { 763 uint32_t ret; 764 uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, false); 765 766 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 767 ret = lduw_p(g2h(ptr)); 768 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 769 return ret; 770 } 771 772 int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr) 773 { 774 int ret; 775 uint16_t meminfo = trace_mem_get_info(MO_TESW, MMU_USER_IDX, false); 776 777 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 778 ret = ldsw_p(g2h(ptr)); 779 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 780 return ret; 781 } 782 783 uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr) 784 { 785 uint32_t ret; 786 uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, false); 787 788 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 789 ret = ldl_p(g2h(ptr)); 790 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 791 return ret; 792 } 793 794 uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr) 795 { 796 uint64_t ret; 797 uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, false); 798 799 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 800 ret = ldq_p(g2h(ptr)); 801 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 802 return ret; 803 } 804 805 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 806 { 807 uint32_t ret; 808 809 set_helper_retaddr(retaddr); 810 ret = cpu_ldub_data(env, ptr); 811 clear_helper_retaddr(); 812 return ret; 813 } 814 815 int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 816 { 817 int ret; 818 819 set_helper_retaddr(retaddr); 820 ret = cpu_ldsb_data(env, ptr); 821 clear_helper_retaddr(); 822 return ret; 823 } 824 825 uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 826 { 827 uint32_t ret; 828 829 set_helper_retaddr(retaddr); 830 ret = cpu_lduw_data(env, ptr); 831 clear_helper_retaddr(); 832 return ret; 833 } 834 835 int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 836 { 837 int ret; 838 839 set_helper_retaddr(retaddr); 840 ret = cpu_ldsw_data(env, ptr); 841 clear_helper_retaddr(); 842 return ret; 843 } 844 845 uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 846 { 847 uint32_t ret; 848 849 set_helper_retaddr(retaddr); 850 ret = cpu_ldl_data(env, ptr); 851 clear_helper_retaddr(); 852 return ret; 853 } 854 855 uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 856 { 857 uint64_t ret; 858 859 set_helper_retaddr(retaddr); 860 ret = cpu_ldq_data(env, ptr); 861 clear_helper_retaddr(); 862 return ret; 863 } 864 865 void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 866 { 867 uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, true); 868 869 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 870 stb_p(g2h(ptr), val); 871 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 872 } 873 874 void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 875 { 876 uint16_t meminfo = trace_mem_get_info(MO_TEUW, MMU_USER_IDX, true); 877 878 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 879 stw_p(g2h(ptr), val); 880 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 881 } 882 883 void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 884 { 885 uint16_t meminfo = trace_mem_get_info(MO_TEUL, MMU_USER_IDX, true); 886 887 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 888 stl_p(g2h(ptr), val); 889 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 890 } 891 892 void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val) 893 { 894 uint16_t meminfo = trace_mem_get_info(MO_TEQ, MMU_USER_IDX, true); 895 896 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 897 stq_p(g2h(ptr), val); 898 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 899 } 900 901 void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, 902 uint32_t val, uintptr_t retaddr) 903 { 904 set_helper_retaddr(retaddr); 905 cpu_stb_data(env, ptr, val); 906 clear_helper_retaddr(); 907 } 908 909 void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr, 910 uint32_t val, uintptr_t retaddr) 911 { 912 set_helper_retaddr(retaddr); 913 cpu_stw_data(env, ptr, val); 914 clear_helper_retaddr(); 915 } 916 917 void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr, 918 uint32_t val, uintptr_t retaddr) 919 { 920 set_helper_retaddr(retaddr); 921 cpu_stl_data(env, ptr, val); 922 clear_helper_retaddr(); 923 } 924 925 void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr, 926 uint64_t val, uintptr_t retaddr) 927 { 928 set_helper_retaddr(retaddr); 929 cpu_stq_data(env, ptr, val); 930 clear_helper_retaddr(); 931 } 932 933 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) 934 { 935 uint32_t ret; 936 937 set_helper_retaddr(1); 938 ret = ldub_p(g2h(ptr)); 939 clear_helper_retaddr(); 940 return ret; 941 } 942 943 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr ptr) 944 { 945 uint32_t ret; 946 947 set_helper_retaddr(1); 948 ret = lduw_p(g2h(ptr)); 949 clear_helper_retaddr(); 950 return ret; 951 } 952 953 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr ptr) 954 { 955 uint32_t ret; 956 957 set_helper_retaddr(1); 958 ret = ldl_p(g2h(ptr)); 959 clear_helper_retaddr(); 960 return ret; 961 } 962 963 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) 964 { 965 uint64_t ret; 966 967 set_helper_retaddr(1); 968 ret = ldq_p(g2h(ptr)); 969 clear_helper_retaddr(); 970 return ret; 971 } 972 973 /* Do not allow unaligned operations to proceed. Return the host address. */ 974 static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, 975 int size, uintptr_t retaddr) 976 { 977 /* Enforce qemu required alignment. */ 978 if (unlikely(addr & (size - 1))) { 979 cpu_loop_exit_atomic(env_cpu(env), retaddr); 980 } 981 void *ret = g2h(addr); 982 set_helper_retaddr(retaddr); 983 return ret; 984 } 985 986 /* Macro to call the above, with local variables from the use context. */ 987 #define ATOMIC_MMU_DECLS do {} while (0) 988 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC()) 989 #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) 990 #define ATOMIC_MMU_IDX MMU_USER_IDX 991 992 #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) 993 #define EXTRA_ARGS 994 995 #include "atomic_common.inc.c" 996 997 #define DATA_SIZE 1 998 #include "atomic_template.h" 999 1000 #define DATA_SIZE 2 1001 #include "atomic_template.h" 1002 1003 #define DATA_SIZE 4 1004 #include "atomic_template.h" 1005 1006 #ifdef CONFIG_ATOMIC64 1007 #define DATA_SIZE 8 1008 #include "atomic_template.h" 1009 #endif 1010 1011 /* The following is only callable from other helpers, and matches up 1012 with the softmmu version. */ 1013 1014 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128 1015 1016 #undef EXTRA_ARGS 1017 #undef ATOMIC_NAME 1018 #undef ATOMIC_MMU_LOOKUP 1019 1020 #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr 1021 #define ATOMIC_NAME(X) \ 1022 HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) 1023 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr) 1024 1025 #define DATA_SIZE 16 1026 #include "atomic_template.h" 1027 #endif 1028