1 /* 2 * User emulator execution 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "disas/disas.h" 22 #include "exec/exec-all.h" 23 #include "tcg/tcg.h" 24 #include "qemu/bitops.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/translate-all.h" 27 #include "exec/helper-proto.h" 28 #include "qemu/atomic128.h" 29 #include "trace/trace-root.h" 30 #include "trace/mem.h" 31 32 #undef EAX 33 #undef ECX 34 #undef EDX 35 #undef EBX 36 #undef ESP 37 #undef EBP 38 #undef ESI 39 #undef EDI 40 #undef EIP 41 #ifdef __linux__ 42 #include <sys/ucontext.h> 43 #endif 44 45 __thread uintptr_t helper_retaddr; 46 47 //#define DEBUG_SIGNAL 48 49 /* exit the current TB from a signal handler. The host registers are 50 restored in a state compatible with the CPU emulator 51 */ 52 static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, 53 sigset_t *old_set) 54 { 55 /* XXX: use siglongjmp ? */ 56 sigprocmask(SIG_SETMASK, old_set, NULL); 57 cpu_loop_exit_noexc(cpu); 58 } 59 60 /* 'pc' is the host PC at which the exception was raised. 'address' is 61 the effective address of the memory exception. 'is_write' is 1 if a 62 write caused the exception and otherwise 0'. 'old_set' is the 63 signal set which should be restored */ 64 static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, 65 int is_write, sigset_t *old_set) 66 { 67 CPUState *cpu = current_cpu; 68 CPUClass *cc; 69 unsigned long address = (unsigned long)info->si_addr; 70 MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; 71 72 switch (helper_retaddr) { 73 default: 74 /* 75 * Fault during host memory operation within a helper function. 76 * The helper's host return address, saved here, gives us a 77 * pointer into the generated code that will unwind to the 78 * correct guest pc. 79 */ 80 pc = helper_retaddr; 81 break; 82 83 case 0: 84 /* 85 * Fault during host memory operation within generated code. 86 * (Or, a unrelated bug within qemu, but we can't tell from here). 87 * 88 * We take the host pc from the signal frame. However, we cannot 89 * use that value directly. Within cpu_restore_state_from_tb, we 90 * assume PC comes from GETPC(), as used by the helper functions, 91 * so we adjust the address by -GETPC_ADJ to form an address that 92 * is within the call insn, so that the address does not accidentally 93 * match the beginning of the next guest insn. However, when the 94 * pc comes from the signal frame it points to the actual faulting 95 * host memory insn and not the return from a call insn. 96 * 97 * Therefore, adjust to compensate for what will be done later 98 * by cpu_restore_state_from_tb. 99 */ 100 pc += GETPC_ADJ; 101 break; 102 103 case 1: 104 /* 105 * Fault during host read for translation, or loosely, "execution". 106 * 107 * The guest pc is already pointing to the start of the TB for which 108 * code is being generated. If the guest translator manages the 109 * page crossings correctly, this is exactly the correct address 110 * (and if the translator doesn't handle page boundaries correctly 111 * there's little we can do about that here). Therefore, do not 112 * trigger the unwinder. 113 * 114 * Like tb_gen_code, release the memory lock before cpu_loop_exit. 115 */ 116 pc = 0; 117 access_type = MMU_INST_FETCH; 118 mmap_unlock(); 119 break; 120 } 121 122 /* For synchronous signals we expect to be coming from the vCPU 123 * thread (so current_cpu should be valid) and either from running 124 * code or during translation which can fault as we cross pages. 125 * 126 * If neither is true then something has gone wrong and we should 127 * abort rather than try and restart the vCPU execution. 128 */ 129 if (!cpu || !cpu->running) { 130 printf("qemu:%s received signal outside vCPU context @ pc=0x%" 131 PRIxPTR "\n", __func__, pc); 132 abort(); 133 } 134 135 #if defined(DEBUG_SIGNAL) 136 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 137 pc, address, is_write, *(unsigned long *)old_set); 138 #endif 139 /* XXX: locking issue */ 140 /* Note that it is important that we don't call page_unprotect() unless 141 * this is really a "write to nonwriteable page" fault, because 142 * page_unprotect() assumes that if it is called for an access to 143 * a page that's writeable this means we had two threads racing and 144 * another thread got there first and already made the page writeable; 145 * so we will retry the access. If we were to call page_unprotect() 146 * for some other kind of fault that should really be passed to the 147 * guest, we'd end up in an infinite loop of retrying the faulting 148 * access. 149 */ 150 if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR && 151 h2g_valid(address)) { 152 switch (page_unprotect(h2g(address), pc)) { 153 case 0: 154 /* Fault not caused by a page marked unwritable to protect 155 * cached translations, must be the guest binary's problem. 156 */ 157 break; 158 case 1: 159 /* Fault caused by protection of cached translation; TBs 160 * invalidated, so resume execution. Retain helper_retaddr 161 * for a possible second fault. 162 */ 163 return 1; 164 case 2: 165 /* Fault caused by protection of cached translation, and the 166 * currently executing TB was modified and must be exited 167 * immediately. Clear helper_retaddr for next execution. 168 */ 169 clear_helper_retaddr(); 170 cpu_exit_tb_from_sighandler(cpu, old_set); 171 /* NORETURN */ 172 173 default: 174 g_assert_not_reached(); 175 } 176 } 177 178 /* Convert forcefully to guest address space, invalid addresses 179 are still valid segv ones */ 180 address = h2g_nocheck(address); 181 182 /* 183 * There is no way the target can handle this other than raising 184 * an exception. Undo signal and retaddr state prior to longjmp. 185 */ 186 sigprocmask(SIG_SETMASK, old_set, NULL); 187 clear_helper_retaddr(); 188 189 cc = CPU_GET_CLASS(cpu); 190 cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, 191 MMU_USER_IDX, false, pc); 192 g_assert_not_reached(); 193 } 194 195 static int probe_access_internal(CPUArchState *env, target_ulong addr, 196 int fault_size, MMUAccessType access_type, 197 bool nonfault, uintptr_t ra) 198 { 199 int flags; 200 201 switch (access_type) { 202 case MMU_DATA_STORE: 203 flags = PAGE_WRITE; 204 break; 205 case MMU_DATA_LOAD: 206 flags = PAGE_READ; 207 break; 208 case MMU_INST_FETCH: 209 flags = PAGE_EXEC; 210 break; 211 default: 212 g_assert_not_reached(); 213 } 214 215 if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) { 216 if (nonfault) { 217 return TLB_INVALID_MASK; 218 } else { 219 CPUState *cpu = env_cpu(env); 220 CPUClass *cc = CPU_GET_CLASS(cpu); 221 cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type, 222 MMU_USER_IDX, false, ra); 223 g_assert_not_reached(); 224 } 225 } 226 return 0; 227 } 228 229 int probe_access_flags(CPUArchState *env, target_ulong addr, 230 MMUAccessType access_type, int mmu_idx, 231 bool nonfault, void **phost, uintptr_t ra) 232 { 233 int flags; 234 235 flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra); 236 *phost = flags ? NULL : g2h(addr); 237 return flags; 238 } 239 240 void *probe_access(CPUArchState *env, target_ulong addr, int size, 241 MMUAccessType access_type, int mmu_idx, uintptr_t ra) 242 { 243 int flags; 244 245 g_assert(-(addr | TARGET_PAGE_MASK) >= size); 246 flags = probe_access_internal(env, addr, size, access_type, false, ra); 247 g_assert(flags == 0); 248 249 return size ? g2h(addr) : NULL; 250 } 251 252 #if defined(__i386__) 253 254 #if defined(__NetBSD__) 255 #include <ucontext.h> 256 257 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) 258 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 259 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 260 #define MASK_sig(context) ((context)->uc_sigmask) 261 #elif defined(__FreeBSD__) || defined(__DragonFly__) 262 #include <ucontext.h> 263 264 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) 265 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 266 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 267 #define MASK_sig(context) ((context)->uc_sigmask) 268 #elif defined(__OpenBSD__) 269 #define EIP_sig(context) ((context)->sc_eip) 270 #define TRAP_sig(context) ((context)->sc_trapno) 271 #define ERROR_sig(context) ((context)->sc_err) 272 #define MASK_sig(context) ((context)->sc_mask) 273 #else 274 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) 275 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 276 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 277 #define MASK_sig(context) ((context)->uc_sigmask) 278 #endif 279 280 int cpu_signal_handler(int host_signum, void *pinfo, 281 void *puc) 282 { 283 siginfo_t *info = pinfo; 284 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 285 ucontext_t *uc = puc; 286 #elif defined(__OpenBSD__) 287 struct sigcontext *uc = puc; 288 #else 289 ucontext_t *uc = puc; 290 #endif 291 unsigned long pc; 292 int trapno; 293 294 #ifndef REG_EIP 295 /* for glibc 2.1 */ 296 #define REG_EIP EIP 297 #define REG_ERR ERR 298 #define REG_TRAPNO TRAPNO 299 #endif 300 pc = EIP_sig(uc); 301 trapno = TRAP_sig(uc); 302 return handle_cpu_signal(pc, info, 303 trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 304 &MASK_sig(uc)); 305 } 306 307 #elif defined(__x86_64__) 308 309 #ifdef __NetBSD__ 310 #define PC_sig(context) _UC_MACHINE_PC(context) 311 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 312 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 313 #define MASK_sig(context) ((context)->uc_sigmask) 314 #elif defined(__OpenBSD__) 315 #define PC_sig(context) ((context)->sc_rip) 316 #define TRAP_sig(context) ((context)->sc_trapno) 317 #define ERROR_sig(context) ((context)->sc_err) 318 #define MASK_sig(context) ((context)->sc_mask) 319 #elif defined(__FreeBSD__) || defined(__DragonFly__) 320 #include <ucontext.h> 321 322 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) 323 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 324 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 325 #define MASK_sig(context) ((context)->uc_sigmask) 326 #else 327 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) 328 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 329 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 330 #define MASK_sig(context) ((context)->uc_sigmask) 331 #endif 332 333 int cpu_signal_handler(int host_signum, void *pinfo, 334 void *puc) 335 { 336 siginfo_t *info = pinfo; 337 unsigned long pc; 338 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 339 ucontext_t *uc = puc; 340 #elif defined(__OpenBSD__) 341 struct sigcontext *uc = puc; 342 #else 343 ucontext_t *uc = puc; 344 #endif 345 346 pc = PC_sig(uc); 347 return handle_cpu_signal(pc, info, 348 TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 349 &MASK_sig(uc)); 350 } 351 352 #elif defined(_ARCH_PPC) 353 354 /*********************************************************************** 355 * signal context platform-specific definitions 356 * From Wine 357 */ 358 #ifdef linux 359 /* All Registers access - only for local access */ 360 #define REG_sig(reg_name, context) \ 361 ((context)->uc_mcontext.regs->reg_name) 362 /* Gpr Registers access */ 363 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) 364 /* Program counter */ 365 #define IAR_sig(context) REG_sig(nip, context) 366 /* Machine State Register (Supervisor) */ 367 #define MSR_sig(context) REG_sig(msr, context) 368 /* Count register */ 369 #define CTR_sig(context) REG_sig(ctr, context) 370 /* User's integer exception register */ 371 #define XER_sig(context) REG_sig(xer, context) 372 /* Link register */ 373 #define LR_sig(context) REG_sig(link, context) 374 /* Condition register */ 375 #define CR_sig(context) REG_sig(ccr, context) 376 377 /* Float Registers access */ 378 #define FLOAT_sig(reg_num, context) \ 379 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) 380 #define FPSCR_sig(context) \ 381 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) 382 /* Exception Registers access */ 383 #define DAR_sig(context) REG_sig(dar, context) 384 #define DSISR_sig(context) REG_sig(dsisr, context) 385 #define TRAP_sig(context) REG_sig(trap, context) 386 #endif /* linux */ 387 388 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 389 #include <ucontext.h> 390 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) 391 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) 392 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) 393 #define XER_sig(context) ((context)->uc_mcontext.mc_xer) 394 #define LR_sig(context) ((context)->uc_mcontext.mc_lr) 395 #define CR_sig(context) ((context)->uc_mcontext.mc_cr) 396 /* Exception Registers access */ 397 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar) 398 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) 399 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) 400 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */ 401 402 int cpu_signal_handler(int host_signum, void *pinfo, 403 void *puc) 404 { 405 siginfo_t *info = pinfo; 406 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 407 ucontext_t *uc = puc; 408 #else 409 ucontext_t *uc = puc; 410 #endif 411 unsigned long pc; 412 int is_write; 413 414 pc = IAR_sig(uc); 415 is_write = 0; 416 #if 0 417 /* ppc 4xx case */ 418 if (DSISR_sig(uc) & 0x00800000) { 419 is_write = 1; 420 } 421 #else 422 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { 423 is_write = 1; 424 } 425 #endif 426 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 427 } 428 429 #elif defined(__alpha__) 430 431 int cpu_signal_handler(int host_signum, void *pinfo, 432 void *puc) 433 { 434 siginfo_t *info = pinfo; 435 ucontext_t *uc = puc; 436 uint32_t *pc = uc->uc_mcontext.sc_pc; 437 uint32_t insn = *pc; 438 int is_write = 0; 439 440 /* XXX: need kernel patch to get write flag faster */ 441 switch (insn >> 26) { 442 case 0x0d: /* stw */ 443 case 0x0e: /* stb */ 444 case 0x0f: /* stq_u */ 445 case 0x24: /* stf */ 446 case 0x25: /* stg */ 447 case 0x26: /* sts */ 448 case 0x27: /* stt */ 449 case 0x2c: /* stl */ 450 case 0x2d: /* stq */ 451 case 0x2e: /* stl_c */ 452 case 0x2f: /* stq_c */ 453 is_write = 1; 454 } 455 456 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 457 } 458 #elif defined(__sparc__) 459 460 int cpu_signal_handler(int host_signum, void *pinfo, 461 void *puc) 462 { 463 siginfo_t *info = pinfo; 464 int is_write; 465 uint32_t insn; 466 #if !defined(__arch64__) || defined(CONFIG_SOLARIS) 467 uint32_t *regs = (uint32_t *)(info + 1); 468 void *sigmask = (regs + 20); 469 /* XXX: is there a standard glibc define ? */ 470 unsigned long pc = regs[1]; 471 #else 472 #ifdef __linux__ 473 struct sigcontext *sc = puc; 474 unsigned long pc = sc->sigc_regs.tpc; 475 void *sigmask = (void *)sc->sigc_mask; 476 #elif defined(__OpenBSD__) 477 struct sigcontext *uc = puc; 478 unsigned long pc = uc->sc_pc; 479 void *sigmask = (void *)(long)uc->sc_mask; 480 #elif defined(__NetBSD__) 481 ucontext_t *uc = puc; 482 unsigned long pc = _UC_MACHINE_PC(uc); 483 void *sigmask = (void *)&uc->uc_sigmask; 484 #endif 485 #endif 486 487 /* XXX: need kernel patch to get write flag faster */ 488 is_write = 0; 489 insn = *(uint32_t *)pc; 490 if ((insn >> 30) == 3) { 491 switch ((insn >> 19) & 0x3f) { 492 case 0x05: /* stb */ 493 case 0x15: /* stba */ 494 case 0x06: /* sth */ 495 case 0x16: /* stha */ 496 case 0x04: /* st */ 497 case 0x14: /* sta */ 498 case 0x07: /* std */ 499 case 0x17: /* stda */ 500 case 0x0e: /* stx */ 501 case 0x1e: /* stxa */ 502 case 0x24: /* stf */ 503 case 0x34: /* stfa */ 504 case 0x27: /* stdf */ 505 case 0x37: /* stdfa */ 506 case 0x26: /* stqf */ 507 case 0x36: /* stqfa */ 508 case 0x25: /* stfsr */ 509 case 0x3c: /* casa */ 510 case 0x3e: /* casxa */ 511 is_write = 1; 512 break; 513 } 514 } 515 return handle_cpu_signal(pc, info, is_write, sigmask); 516 } 517 518 #elif defined(__arm__) 519 520 #if defined(__NetBSD__) 521 #include <ucontext.h> 522 #include <sys/siginfo.h> 523 #endif 524 525 int cpu_signal_handler(int host_signum, void *pinfo, 526 void *puc) 527 { 528 siginfo_t *info = pinfo; 529 #if defined(__NetBSD__) 530 ucontext_t *uc = puc; 531 siginfo_t *si = pinfo; 532 #else 533 ucontext_t *uc = puc; 534 #endif 535 unsigned long pc; 536 uint32_t fsr; 537 int is_write; 538 539 #if defined(__NetBSD__) 540 pc = uc->uc_mcontext.__gregs[_REG_R15]; 541 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) 542 pc = uc->uc_mcontext.gregs[R15]; 543 #else 544 pc = uc->uc_mcontext.arm_pc; 545 #endif 546 547 #ifdef __NetBSD__ 548 fsr = si->si_trap; 549 #else 550 fsr = uc->uc_mcontext.error_code; 551 #endif 552 /* 553 * In the FSR, bit 11 is WnR, assuming a v6 or 554 * later processor. On v5 we will always report 555 * this as a read, which will fail later. 556 */ 557 is_write = extract32(fsr, 11, 1); 558 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 559 } 560 561 #elif defined(__aarch64__) 562 563 #if defined(__NetBSD__) 564 565 #include <ucontext.h> 566 #include <sys/siginfo.h> 567 568 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) 569 { 570 ucontext_t *uc = puc; 571 siginfo_t *si = pinfo; 572 unsigned long pc; 573 int is_write; 574 uint32_t esr; 575 576 pc = uc->uc_mcontext.__gregs[_REG_PC]; 577 esr = si->si_trap; 578 579 /* 580 * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC 581 * is 0b10010x: then bit 6 is the WnR bit 582 */ 583 is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; 584 return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); 585 } 586 587 #else 588 589 #ifndef ESR_MAGIC 590 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ 591 #define ESR_MAGIC 0x45535201 592 struct esr_context { 593 struct _aarch64_ctx head; 594 uint64_t esr; 595 }; 596 #endif 597 598 static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) 599 { 600 return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; 601 } 602 603 static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) 604 { 605 return (struct _aarch64_ctx *)((char *)hdr + hdr->size); 606 } 607 608 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) 609 { 610 siginfo_t *info = pinfo; 611 ucontext_t *uc = puc; 612 uintptr_t pc = uc->uc_mcontext.pc; 613 bool is_write; 614 struct _aarch64_ctx *hdr; 615 struct esr_context const *esrctx = NULL; 616 617 /* Find the esr_context, which has the WnR bit in it */ 618 for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { 619 if (hdr->magic == ESR_MAGIC) { 620 esrctx = (struct esr_context const *)hdr; 621 break; 622 } 623 } 624 625 if (esrctx) { 626 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ 627 uint64_t esr = esrctx->esr; 628 is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; 629 } else { 630 /* 631 * Fall back to parsing instructions; will only be needed 632 * for really ancient (pre-3.16) kernels. 633 */ 634 uint32_t insn = *(uint32_t *)pc; 635 636 is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ 637 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ 638 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ 639 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ 640 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ 641 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ 642 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ 643 /* Ignore bits 10, 11 & 21, controlling indexing. */ 644 || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ 645 || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ 646 /* Ignore bits 23 & 24, controlling indexing. */ 647 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ 648 } 649 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 650 } 651 #endif 652 653 #elif defined(__s390__) 654 655 int cpu_signal_handler(int host_signum, void *pinfo, 656 void *puc) 657 { 658 siginfo_t *info = pinfo; 659 ucontext_t *uc = puc; 660 unsigned long pc; 661 uint16_t *pinsn; 662 int is_write = 0; 663 664 pc = uc->uc_mcontext.psw.addr; 665 666 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead 667 of the normal 2 arguments. The 3rd argument contains the "int_code" 668 from the hardware which does in fact contain the is_write value. 669 The rt signal handler, as far as I can tell, does not give this value 670 at all. Not that we could get to it from here even if it were. */ 671 /* ??? This is not even close to complete, since it ignores all 672 of the read-modify-write instructions. */ 673 pinsn = (uint16_t *)pc; 674 switch (pinsn[0] >> 8) { 675 case 0x50: /* ST */ 676 case 0x42: /* STC */ 677 case 0x40: /* STH */ 678 is_write = 1; 679 break; 680 case 0xc4: /* RIL format insns */ 681 switch (pinsn[0] & 0xf) { 682 case 0xf: /* STRL */ 683 case 0xb: /* STGRL */ 684 case 0x7: /* STHRL */ 685 is_write = 1; 686 } 687 break; 688 case 0xe3: /* RXY format insns */ 689 switch (pinsn[2] & 0xff) { 690 case 0x50: /* STY */ 691 case 0x24: /* STG */ 692 case 0x72: /* STCY */ 693 case 0x70: /* STHY */ 694 case 0x8e: /* STPQ */ 695 case 0x3f: /* STRVH */ 696 case 0x3e: /* STRV */ 697 case 0x2f: /* STRVG */ 698 is_write = 1; 699 } 700 break; 701 } 702 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 703 } 704 705 #elif defined(__mips__) 706 707 #if defined(__misp16) || defined(__mips_micromips) 708 #error "Unsupported encoding" 709 #endif 710 711 int cpu_signal_handler(int host_signum, void *pinfo, 712 void *puc) 713 { 714 siginfo_t *info = pinfo; 715 ucontext_t *uc = puc; 716 uintptr_t pc = uc->uc_mcontext.pc; 717 uint32_t insn = *(uint32_t *)pc; 718 int is_write = 0; 719 720 /* Detect all store instructions at program counter. */ 721 switch((insn >> 26) & 077) { 722 case 050: /* SB */ 723 case 051: /* SH */ 724 case 052: /* SWL */ 725 case 053: /* SW */ 726 case 054: /* SDL */ 727 case 055: /* SDR */ 728 case 056: /* SWR */ 729 case 070: /* SC */ 730 case 071: /* SWC1 */ 731 case 074: /* SCD */ 732 case 075: /* SDC1 */ 733 case 077: /* SD */ 734 #if !defined(__mips_isa_rev) || __mips_isa_rev < 6 735 case 072: /* SWC2 */ 736 case 076: /* SDC2 */ 737 #endif 738 is_write = 1; 739 break; 740 case 023: /* COP1X */ 741 /* Required in all versions of MIPS64 since 742 MIPS64r1 and subsequent versions of MIPS32r2. */ 743 switch (insn & 077) { 744 case 010: /* SWXC1 */ 745 case 011: /* SDXC1 */ 746 case 015: /* SUXC1 */ 747 is_write = 1; 748 } 749 break; 750 } 751 752 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 753 } 754 755 #elif defined(__riscv) 756 757 int cpu_signal_handler(int host_signum, void *pinfo, 758 void *puc) 759 { 760 siginfo_t *info = pinfo; 761 ucontext_t *uc = puc; 762 greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; 763 uint32_t insn = *(uint32_t *)pc; 764 int is_write = 0; 765 766 /* Detect store by reading the instruction at the program 767 counter. Note: we currently only generate 32-bit 768 instructions so we thus only detect 32-bit stores */ 769 switch (((insn >> 0) & 0b11)) { 770 case 3: 771 switch (((insn >> 2) & 0b11111)) { 772 case 8: 773 switch (((insn >> 12) & 0b111)) { 774 case 0: /* sb */ 775 case 1: /* sh */ 776 case 2: /* sw */ 777 case 3: /* sd */ 778 case 4: /* sq */ 779 is_write = 1; 780 break; 781 default: 782 break; 783 } 784 break; 785 case 9: 786 switch (((insn >> 12) & 0b111)) { 787 case 2: /* fsw */ 788 case 3: /* fsd */ 789 case 4: /* fsq */ 790 is_write = 1; 791 break; 792 default: 793 break; 794 } 795 break; 796 default: 797 break; 798 } 799 } 800 801 /* Check for compressed instructions */ 802 switch (((insn >> 13) & 0b111)) { 803 case 7: 804 switch (insn & 0b11) { 805 case 0: /*c.sd */ 806 case 2: /* c.sdsp */ 807 is_write = 1; 808 break; 809 default: 810 break; 811 } 812 break; 813 case 6: 814 switch (insn & 0b11) { 815 case 0: /* c.sw */ 816 case 3: /* c.swsp */ 817 is_write = 1; 818 break; 819 default: 820 break; 821 } 822 break; 823 default: 824 break; 825 } 826 827 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 828 } 829 830 #else 831 832 #error host CPU specific signal handler needed 833 834 #endif 835 836 /* The softmmu versions of these helpers are in cputlb.c. */ 837 838 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) 839 { 840 uint32_t ret; 841 uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, false); 842 843 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 844 ret = ldub_p(g2h(ptr)); 845 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 846 return ret; 847 } 848 849 int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) 850 { 851 int ret; 852 uint16_t meminfo = trace_mem_get_info(MO_SB, MMU_USER_IDX, false); 853 854 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 855 ret = ldsb_p(g2h(ptr)); 856 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 857 return ret; 858 } 859 860 uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr) 861 { 862 uint32_t ret; 863 uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false); 864 865 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 866 ret = lduw_be_p(g2h(ptr)); 867 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 868 return ret; 869 } 870 871 int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) 872 { 873 int ret; 874 uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false); 875 876 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 877 ret = ldsw_be_p(g2h(ptr)); 878 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 879 return ret; 880 } 881 882 uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) 883 { 884 uint32_t ret; 885 uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false); 886 887 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 888 ret = ldl_be_p(g2h(ptr)); 889 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 890 return ret; 891 } 892 893 uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) 894 { 895 uint64_t ret; 896 uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false); 897 898 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 899 ret = ldq_be_p(g2h(ptr)); 900 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 901 return ret; 902 } 903 904 uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr) 905 { 906 uint32_t ret; 907 uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false); 908 909 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 910 ret = lduw_le_p(g2h(ptr)); 911 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 912 return ret; 913 } 914 915 int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) 916 { 917 int ret; 918 uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false); 919 920 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 921 ret = ldsw_le_p(g2h(ptr)); 922 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 923 return ret; 924 } 925 926 uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) 927 { 928 uint32_t ret; 929 uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false); 930 931 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 932 ret = ldl_le_p(g2h(ptr)); 933 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 934 return ret; 935 } 936 937 uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) 938 { 939 uint64_t ret; 940 uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false); 941 942 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 943 ret = ldq_le_p(g2h(ptr)); 944 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 945 return ret; 946 } 947 948 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 949 { 950 uint32_t ret; 951 952 set_helper_retaddr(retaddr); 953 ret = cpu_ldub_data(env, ptr); 954 clear_helper_retaddr(); 955 return ret; 956 } 957 958 int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 959 { 960 int ret; 961 962 set_helper_retaddr(retaddr); 963 ret = cpu_ldsb_data(env, ptr); 964 clear_helper_retaddr(); 965 return ret; 966 } 967 968 uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 969 { 970 uint32_t ret; 971 972 set_helper_retaddr(retaddr); 973 ret = cpu_lduw_be_data(env, ptr); 974 clear_helper_retaddr(); 975 return ret; 976 } 977 978 int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 979 { 980 int ret; 981 982 set_helper_retaddr(retaddr); 983 ret = cpu_ldsw_be_data(env, ptr); 984 clear_helper_retaddr(); 985 return ret; 986 } 987 988 uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 989 { 990 uint32_t ret; 991 992 set_helper_retaddr(retaddr); 993 ret = cpu_ldl_be_data(env, ptr); 994 clear_helper_retaddr(); 995 return ret; 996 } 997 998 uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 999 { 1000 uint64_t ret; 1001 1002 set_helper_retaddr(retaddr); 1003 ret = cpu_ldq_be_data(env, ptr); 1004 clear_helper_retaddr(); 1005 return ret; 1006 } 1007 1008 uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1009 { 1010 uint32_t ret; 1011 1012 set_helper_retaddr(retaddr); 1013 ret = cpu_lduw_le_data(env, ptr); 1014 clear_helper_retaddr(); 1015 return ret; 1016 } 1017 1018 int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1019 { 1020 int ret; 1021 1022 set_helper_retaddr(retaddr); 1023 ret = cpu_ldsw_le_data(env, ptr); 1024 clear_helper_retaddr(); 1025 return ret; 1026 } 1027 1028 uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1029 { 1030 uint32_t ret; 1031 1032 set_helper_retaddr(retaddr); 1033 ret = cpu_ldl_le_data(env, ptr); 1034 clear_helper_retaddr(); 1035 return ret; 1036 } 1037 1038 uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1039 { 1040 uint64_t ret; 1041 1042 set_helper_retaddr(retaddr); 1043 ret = cpu_ldq_le_data(env, ptr); 1044 clear_helper_retaddr(); 1045 return ret; 1046 } 1047 1048 void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1049 { 1050 uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, true); 1051 1052 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1053 stb_p(g2h(ptr), val); 1054 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1055 } 1056 1057 void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1058 { 1059 uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true); 1060 1061 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1062 stw_be_p(g2h(ptr), val); 1063 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1064 } 1065 1066 void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1067 { 1068 uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true); 1069 1070 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1071 stl_be_p(g2h(ptr), val); 1072 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1073 } 1074 1075 void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val) 1076 { 1077 uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true); 1078 1079 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1080 stq_be_p(g2h(ptr), val); 1081 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1082 } 1083 1084 void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1085 { 1086 uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true); 1087 1088 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1089 stw_le_p(g2h(ptr), val); 1090 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1091 } 1092 1093 void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1094 { 1095 uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true); 1096 1097 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1098 stl_le_p(g2h(ptr), val); 1099 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1100 } 1101 1102 void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val) 1103 { 1104 uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true); 1105 1106 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1107 stq_le_p(g2h(ptr), val); 1108 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1109 } 1110 1111 void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, 1112 uint32_t val, uintptr_t retaddr) 1113 { 1114 set_helper_retaddr(retaddr); 1115 cpu_stb_data(env, ptr, val); 1116 clear_helper_retaddr(); 1117 } 1118 1119 void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr, 1120 uint32_t val, uintptr_t retaddr) 1121 { 1122 set_helper_retaddr(retaddr); 1123 cpu_stw_be_data(env, ptr, val); 1124 clear_helper_retaddr(); 1125 } 1126 1127 void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr, 1128 uint32_t val, uintptr_t retaddr) 1129 { 1130 set_helper_retaddr(retaddr); 1131 cpu_stl_be_data(env, ptr, val); 1132 clear_helper_retaddr(); 1133 } 1134 1135 void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr, 1136 uint64_t val, uintptr_t retaddr) 1137 { 1138 set_helper_retaddr(retaddr); 1139 cpu_stq_be_data(env, ptr, val); 1140 clear_helper_retaddr(); 1141 } 1142 1143 void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr, 1144 uint32_t val, uintptr_t retaddr) 1145 { 1146 set_helper_retaddr(retaddr); 1147 cpu_stw_le_data(env, ptr, val); 1148 clear_helper_retaddr(); 1149 } 1150 1151 void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, 1152 uint32_t val, uintptr_t retaddr) 1153 { 1154 set_helper_retaddr(retaddr); 1155 cpu_stl_le_data(env, ptr, val); 1156 clear_helper_retaddr(); 1157 } 1158 1159 void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, 1160 uint64_t val, uintptr_t retaddr) 1161 { 1162 set_helper_retaddr(retaddr); 1163 cpu_stq_le_data(env, ptr, val); 1164 clear_helper_retaddr(); 1165 } 1166 1167 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) 1168 { 1169 uint32_t ret; 1170 1171 set_helper_retaddr(1); 1172 ret = ldub_p(g2h(ptr)); 1173 clear_helper_retaddr(); 1174 return ret; 1175 } 1176 1177 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr ptr) 1178 { 1179 uint32_t ret; 1180 1181 set_helper_retaddr(1); 1182 ret = lduw_p(g2h(ptr)); 1183 clear_helper_retaddr(); 1184 return ret; 1185 } 1186 1187 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr ptr) 1188 { 1189 uint32_t ret; 1190 1191 set_helper_retaddr(1); 1192 ret = ldl_p(g2h(ptr)); 1193 clear_helper_retaddr(); 1194 return ret; 1195 } 1196 1197 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) 1198 { 1199 uint64_t ret; 1200 1201 set_helper_retaddr(1); 1202 ret = ldq_p(g2h(ptr)); 1203 clear_helper_retaddr(); 1204 return ret; 1205 } 1206 1207 /* Do not allow unaligned operations to proceed. Return the host address. */ 1208 static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, 1209 int size, uintptr_t retaddr) 1210 { 1211 /* Enforce qemu required alignment. */ 1212 if (unlikely(addr & (size - 1))) { 1213 cpu_loop_exit_atomic(env_cpu(env), retaddr); 1214 } 1215 void *ret = g2h(addr); 1216 set_helper_retaddr(retaddr); 1217 return ret; 1218 } 1219 1220 /* Macro to call the above, with local variables from the use context. */ 1221 #define ATOMIC_MMU_DECLS do {} while (0) 1222 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC()) 1223 #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) 1224 #define ATOMIC_MMU_IDX MMU_USER_IDX 1225 1226 #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) 1227 #define EXTRA_ARGS 1228 1229 #include "atomic_common.c.inc" 1230 1231 #define DATA_SIZE 1 1232 #include "atomic_template.h" 1233 1234 #define DATA_SIZE 2 1235 #include "atomic_template.h" 1236 1237 #define DATA_SIZE 4 1238 #include "atomic_template.h" 1239 1240 #ifdef CONFIG_ATOMIC64 1241 #define DATA_SIZE 8 1242 #include "atomic_template.h" 1243 #endif 1244 1245 /* The following is only callable from other helpers, and matches up 1246 with the softmmu version. */ 1247 1248 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128 1249 1250 #undef EXTRA_ARGS 1251 #undef ATOMIC_NAME 1252 #undef ATOMIC_MMU_LOOKUP 1253 1254 #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr 1255 #define ATOMIC_NAME(X) \ 1256 HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) 1257 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr) 1258 1259 #define DATA_SIZE 16 1260 #include "atomic_template.h" 1261 #endif 1262