1 /* 2 * User emulator execution 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "disas/disas.h" 22 #include "exec/exec-all.h" 23 #include "tcg.h" 24 #include "qemu/bitops.h" 25 #include "exec/cpu_ldst.h" 26 #include "translate-all.h" 27 #include "exec/helper-proto.h" 28 #include "qemu/atomic128.h" 29 30 #undef EAX 31 #undef ECX 32 #undef EDX 33 #undef EBX 34 #undef ESP 35 #undef EBP 36 #undef ESI 37 #undef EDI 38 #undef EIP 39 #ifdef __linux__ 40 #include <sys/ucontext.h> 41 #endif 42 43 __thread uintptr_t helper_retaddr; 44 45 //#define DEBUG_SIGNAL 46 47 /* exit the current TB from a signal handler. The host registers are 48 restored in a state compatible with the CPU emulator 49 */ 50 static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set) 51 { 52 /* XXX: use siglongjmp ? */ 53 sigprocmask(SIG_SETMASK, old_set, NULL); 54 cpu_loop_exit_noexc(cpu); 55 } 56 57 /* 'pc' is the host PC at which the exception was raised. 'address' is 58 the effective address of the memory exception. 'is_write' is 1 if a 59 write caused the exception and otherwise 0'. 'old_set' is the 60 signal set which should be restored */ 61 static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, 62 int is_write, sigset_t *old_set) 63 { 64 CPUState *cpu = current_cpu; 65 CPUClass *cc; 66 unsigned long address = (unsigned long)info->si_addr; 67 MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; 68 69 switch (helper_retaddr) { 70 default: 71 /* 72 * Fault during host memory operation within a helper function. 73 * The helper's host return address, saved here, gives us a 74 * pointer into the generated code that will unwind to the 75 * correct guest pc. 76 */ 77 pc = helper_retaddr; 78 break; 79 80 case 0: 81 /* 82 * Fault during host memory operation within generated code. 83 * (Or, a unrelated bug within qemu, but we can't tell from here). 84 * 85 * We take the host pc from the signal frame. However, we cannot 86 * use that value directly. Within cpu_restore_state_from_tb, we 87 * assume PC comes from GETPC(), as used by the helper functions, 88 * so we adjust the address by -GETPC_ADJ to form an address that 89 * is within the call insn, so that the address does not accidentially 90 * match the beginning of the next guest insn. However, when the 91 * pc comes from the signal frame it points to the actual faulting 92 * host memory insn and not the return from a call insn. 93 * 94 * Therefore, adjust to compensate for what will be done later 95 * by cpu_restore_state_from_tb. 96 */ 97 pc += GETPC_ADJ; 98 break; 99 100 case 1: 101 /* 102 * Fault during host read for translation, or loosely, "execution". 103 * 104 * The guest pc is already pointing to the start of the TB for which 105 * code is being generated. If the guest translator manages the 106 * page crossings correctly, this is exactly the correct address 107 * (and if the translator doesn't handle page boundaries correctly 108 * there's little we can do about that here). Therefore, do not 109 * trigger the unwinder. 110 * 111 * Like tb_gen_code, release the memory lock before cpu_loop_exit. 112 */ 113 pc = 0; 114 access_type = MMU_INST_FETCH; 115 mmap_unlock(); 116 break; 117 } 118 119 /* For synchronous signals we expect to be coming from the vCPU 120 * thread (so current_cpu should be valid) and either from running 121 * code or during translation which can fault as we cross pages. 122 * 123 * If neither is true then something has gone wrong and we should 124 * abort rather than try and restart the vCPU execution. 125 */ 126 if (!cpu || !cpu->running) { 127 printf("qemu:%s received signal outside vCPU context @ pc=0x%" 128 PRIxPTR "\n", __func__, pc); 129 abort(); 130 } 131 132 #if defined(DEBUG_SIGNAL) 133 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 134 pc, address, is_write, *(unsigned long *)old_set); 135 #endif 136 /* XXX: locking issue */ 137 /* Note that it is important that we don't call page_unprotect() unless 138 * this is really a "write to nonwriteable page" fault, because 139 * page_unprotect() assumes that if it is called for an access to 140 * a page that's writeable this means we had two threads racing and 141 * another thread got there first and already made the page writeable; 142 * so we will retry the access. If we were to call page_unprotect() 143 * for some other kind of fault that should really be passed to the 144 * guest, we'd end up in an infinite loop of retrying the faulting 145 * access. 146 */ 147 if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR && 148 h2g_valid(address)) { 149 switch (page_unprotect(h2g(address), pc)) { 150 case 0: 151 /* Fault not caused by a page marked unwritable to protect 152 * cached translations, must be the guest binary's problem. 153 */ 154 break; 155 case 1: 156 /* Fault caused by protection of cached translation; TBs 157 * invalidated, so resume execution. Retain helper_retaddr 158 * for a possible second fault. 159 */ 160 return 1; 161 case 2: 162 /* Fault caused by protection of cached translation, and the 163 * currently executing TB was modified and must be exited 164 * immediately. Clear helper_retaddr for next execution. 165 */ 166 clear_helper_retaddr(); 167 cpu_exit_tb_from_sighandler(cpu, old_set); 168 /* NORETURN */ 169 170 default: 171 g_assert_not_reached(); 172 } 173 } 174 175 /* Convert forcefully to guest address space, invalid addresses 176 are still valid segv ones */ 177 address = h2g_nocheck(address); 178 179 /* 180 * There is no way the target can handle this other than raising 181 * an exception. Undo signal and retaddr state prior to longjmp. 182 */ 183 sigprocmask(SIG_SETMASK, old_set, NULL); 184 clear_helper_retaddr(); 185 186 cc = CPU_GET_CLASS(cpu); 187 cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); 188 g_assert_not_reached(); 189 } 190 191 void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, 192 uintptr_t retaddr) 193 { 194 if (!guest_addr_valid(addr) || 195 page_check_range(addr, size, PAGE_WRITE) < 0) { 196 CPUState *cpu = env_cpu(env); 197 CPUClass *cc = CPU_GET_CLASS(cpu); 198 199 cc->tlb_fill(cpu, addr, size, MMU_DATA_STORE, MMU_USER_IDX, false, 200 retaddr); 201 g_assert_not_reached(); 202 } 203 } 204 205 #if defined(__i386__) 206 207 #if defined(__NetBSD__) 208 #include <ucontext.h> 209 210 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) 211 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 212 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 213 #define MASK_sig(context) ((context)->uc_sigmask) 214 #elif defined(__FreeBSD__) || defined(__DragonFly__) 215 #include <ucontext.h> 216 217 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) 218 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 219 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 220 #define MASK_sig(context) ((context)->uc_sigmask) 221 #elif defined(__OpenBSD__) 222 #define EIP_sig(context) ((context)->sc_eip) 223 #define TRAP_sig(context) ((context)->sc_trapno) 224 #define ERROR_sig(context) ((context)->sc_err) 225 #define MASK_sig(context) ((context)->sc_mask) 226 #else 227 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) 228 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 229 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 230 #define MASK_sig(context) ((context)->uc_sigmask) 231 #endif 232 233 int cpu_signal_handler(int host_signum, void *pinfo, 234 void *puc) 235 { 236 siginfo_t *info = pinfo; 237 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 238 ucontext_t *uc = puc; 239 #elif defined(__OpenBSD__) 240 struct sigcontext *uc = puc; 241 #else 242 ucontext_t *uc = puc; 243 #endif 244 unsigned long pc; 245 int trapno; 246 247 #ifndef REG_EIP 248 /* for glibc 2.1 */ 249 #define REG_EIP EIP 250 #define REG_ERR ERR 251 #define REG_TRAPNO TRAPNO 252 #endif 253 pc = EIP_sig(uc); 254 trapno = TRAP_sig(uc); 255 return handle_cpu_signal(pc, info, 256 trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 257 &MASK_sig(uc)); 258 } 259 260 #elif defined(__x86_64__) 261 262 #ifdef __NetBSD__ 263 #define PC_sig(context) _UC_MACHINE_PC(context) 264 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 265 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 266 #define MASK_sig(context) ((context)->uc_sigmask) 267 #elif defined(__OpenBSD__) 268 #define PC_sig(context) ((context)->sc_rip) 269 #define TRAP_sig(context) ((context)->sc_trapno) 270 #define ERROR_sig(context) ((context)->sc_err) 271 #define MASK_sig(context) ((context)->sc_mask) 272 #elif defined(__FreeBSD__) || defined(__DragonFly__) 273 #include <ucontext.h> 274 275 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) 276 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 277 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 278 #define MASK_sig(context) ((context)->uc_sigmask) 279 #else 280 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) 281 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 282 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 283 #define MASK_sig(context) ((context)->uc_sigmask) 284 #endif 285 286 int cpu_signal_handler(int host_signum, void *pinfo, 287 void *puc) 288 { 289 siginfo_t *info = pinfo; 290 unsigned long pc; 291 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 292 ucontext_t *uc = puc; 293 #elif defined(__OpenBSD__) 294 struct sigcontext *uc = puc; 295 #else 296 ucontext_t *uc = puc; 297 #endif 298 299 pc = PC_sig(uc); 300 return handle_cpu_signal(pc, info, 301 TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 302 &MASK_sig(uc)); 303 } 304 305 #elif defined(_ARCH_PPC) 306 307 /*********************************************************************** 308 * signal context platform-specific definitions 309 * From Wine 310 */ 311 #ifdef linux 312 /* All Registers access - only for local access */ 313 #define REG_sig(reg_name, context) \ 314 ((context)->uc_mcontext.regs->reg_name) 315 /* Gpr Registers access */ 316 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) 317 /* Program counter */ 318 #define IAR_sig(context) REG_sig(nip, context) 319 /* Machine State Register (Supervisor) */ 320 #define MSR_sig(context) REG_sig(msr, context) 321 /* Count register */ 322 #define CTR_sig(context) REG_sig(ctr, context) 323 /* User's integer exception register */ 324 #define XER_sig(context) REG_sig(xer, context) 325 /* Link register */ 326 #define LR_sig(context) REG_sig(link, context) 327 /* Condition register */ 328 #define CR_sig(context) REG_sig(ccr, context) 329 330 /* Float Registers access */ 331 #define FLOAT_sig(reg_num, context) \ 332 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) 333 #define FPSCR_sig(context) \ 334 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) 335 /* Exception Registers access */ 336 #define DAR_sig(context) REG_sig(dar, context) 337 #define DSISR_sig(context) REG_sig(dsisr, context) 338 #define TRAP_sig(context) REG_sig(trap, context) 339 #endif /* linux */ 340 341 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 342 #include <ucontext.h> 343 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) 344 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) 345 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) 346 #define XER_sig(context) ((context)->uc_mcontext.mc_xer) 347 #define LR_sig(context) ((context)->uc_mcontext.mc_lr) 348 #define CR_sig(context) ((context)->uc_mcontext.mc_cr) 349 /* Exception Registers access */ 350 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar) 351 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) 352 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) 353 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */ 354 355 int cpu_signal_handler(int host_signum, void *pinfo, 356 void *puc) 357 { 358 siginfo_t *info = pinfo; 359 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 360 ucontext_t *uc = puc; 361 #else 362 ucontext_t *uc = puc; 363 #endif 364 unsigned long pc; 365 int is_write; 366 367 pc = IAR_sig(uc); 368 is_write = 0; 369 #if 0 370 /* ppc 4xx case */ 371 if (DSISR_sig(uc) & 0x00800000) { 372 is_write = 1; 373 } 374 #else 375 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { 376 is_write = 1; 377 } 378 #endif 379 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 380 } 381 382 #elif defined(__alpha__) 383 384 int cpu_signal_handler(int host_signum, void *pinfo, 385 void *puc) 386 { 387 siginfo_t *info = pinfo; 388 ucontext_t *uc = puc; 389 uint32_t *pc = uc->uc_mcontext.sc_pc; 390 uint32_t insn = *pc; 391 int is_write = 0; 392 393 /* XXX: need kernel patch to get write flag faster */ 394 switch (insn >> 26) { 395 case 0x0d: /* stw */ 396 case 0x0e: /* stb */ 397 case 0x0f: /* stq_u */ 398 case 0x24: /* stf */ 399 case 0x25: /* stg */ 400 case 0x26: /* sts */ 401 case 0x27: /* stt */ 402 case 0x2c: /* stl */ 403 case 0x2d: /* stq */ 404 case 0x2e: /* stl_c */ 405 case 0x2f: /* stq_c */ 406 is_write = 1; 407 } 408 409 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 410 } 411 #elif defined(__sparc__) 412 413 int cpu_signal_handler(int host_signum, void *pinfo, 414 void *puc) 415 { 416 siginfo_t *info = pinfo; 417 int is_write; 418 uint32_t insn; 419 #if !defined(__arch64__) || defined(CONFIG_SOLARIS) 420 uint32_t *regs = (uint32_t *)(info + 1); 421 void *sigmask = (regs + 20); 422 /* XXX: is there a standard glibc define ? */ 423 unsigned long pc = regs[1]; 424 #else 425 #ifdef __linux__ 426 struct sigcontext *sc = puc; 427 unsigned long pc = sc->sigc_regs.tpc; 428 void *sigmask = (void *)sc->sigc_mask; 429 #elif defined(__OpenBSD__) 430 struct sigcontext *uc = puc; 431 unsigned long pc = uc->sc_pc; 432 void *sigmask = (void *)(long)uc->sc_mask; 433 #elif defined(__NetBSD__) 434 ucontext_t *uc = puc; 435 unsigned long pc = _UC_MACHINE_PC(uc); 436 void *sigmask = (void *)&uc->uc_sigmask; 437 #endif 438 #endif 439 440 /* XXX: need kernel patch to get write flag faster */ 441 is_write = 0; 442 insn = *(uint32_t *)pc; 443 if ((insn >> 30) == 3) { 444 switch ((insn >> 19) & 0x3f) { 445 case 0x05: /* stb */ 446 case 0x15: /* stba */ 447 case 0x06: /* sth */ 448 case 0x16: /* stha */ 449 case 0x04: /* st */ 450 case 0x14: /* sta */ 451 case 0x07: /* std */ 452 case 0x17: /* stda */ 453 case 0x0e: /* stx */ 454 case 0x1e: /* stxa */ 455 case 0x24: /* stf */ 456 case 0x34: /* stfa */ 457 case 0x27: /* stdf */ 458 case 0x37: /* stdfa */ 459 case 0x26: /* stqf */ 460 case 0x36: /* stqfa */ 461 case 0x25: /* stfsr */ 462 case 0x3c: /* casa */ 463 case 0x3e: /* casxa */ 464 is_write = 1; 465 break; 466 } 467 } 468 return handle_cpu_signal(pc, info, is_write, sigmask); 469 } 470 471 #elif defined(__arm__) 472 473 #if defined(__NetBSD__) 474 #include <ucontext.h> 475 #endif 476 477 int cpu_signal_handler(int host_signum, void *pinfo, 478 void *puc) 479 { 480 siginfo_t *info = pinfo; 481 #if defined(__NetBSD__) 482 ucontext_t *uc = puc; 483 #else 484 ucontext_t *uc = puc; 485 #endif 486 unsigned long pc; 487 int is_write; 488 489 #if defined(__NetBSD__) 490 pc = uc->uc_mcontext.__gregs[_REG_R15]; 491 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) 492 pc = uc->uc_mcontext.gregs[R15]; 493 #else 494 pc = uc->uc_mcontext.arm_pc; 495 #endif 496 497 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or 498 * later processor; on v5 we will always report this as a read). 499 */ 500 is_write = extract32(uc->uc_mcontext.error_code, 11, 1); 501 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 502 } 503 504 #elif defined(__aarch64__) 505 506 #ifndef ESR_MAGIC 507 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ 508 #define ESR_MAGIC 0x45535201 509 struct esr_context { 510 struct _aarch64_ctx head; 511 uint64_t esr; 512 }; 513 #endif 514 515 static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) 516 { 517 return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; 518 } 519 520 static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) 521 { 522 return (struct _aarch64_ctx *)((char *)hdr + hdr->size); 523 } 524 525 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) 526 { 527 siginfo_t *info = pinfo; 528 ucontext_t *uc = puc; 529 uintptr_t pc = uc->uc_mcontext.pc; 530 bool is_write; 531 struct _aarch64_ctx *hdr; 532 struct esr_context const *esrctx = NULL; 533 534 /* Find the esr_context, which has the WnR bit in it */ 535 for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { 536 if (hdr->magic == ESR_MAGIC) { 537 esrctx = (struct esr_context const *)hdr; 538 break; 539 } 540 } 541 542 if (esrctx) { 543 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ 544 uint64_t esr = esrctx->esr; 545 is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; 546 } else { 547 /* 548 * Fall back to parsing instructions; will only be needed 549 * for really ancient (pre-3.16) kernels. 550 */ 551 uint32_t insn = *(uint32_t *)pc; 552 553 is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ 554 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ 555 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ 556 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ 557 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ 558 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ 559 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ 560 /* Ignore bits 10, 11 & 21, controlling indexing. */ 561 || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ 562 || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ 563 /* Ignore bits 23 & 24, controlling indexing. */ 564 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ 565 } 566 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 567 } 568 569 #elif defined(__s390__) 570 571 int cpu_signal_handler(int host_signum, void *pinfo, 572 void *puc) 573 { 574 siginfo_t *info = pinfo; 575 ucontext_t *uc = puc; 576 unsigned long pc; 577 uint16_t *pinsn; 578 int is_write = 0; 579 580 pc = uc->uc_mcontext.psw.addr; 581 582 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead 583 of the normal 2 arguments. The 3rd argument contains the "int_code" 584 from the hardware which does in fact contain the is_write value. 585 The rt signal handler, as far as I can tell, does not give this value 586 at all. Not that we could get to it from here even if it were. */ 587 /* ??? This is not even close to complete, since it ignores all 588 of the read-modify-write instructions. */ 589 pinsn = (uint16_t *)pc; 590 switch (pinsn[0] >> 8) { 591 case 0x50: /* ST */ 592 case 0x42: /* STC */ 593 case 0x40: /* STH */ 594 is_write = 1; 595 break; 596 case 0xc4: /* RIL format insns */ 597 switch (pinsn[0] & 0xf) { 598 case 0xf: /* STRL */ 599 case 0xb: /* STGRL */ 600 case 0x7: /* STHRL */ 601 is_write = 1; 602 } 603 break; 604 case 0xe3: /* RXY format insns */ 605 switch (pinsn[2] & 0xff) { 606 case 0x50: /* STY */ 607 case 0x24: /* STG */ 608 case 0x72: /* STCY */ 609 case 0x70: /* STHY */ 610 case 0x8e: /* STPQ */ 611 case 0x3f: /* STRVH */ 612 case 0x3e: /* STRV */ 613 case 0x2f: /* STRVG */ 614 is_write = 1; 615 } 616 break; 617 } 618 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 619 } 620 621 #elif defined(__mips__) 622 623 int cpu_signal_handler(int host_signum, void *pinfo, 624 void *puc) 625 { 626 siginfo_t *info = pinfo; 627 ucontext_t *uc = puc; 628 greg_t pc = uc->uc_mcontext.pc; 629 int is_write; 630 631 /* XXX: compute is_write */ 632 is_write = 0; 633 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 634 } 635 636 #elif defined(__riscv) 637 638 int cpu_signal_handler(int host_signum, void *pinfo, 639 void *puc) 640 { 641 siginfo_t *info = pinfo; 642 ucontext_t *uc = puc; 643 greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; 644 uint32_t insn = *(uint32_t *)pc; 645 int is_write = 0; 646 647 /* Detect store by reading the instruction at the program 648 counter. Note: we currently only generate 32-bit 649 instructions so we thus only detect 32-bit stores */ 650 switch (((insn >> 0) & 0b11)) { 651 case 3: 652 switch (((insn >> 2) & 0b11111)) { 653 case 8: 654 switch (((insn >> 12) & 0b111)) { 655 case 0: /* sb */ 656 case 1: /* sh */ 657 case 2: /* sw */ 658 case 3: /* sd */ 659 case 4: /* sq */ 660 is_write = 1; 661 break; 662 default: 663 break; 664 } 665 break; 666 case 9: 667 switch (((insn >> 12) & 0b111)) { 668 case 2: /* fsw */ 669 case 3: /* fsd */ 670 case 4: /* fsq */ 671 is_write = 1; 672 break; 673 default: 674 break; 675 } 676 break; 677 default: 678 break; 679 } 680 } 681 682 /* Check for compressed instructions */ 683 switch (((insn >> 13) & 0b111)) { 684 case 7: 685 switch (insn & 0b11) { 686 case 0: /*c.sd */ 687 case 2: /* c.sdsp */ 688 is_write = 1; 689 break; 690 default: 691 break; 692 } 693 break; 694 case 6: 695 switch (insn & 0b11) { 696 case 0: /* c.sw */ 697 case 3: /* c.swsp */ 698 is_write = 1; 699 break; 700 default: 701 break; 702 } 703 break; 704 default: 705 break; 706 } 707 708 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 709 } 710 711 #else 712 713 #error host CPU specific signal handler needed 714 715 #endif 716 717 /* The softmmu versions of these helpers are in cputlb.c. */ 718 719 /* Do not allow unaligned operations to proceed. Return the host address. */ 720 static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, 721 int size, uintptr_t retaddr) 722 { 723 /* Enforce qemu required alignment. */ 724 if (unlikely(addr & (size - 1))) { 725 cpu_loop_exit_atomic(env_cpu(env), retaddr); 726 } 727 void *ret = g2h(addr); 728 set_helper_retaddr(retaddr); 729 return ret; 730 } 731 732 /* Macro to call the above, with local variables from the use context. */ 733 #define ATOMIC_MMU_DECLS do {} while (0) 734 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC()) 735 #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) 736 737 #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) 738 #define EXTRA_ARGS 739 740 #define DATA_SIZE 1 741 #include "atomic_template.h" 742 743 #define DATA_SIZE 2 744 #include "atomic_template.h" 745 746 #define DATA_SIZE 4 747 #include "atomic_template.h" 748 749 #ifdef CONFIG_ATOMIC64 750 #define DATA_SIZE 8 751 #include "atomic_template.h" 752 #endif 753 754 /* The following is only callable from other helpers, and matches up 755 with the softmmu version. */ 756 757 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128 758 759 #undef EXTRA_ARGS 760 #undef ATOMIC_NAME 761 #undef ATOMIC_MMU_LOOKUP 762 763 #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr 764 #define ATOMIC_NAME(X) \ 765 HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) 766 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr) 767 768 #define DATA_SIZE 16 769 #include "atomic_template.h" 770 #endif 771