1 /* 2 * User emulator execution 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "disas/disas.h" 22 #include "exec/exec-all.h" 23 #include "tcg/tcg.h" 24 #include "qemu/bitops.h" 25 #include "exec/cpu_ldst.h" 26 #include "exec/translate-all.h" 27 #include "exec/helper-proto.h" 28 #include "qemu/atomic128.h" 29 #include "trace/trace-root.h" 30 #include "trace/mem.h" 31 32 #undef EAX 33 #undef ECX 34 #undef EDX 35 #undef EBX 36 #undef ESP 37 #undef EBP 38 #undef ESI 39 #undef EDI 40 #undef EIP 41 #ifdef __linux__ 42 #include <sys/ucontext.h> 43 #endif 44 45 __thread uintptr_t helper_retaddr; 46 47 //#define DEBUG_SIGNAL 48 49 /* exit the current TB from a signal handler. The host registers are 50 restored in a state compatible with the CPU emulator 51 */ 52 static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu, 53 sigset_t *old_set) 54 { 55 /* XXX: use siglongjmp ? */ 56 sigprocmask(SIG_SETMASK, old_set, NULL); 57 cpu_loop_exit_noexc(cpu); 58 } 59 60 /* 'pc' is the host PC at which the exception was raised. 'address' is 61 the effective address of the memory exception. 'is_write' is 1 if a 62 write caused the exception and otherwise 0'. 'old_set' is the 63 signal set which should be restored */ 64 static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, 65 int is_write, sigset_t *old_set) 66 { 67 CPUState *cpu = current_cpu; 68 CPUClass *cc; 69 unsigned long address = (unsigned long)info->si_addr; 70 MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; 71 72 switch (helper_retaddr) { 73 default: 74 /* 75 * Fault during host memory operation within a helper function. 76 * The helper's host return address, saved here, gives us a 77 * pointer into the generated code that will unwind to the 78 * correct guest pc. 79 */ 80 pc = helper_retaddr; 81 break; 82 83 case 0: 84 /* 85 * Fault during host memory operation within generated code. 86 * (Or, a unrelated bug within qemu, but we can't tell from here). 87 * 88 * We take the host pc from the signal frame. However, we cannot 89 * use that value directly. Within cpu_restore_state_from_tb, we 90 * assume PC comes from GETPC(), as used by the helper functions, 91 * so we adjust the address by -GETPC_ADJ to form an address that 92 * is within the call insn, so that the address does not accidentally 93 * match the beginning of the next guest insn. However, when the 94 * pc comes from the signal frame it points to the actual faulting 95 * host memory insn and not the return from a call insn. 96 * 97 * Therefore, adjust to compensate for what will be done later 98 * by cpu_restore_state_from_tb. 99 */ 100 pc += GETPC_ADJ; 101 break; 102 103 case 1: 104 /* 105 * Fault during host read for translation, or loosely, "execution". 106 * 107 * The guest pc is already pointing to the start of the TB for which 108 * code is being generated. If the guest translator manages the 109 * page crossings correctly, this is exactly the correct address 110 * (and if the translator doesn't handle page boundaries correctly 111 * there's little we can do about that here). Therefore, do not 112 * trigger the unwinder. 113 * 114 * Like tb_gen_code, release the memory lock before cpu_loop_exit. 115 */ 116 pc = 0; 117 access_type = MMU_INST_FETCH; 118 mmap_unlock(); 119 break; 120 } 121 122 /* For synchronous signals we expect to be coming from the vCPU 123 * thread (so current_cpu should be valid) and either from running 124 * code or during translation which can fault as we cross pages. 125 * 126 * If neither is true then something has gone wrong and we should 127 * abort rather than try and restart the vCPU execution. 128 */ 129 if (!cpu || !cpu->running) { 130 printf("qemu:%s received signal outside vCPU context @ pc=0x%" 131 PRIxPTR "\n", __func__, pc); 132 abort(); 133 } 134 135 #if defined(DEBUG_SIGNAL) 136 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 137 pc, address, is_write, *(unsigned long *)old_set); 138 #endif 139 /* XXX: locking issue */ 140 /* Note that it is important that we don't call page_unprotect() unless 141 * this is really a "write to nonwriteable page" fault, because 142 * page_unprotect() assumes that if it is called for an access to 143 * a page that's writeable this means we had two threads racing and 144 * another thread got there first and already made the page writeable; 145 * so we will retry the access. If we were to call page_unprotect() 146 * for some other kind of fault that should really be passed to the 147 * guest, we'd end up in an infinite loop of retrying the faulting 148 * access. 149 */ 150 if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR && 151 h2g_valid(address)) { 152 switch (page_unprotect(h2g(address), pc)) { 153 case 0: 154 /* Fault not caused by a page marked unwritable to protect 155 * cached translations, must be the guest binary's problem. 156 */ 157 break; 158 case 1: 159 /* Fault caused by protection of cached translation; TBs 160 * invalidated, so resume execution. Retain helper_retaddr 161 * for a possible second fault. 162 */ 163 return 1; 164 case 2: 165 /* Fault caused by protection of cached translation, and the 166 * currently executing TB was modified and must be exited 167 * immediately. Clear helper_retaddr for next execution. 168 */ 169 clear_helper_retaddr(); 170 cpu_exit_tb_from_sighandler(cpu, old_set); 171 /* NORETURN */ 172 173 default: 174 g_assert_not_reached(); 175 } 176 } 177 178 /* Convert forcefully to guest address space, invalid addresses 179 are still valid segv ones */ 180 address = h2g_nocheck(address); 181 182 /* 183 * There is no way the target can handle this other than raising 184 * an exception. Undo signal and retaddr state prior to longjmp. 185 */ 186 sigprocmask(SIG_SETMASK, old_set, NULL); 187 clear_helper_retaddr(); 188 189 cc = CPU_GET_CLASS(cpu); 190 cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); 191 g_assert_not_reached(); 192 } 193 194 static int probe_access_internal(CPUArchState *env, target_ulong addr, 195 int fault_size, MMUAccessType access_type, 196 bool nonfault, uintptr_t ra) 197 { 198 int flags; 199 200 switch (access_type) { 201 case MMU_DATA_STORE: 202 flags = PAGE_WRITE; 203 break; 204 case MMU_DATA_LOAD: 205 flags = PAGE_READ; 206 break; 207 case MMU_INST_FETCH: 208 flags = PAGE_EXEC; 209 break; 210 default: 211 g_assert_not_reached(); 212 } 213 214 if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) { 215 if (nonfault) { 216 return TLB_INVALID_MASK; 217 } else { 218 CPUState *cpu = env_cpu(env); 219 CPUClass *cc = CPU_GET_CLASS(cpu); 220 cc->tlb_fill(cpu, addr, fault_size, access_type, 221 MMU_USER_IDX, false, ra); 222 g_assert_not_reached(); 223 } 224 } 225 return 0; 226 } 227 228 int probe_access_flags(CPUArchState *env, target_ulong addr, 229 MMUAccessType access_type, int mmu_idx, 230 bool nonfault, void **phost, uintptr_t ra) 231 { 232 int flags; 233 234 flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra); 235 *phost = flags ? NULL : g2h(addr); 236 return flags; 237 } 238 239 void *probe_access(CPUArchState *env, target_ulong addr, int size, 240 MMUAccessType access_type, int mmu_idx, uintptr_t ra) 241 { 242 int flags; 243 244 g_assert(-(addr | TARGET_PAGE_MASK) >= size); 245 flags = probe_access_internal(env, addr, size, access_type, false, ra); 246 g_assert(flags == 0); 247 248 return size ? g2h(addr) : NULL; 249 } 250 251 #if defined(__i386__) 252 253 #if defined(__NetBSD__) 254 #include <ucontext.h> 255 256 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) 257 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 258 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 259 #define MASK_sig(context) ((context)->uc_sigmask) 260 #elif defined(__FreeBSD__) || defined(__DragonFly__) 261 #include <ucontext.h> 262 263 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) 264 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 265 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 266 #define MASK_sig(context) ((context)->uc_sigmask) 267 #elif defined(__OpenBSD__) 268 #define EIP_sig(context) ((context)->sc_eip) 269 #define TRAP_sig(context) ((context)->sc_trapno) 270 #define ERROR_sig(context) ((context)->sc_err) 271 #define MASK_sig(context) ((context)->sc_mask) 272 #else 273 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) 274 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 275 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 276 #define MASK_sig(context) ((context)->uc_sigmask) 277 #endif 278 279 int cpu_signal_handler(int host_signum, void *pinfo, 280 void *puc) 281 { 282 siginfo_t *info = pinfo; 283 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 284 ucontext_t *uc = puc; 285 #elif defined(__OpenBSD__) 286 struct sigcontext *uc = puc; 287 #else 288 ucontext_t *uc = puc; 289 #endif 290 unsigned long pc; 291 int trapno; 292 293 #ifndef REG_EIP 294 /* for glibc 2.1 */ 295 #define REG_EIP EIP 296 #define REG_ERR ERR 297 #define REG_TRAPNO TRAPNO 298 #endif 299 pc = EIP_sig(uc); 300 trapno = TRAP_sig(uc); 301 return handle_cpu_signal(pc, info, 302 trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 303 &MASK_sig(uc)); 304 } 305 306 #elif defined(__x86_64__) 307 308 #ifdef __NetBSD__ 309 #define PC_sig(context) _UC_MACHINE_PC(context) 310 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 311 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 312 #define MASK_sig(context) ((context)->uc_sigmask) 313 #elif defined(__OpenBSD__) 314 #define PC_sig(context) ((context)->sc_rip) 315 #define TRAP_sig(context) ((context)->sc_trapno) 316 #define ERROR_sig(context) ((context)->sc_err) 317 #define MASK_sig(context) ((context)->sc_mask) 318 #elif defined(__FreeBSD__) || defined(__DragonFly__) 319 #include <ucontext.h> 320 321 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) 322 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 323 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 324 #define MASK_sig(context) ((context)->uc_sigmask) 325 #else 326 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) 327 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 328 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 329 #define MASK_sig(context) ((context)->uc_sigmask) 330 #endif 331 332 int cpu_signal_handler(int host_signum, void *pinfo, 333 void *puc) 334 { 335 siginfo_t *info = pinfo; 336 unsigned long pc; 337 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 338 ucontext_t *uc = puc; 339 #elif defined(__OpenBSD__) 340 struct sigcontext *uc = puc; 341 #else 342 ucontext_t *uc = puc; 343 #endif 344 345 pc = PC_sig(uc); 346 return handle_cpu_signal(pc, info, 347 TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 348 &MASK_sig(uc)); 349 } 350 351 #elif defined(_ARCH_PPC) 352 353 /*********************************************************************** 354 * signal context platform-specific definitions 355 * From Wine 356 */ 357 #ifdef linux 358 /* All Registers access - only for local access */ 359 #define REG_sig(reg_name, context) \ 360 ((context)->uc_mcontext.regs->reg_name) 361 /* Gpr Registers access */ 362 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) 363 /* Program counter */ 364 #define IAR_sig(context) REG_sig(nip, context) 365 /* Machine State Register (Supervisor) */ 366 #define MSR_sig(context) REG_sig(msr, context) 367 /* Count register */ 368 #define CTR_sig(context) REG_sig(ctr, context) 369 /* User's integer exception register */ 370 #define XER_sig(context) REG_sig(xer, context) 371 /* Link register */ 372 #define LR_sig(context) REG_sig(link, context) 373 /* Condition register */ 374 #define CR_sig(context) REG_sig(ccr, context) 375 376 /* Float Registers access */ 377 #define FLOAT_sig(reg_num, context) \ 378 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) 379 #define FPSCR_sig(context) \ 380 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) 381 /* Exception Registers access */ 382 #define DAR_sig(context) REG_sig(dar, context) 383 #define DSISR_sig(context) REG_sig(dsisr, context) 384 #define TRAP_sig(context) REG_sig(trap, context) 385 #endif /* linux */ 386 387 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 388 #include <ucontext.h> 389 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) 390 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) 391 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) 392 #define XER_sig(context) ((context)->uc_mcontext.mc_xer) 393 #define LR_sig(context) ((context)->uc_mcontext.mc_lr) 394 #define CR_sig(context) ((context)->uc_mcontext.mc_cr) 395 /* Exception Registers access */ 396 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar) 397 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) 398 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) 399 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */ 400 401 int cpu_signal_handler(int host_signum, void *pinfo, 402 void *puc) 403 { 404 siginfo_t *info = pinfo; 405 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 406 ucontext_t *uc = puc; 407 #else 408 ucontext_t *uc = puc; 409 #endif 410 unsigned long pc; 411 int is_write; 412 413 pc = IAR_sig(uc); 414 is_write = 0; 415 #if 0 416 /* ppc 4xx case */ 417 if (DSISR_sig(uc) & 0x00800000) { 418 is_write = 1; 419 } 420 #else 421 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { 422 is_write = 1; 423 } 424 #endif 425 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 426 } 427 428 #elif defined(__alpha__) 429 430 int cpu_signal_handler(int host_signum, void *pinfo, 431 void *puc) 432 { 433 siginfo_t *info = pinfo; 434 ucontext_t *uc = puc; 435 uint32_t *pc = uc->uc_mcontext.sc_pc; 436 uint32_t insn = *pc; 437 int is_write = 0; 438 439 /* XXX: need kernel patch to get write flag faster */ 440 switch (insn >> 26) { 441 case 0x0d: /* stw */ 442 case 0x0e: /* stb */ 443 case 0x0f: /* stq_u */ 444 case 0x24: /* stf */ 445 case 0x25: /* stg */ 446 case 0x26: /* sts */ 447 case 0x27: /* stt */ 448 case 0x2c: /* stl */ 449 case 0x2d: /* stq */ 450 case 0x2e: /* stl_c */ 451 case 0x2f: /* stq_c */ 452 is_write = 1; 453 } 454 455 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 456 } 457 #elif defined(__sparc__) 458 459 int cpu_signal_handler(int host_signum, void *pinfo, 460 void *puc) 461 { 462 siginfo_t *info = pinfo; 463 int is_write; 464 uint32_t insn; 465 #if !defined(__arch64__) || defined(CONFIG_SOLARIS) 466 uint32_t *regs = (uint32_t *)(info + 1); 467 void *sigmask = (regs + 20); 468 /* XXX: is there a standard glibc define ? */ 469 unsigned long pc = regs[1]; 470 #else 471 #ifdef __linux__ 472 struct sigcontext *sc = puc; 473 unsigned long pc = sc->sigc_regs.tpc; 474 void *sigmask = (void *)sc->sigc_mask; 475 #elif defined(__OpenBSD__) 476 struct sigcontext *uc = puc; 477 unsigned long pc = uc->sc_pc; 478 void *sigmask = (void *)(long)uc->sc_mask; 479 #elif defined(__NetBSD__) 480 ucontext_t *uc = puc; 481 unsigned long pc = _UC_MACHINE_PC(uc); 482 void *sigmask = (void *)&uc->uc_sigmask; 483 #endif 484 #endif 485 486 /* XXX: need kernel patch to get write flag faster */ 487 is_write = 0; 488 insn = *(uint32_t *)pc; 489 if ((insn >> 30) == 3) { 490 switch ((insn >> 19) & 0x3f) { 491 case 0x05: /* stb */ 492 case 0x15: /* stba */ 493 case 0x06: /* sth */ 494 case 0x16: /* stha */ 495 case 0x04: /* st */ 496 case 0x14: /* sta */ 497 case 0x07: /* std */ 498 case 0x17: /* stda */ 499 case 0x0e: /* stx */ 500 case 0x1e: /* stxa */ 501 case 0x24: /* stf */ 502 case 0x34: /* stfa */ 503 case 0x27: /* stdf */ 504 case 0x37: /* stdfa */ 505 case 0x26: /* stqf */ 506 case 0x36: /* stqfa */ 507 case 0x25: /* stfsr */ 508 case 0x3c: /* casa */ 509 case 0x3e: /* casxa */ 510 is_write = 1; 511 break; 512 } 513 } 514 return handle_cpu_signal(pc, info, is_write, sigmask); 515 } 516 517 #elif defined(__arm__) 518 519 #if defined(__NetBSD__) 520 #include <ucontext.h> 521 #include <sys/siginfo.h> 522 #endif 523 524 int cpu_signal_handler(int host_signum, void *pinfo, 525 void *puc) 526 { 527 siginfo_t *info = pinfo; 528 #if defined(__NetBSD__) 529 ucontext_t *uc = puc; 530 siginfo_t *si = pinfo; 531 #else 532 ucontext_t *uc = puc; 533 #endif 534 unsigned long pc; 535 uint32_t fsr; 536 int is_write; 537 538 #if defined(__NetBSD__) 539 pc = uc->uc_mcontext.__gregs[_REG_R15]; 540 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) 541 pc = uc->uc_mcontext.gregs[R15]; 542 #else 543 pc = uc->uc_mcontext.arm_pc; 544 #endif 545 546 #ifdef __NetBSD__ 547 fsr = si->si_trap; 548 #else 549 fsr = uc->uc_mcontext.error_code; 550 #endif 551 /* 552 * In the FSR, bit 11 is WnR, assuming a v6 or 553 * later processor. On v5 we will always report 554 * this as a read, which will fail later. 555 */ 556 is_write = extract32(fsr, 11, 1); 557 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 558 } 559 560 #elif defined(__aarch64__) 561 562 #if defined(__NetBSD__) 563 564 #include <ucontext.h> 565 #include <sys/siginfo.h> 566 567 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) 568 { 569 ucontext_t *uc = puc; 570 siginfo_t *si = pinfo; 571 unsigned long pc; 572 int is_write; 573 uint32_t esr; 574 575 pc = uc->uc_mcontext.__gregs[_REG_PC]; 576 esr = si->si_trap; 577 578 /* 579 * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC 580 * is 0b10010x: then bit 6 is the WnR bit 581 */ 582 is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; 583 return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask); 584 } 585 586 #else 587 588 #ifndef ESR_MAGIC 589 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ 590 #define ESR_MAGIC 0x45535201 591 struct esr_context { 592 struct _aarch64_ctx head; 593 uint64_t esr; 594 }; 595 #endif 596 597 static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) 598 { 599 return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; 600 } 601 602 static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) 603 { 604 return (struct _aarch64_ctx *)((char *)hdr + hdr->size); 605 } 606 607 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) 608 { 609 siginfo_t *info = pinfo; 610 ucontext_t *uc = puc; 611 uintptr_t pc = uc->uc_mcontext.pc; 612 bool is_write; 613 struct _aarch64_ctx *hdr; 614 struct esr_context const *esrctx = NULL; 615 616 /* Find the esr_context, which has the WnR bit in it */ 617 for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { 618 if (hdr->magic == ESR_MAGIC) { 619 esrctx = (struct esr_context const *)hdr; 620 break; 621 } 622 } 623 624 if (esrctx) { 625 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ 626 uint64_t esr = esrctx->esr; 627 is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; 628 } else { 629 /* 630 * Fall back to parsing instructions; will only be needed 631 * for really ancient (pre-3.16) kernels. 632 */ 633 uint32_t insn = *(uint32_t *)pc; 634 635 is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ 636 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ 637 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ 638 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ 639 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ 640 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ 641 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ 642 /* Ignore bits 10, 11 & 21, controlling indexing. */ 643 || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ 644 || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ 645 /* Ignore bits 23 & 24, controlling indexing. */ 646 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ 647 } 648 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 649 } 650 #endif 651 652 #elif defined(__s390__) 653 654 int cpu_signal_handler(int host_signum, void *pinfo, 655 void *puc) 656 { 657 siginfo_t *info = pinfo; 658 ucontext_t *uc = puc; 659 unsigned long pc; 660 uint16_t *pinsn; 661 int is_write = 0; 662 663 pc = uc->uc_mcontext.psw.addr; 664 665 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead 666 of the normal 2 arguments. The 3rd argument contains the "int_code" 667 from the hardware which does in fact contain the is_write value. 668 The rt signal handler, as far as I can tell, does not give this value 669 at all. Not that we could get to it from here even if it were. */ 670 /* ??? This is not even close to complete, since it ignores all 671 of the read-modify-write instructions. */ 672 pinsn = (uint16_t *)pc; 673 switch (pinsn[0] >> 8) { 674 case 0x50: /* ST */ 675 case 0x42: /* STC */ 676 case 0x40: /* STH */ 677 is_write = 1; 678 break; 679 case 0xc4: /* RIL format insns */ 680 switch (pinsn[0] & 0xf) { 681 case 0xf: /* STRL */ 682 case 0xb: /* STGRL */ 683 case 0x7: /* STHRL */ 684 is_write = 1; 685 } 686 break; 687 case 0xe3: /* RXY format insns */ 688 switch (pinsn[2] & 0xff) { 689 case 0x50: /* STY */ 690 case 0x24: /* STG */ 691 case 0x72: /* STCY */ 692 case 0x70: /* STHY */ 693 case 0x8e: /* STPQ */ 694 case 0x3f: /* STRVH */ 695 case 0x3e: /* STRV */ 696 case 0x2f: /* STRVG */ 697 is_write = 1; 698 } 699 break; 700 } 701 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 702 } 703 704 #elif defined(__mips__) 705 706 #if defined(__misp16) || defined(__mips_micromips) 707 #error "Unsupported encoding" 708 #endif 709 710 int cpu_signal_handler(int host_signum, void *pinfo, 711 void *puc) 712 { 713 siginfo_t *info = pinfo; 714 ucontext_t *uc = puc; 715 uintptr_t pc = uc->uc_mcontext.pc; 716 uint32_t insn = *(uint32_t *)pc; 717 int is_write = 0; 718 719 /* Detect all store instructions at program counter. */ 720 switch((insn >> 26) & 077) { 721 case 050: /* SB */ 722 case 051: /* SH */ 723 case 052: /* SWL */ 724 case 053: /* SW */ 725 case 054: /* SDL */ 726 case 055: /* SDR */ 727 case 056: /* SWR */ 728 case 070: /* SC */ 729 case 071: /* SWC1 */ 730 case 074: /* SCD */ 731 case 075: /* SDC1 */ 732 case 077: /* SD */ 733 #if !defined(__mips_isa_rev) || __mips_isa_rev < 6 734 case 072: /* SWC2 */ 735 case 076: /* SDC2 */ 736 #endif 737 is_write = 1; 738 break; 739 case 023: /* COP1X */ 740 /* Required in all versions of MIPS64 since 741 MIPS64r1 and subsequent versions of MIPS32r2. */ 742 switch (insn & 077) { 743 case 010: /* SWXC1 */ 744 case 011: /* SDXC1 */ 745 case 015: /* SUXC1 */ 746 is_write = 1; 747 } 748 break; 749 } 750 751 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 752 } 753 754 #elif defined(__riscv) 755 756 int cpu_signal_handler(int host_signum, void *pinfo, 757 void *puc) 758 { 759 siginfo_t *info = pinfo; 760 ucontext_t *uc = puc; 761 greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; 762 uint32_t insn = *(uint32_t *)pc; 763 int is_write = 0; 764 765 /* Detect store by reading the instruction at the program 766 counter. Note: we currently only generate 32-bit 767 instructions so we thus only detect 32-bit stores */ 768 switch (((insn >> 0) & 0b11)) { 769 case 3: 770 switch (((insn >> 2) & 0b11111)) { 771 case 8: 772 switch (((insn >> 12) & 0b111)) { 773 case 0: /* sb */ 774 case 1: /* sh */ 775 case 2: /* sw */ 776 case 3: /* sd */ 777 case 4: /* sq */ 778 is_write = 1; 779 break; 780 default: 781 break; 782 } 783 break; 784 case 9: 785 switch (((insn >> 12) & 0b111)) { 786 case 2: /* fsw */ 787 case 3: /* fsd */ 788 case 4: /* fsq */ 789 is_write = 1; 790 break; 791 default: 792 break; 793 } 794 break; 795 default: 796 break; 797 } 798 } 799 800 /* Check for compressed instructions */ 801 switch (((insn >> 13) & 0b111)) { 802 case 7: 803 switch (insn & 0b11) { 804 case 0: /*c.sd */ 805 case 2: /* c.sdsp */ 806 is_write = 1; 807 break; 808 default: 809 break; 810 } 811 break; 812 case 6: 813 switch (insn & 0b11) { 814 case 0: /* c.sw */ 815 case 3: /* c.swsp */ 816 is_write = 1; 817 break; 818 default: 819 break; 820 } 821 break; 822 default: 823 break; 824 } 825 826 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 827 } 828 829 #else 830 831 #error host CPU specific signal handler needed 832 833 #endif 834 835 /* The softmmu versions of these helpers are in cputlb.c. */ 836 837 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) 838 { 839 uint32_t ret; 840 uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, false); 841 842 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 843 ret = ldub_p(g2h(ptr)); 844 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 845 return ret; 846 } 847 848 int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) 849 { 850 int ret; 851 uint16_t meminfo = trace_mem_get_info(MO_SB, MMU_USER_IDX, false); 852 853 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 854 ret = ldsb_p(g2h(ptr)); 855 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 856 return ret; 857 } 858 859 uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr) 860 { 861 uint32_t ret; 862 uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false); 863 864 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 865 ret = lduw_be_p(g2h(ptr)); 866 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 867 return ret; 868 } 869 870 int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) 871 { 872 int ret; 873 uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false); 874 875 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 876 ret = ldsw_be_p(g2h(ptr)); 877 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 878 return ret; 879 } 880 881 uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) 882 { 883 uint32_t ret; 884 uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false); 885 886 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 887 ret = ldl_be_p(g2h(ptr)); 888 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 889 return ret; 890 } 891 892 uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) 893 { 894 uint64_t ret; 895 uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false); 896 897 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 898 ret = ldq_be_p(g2h(ptr)); 899 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 900 return ret; 901 } 902 903 uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr) 904 { 905 uint32_t ret; 906 uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false); 907 908 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 909 ret = lduw_le_p(g2h(ptr)); 910 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 911 return ret; 912 } 913 914 int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) 915 { 916 int ret; 917 uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false); 918 919 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 920 ret = ldsw_le_p(g2h(ptr)); 921 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 922 return ret; 923 } 924 925 uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) 926 { 927 uint32_t ret; 928 uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false); 929 930 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 931 ret = ldl_le_p(g2h(ptr)); 932 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 933 return ret; 934 } 935 936 uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) 937 { 938 uint64_t ret; 939 uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false); 940 941 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 942 ret = ldq_le_p(g2h(ptr)); 943 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 944 return ret; 945 } 946 947 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 948 { 949 uint32_t ret; 950 951 set_helper_retaddr(retaddr); 952 ret = cpu_ldub_data(env, ptr); 953 clear_helper_retaddr(); 954 return ret; 955 } 956 957 int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 958 { 959 int ret; 960 961 set_helper_retaddr(retaddr); 962 ret = cpu_ldsb_data(env, ptr); 963 clear_helper_retaddr(); 964 return ret; 965 } 966 967 uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 968 { 969 uint32_t ret; 970 971 set_helper_retaddr(retaddr); 972 ret = cpu_lduw_be_data(env, ptr); 973 clear_helper_retaddr(); 974 return ret; 975 } 976 977 int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 978 { 979 int ret; 980 981 set_helper_retaddr(retaddr); 982 ret = cpu_ldsw_be_data(env, ptr); 983 clear_helper_retaddr(); 984 return ret; 985 } 986 987 uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 988 { 989 uint32_t ret; 990 991 set_helper_retaddr(retaddr); 992 ret = cpu_ldl_be_data(env, ptr); 993 clear_helper_retaddr(); 994 return ret; 995 } 996 997 uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 998 { 999 uint64_t ret; 1000 1001 set_helper_retaddr(retaddr); 1002 ret = cpu_ldq_be_data(env, ptr); 1003 clear_helper_retaddr(); 1004 return ret; 1005 } 1006 1007 uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1008 { 1009 uint32_t ret; 1010 1011 set_helper_retaddr(retaddr); 1012 ret = cpu_lduw_le_data(env, ptr); 1013 clear_helper_retaddr(); 1014 return ret; 1015 } 1016 1017 int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1018 { 1019 int ret; 1020 1021 set_helper_retaddr(retaddr); 1022 ret = cpu_ldsw_le_data(env, ptr); 1023 clear_helper_retaddr(); 1024 return ret; 1025 } 1026 1027 uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1028 { 1029 uint32_t ret; 1030 1031 set_helper_retaddr(retaddr); 1032 ret = cpu_ldl_le_data(env, ptr); 1033 clear_helper_retaddr(); 1034 return ret; 1035 } 1036 1037 uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 1038 { 1039 uint64_t ret; 1040 1041 set_helper_retaddr(retaddr); 1042 ret = cpu_ldq_le_data(env, ptr); 1043 clear_helper_retaddr(); 1044 return ret; 1045 } 1046 1047 void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1048 { 1049 uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, true); 1050 1051 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1052 stb_p(g2h(ptr), val); 1053 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1054 } 1055 1056 void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1057 { 1058 uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true); 1059 1060 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1061 stw_be_p(g2h(ptr), val); 1062 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1063 } 1064 1065 void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1066 { 1067 uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true); 1068 1069 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1070 stl_be_p(g2h(ptr), val); 1071 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1072 } 1073 1074 void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val) 1075 { 1076 uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true); 1077 1078 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1079 stq_be_p(g2h(ptr), val); 1080 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1081 } 1082 1083 void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1084 { 1085 uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true); 1086 1087 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1088 stw_le_p(g2h(ptr), val); 1089 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1090 } 1091 1092 void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1093 { 1094 uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true); 1095 1096 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1097 stl_le_p(g2h(ptr), val); 1098 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1099 } 1100 1101 void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val) 1102 { 1103 uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true); 1104 1105 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1106 stq_le_p(g2h(ptr), val); 1107 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1108 } 1109 1110 void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, 1111 uint32_t val, uintptr_t retaddr) 1112 { 1113 set_helper_retaddr(retaddr); 1114 cpu_stb_data(env, ptr, val); 1115 clear_helper_retaddr(); 1116 } 1117 1118 void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr, 1119 uint32_t val, uintptr_t retaddr) 1120 { 1121 set_helper_retaddr(retaddr); 1122 cpu_stw_be_data(env, ptr, val); 1123 clear_helper_retaddr(); 1124 } 1125 1126 void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr, 1127 uint32_t val, uintptr_t retaddr) 1128 { 1129 set_helper_retaddr(retaddr); 1130 cpu_stl_be_data(env, ptr, val); 1131 clear_helper_retaddr(); 1132 } 1133 1134 void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr, 1135 uint64_t val, uintptr_t retaddr) 1136 { 1137 set_helper_retaddr(retaddr); 1138 cpu_stq_be_data(env, ptr, val); 1139 clear_helper_retaddr(); 1140 } 1141 1142 void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr, 1143 uint32_t val, uintptr_t retaddr) 1144 { 1145 set_helper_retaddr(retaddr); 1146 cpu_stw_le_data(env, ptr, val); 1147 clear_helper_retaddr(); 1148 } 1149 1150 void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, 1151 uint32_t val, uintptr_t retaddr) 1152 { 1153 set_helper_retaddr(retaddr); 1154 cpu_stl_le_data(env, ptr, val); 1155 clear_helper_retaddr(); 1156 } 1157 1158 void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, 1159 uint64_t val, uintptr_t retaddr) 1160 { 1161 set_helper_retaddr(retaddr); 1162 cpu_stq_le_data(env, ptr, val); 1163 clear_helper_retaddr(); 1164 } 1165 1166 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) 1167 { 1168 uint32_t ret; 1169 1170 set_helper_retaddr(1); 1171 ret = ldub_p(g2h(ptr)); 1172 clear_helper_retaddr(); 1173 return ret; 1174 } 1175 1176 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr ptr) 1177 { 1178 uint32_t ret; 1179 1180 set_helper_retaddr(1); 1181 ret = lduw_p(g2h(ptr)); 1182 clear_helper_retaddr(); 1183 return ret; 1184 } 1185 1186 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr ptr) 1187 { 1188 uint32_t ret; 1189 1190 set_helper_retaddr(1); 1191 ret = ldl_p(g2h(ptr)); 1192 clear_helper_retaddr(); 1193 return ret; 1194 } 1195 1196 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) 1197 { 1198 uint64_t ret; 1199 1200 set_helper_retaddr(1); 1201 ret = ldq_p(g2h(ptr)); 1202 clear_helper_retaddr(); 1203 return ret; 1204 } 1205 1206 /* Do not allow unaligned operations to proceed. Return the host address. */ 1207 static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, 1208 int size, uintptr_t retaddr) 1209 { 1210 /* Enforce qemu required alignment. */ 1211 if (unlikely(addr & (size - 1))) { 1212 cpu_loop_exit_atomic(env_cpu(env), retaddr); 1213 } 1214 void *ret = g2h(addr); 1215 set_helper_retaddr(retaddr); 1216 return ret; 1217 } 1218 1219 /* Macro to call the above, with local variables from the use context. */ 1220 #define ATOMIC_MMU_DECLS do {} while (0) 1221 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC()) 1222 #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) 1223 #define ATOMIC_MMU_IDX MMU_USER_IDX 1224 1225 #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) 1226 #define EXTRA_ARGS 1227 1228 #include "atomic_common.c.inc" 1229 1230 #define DATA_SIZE 1 1231 #include "atomic_template.h" 1232 1233 #define DATA_SIZE 2 1234 #include "atomic_template.h" 1235 1236 #define DATA_SIZE 4 1237 #include "atomic_template.h" 1238 1239 #ifdef CONFIG_ATOMIC64 1240 #define DATA_SIZE 8 1241 #include "atomic_template.h" 1242 #endif 1243 1244 /* The following is only callable from other helpers, and matches up 1245 with the softmmu version. */ 1246 1247 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128 1248 1249 #undef EXTRA_ARGS 1250 #undef ATOMIC_NAME 1251 #undef ATOMIC_MMU_LOOKUP 1252 1253 #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr 1254 #define ATOMIC_NAME(X) \ 1255 HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) 1256 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr) 1257 1258 #define DATA_SIZE 16 1259 #include "atomic_template.h" 1260 #endif 1261