1 /* 2 * User emulator execution 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "disas/disas.h" 22 #include "exec/exec-all.h" 23 #include "tcg/tcg.h" 24 #include "qemu/bitops.h" 25 #include "exec/cpu_ldst.h" 26 #include "translate-all.h" 27 #include "exec/helper-proto.h" 28 #include "qemu/atomic128.h" 29 #include "trace-root.h" 30 #include "trace/mem.h" 31 32 #undef EAX 33 #undef ECX 34 #undef EDX 35 #undef EBX 36 #undef ESP 37 #undef EBP 38 #undef ESI 39 #undef EDI 40 #undef EIP 41 #ifdef __linux__ 42 #include <sys/ucontext.h> 43 #endif 44 45 __thread uintptr_t helper_retaddr; 46 47 //#define DEBUG_SIGNAL 48 49 /* exit the current TB from a signal handler. The host registers are 50 restored in a state compatible with the CPU emulator 51 */ 52 static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set) 53 { 54 /* XXX: use siglongjmp ? */ 55 sigprocmask(SIG_SETMASK, old_set, NULL); 56 cpu_loop_exit_noexc(cpu); 57 } 58 59 /* 'pc' is the host PC at which the exception was raised. 'address' is 60 the effective address of the memory exception. 'is_write' is 1 if a 61 write caused the exception and otherwise 0'. 'old_set' is the 62 signal set which should be restored */ 63 static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, 64 int is_write, sigset_t *old_set) 65 { 66 CPUState *cpu = current_cpu; 67 CPUClass *cc; 68 unsigned long address = (unsigned long)info->si_addr; 69 MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; 70 71 switch (helper_retaddr) { 72 default: 73 /* 74 * Fault during host memory operation within a helper function. 75 * The helper's host return address, saved here, gives us a 76 * pointer into the generated code that will unwind to the 77 * correct guest pc. 78 */ 79 pc = helper_retaddr; 80 break; 81 82 case 0: 83 /* 84 * Fault during host memory operation within generated code. 85 * (Or, a unrelated bug within qemu, but we can't tell from here). 86 * 87 * We take the host pc from the signal frame. However, we cannot 88 * use that value directly. Within cpu_restore_state_from_tb, we 89 * assume PC comes from GETPC(), as used by the helper functions, 90 * so we adjust the address by -GETPC_ADJ to form an address that 91 * is within the call insn, so that the address does not accidentially 92 * match the beginning of the next guest insn. However, when the 93 * pc comes from the signal frame it points to the actual faulting 94 * host memory insn and not the return from a call insn. 95 * 96 * Therefore, adjust to compensate for what will be done later 97 * by cpu_restore_state_from_tb. 98 */ 99 pc += GETPC_ADJ; 100 break; 101 102 case 1: 103 /* 104 * Fault during host read for translation, or loosely, "execution". 105 * 106 * The guest pc is already pointing to the start of the TB for which 107 * code is being generated. If the guest translator manages the 108 * page crossings correctly, this is exactly the correct address 109 * (and if the translator doesn't handle page boundaries correctly 110 * there's little we can do about that here). Therefore, do not 111 * trigger the unwinder. 112 * 113 * Like tb_gen_code, release the memory lock before cpu_loop_exit. 114 */ 115 pc = 0; 116 access_type = MMU_INST_FETCH; 117 mmap_unlock(); 118 break; 119 } 120 121 /* For synchronous signals we expect to be coming from the vCPU 122 * thread (so current_cpu should be valid) and either from running 123 * code or during translation which can fault as we cross pages. 124 * 125 * If neither is true then something has gone wrong and we should 126 * abort rather than try and restart the vCPU execution. 127 */ 128 if (!cpu || !cpu->running) { 129 printf("qemu:%s received signal outside vCPU context @ pc=0x%" 130 PRIxPTR "\n", __func__, pc); 131 abort(); 132 } 133 134 #if defined(DEBUG_SIGNAL) 135 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 136 pc, address, is_write, *(unsigned long *)old_set); 137 #endif 138 /* XXX: locking issue */ 139 /* Note that it is important that we don't call page_unprotect() unless 140 * this is really a "write to nonwriteable page" fault, because 141 * page_unprotect() assumes that if it is called for an access to 142 * a page that's writeable this means we had two threads racing and 143 * another thread got there first and already made the page writeable; 144 * so we will retry the access. If we were to call page_unprotect() 145 * for some other kind of fault that should really be passed to the 146 * guest, we'd end up in an infinite loop of retrying the faulting 147 * access. 148 */ 149 if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR && 150 h2g_valid(address)) { 151 switch (page_unprotect(h2g(address), pc)) { 152 case 0: 153 /* Fault not caused by a page marked unwritable to protect 154 * cached translations, must be the guest binary's problem. 155 */ 156 break; 157 case 1: 158 /* Fault caused by protection of cached translation; TBs 159 * invalidated, so resume execution. Retain helper_retaddr 160 * for a possible second fault. 161 */ 162 return 1; 163 case 2: 164 /* Fault caused by protection of cached translation, and the 165 * currently executing TB was modified and must be exited 166 * immediately. Clear helper_retaddr for next execution. 167 */ 168 clear_helper_retaddr(); 169 cpu_exit_tb_from_sighandler(cpu, old_set); 170 /* NORETURN */ 171 172 default: 173 g_assert_not_reached(); 174 } 175 } 176 177 /* Convert forcefully to guest address space, invalid addresses 178 are still valid segv ones */ 179 address = h2g_nocheck(address); 180 181 /* 182 * There is no way the target can handle this other than raising 183 * an exception. Undo signal and retaddr state prior to longjmp. 184 */ 185 sigprocmask(SIG_SETMASK, old_set, NULL); 186 clear_helper_retaddr(); 187 188 cc = CPU_GET_CLASS(cpu); 189 cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); 190 g_assert_not_reached(); 191 } 192 193 static int probe_access_internal(CPUArchState *env, target_ulong addr, 194 int fault_size, MMUAccessType access_type, 195 bool nonfault, uintptr_t ra) 196 { 197 int flags; 198 199 switch (access_type) { 200 case MMU_DATA_STORE: 201 flags = PAGE_WRITE; 202 break; 203 case MMU_DATA_LOAD: 204 flags = PAGE_READ; 205 break; 206 case MMU_INST_FETCH: 207 flags = PAGE_EXEC; 208 break; 209 default: 210 g_assert_not_reached(); 211 } 212 213 if (!guest_addr_valid(addr) || page_check_range(addr, 1, flags) < 0) { 214 if (nonfault) { 215 return TLB_INVALID_MASK; 216 } else { 217 CPUState *cpu = env_cpu(env); 218 CPUClass *cc = CPU_GET_CLASS(cpu); 219 cc->tlb_fill(cpu, addr, fault_size, access_type, 220 MMU_USER_IDX, false, ra); 221 g_assert_not_reached(); 222 } 223 } 224 return 0; 225 } 226 227 int probe_access_flags(CPUArchState *env, target_ulong addr, 228 MMUAccessType access_type, int mmu_idx, 229 bool nonfault, void **phost, uintptr_t ra) 230 { 231 int flags; 232 233 flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra); 234 *phost = flags ? NULL : g2h(addr); 235 return flags; 236 } 237 238 void *probe_access(CPUArchState *env, target_ulong addr, int size, 239 MMUAccessType access_type, int mmu_idx, uintptr_t ra) 240 { 241 int flags; 242 243 g_assert(-(addr | TARGET_PAGE_MASK) >= size); 244 flags = probe_access_internal(env, addr, size, access_type, false, ra); 245 g_assert(flags == 0); 246 247 return size ? g2h(addr) : NULL; 248 } 249 250 #if defined(__i386__) 251 252 #if defined(__NetBSD__) 253 #include <ucontext.h> 254 255 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP]) 256 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 257 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 258 #define MASK_sig(context) ((context)->uc_sigmask) 259 #elif defined(__FreeBSD__) || defined(__DragonFly__) 260 #include <ucontext.h> 261 262 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip)) 263 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 264 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 265 #define MASK_sig(context) ((context)->uc_sigmask) 266 #elif defined(__OpenBSD__) 267 #define EIP_sig(context) ((context)->sc_eip) 268 #define TRAP_sig(context) ((context)->sc_trapno) 269 #define ERROR_sig(context) ((context)->sc_err) 270 #define MASK_sig(context) ((context)->sc_mask) 271 #else 272 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP]) 273 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 274 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 275 #define MASK_sig(context) ((context)->uc_sigmask) 276 #endif 277 278 int cpu_signal_handler(int host_signum, void *pinfo, 279 void *puc) 280 { 281 siginfo_t *info = pinfo; 282 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 283 ucontext_t *uc = puc; 284 #elif defined(__OpenBSD__) 285 struct sigcontext *uc = puc; 286 #else 287 ucontext_t *uc = puc; 288 #endif 289 unsigned long pc; 290 int trapno; 291 292 #ifndef REG_EIP 293 /* for glibc 2.1 */ 294 #define REG_EIP EIP 295 #define REG_ERR ERR 296 #define REG_TRAPNO TRAPNO 297 #endif 298 pc = EIP_sig(uc); 299 trapno = TRAP_sig(uc); 300 return handle_cpu_signal(pc, info, 301 trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 302 &MASK_sig(uc)); 303 } 304 305 #elif defined(__x86_64__) 306 307 #ifdef __NetBSD__ 308 #define PC_sig(context) _UC_MACHINE_PC(context) 309 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO]) 310 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR]) 311 #define MASK_sig(context) ((context)->uc_sigmask) 312 #elif defined(__OpenBSD__) 313 #define PC_sig(context) ((context)->sc_rip) 314 #define TRAP_sig(context) ((context)->sc_trapno) 315 #define ERROR_sig(context) ((context)->sc_err) 316 #define MASK_sig(context) ((context)->sc_mask) 317 #elif defined(__FreeBSD__) || defined(__DragonFly__) 318 #include <ucontext.h> 319 320 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip)) 321 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno) 322 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err) 323 #define MASK_sig(context) ((context)->uc_sigmask) 324 #else 325 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP]) 326 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO]) 327 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR]) 328 #define MASK_sig(context) ((context)->uc_sigmask) 329 #endif 330 331 int cpu_signal_handler(int host_signum, void *pinfo, 332 void *puc) 333 { 334 siginfo_t *info = pinfo; 335 unsigned long pc; 336 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__) 337 ucontext_t *uc = puc; 338 #elif defined(__OpenBSD__) 339 struct sigcontext *uc = puc; 340 #else 341 ucontext_t *uc = puc; 342 #endif 343 344 pc = PC_sig(uc); 345 return handle_cpu_signal(pc, info, 346 TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0, 347 &MASK_sig(uc)); 348 } 349 350 #elif defined(_ARCH_PPC) 351 352 /*********************************************************************** 353 * signal context platform-specific definitions 354 * From Wine 355 */ 356 #ifdef linux 357 /* All Registers access - only for local access */ 358 #define REG_sig(reg_name, context) \ 359 ((context)->uc_mcontext.regs->reg_name) 360 /* Gpr Registers access */ 361 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context) 362 /* Program counter */ 363 #define IAR_sig(context) REG_sig(nip, context) 364 /* Machine State Register (Supervisor) */ 365 #define MSR_sig(context) REG_sig(msr, context) 366 /* Count register */ 367 #define CTR_sig(context) REG_sig(ctr, context) 368 /* User's integer exception register */ 369 #define XER_sig(context) REG_sig(xer, context) 370 /* Link register */ 371 #define LR_sig(context) REG_sig(link, context) 372 /* Condition register */ 373 #define CR_sig(context) REG_sig(ccr, context) 374 375 /* Float Registers access */ 376 #define FLOAT_sig(reg_num, context) \ 377 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num]) 378 #define FPSCR_sig(context) \ 379 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4))) 380 /* Exception Registers access */ 381 #define DAR_sig(context) REG_sig(dar, context) 382 #define DSISR_sig(context) REG_sig(dsisr, context) 383 #define TRAP_sig(context) REG_sig(trap, context) 384 #endif /* linux */ 385 386 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 387 #include <ucontext.h> 388 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0) 389 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1) 390 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr) 391 #define XER_sig(context) ((context)->uc_mcontext.mc_xer) 392 #define LR_sig(context) ((context)->uc_mcontext.mc_lr) 393 #define CR_sig(context) ((context)->uc_mcontext.mc_cr) 394 /* Exception Registers access */ 395 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar) 396 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr) 397 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc) 398 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */ 399 400 int cpu_signal_handler(int host_signum, void *pinfo, 401 void *puc) 402 { 403 siginfo_t *info = pinfo; 404 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) 405 ucontext_t *uc = puc; 406 #else 407 ucontext_t *uc = puc; 408 #endif 409 unsigned long pc; 410 int is_write; 411 412 pc = IAR_sig(uc); 413 is_write = 0; 414 #if 0 415 /* ppc 4xx case */ 416 if (DSISR_sig(uc) & 0x00800000) { 417 is_write = 1; 418 } 419 #else 420 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) { 421 is_write = 1; 422 } 423 #endif 424 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 425 } 426 427 #elif defined(__alpha__) 428 429 int cpu_signal_handler(int host_signum, void *pinfo, 430 void *puc) 431 { 432 siginfo_t *info = pinfo; 433 ucontext_t *uc = puc; 434 uint32_t *pc = uc->uc_mcontext.sc_pc; 435 uint32_t insn = *pc; 436 int is_write = 0; 437 438 /* XXX: need kernel patch to get write flag faster */ 439 switch (insn >> 26) { 440 case 0x0d: /* stw */ 441 case 0x0e: /* stb */ 442 case 0x0f: /* stq_u */ 443 case 0x24: /* stf */ 444 case 0x25: /* stg */ 445 case 0x26: /* sts */ 446 case 0x27: /* stt */ 447 case 0x2c: /* stl */ 448 case 0x2d: /* stq */ 449 case 0x2e: /* stl_c */ 450 case 0x2f: /* stq_c */ 451 is_write = 1; 452 } 453 454 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 455 } 456 #elif defined(__sparc__) 457 458 int cpu_signal_handler(int host_signum, void *pinfo, 459 void *puc) 460 { 461 siginfo_t *info = pinfo; 462 int is_write; 463 uint32_t insn; 464 #if !defined(__arch64__) || defined(CONFIG_SOLARIS) 465 uint32_t *regs = (uint32_t *)(info + 1); 466 void *sigmask = (regs + 20); 467 /* XXX: is there a standard glibc define ? */ 468 unsigned long pc = regs[1]; 469 #else 470 #ifdef __linux__ 471 struct sigcontext *sc = puc; 472 unsigned long pc = sc->sigc_regs.tpc; 473 void *sigmask = (void *)sc->sigc_mask; 474 #elif defined(__OpenBSD__) 475 struct sigcontext *uc = puc; 476 unsigned long pc = uc->sc_pc; 477 void *sigmask = (void *)(long)uc->sc_mask; 478 #elif defined(__NetBSD__) 479 ucontext_t *uc = puc; 480 unsigned long pc = _UC_MACHINE_PC(uc); 481 void *sigmask = (void *)&uc->uc_sigmask; 482 #endif 483 #endif 484 485 /* XXX: need kernel patch to get write flag faster */ 486 is_write = 0; 487 insn = *(uint32_t *)pc; 488 if ((insn >> 30) == 3) { 489 switch ((insn >> 19) & 0x3f) { 490 case 0x05: /* stb */ 491 case 0x15: /* stba */ 492 case 0x06: /* sth */ 493 case 0x16: /* stha */ 494 case 0x04: /* st */ 495 case 0x14: /* sta */ 496 case 0x07: /* std */ 497 case 0x17: /* stda */ 498 case 0x0e: /* stx */ 499 case 0x1e: /* stxa */ 500 case 0x24: /* stf */ 501 case 0x34: /* stfa */ 502 case 0x27: /* stdf */ 503 case 0x37: /* stdfa */ 504 case 0x26: /* stqf */ 505 case 0x36: /* stqfa */ 506 case 0x25: /* stfsr */ 507 case 0x3c: /* casa */ 508 case 0x3e: /* casxa */ 509 is_write = 1; 510 break; 511 } 512 } 513 return handle_cpu_signal(pc, info, is_write, sigmask); 514 } 515 516 #elif defined(__arm__) 517 518 #if defined(__NetBSD__) 519 #include <ucontext.h> 520 #endif 521 522 int cpu_signal_handler(int host_signum, void *pinfo, 523 void *puc) 524 { 525 siginfo_t *info = pinfo; 526 #if defined(__NetBSD__) 527 ucontext_t *uc = puc; 528 #else 529 ucontext_t *uc = puc; 530 #endif 531 unsigned long pc; 532 int is_write; 533 534 #if defined(__NetBSD__) 535 pc = uc->uc_mcontext.__gregs[_REG_R15]; 536 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) 537 pc = uc->uc_mcontext.gregs[R15]; 538 #else 539 pc = uc->uc_mcontext.arm_pc; 540 #endif 541 542 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or 543 * later processor; on v5 we will always report this as a read). 544 */ 545 is_write = extract32(uc->uc_mcontext.error_code, 11, 1); 546 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 547 } 548 549 #elif defined(__aarch64__) 550 551 #ifndef ESR_MAGIC 552 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */ 553 #define ESR_MAGIC 0x45535201 554 struct esr_context { 555 struct _aarch64_ctx head; 556 uint64_t esr; 557 }; 558 #endif 559 560 static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) 561 { 562 return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; 563 } 564 565 static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) 566 { 567 return (struct _aarch64_ctx *)((char *)hdr + hdr->size); 568 } 569 570 int cpu_signal_handler(int host_signum, void *pinfo, void *puc) 571 { 572 siginfo_t *info = pinfo; 573 ucontext_t *uc = puc; 574 uintptr_t pc = uc->uc_mcontext.pc; 575 bool is_write; 576 struct _aarch64_ctx *hdr; 577 struct esr_context const *esrctx = NULL; 578 579 /* Find the esr_context, which has the WnR bit in it */ 580 for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) { 581 if (hdr->magic == ESR_MAGIC) { 582 esrctx = (struct esr_context const *)hdr; 583 break; 584 } 585 } 586 587 if (esrctx) { 588 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ 589 uint64_t esr = esrctx->esr; 590 is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; 591 } else { 592 /* 593 * Fall back to parsing instructions; will only be needed 594 * for really ancient (pre-3.16) kernels. 595 */ 596 uint32_t insn = *(uint32_t *)pc; 597 598 is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ 599 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ 600 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ 601 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ 602 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ 603 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ 604 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ 605 /* Ignore bits 10, 11 & 21, controlling indexing. */ 606 || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */ 607 || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */ 608 /* Ignore bits 23 & 24, controlling indexing. */ 609 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */ 610 } 611 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 612 } 613 614 #elif defined(__s390__) 615 616 int cpu_signal_handler(int host_signum, void *pinfo, 617 void *puc) 618 { 619 siginfo_t *info = pinfo; 620 ucontext_t *uc = puc; 621 unsigned long pc; 622 uint16_t *pinsn; 623 int is_write = 0; 624 625 pc = uc->uc_mcontext.psw.addr; 626 627 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead 628 of the normal 2 arguments. The 3rd argument contains the "int_code" 629 from the hardware which does in fact contain the is_write value. 630 The rt signal handler, as far as I can tell, does not give this value 631 at all. Not that we could get to it from here even if it were. */ 632 /* ??? This is not even close to complete, since it ignores all 633 of the read-modify-write instructions. */ 634 pinsn = (uint16_t *)pc; 635 switch (pinsn[0] >> 8) { 636 case 0x50: /* ST */ 637 case 0x42: /* STC */ 638 case 0x40: /* STH */ 639 is_write = 1; 640 break; 641 case 0xc4: /* RIL format insns */ 642 switch (pinsn[0] & 0xf) { 643 case 0xf: /* STRL */ 644 case 0xb: /* STGRL */ 645 case 0x7: /* STHRL */ 646 is_write = 1; 647 } 648 break; 649 case 0xe3: /* RXY format insns */ 650 switch (pinsn[2] & 0xff) { 651 case 0x50: /* STY */ 652 case 0x24: /* STG */ 653 case 0x72: /* STCY */ 654 case 0x70: /* STHY */ 655 case 0x8e: /* STPQ */ 656 case 0x3f: /* STRVH */ 657 case 0x3e: /* STRV */ 658 case 0x2f: /* STRVG */ 659 is_write = 1; 660 } 661 break; 662 } 663 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 664 } 665 666 #elif defined(__mips__) 667 668 int cpu_signal_handler(int host_signum, void *pinfo, 669 void *puc) 670 { 671 siginfo_t *info = pinfo; 672 ucontext_t *uc = puc; 673 greg_t pc = uc->uc_mcontext.pc; 674 int is_write; 675 676 /* XXX: compute is_write */ 677 is_write = 0; 678 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 679 } 680 681 #elif defined(__riscv) 682 683 int cpu_signal_handler(int host_signum, void *pinfo, 684 void *puc) 685 { 686 siginfo_t *info = pinfo; 687 ucontext_t *uc = puc; 688 greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; 689 uint32_t insn = *(uint32_t *)pc; 690 int is_write = 0; 691 692 /* Detect store by reading the instruction at the program 693 counter. Note: we currently only generate 32-bit 694 instructions so we thus only detect 32-bit stores */ 695 switch (((insn >> 0) & 0b11)) { 696 case 3: 697 switch (((insn >> 2) & 0b11111)) { 698 case 8: 699 switch (((insn >> 12) & 0b111)) { 700 case 0: /* sb */ 701 case 1: /* sh */ 702 case 2: /* sw */ 703 case 3: /* sd */ 704 case 4: /* sq */ 705 is_write = 1; 706 break; 707 default: 708 break; 709 } 710 break; 711 case 9: 712 switch (((insn >> 12) & 0b111)) { 713 case 2: /* fsw */ 714 case 3: /* fsd */ 715 case 4: /* fsq */ 716 is_write = 1; 717 break; 718 default: 719 break; 720 } 721 break; 722 default: 723 break; 724 } 725 } 726 727 /* Check for compressed instructions */ 728 switch (((insn >> 13) & 0b111)) { 729 case 7: 730 switch (insn & 0b11) { 731 case 0: /*c.sd */ 732 case 2: /* c.sdsp */ 733 is_write = 1; 734 break; 735 default: 736 break; 737 } 738 break; 739 case 6: 740 switch (insn & 0b11) { 741 case 0: /* c.sw */ 742 case 3: /* c.swsp */ 743 is_write = 1; 744 break; 745 default: 746 break; 747 } 748 break; 749 default: 750 break; 751 } 752 753 return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); 754 } 755 756 #else 757 758 #error host CPU specific signal handler needed 759 760 #endif 761 762 /* The softmmu versions of these helpers are in cputlb.c. */ 763 764 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr) 765 { 766 uint32_t ret; 767 uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, false); 768 769 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 770 ret = ldub_p(g2h(ptr)); 771 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 772 return ret; 773 } 774 775 int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr) 776 { 777 int ret; 778 uint16_t meminfo = trace_mem_get_info(MO_SB, MMU_USER_IDX, false); 779 780 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 781 ret = ldsb_p(g2h(ptr)); 782 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 783 return ret; 784 } 785 786 uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr) 787 { 788 uint32_t ret; 789 uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false); 790 791 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 792 ret = lduw_be_p(g2h(ptr)); 793 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 794 return ret; 795 } 796 797 int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr) 798 { 799 int ret; 800 uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false); 801 802 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 803 ret = ldsw_be_p(g2h(ptr)); 804 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 805 return ret; 806 } 807 808 uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr) 809 { 810 uint32_t ret; 811 uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false); 812 813 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 814 ret = ldl_be_p(g2h(ptr)); 815 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 816 return ret; 817 } 818 819 uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr) 820 { 821 uint64_t ret; 822 uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false); 823 824 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 825 ret = ldq_be_p(g2h(ptr)); 826 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 827 return ret; 828 } 829 830 uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr) 831 { 832 uint32_t ret; 833 uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false); 834 835 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 836 ret = lduw_le_p(g2h(ptr)); 837 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 838 return ret; 839 } 840 841 int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr) 842 { 843 int ret; 844 uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false); 845 846 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 847 ret = ldsw_le_p(g2h(ptr)); 848 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 849 return ret; 850 } 851 852 uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr) 853 { 854 uint32_t ret; 855 uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false); 856 857 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 858 ret = ldl_le_p(g2h(ptr)); 859 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 860 return ret; 861 } 862 863 uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr) 864 { 865 uint64_t ret; 866 uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false); 867 868 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 869 ret = ldq_le_p(g2h(ptr)); 870 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 871 return ret; 872 } 873 874 uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 875 { 876 uint32_t ret; 877 878 set_helper_retaddr(retaddr); 879 ret = cpu_ldub_data(env, ptr); 880 clear_helper_retaddr(); 881 return ret; 882 } 883 884 int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 885 { 886 int ret; 887 888 set_helper_retaddr(retaddr); 889 ret = cpu_ldsb_data(env, ptr); 890 clear_helper_retaddr(); 891 return ret; 892 } 893 894 uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 895 { 896 uint32_t ret; 897 898 set_helper_retaddr(retaddr); 899 ret = cpu_lduw_be_data(env, ptr); 900 clear_helper_retaddr(); 901 return ret; 902 } 903 904 int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 905 { 906 int ret; 907 908 set_helper_retaddr(retaddr); 909 ret = cpu_ldsw_be_data(env, ptr); 910 clear_helper_retaddr(); 911 return ret; 912 } 913 914 uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 915 { 916 uint32_t ret; 917 918 set_helper_retaddr(retaddr); 919 ret = cpu_ldl_be_data(env, ptr); 920 clear_helper_retaddr(); 921 return ret; 922 } 923 924 uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 925 { 926 uint64_t ret; 927 928 set_helper_retaddr(retaddr); 929 ret = cpu_ldq_be_data(env, ptr); 930 clear_helper_retaddr(); 931 return ret; 932 } 933 934 uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 935 { 936 uint32_t ret; 937 938 set_helper_retaddr(retaddr); 939 ret = cpu_lduw_le_data(env, ptr); 940 clear_helper_retaddr(); 941 return ret; 942 } 943 944 int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 945 { 946 int ret; 947 948 set_helper_retaddr(retaddr); 949 ret = cpu_ldsw_le_data(env, ptr); 950 clear_helper_retaddr(); 951 return ret; 952 } 953 954 uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 955 { 956 uint32_t ret; 957 958 set_helper_retaddr(retaddr); 959 ret = cpu_ldl_le_data(env, ptr); 960 clear_helper_retaddr(); 961 return ret; 962 } 963 964 uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) 965 { 966 uint64_t ret; 967 968 set_helper_retaddr(retaddr); 969 ret = cpu_ldq_le_data(env, ptr); 970 clear_helper_retaddr(); 971 return ret; 972 } 973 974 void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 975 { 976 uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, true); 977 978 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 979 stb_p(g2h(ptr), val); 980 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 981 } 982 983 void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 984 { 985 uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true); 986 987 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 988 stw_be_p(g2h(ptr), val); 989 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 990 } 991 992 void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 993 { 994 uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true); 995 996 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 997 stl_be_p(g2h(ptr), val); 998 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 999 } 1000 1001 void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val) 1002 { 1003 uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true); 1004 1005 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1006 stq_be_p(g2h(ptr), val); 1007 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1008 } 1009 1010 void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1011 { 1012 uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true); 1013 1014 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1015 stw_le_p(g2h(ptr), val); 1016 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1017 } 1018 1019 void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val) 1020 { 1021 uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true); 1022 1023 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1024 stl_le_p(g2h(ptr), val); 1025 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1026 } 1027 1028 void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val) 1029 { 1030 uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true); 1031 1032 trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo); 1033 stq_le_p(g2h(ptr), val); 1034 qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo); 1035 } 1036 1037 void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, 1038 uint32_t val, uintptr_t retaddr) 1039 { 1040 set_helper_retaddr(retaddr); 1041 cpu_stb_data(env, ptr, val); 1042 clear_helper_retaddr(); 1043 } 1044 1045 void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr, 1046 uint32_t val, uintptr_t retaddr) 1047 { 1048 set_helper_retaddr(retaddr); 1049 cpu_stw_be_data(env, ptr, val); 1050 clear_helper_retaddr(); 1051 } 1052 1053 void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr, 1054 uint32_t val, uintptr_t retaddr) 1055 { 1056 set_helper_retaddr(retaddr); 1057 cpu_stl_be_data(env, ptr, val); 1058 clear_helper_retaddr(); 1059 } 1060 1061 void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr, 1062 uint64_t val, uintptr_t retaddr) 1063 { 1064 set_helper_retaddr(retaddr); 1065 cpu_stq_be_data(env, ptr, val); 1066 clear_helper_retaddr(); 1067 } 1068 1069 void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr, 1070 uint32_t val, uintptr_t retaddr) 1071 { 1072 set_helper_retaddr(retaddr); 1073 cpu_stw_le_data(env, ptr, val); 1074 clear_helper_retaddr(); 1075 } 1076 1077 void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, 1078 uint32_t val, uintptr_t retaddr) 1079 { 1080 set_helper_retaddr(retaddr); 1081 cpu_stl_le_data(env, ptr, val); 1082 clear_helper_retaddr(); 1083 } 1084 1085 void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, 1086 uint64_t val, uintptr_t retaddr) 1087 { 1088 set_helper_retaddr(retaddr); 1089 cpu_stq_le_data(env, ptr, val); 1090 clear_helper_retaddr(); 1091 } 1092 1093 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) 1094 { 1095 uint32_t ret; 1096 1097 set_helper_retaddr(1); 1098 ret = ldub_p(g2h(ptr)); 1099 clear_helper_retaddr(); 1100 return ret; 1101 } 1102 1103 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr ptr) 1104 { 1105 uint32_t ret; 1106 1107 set_helper_retaddr(1); 1108 ret = lduw_p(g2h(ptr)); 1109 clear_helper_retaddr(); 1110 return ret; 1111 } 1112 1113 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr ptr) 1114 { 1115 uint32_t ret; 1116 1117 set_helper_retaddr(1); 1118 ret = ldl_p(g2h(ptr)); 1119 clear_helper_retaddr(); 1120 return ret; 1121 } 1122 1123 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) 1124 { 1125 uint64_t ret; 1126 1127 set_helper_retaddr(1); 1128 ret = ldq_p(g2h(ptr)); 1129 clear_helper_retaddr(); 1130 return ret; 1131 } 1132 1133 /* Do not allow unaligned operations to proceed. Return the host address. */ 1134 static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, 1135 int size, uintptr_t retaddr) 1136 { 1137 /* Enforce qemu required alignment. */ 1138 if (unlikely(addr & (size - 1))) { 1139 cpu_loop_exit_atomic(env_cpu(env), retaddr); 1140 } 1141 void *ret = g2h(addr); 1142 set_helper_retaddr(retaddr); 1143 return ret; 1144 } 1145 1146 /* Macro to call the above, with local variables from the use context. */ 1147 #define ATOMIC_MMU_DECLS do {} while (0) 1148 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC()) 1149 #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) 1150 #define ATOMIC_MMU_IDX MMU_USER_IDX 1151 1152 #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) 1153 #define EXTRA_ARGS 1154 1155 #include "atomic_common.inc.c" 1156 1157 #define DATA_SIZE 1 1158 #include "atomic_template.h" 1159 1160 #define DATA_SIZE 2 1161 #include "atomic_template.h" 1162 1163 #define DATA_SIZE 4 1164 #include "atomic_template.h" 1165 1166 #ifdef CONFIG_ATOMIC64 1167 #define DATA_SIZE 8 1168 #include "atomic_template.h" 1169 #endif 1170 1171 /* The following is only callable from other helpers, and matches up 1172 with the softmmu version. */ 1173 1174 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128 1175 1176 #undef EXTRA_ARGS 1177 #undef ATOMIC_NAME 1178 #undef ATOMIC_MMU_LOOKUP 1179 1180 #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr 1181 #define ATOMIC_NAME(X) \ 1182 HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) 1183 #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr) 1184 1185 #define DATA_SIZE 16 1186 #include "atomic_template.h" 1187 #endif 1188