1*33646c72SRichard Henderson /* 2*33646c72SRichard Henderson * softmmu size bounds 3*33646c72SRichard Henderson * SPDX-License-Identifier: LGPL-2.1-or-later 4*33646c72SRichard Henderson */ 5*33646c72SRichard Henderson 6*33646c72SRichard Henderson #ifndef ACCEL_TCG_TLB_BOUNDS_H 7*33646c72SRichard Henderson #define ACCEL_TCG_TLB_BOUNDS_H 8*33646c72SRichard Henderson 9*33646c72SRichard Henderson #define CPU_TLB_DYN_MIN_BITS 6 10*33646c72SRichard Henderson #define CPU_TLB_DYN_DEFAULT_BITS 8 11*33646c72SRichard Henderson 12*33646c72SRichard Henderson # if HOST_LONG_BITS == 32 13*33646c72SRichard Henderson /* Make sure we do not require a double-word shift for the TLB load */ 14*33646c72SRichard Henderson # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) 15*33646c72SRichard Henderson # else /* HOST_LONG_BITS == 64 */ 16*33646c72SRichard Henderson /* 17*33646c72SRichard Henderson * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == 18*33646c72SRichard Henderson * 2**34 == 16G of address space. This is roughly what one would expect a 19*33646c72SRichard Henderson * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel 20*33646c72SRichard Henderson * Skylake's Level-2 STLB has 16 1G entries. 21*33646c72SRichard Henderson * Also, make sure we do not size the TLB past the guest's address space. 22*33646c72SRichard Henderson */ 23*33646c72SRichard Henderson # ifdef TARGET_PAGE_BITS_VARY 24*33646c72SRichard Henderson # define CPU_TLB_DYN_MAX_BITS \ 25*33646c72SRichard Henderson MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 26*33646c72SRichard Henderson # else 27*33646c72SRichard Henderson # define CPU_TLB_DYN_MAX_BITS \ 28*33646c72SRichard Henderson MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 29*33646c72SRichard Henderson # endif 30*33646c72SRichard Henderson # endif 31*33646c72SRichard Henderson 32*33646c72SRichard Henderson #endif /* ACCEL_TCG_TLB_BOUNDS_H */ 33