1 /* 2 * QEMU TCG vCPU common functionality 3 * 4 * Functionality common to all TCG vCPU variants: mttcg, rr and icount. 5 * 6 * Copyright (c) 2003-2008 Fabrice Bellard 7 * Copyright (c) 2014 Red Hat Inc. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "sysemu/tcg.h" 30 #include "sysemu/replay.h" 31 #include "sysemu/cpu-timers.h" 32 #include "qemu/main-loop.h" 33 #include "qemu/guest-random.h" 34 #include "qemu/timer.h" 35 #include "exec/exec-all.h" 36 #include "exec/hwaddr.h" 37 #include "exec/tb-flush.h" 38 #include "exec/gdbstub.h" 39 40 #include "tcg-accel-ops.h" 41 #include "tcg-accel-ops-mttcg.h" 42 #include "tcg-accel-ops-rr.h" 43 #include "tcg-accel-ops-icount.h" 44 45 /* common functionality among all TCG variants */ 46 47 void tcg_cpu_init_cflags(CPUState *cpu, bool parallel) 48 { 49 uint32_t cflags; 50 51 /* 52 * Include the cluster number in the hash we use to look up TBs. 53 * This is important because a TB that is valid for one cluster at 54 * a given physical address and set of CPU flags is not necessarily 55 * valid for another: 56 * the two clusters may have different views of physical memory, or 57 * may have different CPU features (eg FPU present or absent). 58 */ 59 cflags = cpu->cluster_index << CF_CLUSTER_SHIFT; 60 61 cflags |= parallel ? CF_PARALLEL : 0; 62 cflags |= icount_enabled() ? CF_USE_ICOUNT : 0; 63 cpu->tcg_cflags |= cflags; 64 } 65 66 void tcg_cpus_destroy(CPUState *cpu) 67 { 68 cpu_thread_signal_destroyed(cpu); 69 } 70 71 int tcg_cpus_exec(CPUState *cpu) 72 { 73 int ret; 74 assert(tcg_enabled()); 75 cpu_exec_start(cpu); 76 ret = cpu_exec(cpu); 77 cpu_exec_end(cpu); 78 return ret; 79 } 80 81 /* mask must never be zero, except for A20 change call */ 82 void tcg_handle_interrupt(CPUState *cpu, int mask) 83 { 84 g_assert(qemu_mutex_iothread_locked()); 85 86 cpu->interrupt_request |= mask; 87 88 /* 89 * If called from iothread context, wake the target cpu in 90 * case its halted. 91 */ 92 if (!qemu_cpu_is_self(cpu)) { 93 qemu_cpu_kick(cpu); 94 } else { 95 qatomic_set(&cpu->neg.icount_decr.u16.high, -1); 96 } 97 } 98 99 static bool tcg_supports_guest_debug(void) 100 { 101 return true; 102 } 103 104 /* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */ 105 static inline int xlat_gdb_type(CPUState *cpu, int gdbtype) 106 { 107 static const int xlat[] = { 108 [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE, 109 [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ, 110 [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS, 111 }; 112 113 CPUClass *cc = CPU_GET_CLASS(cpu); 114 int cputype = xlat[gdbtype]; 115 116 if (cc->gdb_stop_before_watchpoint) { 117 cputype |= BP_STOP_BEFORE_ACCESS; 118 } 119 return cputype; 120 } 121 122 static int tcg_insert_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len) 123 { 124 CPUState *cpu; 125 int err = 0; 126 127 switch (type) { 128 case GDB_BREAKPOINT_SW: 129 case GDB_BREAKPOINT_HW: 130 CPU_FOREACH(cpu) { 131 err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); 132 if (err) { 133 break; 134 } 135 } 136 return err; 137 case GDB_WATCHPOINT_WRITE: 138 case GDB_WATCHPOINT_READ: 139 case GDB_WATCHPOINT_ACCESS: 140 CPU_FOREACH(cpu) { 141 err = cpu_watchpoint_insert(cpu, addr, len, 142 xlat_gdb_type(cpu, type), NULL); 143 if (err) { 144 break; 145 } 146 } 147 return err; 148 default: 149 return -ENOSYS; 150 } 151 } 152 153 static int tcg_remove_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len) 154 { 155 CPUState *cpu; 156 int err = 0; 157 158 switch (type) { 159 case GDB_BREAKPOINT_SW: 160 case GDB_BREAKPOINT_HW: 161 CPU_FOREACH(cpu) { 162 err = cpu_breakpoint_remove(cpu, addr, BP_GDB); 163 if (err) { 164 break; 165 } 166 } 167 return err; 168 case GDB_WATCHPOINT_WRITE: 169 case GDB_WATCHPOINT_READ: 170 case GDB_WATCHPOINT_ACCESS: 171 CPU_FOREACH(cpu) { 172 err = cpu_watchpoint_remove(cpu, addr, len, 173 xlat_gdb_type(cpu, type)); 174 if (err) { 175 break; 176 } 177 } 178 return err; 179 default: 180 return -ENOSYS; 181 } 182 } 183 184 static inline void tcg_remove_all_breakpoints(CPUState *cpu) 185 { 186 cpu_breakpoint_remove_all(cpu, BP_GDB); 187 cpu_watchpoint_remove_all(cpu, BP_GDB); 188 } 189 190 static void tcg_accel_ops_init(AccelOpsClass *ops) 191 { 192 if (qemu_tcg_mttcg_enabled()) { 193 ops->create_vcpu_thread = mttcg_start_vcpu_thread; 194 ops->kick_vcpu_thread = mttcg_kick_vcpu_thread; 195 ops->handle_interrupt = tcg_handle_interrupt; 196 } else { 197 ops->create_vcpu_thread = rr_start_vcpu_thread; 198 ops->kick_vcpu_thread = rr_kick_vcpu_thread; 199 200 if (icount_enabled()) { 201 ops->handle_interrupt = icount_handle_interrupt; 202 ops->get_virtual_clock = icount_get; 203 ops->get_elapsed_ticks = icount_get; 204 } else { 205 ops->handle_interrupt = tcg_handle_interrupt; 206 } 207 } 208 209 ops->supports_guest_debug = tcg_supports_guest_debug; 210 ops->insert_breakpoint = tcg_insert_breakpoint; 211 ops->remove_breakpoint = tcg_remove_breakpoint; 212 ops->remove_all_breakpoints = tcg_remove_all_breakpoints; 213 } 214 215 static void tcg_accel_ops_class_init(ObjectClass *oc, void *data) 216 { 217 AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); 218 219 ops->ops_init = tcg_accel_ops_init; 220 } 221 222 static const TypeInfo tcg_accel_ops_type = { 223 .name = ACCEL_OPS_NAME("tcg"), 224 225 .parent = TYPE_ACCEL_OPS, 226 .class_init = tcg_accel_ops_class_init, 227 .abstract = true, 228 }; 229 module_obj(ACCEL_OPS_NAME("tcg")); 230 231 static void tcg_accel_ops_register_types(void) 232 { 233 type_register_static(&tcg_accel_ops_type); 234 } 235 type_init(tcg_accel_ops_register_types); 236