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"verify_chip_mark_1", 1748 "01": "verify_chip_mark_1" 1749 }, 1750 "03": { 1751 "00": "verify_chip_mark_2", 1752 "01": "verify_chip_mark_2" 1753 }, 1754 "04": { 1755 "00": "verify_chip_mark_3", 1756 "01": "verify_chip_mark_3" 1757 }, 1758 "05": { 1759 "00": "verify_chip_mark_4", 1760 "01": "verify_chip_mark_4" 1761 }, 1762 "06": { 1763 "00": "verify_chip_mark_5", 1764 "01": "verify_chip_mark_5" 1765 }, 1766 "07": { 1767 "00": "verify_chip_mark_6", 1768 "01": "verify_chip_mark_6" 1769 }, 1770 "08": { 1771 "00": "verify_chip_mark_7", 1772 "01": "verify_chip_mark_7" 1773 }, 1774 "09": { 1775 "00": "mainline_nce_tce_handling", 1776 "01": "mainline_nce_tce_handling" 1777 }, 1778 "0a": { 1779 "00": "mainline_nce_tce_handling", 1780 "01": "mainline_nce_tce_handling" 1781 }, 1782 "0b": { 1783 "00": "level2_M_th_1", 1784 "01": "level2_M_th_1" 1785 }, 1786 "0c": { 1787 "00": "level2_M_th_1", 1788 "01": "level2_M_th_1" 1789 }, 1790 "0d": { 1791 "00": "level2_M_th_1", 1792 "01": "level2_M_th_1" 1793 }, 1794 "0e": { 1795 "00": "dimm0_H_mem_port0_L_th_1", 1796 "01": "dimm1_H_mem_port1_L_th_1", 1797 "flags": ["odp_data_corrupt_side_effect", "sue_source"] 1798 }, 1799 "0f": { 1800 "00": "mainline_ue_handling_0", 1801 "01": "mainline_ue_handling_1", 1802 "flags": ["odp_data_corrupt_side_effect", "sue_source"] 1803 }, 1804 "10": { 1805 "00": "dimm0_H_mem_port0_L_th_1", 1806 "01": "dimm1_H_mem_port1_L_th_1", 1807 "flags": ["sue_source"] 1808 }, 1809 "11": { 1810 "00": "dimm0_H_mem_port0_L_th_1", 1811 "01": "dimm1_H_mem_port1_L_th_1", 1812 "flags": ["odp_data_corrupt_side_effect", "sue_source"] 1813 }, 1814 "12": { 1815 "00": "mainline_iue_handling_0", 1816 "01": "mainline_iue_handling_1", 1817 "flags": ["sue_source", "odp_data_corrupt_side_effect"] 1818 }, 1819 "13": { 1820 "00": "dimm0_H_mem_port0_L_th_32perDay", 1821 "01": "dimm1_H_mem_port1_L_th_32perDay" 1822 }, 1823 "14": { 1824 "00": "memory_impe_handling_0", 1825 "01": "memory_impe_handling_1" 1826 }, 1827 "15": { 1828 "00": "level2_M_th_1", 1829 "01": "level2_M_th_1" 1830 }, 1831 "16": { 1832 "00": "level2_M_th_1", 1833 "01": "level2_M_th_1" 1834 }, 1835 "17": { 1836 "00": "level2_M_th_1", 1837 "01": "level2_M_th_1" 1838 }, 1839 "18": { 1840 "00": "level2_M_th_1", 1841 "01": "level2_M_th_1" 1842 }, 1843 "19": { 1844 "00": "level2_M_th_1", 1845 "01": "level2_M_th_1" 1846 }, 1847 "1a": { 1848 "00": "level2_M_th_1", 1849 "01": "level2_M_th_1" 1850 }, 1851 "1b": { 1852 "00": "level2_M_th_1", 1853 "01": "level2_M_th_1" 1854 }, 1855 "1c": { 1856 "00": "level2_M_th_1", 1857 "01": "level2_M_th_1" 1858 }, 1859 "1d": { 1860 "00": "level2_M_th_1", 1861 "01": "level2_M_th_1" 1862 }, 1863 "1e": { 1864 "00": "level2_M_th_1", 1865 "01": "level2_M_th_1" 1866 }, 1867 "1f": { 1868 "00": "level2_M_th_1", 1869 "01": "level2_M_th_1" 1870 }, 1871 "20": { 1872 "00": "level2_M_th_1", 1873 "01": "level2_M_th_1" 1874 }, 1875 "21": { 1876 "00": "level2_M_th_1", 1877 "01": "level2_M_th_1" 1878 }, 1879 "22": { 1880 "00": "dimm0_H_mem_port0_L_th_1", 1881 "01": "dimm1_H_mem_port1_L_th_1", 1882 "flags": ["odp_data_corrupt_side_effect", "sue_source"] 1883 }, 1884 "23": { 1885 "00": "level2_M_th_1", 1886 "01": "level2_M_th_1" 1887 }, 1888 "24": { 1889 "00": "dimm0_H_mem_port0_L_th_1", 1890 "01": "dimm1_H_mem_port1_L_th_1" 1891 }, 1892 "25": { 1893 "00": "dimm0_H_mem_port0_L_th_1", 1894 "01": "dimm1_H_mem_port1_L_th_1", 1895 "flags": ["odp_data_corrupt_side_effect", "sue_source"] 1896 }, 1897 "26": { 1898 "00": "maintenance_iue_handling_0", 1899 "01": "maintenance_iue_handling_1", 1900 "flags": ["sue_source", "odp_data_corrupt_side_effect"] 1901 }, 1902 "27": { 1903 "00": "dimm0_H_mem_port0_L_th_32perDay", 1904 "01": "dimm1_H_mem_port1_L_th_32perDay" 1905 }, 1906 "28": { 1907 "00": "memory_impe_handling_0", 1908 "01": "memory_impe_handling_1" 1909 }, 1910 "29": { 1911 "00": "mem_port0_M_th_32perDay", 1912 "01": "mem_port1_M_th_32perDay" 1913 }, 1914 "2a": { 1915 "00": "mem_port0_M_info_only", 1916 "01": "mem_port1_M_info_only" 1917 }, 1918 "2b": { 1919 "00": "mem_port0_M_th_1", 1920 "01": "mem_port1_M_th_1" 1921 }, 1922 "2c": { 1923 "00": "mem_port0_M_th_1", 1924 "01": "mem_port1_M_th_1", 1925 "flags": ["sue_source"] 1926 }, 1927 "2d": { 1928 "00": "mem_port0_M_th_1", 1929 "01": "mem_port1_M_th_1", 1930 "flags": ["sue_source"] 1931 }, 1932 "2e": { 1933 "00": "mem_port0_M_th_32perDay", 1934 "01": "mem_port1_M_th_32perDay" 1935 }, 1936 "2f": { 1937 "00": "mem_port0_M_th_32perDay", 1938 "01": "mem_port1_M_th_32perDay" 1939 }, 1940 "30": { 1941 "00": "mem_port0_M_th_1", 1942 "01": "mem_port1_M_th_1", 1943 "flags": ["sue_source"] 1944 }, 1945 "31": { 1946 "00": "mem_port0_M_th_1", 1947 "01": "mem_port1_M_th_1", 1948 "flags": ["sue_source"] 1949 }, 1950 "32": { 1951 "00": "level2_M_th_1", 1952 "01": "level2_M_th_1" 1953 }, 1954 "33": { 1955 "00": "level2_M_th_1", 1956 "01": "level2_M_th_1" 1957 }, 1958 "34": { 1959 "00": "level2_M_th_1", 1960 "01": "level2_M_th_1" 1961 }, 1962 "35": { 1963 "00": "level2_M_th_1", 1964 "01": "level2_M_th_1" 1965 }, 1966 "36": { 1967 "00": "mem_port0_M_th_1", 1968 "01": "mem_port1_M_th_1", 1969 "flags": ["sue_source"] 1970 }, 1971 "37": { 1972 "00": "level2_M_th_1", 1973 "01": "level2_M_th_1" 1974 }, 1975 "38": { 1976 "00": "level2_M_th_1", 1977 "01": "level2_M_th_1" 1978 }, 1979 "39": { 1980 "00": "level2_M_th_1", 1981 "01": "level2_M_th_1" 1982 }, 1983 "3a": { 1984 "00": "level2_M_th_1", 1985 "01": "level2_M_th_1" 1986 }, 1987 "3b": { 1988 "00": "level2_M_th_1", 1989 "01": "level2_M_th_1" 1990 }, 1991 "3c": { 1992 "00": "level2_M_th_1", 1993 "01": "level2_M_th_1" 1994 }, 1995 "3d": { 1996 "00": "level2_M_th_1", 1997 "01": "level2_M_th_1" 1998 }, 1999 "3e": { 2000 "00": "level2_M_th_1", 2001 "01": "level2_M_th_1" 2002 } 2003 } 2004 }, 2005 "units": { 2006 "dimm0": "mem_port0/dimm0", 2007 "dimm1": "mem_port1/dimm1", 2008 "mem_port0": "mem_port0", 2009 "mem_port1": "mem_port1" 2010 }, 2011 "version": 2 2012} 2013