1From b06a228a5fd1589fc9bed654b3288b321fc21aa1 Mon Sep 17 00:00:00 2001
2From: "Richard W.M. Jones" <rjones@redhat.com>
3Date: Sun, 20 Nov 2016 15:04:52 +0000
4Subject: [PATCH] Add support for RISC-V.
5
6The architecture is sufficiently similar to aarch64 that simply
7extending the existing aarch64 macro works.
8---
9 src/include/storage/s_lock.h | 5 +++--
10 1 file changed, 3 insertions(+), 2 deletions(-)
11
12diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h
13index 3fe29ce..7cd578f 100644
14--- a/src/include/storage/s_lock.h
15+++ b/src/include/storage/s_lock.h
16@@ -316,11 +316,12 @@ tas(volatile slock_t *lock)
17
18 /*
19  * On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available.
20+ * On RISC-V, the same.
21  *
22  * We use the int-width variant of the builtin because it works on more chips
23  * than other widths.
24  */
25-#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64)
26+#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) || defined(__riscv)
27 #ifdef HAVE_GCC__SYNC_INT32_TAS
28 #define HAS_TEST_AND_SET
29
30@@ -337,7 +338,7 @@ tas(volatile slock_t *lock)
31 #define S_UNLOCK(lock) __sync_lock_release(lock)
32
33 #endif	 /* HAVE_GCC__SYNC_INT32_TAS */
34-#endif	 /* __arm__ || __arm || __aarch64__ || __aarch64 */
35+#endif	 /* __arm__ || __arm || __aarch64__ || __aarch64 || __riscv */
36
37
38 /* S/390 and S/390x Linux (32- and 64-bit zSeries) */
39--
402.9.3
41
42