1*971257a7SLogananth SundararajFrom 1fb38f86a77ec6656f87f427124a65dc6c0fdf5f Mon Sep 17 00:00:00 2001 2*971257a7SLogananth SundararajFrom: Logananth Sundararaj <logananth_s@hcl.com> 3*971257a7SLogananth SundararajDate: Tue, 8 Mar 2022 19:24:49 +0530 4*971257a7SLogananth SundararajSubject: [PATCH] spl-host-console-handle 5*971257a7SLogananth Sundararaj 6*971257a7SLogananth SundararajThis patch adds four 1S server console through debug card 7*971257a7SLogananth Sundararajconnected to YosemiteV2 during boot. 8*971257a7SLogananth Sundararaj 9*971257a7SLogananth SundararajHandswitch in the adaptor card connected to AST2500 GPIOs as below, 10*971257a7SLogananth SundararajGPIOAA7 ---SW_ID8 11*971257a7SLogananth SundararajGPIOAA6 ---SW_ID4 12*971257a7SLogananth SundararajGPIOAA5 ---SW_ID2 13*971257a7SLogananth SundararajGPIOAA4 ---SW_ID1 14*971257a7SLogananth Sundararaj 15*971257a7SLogananth SundararajSW_ID8 SW_ID4 SW_ID2 SW_ID1 Position Descritpion 16*971257a7SLogananth SundararajL L L L 1 1s server slot1 select 17*971257a7SLogananth Sundararaj 18*971257a7SLogananth SundararajL L L H 2 1s server slot2 select 19*971257a7SLogananth Sundararaj 20*971257a7SLogananth SundararajL L H L 3 1s server slot3 select 21*971257a7SLogananth Sundararaj 22*971257a7SLogananth SundararajL L H H 4 1s server slot4 select 23*971257a7SLogananth Sundararaj 24*971257a7SLogananth SundararajL H L L 5 BMC Debug port select 25*971257a7SLogananth Sundararaj 26*971257a7SLogananth SundararajL H L H 6 1s server slot1 select 27*971257a7SLogananth Sundararaj 28*971257a7SLogananth SundararajL H H L 7 1s server slot2 select 29*971257a7SLogananth Sundararaj 30*971257a7SLogananth SundararajL H H H 8 1s server slot3 select 31*971257a7SLogananth Sundararaj 32*971257a7SLogananth SundararajH L L L 9 1s server slot4 select 33*971257a7SLogananth Sundararaj 34*971257a7SLogananth SundararajH L L H 10 BMC Debug port select 35*971257a7SLogananth Sundararaj 36*971257a7SLogananth SundararajBMC and Hosts UART control flow 37*971257a7SLogananth SundararajGPIOE0 --- DEBUG_UART_SEL_0 38*971257a7SLogananth SundararajGPIOE1 --- DEBUG_UART_SEL_1 39*971257a7SLogananth SundararajGPIOE2 --- DEBUG_UART_SEL_2 40*971257a7SLogananth SundararajGPIOE2 --- DEBUG_UART_RX_SEL_N 41*971257a7SLogananth Sundararaj 42*971257a7SLogananth SundararajSEL_2 SEL_1 SEL_0 RX_SEL_N CONSOLE 43*971257a7SLogananth Sundararaj0 0 0 0 SLOT1 44*971257a7SLogananth Sundararaj0 0 1 0 SLOT2 45*971257a7SLogananth Sundararaj0 1 0 0 SLOT3 46*971257a7SLogananth Sundararaj0 1 1 0 SLOT4 47*971257a7SLogananth Sundararaj1 0 0 1 BMC Debug 48*971257a7SLogananth Sundararaj 49*971257a7SLogananth SundararajSigned-off-by: Logananth Sundararaj <logananth_s@hcl.com> 50*971257a7SLogananth Sundararaj--- 51*971257a7SLogananth Sundararaj arch/arm/mach-aspeed/ast2500/platform.S | 69 ++++++++++++++++++++++--- 52*971257a7SLogananth Sundararaj 1 file changed, 61 insertions(+), 8 deletions(-) 53*971257a7SLogananth Sundararaj 54*971257a7SLogananth Sundararajdiff --git a/arch/arm/mach-aspeed/ast2500/platform.S b/arch/arm/mach-aspeed/ast2500/platform.S 55*971257a7SLogananth Sundararajindex 137ed2c587..76a31c709a 100644 56*971257a7SLogananth Sundararaj--- a/arch/arm/mach-aspeed/ast2500/platform.S 57*971257a7SLogananth Sundararaj+++ b/arch/arm/mach-aspeed/ast2500/platform.S 58*971257a7SLogananth Sundararaj@@ -315,6 +315,59 @@ TIME_TABLE_DDR4_1600: 59*971257a7SLogananth Sundararaj str r1, [r0] 60*971257a7SLogananth Sundararaj .endm 61*971257a7SLogananth Sundararaj 62*971257a7SLogananth Sundararaj+ .macro console_slot1 63*971257a7SLogananth Sundararaj+ ldr r0, =0x1e780024 64*971257a7SLogananth Sundararaj+ ldr r1, [r0] 65*971257a7SLogananth Sundararaj+ orr r1, r1, #0xF 66*971257a7SLogananth Sundararaj+ str r1, [r0] 67*971257a7SLogananth Sundararaj+ 68*971257a7SLogananth Sundararaj+ ldr r0, =0x1e780020 69*971257a7SLogananth Sundararaj+ ldr r1, [r0] 70*971257a7SLogananth Sundararaj+ and r1, r1, #0xFFFFFFF0 71*971257a7SLogananth Sundararaj+ orr r1, r1, #0x0 72*971257a7SLogananth Sundararaj+ str r1, [r0] 73*971257a7SLogananth Sundararaj+ .endm 74*971257a7SLogananth Sundararaj+ 75*971257a7SLogananth Sundararaj+ .macro console_slot2 76*971257a7SLogananth Sundararaj+ ldr r0, =0x1e780024 77*971257a7SLogananth Sundararaj+ ldr r1, [r0] 78*971257a7SLogananth Sundararaj+ orr r1, r1, #0xF 79*971257a7SLogananth Sundararaj+ str r1, [r0] 80*971257a7SLogananth Sundararaj+ 81*971257a7SLogananth Sundararaj+ ldr r0, =0x1e780020 82*971257a7SLogananth Sundararaj+ ldr r1, [r0] 83*971257a7SLogananth Sundararaj+ and r1, r1, #0xFFFFFFF0 84*971257a7SLogananth Sundararaj+ orr r1, r1, #0x1 85*971257a7SLogananth Sundararaj+ str r1, [r0] 86*971257a7SLogananth Sundararaj+ .endm 87*971257a7SLogananth Sundararaj+ 88*971257a7SLogananth Sundararaj+ .macro console_slot3 89*971257a7SLogananth Sundararaj+ ldr r0, =0x1e780024 90*971257a7SLogananth Sundararaj+ ldr r1, [r0] 91*971257a7SLogananth Sundararaj+ orr r1, r1, #0xF 92*971257a7SLogananth Sundararaj+ str r1, [r0] 93*971257a7SLogananth Sundararaj+ 94*971257a7SLogananth Sundararaj+ ldr r0, =0x1e780020 95*971257a7SLogananth Sundararaj+ ldr r1, [r0] 96*971257a7SLogananth Sundararaj+ and r1, r1, #0xFFFFFFF0 97*971257a7SLogananth Sundararaj+ orr r1, r1, #0x2 98*971257a7SLogananth Sundararaj+ str r1, [r0] 99*971257a7SLogananth Sundararaj+ .endm 100*971257a7SLogananth Sundararaj+ 101*971257a7SLogananth Sundararaj+ .macro console_slot4 102*971257a7SLogananth Sundararaj+ ldr r0, =0x1e780024 103*971257a7SLogananth Sundararaj+ ldr r1, [r0] 104*971257a7SLogananth Sundararaj+ orr r1, r1, #0xF 105*971257a7SLogananth Sundararaj+ str r1, [r0] 106*971257a7SLogananth Sundararaj+ 107*971257a7SLogananth Sundararaj+ ldr r0, =0x1e780020 108*971257a7SLogananth Sundararaj+ ldr r1, [r0] 109*971257a7SLogananth Sundararaj+ and r1, r1, #0xFFFFFFF0 110*971257a7SLogananth Sundararaj+ orr r1, r1, #0x3 111*971257a7SLogananth Sundararaj+ str r1, [r0] 112*971257a7SLogananth Sundararaj+ .endm 113*971257a7SLogananth Sundararaj+ 114*971257a7SLogananth Sundararaj+ 115*971257a7SLogananth Sundararaj .macro console_sel 116*971257a7SLogananth Sundararaj 117*971257a7SLogananth Sundararaj // Disable SoL UARTs[1-4] 118*971257a7SLogananth Sundararaj@@ -354,28 +407,28 @@ dbg_card_pres\@: 119*971257a7SLogananth Sundararaj ldr r1, =0x00 120*971257a7SLogananth Sundararaj cmp r0, r1 121*971257a7SLogananth Sundararaj bne case_pos2\@ 122*971257a7SLogananth Sundararaj- console_bmc 123*971257a7SLogananth Sundararaj+ console_slot1 124*971257a7SLogananth Sundararaj b case_end\@ 125*971257a7SLogananth Sundararaj case_pos2\@: 126*971257a7SLogananth Sundararaj //Test for position#2 127*971257a7SLogananth Sundararaj ldr r1, =0x01 128*971257a7SLogananth Sundararaj cmp r0, r1 129*971257a7SLogananth Sundararaj bne case_pos3\@ 130*971257a7SLogananth Sundararaj- console_bmc 131*971257a7SLogananth Sundararaj+ console_slot2 132*971257a7SLogananth Sundararaj b case_end\@ 133*971257a7SLogananth Sundararaj case_pos3\@: 134*971257a7SLogananth Sundararaj //Test for position#3 135*971257a7SLogananth Sundararaj ldr r1, =0x02 136*971257a7SLogananth Sundararaj cmp r0, r1 137*971257a7SLogananth Sundararaj bne case_pos4\@ 138*971257a7SLogananth Sundararaj- console_bmc 139*971257a7SLogananth Sundararaj+ console_slot3 140*971257a7SLogananth Sundararaj b case_end\@ 141*971257a7SLogananth Sundararaj case_pos4\@: 142*971257a7SLogananth Sundararaj //Test for position#4 143*971257a7SLogananth Sundararaj ldr r1, =0x03 144*971257a7SLogananth Sundararaj cmp r0, r1 145*971257a7SLogananth Sundararaj bne case_pos5\@ 146*971257a7SLogananth Sundararaj- console_bmc 147*971257a7SLogananth Sundararaj+ console_slot4 148*971257a7SLogananth Sundararaj b case_end\@ 149*971257a7SLogananth Sundararaj case_pos5\@: 150*971257a7SLogananth Sundararaj //Test for position#5 151*971257a7SLogananth Sundararaj@@ -389,28 +442,28 @@ case_pos6\@: 152*971257a7SLogananth Sundararaj ldr r1, =0x05 153*971257a7SLogananth Sundararaj cmp r0, r1 154*971257a7SLogananth Sundararaj bne case_pos7\@ 155*971257a7SLogananth Sundararaj- console_bmc 156*971257a7SLogananth Sundararaj+ console_slot1 157*971257a7SLogananth Sundararaj b case_end\@ 158*971257a7SLogananth Sundararaj case_pos7\@: 159*971257a7SLogananth Sundararaj //Test for position#7 160*971257a7SLogananth Sundararaj ldr r1, =0x06 161*971257a7SLogananth Sundararaj cmp r0, r1 162*971257a7SLogananth Sundararaj bne case_pos8\@ 163*971257a7SLogananth Sundararaj- console_bmc 164*971257a7SLogananth Sundararaj+ console_slot2 165*971257a7SLogananth Sundararaj b case_end\@ 166*971257a7SLogananth Sundararaj case_pos8\@: 167*971257a7SLogananth Sundararaj //Test for position#8 168*971257a7SLogananth Sundararaj ldr r1, =0x07 169*971257a7SLogananth Sundararaj cmp r0, r1 170*971257a7SLogananth Sundararaj bne case_pos9\@ 171*971257a7SLogananth Sundararaj- console_bmc 172*971257a7SLogananth Sundararaj+ console_slot3 173*971257a7SLogananth Sundararaj b case_end\@ 174*971257a7SLogananth Sundararaj case_pos9\@: 175*971257a7SLogananth Sundararaj //Test for position#9 176*971257a7SLogananth Sundararaj ldr r1, =0x08 177*971257a7SLogananth Sundararaj cmp r0, r1 178*971257a7SLogananth Sundararaj bne case_pos10\@ 179*971257a7SLogananth Sundararaj- console_bmc 180*971257a7SLogananth Sundararaj+ console_slot4 181*971257a7SLogananth Sundararaj b case_end\@ 182*971257a7SLogananth Sundararaj case_pos10\@: 183*971257a7SLogananth Sundararaj //Test for position#10 184*971257a7SLogananth Sundararaj-- 185*971257a7SLogananth Sundararaj2.17.1 186