1From 5a649c3dd0452eba0028c51546e2981e0b04de4f Mon Sep 17 00:00:00 2001
2From: Logananth Sundararaj <logananth_s@hcl.com>
3Date: Tue, 8 Mar 2022 19:18:27 +0530
4Subject: [PATCH] board-aspeed-Add-Mux-for-yosemitev2
5
6Signed-off-by: Logananth Sundararaj <logananth_s@hcl.com>
7---
8 arch/arm/mach-aspeed/ast2500/platform.S | 191 ++++++++++++++++++++----
9 1 file changed, 162 insertions(+), 29 deletions(-)
10
11diff --git a/arch/arm/mach-aspeed/ast2500/platform.S b/arch/arm/mach-aspeed/ast2500/platform.S
12index aef55c4a0a..137ed2c587 100644
13--- a/arch/arm/mach-aspeed/ast2500/platform.S
14+++ b/arch/arm/mach-aspeed/ast2500/platform.S
15@@ -302,6 +302,156 @@ TIME_TABLE_DDR4_1600:
16     ldr   r2, =0x00000800
17     .endm
18
19+    .macro console_bmc
20+    ldr r0, =0x1e780024
21+    ldr r1, [r0]
22+    orr r1, r1, #0xF
23+    str r1, [r0]
24+
25+    ldr r0, =0x1e780020
26+    ldr r1, [r0]
27+    and r1, r1, #0xFFFFFFF0
28+    orr r1, r1, #0xC
29+    str r1, [r0]
30+    .endm
31+
32+.macro console_sel
33+
34+  // Disable SoL UARTs[1-4]
35+  ldr r0, =0x1e6e2080
36+  ldr r1, [r0]
37+  ldr r2, =0xBFBFFFFF
38+  and r1, r1, r2
39+  str r1, [r0]
40+
41+  ldr r0, =0x1e6e2084
42+  ldr r1, [r0]
43+  and r1, r1, r2
44+  str r1, [r0]
45+  // Enable GPIOE[0-3] Tolerant
46+  ldr r0, =0x1e78003c
47+  ldr r1, [r0]
48+  orr r1, r1, #0xF
49+  str r1, [r0]
50+
51+  // Read debug card present
52+  ldr r2, =0x1e780080
53+  ldr r0, [r2]
54+  and r0, r0, #0x00000800
55+  ldr r1, =0x0800
56+  cmp r0, r1
57+  bne dbg_card_pres\@
58+  console_bmc
59+  b case_end\@
60+
61+dbg_card_pres\@:
62+  // Read key position
63+  ldr r2, =0x1e7801e0
64+  ldr r0, [r2]
65+  bic r1, r0, #0xFF0FFFFF
66+  mov r0, r1, lsr #20
67+  //Test for position#1
68+  ldr r1, =0x00
69+  cmp r0, r1
70+  bne case_pos2\@
71+ console_bmc
72+  b case_end\@
73+case_pos2\@:
74+ //Test for position#2
75+  ldr r1, =0x01
76+  cmp r0, r1
77+  bne case_pos3\@
78+ console_bmc
79+  b case_end\@
80+case_pos3\@:
81+ //Test for position#3
82+  ldr r1, =0x02
83+  cmp r0, r1
84+  bne case_pos4\@
85+  console_bmc
86+  b case_end\@
87+case_pos4\@:
88+//Test for position#4
89+  ldr r1, =0x03
90+  cmp r0, r1
91+  bne case_pos5\@
92+  console_bmc
93+  b case_end\@
94+case_pos5\@:
95+  //Test for position#5
96+  ldr r1, =0x04
97+  cmp r0, r1
98+  bne case_pos6\@
99+  console_bmc
100+  b case_end\@
101+case_pos6\@:
102+  //Test for position#6
103+  ldr r1, =0x05
104+  cmp r0, r1
105+  bne case_pos7\@
106+  console_bmc
107+  b case_end\@
108+case_pos7\@:
109+ //Test for position#7
110+   ldr r1, =0x06
111+   cmp r0, r1
112+   bne case_pos8\@
113+   console_bmc
114+   b case_end\@
115+case_pos8\@:
116+  //Test for position#8
117+   ldr r1, =0x07
118+   cmp r0, r1
119+   bne case_pos9\@
120+   console_bmc
121+   b case_end\@
122+case_pos9\@:
123+    //Test for position#9
124+   ldr r1, =0x08
125+   cmp r0, r1
126+   bne case_pos10\@
127+   console_bmc
128+   b case_end\@
129+case_pos10\@:
130+   //Test for position#10
131+   ldr r1, =0x09
132+   cmp r0, r1
133+   bne case_end\@
134+   console_bmc
135+   b case_end\@
136+case_end\@:
137+.endm
138+
139+    .macro uart_console_setup
140+    console_sel
141+    /* setup UART console */
142+    ldr   r0, =0x1E78400C
143+    mov   r1, #0x83
144+    str   r1, [r0]
145+
146+    ldr   r0, =0x1e6e202c
147+    ldr   r2, [r0]
148+    mov   r2, r2, lsr #12
149+    tst   r2, #0x01
150+    ldr   r0, =0x1E784000
151+    moveq r1, #0x1A                              @ Baudrate 57600
152+    movne r1, #0x02                              @ Baudrate 57600, div13
153+
154+    str   r1, [r0]
155+
156+    ldr   r0, =0x1E784004
157+    mov   r1, #0x00
158+    str   r1, [r0]
159+
160+    ldr   r0, =0x1E78400C
161+    mov   r1, #0x03
162+    str   r1, [r0]
163+
164+    ldr   r0, =0x1E784008
165+    mov   r1, #0x07
166+    str   r1, [r0]
167+    .endm
168+
169     .macro print_hex_char
170     and   r1, r1, #0xF
171     cmp   r1, #9
172@@ -321,6 +471,16 @@ init_dram:
173     /********************************************
174        Initial Reset Procedure : Begin
175      *******************************************/
176+    /* save into SRAM */
177+    ldr r0, =0x1e720200 /* vbs.uboot_exec_address */
178+    str r4, [r0]
179+
180+    uart_console_setup
181+
182+    ldr   r0, =0x1E720204
183+    mov   r1, #0x0
184+    str   r1, [r0]
185+
186     /* Clear AHB bus lock condition */
187     ldr   r0, =0x1e600000
188     ldr   r1, =0xAEED1A03
189@@ -794,6 +954,8 @@ wait_ddr_reset:
190     clear_delay_timer
191     /* end delay 10ms */
192
193+    uart_console_setup
194+
195 /* Debug - UART console message */
196 #ifdef CONFIG_DRAM_UART_TO_UART1
197     ldr   r0, =0x1e78909c                        @ route UART5 to UART Port1, 2016.08.29
198@@ -807,35 +969,6 @@ wait_ddr_reset:
199     str   r1, [r0]
200 #endif
201
202-    ldr   r0, =0x1e78400c
203-    mov   r1, #0x83
204-    str   r1, [r0]
205-
206-    ldr   r0, =0x1e6e202c
207-    ldr   r2, [r0]
208-    mov   r2, r2, lsr #12
209-    tst   r2, #0x01
210-    ldr   r0, =0x1e784000
211-    moveq r1, #0x0D                              @ Baudrate 115200
212-    movne r1, #0x01                              @ Baudrate 115200, div13
213-#ifdef CONFIG_DRAM_UART_38400
214-    moveq r1, #0x27                              @ Baudrate 38400
215-    movne r1, #0x03                              @ Baudrate 38400 , div13
216-#endif
217-    str   r1, [r0]
218-
219-    ldr   r0, =0x1e784004
220-    mov   r1, #0x00
221-    str   r1, [r0]
222-
223-    ldr   r0, =0x1e78400c
224-    mov   r1, #0x03
225-    str   r1, [r0]
226-
227-    ldr   r0, =0x1e784008
228-    mov   r1, #0x07
229-    str   r1, [r0]
230-
231     ldr   r0, =0x1e784000
232     mov   r1, #0x0D                              @ '\r'
233     str   r1, [r0]
234--
2352.17.1
236