1From 56f2afcd10e8404a3c4efed6277a005fc4099e48 Mon Sep 17 00:00:00 2001 2From: Vishnu Banavath <vishnu.banavath@arm.com> 3Date: Thu, 30 Jun 2022 18:36:26 +0100 4Subject: [PATCH] plat-n1sdp: add N1SDP platform support 5 6Upstream-Status: Pending [Not submitted to upstream yet] 7Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> 8 9These changes are to add N1SDP platform to optee-os 10 11Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> 12Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com> 13Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> 14--- 15 core/arch/arm/plat-n1sdp/conf.mk | 41 +++++++++++++++++ 16 core/arch/arm/plat-n1sdp/main.c | 53 ++++++++++++++++++++++ 17 core/arch/arm/plat-n1sdp/n1sdp_core_pos.S | 32 +++++++++++++ 18 core/arch/arm/plat-n1sdp/platform_config.h | 49 ++++++++++++++++++++ 19 core/arch/arm/plat-n1sdp/sub.mk | 3 ++ 20 5 files changed, 178 insertions(+) 21 create mode 100644 core/arch/arm/plat-n1sdp/conf.mk 22 create mode 100644 core/arch/arm/plat-n1sdp/main.c 23 create mode 100644 core/arch/arm/plat-n1sdp/n1sdp_core_pos.S 24 create mode 100644 core/arch/arm/plat-n1sdp/platform_config.h 25 create mode 100644 core/arch/arm/plat-n1sdp/sub.mk 26 27diff --git a/core/arch/arm/plat-n1sdp/conf.mk b/core/arch/arm/plat-n1sdp/conf.mk 28new file mode 100644 29index 000000000..3dc79fe20 30--- /dev/null 31+++ b/core/arch/arm/plat-n1sdp/conf.mk 32@@ -0,0 +1,41 @@ 33+include core/arch/arm/cpu/cortex-armv8-0.mk 34+ 35+CFG_DEBUG_INFO = y 36+CFG_TEE_CORE_LOG_LEVEL = 4 37+ 38+# Workaround 808870: Unconditional VLDM instructions might cause an 39+# alignment fault even though the address is aligned 40+# Either hard float must be disabled for AArch32 or strict alignment checks 41+# must be disabled 42+ifeq ($(CFG_SCTLR_ALIGNMENT_CHECK),y) 43+$(call force,CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT,y) 44+else 45+$(call force,CFG_SCTLR_ALIGNMENT_CHECK,n) 46+endif 47+ 48+CFG_ARM64_core ?= y 49+ 50+CFG_ARM_GICV3 = y 51+ 52+# ARM debugger needs this 53+platform-cflags-debug-info = -gdwarf-4 54+platform-aflags-debug-info = -gdwarf-4 55+ 56+CFG_CORE_SEL1_SPMC = y 57+CFG_WITH_ARM_TRUSTED_FW = y 58+ 59+$(call force,CFG_GIC,y) 60+$(call force,CFG_PL011,y) 61+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 62+ 63+CFG_CORE_HEAP_SIZE = 0x32000 # 200kb 64+ 65+CFG_TEE_CORE_NB_CORE = 4 66+CFG_TZDRAM_START ?= 0xDE000000 67+CFG_TZDRAM_SIZE ?= 0x02000000 68+ 69+CFG_SHMEM_START ?= 0x83000000 70+CFG_SHMEM_SIZE ?= 0x00210000 71+# DRAM1 is defined above 4G 72+$(call force,CFG_CORE_LARGE_PHYS_ADDR,y) 73+$(call force,CFG_CORE_ARM64_PA_BITS,36) 74diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c 75new file mode 100644 76index 000000000..38212d84c 77--- /dev/null 78+++ b/core/arch/arm/plat-n1sdp/main.c 79@@ -0,0 +1,53 @@ 80+// SPDX-License-Identifier: BSD-2-Clause 81+/* 82+ * Copyright (c) 2022, Arm Limited. 83+ */ 84+ 85+#include <arm.h> 86+#include <console.h> 87+#include <drivers/gic.h> 88+#include <drivers/pl011.h> 89+#include <drivers/tzc400.h> 90+#include <initcall.h> 91+#include <keep.h> 92+#include <kernel/boot.h> 93+#include <kernel/interrupt.h> 94+#include <kernel/misc.h> 95+#include <kernel/notif.h> 96+#include <kernel/panic.h> 97+#include <kernel/spinlock.h> 98+#include <kernel/tee_time.h> 99+#include <mm/core_memprot.h> 100+#include <mm/core_mmu.h> 101+#include <platform_config.h> 102+#include <sm/psci.h> 103+#include <stdint.h> 104+#include <string.h> 105+#include <trace.h> 106+ 107+static struct pl011_data console_data __nex_bss; 108+ 109+register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 110+ 111+register_ddr(DRAM0_BASE, DRAM0_SIZE); 112+ 113+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 114+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 115+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE); 116+ 117+void main_init_gic(void) 118+{ 119+ gic_init(GICC_BASE, GICD_BASE); 120+} 121+ 122+void main_secondary_init_gic(void) 123+{ 124+ gic_init_per_cpu(); 125+} 126+ 127+void console_init(void) 128+{ 129+ pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 130+ CONSOLE_BAUDRATE); 131+ register_serial_console(&console_data.chip); 132+} 133diff --git a/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S b/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S 134new file mode 100644 135index 000000000..439d4e675 136--- /dev/null 137+++ b/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S 138@@ -0,0 +1,32 @@ 139+/* SPDX-License-Identifier: BSD-2-Clause */ 140+/* 141+ * Copyright (c) 2022, Arm Limited 142+ */ 143+ 144+#include <asm.S> 145+#include <arm.h> 146+#include "platform_config.h" 147+ 148+FUNC get_core_pos_mpidr , : 149+ mov x4, x0 150+ 151+ /* 152+ * The MT bit in MPIDR is always set for n1sdp and the 153+ * affinity level 0 corresponds to thread affinity level. 154+ */ 155+ 156+ /* Extract individual affinity fields from MPIDR */ 157+ ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 158+ ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 159+ ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 160+ ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS 161+ 162+ /* Compute linear position */ 163+ mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP 164+ madd x2, x3, x4, x2 165+ mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER 166+ madd x1, x2, x4, x1 167+ mov x4, #N1SDP_MAX_PE_PER_CPU 168+ madd x0, x1, x4, x0 169+ ret 170+END_FUNC get_core_pos_mpidr 171diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h 172new file mode 100644 173index 000000000..81b994091 174--- /dev/null 175+++ b/core/arch/arm/plat-n1sdp/platform_config.h 176@@ -0,0 +1,49 @@ 177+/* SPDX-License-Identifier: BSD-2-Clause */ 178+/* 179+ * Copyright (c) 2022, Arm Limited 180+ */ 181+ 182+#ifndef PLATFORM_CONFIG_H 183+#define PLATFORM_CONFIG_H 184+ 185+#include <mm/generic_ram_layout.h> 186+#include <stdint.h> 187+ 188+/* Make stacks aligned to data cache line length */ 189+#define STACK_ALIGNMENT 64 190+ 191+ /* N1SDP topology related constants */ 192+#define N1SDP_MAX_CPUS_PER_CLUSTER U(2) 193+#define PLAT_ARM_CLUSTER_COUNT U(2) 194+#define PLAT_N1SDP_CHIP_COUNT U(2) 195+#define N1SDP_MAX_CLUSTERS_PER_CHIP U(2) 196+#define N1SDP_MAX_PE_PER_CPU U(1) 197+ 198+#define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \ 199+ PLAT_ARM_CLUSTER_COUNT * \ 200+ N1SDP_MAX_CPUS_PER_CLUSTER * \ 201+ N1SDP_MAX_PE_PER_CPU) 202+ 203+#define GIC_BASE 0x2c010000 204+ 205+#define UART1_BASE 0x1C0A0000 206+#define UART1_CLK_IN_HZ 24000000 /*24MHz*/ 207+ 208+#define CONSOLE_UART_BASE UART1_BASE 209+#define CONSOLE_UART_CLK_IN_HZ UART1_CLK_IN_HZ 210+ 211+#define DRAM0_BASE 0x80000000 212+#define DRAM0_SIZE 0x80000000 213+ 214+#define GICD_BASE 0x30000000 215+#define GICC_BASE 0x2C000000 216+#define GICR_BASE 0x300C0000 217+ 218+#ifndef UART_BAUDRATE 219+#define UART_BAUDRATE 115200 220+#endif 221+#ifndef CONSOLE_BAUDRATE 222+#define CONSOLE_BAUDRATE UART_BAUDRATE 223+#endif 224+ 225+#endif /*PLATFORM_CONFIG_H*/ 226diff --git a/core/arch/arm/plat-n1sdp/sub.mk b/core/arch/arm/plat-n1sdp/sub.mk 227new file mode 100644 228index 000000000..a0b49da14 229--- /dev/null 230+++ b/core/arch/arm/plat-n1sdp/sub.mk 231@@ -0,0 +1,3 @@ 232+global-incdirs-y += . 233+srcs-y += main.c 234+srcs-y += n1sdp_core_pos.S 235-- 2362.25.1 237 238