1 // SPDX-License-Identifier: GPL-2.0+ 2 3 /* 4 * Copyright 2018 IBM Corporation. 5 */ 6 7 #define __SANE_USERSPACE_TYPES__ 8 9 #include <sys/types.h> 10 #include <stdint.h> 11 #include <malloc.h> 12 #include <unistd.h> 13 #include <signal.h> 14 #include <stdlib.h> 15 #include <string.h> 16 #include <stdio.h> 17 #include "utils.h" 18 19 #define CACHELINE_SIZE 128 20 21 struct perf_event_read { 22 __u64 nr; 23 __u64 l1d_misses; 24 }; 25 26 static inline __u64 load(void *addr) 27 { 28 __u64 tmp; 29 30 asm volatile("ld %0,0(%1)" : "=r"(tmp) : "b"(addr)); 31 32 return tmp; 33 } 34 35 static void syscall_loop(char *p, unsigned long iterations, 36 unsigned long zero_size) 37 { 38 for (unsigned long i = 0; i < iterations; i++) { 39 for (unsigned long j = 0; j < zero_size; j += CACHELINE_SIZE) 40 load(p + j); 41 getppid(); 42 } 43 } 44 45 static void sigill_handler(int signr, siginfo_t *info, void *unused) 46 { 47 static int warned; 48 ucontext_t *ctx = (ucontext_t *)unused; 49 unsigned long *pc = &UCONTEXT_NIA(ctx); 50 51 /* mtspr 3,RS to check for move to DSCR below */ 52 if ((*((unsigned int *)*pc) & 0xfc1fffff) == 0x7c0303a6) { 53 if (!warned++) 54 printf("WARNING: Skipping over dscr setup. Consider running 'ppc64_cpu --dscr=1' manually.\n"); 55 *pc += 4; 56 } else { 57 printf("SIGILL at %p\n", pc); 58 abort(); 59 } 60 } 61 62 static void set_dscr(unsigned long val) 63 { 64 static int init; 65 struct sigaction sa; 66 67 if (!init) { 68 memset(&sa, 0, sizeof(sa)); 69 sa.sa_sigaction = sigill_handler; 70 sa.sa_flags = SA_SIGINFO; 71 if (sigaction(SIGILL, &sa, NULL)) 72 perror("sigill_handler"); 73 init = 1; 74 } 75 76 asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR)); 77 } 78 79 int entry_flush_test(void) 80 { 81 char *p; 82 int repetitions = 10; 83 int fd, passes = 0, iter, rc = 0; 84 struct perf_event_read v; 85 __u64 l1d_misses_total = 0; 86 unsigned long iterations = 100000, zero_size = 24 * 1024; 87 unsigned long l1d_misses_expected; 88 int rfi_flush_orig; 89 int entry_flush, entry_flush_orig; 90 91 SKIP_IF(geteuid() != 0); 92 93 // The PMU event we use only works on Power7 or later 94 SKIP_IF(!have_hwcap(PPC_FEATURE_ARCH_2_06)); 95 96 if (read_debugfs_file("powerpc/rfi_flush", &rfi_flush_orig) < 0) { 97 perror("Unable to read powerpc/rfi_flush debugfs file"); 98 SKIP_IF(1); 99 } 100 101 if (read_debugfs_file("powerpc/entry_flush", &entry_flush_orig) < 0) { 102 perror("Unable to read powerpc/entry_flush debugfs file"); 103 SKIP_IF(1); 104 } 105 106 if (rfi_flush_orig != 0) { 107 if (write_debugfs_file("powerpc/rfi_flush", 0) < 0) { 108 perror("error writing to powerpc/rfi_flush debugfs file"); 109 FAIL_IF(1); 110 } 111 } 112 113 entry_flush = entry_flush_orig; 114 115 fd = perf_event_open_counter(PERF_TYPE_RAW, /* L1d miss */ 0x400f0, -1); 116 FAIL_IF(fd < 0); 117 118 p = (char *)memalign(zero_size, CACHELINE_SIZE); 119 120 FAIL_IF(perf_event_enable(fd)); 121 122 // disable L1 prefetching 123 set_dscr(1); 124 125 iter = repetitions; 126 127 /* 128 * We expect to see l1d miss for each cacheline access when entry_flush 129 * is set. Allow a small variation on this. 130 */ 131 l1d_misses_expected = iterations * (zero_size / CACHELINE_SIZE - 2); 132 133 again: 134 FAIL_IF(perf_event_reset(fd)); 135 136 syscall_loop(p, iterations, zero_size); 137 138 FAIL_IF(read(fd, &v, sizeof(v)) != sizeof(v)); 139 140 if (entry_flush && v.l1d_misses >= l1d_misses_expected) 141 passes++; 142 else if (!entry_flush && v.l1d_misses < (l1d_misses_expected / 2)) 143 passes++; 144 145 l1d_misses_total += v.l1d_misses; 146 147 while (--iter) 148 goto again; 149 150 if (passes < repetitions) { 151 printf("FAIL (L1D misses with entry_flush=%d: %llu %c %lu) [%d/%d failures]\n", 152 entry_flush, l1d_misses_total, entry_flush ? '<' : '>', 153 entry_flush ? repetitions * l1d_misses_expected : 154 repetitions * l1d_misses_expected / 2, 155 repetitions - passes, repetitions); 156 rc = 1; 157 } else { 158 printf("PASS (L1D misses with entry_flush=%d: %llu %c %lu) [%d/%d pass]\n", 159 entry_flush, l1d_misses_total, entry_flush ? '>' : '<', 160 entry_flush ? repetitions * l1d_misses_expected : 161 repetitions * l1d_misses_expected / 2, 162 passes, repetitions); 163 } 164 165 if (entry_flush == entry_flush_orig) { 166 entry_flush = !entry_flush_orig; 167 if (write_debugfs_file("powerpc/entry_flush", entry_flush) < 0) { 168 perror("error writing to powerpc/entry_flush debugfs file"); 169 return 1; 170 } 171 iter = repetitions; 172 l1d_misses_total = 0; 173 passes = 0; 174 goto again; 175 } 176 177 perf_event_disable(fd); 178 close(fd); 179 180 set_dscr(0); 181 182 if (write_debugfs_file("powerpc/rfi_flush", rfi_flush_orig) < 0) { 183 perror("unable to restore original value of powerpc/rfi_flush debugfs file"); 184 return 1; 185 } 186 187 if (write_debugfs_file("powerpc/entry_flush", entry_flush_orig) < 0) { 188 perror("unable to restore original value of powerpc/entry_flush debugfs file"); 189 return 1; 190 } 191 192 return rc; 193 } 194 195 int main(int argc, char *argv[]) 196 { 197 return test_harness(entry_flush_test, "entry_flush_test"); 198 } 199