1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2022, Athira Rajeev, IBM Corp. 4 * Copyright 2022, Madhavan Srinivasan, IBM Corp. 5 * Copyright 2022, Kajol Jain, IBM Corp. 6 */ 7 8 #include <unistd.h> 9 #include <sys/syscall.h> 10 #include <string.h> 11 #include <stdio.h> 12 #include <sys/ioctl.h> 13 #include <sys/mman.h> 14 #include <stdlib.h> 15 #include <ctype.h> 16 17 #include "misc.h" 18 19 #define PAGE_SIZE sysconf(_SC_PAGESIZE) 20 21 /* Storage for platform version */ 22 int pvr; 23 u64 platform_extended_mask; 24 25 /* Mask and Shift for Event code fields */ 26 int ev_mask_pmcxsel, ev_shift_pmcxsel; //pmcxsel field 27 int ev_mask_marked, ev_shift_marked; //marked filed 28 int ev_mask_comb, ev_shift_comb; //combine field 29 int ev_mask_unit, ev_shift_unit; //unit field 30 int ev_mask_pmc, ev_shift_pmc; //pmc field 31 int ev_mask_cache, ev_shift_cache; //Cache sel field 32 int ev_mask_sample, ev_shift_sample; //Random sampling field 33 int ev_mask_thd_sel, ev_shift_thd_sel; //thresh_sel field 34 int ev_mask_thd_start, ev_shift_thd_start; //thresh_start field 35 int ev_mask_thd_stop, ev_shift_thd_stop; //thresh_stop field 36 int ev_mask_thd_cmp, ev_shift_thd_cmp; //thresh cmp field 37 int ev_mask_sm, ev_shift_sm; //SDAR mode field 38 int ev_mask_rsq, ev_shift_rsq; //radix scope qual field 39 int ev_mask_l2l3, ev_shift_l2l3; //l2l3 sel field 40 int ev_mask_mmcr3_src, ev_shift_mmcr3_src; //mmcr3 field 41 42 static void init_ev_encodes(void) 43 { 44 ev_mask_pmcxsel = 0xff; 45 ev_shift_pmcxsel = 0; 46 ev_mask_marked = 1; 47 ev_shift_marked = 8; 48 ev_mask_unit = 0xf; 49 ev_shift_unit = 12; 50 ev_mask_pmc = 0xf; 51 ev_shift_pmc = 16; 52 ev_mask_sample = 0x1f; 53 ev_shift_sample = 24; 54 ev_mask_thd_sel = 0x7; 55 ev_shift_thd_sel = 29; 56 ev_mask_thd_start = 0xf; 57 ev_shift_thd_start = 36; 58 ev_mask_thd_stop = 0xf; 59 ev_shift_thd_stop = 32; 60 61 switch (pvr) { 62 case POWER10: 63 ev_mask_thd_cmp = 0x3ffff; 64 ev_shift_thd_cmp = 0; 65 ev_mask_rsq = 1; 66 ev_shift_rsq = 9; 67 ev_mask_comb = 3; 68 ev_shift_comb = 10; 69 ev_mask_cache = 3; 70 ev_shift_cache = 20; 71 ev_mask_sm = 0x3; 72 ev_shift_sm = 22; 73 ev_mask_l2l3 = 0x1f; 74 ev_shift_l2l3 = 40; 75 ev_mask_mmcr3_src = 0x7fff; 76 ev_shift_mmcr3_src = 45; 77 break; 78 case POWER9: 79 ev_mask_comb = 3; 80 ev_shift_comb = 10; 81 ev_mask_cache = 0xf; 82 ev_shift_cache = 20; 83 ev_mask_thd_cmp = 0x3ff; 84 ev_shift_thd_cmp = 40; 85 ev_mask_sm = 0x3; 86 ev_shift_sm = 50; 87 break; 88 default: 89 FAIL_IF_EXIT(1); 90 } 91 } 92 93 /* Return the extended regs mask value */ 94 static u64 perf_get_platform_reg_mask(void) 95 { 96 if (have_hwcap2(PPC_FEATURE2_ARCH_3_1)) 97 return PERF_POWER10_MASK; 98 if (have_hwcap2(PPC_FEATURE2_ARCH_3_00)) 99 return PERF_POWER9_MASK; 100 101 return -1; 102 } 103 104 int check_extended_regs_support(void) 105 { 106 int fd; 107 struct event event; 108 109 event_init(&event, 0x1001e); 110 111 event.attr.type = 4; 112 event.attr.sample_period = 1; 113 event.attr.disabled = 1; 114 event.attr.sample_type = PERF_SAMPLE_REGS_INTR; 115 event.attr.sample_regs_intr = platform_extended_mask; 116 117 fd = event_open(&event); 118 if (fd != -1) 119 return 0; 120 121 return -1; 122 } 123 124 int check_pvr_for_sampling_tests(void) 125 { 126 pvr = PVR_VER(mfspr(SPRN_PVR)); 127 128 platform_extended_mask = perf_get_platform_reg_mask(); 129 130 /* 131 * Check for supported platforms 132 * for sampling test 133 */ 134 if ((pvr != POWER10) && (pvr != POWER9)) 135 goto out; 136 137 /* 138 * Check PMU driver registered by looking for 139 * PPC_FEATURE2_EBB bit in AT_HWCAP2 140 */ 141 if (!have_hwcap2(PPC_FEATURE2_EBB)) 142 goto out; 143 144 /* check if platform supports extended regs */ 145 if (check_extended_regs_support()) 146 goto out; 147 148 init_ev_encodes(); 149 return 0; 150 out: 151 printf("%s: Sampling tests un-supported\n", __func__); 152 return -1; 153 } 154 /* 155 * Allocate mmap buffer of "mmap_pages" number of 156 * pages. 157 */ 158 void *event_sample_buf_mmap(int fd, int mmap_pages) 159 { 160 size_t page_size = sysconf(_SC_PAGESIZE); 161 size_t mmap_size; 162 void *buff; 163 164 if (mmap_pages <= 0) 165 return NULL; 166 167 if (fd <= 0) 168 return NULL; 169 170 mmap_size = page_size * (1 + mmap_pages); 171 buff = mmap(NULL, mmap_size, 172 PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); 173 174 if (buff == MAP_FAILED) { 175 perror("mmap() failed."); 176 return NULL; 177 } 178 return buff; 179 } 180 181 /* 182 * Post process the mmap buffer. 183 * - If sample_count != NULL then return count of total 184 * number of samples present in the mmap buffer. 185 * - If sample_count == NULL then return the address 186 * of first sample from the mmap buffer 187 */ 188 void *__event_read_samples(void *sample_buff, size_t *size, u64 *sample_count) 189 { 190 size_t page_size = sysconf(_SC_PAGESIZE); 191 struct perf_event_header *header = sample_buff + page_size; 192 struct perf_event_mmap_page *metadata_page = sample_buff; 193 unsigned long data_head, data_tail; 194 195 /* 196 * PERF_RECORD_SAMPLE: 197 * struct { 198 * struct perf_event_header hdr; 199 * u64 data[]; 200 * }; 201 */ 202 203 data_head = metadata_page->data_head; 204 /* sync memory before reading sample */ 205 mb(); 206 data_tail = metadata_page->data_tail; 207 208 /* Check for sample_count */ 209 if (sample_count) 210 *sample_count = 0; 211 212 while (1) { 213 /* 214 * Reads the mmap data buffer by moving 215 * the data_tail to know the last read data. 216 * data_head points to head in data buffer. 217 * refer "struct perf_event_mmap_page" in 218 * "include/uapi/linux/perf_event.h". 219 */ 220 if (data_head - data_tail < sizeof(header)) 221 return NULL; 222 223 data_tail += sizeof(header); 224 if (header->type == PERF_RECORD_SAMPLE) { 225 *size = (header->size - sizeof(header)); 226 if (!sample_count) 227 return sample_buff + page_size + data_tail; 228 data_tail += *size; 229 *sample_count += 1; 230 } else { 231 *size = (header->size - sizeof(header)); 232 if ((metadata_page->data_tail + *size) > metadata_page->data_head) 233 data_tail = metadata_page->data_head; 234 else 235 data_tail += *size; 236 } 237 header = (struct perf_event_header *)((void *)header + header->size); 238 } 239 return NULL; 240 } 241 242 int collect_samples(void *sample_buff) 243 { 244 u64 sample_count; 245 size_t size = 0; 246 247 __event_read_samples(sample_buff, &size, &sample_count); 248 return sample_count; 249 } 250 251 static void *perf_read_first_sample(void *sample_buff, size_t *size) 252 { 253 return __event_read_samples(sample_buff, size, NULL); 254 } 255 256 u64 *get_intr_regs(struct event *event, void *sample_buff) 257 { 258 u64 type = event->attr.sample_type; 259 u64 *intr_regs; 260 size_t size = 0; 261 262 if ((type ^ PERF_SAMPLE_REGS_INTR)) 263 return NULL; 264 265 intr_regs = (u64 *)perf_read_first_sample(sample_buff, &size); 266 if (!intr_regs) 267 return NULL; 268 269 /* 270 * First entry in the sample buffer used to specify 271 * PERF_SAMPLE_REGS_ABI_64, skip perf regs abi to access 272 * interrupt registers. 273 */ 274 ++intr_regs; 275 276 return intr_regs; 277 } 278 279 static const int __perf_reg_mask(const char *register_name) 280 { 281 if (!strcmp(register_name, "R0")) 282 return 0; 283 else if (!strcmp(register_name, "R1")) 284 return 1; 285 else if (!strcmp(register_name, "R2")) 286 return 2; 287 else if (!strcmp(register_name, "R3")) 288 return 3; 289 else if (!strcmp(register_name, "R4")) 290 return 4; 291 else if (!strcmp(register_name, "R5")) 292 return 5; 293 else if (!strcmp(register_name, "R6")) 294 return 6; 295 else if (!strcmp(register_name, "R7")) 296 return 7; 297 else if (!strcmp(register_name, "R8")) 298 return 8; 299 else if (!strcmp(register_name, "R9")) 300 return 9; 301 else if (!strcmp(register_name, "R10")) 302 return 10; 303 else if (!strcmp(register_name, "R11")) 304 return 11; 305 else if (!strcmp(register_name, "R12")) 306 return 12; 307 else if (!strcmp(register_name, "R13")) 308 return 13; 309 else if (!strcmp(register_name, "R14")) 310 return 14; 311 else if (!strcmp(register_name, "R15")) 312 return 15; 313 else if (!strcmp(register_name, "R16")) 314 return 16; 315 else if (!strcmp(register_name, "R17")) 316 return 17; 317 else if (!strcmp(register_name, "R18")) 318 return 18; 319 else if (!strcmp(register_name, "R19")) 320 return 19; 321 else if (!strcmp(register_name, "R20")) 322 return 20; 323 else if (!strcmp(register_name, "R21")) 324 return 21; 325 else if (!strcmp(register_name, "R22")) 326 return 22; 327 else if (!strcmp(register_name, "R23")) 328 return 23; 329 else if (!strcmp(register_name, "R24")) 330 return 24; 331 else if (!strcmp(register_name, "R25")) 332 return 25; 333 else if (!strcmp(register_name, "R26")) 334 return 26; 335 else if (!strcmp(register_name, "R27")) 336 return 27; 337 else if (!strcmp(register_name, "R28")) 338 return 28; 339 else if (!strcmp(register_name, "R29")) 340 return 29; 341 else if (!strcmp(register_name, "R30")) 342 return 30; 343 else if (!strcmp(register_name, "R31")) 344 return 31; 345 else if (!strcmp(register_name, "NIP")) 346 return 32; 347 else if (!strcmp(register_name, "MSR")) 348 return 33; 349 else if (!strcmp(register_name, "ORIG_R3")) 350 return 34; 351 else if (!strcmp(register_name, "CTR")) 352 return 35; 353 else if (!strcmp(register_name, "LINK")) 354 return 36; 355 else if (!strcmp(register_name, "XER")) 356 return 37; 357 else if (!strcmp(register_name, "CCR")) 358 return 38; 359 else if (!strcmp(register_name, "SOFTE")) 360 return 39; 361 else if (!strcmp(register_name, "TRAP")) 362 return 40; 363 else if (!strcmp(register_name, "DAR")) 364 return 41; 365 else if (!strcmp(register_name, "DSISR")) 366 return 42; 367 else if (!strcmp(register_name, "SIER")) 368 return 43; 369 else if (!strcmp(register_name, "MMCRA")) 370 return 44; 371 else if (!strcmp(register_name, "MMCR0")) 372 return 45; 373 else if (!strcmp(register_name, "MMCR1")) 374 return 46; 375 else if (!strcmp(register_name, "MMCR2")) 376 return 47; 377 else if (!strcmp(register_name, "MMCR3")) 378 return 48; 379 else if (!strcmp(register_name, "SIER2")) 380 return 49; 381 else if (!strcmp(register_name, "SIER3")) 382 return 50; 383 else if (!strcmp(register_name, "PMC1")) 384 return 51; 385 else if (!strcmp(register_name, "PMC2")) 386 return 52; 387 else if (!strcmp(register_name, "PMC3")) 388 return 53; 389 else if (!strcmp(register_name, "PMC4")) 390 return 54; 391 else if (!strcmp(register_name, "PMC5")) 392 return 55; 393 else if (!strcmp(register_name, "PMC6")) 394 return 56; 395 else if (!strcmp(register_name, "SDAR")) 396 return 57; 397 else if (!strcmp(register_name, "SIAR")) 398 return 58; 399 else 400 return -1; 401 } 402 403 u64 get_reg_value(u64 *intr_regs, char *register_name) 404 { 405 int register_bit_position; 406 407 register_bit_position = __perf_reg_mask(register_name); 408 409 if (register_bit_position < 0 || (!((platform_extended_mask >> 410 (register_bit_position - 1)) & 1))) 411 return -1; 412 413 return *(intr_regs + register_bit_position); 414 } 415 416 int get_thresh_cmp_val(struct event event) 417 { 418 int exp = 0; 419 u64 result = 0; 420 u64 value; 421 422 if (!have_hwcap2(PPC_FEATURE2_ARCH_3_1)) 423 return EV_CODE_EXTRACT(event.attr.config, thd_cmp); 424 425 value = EV_CODE_EXTRACT(event.attr.config1, thd_cmp); 426 427 if (!value) 428 return value; 429 430 /* 431 * Incase of P10, thresh_cmp value is not part of raw event code 432 * and provided via attr.config1 parameter. To program threshold in MMCRA, 433 * take a 18 bit number N and shift right 2 places and increment 434 * the exponent E by 1 until the upper 10 bits of N are zero. 435 * Write E to the threshold exponent and write the lower 8 bits of N 436 * to the threshold mantissa. 437 * The max threshold that can be written is 261120. 438 */ 439 if (value > 261120) 440 value = 261120; 441 while ((64 - __builtin_clzl(value)) > 8) { 442 exp++; 443 value >>= 2; 444 } 445 446 /* 447 * Note that it is invalid to write a mantissa with the 448 * upper 2 bits of mantissa being zero, unless the 449 * exponent is also zero. 450 */ 451 if (!(value & 0xC0) && exp) 452 result = -1; 453 else 454 result = (exp << 8) | value; 455 return result; 456 } 457