1*8eaca8c4SKajol Jain // SPDX-License-Identifier: GPL-2.0-only
2*8eaca8c4SKajol Jain /*
3*8eaca8c4SKajol Jain  * Copyright 2022, Kajol Jain, IBM Corp.
4*8eaca8c4SKajol Jain  */
5*8eaca8c4SKajol Jain 
6*8eaca8c4SKajol Jain #include <stdio.h>
7*8eaca8c4SKajol Jain #include <stdlib.h>
8*8eaca8c4SKajol Jain 
9*8eaca8c4SKajol Jain #include "../event.h"
10*8eaca8c4SKajol Jain #include "utils.h"
11*8eaca8c4SKajol Jain #include "../sampling_tests/misc.h"
12*8eaca8c4SKajol Jain 
13*8eaca8c4SKajol Jain /*
14*8eaca8c4SKajol Jain  * Primary PMU events used here is PM_MRK_INST_CMPL (0x401e0) and
15*8eaca8c4SKajol Jain  * PM_THRESH_MET (0x101ec)
16*8eaca8c4SKajol Jain  * Threshold event selection used is issue to complete for cycles
17*8eaca8c4SKajol Jain  * Sampling criteria is Load or Store only sampling
18*8eaca8c4SKajol Jain  */
19*8eaca8c4SKajol Jain #define p9_EventCode_1 0x13e35340401e0
20*8eaca8c4SKajol Jain #define p9_EventCode_2 0x17d34340101ec
21*8eaca8c4SKajol Jain #define p9_EventCode_3 0x13e35340101ec
22*8eaca8c4SKajol Jain #define p10_EventCode_1 0x35340401e0
23*8eaca8c4SKajol Jain #define p10_EventCode_2 0x35340101ec
24*8eaca8c4SKajol Jain 
25*8eaca8c4SKajol Jain /*
26*8eaca8c4SKajol Jain  * Testcase for group constraint check of thresh_cmp bits which is
27*8eaca8c4SKajol Jain  * used to program thresh compare field in Monitor Mode Control Register A
28*8eaca8c4SKajol Jain  * (MMCRA: 9-18 bits for power9 and MMCRA: 8-18 bits for power10).
29*8eaca8c4SKajol Jain  * All events in the group should match thresh compare bits otherwise
30*8eaca8c4SKajol Jain  * event_open for the group will fail.
31*8eaca8c4SKajol Jain  */
group_constraint_thresh_cmp(void)32*8eaca8c4SKajol Jain static int group_constraint_thresh_cmp(void)
33*8eaca8c4SKajol Jain {
34*8eaca8c4SKajol Jain 	struct event event, leader;
35*8eaca8c4SKajol Jain 
36*8eaca8c4SKajol Jain 	/* Check for platform support for the test */
37*8eaca8c4SKajol Jain 	SKIP_IF(platform_check_for_tests());
38*8eaca8c4SKajol Jain 
39*8eaca8c4SKajol Jain 	if (have_hwcap2(PPC_FEATURE2_ARCH_3_1)) {
40*8eaca8c4SKajol Jain 		/* Init the events for the group contraint check for thresh_cmp bits */
41*8eaca8c4SKajol Jain 		event_init(&leader, p10_EventCode_1);
42*8eaca8c4SKajol Jain 
43*8eaca8c4SKajol Jain 		/* Add the thresh_cmp value for leader in config1 */
44*8eaca8c4SKajol Jain 		leader.attr.config1 = 1000;
45*8eaca8c4SKajol Jain 		FAIL_IF(event_open(&leader));
46*8eaca8c4SKajol Jain 
47*8eaca8c4SKajol Jain 		event_init(&event, p10_EventCode_2);
48*8eaca8c4SKajol Jain 
49*8eaca8c4SKajol Jain 		/* Add the different thresh_cmp value from the leader event in config1 */
50*8eaca8c4SKajol Jain 		event.attr.config1 = 2000;
51*8eaca8c4SKajol Jain 
52*8eaca8c4SKajol Jain 		/* Expected to fail as sibling and leader event request different thresh_cmp bits */
53*8eaca8c4SKajol Jain 		FAIL_IF(!event_open_with_group(&event, leader.fd));
54*8eaca8c4SKajol Jain 
55*8eaca8c4SKajol Jain 		event_close(&event);
56*8eaca8c4SKajol Jain 
57*8eaca8c4SKajol Jain 		/* Init the event for the group contraint thresh compare test */
58*8eaca8c4SKajol Jain 		event_init(&event, p10_EventCode_2);
59*8eaca8c4SKajol Jain 
60*8eaca8c4SKajol Jain 		/* Add the same thresh_cmp value for leader and sibling event in config1 */
61*8eaca8c4SKajol Jain 		event.attr.config1 = 1000;
62*8eaca8c4SKajol Jain 
63*8eaca8c4SKajol Jain 		/* Expected to succeed as sibling and leader event request same thresh_cmp bits */
64*8eaca8c4SKajol Jain 		FAIL_IF(event_open_with_group(&event, leader.fd));
65*8eaca8c4SKajol Jain 
66*8eaca8c4SKajol Jain 		event_close(&leader);
67*8eaca8c4SKajol Jain 		event_close(&event);
68*8eaca8c4SKajol Jain 	} else {
69*8eaca8c4SKajol Jain 		/* Init the events for the group contraint check for thresh_cmp bits */
70*8eaca8c4SKajol Jain 		event_init(&leader, p9_EventCode_1);
71*8eaca8c4SKajol Jain 		FAIL_IF(event_open(&leader));
72*8eaca8c4SKajol Jain 
73*8eaca8c4SKajol Jain 		event_init(&event, p9_EventCode_2);
74*8eaca8c4SKajol Jain 
75*8eaca8c4SKajol Jain 		/* Expected to fail as sibling and leader event request different thresh_cmp bits */
76*8eaca8c4SKajol Jain 		FAIL_IF(!event_open_with_group(&event, leader.fd));
77*8eaca8c4SKajol Jain 
78*8eaca8c4SKajol Jain 		event_close(&event);
79*8eaca8c4SKajol Jain 
80*8eaca8c4SKajol Jain 		/* Init the event for the group contraint thresh compare test */
81*8eaca8c4SKajol Jain 		event_init(&event, p9_EventCode_3);
82*8eaca8c4SKajol Jain 
83*8eaca8c4SKajol Jain 		/* Expected to succeed as sibling and leader event request same thresh_cmp bits */
84*8eaca8c4SKajol Jain 		FAIL_IF(event_open_with_group(&event, leader.fd));
85*8eaca8c4SKajol Jain 
86*8eaca8c4SKajol Jain 		event_close(&leader);
87*8eaca8c4SKajol Jain 		event_close(&event);
88*8eaca8c4SKajol Jain 	}
89*8eaca8c4SKajol Jain 
90*8eaca8c4SKajol Jain 	return 0;
91*8eaca8c4SKajol Jain }
92*8eaca8c4SKajol Jain 
main(void)93*8eaca8c4SKajol Jain int main(void)
94*8eaca8c4SKajol Jain {
95*8eaca8c4SKajol Jain 	return test_harness(group_constraint_thresh_cmp, "group_constraint_thresh_cmp");
96*8eaca8c4SKajol Jain }
97