1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ucna_injection_test 4 * 5 * Copyright (C) 2022, Google LLC. 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2. 8 * 9 * Test that user space can inject UnCorrectable No Action required (UCNA) 10 * memory errors to the guest. 11 * 12 * The test starts one vCPU with the MCG_CMCI_P enabled. It verifies that 13 * proper UCNA errors can be injected to a vCPU with MCG_CMCI_P and 14 * corresponding per-bank control register (MCI_CTL2) bit enabled. 15 * The test also checks that the UCNA errors get recorded in the 16 * Machine Check bank registers no matter the error signal interrupts get 17 * delivered into the guest or not. 18 * 19 */ 20 21 #define _GNU_SOURCE /* for program_invocation_short_name */ 22 #include <pthread.h> 23 #include <inttypes.h> 24 #include <string.h> 25 #include <time.h> 26 27 #include "kvm_util_base.h" 28 #include "kvm_util.h" 29 #include "mce.h" 30 #include "processor.h" 31 #include "test_util.h" 32 #include "apic.h" 33 34 #define SYNC_FIRST_UCNA 9 35 #define SYNC_SECOND_UCNA 10 36 #define SYNC_GP 11 37 #define FIRST_UCNA_ADDR 0xdeadbeef 38 #define SECOND_UCNA_ADDR 0xcafeb0ba 39 40 /* 41 * Vector for the CMCI interrupt. 42 * Value is arbitrary. Any value in 0x20-0xFF should work: 43 * https://wiki.osdev.org/Interrupt_Vector_Table 44 */ 45 #define CMCI_VECTOR 0xa9 46 47 #define UCNA_BANK 0x7 // IMC0 bank 48 49 #define MCI_CTL2_RESERVED_BIT BIT_ULL(29) 50 51 static uint64_t supported_mcg_caps; 52 53 /* 54 * Record states about the injected UCNA. 55 * The variables started with the 'i_' prefixes are recorded in interrupt 56 * handler. Variables without the 'i_' prefixes are recorded in guest main 57 * execution thread. 58 */ 59 static volatile uint64_t i_ucna_rcvd; 60 static volatile uint64_t i_ucna_addr; 61 static volatile uint64_t ucna_addr; 62 static volatile uint64_t ucna_addr2; 63 64 struct thread_params { 65 struct kvm_vcpu *vcpu; 66 uint64_t *p_i_ucna_rcvd; 67 uint64_t *p_i_ucna_addr; 68 uint64_t *p_ucna_addr; 69 uint64_t *p_ucna_addr2; 70 }; 71 72 static void verify_apic_base_addr(void) 73 { 74 uint64_t msr = rdmsr(MSR_IA32_APICBASE); 75 uint64_t base = GET_APIC_BASE(msr); 76 77 GUEST_ASSERT(base == APIC_DEFAULT_GPA); 78 } 79 80 static void ucna_injection_guest_code(void) 81 { 82 uint64_t ctl2; 83 verify_apic_base_addr(); 84 xapic_enable(); 85 86 /* Sets up the interrupt vector and enables per-bank CMCI sigaling. */ 87 xapic_write_reg(APIC_LVTCMCI, CMCI_VECTOR | APIC_DM_FIXED); 88 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); 89 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); 90 91 /* Enables interrupt in guest. */ 92 asm volatile("sti"); 93 94 /* Let user space inject the first UCNA */ 95 GUEST_SYNC(SYNC_FIRST_UCNA); 96 97 ucna_addr = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK)); 98 99 /* Disables the per-bank CMCI signaling. */ 100 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); 101 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 & ~MCI_CTL2_CMCI_EN); 102 103 /* Let the user space inject the second UCNA */ 104 GUEST_SYNC(SYNC_SECOND_UCNA); 105 106 ucna_addr2 = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK)); 107 GUEST_DONE(); 108 } 109 110 static void cmci_disabled_guest_code(void) 111 { 112 uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); 113 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); 114 115 GUEST_DONE(); 116 } 117 118 static void cmci_enabled_guest_code(void) 119 { 120 uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); 121 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT); 122 123 GUEST_DONE(); 124 } 125 126 static void guest_cmci_handler(struct ex_regs *regs) 127 { 128 i_ucna_rcvd++; 129 i_ucna_addr = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK)); 130 xapic_write_reg(APIC_EOI, 0); 131 } 132 133 static void guest_gp_handler(struct ex_regs *regs) 134 { 135 GUEST_SYNC(SYNC_GP); 136 } 137 138 static void run_vcpu_expect_gp(struct kvm_vcpu *vcpu) 139 { 140 unsigned int exit_reason; 141 struct ucall uc; 142 143 vcpu_run(vcpu); 144 145 exit_reason = vcpu->run->exit_reason; 146 TEST_ASSERT(exit_reason == KVM_EXIT_IO, 147 "exited with unexpected exit reason %u-%s, expected KVM_EXIT_IO", 148 exit_reason, exit_reason_str(exit_reason)); 149 TEST_ASSERT(get_ucall(vcpu, &uc) == UCALL_SYNC, 150 "Expect UCALL_SYNC\n"); 151 TEST_ASSERT(uc.args[1] == SYNC_GP, "#GP is expected."); 152 printf("vCPU received GP in guest.\n"); 153 } 154 155 static void inject_ucna(struct kvm_vcpu *vcpu, uint64_t addr) { 156 /* 157 * A UCNA error is indicated with VAL=1, UC=1, PCC=0, S=0 and AR=0 in 158 * the IA32_MCi_STATUS register. 159 * MSCOD=1 (BIT[16] - MscodDataRdErr). 160 * MCACOD=0x0090 (Memory controller error format, channel 0) 161 */ 162 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | 163 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | 0x10090; 164 struct kvm_x86_mce mce = {}; 165 mce.status = status; 166 mce.mcg_status = 0; 167 /* 168 * MCM_ADDR_PHYS indicates the reported address is a physical address. 169 * Lowest 6 bits is the recoverable address LSB, i.e., the injected MCE 170 * is at 4KB granularity. 171 */ 172 mce.misc = (MCM_ADDR_PHYS << 6) | 0xc; 173 mce.addr = addr; 174 mce.bank = UCNA_BANK; 175 176 vcpu_ioctl(vcpu, KVM_X86_SET_MCE, &mce); 177 } 178 179 static void *run_ucna_injection(void *arg) 180 { 181 struct thread_params *params = (struct thread_params *)arg; 182 struct ucall uc; 183 int old; 184 int r; 185 unsigned int exit_reason; 186 187 r = pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS, &old); 188 TEST_ASSERT(r == 0, 189 "pthread_setcanceltype failed with errno=%d", 190 r); 191 192 vcpu_run(params->vcpu); 193 194 exit_reason = params->vcpu->run->exit_reason; 195 TEST_ASSERT(exit_reason == KVM_EXIT_IO, 196 "unexpected exit reason %u-%s, expected KVM_EXIT_IO", 197 exit_reason, exit_reason_str(exit_reason)); 198 TEST_ASSERT(get_ucall(params->vcpu, &uc) == UCALL_SYNC, 199 "Expect UCALL_SYNC\n"); 200 TEST_ASSERT(uc.args[1] == SYNC_FIRST_UCNA, "Injecting first UCNA."); 201 202 printf("Injecting first UCNA at %#x.\n", FIRST_UCNA_ADDR); 203 204 inject_ucna(params->vcpu, FIRST_UCNA_ADDR); 205 vcpu_run(params->vcpu); 206 207 exit_reason = params->vcpu->run->exit_reason; 208 TEST_ASSERT(exit_reason == KVM_EXIT_IO, 209 "unexpected exit reason %u-%s, expected KVM_EXIT_IO", 210 exit_reason, exit_reason_str(exit_reason)); 211 TEST_ASSERT(get_ucall(params->vcpu, &uc) == UCALL_SYNC, 212 "Expect UCALL_SYNC\n"); 213 TEST_ASSERT(uc.args[1] == SYNC_SECOND_UCNA, "Injecting second UCNA."); 214 215 printf("Injecting second UCNA at %#x.\n", SECOND_UCNA_ADDR); 216 217 inject_ucna(params->vcpu, SECOND_UCNA_ADDR); 218 vcpu_run(params->vcpu); 219 220 exit_reason = params->vcpu->run->exit_reason; 221 TEST_ASSERT(exit_reason == KVM_EXIT_IO, 222 "unexpected exit reason %u-%s, expected KVM_EXIT_IO", 223 exit_reason, exit_reason_str(exit_reason)); 224 if (get_ucall(params->vcpu, &uc) == UCALL_ABORT) { 225 TEST_ASSERT(false, "vCPU assertion failure: %s.\n", 226 (const char *)uc.args[0]); 227 } 228 229 return NULL; 230 } 231 232 static void test_ucna_injection(struct kvm_vcpu *vcpu, struct thread_params *params) 233 { 234 struct kvm_vm *vm = vcpu->vm; 235 params->vcpu = vcpu; 236 params->p_i_ucna_rcvd = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_rcvd); 237 params->p_i_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_addr); 238 params->p_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr); 239 params->p_ucna_addr2 = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr2); 240 241 run_ucna_injection(params); 242 243 TEST_ASSERT(*params->p_i_ucna_rcvd == 1, "Only first UCNA get signaled."); 244 TEST_ASSERT(*params->p_i_ucna_addr == FIRST_UCNA_ADDR, 245 "Only first UCNA reported addr get recorded via interrupt."); 246 TEST_ASSERT(*params->p_ucna_addr == FIRST_UCNA_ADDR, 247 "First injected UCNAs should get exposed via registers."); 248 TEST_ASSERT(*params->p_ucna_addr2 == SECOND_UCNA_ADDR, 249 "Second injected UCNAs should get exposed via registers."); 250 251 printf("Test successful.\n" 252 "UCNA CMCI interrupts received: %ld\n" 253 "Last UCNA address received via CMCI: %lx\n" 254 "First UCNA address in vCPU thread: %lx\n" 255 "Second UCNA address in vCPU thread: %lx\n", 256 *params->p_i_ucna_rcvd, *params->p_i_ucna_addr, 257 *params->p_ucna_addr, *params->p_ucna_addr2); 258 } 259 260 static void setup_mce_cap(struct kvm_vcpu *vcpu, bool enable_cmci_p) 261 { 262 uint64_t mcg_caps = MCG_CTL_P | MCG_SER_P | MCG_LMCE_P | KVM_MAX_MCE_BANKS; 263 if (enable_cmci_p) 264 mcg_caps |= MCG_CMCI_P; 265 266 mcg_caps &= supported_mcg_caps | MCG_CAP_BANKS_MASK; 267 vcpu_ioctl(vcpu, KVM_X86_SETUP_MCE, &mcg_caps); 268 } 269 270 static struct kvm_vcpu *create_vcpu_with_mce_cap(struct kvm_vm *vm, uint32_t vcpuid, 271 bool enable_cmci_p, void *guest_code) 272 { 273 struct kvm_vcpu *vcpu = vm_vcpu_add(vm, vcpuid, guest_code); 274 setup_mce_cap(vcpu, enable_cmci_p); 275 return vcpu; 276 } 277 278 int main(int argc, char *argv[]) 279 { 280 struct thread_params params; 281 struct kvm_vm *vm; 282 struct kvm_vcpu *ucna_vcpu; 283 struct kvm_vcpu *cmcidis_vcpu; 284 struct kvm_vcpu *cmci_vcpu; 285 286 kvm_check_cap(KVM_CAP_MCE); 287 288 vm = __vm_create(VM_MODE_DEFAULT, 3, 0); 289 290 kvm_ioctl(vm->kvm_fd, KVM_X86_GET_MCE_CAP_SUPPORTED, 291 &supported_mcg_caps); 292 293 if (!(supported_mcg_caps & MCG_CMCI_P)) { 294 print_skip("MCG_CMCI_P is not supported"); 295 exit(KSFT_SKIP); 296 } 297 298 ucna_vcpu = create_vcpu_with_mce_cap(vm, 0, true, ucna_injection_guest_code); 299 cmcidis_vcpu = create_vcpu_with_mce_cap(vm, 1, false, cmci_disabled_guest_code); 300 cmci_vcpu = create_vcpu_with_mce_cap(vm, 2, true, cmci_enabled_guest_code); 301 302 vm_init_descriptor_tables(vm); 303 vcpu_init_descriptor_tables(ucna_vcpu); 304 vcpu_init_descriptor_tables(cmcidis_vcpu); 305 vcpu_init_descriptor_tables(cmci_vcpu); 306 vm_install_exception_handler(vm, CMCI_VECTOR, guest_cmci_handler); 307 vm_install_exception_handler(vm, GP_VECTOR, guest_gp_handler); 308 309 virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA); 310 311 test_ucna_injection(ucna_vcpu, ¶ms); 312 run_vcpu_expect_gp(cmcidis_vcpu); 313 run_vcpu_expect_gp(cmci_vcpu); 314 315 kvm_vm_free(vm); 316 } 317