1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * ucna_injection_test
4  *
5  * Copyright (C) 2022, Google LLC.
6  *
7  * This work is licensed under the terms of the GNU GPL, version 2.
8  *
9  * Test that user space can inject UnCorrectable No Action required (UCNA)
10  * memory errors to the guest.
11  *
12  * The test starts one vCPU with the MCG_CMCI_P enabled. It verifies that
13  * proper UCNA errors can be injected to a vCPU with MCG_CMCI_P and
14  * corresponding per-bank control register (MCI_CTL2) bit enabled.
15  * The test also checks that the UCNA errors get recorded in the
16  * Machine Check bank registers no matter the error signal interrupts get
17  * delivered into the guest or not.
18  *
19  */
20 
21 #define _GNU_SOURCE /* for program_invocation_short_name */
22 #include <pthread.h>
23 #include <inttypes.h>
24 #include <string.h>
25 #include <time.h>
26 
27 #include "kvm_util_base.h"
28 #include "kvm_util.h"
29 #include "mce.h"
30 #include "processor.h"
31 #include "test_util.h"
32 #include "apic.h"
33 
34 #define SYNC_FIRST_UCNA 9
35 #define SYNC_SECOND_UCNA 10
36 #define SYNC_GP 11
37 #define FIRST_UCNA_ADDR 0xdeadbeef
38 #define SECOND_UCNA_ADDR 0xcafeb0ba
39 
40 /*
41  * Vector for the CMCI interrupt.
42  * Value is arbitrary. Any value in 0x20-0xFF should work:
43  * https://wiki.osdev.org/Interrupt_Vector_Table
44  */
45 #define CMCI_VECTOR  0xa9
46 
47 #define UCNA_BANK  0x7	// IMC0 bank
48 
49 #define MCI_CTL2_RESERVED_BIT BIT_ULL(29)
50 
51 static uint64_t supported_mcg_caps;
52 
53 /*
54  * Record states about the injected UCNA.
55  * The variables started with the 'i_' prefixes are recorded in interrupt
56  * handler. Variables without the 'i_' prefixes are recorded in guest main
57  * execution thread.
58  */
59 static volatile uint64_t i_ucna_rcvd;
60 static volatile uint64_t i_ucna_addr;
61 static volatile uint64_t ucna_addr;
62 static volatile uint64_t ucna_addr2;
63 
64 struct thread_params {
65 	struct kvm_vcpu *vcpu;
66 	uint64_t *p_i_ucna_rcvd;
67 	uint64_t *p_i_ucna_addr;
68 	uint64_t *p_ucna_addr;
69 	uint64_t *p_ucna_addr2;
70 };
71 
72 static void verify_apic_base_addr(void)
73 {
74 	uint64_t msr = rdmsr(MSR_IA32_APICBASE);
75 	uint64_t base = GET_APIC_BASE(msr);
76 
77 	GUEST_ASSERT(base == APIC_DEFAULT_GPA);
78 }
79 
80 static void ucna_injection_guest_code(void)
81 {
82 	uint64_t ctl2;
83 	verify_apic_base_addr();
84 	xapic_enable();
85 
86 	/* Sets up the interrupt vector and enables per-bank CMCI sigaling. */
87 	xapic_write_reg(APIC_LVTCMCI, CMCI_VECTOR | APIC_DM_FIXED);
88 	ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
89 	wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
90 
91 	/* Enables interrupt in guest. */
92 	asm volatile("sti");
93 
94 	/* Let user space inject the first UCNA */
95 	GUEST_SYNC(SYNC_FIRST_UCNA);
96 
97 	ucna_addr = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
98 
99 	/* Disables the per-bank CMCI signaling. */
100 	ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
101 	wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 & ~MCI_CTL2_CMCI_EN);
102 
103 	/* Let the user space inject the second UCNA */
104 	GUEST_SYNC(SYNC_SECOND_UCNA);
105 
106 	ucna_addr2 = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
107 	GUEST_DONE();
108 }
109 
110 static void cmci_disabled_guest_code(void)
111 {
112 	uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
113 	wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
114 
115 	GUEST_DONE();
116 }
117 
118 static void cmci_enabled_guest_code(void)
119 {
120 	uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
121 	wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT);
122 
123 	GUEST_DONE();
124 }
125 
126 static void guest_cmci_handler(struct ex_regs *regs)
127 {
128 	i_ucna_rcvd++;
129 	i_ucna_addr = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
130 	xapic_write_reg(APIC_EOI, 0);
131 }
132 
133 static void guest_gp_handler(struct ex_regs *regs)
134 {
135 	GUEST_SYNC(SYNC_GP);
136 }
137 
138 static void run_vcpu_expect_gp(struct kvm_vcpu *vcpu)
139 {
140 	struct ucall uc;
141 
142 	vcpu_run(vcpu);
143 
144 	TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO);
145 	TEST_ASSERT(get_ucall(vcpu, &uc) == UCALL_SYNC,
146 		    "Expect UCALL_SYNC\n");
147 	TEST_ASSERT(uc.args[1] == SYNC_GP, "#GP is expected.");
148 	printf("vCPU received GP in guest.\n");
149 }
150 
151 static void inject_ucna(struct kvm_vcpu *vcpu, uint64_t addr) {
152 	/*
153 	 * A UCNA error is indicated with VAL=1, UC=1, PCC=0, S=0 and AR=0 in
154 	 * the IA32_MCi_STATUS register.
155 	 * MSCOD=1 (BIT[16] - MscodDataRdErr).
156 	 * MCACOD=0x0090 (Memory controller error format, channel 0)
157 	 */
158 	uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
159 			  MCI_STATUS_MISCV | MCI_STATUS_ADDRV | 0x10090;
160 	struct kvm_x86_mce mce = {};
161 	mce.status = status;
162 	mce.mcg_status = 0;
163 	/*
164 	 * MCM_ADDR_PHYS indicates the reported address is a physical address.
165 	 * Lowest 6 bits is the recoverable address LSB, i.e., the injected MCE
166 	 * is at 4KB granularity.
167 	 */
168 	mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
169 	mce.addr = addr;
170 	mce.bank = UCNA_BANK;
171 
172 	vcpu_ioctl(vcpu, KVM_X86_SET_MCE, &mce);
173 }
174 
175 static void *run_ucna_injection(void *arg)
176 {
177 	struct thread_params *params = (struct thread_params *)arg;
178 	struct ucall uc;
179 	int old;
180 	int r;
181 
182 	r = pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS, &old);
183 	TEST_ASSERT(r == 0,
184 		    "pthread_setcanceltype failed with errno=%d",
185 		    r);
186 
187 	vcpu_run(params->vcpu);
188 
189 	TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
190 	TEST_ASSERT(get_ucall(params->vcpu, &uc) == UCALL_SYNC,
191 		    "Expect UCALL_SYNC\n");
192 	TEST_ASSERT(uc.args[1] == SYNC_FIRST_UCNA, "Injecting first UCNA.");
193 
194 	printf("Injecting first UCNA at %#x.\n", FIRST_UCNA_ADDR);
195 
196 	inject_ucna(params->vcpu, FIRST_UCNA_ADDR);
197 	vcpu_run(params->vcpu);
198 
199 	TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
200 	TEST_ASSERT(get_ucall(params->vcpu, &uc) == UCALL_SYNC,
201 		    "Expect UCALL_SYNC\n");
202 	TEST_ASSERT(uc.args[1] == SYNC_SECOND_UCNA, "Injecting second UCNA.");
203 
204 	printf("Injecting second UCNA at %#x.\n", SECOND_UCNA_ADDR);
205 
206 	inject_ucna(params->vcpu, SECOND_UCNA_ADDR);
207 	vcpu_run(params->vcpu);
208 
209 	TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
210 	if (get_ucall(params->vcpu, &uc) == UCALL_ABORT) {
211 		TEST_ASSERT(false, "vCPU assertion failure: %s.\n",
212 			    (const char *)uc.args[0]);
213 	}
214 
215 	return NULL;
216 }
217 
218 static void test_ucna_injection(struct kvm_vcpu *vcpu, struct thread_params *params)
219 {
220 	struct kvm_vm *vm = vcpu->vm;
221 	params->vcpu = vcpu;
222 	params->p_i_ucna_rcvd = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_rcvd);
223 	params->p_i_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_addr);
224 	params->p_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr);
225 	params->p_ucna_addr2 = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr2);
226 
227 	run_ucna_injection(params);
228 
229 	TEST_ASSERT(*params->p_i_ucna_rcvd == 1, "Only first UCNA get signaled.");
230 	TEST_ASSERT(*params->p_i_ucna_addr == FIRST_UCNA_ADDR,
231 		    "Only first UCNA reported addr get recorded via interrupt.");
232 	TEST_ASSERT(*params->p_ucna_addr == FIRST_UCNA_ADDR,
233 		    "First injected UCNAs should get exposed via registers.");
234 	TEST_ASSERT(*params->p_ucna_addr2 == SECOND_UCNA_ADDR,
235 		    "Second injected UCNAs should get exposed via registers.");
236 
237 	printf("Test successful.\n"
238 	       "UCNA CMCI interrupts received: %ld\n"
239 	       "Last UCNA address received via CMCI: %lx\n"
240 	       "First UCNA address in vCPU thread: %lx\n"
241 	       "Second UCNA address in vCPU thread: %lx\n",
242 	       *params->p_i_ucna_rcvd, *params->p_i_ucna_addr,
243 	       *params->p_ucna_addr, *params->p_ucna_addr2);
244 }
245 
246 static void setup_mce_cap(struct kvm_vcpu *vcpu, bool enable_cmci_p)
247 {
248 	uint64_t mcg_caps = MCG_CTL_P | MCG_SER_P | MCG_LMCE_P | KVM_MAX_MCE_BANKS;
249 	if (enable_cmci_p)
250 		mcg_caps |= MCG_CMCI_P;
251 
252 	mcg_caps &= supported_mcg_caps | MCG_CAP_BANKS_MASK;
253 	vcpu_ioctl(vcpu, KVM_X86_SETUP_MCE, &mcg_caps);
254 }
255 
256 static struct kvm_vcpu *create_vcpu_with_mce_cap(struct kvm_vm *vm, uint32_t vcpuid,
257 						 bool enable_cmci_p, void *guest_code)
258 {
259 	struct kvm_vcpu *vcpu = vm_vcpu_add(vm, vcpuid, guest_code);
260 	setup_mce_cap(vcpu, enable_cmci_p);
261 	return vcpu;
262 }
263 
264 int main(int argc, char *argv[])
265 {
266 	struct thread_params params;
267 	struct kvm_vm *vm;
268 	struct kvm_vcpu *ucna_vcpu;
269 	struct kvm_vcpu *cmcidis_vcpu;
270 	struct kvm_vcpu *cmci_vcpu;
271 
272 	kvm_check_cap(KVM_CAP_MCE);
273 
274 	vm = __vm_create(VM_MODE_DEFAULT, 3, 0);
275 
276 	kvm_ioctl(vm->kvm_fd, KVM_X86_GET_MCE_CAP_SUPPORTED,
277 		  &supported_mcg_caps);
278 
279 	if (!(supported_mcg_caps & MCG_CMCI_P)) {
280 		print_skip("MCG_CMCI_P is not supported");
281 		exit(KSFT_SKIP);
282 	}
283 
284 	ucna_vcpu = create_vcpu_with_mce_cap(vm, 0, true, ucna_injection_guest_code);
285 	cmcidis_vcpu = create_vcpu_with_mce_cap(vm, 1, false, cmci_disabled_guest_code);
286 	cmci_vcpu = create_vcpu_with_mce_cap(vm, 2, true, cmci_enabled_guest_code);
287 
288 	vm_init_descriptor_tables(vm);
289 	vcpu_init_descriptor_tables(ucna_vcpu);
290 	vcpu_init_descriptor_tables(cmcidis_vcpu);
291 	vcpu_init_descriptor_tables(cmci_vcpu);
292 	vm_install_exception_handler(vm, CMCI_VECTOR, guest_cmci_handler);
293 	vm_install_exception_handler(vm, GP_VECTOR, guest_gp_handler);
294 
295 	virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA);
296 
297 	test_ucna_injection(ucna_vcpu, &params);
298 	run_vcpu_expect_gp(cmcidis_vcpu);
299 	run_vcpu_expect_gp(cmci_vcpu);
300 
301 	kvm_vm_free(vm);
302 }
303