1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * tools/testing/selftests/kvm/lib/x86_64/vmx.c 4 * 5 * Copyright (C) 2018, Google LLC. 6 */ 7 8 #include "test_util.h" 9 #include "kvm_util.h" 10 #include "processor.h" 11 #include "vmx.h" 12 13 #define PAGE_SHIFT_4K 12 14 15 #define KVM_EPT_PAGE_TABLE_MIN_PADDR 0x1c0000 16 17 bool enable_evmcs; 18 19 struct hv_enlightened_vmcs *current_evmcs; 20 struct hv_vp_assist_page *current_vp_assist; 21 22 struct eptPageTableEntry { 23 uint64_t readable:1; 24 uint64_t writable:1; 25 uint64_t executable:1; 26 uint64_t memory_type:3; 27 uint64_t ignore_pat:1; 28 uint64_t page_size:1; 29 uint64_t accessed:1; 30 uint64_t dirty:1; 31 uint64_t ignored_11_10:2; 32 uint64_t address:40; 33 uint64_t ignored_62_52:11; 34 uint64_t suppress_ve:1; 35 }; 36 37 struct eptPageTablePointer { 38 uint64_t memory_type:3; 39 uint64_t page_walk_length:3; 40 uint64_t ad_enabled:1; 41 uint64_t reserved_11_07:5; 42 uint64_t address:40; 43 uint64_t reserved_63_52:12; 44 }; 45 int vcpu_enable_evmcs(struct kvm_vcpu *vcpu) 46 { 47 uint16_t evmcs_ver; 48 49 vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 50 (unsigned long)&evmcs_ver); 51 52 /* KVM should return supported EVMCS version range */ 53 TEST_ASSERT(((evmcs_ver >> 8) >= (evmcs_ver & 0xff)) && 54 (evmcs_ver & 0xff) > 0, 55 "Incorrect EVMCS version range: %x:%x\n", 56 evmcs_ver & 0xff, evmcs_ver >> 8); 57 58 return evmcs_ver; 59 } 60 61 /* Allocate memory regions for nested VMX tests. 62 * 63 * Input Args: 64 * vm - The VM to allocate guest-virtual addresses in. 65 * 66 * Output Args: 67 * p_vmx_gva - The guest virtual address for the struct vmx_pages. 68 * 69 * Return: 70 * Pointer to structure with the addresses of the VMX areas. 71 */ 72 struct vmx_pages * 73 vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva) 74 { 75 vm_vaddr_t vmx_gva = vm_vaddr_alloc_page(vm); 76 struct vmx_pages *vmx = addr_gva2hva(vm, vmx_gva); 77 78 /* Setup of a region of guest memory for the vmxon region. */ 79 vmx->vmxon = (void *)vm_vaddr_alloc_page(vm); 80 vmx->vmxon_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmxon); 81 vmx->vmxon_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmxon); 82 83 /* Setup of a region of guest memory for a vmcs. */ 84 vmx->vmcs = (void *)vm_vaddr_alloc_page(vm); 85 vmx->vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmcs); 86 vmx->vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmcs); 87 88 /* Setup of a region of guest memory for the MSR bitmap. */ 89 vmx->msr = (void *)vm_vaddr_alloc_page(vm); 90 vmx->msr_hva = addr_gva2hva(vm, (uintptr_t)vmx->msr); 91 vmx->msr_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->msr); 92 memset(vmx->msr_hva, 0, getpagesize()); 93 94 /* Setup of a region of guest memory for the shadow VMCS. */ 95 vmx->shadow_vmcs = (void *)vm_vaddr_alloc_page(vm); 96 vmx->shadow_vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->shadow_vmcs); 97 vmx->shadow_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->shadow_vmcs); 98 99 /* Setup of a region of guest memory for the VMREAD and VMWRITE bitmaps. */ 100 vmx->vmread = (void *)vm_vaddr_alloc_page(vm); 101 vmx->vmread_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmread); 102 vmx->vmread_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmread); 103 memset(vmx->vmread_hva, 0, getpagesize()); 104 105 vmx->vmwrite = (void *)vm_vaddr_alloc_page(vm); 106 vmx->vmwrite_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmwrite); 107 vmx->vmwrite_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmwrite); 108 memset(vmx->vmwrite_hva, 0, getpagesize()); 109 110 /* Setup of a region of guest memory for the VP Assist page. */ 111 vmx->vp_assist = (void *)vm_vaddr_alloc_page(vm); 112 vmx->vp_assist_hva = addr_gva2hva(vm, (uintptr_t)vmx->vp_assist); 113 vmx->vp_assist_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vp_assist); 114 115 /* Setup of a region of guest memory for the enlightened VMCS. */ 116 vmx->enlightened_vmcs = (void *)vm_vaddr_alloc_page(vm); 117 vmx->enlightened_vmcs_hva = 118 addr_gva2hva(vm, (uintptr_t)vmx->enlightened_vmcs); 119 vmx->enlightened_vmcs_gpa = 120 addr_gva2gpa(vm, (uintptr_t)vmx->enlightened_vmcs); 121 122 *p_vmx_gva = vmx_gva; 123 return vmx; 124 } 125 126 bool prepare_for_vmx_operation(struct vmx_pages *vmx) 127 { 128 uint64_t feature_control; 129 uint64_t required; 130 unsigned long cr0; 131 unsigned long cr4; 132 133 /* 134 * Ensure bits in CR0 and CR4 are valid in VMX operation: 135 * - Bit X is 1 in _FIXED0: bit X is fixed to 1 in CRx. 136 * - Bit X is 0 in _FIXED1: bit X is fixed to 0 in CRx. 137 */ 138 __asm__ __volatile__("mov %%cr0, %0" : "=r"(cr0) : : "memory"); 139 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1); 140 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0); 141 __asm__ __volatile__("mov %0, %%cr0" : : "r"(cr0) : "memory"); 142 143 __asm__ __volatile__("mov %%cr4, %0" : "=r"(cr4) : : "memory"); 144 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1); 145 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0); 146 /* Enable VMX operation */ 147 cr4 |= X86_CR4_VMXE; 148 __asm__ __volatile__("mov %0, %%cr4" : : "r"(cr4) : "memory"); 149 150 /* 151 * Configure IA32_FEATURE_CONTROL MSR to allow VMXON: 152 * Bit 0: Lock bit. If clear, VMXON causes a #GP. 153 * Bit 2: Enables VMXON outside of SMX operation. If clear, VMXON 154 * outside of SMX causes a #GP. 155 */ 156 required = FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 157 required |= FEAT_CTL_LOCKED; 158 feature_control = rdmsr(MSR_IA32_FEAT_CTL); 159 if ((feature_control & required) != required) 160 wrmsr(MSR_IA32_FEAT_CTL, feature_control | required); 161 162 /* Enter VMX root operation. */ 163 *(uint32_t *)(vmx->vmxon) = vmcs_revision(); 164 if (vmxon(vmx->vmxon_gpa)) 165 return false; 166 167 return true; 168 } 169 170 bool load_vmcs(struct vmx_pages *vmx) 171 { 172 if (!enable_evmcs) { 173 /* Load a VMCS. */ 174 *(uint32_t *)(vmx->vmcs) = vmcs_revision(); 175 if (vmclear(vmx->vmcs_gpa)) 176 return false; 177 178 if (vmptrld(vmx->vmcs_gpa)) 179 return false; 180 181 /* Setup shadow VMCS, do not load it yet. */ 182 *(uint32_t *)(vmx->shadow_vmcs) = 183 vmcs_revision() | 0x80000000ul; 184 if (vmclear(vmx->shadow_vmcs_gpa)) 185 return false; 186 } else { 187 if (evmcs_vmptrld(vmx->enlightened_vmcs_gpa, 188 vmx->enlightened_vmcs)) 189 return false; 190 current_evmcs->revision_id = EVMCS_VERSION; 191 } 192 193 return true; 194 } 195 196 static bool ept_vpid_cap_supported(uint64_t mask) 197 { 198 return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask; 199 } 200 201 bool ept_1g_pages_supported(void) 202 { 203 return ept_vpid_cap_supported(VMX_EPT_VPID_CAP_1G_PAGES); 204 } 205 206 /* 207 * Initialize the control fields to the most basic settings possible. 208 */ 209 static inline void init_vmcs_control_fields(struct vmx_pages *vmx) 210 { 211 uint32_t sec_exec_ctl = 0; 212 213 vmwrite(VIRTUAL_PROCESSOR_ID, 0); 214 vmwrite(POSTED_INTR_NV, 0); 215 216 vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS)); 217 218 if (vmx->eptp_gpa) { 219 uint64_t ept_paddr; 220 struct eptPageTablePointer eptp = { 221 .memory_type = VMX_BASIC_MEM_TYPE_WB, 222 .page_walk_length = 3, /* + 1 */ 223 .ad_enabled = ept_vpid_cap_supported(VMX_EPT_VPID_CAP_AD_BITS), 224 .address = vmx->eptp_gpa >> PAGE_SHIFT_4K, 225 }; 226 227 memcpy(&ept_paddr, &eptp, sizeof(ept_paddr)); 228 vmwrite(EPT_POINTER, ept_paddr); 229 sec_exec_ctl |= SECONDARY_EXEC_ENABLE_EPT; 230 } 231 232 if (!vmwrite(SECONDARY_VM_EXEC_CONTROL, sec_exec_ctl)) 233 vmwrite(CPU_BASED_VM_EXEC_CONTROL, 234 rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); 235 else { 236 vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS)); 237 GUEST_ASSERT(!sec_exec_ctl); 238 } 239 240 vmwrite(EXCEPTION_BITMAP, 0); 241 vmwrite(PAGE_FAULT_ERROR_CODE_MASK, 0); 242 vmwrite(PAGE_FAULT_ERROR_CODE_MATCH, -1); /* Never match */ 243 vmwrite(CR3_TARGET_COUNT, 0); 244 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) | 245 VM_EXIT_HOST_ADDR_SPACE_SIZE); /* 64-bit host */ 246 vmwrite(VM_EXIT_MSR_STORE_COUNT, 0); 247 vmwrite(VM_EXIT_MSR_LOAD_COUNT, 0); 248 vmwrite(VM_ENTRY_CONTROLS, rdmsr(MSR_IA32_VMX_ENTRY_CTLS) | 249 VM_ENTRY_IA32E_MODE); /* 64-bit guest */ 250 vmwrite(VM_ENTRY_MSR_LOAD_COUNT, 0); 251 vmwrite(VM_ENTRY_INTR_INFO_FIELD, 0); 252 vmwrite(TPR_THRESHOLD, 0); 253 254 vmwrite(CR0_GUEST_HOST_MASK, 0); 255 vmwrite(CR4_GUEST_HOST_MASK, 0); 256 vmwrite(CR0_READ_SHADOW, get_cr0()); 257 vmwrite(CR4_READ_SHADOW, get_cr4()); 258 259 vmwrite(MSR_BITMAP, vmx->msr_gpa); 260 vmwrite(VMREAD_BITMAP, vmx->vmread_gpa); 261 vmwrite(VMWRITE_BITMAP, vmx->vmwrite_gpa); 262 } 263 264 /* 265 * Initialize the host state fields based on the current host state, with 266 * the exception of HOST_RSP and HOST_RIP, which should be set by vmlaunch 267 * or vmresume. 268 */ 269 static inline void init_vmcs_host_state(void) 270 { 271 uint32_t exit_controls = vmreadz(VM_EXIT_CONTROLS); 272 273 vmwrite(HOST_ES_SELECTOR, get_es()); 274 vmwrite(HOST_CS_SELECTOR, get_cs()); 275 vmwrite(HOST_SS_SELECTOR, get_ss()); 276 vmwrite(HOST_DS_SELECTOR, get_ds()); 277 vmwrite(HOST_FS_SELECTOR, get_fs()); 278 vmwrite(HOST_GS_SELECTOR, get_gs()); 279 vmwrite(HOST_TR_SELECTOR, get_tr()); 280 281 if (exit_controls & VM_EXIT_LOAD_IA32_PAT) 282 vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT)); 283 if (exit_controls & VM_EXIT_LOAD_IA32_EFER) 284 vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER)); 285 if (exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 286 vmwrite(HOST_IA32_PERF_GLOBAL_CTRL, 287 rdmsr(MSR_CORE_PERF_GLOBAL_CTRL)); 288 289 vmwrite(HOST_IA32_SYSENTER_CS, rdmsr(MSR_IA32_SYSENTER_CS)); 290 291 vmwrite(HOST_CR0, get_cr0()); 292 vmwrite(HOST_CR3, get_cr3()); 293 vmwrite(HOST_CR4, get_cr4()); 294 vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE)); 295 vmwrite(HOST_GS_BASE, rdmsr(MSR_GS_BASE)); 296 vmwrite(HOST_TR_BASE, 297 get_desc64_base((struct desc64 *)(get_gdt().address + get_tr()))); 298 vmwrite(HOST_GDTR_BASE, get_gdt().address); 299 vmwrite(HOST_IDTR_BASE, get_idt().address); 300 vmwrite(HOST_IA32_SYSENTER_ESP, rdmsr(MSR_IA32_SYSENTER_ESP)); 301 vmwrite(HOST_IA32_SYSENTER_EIP, rdmsr(MSR_IA32_SYSENTER_EIP)); 302 } 303 304 /* 305 * Initialize the guest state fields essentially as a clone of 306 * the host state fields. Some host state fields have fixed 307 * values, and we set the corresponding guest state fields accordingly. 308 */ 309 static inline void init_vmcs_guest_state(void *rip, void *rsp) 310 { 311 vmwrite(GUEST_ES_SELECTOR, vmreadz(HOST_ES_SELECTOR)); 312 vmwrite(GUEST_CS_SELECTOR, vmreadz(HOST_CS_SELECTOR)); 313 vmwrite(GUEST_SS_SELECTOR, vmreadz(HOST_SS_SELECTOR)); 314 vmwrite(GUEST_DS_SELECTOR, vmreadz(HOST_DS_SELECTOR)); 315 vmwrite(GUEST_FS_SELECTOR, vmreadz(HOST_FS_SELECTOR)); 316 vmwrite(GUEST_GS_SELECTOR, vmreadz(HOST_GS_SELECTOR)); 317 vmwrite(GUEST_LDTR_SELECTOR, 0); 318 vmwrite(GUEST_TR_SELECTOR, vmreadz(HOST_TR_SELECTOR)); 319 vmwrite(GUEST_INTR_STATUS, 0); 320 vmwrite(GUEST_PML_INDEX, 0); 321 322 vmwrite(VMCS_LINK_POINTER, -1ll); 323 vmwrite(GUEST_IA32_DEBUGCTL, 0); 324 vmwrite(GUEST_IA32_PAT, vmreadz(HOST_IA32_PAT)); 325 vmwrite(GUEST_IA32_EFER, vmreadz(HOST_IA32_EFER)); 326 vmwrite(GUEST_IA32_PERF_GLOBAL_CTRL, 327 vmreadz(HOST_IA32_PERF_GLOBAL_CTRL)); 328 329 vmwrite(GUEST_ES_LIMIT, -1); 330 vmwrite(GUEST_CS_LIMIT, -1); 331 vmwrite(GUEST_SS_LIMIT, -1); 332 vmwrite(GUEST_DS_LIMIT, -1); 333 vmwrite(GUEST_FS_LIMIT, -1); 334 vmwrite(GUEST_GS_LIMIT, -1); 335 vmwrite(GUEST_LDTR_LIMIT, -1); 336 vmwrite(GUEST_TR_LIMIT, 0x67); 337 vmwrite(GUEST_GDTR_LIMIT, 0xffff); 338 vmwrite(GUEST_IDTR_LIMIT, 0xffff); 339 vmwrite(GUEST_ES_AR_BYTES, 340 vmreadz(GUEST_ES_SELECTOR) == 0 ? 0x10000 : 0xc093); 341 vmwrite(GUEST_CS_AR_BYTES, 0xa09b); 342 vmwrite(GUEST_SS_AR_BYTES, 0xc093); 343 vmwrite(GUEST_DS_AR_BYTES, 344 vmreadz(GUEST_DS_SELECTOR) == 0 ? 0x10000 : 0xc093); 345 vmwrite(GUEST_FS_AR_BYTES, 346 vmreadz(GUEST_FS_SELECTOR) == 0 ? 0x10000 : 0xc093); 347 vmwrite(GUEST_GS_AR_BYTES, 348 vmreadz(GUEST_GS_SELECTOR) == 0 ? 0x10000 : 0xc093); 349 vmwrite(GUEST_LDTR_AR_BYTES, 0x10000); 350 vmwrite(GUEST_TR_AR_BYTES, 0x8b); 351 vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0); 352 vmwrite(GUEST_ACTIVITY_STATE, 0); 353 vmwrite(GUEST_SYSENTER_CS, vmreadz(HOST_IA32_SYSENTER_CS)); 354 vmwrite(VMX_PREEMPTION_TIMER_VALUE, 0); 355 356 vmwrite(GUEST_CR0, vmreadz(HOST_CR0)); 357 vmwrite(GUEST_CR3, vmreadz(HOST_CR3)); 358 vmwrite(GUEST_CR4, vmreadz(HOST_CR4)); 359 vmwrite(GUEST_ES_BASE, 0); 360 vmwrite(GUEST_CS_BASE, 0); 361 vmwrite(GUEST_SS_BASE, 0); 362 vmwrite(GUEST_DS_BASE, 0); 363 vmwrite(GUEST_FS_BASE, vmreadz(HOST_FS_BASE)); 364 vmwrite(GUEST_GS_BASE, vmreadz(HOST_GS_BASE)); 365 vmwrite(GUEST_LDTR_BASE, 0); 366 vmwrite(GUEST_TR_BASE, vmreadz(HOST_TR_BASE)); 367 vmwrite(GUEST_GDTR_BASE, vmreadz(HOST_GDTR_BASE)); 368 vmwrite(GUEST_IDTR_BASE, vmreadz(HOST_IDTR_BASE)); 369 vmwrite(GUEST_DR7, 0x400); 370 vmwrite(GUEST_RSP, (uint64_t)rsp); 371 vmwrite(GUEST_RIP, (uint64_t)rip); 372 vmwrite(GUEST_RFLAGS, 2); 373 vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, 0); 374 vmwrite(GUEST_SYSENTER_ESP, vmreadz(HOST_IA32_SYSENTER_ESP)); 375 vmwrite(GUEST_SYSENTER_EIP, vmreadz(HOST_IA32_SYSENTER_EIP)); 376 } 377 378 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp) 379 { 380 init_vmcs_control_fields(vmx); 381 init_vmcs_host_state(); 382 init_vmcs_guest_state(guest_rip, guest_rsp); 383 } 384 385 static void nested_create_pte(struct kvm_vm *vm, 386 struct eptPageTableEntry *pte, 387 uint64_t nested_paddr, 388 uint64_t paddr, 389 int current_level, 390 int target_level) 391 { 392 if (!pte->readable) { 393 pte->writable = true; 394 pte->readable = true; 395 pte->executable = true; 396 pte->page_size = (current_level == target_level); 397 if (pte->page_size) 398 pte->address = paddr >> vm->page_shift; 399 else 400 pte->address = vm_alloc_page_table(vm) >> vm->page_shift; 401 } else { 402 /* 403 * Entry already present. Assert that the caller doesn't want 404 * a hugepage at this level, and that there isn't a hugepage at 405 * this level. 406 */ 407 TEST_ASSERT(current_level != target_level, 408 "Cannot create hugepage at level: %u, nested_paddr: 0x%lx\n", 409 current_level, nested_paddr); 410 TEST_ASSERT(!pte->page_size, 411 "Cannot create page table at level: %u, nested_paddr: 0x%lx\n", 412 current_level, nested_paddr); 413 } 414 } 415 416 417 void __nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm, 418 uint64_t nested_paddr, uint64_t paddr, int target_level) 419 { 420 const uint64_t page_size = PG_LEVEL_SIZE(target_level); 421 struct eptPageTableEntry *pt = vmx->eptp_hva, *pte; 422 uint16_t index; 423 424 TEST_ASSERT(vm->mode == VM_MODE_PXXV48_4K, "Attempt to use " 425 "unknown or unsupported guest mode, mode: 0x%x", vm->mode); 426 427 TEST_ASSERT((nested_paddr >> 48) == 0, 428 "Nested physical address 0x%lx requires 5-level paging", 429 nested_paddr); 430 TEST_ASSERT((nested_paddr % page_size) == 0, 431 "Nested physical address not on page boundary,\n" 432 " nested_paddr: 0x%lx page_size: 0x%lx", 433 nested_paddr, page_size); 434 TEST_ASSERT((nested_paddr >> vm->page_shift) <= vm->max_gfn, 435 "Physical address beyond beyond maximum supported,\n" 436 " nested_paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", 437 paddr, vm->max_gfn, vm->page_size); 438 TEST_ASSERT((paddr % page_size) == 0, 439 "Physical address not on page boundary,\n" 440 " paddr: 0x%lx page_size: 0x%lx", 441 paddr, page_size); 442 TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, 443 "Physical address beyond beyond maximum supported,\n" 444 " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", 445 paddr, vm->max_gfn, vm->page_size); 446 447 for (int level = PG_LEVEL_512G; level >= PG_LEVEL_4K; level--) { 448 index = (nested_paddr >> PG_LEVEL_SHIFT(level)) & 0x1ffu; 449 pte = &pt[index]; 450 451 nested_create_pte(vm, pte, nested_paddr, paddr, level, target_level); 452 453 if (pte->page_size) 454 break; 455 456 pt = addr_gpa2hva(vm, pte->address * vm->page_size); 457 } 458 459 /* 460 * For now mark these as accessed and dirty because the only 461 * testcase we have needs that. Can be reconsidered later. 462 */ 463 pte->accessed = true; 464 pte->dirty = true; 465 466 } 467 468 void nested_pg_map(struct vmx_pages *vmx, struct kvm_vm *vm, 469 uint64_t nested_paddr, uint64_t paddr) 470 { 471 __nested_pg_map(vmx, vm, nested_paddr, paddr, PG_LEVEL_4K); 472 } 473 474 /* 475 * Map a range of EPT guest physical addresses to the VM's physical address 476 * 477 * Input Args: 478 * vm - Virtual Machine 479 * nested_paddr - Nested guest physical address to map 480 * paddr - VM Physical Address 481 * size - The size of the range to map 482 * level - The level at which to map the range 483 * 484 * Output Args: None 485 * 486 * Return: None 487 * 488 * Within the VM given by vm, creates a nested guest translation for the 489 * page range starting at nested_paddr to the page range starting at paddr. 490 */ 491 void __nested_map(struct vmx_pages *vmx, struct kvm_vm *vm, 492 uint64_t nested_paddr, uint64_t paddr, uint64_t size, 493 int level) 494 { 495 size_t page_size = PG_LEVEL_SIZE(level); 496 size_t npages = size / page_size; 497 498 TEST_ASSERT(nested_paddr + size > nested_paddr, "Vaddr overflow"); 499 TEST_ASSERT(paddr + size > paddr, "Paddr overflow"); 500 501 while (npages--) { 502 __nested_pg_map(vmx, vm, nested_paddr, paddr, level); 503 nested_paddr += page_size; 504 paddr += page_size; 505 } 506 } 507 508 void nested_map(struct vmx_pages *vmx, struct kvm_vm *vm, 509 uint64_t nested_paddr, uint64_t paddr, uint64_t size) 510 { 511 __nested_map(vmx, vm, nested_paddr, paddr, size, PG_LEVEL_4K); 512 } 513 514 /* Prepare an identity extended page table that maps all the 515 * physical pages in VM. 516 */ 517 void nested_map_memslot(struct vmx_pages *vmx, struct kvm_vm *vm, 518 uint32_t memslot) 519 { 520 sparsebit_idx_t i, last; 521 struct userspace_mem_region *region = 522 memslot2region(vm, memslot); 523 524 i = (region->region.guest_phys_addr >> vm->page_shift) - 1; 525 last = i + (region->region.memory_size >> vm->page_shift); 526 for (;;) { 527 i = sparsebit_next_clear(region->unused_phy_pages, i); 528 if (i > last) 529 break; 530 531 nested_map(vmx, vm, 532 (uint64_t)i << vm->page_shift, 533 (uint64_t)i << vm->page_shift, 534 1 << vm->page_shift); 535 } 536 } 537 538 /* Identity map a region with 1GiB Pages. */ 539 void nested_identity_map_1g(struct vmx_pages *vmx, struct kvm_vm *vm, 540 uint64_t addr, uint64_t size) 541 { 542 __nested_map(vmx, vm, addr, addr, size, PG_LEVEL_1G); 543 } 544 545 void prepare_eptp(struct vmx_pages *vmx, struct kvm_vm *vm, 546 uint32_t eptp_memslot) 547 { 548 vmx->eptp = (void *)vm_vaddr_alloc_page(vm); 549 vmx->eptp_hva = addr_gva2hva(vm, (uintptr_t)vmx->eptp); 550 vmx->eptp_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->eptp); 551 } 552 553 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm) 554 { 555 vmx->apic_access = (void *)vm_vaddr_alloc_page(vm); 556 vmx->apic_access_hva = addr_gva2hva(vm, (uintptr_t)vmx->apic_access); 557 vmx->apic_access_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->apic_access); 558 } 559