1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * tools/testing/selftests/kvm/lib/x86_64/vmx.c 4 * 5 * Copyright (C) 2018, Google LLC. 6 */ 7 8 #include "test_util.h" 9 #include "kvm_util.h" 10 #include "processor.h" 11 #include "vmx.h" 12 13 bool enable_evmcs; 14 15 int vcpu_enable_evmcs(struct kvm_vm *vm, int vcpu_id) 16 { 17 uint16_t evmcs_ver; 18 19 struct kvm_enable_cap enable_evmcs_cap = { 20 .cap = KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 21 .args[0] = (unsigned long)&evmcs_ver 22 }; 23 24 vcpu_ioctl(vm, vcpu_id, KVM_ENABLE_CAP, &enable_evmcs_cap); 25 26 /* KVM should return supported EVMCS version range */ 27 TEST_ASSERT(((evmcs_ver >> 8) >= (evmcs_ver & 0xff)) && 28 (evmcs_ver & 0xff) > 0, 29 "Incorrect EVMCS version range: %x:%x\n", 30 evmcs_ver & 0xff, evmcs_ver >> 8); 31 32 return evmcs_ver; 33 } 34 35 /* Allocate memory regions for nested VMX tests. 36 * 37 * Input Args: 38 * vm - The VM to allocate guest-virtual addresses in. 39 * 40 * Output Args: 41 * p_vmx_gva - The guest virtual address for the struct vmx_pages. 42 * 43 * Return: 44 * Pointer to structure with the addresses of the VMX areas. 45 */ 46 struct vmx_pages * 47 vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva) 48 { 49 vm_vaddr_t vmx_gva = vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0); 50 struct vmx_pages *vmx = addr_gva2hva(vm, vmx_gva); 51 52 /* Setup of a region of guest memory for the vmxon region. */ 53 vmx->vmxon = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0); 54 vmx->vmxon_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmxon); 55 vmx->vmxon_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmxon); 56 57 /* Setup of a region of guest memory for a vmcs. */ 58 vmx->vmcs = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0); 59 vmx->vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmcs); 60 vmx->vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmcs); 61 62 /* Setup of a region of guest memory for the MSR bitmap. */ 63 vmx->msr = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0); 64 vmx->msr_hva = addr_gva2hva(vm, (uintptr_t)vmx->msr); 65 vmx->msr_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->msr); 66 memset(vmx->msr_hva, 0, getpagesize()); 67 68 /* Setup of a region of guest memory for the shadow VMCS. */ 69 vmx->shadow_vmcs = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0); 70 vmx->shadow_vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->shadow_vmcs); 71 vmx->shadow_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->shadow_vmcs); 72 73 /* Setup of a region of guest memory for the VMREAD and VMWRITE bitmaps. */ 74 vmx->vmread = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0); 75 vmx->vmread_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmread); 76 vmx->vmread_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmread); 77 memset(vmx->vmread_hva, 0, getpagesize()); 78 79 vmx->vmwrite = (void *)vm_vaddr_alloc(vm, getpagesize(), 0x10000, 0, 0); 80 vmx->vmwrite_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmwrite); 81 vmx->vmwrite_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmwrite); 82 memset(vmx->vmwrite_hva, 0, getpagesize()); 83 84 /* Setup of a region of guest memory for the VP Assist page. */ 85 vmx->vp_assist = (void *)vm_vaddr_alloc(vm, getpagesize(), 86 0x10000, 0, 0); 87 vmx->vp_assist_hva = addr_gva2hva(vm, (uintptr_t)vmx->vp_assist); 88 vmx->vp_assist_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vp_assist); 89 90 /* Setup of a region of guest memory for the enlightened VMCS. */ 91 vmx->enlightened_vmcs = (void *)vm_vaddr_alloc(vm, getpagesize(), 92 0x10000, 0, 0); 93 vmx->enlightened_vmcs_hva = 94 addr_gva2hva(vm, (uintptr_t)vmx->enlightened_vmcs); 95 vmx->enlightened_vmcs_gpa = 96 addr_gva2gpa(vm, (uintptr_t)vmx->enlightened_vmcs); 97 98 *p_vmx_gva = vmx_gva; 99 return vmx; 100 } 101 102 bool prepare_for_vmx_operation(struct vmx_pages *vmx) 103 { 104 uint64_t feature_control; 105 uint64_t required; 106 unsigned long cr0; 107 unsigned long cr4; 108 109 /* 110 * Ensure bits in CR0 and CR4 are valid in VMX operation: 111 * - Bit X is 1 in _FIXED0: bit X is fixed to 1 in CRx. 112 * - Bit X is 0 in _FIXED1: bit X is fixed to 0 in CRx. 113 */ 114 __asm__ __volatile__("mov %%cr0, %0" : "=r"(cr0) : : "memory"); 115 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1); 116 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0); 117 __asm__ __volatile__("mov %0, %%cr0" : : "r"(cr0) : "memory"); 118 119 __asm__ __volatile__("mov %%cr4, %0" : "=r"(cr4) : : "memory"); 120 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1); 121 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0); 122 /* Enable VMX operation */ 123 cr4 |= X86_CR4_VMXE; 124 __asm__ __volatile__("mov %0, %%cr4" : : "r"(cr4) : "memory"); 125 126 /* 127 * Configure IA32_FEATURE_CONTROL MSR to allow VMXON: 128 * Bit 0: Lock bit. If clear, VMXON causes a #GP. 129 * Bit 2: Enables VMXON outside of SMX operation. If clear, VMXON 130 * outside of SMX causes a #GP. 131 */ 132 required = FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 133 required |= FEATURE_CONTROL_LOCKED; 134 feature_control = rdmsr(MSR_IA32_FEATURE_CONTROL); 135 if ((feature_control & required) != required) 136 wrmsr(MSR_IA32_FEATURE_CONTROL, feature_control | required); 137 138 /* Enter VMX root operation. */ 139 *(uint32_t *)(vmx->vmxon) = vmcs_revision(); 140 if (vmxon(vmx->vmxon_gpa)) 141 return false; 142 143 return true; 144 } 145 146 bool load_vmcs(struct vmx_pages *vmx) 147 { 148 if (!enable_evmcs) { 149 /* Load a VMCS. */ 150 *(uint32_t *)(vmx->vmcs) = vmcs_revision(); 151 if (vmclear(vmx->vmcs_gpa)) 152 return false; 153 154 if (vmptrld(vmx->vmcs_gpa)) 155 return false; 156 157 /* Setup shadow VMCS, do not load it yet. */ 158 *(uint32_t *)(vmx->shadow_vmcs) = 159 vmcs_revision() | 0x80000000ul; 160 if (vmclear(vmx->shadow_vmcs_gpa)) 161 return false; 162 } else { 163 if (evmcs_vmptrld(vmx->enlightened_vmcs_gpa, 164 vmx->enlightened_vmcs)) 165 return false; 166 current_evmcs->revision_id = vmcs_revision(); 167 } 168 169 return true; 170 } 171 172 /* 173 * Initialize the control fields to the most basic settings possible. 174 */ 175 static inline void init_vmcs_control_fields(struct vmx_pages *vmx) 176 { 177 vmwrite(VIRTUAL_PROCESSOR_ID, 0); 178 vmwrite(POSTED_INTR_NV, 0); 179 180 vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS)); 181 if (!vmwrite(SECONDARY_VM_EXEC_CONTROL, 0)) 182 vmwrite(CPU_BASED_VM_EXEC_CONTROL, 183 rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); 184 else 185 vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS)); 186 vmwrite(EXCEPTION_BITMAP, 0); 187 vmwrite(PAGE_FAULT_ERROR_CODE_MASK, 0); 188 vmwrite(PAGE_FAULT_ERROR_CODE_MATCH, -1); /* Never match */ 189 vmwrite(CR3_TARGET_COUNT, 0); 190 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) | 191 VM_EXIT_HOST_ADDR_SPACE_SIZE); /* 64-bit host */ 192 vmwrite(VM_EXIT_MSR_STORE_COUNT, 0); 193 vmwrite(VM_EXIT_MSR_LOAD_COUNT, 0); 194 vmwrite(VM_ENTRY_CONTROLS, rdmsr(MSR_IA32_VMX_ENTRY_CTLS) | 195 VM_ENTRY_IA32E_MODE); /* 64-bit guest */ 196 vmwrite(VM_ENTRY_MSR_LOAD_COUNT, 0); 197 vmwrite(VM_ENTRY_INTR_INFO_FIELD, 0); 198 vmwrite(TPR_THRESHOLD, 0); 199 200 vmwrite(CR0_GUEST_HOST_MASK, 0); 201 vmwrite(CR4_GUEST_HOST_MASK, 0); 202 vmwrite(CR0_READ_SHADOW, get_cr0()); 203 vmwrite(CR4_READ_SHADOW, get_cr4()); 204 205 vmwrite(MSR_BITMAP, vmx->msr_gpa); 206 vmwrite(VMREAD_BITMAP, vmx->vmread_gpa); 207 vmwrite(VMWRITE_BITMAP, vmx->vmwrite_gpa); 208 } 209 210 /* 211 * Initialize the host state fields based on the current host state, with 212 * the exception of HOST_RSP and HOST_RIP, which should be set by vmlaunch 213 * or vmresume. 214 */ 215 static inline void init_vmcs_host_state(void) 216 { 217 uint32_t exit_controls = vmreadz(VM_EXIT_CONTROLS); 218 219 vmwrite(HOST_ES_SELECTOR, get_es()); 220 vmwrite(HOST_CS_SELECTOR, get_cs()); 221 vmwrite(HOST_SS_SELECTOR, get_ss()); 222 vmwrite(HOST_DS_SELECTOR, get_ds()); 223 vmwrite(HOST_FS_SELECTOR, get_fs()); 224 vmwrite(HOST_GS_SELECTOR, get_gs()); 225 vmwrite(HOST_TR_SELECTOR, get_tr()); 226 227 if (exit_controls & VM_EXIT_LOAD_IA32_PAT) 228 vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT)); 229 if (exit_controls & VM_EXIT_LOAD_IA32_EFER) 230 vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER)); 231 if (exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 232 vmwrite(HOST_IA32_PERF_GLOBAL_CTRL, 233 rdmsr(MSR_CORE_PERF_GLOBAL_CTRL)); 234 235 vmwrite(HOST_IA32_SYSENTER_CS, rdmsr(MSR_IA32_SYSENTER_CS)); 236 237 vmwrite(HOST_CR0, get_cr0()); 238 vmwrite(HOST_CR3, get_cr3()); 239 vmwrite(HOST_CR4, get_cr4()); 240 vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE)); 241 vmwrite(HOST_GS_BASE, rdmsr(MSR_GS_BASE)); 242 vmwrite(HOST_TR_BASE, 243 get_desc64_base((struct desc64 *)(get_gdt_base() + get_tr()))); 244 vmwrite(HOST_GDTR_BASE, get_gdt_base()); 245 vmwrite(HOST_IDTR_BASE, get_idt_base()); 246 vmwrite(HOST_IA32_SYSENTER_ESP, rdmsr(MSR_IA32_SYSENTER_ESP)); 247 vmwrite(HOST_IA32_SYSENTER_EIP, rdmsr(MSR_IA32_SYSENTER_EIP)); 248 } 249 250 /* 251 * Initialize the guest state fields essentially as a clone of 252 * the host state fields. Some host state fields have fixed 253 * values, and we set the corresponding guest state fields accordingly. 254 */ 255 static inline void init_vmcs_guest_state(void *rip, void *rsp) 256 { 257 vmwrite(GUEST_ES_SELECTOR, vmreadz(HOST_ES_SELECTOR)); 258 vmwrite(GUEST_CS_SELECTOR, vmreadz(HOST_CS_SELECTOR)); 259 vmwrite(GUEST_SS_SELECTOR, vmreadz(HOST_SS_SELECTOR)); 260 vmwrite(GUEST_DS_SELECTOR, vmreadz(HOST_DS_SELECTOR)); 261 vmwrite(GUEST_FS_SELECTOR, vmreadz(HOST_FS_SELECTOR)); 262 vmwrite(GUEST_GS_SELECTOR, vmreadz(HOST_GS_SELECTOR)); 263 vmwrite(GUEST_LDTR_SELECTOR, 0); 264 vmwrite(GUEST_TR_SELECTOR, vmreadz(HOST_TR_SELECTOR)); 265 vmwrite(GUEST_INTR_STATUS, 0); 266 vmwrite(GUEST_PML_INDEX, 0); 267 268 vmwrite(VMCS_LINK_POINTER, -1ll); 269 vmwrite(GUEST_IA32_DEBUGCTL, 0); 270 vmwrite(GUEST_IA32_PAT, vmreadz(HOST_IA32_PAT)); 271 vmwrite(GUEST_IA32_EFER, vmreadz(HOST_IA32_EFER)); 272 vmwrite(GUEST_IA32_PERF_GLOBAL_CTRL, 273 vmreadz(HOST_IA32_PERF_GLOBAL_CTRL)); 274 275 vmwrite(GUEST_ES_LIMIT, -1); 276 vmwrite(GUEST_CS_LIMIT, -1); 277 vmwrite(GUEST_SS_LIMIT, -1); 278 vmwrite(GUEST_DS_LIMIT, -1); 279 vmwrite(GUEST_FS_LIMIT, -1); 280 vmwrite(GUEST_GS_LIMIT, -1); 281 vmwrite(GUEST_LDTR_LIMIT, -1); 282 vmwrite(GUEST_TR_LIMIT, 0x67); 283 vmwrite(GUEST_GDTR_LIMIT, 0xffff); 284 vmwrite(GUEST_IDTR_LIMIT, 0xffff); 285 vmwrite(GUEST_ES_AR_BYTES, 286 vmreadz(GUEST_ES_SELECTOR) == 0 ? 0x10000 : 0xc093); 287 vmwrite(GUEST_CS_AR_BYTES, 0xa09b); 288 vmwrite(GUEST_SS_AR_BYTES, 0xc093); 289 vmwrite(GUEST_DS_AR_BYTES, 290 vmreadz(GUEST_DS_SELECTOR) == 0 ? 0x10000 : 0xc093); 291 vmwrite(GUEST_FS_AR_BYTES, 292 vmreadz(GUEST_FS_SELECTOR) == 0 ? 0x10000 : 0xc093); 293 vmwrite(GUEST_GS_AR_BYTES, 294 vmreadz(GUEST_GS_SELECTOR) == 0 ? 0x10000 : 0xc093); 295 vmwrite(GUEST_LDTR_AR_BYTES, 0x10000); 296 vmwrite(GUEST_TR_AR_BYTES, 0x8b); 297 vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0); 298 vmwrite(GUEST_ACTIVITY_STATE, 0); 299 vmwrite(GUEST_SYSENTER_CS, vmreadz(HOST_IA32_SYSENTER_CS)); 300 vmwrite(VMX_PREEMPTION_TIMER_VALUE, 0); 301 302 vmwrite(GUEST_CR0, vmreadz(HOST_CR0)); 303 vmwrite(GUEST_CR3, vmreadz(HOST_CR3)); 304 vmwrite(GUEST_CR4, vmreadz(HOST_CR4)); 305 vmwrite(GUEST_ES_BASE, 0); 306 vmwrite(GUEST_CS_BASE, 0); 307 vmwrite(GUEST_SS_BASE, 0); 308 vmwrite(GUEST_DS_BASE, 0); 309 vmwrite(GUEST_FS_BASE, vmreadz(HOST_FS_BASE)); 310 vmwrite(GUEST_GS_BASE, vmreadz(HOST_GS_BASE)); 311 vmwrite(GUEST_LDTR_BASE, 0); 312 vmwrite(GUEST_TR_BASE, vmreadz(HOST_TR_BASE)); 313 vmwrite(GUEST_GDTR_BASE, vmreadz(HOST_GDTR_BASE)); 314 vmwrite(GUEST_IDTR_BASE, vmreadz(HOST_IDTR_BASE)); 315 vmwrite(GUEST_DR7, 0x400); 316 vmwrite(GUEST_RSP, (uint64_t)rsp); 317 vmwrite(GUEST_RIP, (uint64_t)rip); 318 vmwrite(GUEST_RFLAGS, 2); 319 vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, 0); 320 vmwrite(GUEST_SYSENTER_ESP, vmreadz(HOST_IA32_SYSENTER_ESP)); 321 vmwrite(GUEST_SYSENTER_EIP, vmreadz(HOST_IA32_SYSENTER_EIP)); 322 } 323 324 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp) 325 { 326 init_vmcs_control_fields(vmx); 327 init_vmcs_host_state(); 328 init_vmcs_guest_state(guest_rip, guest_rsp); 329 } 330