1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RISC-V code 4 * 5 * Copyright (C) 2021 Western Digital Corporation or its affiliates. 6 */ 7 8 #include <linux/compiler.h> 9 #include <assert.h> 10 11 #include "kvm_util.h" 12 #include "processor.h" 13 14 #define DEFAULT_RISCV_GUEST_STACK_VADDR_MIN 0xac0000 15 16 static uint64_t page_align(struct kvm_vm *vm, uint64_t v) 17 { 18 return (v + vm->page_size) & ~(vm->page_size - 1); 19 } 20 21 static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry) 22 { 23 return ((entry & PGTBL_PTE_ADDR_MASK) >> PGTBL_PTE_ADDR_SHIFT) << 24 PGTBL_PAGE_SIZE_SHIFT; 25 } 26 27 static uint64_t ptrs_per_pte(struct kvm_vm *vm) 28 { 29 return PGTBL_PAGE_SIZE / sizeof(uint64_t); 30 } 31 32 static uint64_t pte_index_mask[] = { 33 PGTBL_L0_INDEX_MASK, 34 PGTBL_L1_INDEX_MASK, 35 PGTBL_L2_INDEX_MASK, 36 PGTBL_L3_INDEX_MASK, 37 }; 38 39 static uint32_t pte_index_shift[] = { 40 PGTBL_L0_INDEX_SHIFT, 41 PGTBL_L1_INDEX_SHIFT, 42 PGTBL_L2_INDEX_SHIFT, 43 PGTBL_L3_INDEX_SHIFT, 44 }; 45 46 static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level) 47 { 48 TEST_ASSERT(level > -1, 49 "Negative page table level (%d) not possible", level); 50 TEST_ASSERT(level < vm->pgtable_levels, 51 "Invalid page table level (%d)", level); 52 53 return (gva & pte_index_mask[level]) >> pte_index_shift[level]; 54 } 55 56 void virt_arch_pgd_alloc(struct kvm_vm *vm) 57 { 58 if (!vm->pgd_created) { 59 vm_paddr_t paddr = vm_phy_pages_alloc(vm, 60 page_align(vm, ptrs_per_pte(vm) * 8) / vm->page_size, 61 KVM_GUEST_PAGE_TABLE_MIN_PADDR, 0); 62 vm->pgd = paddr; 63 vm->pgd_created = true; 64 } 65 } 66 67 void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr) 68 { 69 uint64_t *ptep, next_ppn; 70 int level = vm->pgtable_levels - 1; 71 72 TEST_ASSERT((vaddr % vm->page_size) == 0, 73 "Virtual address not on page boundary,\n" 74 " vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size); 75 TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, 76 (vaddr >> vm->page_shift)), 77 "Invalid virtual address, vaddr: 0x%lx", vaddr); 78 TEST_ASSERT((paddr % vm->page_size) == 0, 79 "Physical address not on page boundary,\n" 80 " paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size); 81 TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn, 82 "Physical address beyond maximum supported,\n" 83 " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", 84 paddr, vm->max_gfn, vm->page_size); 85 86 ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, vaddr, level) * 8; 87 if (!*ptep) { 88 next_ppn = vm_alloc_page_table(vm) >> PGTBL_PAGE_SIZE_SHIFT; 89 *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) | 90 PGTBL_PTE_VALID_MASK; 91 } 92 level--; 93 94 while (level > -1) { 95 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + 96 pte_index(vm, vaddr, level) * 8; 97 if (!*ptep && level > 0) { 98 next_ppn = vm_alloc_page_table(vm) >> 99 PGTBL_PAGE_SIZE_SHIFT; 100 *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) | 101 PGTBL_PTE_VALID_MASK; 102 } 103 level--; 104 } 105 106 paddr = paddr >> PGTBL_PAGE_SIZE_SHIFT; 107 *ptep = (paddr << PGTBL_PTE_ADDR_SHIFT) | 108 PGTBL_PTE_PERM_MASK | PGTBL_PTE_VALID_MASK; 109 } 110 111 vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva) 112 { 113 uint64_t *ptep; 114 int level = vm->pgtable_levels - 1; 115 116 if (!vm->pgd_created) 117 goto unmapped_gva; 118 119 ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, gva, level) * 8; 120 if (!ptep) 121 goto unmapped_gva; 122 level--; 123 124 while (level > -1) { 125 ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + 126 pte_index(vm, gva, level) * 8; 127 if (!ptep) 128 goto unmapped_gva; 129 level--; 130 } 131 132 return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1)); 133 134 unmapped_gva: 135 TEST_FAIL("No mapping for vm virtual address gva: 0x%lx level: %d", 136 gva, level); 137 exit(1); 138 } 139 140 static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, 141 uint64_t page, int level) 142 { 143 #ifdef DEBUG 144 static const char *const type[] = { "pte", "pmd", "pud", "p4d"}; 145 uint64_t pte, *ptep; 146 147 if (level < 0) 148 return; 149 150 for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) { 151 ptep = addr_gpa2hva(vm, pte); 152 if (!*ptep) 153 continue; 154 fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "", 155 type[level], pte, *ptep, ptep); 156 pte_dump(stream, vm, indent + 1, 157 pte_addr(vm, *ptep), level - 1); 158 } 159 #endif 160 } 161 162 void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent) 163 { 164 int level = vm->pgtable_levels - 1; 165 uint64_t pgd, *ptep; 166 167 if (!vm->pgd_created) 168 return; 169 170 for (pgd = vm->pgd; pgd < vm->pgd + ptrs_per_pte(vm) * 8; pgd += 8) { 171 ptep = addr_gpa2hva(vm, pgd); 172 if (!*ptep) 173 continue; 174 fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "", 175 pgd, *ptep, ptep); 176 pte_dump(stream, vm, indent + 1, 177 pte_addr(vm, *ptep), level - 1); 178 } 179 } 180 181 void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu) 182 { 183 struct kvm_vm *vm = vcpu->vm; 184 unsigned long satp; 185 186 /* 187 * The RISC-V Sv48 MMU mode supports 56-bit physical address 188 * for 48-bit virtual address with 4KB last level page size. 189 */ 190 switch (vm->mode) { 191 case VM_MODE_P52V48_4K: 192 case VM_MODE_P48V48_4K: 193 case VM_MODE_P40V48_4K: 194 break; 195 default: 196 TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); 197 } 198 199 satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN; 200 satp |= SATP_MODE_48; 201 202 vcpu_set_reg(vcpu, RISCV_CSR_REG(satp), satp); 203 } 204 205 void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) 206 { 207 struct kvm_riscv_core core; 208 209 vcpu_get_reg(vcpu, RISCV_CORE_REG(mode), &core.mode); 210 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc), &core.regs.pc); 211 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra), &core.regs.ra); 212 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp), &core.regs.sp); 213 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp), &core.regs.gp); 214 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp), &core.regs.tp); 215 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0), &core.regs.t0); 216 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1), &core.regs.t1); 217 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2), &core.regs.t2); 218 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0), &core.regs.s0); 219 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1), &core.regs.s1); 220 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0), &core.regs.a0); 221 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1), &core.regs.a1); 222 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2), &core.regs.a2); 223 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3), &core.regs.a3); 224 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4), &core.regs.a4); 225 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5), &core.regs.a5); 226 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6), &core.regs.a6); 227 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7), &core.regs.a7); 228 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2), &core.regs.s2); 229 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3), &core.regs.s3); 230 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4), &core.regs.s4); 231 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5), &core.regs.s5); 232 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6), &core.regs.s6); 233 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7), &core.regs.s7); 234 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8), &core.regs.s8); 235 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9), &core.regs.s9); 236 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10), &core.regs.s10); 237 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11), &core.regs.s11); 238 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3), &core.regs.t3); 239 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4), &core.regs.t4); 240 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5), &core.regs.t5); 241 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6), &core.regs.t6); 242 243 fprintf(stream, 244 " MODE: 0x%lx\n", core.mode); 245 fprintf(stream, 246 " PC: 0x%016lx RA: 0x%016lx SP: 0x%016lx GP: 0x%016lx\n", 247 core.regs.pc, core.regs.ra, core.regs.sp, core.regs.gp); 248 fprintf(stream, 249 " TP: 0x%016lx T0: 0x%016lx T1: 0x%016lx T2: 0x%016lx\n", 250 core.regs.tp, core.regs.t0, core.regs.t1, core.regs.t2); 251 fprintf(stream, 252 " S0: 0x%016lx S1: 0x%016lx A0: 0x%016lx A1: 0x%016lx\n", 253 core.regs.s0, core.regs.s1, core.regs.a0, core.regs.a1); 254 fprintf(stream, 255 " A2: 0x%016lx A3: 0x%016lx A4: 0x%016lx A5: 0x%016lx\n", 256 core.regs.a2, core.regs.a3, core.regs.a4, core.regs.a5); 257 fprintf(stream, 258 " A6: 0x%016lx A7: 0x%016lx S2: 0x%016lx S3: 0x%016lx\n", 259 core.regs.a6, core.regs.a7, core.regs.s2, core.regs.s3); 260 fprintf(stream, 261 " S4: 0x%016lx S5: 0x%016lx S6: 0x%016lx S7: 0x%016lx\n", 262 core.regs.s4, core.regs.s5, core.regs.s6, core.regs.s7); 263 fprintf(stream, 264 " S8: 0x%016lx S9: 0x%016lx S10: 0x%016lx S11: 0x%016lx\n", 265 core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11); 266 fprintf(stream, 267 " T3: 0x%016lx T4: 0x%016lx T5: 0x%016lx T6: 0x%016lx\n", 268 core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6); 269 } 270 271 static void __aligned(16) guest_unexp_trap(void) 272 { 273 sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, 274 KVM_RISCV_SELFTESTS_SBI_UNEXP, 275 0, 0, 0, 0, 0, 0); 276 } 277 278 struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, 279 void *guest_code) 280 { 281 int r; 282 size_t stack_size = vm->page_size == 4096 ? 283 DEFAULT_STACK_PGS * vm->page_size : 284 vm->page_size; 285 unsigned long stack_vaddr = vm_vaddr_alloc(vm, stack_size, 286 DEFAULT_RISCV_GUEST_STACK_VADDR_MIN); 287 unsigned long current_gp = 0; 288 struct kvm_mp_state mps; 289 struct kvm_vcpu *vcpu; 290 291 vcpu = __vm_vcpu_add(vm, vcpu_id); 292 riscv_vcpu_mmu_setup(vcpu); 293 294 /* 295 * With SBI HSM support in KVM RISC-V, all secondary VCPUs are 296 * powered-off by default so we ensure that all secondary VCPUs 297 * are powered-on using KVM_SET_MP_STATE ioctl(). 298 */ 299 mps.mp_state = KVM_MP_STATE_RUNNABLE; 300 r = __vcpu_ioctl(vcpu, KVM_SET_MP_STATE, &mps); 301 TEST_ASSERT(!r, "IOCTL KVM_SET_MP_STATE failed (error %d)", r); 302 303 /* Setup global pointer of guest to be same as the host */ 304 asm volatile ( 305 "add %0, gp, zero" : "=r" (current_gp) : : "memory"); 306 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.gp), current_gp); 307 308 /* Setup stack pointer and program counter of guest */ 309 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_vaddr + stack_size); 310 vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code); 311 312 /* Setup default exception vector of guest */ 313 vcpu_set_reg(vcpu, RISCV_CSR_REG(stvec), (unsigned long)guest_unexp_trap); 314 315 return vcpu; 316 } 317 318 void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) 319 { 320 va_list ap; 321 uint64_t id = RISCV_CORE_REG(regs.a0); 322 int i; 323 324 TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n" 325 " num: %u\n", num); 326 327 va_start(ap, num); 328 329 for (i = 0; i < num; i++) { 330 switch (i) { 331 case 0: 332 id = RISCV_CORE_REG(regs.a0); 333 break; 334 case 1: 335 id = RISCV_CORE_REG(regs.a1); 336 break; 337 case 2: 338 id = RISCV_CORE_REG(regs.a2); 339 break; 340 case 3: 341 id = RISCV_CORE_REG(regs.a3); 342 break; 343 case 4: 344 id = RISCV_CORE_REG(regs.a4); 345 break; 346 case 5: 347 id = RISCV_CORE_REG(regs.a5); 348 break; 349 case 6: 350 id = RISCV_CORE_REG(regs.a6); 351 break; 352 case 7: 353 id = RISCV_CORE_REG(regs.a7); 354 break; 355 } 356 vcpu_set_reg(vcpu, id, va_arg(ap, uint64_t)); 357 } 358 359 va_end(ap); 360 } 361 362 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu) 363 { 364 } 365