1 /* 2 * tools/testing/selftests/kvm/include/x86_64/vmx.h 3 * 4 * Copyright (C) 2018, Google LLC. 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. 7 * 8 */ 9 10 #ifndef SELFTEST_KVM_VMX_H 11 #define SELFTEST_KVM_VMX_H 12 13 #include <stdint.h> 14 #include "processor.h" 15 16 #define CPUID_VMX_BIT 5 17 18 #define CPUID_VMX (1 << 5) 19 20 /* 21 * Definitions of Primary Processor-Based VM-Execution Controls. 22 */ 23 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 24 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008 25 #define CPU_BASED_HLT_EXITING 0x00000080 26 #define CPU_BASED_INVLPG_EXITING 0x00000200 27 #define CPU_BASED_MWAIT_EXITING 0x00000400 28 #define CPU_BASED_RDPMC_EXITING 0x00000800 29 #define CPU_BASED_RDTSC_EXITING 0x00001000 30 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000 31 #define CPU_BASED_CR3_STORE_EXITING 0x00010000 32 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 33 #define CPU_BASED_CR8_STORE_EXITING 0x00100000 34 #define CPU_BASED_TPR_SHADOW 0x00200000 35 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 36 #define CPU_BASED_MOV_DR_EXITING 0x00800000 37 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000 38 #define CPU_BASED_USE_IO_BITMAPS 0x02000000 39 #define CPU_BASED_MONITOR_TRAP 0x08000000 40 #define CPU_BASED_USE_MSR_BITMAPS 0x10000000 41 #define CPU_BASED_MONITOR_EXITING 0x20000000 42 #define CPU_BASED_PAUSE_EXITING 0x40000000 43 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 44 45 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172 46 47 /* 48 * Definitions of Secondary Processor-Based VM-Execution Controls. 49 */ 50 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 51 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002 52 #define SECONDARY_EXEC_DESC 0x00000004 53 #define SECONDARY_EXEC_RDTSCP 0x00000008 54 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 55 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020 56 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 57 #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 58 #define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 59 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 60 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 61 #define SECONDARY_EXEC_RDRAND_EXITING 0x00000800 62 #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 63 #define SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 64 #define SECONDARY_EXEC_SHADOW_VMCS 0x00004000 65 #define SECONDARY_EXEC_RDSEED_EXITING 0x00010000 66 #define SECONDARY_EXEC_ENABLE_PML 0x00020000 67 #define SECONDARY_EPT_VE 0x00040000 68 #define SECONDARY_ENABLE_XSAV_RESTORE 0x00100000 69 #define SECONDARY_EXEC_TSC_SCALING 0x02000000 70 71 #define PIN_BASED_EXT_INTR_MASK 0x00000001 72 #define PIN_BASED_NMI_EXITING 0x00000008 73 #define PIN_BASED_VIRTUAL_NMIS 0x00000020 74 #define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 75 #define PIN_BASED_POSTED_INTR 0x00000080 76 77 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016 78 79 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 80 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 81 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 82 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 83 #define VM_EXIT_SAVE_IA32_PAT 0x00040000 84 #define VM_EXIT_LOAD_IA32_PAT 0x00080000 85 #define VM_EXIT_SAVE_IA32_EFER 0x00100000 86 #define VM_EXIT_LOAD_IA32_EFER 0x00200000 87 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 88 89 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff 90 91 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 92 #define VM_ENTRY_IA32E_MODE 0x00000200 93 #define VM_ENTRY_SMM 0x00000400 94 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 95 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 96 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000 97 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000 98 99 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff 100 101 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f 102 #define VMX_MISC_SAVE_EFER_LMA 0x00000020 103 104 #define EXIT_REASON_FAILED_VMENTRY 0x80000000 105 #define EXIT_REASON_EXCEPTION_NMI 0 106 #define EXIT_REASON_EXTERNAL_INTERRUPT 1 107 #define EXIT_REASON_TRIPLE_FAULT 2 108 #define EXIT_REASON_PENDING_INTERRUPT 7 109 #define EXIT_REASON_NMI_WINDOW 8 110 #define EXIT_REASON_TASK_SWITCH 9 111 #define EXIT_REASON_CPUID 10 112 #define EXIT_REASON_HLT 12 113 #define EXIT_REASON_INVD 13 114 #define EXIT_REASON_INVLPG 14 115 #define EXIT_REASON_RDPMC 15 116 #define EXIT_REASON_RDTSC 16 117 #define EXIT_REASON_VMCALL 18 118 #define EXIT_REASON_VMCLEAR 19 119 #define EXIT_REASON_VMLAUNCH 20 120 #define EXIT_REASON_VMPTRLD 21 121 #define EXIT_REASON_VMPTRST 22 122 #define EXIT_REASON_VMREAD 23 123 #define EXIT_REASON_VMRESUME 24 124 #define EXIT_REASON_VMWRITE 25 125 #define EXIT_REASON_VMOFF 26 126 #define EXIT_REASON_VMON 27 127 #define EXIT_REASON_CR_ACCESS 28 128 #define EXIT_REASON_DR_ACCESS 29 129 #define EXIT_REASON_IO_INSTRUCTION 30 130 #define EXIT_REASON_MSR_READ 31 131 #define EXIT_REASON_MSR_WRITE 32 132 #define EXIT_REASON_INVALID_STATE 33 133 #define EXIT_REASON_MWAIT_INSTRUCTION 36 134 #define EXIT_REASON_MONITOR_INSTRUCTION 39 135 #define EXIT_REASON_PAUSE_INSTRUCTION 40 136 #define EXIT_REASON_MCE_DURING_VMENTRY 41 137 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43 138 #define EXIT_REASON_APIC_ACCESS 44 139 #define EXIT_REASON_EOI_INDUCED 45 140 #define EXIT_REASON_EPT_VIOLATION 48 141 #define EXIT_REASON_EPT_MISCONFIG 49 142 #define EXIT_REASON_INVEPT 50 143 #define EXIT_REASON_RDTSCP 51 144 #define EXIT_REASON_PREEMPTION_TIMER 52 145 #define EXIT_REASON_INVVPID 53 146 #define EXIT_REASON_WBINVD 54 147 #define EXIT_REASON_XSETBV 55 148 #define EXIT_REASON_APIC_WRITE 56 149 #define EXIT_REASON_INVPCID 58 150 #define EXIT_REASON_PML_FULL 62 151 #define EXIT_REASON_XSAVES 63 152 #define EXIT_REASON_XRSTORS 64 153 #define LAST_EXIT_REASON 64 154 155 enum vmcs_field { 156 VIRTUAL_PROCESSOR_ID = 0x00000000, 157 POSTED_INTR_NV = 0x00000002, 158 GUEST_ES_SELECTOR = 0x00000800, 159 GUEST_CS_SELECTOR = 0x00000802, 160 GUEST_SS_SELECTOR = 0x00000804, 161 GUEST_DS_SELECTOR = 0x00000806, 162 GUEST_FS_SELECTOR = 0x00000808, 163 GUEST_GS_SELECTOR = 0x0000080a, 164 GUEST_LDTR_SELECTOR = 0x0000080c, 165 GUEST_TR_SELECTOR = 0x0000080e, 166 GUEST_INTR_STATUS = 0x00000810, 167 GUEST_PML_INDEX = 0x00000812, 168 HOST_ES_SELECTOR = 0x00000c00, 169 HOST_CS_SELECTOR = 0x00000c02, 170 HOST_SS_SELECTOR = 0x00000c04, 171 HOST_DS_SELECTOR = 0x00000c06, 172 HOST_FS_SELECTOR = 0x00000c08, 173 HOST_GS_SELECTOR = 0x00000c0a, 174 HOST_TR_SELECTOR = 0x00000c0c, 175 IO_BITMAP_A = 0x00002000, 176 IO_BITMAP_A_HIGH = 0x00002001, 177 IO_BITMAP_B = 0x00002002, 178 IO_BITMAP_B_HIGH = 0x00002003, 179 MSR_BITMAP = 0x00002004, 180 MSR_BITMAP_HIGH = 0x00002005, 181 VM_EXIT_MSR_STORE_ADDR = 0x00002006, 182 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007, 183 VM_EXIT_MSR_LOAD_ADDR = 0x00002008, 184 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009, 185 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a, 186 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b, 187 PML_ADDRESS = 0x0000200e, 188 PML_ADDRESS_HIGH = 0x0000200f, 189 TSC_OFFSET = 0x00002010, 190 TSC_OFFSET_HIGH = 0x00002011, 191 VIRTUAL_APIC_PAGE_ADDR = 0x00002012, 192 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013, 193 APIC_ACCESS_ADDR = 0x00002014, 194 APIC_ACCESS_ADDR_HIGH = 0x00002015, 195 POSTED_INTR_DESC_ADDR = 0x00002016, 196 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017, 197 EPT_POINTER = 0x0000201a, 198 EPT_POINTER_HIGH = 0x0000201b, 199 EOI_EXIT_BITMAP0 = 0x0000201c, 200 EOI_EXIT_BITMAP0_HIGH = 0x0000201d, 201 EOI_EXIT_BITMAP1 = 0x0000201e, 202 EOI_EXIT_BITMAP1_HIGH = 0x0000201f, 203 EOI_EXIT_BITMAP2 = 0x00002020, 204 EOI_EXIT_BITMAP2_HIGH = 0x00002021, 205 EOI_EXIT_BITMAP3 = 0x00002022, 206 EOI_EXIT_BITMAP3_HIGH = 0x00002023, 207 VMREAD_BITMAP = 0x00002026, 208 VMREAD_BITMAP_HIGH = 0x00002027, 209 VMWRITE_BITMAP = 0x00002028, 210 VMWRITE_BITMAP_HIGH = 0x00002029, 211 XSS_EXIT_BITMAP = 0x0000202C, 212 XSS_EXIT_BITMAP_HIGH = 0x0000202D, 213 TSC_MULTIPLIER = 0x00002032, 214 TSC_MULTIPLIER_HIGH = 0x00002033, 215 GUEST_PHYSICAL_ADDRESS = 0x00002400, 216 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401, 217 VMCS_LINK_POINTER = 0x00002800, 218 VMCS_LINK_POINTER_HIGH = 0x00002801, 219 GUEST_IA32_DEBUGCTL = 0x00002802, 220 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803, 221 GUEST_IA32_PAT = 0x00002804, 222 GUEST_IA32_PAT_HIGH = 0x00002805, 223 GUEST_IA32_EFER = 0x00002806, 224 GUEST_IA32_EFER_HIGH = 0x00002807, 225 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808, 226 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809, 227 GUEST_PDPTR0 = 0x0000280a, 228 GUEST_PDPTR0_HIGH = 0x0000280b, 229 GUEST_PDPTR1 = 0x0000280c, 230 GUEST_PDPTR1_HIGH = 0x0000280d, 231 GUEST_PDPTR2 = 0x0000280e, 232 GUEST_PDPTR2_HIGH = 0x0000280f, 233 GUEST_PDPTR3 = 0x00002810, 234 GUEST_PDPTR3_HIGH = 0x00002811, 235 GUEST_BNDCFGS = 0x00002812, 236 GUEST_BNDCFGS_HIGH = 0x00002813, 237 HOST_IA32_PAT = 0x00002c00, 238 HOST_IA32_PAT_HIGH = 0x00002c01, 239 HOST_IA32_EFER = 0x00002c02, 240 HOST_IA32_EFER_HIGH = 0x00002c03, 241 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04, 242 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05, 243 PIN_BASED_VM_EXEC_CONTROL = 0x00004000, 244 CPU_BASED_VM_EXEC_CONTROL = 0x00004002, 245 EXCEPTION_BITMAP = 0x00004004, 246 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006, 247 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008, 248 CR3_TARGET_COUNT = 0x0000400a, 249 VM_EXIT_CONTROLS = 0x0000400c, 250 VM_EXIT_MSR_STORE_COUNT = 0x0000400e, 251 VM_EXIT_MSR_LOAD_COUNT = 0x00004010, 252 VM_ENTRY_CONTROLS = 0x00004012, 253 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014, 254 VM_ENTRY_INTR_INFO_FIELD = 0x00004016, 255 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018, 256 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a, 257 TPR_THRESHOLD = 0x0000401c, 258 SECONDARY_VM_EXEC_CONTROL = 0x0000401e, 259 PLE_GAP = 0x00004020, 260 PLE_WINDOW = 0x00004022, 261 VM_INSTRUCTION_ERROR = 0x00004400, 262 VM_EXIT_REASON = 0x00004402, 263 VM_EXIT_INTR_INFO = 0x00004404, 264 VM_EXIT_INTR_ERROR_CODE = 0x00004406, 265 IDT_VECTORING_INFO_FIELD = 0x00004408, 266 IDT_VECTORING_ERROR_CODE = 0x0000440a, 267 VM_EXIT_INSTRUCTION_LEN = 0x0000440c, 268 VMX_INSTRUCTION_INFO = 0x0000440e, 269 GUEST_ES_LIMIT = 0x00004800, 270 GUEST_CS_LIMIT = 0x00004802, 271 GUEST_SS_LIMIT = 0x00004804, 272 GUEST_DS_LIMIT = 0x00004806, 273 GUEST_FS_LIMIT = 0x00004808, 274 GUEST_GS_LIMIT = 0x0000480a, 275 GUEST_LDTR_LIMIT = 0x0000480c, 276 GUEST_TR_LIMIT = 0x0000480e, 277 GUEST_GDTR_LIMIT = 0x00004810, 278 GUEST_IDTR_LIMIT = 0x00004812, 279 GUEST_ES_AR_BYTES = 0x00004814, 280 GUEST_CS_AR_BYTES = 0x00004816, 281 GUEST_SS_AR_BYTES = 0x00004818, 282 GUEST_DS_AR_BYTES = 0x0000481a, 283 GUEST_FS_AR_BYTES = 0x0000481c, 284 GUEST_GS_AR_BYTES = 0x0000481e, 285 GUEST_LDTR_AR_BYTES = 0x00004820, 286 GUEST_TR_AR_BYTES = 0x00004822, 287 GUEST_INTERRUPTIBILITY_INFO = 0x00004824, 288 GUEST_ACTIVITY_STATE = 0X00004826, 289 GUEST_SYSENTER_CS = 0x0000482A, 290 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E, 291 HOST_IA32_SYSENTER_CS = 0x00004c00, 292 CR0_GUEST_HOST_MASK = 0x00006000, 293 CR4_GUEST_HOST_MASK = 0x00006002, 294 CR0_READ_SHADOW = 0x00006004, 295 CR4_READ_SHADOW = 0x00006006, 296 CR3_TARGET_VALUE0 = 0x00006008, 297 CR3_TARGET_VALUE1 = 0x0000600a, 298 CR3_TARGET_VALUE2 = 0x0000600c, 299 CR3_TARGET_VALUE3 = 0x0000600e, 300 EXIT_QUALIFICATION = 0x00006400, 301 GUEST_LINEAR_ADDRESS = 0x0000640a, 302 GUEST_CR0 = 0x00006800, 303 GUEST_CR3 = 0x00006802, 304 GUEST_CR4 = 0x00006804, 305 GUEST_ES_BASE = 0x00006806, 306 GUEST_CS_BASE = 0x00006808, 307 GUEST_SS_BASE = 0x0000680a, 308 GUEST_DS_BASE = 0x0000680c, 309 GUEST_FS_BASE = 0x0000680e, 310 GUEST_GS_BASE = 0x00006810, 311 GUEST_LDTR_BASE = 0x00006812, 312 GUEST_TR_BASE = 0x00006814, 313 GUEST_GDTR_BASE = 0x00006816, 314 GUEST_IDTR_BASE = 0x00006818, 315 GUEST_DR7 = 0x0000681a, 316 GUEST_RSP = 0x0000681c, 317 GUEST_RIP = 0x0000681e, 318 GUEST_RFLAGS = 0x00006820, 319 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822, 320 GUEST_SYSENTER_ESP = 0x00006824, 321 GUEST_SYSENTER_EIP = 0x00006826, 322 HOST_CR0 = 0x00006c00, 323 HOST_CR3 = 0x00006c02, 324 HOST_CR4 = 0x00006c04, 325 HOST_FS_BASE = 0x00006c06, 326 HOST_GS_BASE = 0x00006c08, 327 HOST_TR_BASE = 0x00006c0a, 328 HOST_GDTR_BASE = 0x00006c0c, 329 HOST_IDTR_BASE = 0x00006c0e, 330 HOST_IA32_SYSENTER_ESP = 0x00006c10, 331 HOST_IA32_SYSENTER_EIP = 0x00006c12, 332 HOST_RSP = 0x00006c14, 333 HOST_RIP = 0x00006c16, 334 }; 335 336 struct vmx_msr_entry { 337 uint32_t index; 338 uint32_t reserved; 339 uint64_t value; 340 } __attribute__ ((aligned(16))); 341 342 #include "evmcs.h" 343 344 static inline int vmxon(uint64_t phys) 345 { 346 uint8_t ret; 347 348 __asm__ __volatile__ ("vmxon %[pa]; setna %[ret]" 349 : [ret]"=rm"(ret) 350 : [pa]"m"(phys) 351 : "cc", "memory"); 352 353 return ret; 354 } 355 356 static inline void vmxoff(void) 357 { 358 __asm__ __volatile__("vmxoff"); 359 } 360 361 static inline int vmclear(uint64_t vmcs_pa) 362 { 363 uint8_t ret; 364 365 __asm__ __volatile__ ("vmclear %[pa]; setna %[ret]" 366 : [ret]"=rm"(ret) 367 : [pa]"m"(vmcs_pa) 368 : "cc", "memory"); 369 370 return ret; 371 } 372 373 static inline int vmptrld(uint64_t vmcs_pa) 374 { 375 uint8_t ret; 376 377 if (enable_evmcs) 378 return -1; 379 380 __asm__ __volatile__ ("vmptrld %[pa]; setna %[ret]" 381 : [ret]"=rm"(ret) 382 : [pa]"m"(vmcs_pa) 383 : "cc", "memory"); 384 385 return ret; 386 } 387 388 static inline int vmptrst(uint64_t *value) 389 { 390 uint64_t tmp; 391 uint8_t ret; 392 393 if (enable_evmcs) 394 return evmcs_vmptrst(value); 395 396 __asm__ __volatile__("vmptrst %[value]; setna %[ret]" 397 : [value]"=m"(tmp), [ret]"=rm"(ret) 398 : : "cc", "memory"); 399 400 *value = tmp; 401 return ret; 402 } 403 404 /* 405 * A wrapper around vmptrst that ignores errors and returns zero if the 406 * vmptrst instruction fails. 407 */ 408 static inline uint64_t vmptrstz(void) 409 { 410 uint64_t value = 0; 411 vmptrst(&value); 412 return value; 413 } 414 415 /* 416 * No guest state (e.g. GPRs) is established by this vmlaunch. 417 */ 418 static inline int vmlaunch(void) 419 { 420 int ret; 421 422 if (enable_evmcs) 423 return evmcs_vmlaunch(); 424 425 __asm__ __volatile__("push %%rbp;" 426 "push %%rcx;" 427 "push %%rdx;" 428 "push %%rsi;" 429 "push %%rdi;" 430 "push $0;" 431 "vmwrite %%rsp, %[host_rsp];" 432 "lea 1f(%%rip), %%rax;" 433 "vmwrite %%rax, %[host_rip];" 434 "vmlaunch;" 435 "incq (%%rsp);" 436 "1: pop %%rax;" 437 "pop %%rdi;" 438 "pop %%rsi;" 439 "pop %%rdx;" 440 "pop %%rcx;" 441 "pop %%rbp;" 442 : [ret]"=&a"(ret) 443 : [host_rsp]"r"((uint64_t)HOST_RSP), 444 [host_rip]"r"((uint64_t)HOST_RIP) 445 : "memory", "cc", "rbx", "r8", "r9", "r10", 446 "r11", "r12", "r13", "r14", "r15"); 447 return ret; 448 } 449 450 /* 451 * No guest state (e.g. GPRs) is established by this vmresume. 452 */ 453 static inline int vmresume(void) 454 { 455 int ret; 456 457 if (enable_evmcs) 458 return evmcs_vmresume(); 459 460 __asm__ __volatile__("push %%rbp;" 461 "push %%rcx;" 462 "push %%rdx;" 463 "push %%rsi;" 464 "push %%rdi;" 465 "push $0;" 466 "vmwrite %%rsp, %[host_rsp];" 467 "lea 1f(%%rip), %%rax;" 468 "vmwrite %%rax, %[host_rip];" 469 "vmresume;" 470 "incq (%%rsp);" 471 "1: pop %%rax;" 472 "pop %%rdi;" 473 "pop %%rsi;" 474 "pop %%rdx;" 475 "pop %%rcx;" 476 "pop %%rbp;" 477 : [ret]"=&a"(ret) 478 : [host_rsp]"r"((uint64_t)HOST_RSP), 479 [host_rip]"r"((uint64_t)HOST_RIP) 480 : "memory", "cc", "rbx", "r8", "r9", "r10", 481 "r11", "r12", "r13", "r14", "r15"); 482 return ret; 483 } 484 485 static inline void vmcall(void) 486 { 487 /* Currently, L1 destroys our GPRs during vmexits. */ 488 __asm__ __volatile__("push %%rbp; vmcall; pop %%rbp" : : : 489 "rax", "rbx", "rcx", "rdx", 490 "rsi", "rdi", "r8", "r9", "r10", "r11", "r12", 491 "r13", "r14", "r15"); 492 } 493 494 static inline int vmread(uint64_t encoding, uint64_t *value) 495 { 496 uint64_t tmp; 497 uint8_t ret; 498 499 if (enable_evmcs) 500 return evmcs_vmread(encoding, value); 501 502 __asm__ __volatile__("vmread %[encoding], %[value]; setna %[ret]" 503 : [value]"=rm"(tmp), [ret]"=rm"(ret) 504 : [encoding]"r"(encoding) 505 : "cc", "memory"); 506 507 *value = tmp; 508 return ret; 509 } 510 511 /* 512 * A wrapper around vmread that ignores errors and returns zero if the 513 * vmread instruction fails. 514 */ 515 static inline uint64_t vmreadz(uint64_t encoding) 516 { 517 uint64_t value = 0; 518 vmread(encoding, &value); 519 return value; 520 } 521 522 static inline int vmwrite(uint64_t encoding, uint64_t value) 523 { 524 uint8_t ret; 525 526 if (enable_evmcs) 527 return evmcs_vmwrite(encoding, value); 528 529 __asm__ __volatile__ ("vmwrite %[value], %[encoding]; setna %[ret]" 530 : [ret]"=rm"(ret) 531 : [value]"rm"(value), [encoding]"r"(encoding) 532 : "cc", "memory"); 533 534 return ret; 535 } 536 537 static inline uint32_t vmcs_revision(void) 538 { 539 return rdmsr(MSR_IA32_VMX_BASIC); 540 } 541 542 struct vmx_pages { 543 void *vmxon_hva; 544 uint64_t vmxon_gpa; 545 void *vmxon; 546 547 void *vmcs_hva; 548 uint64_t vmcs_gpa; 549 void *vmcs; 550 551 void *msr_hva; 552 uint64_t msr_gpa; 553 void *msr; 554 555 void *shadow_vmcs_hva; 556 uint64_t shadow_vmcs_gpa; 557 void *shadow_vmcs; 558 559 void *vmread_hva; 560 uint64_t vmread_gpa; 561 void *vmread; 562 563 void *vmwrite_hva; 564 uint64_t vmwrite_gpa; 565 void *vmwrite; 566 567 void *vp_assist_hva; 568 uint64_t vp_assist_gpa; 569 void *vp_assist; 570 571 void *enlightened_vmcs_hva; 572 uint64_t enlightened_vmcs_gpa; 573 void *enlightened_vmcs; 574 }; 575 576 struct vmx_pages *vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva); 577 bool prepare_for_vmx_operation(struct vmx_pages *vmx); 578 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp); 579 bool load_vmcs(struct vmx_pages *vmx); 580 581 #endif /* SELFTEST_KVM_VMX_H */ 582